This is information on a product in full production.
February 2013 Doc ID 17659 Rev 8 1/121
1
STM32L15xx6/8/B
Ultra-low-power 32-bit MCU ARM-based Cortex-M3,
128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC
Datasheet − production data
Features
■Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40°C to 85°C/105°C temperature range
– 0.3 µA Standby mode (3 wakeup pins)
–0.9 µA Standby mode + RTC
– 0.57 µA Stop mode (16 wakeup lines)
– 1.2 µA Stop mode + RTC
– 9 µA Low-power Run mode
– 214 µA/MHz Run mode
– 10 nA ultra-low I/O leakage
– < 8 µs wakeup time
■Core: ARM 32-bit Cortex™-M3 CPU
– From 32 kHz up to 32 MHz max
– 33.3 DMIPS peak (Dhrystone 2.1)
– Memory protection unit
■Reset and supply management
– Ultra-safe, low-power BOR (brownout
reset) with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
■Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– High Speed Internal 16 MHz factory-
trimmed RC (+/- 1%)
– Internal Low Power 37 kHz RC
– Internal multispeed low power 65 kHz to
4.2 MHz
– PLL for CPU clock and USB (48 MHz)
■Pre-programmed bootloader
– USART supported
■Development support
– Serial wire debug supported
– JTAG and trace supported
■Up to 83 fast I/Os (73 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors
■Memories
– Up to 128 KB Flash with ECC
– Up to 16 KB RAM
– Up to 4 KB of true EEPROM with ECC
– 80 Byte Backup Register
■LCD Driver for up to 8x40 segments
– Support contrast adjustment
– Support blinking mode
– Step-up converter on board
■Rich analog peripherals (down to 1.8 V)
– 12-bit ADC 1 Msps up to 24 channels
– 12-bit DAC 2 channels with output buffers
– 2x Ultra-low-power-comparators
(window mode and wake up capability)
■DMA controller 7x channels
■8x peripherals communication interface
– 1x USB 2.0 (internal 48 MHz PLL)
– 3x USART (ISO 7816, IrDA)
– 2x SPI 16 Mbits/s
– 2x I2C (SMBus/PMBus)
■10x timers: 6x 16-bit with up to 4 IC/OC/PWM
channels, 2x 16-bit basic timer, 2x watchdog
timers (independent and window)
■Up to 20 capacitive sensing channels
supporting touchkey, linear and rotary touch
sensors
■CRC calculation unit, 96-bit unique ID
Table 1. Device summary
Reference Part number
STM32L151xx
STM32L151CB, STM32L151C8, STM32L151C6,
STM32L151RB, STM32L151R8, STM32L151R6,
STM32L151VB, STM32L151V8
STM32L152xx
STM32L152CB, STM32L152C8, STM32L152C6,
STM32L152RB, STM32L152R8, STM32L152R6,
STM32L152VB, STM32L152V8
LQFP100 14 × 14 mm
LQFP64 10 × 10 mm
LQFP48 7 × 7 mm
BGA100 7 × 7 mm
BGA64 5 × 5 mm
UFQFPN48
7 × 7 mm
www.st.com
Contents STM32L151x6/8/B, STM32L152x6/8/B
2/121 Doc ID 17659 Rev 8
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 ARM® Cortex™-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 22
3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.12 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 25
3.13 Routing interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32L151x6/8/B, STM32L152x6/8/B Contents
Doc ID 17659 Rev 8 3/121
3.15.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11) 28
3.15.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 29
3.16.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.4 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 30
3.18 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 51
6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.5 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.6 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.7 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.8 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.9 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Contents STM32L151x6/8/B, STM32L152x6/8/B
4/121 Doc ID 17659 Rev 8
6.3.10 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 77
6.3.11 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.19 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.20 LCD controller (STM32L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
STM32L151x6/8/B, STM32L152x6/8/B List of tables
Doc ID 17659 Rev 8 5/121
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Ultra-low-power STM32L15xxx device features and peripheral counts . . . . . . . . . . . . . . . 10
Table 3. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14
Table 4. CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Functionalities depending on the working mode (from Run/active down to
standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. STM32L15xxx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10. Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 15. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 16. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 17. Current consumption in Run mode, code with data processing running from Flash. . . . . . 54
Table 18. Current consumption in Run mode, code with data processing running from RAM . . . . . . 55
Table 19. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 20. Current consumption in Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 21. Current consumption in Low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 22. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 23. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 61
Table 24. Typical and maximum timings in Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 25. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 26. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 27. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 28. HSE 1-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 32. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 33. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 34. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 35. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 36. Flash memory, data EEPROM endurance and data retention . . . . . . . . . . . . . . . . . . . . . . 75
Table 37. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 38. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 39. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 40. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 41. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 42. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 43. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 44. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 45. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 46. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 47. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
List of tables STM32L151x6/8/B, STM32L152x6/8/B
6/121 Doc ID 17659 Rev 8
Table 48. SCL frequency (fPCLK1= 32 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 49. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 50. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 51. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 52. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 53. ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 54. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 55. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 56. RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 57. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 58. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 59. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 60. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 61. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 62. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 104
Table 63. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 106
Table 64. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 108
Table 65. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . 110
Table 66. UFBGA100 - 7 x 7 x 0.6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . 111
Table 67. TFBGA64 - 8.0x8.0x1.2 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . 112
Table 68. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 69. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
STM32L151x6/8/B, STM32L152x6/8/B List of figures
Doc ID 17659 Rev 8 7/121
List of figures
Figure 1. Ultra-low-power STM32L15xxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. STM32L15xVx UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4. STM32L15xVx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 5. STM32L15xRx TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 6. STM32L15xRx LQFP64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 7. STM32L15xCx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 8. STM32L15xCx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 10. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 14. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 18. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 19. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 20. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 21. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 22. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 23. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 24. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 25. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 26. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 27. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 28. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 95
Figure 29. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 95
Figure 30. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 31. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 103
Figure 32. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 33. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 105
Figure 34. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 35. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 107
Figure 36. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 37. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 38. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 39. UFBGA100 - 7 x 7 x 0.6 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . 111
Figure 40. TFBGA64 - 8.0x8.0x1.2 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . 112
Figure 41. Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 113
Figure 42. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Introduction STM32L151x6/8/B, STM32L152x6/8/B
8/121 Doc ID 17659 Rev 8
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L151xx and STM32L152xx ultra-low-power ARM Cortex™-based
microcontrollers product line.
The ultra-low-power STM32L15xxx family includes devices in 3 different package types:
from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are
included, the description below gives an overview of the complete range of peripherals
proposed in this family.
These features make the ultra-low-power STM32L15xxx microcontroller family suitable for a
wide range of applications:
●Medical and handheld equipment
●Application control and user interface
●PC peripherals, gaming, GPS and sport equipment
●Alarm systems, Wired and wireless sensors, Video intercom
●Utility metering
This STM32L151xx and STM32L152xx datasheet should be read in conjunction with the
STM32L1xxxx reference manual (RM0038).
The document "Getting started with STM32L1xxx hardware development" AN3216 gives a
hardware implementation overview. The both documents are available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337g.
Figure 1 shows the general block diagram of the device family.
STM32L151x6/8/B, STM32L152x6/8/B Description
Doc ID 17659 Rev 8 9/121
2 Description
The ultra-low-power STM32L15xxx incorporates the connectivity power of the universal
serial bus (USB) with the high-performance ARM Cortex™-M3 32-bit RISC core operating at
a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories
(Flash memory up to 128 Kbytes and RAM up to 16 Kbytes) and an extensive range of
enhanced I/Os and peripherals connected to two APB buses.
All devices offer a 12-bit ADC, 2 DACs and 2 ultra-low-power comparators, six general-
purpose 16-bit timers and two basic timers, which can be used as time bases.
Moreover, the STM32L15xxx devices contain standard and advanced communication
interfaces: up to two I2Cs and SPIs, three USARTs and a USB. The STM32L15xxx devices
offer up to 20 capacitive sensing channels to simply add touch sensing functionality to any
application.
They also include a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller has a built-in LCD voltage generator that allows you to
drive up to 8 multiplexed LCDs with contrast independent of the supply voltage.
The ultra-low-power STM32L15xxx operates from a 1.8 to 3.6 V power supply (down to
1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option.
It is available in the -40 to +85 °C temperature range, extended to 105°C in low power
dissipation state. A comprehensive set of power-saving modes allows the design of low-
power applications.
Description STM32L151x6/8/B, STM32L152x6/8/B
10/121 Doc ID 17659 Rev 8
2.1 Device overview
.
Table 2. Ultra-low-power STM32L15xxx device features and peripheral counts
Peripheral STM32L15xCx STM32L15xRx STM32L15xVx
Flash (Kbytes) 32 64 128 32 64 128 64 128
Data EEPROM (Kbytes) 4
RAM (Kbytes) 10 10 16 10 10 16 10 16
Timers
General-
purpose 6
Basic 2
Communication
interfaces
SPI 2
I2C2
USART 3
USB 1
GPIOs 37 51 83
12-bit synchronized ADC
Number of channels
1
16 channels
1
20 channels
1
24 channels
12-bit DAC
Number of channels
2
2
LCD (STM32L152xx Only)
COM x SEG 4x16 4x32
8x28
4x44
8x40
Comparator 2
Capacitive sensing channels 13 20
Max. CPU frequency 32 MHz
Operating voltage 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
Operating temperatures Ambient temperatures: –40 to +85 °C
Junction temperature: –40 to + 105 °C
Packages LQFP48, UFQFPN48 LQFP64, BGA64 LQFP100, BGA100
STM32L151x6/8/B, STM32L152x6/8/B Description
Doc ID 17659 Rev 8 11/121
2.2 Ultra-low-power device continuum
The ultra-low-power STM32L151xx and STM32L152xx are fully pin-to-pin and software
compatible. Besides the full compatibility within the family, the devices are part of
STMicroelectronics microcontrollers ultra-low-power strategy which also includes
STM8L101xx and STM8L15xx devices. The STM8L and STM32L families allow a
continuum of performance, peripherals, system architecture and features.
They are all based on STMicroelectronics ultralow leakage process.
Note: The ultra-low-power STM32L and general-purpose STM32Fxxxx families are pin-to-pin
compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx
devices. Please refer to the STM32F and STM8L documentation for more information on
these devices.
2.2.1 Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
2.2.2 Shared peripherals
STM8L15xxx and STM32L15xxx share identical peripherals which ensure a very easy
migration from one family to another:
●Analog peripherals: ADC, DAC and comparators
●Digital peripherals: RTC and some communication interfaces
2.2.3 Common system strategy
To offer flexibility and optimize performance, the STM8L15xx and STM32L15xx families use
a common architecture:
●Same power supply range from 1.65 V to 3.6 V, (1.65 V at power down only for
STM8L15xx devices)
●Architecture optimized to reach ultralow consumption both in low power modes and
Run mode
●Fast startup strategy from low power modes
●Flexible system clock
●Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector.
2.2.4 Features
ST ultra-low-power continuum also lies in feature compatibility:
●More than 10 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
●Memory density ranging from 4 to 384 Kbytes
Functional overview STM32L151x6/8/B, STM32L152x6/8/B
12/121 Doc ID 17659 Rev 8
3 Functional overview
Figure 1 shows the block diagrams.
Figure 1. Ultra-low-power STM32L15xxx block diagram
1. AF = alternate function on I/O port pin.
EXT. IT
WWDG
12-bit ADC
JTAG &SW
24 A F
JT D I
JT CK/ S WCLK
JTMS /S WDAT
NJT R ST
JTDO
NRST
V
DD
=1. 65 V to 3.6 V
83A F
AH B2
US B_DP
US B_DM
MO S I,MIS O, S CK, NS S
WKU P
F
ma x
:32MHz
V
SS
S C L, SD A, SMB u s ,P MB u s
I2C 2
V
DDREF _ADC *
GP DMA
TIM2
TIM3
X T AL O S C
1-24 MHz
X T A L 32 kHz
OSC_IN
OSC_OUT
OS C32 _OUT
OS C32 _IN
PLL &
APB1 : F
ma x
=32MHz
A HBP CL K
HC L K clock
management
AP BP CL K
as AF
as AF
VOLT. R E G.
V
CO R E
PO W E R
as A F
TIM4
B u s Matrix
Int er face
RT C
RC HS
Ibus
Db us
pbus
obl
Flash
US B RAM 512 B
US ART 1
US ART 2
SP I2
7 c hannels
SC L, S D A
I2C 1 as AF
RX ,T X , CT S , RT S ,
US ART 3
Te mp s ens or
V
SS REF_ ADC *
AHB:F
max
=32 MHz
4Channels
4Channels
4Channels
FC LK
IWDG
@V DD
Supply
monitoring
@V DD A
VDDA /
VSS A
@V DD A
S m artC ard a s AF
RX ,T X , C T S, R T S,
S m ar tC ar d as AF
RX ,TX, C T S, R T S,
S m artCa r d as A F
AP B2 : F
ma x
=32 MHz
NV IC
SPI 1
MOSI ,MIS O,
SC K, NS S as AF
IF
@VD D A
PV D
Power reset
Int
AHB 2
AW U
@V DD A
RTC_OUT, RTC_TS,RTC_TAMP
System
P A [15:0 ]
P B [15:0 ]
P C [15:0 ]
PD[ 15:0]
PE[1 5:0 ]
LCD 8x4 0 (4x44 ) SEG x
COM x
IFIFIF
@V DD A
DAC_OUT1 as AF
MP U
Co mp 2
COMP2 _IN - /IN+
Co mp 1
TIM6
TIM7M
TI M9
TI M10
TI M11
2 Channe ls
1 C hannel
1 Channel
General purpose
timers
128 KB Flash
4 KB data EEPROM
LCD step-up
converter
V
LCD
=2.5 V to 3.6 V
V
LC D
BA SI C T IME RS
RTC_AFIN
VR EF O U TPU T
Ai15687h
Cortex-M3 CPU
Trace controller
ETM
RAM
16 KB
12-bit DAC1
12-bit DAC2
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
TRACECK, TRACED0, TRACED1, TRACED2, TRACED3
RC MS
RC LS
Standby interface
Backup interface
USB 2.0 FS device
BOR/V REFINT
Power-up/
Power-down
Backup
register
PH[2 :0 ] GPIOH
DAC_OUT2 as AF
AHB/APB2 AHB/APB1
STM32L151x6/8/B, STM32L152x6/8/B Functional overview
Doc ID 17659 Rev 8 13/121
3.1 Low power modes
The ultra-low-power STM32L15xxx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the internal low-drop regulator that supplies the
logic can be adjusted according to the system’s maximum operating frequency and the
external voltage supply:
●In range 1 (VDD range limited to 2.0-3.6 V), the CPU runs at up to 32 MHz (refer to
Table 17 for consumption).
●In range 2 (full VDD range), the CPU runs at up to 16 MHz (refer to Table 17 for
consumption)
●In range 3 (full VDD range), the CPU runs at up to 4 MHz (generated only with the
multispeed internal RC oscillator clock source). Refer to Table 17 for consumption.
Seven low power modes are provided to achieve the best compromise between low power
consumption, short startup time and available wakeup sources:
●Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Sleep mode power consumption: refer to Tabl e 19 .
●Low power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the
minimum clock (65 kHz), execution from SRAM or Flash memory, and internal regulator
in low power mode to minimize the regulator's operating current. In the Low power run
mode, the clock frequency and the number of enabled peripherals are both limited.
Low power run mode consumption: refer to Table 20.
●Low power sleep mode
This mode is achieved by entering the Sleep mode with the internal voltage regulator in
Low power mode to minimize the regulator’s operating current. In the Low power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
Low power sleep mode consumption: refer to Table 21.
●Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can be
the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event
or the RTC wakeup.
●Stop mode without RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Functional overview STM32L151x6/8/B, STM32L152x6/8/B
14/121 Doc ID 17659 Rev 8
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
Stop mode consumption: refer to Tab l e 22 .
●Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
●Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI,
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Standby mode consumption: refer to Table 23.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering the
Stop or Standby mode.
Table 3. Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply range
Operating power
supply range
DAC and ADC
operation USB Dynamic voltage
scaling range I/O operation
VDD = 1.65 to 1.8 V Not functional Not functional Range 2 or
range 3
Degraded speed
performance
VDD = 1.8 to 2.0 V Conversion time
up to 500 Ksps Not functional Range 2 or
range 3
Degraded speed
performance
VDD = 2.0 to 2.4 V Conversion time
up to 500 Ksps Functional(1)
1. Should be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V.
Range 1, range 2
or range 3 Full speed operation
VDD = 2.4 to 3.6 V Conversion time
up to 1 Msps Functional(1) Range 1, range 2
or range 3 Full speed operation
STM32L151x6/8/B, STM32L152x6/8/B Functional overview
Doc ID 17659 Rev 8 15/121
Table 4. CPU frequency range depending on dynamic voltage scaling
CPU frequency range Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws) Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws) Range 2
2.1 MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws) Range 3
Functional overview STM32L151x6/8/B, STM32L152x6/8/B
16/121 Doc ID 17659 Rev 8
Table 5. Functionalities depending on the working mode (from Run/active down to
standby)
Ips Run/Active Sleep
Low-
power
Run
Low-
power
Sleep
Stop Standby
Wakeup
capability
Wakeup
capability
CPU Y -- Y -- -- --
Flash Y Y Y N -- --
RAM Y Y Y Y Y --
Backup Registers Y Y Y Y Y Y
EEPROM Y -- Y Y Y --
Brown-out rest
(BOR) YYYYYYY
DMA Y Y Y Y -- --
Programable
Voltage Detector
(PVD)
YYYYYYY
Power On Reset
(POR) YYYYYYY
Power Down Rest
(PDR) YYYYY Y
High Speed
Internal (HSI) Y Y -- -- -- --
High Speed
External (HSE) Y Y -- -- -- --
Low Speed Internal
(LSI) YYYYY --
Low Speed
External (LSE) YYYYY --
Multi-Speed
Internal (MSI) Y Y Y Y -- --
Inter-Connect
Controler Y Y Y Y -- --
RTC Y Y Y Y Y Y Y
RTC Tamper Y Y Y Y Y Y Y Y
Auto WakeUp
(AWU) YYYYYYYY
LCD Y Y Y Y Y --
USB Y Y -- -- -- Y --
USART Y Y Y Y Y (1) --
SPI Y Y Y Y --
I2C Y Y Y Y (1) --
STM32L151x6/8/B, STM32L152x6/8/B Functional overview
Doc ID 17659 Rev 8 17/121
3.2 ARM® Cortex™-M3 core with MPU
The ARM Cortex™-M3 processor is the industry leading processor for embedded systems.
It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L15xxx is compatible with all ARM tools and
software.
ADC Y Y -- -- -- --
DAC Y Y Y Y Y --
Tempsensor Y Y Y Y Y --
Comparators Y Y Y Y Y Y --
16-bit and 32-bit
Timers Y Y Y Y -- --
IWDG Y Y Y Y Y Y Y Y
WWDG Y Y Y Y -- --
Touch sensing Y -- -- -- -- --
Systic Timer Y Y Y Y --
GPIOs Y Y Y Y Y Y 3Pins
Wakeup time to
Run mode 0 µs 0.36 µs 3 µs 32 µs < 8 µs 50 µs
Consumption
VDD=1.8V to 3.6V
(Typ)
Do wn t o
214 µA/MHz
(from Flash)
D o w n t o
50 µA/MHz
(from Flash)
Down to
9 µA
Down to
4.4 µA
0.65 µA (No
RTC) VDD=1.8V
0.3 µA (No RTC)
VDD=1.8V
1.4 µA (with
RTC) VDD=1.8V
1 µA (with RTC)
VDD=1.8V
0.65 µA (No
RTC) VDD=3.0V
0.3 µA (No RTC)
VDD=3.0V
1.6 µA (with
RTC) VDD=3.0V
1.3 µA (with
RTC) VDD=3.0V
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.
Table 5. Functionalities depending on the working mode (from Run/active down to
standby) (continued)
Ips Run/Active Sleep
Low-
power
Run
Low-
power
Sleep
Stop Standby
Wakeup
capability
Wakeup
capability
Functional overview STM32L151x6/8/B, STM32L152x6/8/B
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Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L15xxx embeds a nested vectored interrupt controller able to
handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of
Cortex™-M3) and 16 priority levels.
●Closely coupled NVIC gives low-latency interrupt processing
●Interrupt entry vector table address passed directly to the core
●Closely coupled NVIC core interface
●Allows early processing of interrupts
●Processing of late arriving, higher-priority interrupts
●Support for tail-chaining
●Processor state automatically saved
●Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3 Reset and supply management
3.3.1 Power supply schemes
●VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
●VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
3.3.2 Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
●The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
●The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.
STM32L151x6/8/B, STM32L152x6/8/B Functional overview
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Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3 Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●MR is used in Run mode (nominal regulation)
●LPR is used in the Low-power run, Low-power sleep and Stop modes
●Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost are lost except for the standby circuitry (wakeup logic,
IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR).
3.3.4 Boot modes
At startup, boot pins are used to select one of three boot options:
●Boot from Flash memory
●Boot from System Memory
●Boot from embedded RAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1 or USART2. See STM32™ microcontroller system memory boot mode
AN2606 for details.
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20/121 Doc ID 17659 Rev 8
3.4 Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low power modes and ensures clock
robustness. It features:
●Clock prescaler: to get the best tradeoff between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
●Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
●Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
●Master clock source: three different clock sources can be used to drive the master
clock:
– 1-24 MHz high-speed external crystal (HSE), that can supply a PLL
– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz)
with a consumption proportional to speed, down to 750 nA typical. When a
32.768 kHz clock source is available in the system (LSE), the MSI frequency can
be trimmed by software down to a ±0.5% accuracy.
●Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:
– 32.768 kHz low-speed external crystal (LSE)
– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
●RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
●USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
●Startup clock: after reset, the microcontroller restarts by default with an internal
2.1 MHz clock (MSI). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
●Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
●Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 32 MHz. See Figure 2 for details on the clock tree.
STM32L151x6/8/B, STM32L152x6/8/B Functional overview
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Figure 2. Clock tree
2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
24 MHz or 32 MHz.
AHB
Prescaler
/1, 2..512
APB1
Prescaler
/1, 2, 4, 8, 16
PCLK1
HCLK
to AHB bus, core,
memory and DMA
peripherals
to APB1
Peripheral Clock
Enable
Enable
Peripheral Clock
APB2
Prescaler
/1, 2, 4, 8, 16
PCLK2
to TIM9, 10, and 11
peripherals to APB2
Peripheral Clock
Enable
Enable
Peripheral Clock
32 MHz max
32 MHz max
to Cortex System timer
/8
Clock
Enable
SYSCLK
TIMxCLK
TIMxCLK
FCLK Cortex
free running clock
to TIM2,3,4,6 and 7
If (APB1 prescaler =1) x1
else x2
If (APB2 prescaler =1) x1
else x2
32 MHz max
HSE OSC
1-24 MHz
OSC_IN
OSC_OUT
HSI RC
16 MHz
x3,x4,x6,x8
x12,x16,x24
PLLMUL
PLLCLK
HSI
HSI
HSE
PLLSRC SW
CSS
x32,x48
/2,/3,/4
48 MHz
USBCLK
to USB interface
PLLDIV
to ADC
Peripheral clock
enable
ADCCLK
MHz max
32
OSC32_IN
OSC32_OUT
LSE OSC
32.768 kHz
LSI RC
37 kHz
to Independent Watchdog (IWDG)
MCO
PLLCLK
HSI
HSE
LSE
LSI
/2,4,
8,16
to RTC
MCOSEL
RTCCLK
RTCSEL[1:0]
IWDGCLK
SYSCLK
/1,2,4,
8,16
MSI
LSE
LSI
to LCD
to
Timer 9, 10, 11 ETR
HSE = High-speed external clock signal
LSE = Low -speed external clock signal
LSI = Low-speed internal clock signal
HSI = High-speed internal clock signal
Legend :
ai17212c
MS I = Multispeed internal clock signal
PLLVCO/2
MSI RC
MSI
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3.5 Low power real-time clock and backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded
decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made
automatically. The RTC provides a programmable alarm and programmable periodic
interrupts with wakeup from Stop and Standby modes.
●The programmable wakeup time ranges from 120 µs to 36 hours
●Stop mode consumption with LSI and Auto-wakeup: 1.2 µA (at 1.8 V) and 1.4 µA (at
3.0 V)
●Stop mode consumption with LSE, calendar and Auto-wakeup: 1.3 µA (at 1.8V), 1.6 µA
(at 3.0 V)
The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.
There are twenty 32-bit backup registers provided to store 80 bytes of user application data.
They are cleared in case of tamper detection.
3.6 GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high current capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected
to the 16 external interrupt lines. The 7 other lines are connected to RTC, PVD, USB or
Comparator events.
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3.7 Memories
The STM32L15xxx devices have the following features:
●Up to 16 Kbyte of embedded RAM accessed (read/write) at CPU clock speed with 0
wait states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
●The non-volatile memory is divided into three arrays:
– 32, 64 or 128 Kbyte of embedded Flash program memory
– 4 Kbyte of data EEPROM
– Options bytes
The options bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
– Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire)
and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.8 DMA (direct memory access)
The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers
and ADC.
3.9 LCD (liquid crystal display)
The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
●Internal step-up converter to guarantee functionality and contrast control irrespective of
VDD. This converter can be deactivated, in which case the VLCD pin is used to provide
the voltage to the LCD
●Supports static, 1/2, 1/3, 1/4 and 1/8 duty
●Supports static, 1/2, 1/3 and 1/4 bias
●Phase inversion to reduce power consumption and EMI
●Up to 8 pixels can be programmed to blink
●Unneeded segments and common pins can be used as general I/O pins
●LCD RAM can be updated at any time owing to a double-buffer
●The LCD controller can operate in Stop mode
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3.10 ADC (analog-to-digital converter)
A 12-bit analog-to-digital converters is embedded into STM32L15xxx devices with up to 24
external channels, performing conversions in single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start trigger and injection trigger, to allow the application to synchronize A/D
conversions and timers. An injection mode allows high priority conversions to be done by
interrupting a scan mode which runs in as a background task.
The ADC includes a specific low power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.
3.10.1 Temperature sensor
The temperature sensor (TSENSE) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy
of the temperature measurement. As the offset of the temperature sensor varies from chip
to chip due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 6. Temperature sensor calibration values
Calibration value name Description Memory address
TSENSE_CAL1
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3 V
0x1FF8 007A-0x1FF8 007B
TSENSE_CAL2
TS ADC raw data acquired at
temperature of 110 °C
VDDA= 3 V
0x1FF8 007E-0x1FF8 007F
STM32L151x6/8/B, STM32L152x6/8/B Functional overview
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3.10.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the VDD value (when no external voltage, VREF+, is
available for ADC). The precise voltage of VREFINT is individually measured for each part by
ST during production test and stored in the system memory area. It is accessible in read-
only mode.
3.11 DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
This dual digital Interface supports the following features:
●two DAC converters: one for each output channel
●left or right data alignment in 12-bit mode
●synchronized update capability
●noise-wave generation
●triangular-wave generation
●dual DAC channels’ independent or simultaneous conversions
●DMA capability for each channel (including the underrun interrupt)
●external triggers for conversion
●input reference voltage VREF+
Eight DAC trigger inputs are used in the STM32L15xxx. The DAC channels are triggered
through the timer update outputs that are also connected to different DMA channels.
3.12 Ultra-low-power comparators and reference voltage
The STM32L15xxx embeds two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).
●one comparator with fixed threshold
●one comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of
the following:
– DAC output
– External I/O
– Internal reference voltage (VREFINT) or VREFINT submultiple (1/4, 1/2, 3/4)
Table 7. Internal voltage reference measured values
Calibration value name Description Memory address
VREFINT_CAL
Raw data acquired at
temperature of 30 °C
VDDA= 3 V
0x1FF8 0078-0x1FF8 0079
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Both comparators can wake up from Stop mode, and be combined into a window
comparator.
The internal reference voltage is available externally via a low power / low current output
buffer (driving current capability of 1 µA typical).
3.13 Routing interface
This interface controls the internal routing of I/Os to TIM2, TIM3, TIM4 and to the
comparator and reference voltage output.
3.14 Touch sensing
The STM32L15xxx devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 20 capacitive sensing channels
distributed over 10 analog I/O groups. Only software capacitive sensing acquisition mode is
supported.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. The capacitive sensing acquisition only requires few external components to
operate.
Reliable touch sensing functionality can be quickly and easily implemented using the free
STM32L1xx STMTouch touch sensing firmware library.
3.15 Timers and watchdogs
The ultra-low-power STM32L15xxx devices include six general-purpose timers, two basic
timers and two watchdog timers.
Ta bl e 8 compares the features of the general-purpose and basic timers.
Table 8. Timer feature comparison
Timer Counter
resolution
Counter
type
Prescaler
factor
DMA request
generation
Capture/compare
channels
Complementary
outputs
TIM2,
TIM3,
TIM4
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Ye s 4 N o
TIM9 16-bit Up
Any integer
between 1
and 65536
No 2 No
STM32L151x6/8/B, STM32L152x6/8/B Functional overview
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TIM10,
TIM11 16-bit Up
Any integer
between 1
and 65536
No 1 No
TIM6,
TIM7 16-bit Up
Any integer
between 1
and 65536
Ye s 0 N o
Table 8. Timer feature comparison
Timer Counter
resolution
Counter
type
Prescaler
factor
DMA request
generation
Capture/compare
channels
Complementary
outputs
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28/121 Doc ID 17659 Rev 8
3.15.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11)
There are six synchronizable general-purpose timers embedded in the STM32L15xxx
devices (see Ta b l e 8 for differences).
TIM2, TIM3, TIM4
These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.
They feature 4 independent channels each for input capture/output compare, PWM or one-
pulse mode output. This gives up to 12 input captures/output compares/PWMs on the
largest packages.
The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM10, TIM11
and TIM9 general-purpose timers via the Timer Link feature for synchronization or event
chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers
can be used to generate PWM outputs.
TIM2, TIM3, TIM4 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
TIM10, TIM11 and TIM9
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and
TIM11 feature one independent channel, whereas TIM9 has two independent channels for
input capture/output compare, PWM or one-pulse mode output. They can be synchronized
with the TIM2, TIM3, TIM4 full-featured general-purpose timers.
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
3.15.2 Basic timers (TIM6 and TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
3.15.3 SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.
3.15.4 Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
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3.15.5 Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.16 Communication interfaces
3.16.1 I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
3.16.2 Universal synchronous/asynchronous receiver transmitter (USART)
All USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They provide
hardware management of the CTS and RTS signals. They support IrDA SIR ENDEC, are
ISO 7816 compliant and have LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
3.16.3 Serial peripheral interface (SPI)
Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
3.16.4 Universal serial bus (USB)
The STM32L15xxx embeds a USB device peripheral compatible with the USB full speed
12 Mbit/s. The USB interface implements a full speed (12 Mbit/s) function interface. It has
software-configurable endpoint setting and supports suspend/resume. The dedicated
48 MHz clock is generated from the internal main PLL (the clock source must use a HSE
crystal oscillator).
Functional overview STM32L151x6/8/B, STM32L152x6/8/B
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3.17 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.18 Development support
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a
specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.
The JTAG port can be permanently disabled with a JTAG fuse.
Embedded Trace Macrocell™
The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L15xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer running debugger software. TPA
hardware is commercially available from common development tool vendors. It operates
with third party debugger software tools.
STM32L151x6/8/B, STM32L152x6/8/B Pin descriptions
Doc ID 17659 Rev 8 31/121
4 Pin descriptions
Figure 3. STM32L15xVx UFBGA100 ballout
1. This figure shows the package top view.
ai17096e
A
B
E
D
C
F
G
H
J
K
L
M
PE3
OSC_IN
PC15
OSC32_OUT
PC14
PC13
WKUP2
PE4
OSC_OUT
PC0
VSSA
VREF-
VREF+
VDDA
PE1
PE5
PE2
PE6
WUKP3
VLCD
VSS_5
VDD_5
NRST
PC1
PC3
PA 0
WKUP1
PA 1
PB8
PE0
PB9
VSS_3
VSS_4
VDD_4
PC2
PA 2
PA 3
PA 4
BOOT0
PB7
VDD_3
PA 5
PA 6
PA 7
PD7
PB6
PB5
PC4
PC5
PB0
PD5
PD6
PB2
PB1
PB4
PD4
PE8
PE7
PB3
PD3
PD2
PD9
PE10
PE9
PA15
PD1
PD0
PD8
PE12
PE11
PA14
PC12
PC11
PC8
PA 9
PD15
PD12
PB15
PB10
PE13
PA 1 3
PC10
PH2
PA 8
PC7
PD14
PD11
PB14
PB11
PE14
VSS_2
VDD_2
PA12
PA11
PA10
PC9
PC6
PD13
PD10
PB13
PB12
PE15
VSS_1
VDD_1
2 3 4 5 6 7 8 9 10 11 12
1
PH0
PH1
OSC32_IN
Pin descriptions STM32L151x6/8/B, STM32L152x6/8/B
32/121 Doc ID 17659 Rev 8
Figure 4. STM32L15xVx LQFP100 pinout
1. This figure shows the package top view.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
PH2
PA13
PA12
PA11
PA10
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA 3
VSS_4
VDD_4
PA 4
PA 5
PA 6
PA 7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PE2
PE3
PE4
PE5
PE6-WKUP3
VLCD
PC13-WKUP2
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA 0 - W K U P1
PA1
PA2
ai15692c
LQFP100
PA8
PA9
STM32L151x6/8/B, STM32L152x6/8/B Pin descriptions
Doc ID 17659 Rev 8 33/121
Figure 5. STM32L15xRx TFBGA64 ballout
1. This figure shows the package top view.
AI16090c
PB2
PC14-
OSC32_IN
PA7PA4
PA2
PA15
PB11
PB1PA6PA3
H
PB10
PC5PC4
D PA8
PA9
BOOT0PB8
C
PC9
PA11
PB6
PC12
VDDA
PB9
BPA12
PC10
PC15-
OSC32_OUT
PB3
PD2
A
87654321
VSS_4
OSC_IN
OSC_OUT VDD_4
G
F
E
PC2
VREF+
PC13-
WKUP2 PB4 PA13PA14
PB7 PB5
VSS_3
PC7 PC8PC0NRST PC1
PB0PA5 PB14
VDD_2
VDD_3
PB13
VLCD PC11
PA10
VSS_2 VSS_1
PC6VSSA
PA1
VDD_1
PB15
PB12
PA0-WKUP1
PH0-
PH1-
Pin descriptions STM32L151x6/8/B, STM32L152x6/8/B
34/121 Doc ID 17659 Rev 8
Figure 6. STM32L15xRx LQFP64 pinout
1. This figure shows the package top view.
Figure 7. STM32L15xCx LQFP48 pinout
1. This figure shows the package top view.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VLCD
PC13-WKUP2
PC14-OSC32_IN
PC15-OSC32_OUT
PH0 -OSC_IN
PH1- OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA 0 - W K U P1
PA1
PA2
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA 1 5
PA 1 4
VDD_2
VSS_2
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
LQFP64
ai15693c
STM32L151x6/8/B, STM32L152x6/8/B Pin descriptions
Doc ID 17659 Rev 8 35/121
Figure 8. STM32L15xCx UFQFPN48 pinout
1. This figure shows the package top view.
VSS_3
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
48 47 46 45 44 43 42 41 40
136 VDD_2
235 VSS_2
334 PA13
4
UFQFPN48
33 PA12
VSSA
532 PA11
VDDA
631 PA10
PA0-WKUP1
730 PA9
PA1
829 PA8
PA2
928
VDD_1
13 14 15 16 17 18 19 20 21
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
VSS_1
ai15695d
10
11
12
27
26
25
22 23 24
39 38 37
PB10
PB11
PB15
PB14
PB13
PB12
VLCD
PC13-WKUP2
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
PB9
PB8
VDD_3
Pin descriptions STM32L151x6/8/B, STM32L152x6/8/B
36/121 Doc ID 17659 Rev 8
Table 9. STM32L15xxx pin definitions
Pins
Pin name
Type(1)
I/O Level(2)
Main
function(3)
(after reset)
Alternate functions
LQFP100
LQFP64
TFBGA64
UFBGA100
LQFP48 or UFQFPN48
1 - B2 - PE2 I/O FT PE2 TRACECLK/LCD_SEG38/TIM3_ETR
2 - A1 - PE3 I/O FT PE3 TRACED0/LCD_SEG39/TIM3_CH1
3 - B1 - PE4 I/O FT PE4 TRACED1/TIM3_CH2
4 - C2 - PE5 I/O FT PE5 TRACED2/TIM9_CH1
5 - D2 - PE6-WKUP3 I/O FT PE6 TRACED3/WKUP3/TIM9_CH2
6 1 B2 E2 1 VLCD(4) SV
LCD
7 2 A2 C1 2 PC13-WKUP2 I/O FT PC13 RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2
83A1D13 PC14-
OSC32_IN(5) I/O PC14 OSC32_IN
9 4 B1 E1 4
PC15-
OSC32_OUT
(5)
I/O PC15 OSC32_OUT
10 - - F2 - VSS_5 SV
SS_5
11 - - G2 - VDD_5 SV
DD_5
12 5 C1 F1 5 PH0-
OSC_IN(6) I PH0 OSC_IN
13 6 D1 G1 6 PH1-
OSC_OUT O PH1 OSC_OUT
14 7 E1 H2 7 NRST I/O NRST
15 8 E3 H1 - PC0 I/O FT PC0 ADC_IN10/LCD_SEG18/COMP1_INP
16 9 E2 J2 - PC1 I/O FT PC1 ADC_IN11/LCD_SEG19/COMP1_INP
17 10 F2 J3 - PC2 I/O FT PC2 ADC_IN12/LCD_SEG20/COMP1_INP
18 11 -(7) K2 - PC3 I/O PC3 ADC_IN13/LCD_SEG21/COMP1_INP
19 12 F1 J1 8 VSSA SV
SSA
20 - - K1 - VREF- SV
REF-
21 - G1
(7) L1 - VREF+ SV
REF+
22 13 H1 M1 9 VDDA SV
DDA
23 14 G2 L2 10 PA0-WKUP1 I/O FT PA0 WKUP1/USART2_CTS/ADC_IN0/TIM2_CH1_ETR/
COMP1_INP
24 15 H2 M2 11 PA1 I/O FT PA1 USART2_RTS/ADC_IN1/TIM2_CH2/LCD_SEG0/
COMP1_INP
STM32L151x6/8/B, STM32L152x6/8/B Pin descriptions
Doc ID 17659 Rev 8 37/121
25 16 F3 K3 12 PA2 I/O FT PA2 USART2_TX/ADC_IN2/TIM2_CH3/TIM9_CH1/
LCD_SEG1/COMP1_INP
26 17 G3 L3 13 PA3 I/O PA3 USART2_RX/ADC_IN3/TIM2_CH4/TIM9_CH2/
LCD_SEG2/COMP1_INP
27 18 C2 E3 - VSS_4 SV
SS_4
28 19 D2 H3 - VDD_4 SV
DD_4
29 20 H3 M3 14 PA4 I/O PA4 SPI1_NSS/USART2_CK/
ADC_IN4/DAC_OUT1/COMP1_INP
30 21 F4 K4 15 PA5 I/O PA5 SPI1_SCK/ADC_IN5/
DAC_OUT2/TIM2_CH1_ETR/COMP1_INP
31 22 G4 L4 16 PA6 I/O FT PA6 SPI1_MISO/ADC_IN6/TIM3_CH1/
LCD_SEG3/TIM10_CH1/COMP1_INP
32 23 H4 M4 17 PA7 I/O FT PA7 SPI1_MOSI/ADC_IN7/TIM3_CH2/
LCD_SEG4/TIM11_CH1/COMP1_INP
33 24 H5 K5 - PC4 I/O FT PC4 ADC_IN14/LCD_SEG22/COMP1_INP
34 25 H6 L5 - PC5 I/O FT PC5 ADC_IN15/LCD_SEG23/COMP1_INP
35 26 F5 M5 18 PB0 I/O PB0 ADC_IN8/TIM3_CH3/LCD_SEG5/
COMP1_INP/VREF_OUT
36 27 G5 M6 19 PB1 I/O FT PB1 ADC_IN9/TIM3_CH4/LCD_SEG6/
COMP1_INP/VREF_OUT
37 28 G6 L6 20 PB2 I/O FT PB2/BOOT1
38 - - M7 - PE7 I/O PE7 ADC_IN22/COMP1_INP
39 - - L7 - PE8 I/O PE8 ADC_IN23/COMP1_INP
40 - - M8 - PE9 I/O PE9 ADC_IN24/TIM2_CH1_ETR/COMP1_INP
41 - - L8 - PE10 I/O PE10 ADC_IN25/TIM2_CH2/COMP1_INP
42 - - M9 - PE11 I/O FT PE11 TIM2_CH3
43 - - L9 - PE12 I/O FT PE12 TIM2_CH4/SPI1_NSS
44 - - M10 - PE13 I/O FT PE13 SPI1_SCK
45 - - M11 - PE14 I/O FT PE14 SPI1_MISO
46 - - M12 - PE15 I/O FT PE15 SPI1_MOSI
47 29 G7 L10 21 PB10 I/O FT PB10 I2C2_SCL/USART3_TX/TIM2_CH3/LCD_SEG10
48 30 H7 L11 22 PB11 I/O FT PB11 I2C2_SDA/USART3_RX/TIM2_CH4/LCD_SEG11
Table 9. STM32L15xxx pin definitions (continued)
Pins
Pin name
Type(1)
I/O Level(2)
Main
function(3)
(after reset)
Alternate functions
LQFP100
LQFP64
TFBGA64
UFBGA100
LQFP48 or UFQFPN48
Pin descriptions STM32L151x6/8/B, STM32L152x6/8/B
38/121 Doc ID 17659 Rev 8
49 31 D6 F12 23 VSS_1 SV
SS_1
50 32 E6 G12 24 VDD_1 SV
DD_1
51 33 H8 L12 25 PB12 I/O FT PB12 SPI2_NSS/I2C2_SMBA/USART3_CK/LCD_SEG12/
ADC_IN18/COMP1_INP/TIM10_CH1
52 34 G8 K12 26 PB13 I/O FT PB13 SPI2_SCK/USART3_CTS/LCD_SEG13/ADC_IN19/
COMP1_INP/TIM9_CH1
53 35 F8 K11 27 PB14 I/O FT PB14 SPI2_MISO/USART3_RTS/LCD_SEG14/ADC_IN20/
COMP1_INP/TIM9_CH2
54 36 F7 K10 28 PB15 I/O FT PB15 SPI2_MOSI/LCD_SEG15/ADC_IN21/
COMP1_INP/TIM11_CH1/RTC_REFIN
55 - - K9 - PD8 I/O FT PD8 USART3_TX/LCD_SEG28
56 - - K8 - PD9 I/O FT PD9 USART3_RX/LCD_SEG29
57 - - J12 - PD10 I/O FT PD10 USART3_CK/LCD_SEG30
58 - - J11 - PD11 I/O FT PD11 USART3_CTS/LCD_SEG31
59 - - J10 - PD12 I/O FT PD12 TIM4_CH1/USART3_RTS/LCD_SEG32
60 - - H12 - PD13 I/O FT PD13 TIM4_CH2/LCD_SEG33
61 - - H11 - PD14 I/O FT PD14 TIM4_CH3/LCD_SEG34
62 - - H10 - PD15 I/O FT PD15 TIM4_CH4/LCD_SEG35
63 37 F6 E12 - PC6 I/O FT PC6 TIM3_CH1/LCD_SEG24
64 38 E7 E11 PC7 I/O FT PC7 TIM3_CH2/LCD_SEG25
65 39 E8 E10 PC8 I/O FT PC8 TIM3_CH3/LCD_SEG26
66 40 D8 D12 - PC9 I/O FT PC9 TIM3_CH4/LCD_SEG27
67 41 D7 D11 29 PA8 I/O FT PA8 USART1_CK/MCO/LCD_COM0
68 42 C7 D10 30 PA9 I/O FT PA9 USART1_TX/LCD_COM1
69 43 C6 C12 31 PA10 I/O FT PA10 USART1_RX/LCD_COM2
70 44 C8 B12 32 PA11 I/O FT PA11 USART1_CTS/USB_DM/SPI1_MISO
71 45 B8 A12 33 PA12 I/O FT PA12 USART1_RTS/USB_DP/SPI1_MOSI
72 46 A8 A11 34 PA13 I/O FT JTMS/
SWDAT
73 - - C11 - PH2 I/O FT PH2
74 47 D5 F11 35 VSS_2 SV
SS_2
Table 9. STM32L15xxx pin definitions (continued)
Pins
Pin name
Type(1)
I/O Level(2)
Main
function(3)
(after reset)
Alternate functions
LQFP100
LQFP64
TFBGA64
UFBGA100
LQFP48 or UFQFPN48
STM32L151x6/8/B, STM32L152x6/8/B Pin descriptions
Doc ID 17659 Rev 8 39/121
75 48 E5 G11 36 VDD_2 SV
DD_2
76 49 A7 A10 37 PA14 I/O FT JTCK
/SWCLK
77 50 A6 A9 38 PA15 I/O FT JTDI TIM2_CH1_ETR/PA15/SPI1_NSS/LCD_SEG17
78 51 B7 B11 - PC10 I/O FT PC10 USART3_TX/LCD_SEG28/LCD_SEG40/
LCD_COM4
79 52 B6 C10 - PC11 I/O FT PC11 USART3_RX/LCD_SEG29/LCD_SEG41/
LCD_COM5
80 53 C5 B10 - PC12 I/O FT PC12 USART3_CK/LCD_SEG30/LCD_SEG42/
LCD_COM6
81 - - C9 - PD0 I/O FT PD0 SPI2_NSS/TIM9_CH1
82 - - B9 - PD1 I/O FT PD1 SPI2_SCK
83 54 B5 C8 PD2 I/O FT PD2 TIM3_ETR/LCD_SEG31/LCD_SEG43/LCD_COM7
84 - - B8 - PD3 I/O FT PD3 USART2_CTS/SPI2_MISO
85 - - B7 - PD4 I/O FT PD4 USART2_RTS/SPI2_MOSI
86 - - A6 - PD5 I/O FT PD5 USART2_TX
87 - - B6 - PD6 I/O FT PD6 USART2_RX
88 - - A5 - PD7 I/O FT PD7 USART2_CK/TIM9_CH2
89 55 A5 A8 39 PB3 I/O FT JTDO TIM2_CH2/PB3/SPI1_SCK/COMP2_INM/
LCD_SEG7
90 56 A4 A7 40 PB4 I/O FT NJTRST TIM3_CH1/PB4/
SPI1_MISO/COMP2_INP/LCD_SEG8
91 57 C4 C5 41 PB5 I/O FT PB5 I2C1_SMBA/TIM3_CH2/SPI1_MOSI/COMP2_INP/
LCD_SEG9
92 58 D3 B5 42 PB6 I/O FT PB6 I2C1_SCL/TIM4_CH1/USART1_TX
93 59 C3 B4 43 PB7 I/O FT PB7 I2C1_SDA/TIM4_CH2/
USART1_RX/PVD_IN
94 60 B4 A4 44 BOOT0 I BOOT0
95 61 B3 A3 45 PB8 I/O FT PB8 TIM4_CH3/I2C1_SCL/LCD_SEG16/TIM10_CH1
96 62 A3 B3 46 PB9 I/O FT PB9 TIM4_CH4/I2C1_SDA/LCD_COM3/TIM11_CH1
97 - - C3 - PE0 I/O FT PE0 TIM4_ETR/LCD_SEG36/TIM10_CH1
98 - - A2 - PE1 I/O FT PE1 LCD_SEG37/TIM11_CH1
Table 9. STM32L15xxx pin definitions (continued)
Pins
Pin name
Type(1)
I/O Level(2)
Main
function(3)
(after reset)
Alternate functions
LQFP100
LQFP64
TFBGA64
UFBGA100
LQFP48 or UFQFPN48
Pin descriptions STM32L151x6/8/B, STM32L152x6/8/B
40/121 Doc ID 17659 Rev 8
99 63 D4 D3 47 VSS_3 SV
SS_3
100 64 E4 C4 48 VDD_3 SV
DD_3
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to Table 2 on page 10.
4. Applicable to STM32L152xx devices only. In STM32L151xx devices, this pin should be connected to VDD.
5. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is on (by setting the
LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose
PC14/PC15 I/Os, respectively, when the LSE oscillator is off ( after reset, the LSE oscillator is off ). The LSE has priority
over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
section in the STM32L15xxx reference manual (RM0038).
6. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is on ( by setting the HSEON
bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,
respectively, when the HSE oscillator is off (after reset, the HSE oscillator is off ). The HSE has priority over the GPIO
function.
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.
Table 9. STM32L15xxx pin definitions (continued)
Pins
Pin name
Type(1)
I/O Level(2)
Main
function(3)
(after reset)
Alternate functions
LQFP100
LQFP64
TFBGA64
UFBGA100
LQFP48 or UFQFPN48
STM32L151x6/8/B, STM32L152x6/8/B Pin descriptions
Doc ID 17659 Rev 8 41/121
Table 10. Alternate function input/output
Port
name
Digital alternate function number
AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15
Alternate function
SYSTEM TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART
1/2/3 N/A N/A USB LCD N/A N/A RI SYSTEM
BOOT0 BOOT0
NRST NRST
PA0-WKUP1 WKUP1 TIM2_CH1_
ETR
USART2_
CTS TIMx_IC1 EVENTOUT
PA1 TIM2_CH2 USART2_
RTS [SEG0] TIMx_IC2 EVENTOUT
PA2 TIM2_CH3 TIM9_CH1 USART2_
TX [SEG1] TIMx_IC3 EVENTOUT
PA3 TIM2_CH4 TIM9_CH2 USART2_
RX [SEG2] TIMx_IC4 EVENTOUT
PA4 SPI1_NSS USART2_
CK TIMx_IC1 EVENTOUT
PA5 TIM2_CH1_
ETR SPI1_SCK TIMx_IC2 EVENTOUT
PA6 TIM3_CH1 TIM10_CH1 SPI1_MISO [SEG3] TIMx_IC3 EVENTOUT
PA7 TIM3_CH2 TIM11_CH1 SPI1_MOSI [SEG4] TIMx_IC4 EVENTOUT
PA8 MC O USART1_
CK [COM0] TIMx_IC1 EVENTOUT
PA9 USART1_
TX [COM1] TIMx_IC2 EVENTOUT
PA10 USART1_
RX [COM2] TIMx_IC3 EVENTOUT
PA11 SPI1_MISO USART1_
CTS DM TIMx_IC4 EVENTOUT
PA12 SPI1_MOSI USART1_
RTS DP TIMx_IC1 EVENTOUT
PA13 JTMS-SWDAT TIMx_IC2 EVENTOUT
PA14 JTCK-SWCLK TIMx_IC3 EVENTOUT
Pin descriptions STM32L151x6/8/B, STM32L152x6/8/B
42/121 Doc ID 17659 Rev 8
PA15 JTDI TIM2_CH1_
ETR SPI1_NSS SEG17 TIMx_IC4 EVENTOUT
PB0 TIM3_CH3 [SEG5] EVENTOUT
PB1 TIM3_CH4 [SEG6] EVENTOUT
PB2 BOOT1 EVENTOUT
PB3 JTDO TIM2_CH2 SPI1_SCK [SEG7] EVENTOUT
PB4 JTRST TIM3_CH1 SPI1_MISO [SEG8] EVENTOUT
PB5 TIM3_CH2 I2C1_
SMBA SPI1_MOSI [SEG9] EVENTOUT
PB6 TIM4_CH1 I2C1_SCL USART1_
TX EVENTOUT
PB7 TIM4_CH2 I2C1_SDA USART1_
RX EVENTOUT
PB8 TIM4_CH3 TIM10_CH1* I2C1_SCL SEG16 EVENTOUT
PB9 TIM4_CH4 TIM11_CH1* I2C1_SDA [COM3] EVENTOUT
PB10 TIM2_CH3 I2C2_SCL
USART3_
TX SEG10 EVENTOUT
PB11 TIM2_CH4 I2C2_SDA
USART3_
RX SEG11 EVENTOUT
PB12 TIM10_CH1 I2C2_
SMBA SPI2_NSS USART3_
CK SEG12 EVENTOUT
PB13 TIM9_CH1 SPI2_SCK
USART3_
CTS SEG13 EVENTOUT
PB14 TIM9_CH2 SPI2_MISO
USART3_
RTS SEG14 EVENTOUT
PB15 RTC_REFIN TIM11_CH1 SPI2_MOSI SEG15 EVENTOUT
PC0 SEG18 TIMx_IC1 EVENTOUT
PC1 SEG19 TIMx_IC2 EVENTOUT
Table 10. Alternate function input/output (continued)
Port
name
Digital alternate function number
AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15
Alternate function
SYSTEM TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART
1/2/3 N/A N/A USB LCD N/A N/A RI SYSTEM
STM32L151x6/8/B, STM32L152x6/8/B Pin descriptions
Doc ID 17659 Rev 8 43/121
PC2 SEG20 TIMx_IC3 EVENTOUT
PC3 SEG21 TIMx_IC4 EVENTOUT
PC4 SEG22 TIMx_IC1 EVENTOUT
PC5 SEG23 TIMx_IC2 EVENTOUT
PC6 TIM3_CH1 SEG24 TIMx_IC3 EVENTOUT
PC7 TIM3_CH2 SEG25 TIMx_IC4 EVENTOUT
PC8 TIM3_CH3 SEG26 TIMx_IC1 EVENTOUT
PC9 TIM3_CH4 SEG27 TIMx_IC2 EVENTOUT
PC10 USART3_
TX
COM4 /
SEG28 /
SEG40
TIMx_IC3 EVENTOUT
PC11 USART3_
RX
COM5 /
SEG29 /
SEG41
TIMx_IC4 EVENTOUT
PC12 USART3_
CK
COM6 /
SEG30 /
SEG42
TIMx_IC1 EVENTOUT
PC13-
WKUP2
RTC_TAMP1/
RTC_TS/
RTC_OUT/
WKUP2
TIMx_IC2 EVENTOUT
PC14-
OSC32_IN OSC32_IN TIMx_IC3 EVENTOUT
PC15-
OSC32_OUT OSC32_OUT TIMx_IC4 EVENTOUT
PD0 TIM9_CH1 SPI2_NSS TIMx_IC1 EVENTOUT
PD1 SPI2_SCK TIMx_IC2 EVENTOUT
Table 10. Alternate function input/output (continued)
Port
name
Digital alternate function number
AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15
Alternate function
SYSTEM TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART
1/2/3 N/A N/A USB LCD N/A N/A RI SYSTEM
Pin descriptions STM32L151x6/8/B, STM32L152x6/8/B
44/121 Doc ID 17659 Rev 8
PD2 TIM3_ETR
COM7 /
SEG31 /
SEG43
TIMx_IC3 EVENTOUT
PD3 SPI2_MISO USART2_
CTS TIMx_IC4 EVENTOUT
PD4 SPI2_MOSI USART2_
RTS TIMx_IC1 EVENTOUT
PD5 USART2_
TX TIMx_IC2 EVENTOUT
PD6 USART2_
RX TIMx_IC3 EVENTOUT
PD7 TIM9_CH2 USART2_
CK TIMx_IC4 EVENTOUT
PD8 USART3_
TX SEG28 TIMx_IC1 EVENTOUT
PD9 USART3_
RX SEG29 TIMx_IC2 EVENTOUT
PD10 USART3_
CK SEG30 TIMx_IC3 EVENTOUT
PD11 USART3_
CTS SEG31 TIMx_IC4 EVENTOUT
PD12 TIM4_CH1 USART3_
RTS SEG32 TIMx_IC1 EVENTOUT
PD13 TIM4_CH2 SEG33 TIMx_IC2 EVENTOUT
PD14 TIM4_CH3 SEG34 TIMx_IC3 EVENTOUT
PD15 TIM4_CH4 SEG35 TIMx_IC4 EVENTOUT
PE0 TIM4_ETR TIM10_CH1 SEG36 TIMx_IC1 EVENTOUT
PE1 TIM11_CH1 SEG37 TIMx_IC2 EVENTOUT
PE2 TRACECK TIM3_ETR SEG 38 TIMx_IC3 EVENTOUT
PE3 TRACED0 TIM3_CH1 SEG 39 TIMx_IC4 EVENTOUT
Table 10. Alternate function input/output (continued)
Port
name
Digital alternate function number
AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15
Alternate function
SYSTEM TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART
1/2/3 N/A N/A USB LCD N/A N/A RI SYSTEM
STM32L151x6/8/B, STM32L152x6/8/B Pin descriptions
Doc ID 17659 Rev 8 45/121
PE4 TRACED1 TIM3_CH2 TIMx_IC1 EVENTOUT
PE5 TRACED2 TIM9_CH1* TIMx_IC2 EVENTOUT
PE6 TRACED3 /
WKUP3 TIM9_CH2* TIMx_IC3 EVENTOUT
PE7 TIMx_IC4 EVENTOUT
PE8 TIMx_IC1 EVENTOUT
PE9 TIM2_CH1_
ETR TIMx_IC2 EVENTOUT
PE10 TIM2_CH2 TIMx_IC3 EVENTOUT
PE11 TIM2_CH3 TIMx_IC4 EVENTOUT
PE12 TIM2_CH4 SPI1_NSS TIMx_IC1 EVENTOUT
PE13 SPI1_SCK TIMx_IC2 EVENTOUT
PE14 SPI1_MISO TIMx_IC3 EVENTOUT
PE15 SPI1_MOSI TIMx_IC4 EVENTOUT
PH0-OSC_IN OSC_IN
PH1-
OSC_OUT OSC_OUT
PH2
Table 10. Alternate function input/output (continued)
Port
name
Digital alternate function number
AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFIO8 AFIO9 AFIO10 AFIO11 AFIO12 AFIO13 AFIO14 AFIO15
Alternate function
SYSTEM TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART
1/2/3 N/A N/A USB LCD N/A N/A RI SYSTEM
Memory mapping STM32L151x6/8/B, STM32L152x6/8/B
46/121 Doc ID 17659 Rev 8
5 Memory mapping
The memory map is shown in the following figure.
Figure 9. Memory map
reserved
0x4000 0000
0x4000 0400
0x4000 0800
0x4000 0C00
0x4000 2800
0x4000 2C00
0x4000 3000
0x4000 3400
0x4000 3800
0x4000 3C00
0x4000 4400
0x4000 4800
0x4000 4C00
0x4001 0C00
0x4001 1000
0x4001 1400
APB memory space
CRC
0x4002 3800
TIM2
Reserved
0x4001 0800
0x4001 2400
0x4001 2800
0x4001 3000
0x4001 3400
0x4001 3800
TIM3
TIM4
RTC
WWDG
IWDG
reserved
SPI2
USART2
USART3
SYSCFG
TIM9
TIM11
rese rve d
ADC
reserved
USART1
reserved
0x4002 3400
0x4002 0000
0x4001 3C00
0x4000 5400
0x4000 5800
reserved
reserved
SPI1
I2C1
0x4000 6000
0x4000 5C00
PWR
TIM10
I2C2
reserved
EXTI
reserved
RCC
Flash Interf ace
reserved
reserved
reserved
0x4000 6200
0x4000 7000
0x4000 7400
0x4000 7C00
0x4001 0400
0x4002 3C00
0x4002 4000
0x4002 6000
0x4002 6400
0x6000 0000
0xE010 0000
reserved
0xFFFF FFFF
USB Registers
DMA
0
1
2
3
4
5
6
7
0x2000 0000
0x4000 0000
0x6000 0000
0x8000 0000
0xA000 0000
0xC000 0000
0xE000 0000
0xFFFF FFFF
0x0000 0000
Peripherals
SRAM
Cortex- M3 Internal
Peripherals
0xE010 0000
ai18200b
512 byte
USB
TIM6
TIM7
LCD
reserved
reserved
0x4000 1000
0x4000 1400
0x4000 2400
0x4000 1C00
DAC1 & 2
0x4000 7800
Port A
Port B
Port C
Port D
Port E
Port H
reserved
0x4002 3000
0x4002 1800
0x4002 1400
0x4002 1000
0x4002 0C00
0x4002 0800
0x4002 0400
COMP + RI
Flash memory
rese rved
rese rved
0x0800 0000
0x0801 FFFF
0x1FF0 0000
0x1FF8 001F
System memory
Option Bytes
0x1FF0 0FFF
0x1FF8 0000
Aliased to Flash or system
memory depending on
BOOT pins
0x0000 0000
rese rved
Data EEPROM
rese rved
0x0808 0000
0x0808 0FFF
0x4001 0000
reserved
reserved
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 47/121
6 Electrical characteristics
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.65 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions Figure 11. Pin input voltage
ai17851
C = 50 pF
STM32L15xxx pin
ai17852
STM32L15xxx pin
VIN
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
48/121 Doc ID 17659 Rev 8
6.1.6 Power supply scheme
Figure 12. Power supply scheme
6.1.7 Current consumption measurement
Figure 13. Current consumption measurement scheme
ai15401c
VDD1/2/.../5
Analo g:
RCs, PLL,
...
GP I/O s
OUT
IN
Kernel logic
(CPU,
Digital
& Memories)
Standby-power circuitry
(OSC32K,RTC,
RTC backup registers)
Wake-up logic
11 × 100 nF
+ 1 × 4.7 µF
Regulator
VSS1/2/.../5
VDDA
VREF+
VREF-
VSSA
ADC
Level shifter
IO
Logic
VDD
10 nF
+ 1 µF
VREF
10 nF
+ 1 µF
VDD
ai14126b
VDD
VDDA
IDD
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 49/121
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Ta b l e 11: Voltage characteristics,
Ta bl e 12: Current characteristics, and Ta bl e 13: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 11. Voltage characteristics
Symbol Ratings Min Max Unit
VDD–VSS
External main supply voltage
(including VDDA and VDD)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
–0.3 4.0
V
VIN(2)
2. VIN maximum must always be respected. Refer to Table 12 for maximum allowed injected current values.
Input voltage on five-volt tolerant pin VSS − 0.3 VDD+4.0
Input voltage on any other pin VSS − 0.3 4.0
|ΔVDDx| Variations between different VDD power pins 50 mV
|VSSX − VSS| Variations between all different ground pins 50
VESD(HBM)
Electrostatic discharge voltage
(human body model) see Section 6.3.10
Table 12. Current characteristics
Symbol Ratings Max. Unit
IVDD Total current into VDD/VDDA power lines (source)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
80
mA
IVSS Total current out of VSS ground lines (sink)(1) 80
IIO
Output current sunk by any I/O and control pin 25
Output current sourced by any I/O and control pin - 25
IINJ(PIN) (2)
2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.16.
Injected current on five-volt tolerant I/O(3)
3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN)
must never be exceeded. Refer to Table 11 for maximum allowed input voltage values.
+0 /-5
Injected current on any other pin (4)
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN)
must never be exceeded. Refer to Table 11: Voltage characteristics for the maximum allowed input voltage
values.
± 5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(5)
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
± 25
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
50/121 Doc ID 17659 Rev 8
6.3 Operating conditions
6.3.1 General operating conditions
Table 13. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature 150 °C
Table 14. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency 0 32
MHzfPCLK1 Internal APB1 clock frequency 0 32
fPCLK2 Internal APB2 clock frequency 0 32
VDD Standard operating voltage
BOR detector disabled 1.65 3.6
V
BOR detector enabled,
at power on 1.8 3.6
BOR detector disabled,
after power on 1.65 3.6
VDDA(1)
1. When the ADC is used, refer to Table 54: ADC characteristics.
Analog operating voltage
(ADC and DAC not used) Must be the same voltage
as VDD(2)
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
1.65 3.6
V
Analog operating voltage
(ADC or DAC used) 1.8 3.6
PD
Power dissipation at
TA = 85 °C(3)
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 68: Thermal
characteristics on page 114).
BGA100 package 339 mW
TA Temperature range Maximum power dissipation –40 85 °C
Low power dissipation(4)
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max
(see Table 68: Thermal characteristics on page 114).
–40 105
TJ Junction temperature range -40 °C ≤ TA ≤ 105 °C –40 105 °C
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 51/121
6.3.2 Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Ta b l e 14.
Table 15. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
tVDD(1)
VDD rise time rate
BOR detector enabled 0 ∞
µs/V
BOR detector disabled 0 1000
VDD fall time rate
BOR detector enabled 20 ∞
BOR detector disabled 0 1000
TRSTTEMPO(1) Reset temporization VDD rising, BOR enabled 2 3.3 ms
VDD rising, BOR disabled(2) 0.4 0.7 1.6
VPOR/PDR
Power on/power down reset
threshold
Falling edge 1 1.5 1.65
V
Rising edge 1.3 1.5 1.65
VBOR0 Brown-out reset threshold 0 Falling edge 1.67 1.7 1.74
Rising edge 1.69 1.76 1.8
VBOR1 Brown-out reset threshold 1 Falling edge 1.87 1.93 1.97
Rising edge 1.96 2.03 2.07
VBOR2 Brown-out reset threshold 2 Falling edge 2.22 2.30 2.35
Rising edge 2.31 2.41 2.44
VBOR3 Brown-out reset threshold 3 Falling edge 2.45 2.55 2.60
Rising edge 2.54 2.66 2.7
VBOR4 Brown-out reset threshold 4 Falling edge 2.68 2.8 2.85
Rising edge 2.78 2.9 2.95
VPVD0
Programmable voltage detector
threshold 0
Falling edge 1.8 1.85 1.88
Rising edge 1.88 1.94 1.99
VPVD1 PVD threshold 1 Falling edge 1.98 2.04 2.09
Rising edge 2.08 2.14 2.18
VPVD2 PVD threshold 2 Falling edge 2.20 2.24 2.28
Rising edge 2.28 2.34 2.38
VPVD3 PVD threshold 3 Falling edge 2.39 2.44 2.48
Rising edge 2.47 2.54 2.58
VPVD4 PVD threshold 4 Falling edge 2.57 2.64 2.69
Rising edge 2.68 2.74 2.79
VPVD5 PVD threshold 5 Falling edge 2.77 2.83 2.88
Rising edge 2.87 2.94 2.99
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
52/121 Doc ID 17659 Rev 8
VPVD6 PVD threshold 6 Falling edge 2.97 3.05 3.09 V
Rising edge 3.08 3.15 3.20
Vhyst Hysteresis voltage
BOR0 threshold 40
mV
All BOR and PVD thresholds
excepting BOR0 100
1. Guaranteed by characterisation, not tested in production.
2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details.
Table 15. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 53/121
6.3.3 Embedded internal reference voltage
The parameters given in Ta b l e 16 are based on characterization results, unless otherwise
specified.
Table 16. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT out(1) Internal reference voltage – 40 °C < TJ < +105 °C 1.202 1.224 1.242 V
IREFINT
Internal reference current
consumption 1.4 2.3 µA
TVREFINT Internal reference startup time 2 3 ms
VVREF_MEAS
VDDA and VREF+ voltage during
VREFINT factory measure 2.99 3 3.01 V
AVREF_MEAS
Accuracy of factory-measured
VREF value(2)
Including uncertainties
due to ADC and
VDDA/VREF+ values
±5 mV
TCoeff(3) Temperature coefficient –40 °C < TJ < +105 °C 20 50 ppm/°C
0 °C < TJ < +50 °C 20
ACoeff(3) Long-term stability 1000 hours, T= 25 °C 1000 ppm
VDDCoeff(3) Voltage coefficient 3.0 V < VDDA < 3.6 V 2000 ppm/V
TS_vrefint(3)(4)
ADC sampling time when
reading the internal reference
voltage
510 µs
TADC_BUF(3) Startup time of reference voltage
buffer for ADC 10 µs
IBUF_ADC(3) Consumption of reference
voltage buffer for ADC 13.5 25 µA
IVREF_OUT(3) VREF_OUT output current(5) 1µA
CVREF_OUT(3) VREF_OUT output load 50 pF
ILPBUF(3)
Consumption of reference
voltage buffer for VREF_OUT
and COMP
730 1200 nA
VREFINT_DIV1(3) 1/4 reference voltage 24 25 26
%
VREFINT
VREFINT_DIV2(3) 1/2 reference voltage 49 50 51
VREFINT_DIV3(3) 3/4 reference voltage 74 75 76
1. Tested in production;
2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
3. Guaranteed by design, not tested in production.
4. Shortest sampling time can be determined in the application by multiple iterations.
5. To guarantee less than 1% VREF_OUT deviation.
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
54/121 Doc ID 17659 Rev 8
6.3.4 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code. The current consumption is measured as described in Figure 13: Current
consumption measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
●VDD = 3.6 V
●All I/O pins are in input mode with a static value at VDD or VSS (no load)
●All peripherals are disabled except when explicitly mentioned
●The Flash memory access time is adjusted depending on fHCLK frequency and voltage
range
●Prefetch and 64-bit access are enabled in configurations with 1 wait state
The parameters given in Ta b l e 17, Ta bl e 14 and Ta b le 15 are derived from tests performed
under ambient temperature and VDD supply voltage conditions summarized in Ta b l e 14.
Table 17. Current consumption in Run mode, code with data processing running from Flash
Symbol Parameter Conditions fHCLK Typ
Max(1)
Unit
55 °C 85 °C 105 °C
IDD (Run
from
Flash)
Supply
current in
Run mode,
code
executed
from Flash
fHSE = fHCLK
up to 8 MHz,
included
fHSE = fHCLK/2
above 8 MHz
(PLL ON)(2)
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
1 MHz 270 400 400 400
µA2 MHz 470 600 600 600
4 MHz 890 1025 1025 1025
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
4 MHz 1 1.3 1.3 1.3
mA
8 MHz 2 2.5 2.5 2.5
16 MHz 3.9 5 5 5
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
8 MHz 2.16 3 3 3
16 MHz 4.8 5.5 5.5 5.5
32 MHz 9.6 11 11 11
HSI clock source
(16 MHz)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz 4 5 5 5
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz 9.4 11 11 11
MSI clock, 65 kHz Range 3,
VCORE=1.2 V
VOS[1:0] = 11
65 kHz 0.05 0.085 0.09 0.1
MSI clock, 524 kHz 524 kHz 0.15 0.185 0.19 0.2
MSI clock, 4.2 MHz 4.2 MHz 0.9 1 1 1
1. Based on characterization, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 55/121
Table 18. Current consumption in Run mode, code with data processing running from RAM
Symbol Parameter Conditions fHCLK Typ
Max(1)
Unit
55 °C 85 °C 105 °C
IDD (Run
from
RAM)
Supply current
in Run mode,
code executed
from RAM,
Flash switched
off
fHSE = fHCLK
up to 8 MHz,
included
fHSE = fHCLK/2
above 8 MHz
(PLL ON)(2)
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
1 MHz 200 300 300 300
µA2 MHz 380 500 500 500
4 MHz 720 860 860 860(3)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
4 MHz 0.9 1 1 1
mA
8 MHz 1.65 2 2 2
16 MHz 3.2 3.7 3.7 3.7
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
8 MHz 2 2.5 2.5 2.5
16 MHz 4 4.5 4.5 4.5
32 MHz 7.7 8.5 8.5 8.5
HSI clock source
(16 MHz)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz 3.3 3.8 3.8 3.8
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz 7.8 9.2 9.2 9.2
MSI clock, 65 kHz Range 3,
VCORE=1.2 V
VOS[1:0] = 11
65 kHz 40 60 60 80
µAMSI clock, 524 kHz 524 kHz 110 140 140 160
MSI clock, 4.2 MHz 4.2 MHz 700 800 800 820
1. Based on characterization, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
3. Tested in production.
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
56/121 Doc ID 17659 Rev 8
Table 19. Current consumption in Sleep mode
Symbol Parameter Conditions fHCLK Typ
Max(1)
Unit
55 °C 85 °C 105 °C
IDD
(Sleep)
Supply
current in
Sleep
mode,
code
executed
from RAM,
Flash
switched
OFF
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
above 16 MHz (PLL
ON)(2)
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
1 MHz 80 140 140 140
µA
2 MHz 150 210 210 210
4 MHz 280 330 330 330(3)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
4 MHz 280 400 400 400
8 MHz 450 550 550 550
16 MHz 900 1050 1050 1050
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
8 MHz 550 650 650 650
16 MHz 1050 1200 1200 1200
32 MHz 2300 2500 2500 2500
HSI clock source
(16 MHz)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz 1000 1100 1100 1100
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz 2300 2500 2500 2500
MSI clock, 65 kHz Range 3,
VCORE=1.2 V
VOS[1:0] = 11
65 kHz 30 50 50 60
MSI clock, 524 kHz 524 kHz 50 70 70 80
MSI clock, 4.2 MHz 4.2 MHz 200 240 240 250
Supply
current in
Sleep
mode,
code
executed
from Flash
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
above 16 MHz (PLL
ON)(2)
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
1 MHz 80 140 140 140
µA
2 MHz 150 210 210 210
4 MHz 290 350 350 350
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
4 MHz 300 400 400 400
8 MHz 500 600 600 600
16 MHz 1000 1100 1100 1100
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
8 MHz 550 650 650 650
16 MHz 1050 1200 1200 1200
32 MHz 2300 2500 2500 2500
HSI clock source
(16 MHz)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz 1000 1100 1100 1100
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz 2300 2500 2500 2500
IDD
(Sleep)
Supply
current in
Sleep
mode,
code
executed
from Flash
MSI clock, 65 kHz
Range 3,
VCORE=1.2V
VOS[1:0] = 11
65 kHz 40 70 70 80
µA
MSI clock, 524 kHz 524 kHz 60 90 90 100
MSI clock, 4.2 MHz 4.2 MHz 210 250 250 260
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 57/121
1. Based on characterization, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)
3. Tested in production
Table 20. Current consumption in Low power run mode
Symbol Parameter Conditions Typ Max
(1) Unit
IDD (LP
Run)
Supply
current in
Low power
run mode
All
peripherals
OFF, code
executed
from RAM,
Flash
switched
OFF, VDD
from 1.65 V
to 3.6 V
MSI clock, 65 kHz
fHCLK = 32 kHz
TA = -40 °C to 25 °C 9 12
µA
TA = 85 °C 17.5 24
TA = 105 °C 31 46
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = -40 °C to 25 °C 14 17
TA = 85 °C 22 29
TA = 105 °C 35 51
MSI clock, 131 kHz
fHCLK = 131 kHz
TA = -40 °C to 25 °C 37 42
TA = 55 °C 37 42
TA = 85 °C 37 42
TA = 105 °C 48 65
All
peripherals
OFF, code
executed
from Flash,
VDD from
1.65 V to
3.6 V
MSI clock, 65 kHz
fHCLK = 32 kHz
TA = -40 °C to 25 °C 24 32
TA = 85 °C 33 42
TA = 105 °C 48 64
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = -40 °C to 25 °C 31 40
TA = 85 °C 40 48
TA = 105 °C 54 70
MSI clock, 131 kHz
fHCLK = 131 kHz
TA = -40 °C to 25 °C 48 58
TA = 55 °C 54 63
TA = 85 °C 56 65
TA = 105 °C 70 90
IDD Max
(LP
Run)(2)
Max allowed
current in
Low power
run mode
VDD from
1.65 V to
3.6 V
200
1. Based on characterization, not tested in production, unless otherwise specified.
2. This limitation is related to the consumption of the CPU core and the peripherals that are powered by the regulator.
Consumption of the I/Os is not included in this limitation.
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
58/121 Doc ID 17659 Rev 8
Table 21. Current consumption in Low power sleep mode
Symbol Parameter Conditions Typ Max
(1)
1. Based on characterization, not tested in production, unless otherwise specified.
Unit
IDD (LP
Sleep)
Supply
current in
Low power
sleep
mode
All
peripherals
OFF, VDD
from 1.65 V
to 3.6 V
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash OFF
TA = -40 °C to 25 °C 4.4
µA
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash ON
TA = -40 °C to 25 °C 17.5 25
TA = 85 °C 22 27
TA = 105 °C 31 39
MSI clock, 65 kHz
fHCLK = 65 kHz,
Flash ON
TA = -40 °C to 25 °C 18 26
TA = 85 °C 23 28
TA = 105 °C 31 40
MSI clock, 131 kHz
fHCLK = 131 kHz,
Flash ON
TA = -40 °C to 25 °C 22 30
TA = 55 °C 24 32
TA = 85 °C 26 34
TA = 105 °C 34 45
TIM9 and
USART1
enabled,
Flash ON,
VDD from
1.65 V to
3.6 V
MSI clock, 65 kHz
fHCLK = 32 kHz
TA = -40 °C to 25 °C 17.5 25
TA = 85 °C 22 27
TA = 105 °C 31 39
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = -40 °C to 25 °C 18 26
TA = 85 °C 23 28
TA = 105 °C 31 40
MSI clock, 131 kHz
fHCLK = 131 kHz
TA = -40 °C to 25 °C 22 30
TA = 55 °C 24 32
TA = 85 °C 26 34
TA = 105 °C 34 45
IDD Max
(LP Sleep)
Max
allowed
current in
Low power
Sleep
mode
VDD from
1.65 V to
3.6 V
200
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 59/121
Table 22. Typical and maximum current consumptions in Stop mode
Symbol Parameter Conditions Typ(1) Max
(1)(2) Unit
IDD (Stop
with RTC)
Supply current in
Stop mode with
RTC enabled
RTC clocked by LSI,
regulator in LP mode,
HSI and HSE OFF
(no independent
watchdog)
LCD OFF
TA = -40°C to 25°C
VDD = 1.8 V 1.2 2.75
µA
TA = -40°C to 25°C 1.4 4
TA = 55°C 2.6 6
TA= 85°C 4.8 10
TA = 105°C 10.2 23
LCD ON
(static
duty)(3)
TA = -40°C to 25°C 3.3 6
TA = 55°C 4.5 8
TA= 85°C 6.6 12
TA = 105°C 13.6 27
LCD ON
(1/8
duty)(4)
TA = -40°C to 25°C 7.7 10
TA = 55°C 8.6 12
TA= 85°C 10.7 16
TA = 105°C 19.8 40
RTC clocked by LSE
external clock (32.768
kHz), regulator in LP
mode, HSI and HSE
OFF (no independent
watchdog)
LCD OFF
TA = -40°C to 25°C 1.6 4
TA = 55°C 2.7 6
TA= 85°C 4.8 10
TA = 105°C 10.3 23
LCD ON
(static
duty)(3)
TA = -40°C to 25°C 3.6 6
TA = 55°C 4.6 8
TA= 85°C 6.7 12
TA = 105°C 10.9 23
LCD ON
(1/8
duty)(4)
TA = -40°C to 25°C 7.6 10
TA = 55°C 8.6 12
TA= 85°C 10.7 16
TA = 105°C 19.8 40
RTC clocked by LSE
(no independent
watchdog)(5)
LCD OFF
TA = -40°C to 25°C
VDD = 1.8 V 1.45
TA = -40°C to 25°C
VDD = 3.0 V 1.9
TA = -40°C to 25°C
VDD = 3.6 V 2.2
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
60/121 Doc ID 17659 Rev 8
IDD (Stop)
Supply current in
Stop mode (
RTC disabled)
Regulator in LP mode, HSI and
HSE OFF, independent watchdog
and LSI enabled
TA = -40°C to 25°C 1.1 2.2
µA
Regulator in LP mode, LSI, HSI
and HSE OFF (no independent
watchdog)
TA = -40°C to 25°C 0.5 0.9
TA = 55°C 1.9 5
TA= 85°C 3.7 8
TA = 105°C 8.9 20(6)
IDD (WU
from Stop)
RMS (root mean
square) supply
current during
wakeup time
when exiting
from Stop mode
MSI = 4.2 MHz
VDD = 3.0 V
TA = -40°C to 25°C
2
mA
MSI = 1.05 MHz 1.45
MSI = 65 kHz(7) 1.45
1. The typical values are given for VDD = 3.0 V and max values are given for VDD = 3.6 V, unless otherwise
specified.
2. Based on characterization, not tested in production, unless otherwise specified
3. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected
4. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
5. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY)
with two 6.8pF loading capacitors.
6. Tested in production
7. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the
remaining time of the wakeup period, the current is similar to the Run mode current.
Table 22. Typical and maximum current consumptions in Stop mode
Symbol Parameter Conditions Typ(1) Max
(1)(2) Unit
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 61/121
Table 23. Typical and maximum current consumptions in Standby mode
Symbol Parameter Conditions Typ(1) Max
(1)(2) Unit
IDD
(Standby
with RTC)
Supply current in Standby
mode with RTC enabled
RTC clocked by LSI (no
independent watchdog)
TA = -40 °C to 25 °C
VDD = 1.8 V 0.9
TA = -40 °C to 25 °C 1.1 1.8
µA
TA = 55 °C 1.42 2.5
TA= 85 °C 1.87 3
TA = 105 °C 2.78 5
RTC clocked by LSE (no
independent watchdog)(3)
TA = -40 °C to 25 °C
VDD = 1.8 V 1
TA = -40 °C to 25 °C 1.33 2.9
TA = 55 °C 1.59 3.4
TA= 85 °C 2.01 4.3
TA = 105 °C 3.27 6.3
IDD
(Standby)
Supply current in Standby
mode with RTC disabled
Independent watchdog and
LSI enabled TA = -40 °C to 25 °C 1.1 1.6
Independent watchdog and
LSI OFF
TA = -40 °C to 25 °C 0.3 0.55
TA = 55 °C 0.5 0.8
TA = 85 °C 1 1.7
TA = 105 °C 2.5 4(4)
IDD (WU
from
Standby)
RMS supply current during
wakeup time when exiting
from Standby mode
VDD = 3.0 V
TA = -40 °C to 25 °C 1µA
1. The typical values are given for VDD = 3.0 V and max values are given for VDD = 3.6 V, unless otherwise specified.
2. Based on characterization, not tested in production, unless otherwise specified.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.
4. Tested in production.
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
62/121 Doc ID 17659 Rev 8
Wakeup time from Low power mode
The wakeup times given in the following table are measured with the MSI RC oscillator. The
clock source used to wake up the device depends on the current operating mode:
●Sleep mode: the clock source is the clock that was set before entering Sleep mode
●Stop mode: the clock source is the MSI oscillator in the range configured before
entering Stop mode
●Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Ta b l e 14.
Table 24. Typical and maximum timings in Low power modes
Symbol Parameter Conditions Typ Max(1)
1. Based on characterization, not tested in production, unless otherwise specified
Unit
tWUSLEEP Wakeup from Sleep mode fHCLK = 32 MHz 0.36
µs
tWUSLEEP_LP
Wakeup from Low power
sleep mode
fHCLK = 262 kHz
fHCLK = 262 kHz
Flash enabled 32
fHCLK = 262 kHz
Flash switched OFF 34
tWUSTOP
Wakeup from Stop mode,
regulator in Run mode fHCLK = fMSI = 4.2 MHz 8.2
Wakeup from Stop mode,
regulator in low power mode
fHCLK = fMSI = 4.2 MHz
Voltage range 1 and 2 8.2 9.3
fHCLK = fMSI = 4.2 MHz
Voltage range 3 7.8 11.2
fHCLK = fMSI = 2.1 MHz 10 12
fHCLK = fMSI = 1.05 MHz 15.5 20
fHCLK = fMSI = 524 kHz 29 35
fHCLK = fMSI = 262 kHz 53 63
fHCLK = fMSI = 131 kHz 105 118
fHCLK = MSI = 65 kHz 210 237
tWUSTDBY
Wakeup from Standby mode
FWU bit = 1 fHCLK = MSI = 2.1 MHz 50 103
Wakeup from Standby mode
FWU bit = 0 fHCLK = MSI = 2.1 MHz 2.5 3.2 ms
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 63/121
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
●all I/O pins are in input mode with a static value at VDD or VSS (no load)
●all peripherals are disabled unless otherwise mentioned
●the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
Table 25. Peripheral current consumption(1)
Peripheral
Typical consumption, VDD = 3.0 V, TA = 25 °C
Unit
Range 1,
VCORE=
1.8 V
VOS[1:0] =
01
Range 2,
VCORE=
1.5 V
VOS[1:0] =
10
Range 3,
VCORE=
1.2 V
VOS[1:0] =
11
Low power
sleep and
run
APB1
TIM2 13 10.5 8 10.5
µA/MHz
(fHCLK)
TIM3 14 12 9 12
TIM4 12.5 10.5 8 11
TIM6 5.5 4.5 3.5 4.5
TIM7 5.5 5 3.5 4.5
LCD 5.553.55
WWDG 4 3.5 2.5 3.5
SPI2 5.5 5 4 5
USART2 9 8 5.5 8.5
USART3 10.5 9 6 8
I2C1 8.5 7 5.5 7.5
I2C2 8.5 7 5.5 6.5
USB 12.5 10 6.5 10
PWR 4.5 4 3 3.5
DAC 9 7.5 6 7
COMP 4.5 4 3.5 4.5
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
64/121 Doc ID 17659 Rev 8
APB2
SYSCFG &
RI 32.522.5
µA/MHz
(fHCLK)
TIM9 9 7.5 6 7
TIM10 6.5 5.5 4.5 5.5
TIM11 7 6 4.5 5.5
ADC(2) 11.5 9.5 8 9
SPI1 5 4.5 3 4
USART197.567.5
AHB
GPIOA 5 4.5 3.5 4
GPIOB 5 4.5 3.5 4.5
GPIOC 5 4.5 3.5 4.5
GPIOD 5 4.5 3.5 4.5
GPIOE 5 4.5 3.5 4.5
GPIOH4433.5
CRC 1 0.5 0.5 0.5
FLASH 13 11.5 9 18.5
DMA1 12 10 8 10.5
All enabled 166 138 106 130
IDD (RTC) 0.47
µA
IDD (LCD) 3.1
IDD (ADC)(3) 1450
IDD (DAC)(4) 340
IDD (COMP1) 0.16
IDD (COMP2)
Slow mode 2
Fast mode 5
IDD (PVD / BOR)(5) 2.6
IDD (IWDG) 0.25
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
3. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC
conversion (HSI consumption not included).
Table 25. Peripheral current consumption(1) (continued)
Peripheral
Typical consumption, VDD = 3.0 V, TA = 25 °C
Unit
Range 1,
VCORE=
1.8 V
VOS[1:0] =
01
Range 2,
VCORE=
1.5 V
VOS[1:0] =
10
Range 3,
VCORE=
1.2 V
VOS[1:0] =
11
Low power
sleep and
run
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 65/121
6.3.5 External clock source characteristics
High-speed external user clock generated from an external source
4. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC
conversion of VDD/2. DAC is in buffered mode, output is left floating.
5. Including supply current of internal reference voltage.
Table 26. High-speed external user clock characteristics(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext
User external clock source
frequency 1832MHz
VHSEH OSC_IN input pin high level voltage 0.7VDD VDD V
VHSEL OSC_IN input pin low level voltage VSS 0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time 12
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time 20
Cin(HSE) OSC_IN input capacitance 2.6 pF
DuCy(HSE) Duty cycle 45 55 %
ILOSC_IN Input leakage current VSS ≤ VIN ≤ VD
D
±1 µA
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
66/121 Doc ID 17659 Rev 8
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a low-
speed external clock source, and under ambient temperature and supply voltage conditions
summarized in Ta b l e 14.
Figure 14. Low-speed external clock source AC timing diagram
Table 27. Low-speed external user clock characteristics(1)
1. Guaranteed by design, not tested in production
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext
User external clock source
frequency 1 32.768 1000 kHz
VLSEH
OSC32_IN input pin high level
voltage 0.7VDD VDD
V
VLSEL
OSC32_IN input pin low level
voltage VSS 0.3VDD
tw(LSE)
tw(LSE)
OSC32_IN high or low time 465 - -
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time - - 10
CIN(LSE) OSC32_IN input capacitance - 0.6 - pF
DuCy(LSE) Duty cycle 45 - 55 %
ILOSC32_IN Input leakage current VSS ≤ VIN ≤ VDD --±1µA
ai18233
OSC32_IN
EXTER NAL
STM32Lxx
CLOCK SOURCE
VLSEH
tf(LSE) tW(LSE)
IL
90%
10%
TLSE
t
tr(LSE) tW(LSE)
fLSE_ext
VLSEL
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 67/121
Figure 15. High-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta b l e 28. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
ai18232
OSC _I N
EXTER NAL
STM32Lxx
CLOCK SOURCE
VHSEH
tf(HSE) tW(HSE)
IL
90%
10%
THSE
t
tr(HSE) tW(HSE)
fHSE_ext
VHSEL
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
68/121 Doc ID 17659 Rev 8
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
Table 28. HSE 1-24 MHz oscillator characteristics(1)(2)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization results, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
fOSC_IN Oscillator frequency 1 24 MHz
RFFeedback resistor 200 kΩ
C
Recommended load
capacitance versus
equivalent serial resistance
of the crystal (RS)(3)
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
RS = 30 Ω 20 pF
IHSE HSE driving current VDD= 3.3 V, VIN = VSS
with 30 pF load 3mA
IDD(HSE)
HSE oscillator power
consumption
C = 20 pF
fOSC = 16 MHz
2.5 (startup)
0.7 (stabilized) mA
C = 10 pF
fOSC = 16 MHz
2.5 (startup)
0.46 (stabilized)
gmOscillator transconductance Startup 3.5 mA
/V
tSU(HSE)
(4)
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
Startup time VDD is stabilized 1 ms
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 69/121
Figure 16. HSE oscillator circuit diagram
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta b l e 29. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
1. Based on characterization, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
fLSE
Low speed external oscillator
frequency 32.768 kHz
RFFeedback resistor 1.2 MΩ
C(2)
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details;
RS = 30 kΩ8pF
ILSE LSE driving current VDD = 3.3 V, VIN = VSS 1.1 µA
IDD (LSE)
LSE oscillator current
consumption
VDD = 1.8 V 450
nAVDD = 3.0 V 600
VDD = 3.6V 750
gmOscillator transconductance 3 µA/V
tSU(LSE)(4)
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Startup time VDD is stabilized 1 s
OSC_OUT
OSC_IN
f
HSE
to core
C
L1
C
L2
R
F
STM32
Resonator
Consumption
control
g
m
R
m
C
m
L
m
C
O
Resonator
ai18235
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
70/121 Doc ID 17659 Rev 8
Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator (see Figure 17).
CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Figure 17. Typical application with a 32.768 kHz crystal
ai17853
OSC32_OUT
OSC32_IN
fLSE
CL1
RF
STM32L15xxx
32.768 kHz
resonator
CL2
Resonator with
integrated capacitors
Bias
controlled
gain
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 71/121
6.3.6 Internal clock source characteristics
The parameters given in Ta b l e 30 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Ta bl e 14.
High-speed internal (HSI) RC oscillator
Low-speed internal (LSI) RC oscillator
Table 30. HSI oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency VDD = 3.0 V 16 MHz
TRIM(1)(2)
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
HSI user-trimmed
resolution
Trimming code is not a multiple of 16 ± 0.4 0.7 %
Trimming code is a multiple of 16 ± 1.5 %
ACCHSI(2)
2. Based on characterization, not tested in production.
Accuracy of the
factory-calibrated
HSI oscillator
VDDA = 3.0 V, TA = 25 °C -1(3)
3. Tested in production.
1(3) %
VDDA = 3.0 V, TA = 0 to 55 °C -1.5 1.5 %
VDDA = 3.0 V, TA = -10 to 70 °C -2 2 %
VDDA = 3.0 V, TA = -10 to 85 °C -2.5 2 %
VDDA = 3.0 V, TA = -10 to 105 °C -4 2 %
VDDA = 1.65 V to 3.6 V
TA = -40 to 105 °C -4 3 %
tSU(HSI)(2) HSI oscillator
startup time 3.7 6 µs
IDD(HSI)(2) HSI oscillator
power consumption 100 140 µA
Table 31. LSI oscillator characteristics
Symbol Parameter Min Typ Max Unit
fLSI(1)
1. Tested in production.
LSI frequency 26 38 56 kHz
DLSI(2)
2. This is a deviation for an individual part, once the initial frequency has been measured.
LSI oscillator frequency drift
0°C ≤ TA ≤ 85°C -10 4 %
tsu(LSI)(3)
3. Guaranteed by design, not tested in production.
LSI oscillator startup time 200 µs
IDD(LSI)(3) LSI oscillator power consumption 400 510 nA
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
72/121 Doc ID 17659 Rev 8
Multi-speed internal (MSI) RC oscillator
Table 32. MSI oscillator characteristics
Symbol Parameter Condition Typ Max Unit
fMSI
Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
MSI range 0 65.5
kHz
MSI range 1 131
MSI range 2 262
MSI range 3 524
MSI range 4 1.05
MHzMSI range 5 2.1
MSI range 6 4.2
ACCMSI Frequency error after factory calibration ±0.5 %
DTEMP(MSI)(1) MSI oscillator frequency drift
0 °C ≤ TA ≤ 85 °C ±3%
DVOLT(MSI)(1) MSI oscillator frequency drift
1.65 V ≤ VDD ≤ 3.6 V, TA = 25 °C 2.5 %/V
IDD(MSI)(2) MSI oscillator power consumption
MSI range 0 0.75
µA
MSI range 1 1
MSI range 2 1.5
MSI range 3 2.5
MSI range 4 4.5
MSI range 5 8
MSI range 6 15
tSU(MSI) MSI oscillator startup time
MSI range 0 30
µs
MSI range 1 20
MSI range 2 15
MSI range 3 10
MSI range 4 6
MSI range 5 5
MSI range 6,
Voltage range 1
and 2
3.5
MSI range 6,
Voltage range 3 5
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 73/121
6.3.7 PLL characteristics
The parameters given in Ta b l e 33 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Ta bl e 14.
tSTAB(MSI)(2) MSI oscillator stabilization time
MSI range 0 40
µs
MSI range 1 20
MSI range 2 10
MSI range 3 4
MSI range 4 2.5
MSI range 5 2
MSI range 6,
Voltage range 1
and 2
2
MSI range 3,
Voltage range 3 3
fOVER(MSI) MSI oscillator frequency overshoot
Any range to
range 5 4
MHz
Any range to
range 6 6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Based on characterization, not tested in production.
Table 32. MSI oscillator characteristics (continued)
Symbol Parameter Condition Typ Max Unit
Table 33. PLL characteristics
Symbol Parameter
Value
Unit
Min Typ Max(1)
1. Based on characterization, not tested in production.
fPLL_IN
PLL input clock(2)
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
224MHz
PLL input clock duty cycle 45 55 %
fPLL_OUT PLL output clock 2 32 MHz
tLOCK
Worst case PLL lock time
PLL input = 2 MHz
PLL VCO = 96 MHz
100 130 µs
Jitter Cycle-to-cycle jitter ± 600 ps
IDDA(PLL) Current consumption on VDDA 220 450 µA
IDD(PLL) Current consumption on VDD 120 150
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74/121 Doc ID 17659 Rev 8
6.3.8 Memory characteristics
The characteristics are given at TA = -40 to 105 °C unless otherwise specified.
RAM memory
Table 34. RAM and hardware registers
Flash memory and data EEPROM
Symbol Parameter Conditions Min Typ Max Unit
VRM Data retention mode(1)
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
STOP mode (or RESET) 1.65 V
Table 35. Flash memory and data EEPROM characteristics
Symbol Parameter Conditions Min Typ Max(1)
1. Guaranteed by design, not tested in production.
Unit
VDD
Operating voltage
Read / Write / Erase 1.65 3.6 V
tprog
Programming time for
word or half-page
Erasing 3.28 3.94 ms
Programming 3.28 3.94
IDD
Average current during
whole programme/erase
operation TA = 25 °C, VDD = 3.6 V
300 µA
Maximum current (peak)
during programme/erase
operation
1.5 2.5 mA
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
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6.3.9 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Ta b l e 37. They are based on the EMS levels and classes
defined in application note AN1709.
Table 36. Flash memory, data EEPROM endurance and data retention
Symbol Parameter Conditions
Value
Unit
Min(1)
1. Based on characterization not tested in production.
Typ Max
NCYC(2)
Cycling (erase / write )
Program memory TA = -40°C to
105 °C
10
kcycles
Cycling (erase / write )
EEPROM data memory 300
tRET(2)
2. Characterization is done according to JEDEC JESD22-A117.
Data retention (program memory) after
10 kcycles at TA = 85 °C TRET = +85 °C
30
years
Data retention (EEPROM data memory)
after 300 kcycles at TA = 85 °C 30
Data retention (program memory) after
10 kcycles at TA = 105 °C TRET = +105 °C
10
Data retention (EEPROM data memory)
after 300 kcycles at TA = 105 °C 10
Table 37. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 32 MHz
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
4A
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
76/121 Doc ID 17659 Rev 8
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●Corrupted program counter
●Unexpected reset
●Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 38. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs. frequency range
Unit
4 MHz
voltage
range 3
16 MHz
voltage
range 2
32 MHz
voltage
range 1
SEMI Peak level
VDD = 3.3 V,
TA = 25 °C,
LQFP100 package
compliant with IEC
61967-2
0.1 to 30 MHz 3 -6 -5
dBµV30 to 130 MHz 18 4 -7
130 MHz to 1GHz 15 5 -7
SAE EMI Level 2.5 2 1 -
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
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6.3.10 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●A supply overvoltage is applied to each power supply pin
●A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
6.3.11 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation. However,
in order to give an indication of the robustness of the microcontroller in cases when
abnormal injection accidentally happens, susceptibility tests are performed on a sample
basis during device characterization.
Table 39. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum value(1)
1. Based on characterization results, not tested in production.
Unit
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = +25 °C, conforming
to JESD22-A114 22000
V
VESD(CDM)
Electrostatic discharge
voltage (charge device model)
TA = +25 °C, conforming
to JESD22-C101 II 500
Table 40. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
78/121 Doc ID 17659 Rev 8
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in the following table.
Table 41. I/O current injection susceptibility
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
IINJ
Injected current on true open-drain pins -5 +0
mAInjected current on all 5 V tolerant (FT) pins -5 +0
Injected current on any other pin -5 +5
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
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6.3.12 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Ta b l e 42 are derived from tests
performed under conditions summarized in Ta b le 14. All I/Os are CMOS and TTL compliant.
Table 42. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage
TTL ports
2.7 V ≤ VDD≤ 3.6 V
VSS - 0.3 0.8
V
VIH
Standard I/O input high level voltage 2(1) VDD+0.3
FT(2) I/O input high level voltage 5.5V
VIL Input low level voltage CMOS ports
1.65 V ≤ VDD≤ 3.6 V –0.3 0.3VDD(3)
VIH
Standard I/O Input high level voltage CMOS ports
1.65 V ≤ VDD≤ 3.6 V
0.7
VDD(3)(4)
VDD+0.3
FT(5) I/O input high level voltage
CMOS ports
1.65 V ≤ VDD≤ 2.0 V 5.25
CMOS ports
2.0 V≤ VDD≤ 3.6 V 5.5
Vhys
Standard I/O Schmitt trigger voltage
hysteresis(6) 10% VDD(7)
Ilkg Input leakage current (8)(3)
VSS ≤ VIN ≤ VDD
I/Os with LCD ±50
nA
VSS ≤ VIN ≤ VDD
I/Os with analog switches ±50
VSS ≤ VIN ≤ VDD
I/Os with analog switches
and LCD
±50
VSS ≤ VIN ≤ VDD
I/Os with USB TBD
VSS ≤ VIN ≤ VDD
Standard I/Os ±50
RPU Weak pull-up equivalent resistor(9)(3) VIN = VSS 30 45 60 kΩ
RPD Weak pull-down equivalent resistor(9)(3) VIN = VDD 30 45 60 kΩ
CIO I/O pin capacitance 5 pF
1. Guaranteed by design.
2. FT = 5V tolerant. To sustain a voltage higher than VDD +0.5 the internal pull-up/pull-down resistors must be disabled.
3. Tested in production
4. 0.7VDD for 5V-tolerant receiver
5. FT = Five-volt tolerant.
6. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
7. With a minimum of 200 mV. Based on characterization, not tested in production.
8. The max. value may be exceeded if negative current is injected on adjacent pins.
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with the non-standard VOL/VOH specifications given in Ta bl e 43.
in the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
●The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Ta bl e 1 2 ).
●The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 12).
Output voltage levels
Unless otherwise specified, the parameters given in Ta b l e 43 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Ta bl e 14. All I/Os are CMOS and TTL compliant.
9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
Table 43. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
VOL(1)(2)
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. Tested in production.
Output low level voltage for an I/O pin
when 8 pins are sunk at same time IIO = +8 mA
2.7 V < VDD < 3.6 V
0.4
V
VOH(3)(2)
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
Output high level voltage for an I/O pin
when 8 pins are sourced at same time 2.4
VOL (1)(4) Output low level voltage for an I/O pin
when 8 pins are sunk at same time IIO =+ 4 mA
1.65 V < VDD <
2.7 V
0.45
VOH (3)(4) Output high level voltage for an I/O pin
when 8 pins are sourced at same time VDD-0.45
VOL(1)(4)
4. Based on characterization data, not tested in production.
Output low level voltage for an I/O pin
when 4 pins are sunk at same time IIO = +20 mA
2.7 V < VDD < 3.6 V
1.3
VOH(3)(4) Output high level voltage for an I/O pin
when 4 pins are sourced at same time VDD-1.3
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 18 and
Ta bl e 44, respectively.
Unless otherwise specified, the parameters given in Ta b l e 44 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Ta bl e 14.
Table 44. I/O AC characteristics(1)
OSPEEDRx
[1:0] bit
value(1)
Symbol Parameter Conditions Min Max(2) Unit
00
fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 400 kHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 400
tf(IO)out
tr(IO)out
Output rise and fall time CL = 50 pF, VDD = 2.7 V to 3.6 V - 625 ns
CL = 50 pF, VDD = 1.65 V to 2.7 V - 625
01
fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 2 MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 1
tf(IO)out
tr(IO)out
Output rise and fall time CL = 50 pF, VDD = 2.7 V to 3.6 V - 125 ns
CL = 50 pF, VDD = 1.65 V to 2.7 V - 250
10
Fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 10 MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 2
tf(IO)out
tr(IO)out
Output rise and fall time CL = 50 pF, VDD = 2.7 V to 3.6 V - 25 ns
CL = 50 pF, VDD = 1.65 V to 2.7 V - 125
11
Fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 50 MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 8
tf(IO)out
tr(IO)out
Output rise and fall time CL = 30 pF, VDD = 2.7 V to 3.6 V - 5
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V - 30
-t
EXTIpw
Pulse width of external
signals detected by the
EXTI controller
8-
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L15xxx reference manual for a description
of GPIO Port configuration register.
2. Guaranteed by design. Not tested in production.
3. The maximum frequency is defined in Figure 18.
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Figure 18. I/O AC characteristics definition
6.3.13 NRST pin characteristics
The NRST pin input driver uses CMOS technology.
Unless otherwise specified, the parameters given in Ta b l e 45 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Ta bl e 14.
ai14131b
10%
90%
50%
tr( I O)ou t
External
Output
on 50pF
Maximum frequency is achieved if (t
r
+ t
f
) ≤ 2/3)T and if the duty cycle is (45-55%)
10 %
50%
90%
when loaded by 50 pF
T
tf(I O)ou t
Table 45. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST)(1)
1. Guaranteed by design, not tested in production.
NRST input low level voltage VSS 0.8
V
VIH(NRST)(1) NRST input high level voltage 1.4 VDD
VOL(NRST)(1) NRST output low level
voltage
IOL = 2 mA
2.7 V < VDD < 3.6 V 0.4
IOL = 1.5 mA
1.65 V < VDD < 2.7 V
Vhys(NRST)(1) NRST Schmitt trigger voltage
hysteresis 10%VDD(2)
2. 200 mV minimum value
mV
RPU
Weak pull-up equivalent
resistor(3)
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is around 10%.
VIN = VSS 30 45 60 kΩ
VF(NRST)(1) NRST input filtered pulse 50 ns
VNF(NRST)(1) NRST input not filtered pulse 350 ns
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
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Figure 19. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 45. Otherwise the reset will not be taken into account by the device.
6.3.14 TIM timer characteristics
The parameters given in the following table are guaranteed by design.
Refer to Section 6.3.11: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).
ai17854
STM32L15xxx
RPU
NRST
(2)
VDD
Filter
Internal reset
0.1 μF
External
reset circuit
(1)
Table 46. TIMx(1) characteristics
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
Symbol Parameter Conditions Min Max Unit
tres(TIM) Timer resolution time 1tTIMxCLK
fTIMxCLK = 32 MHz 31.25 ns
fEXT Timer external clock
frequency on CH1 to CH4
0
fTIMxCLK/2 MHz
fTIMxCLK = 32 MHz 0 16 MHz
ResTIM Timer resolution 16 bit
tCOUNTER
16-bit counter clock period
when internal clock is
selected (timer’s prescaler
disabled)
1 65536 tTIMxCLK
fTIMxCLK = 32 MHz 0.0312 2048 µs
tMAX_COUNT Maximum possible count 65536 × 65536 tTIMxCLK
fTIMxCLK = 32 MHz 134.2 s
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6.3.15 Communications interfaces
I2C interface characteristics
The line I2C interface meets the requirements of the standard I2C communication protocol
with the following restrictions: SDA and SCL are not “true” open-drain I/O pins. When
configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled,
but is still present.
The I2C characteristics are described in Ta b l e 47. Refer also to Section 6.3.11: I/O current
injection characteristics for more details on the input/output alternate function characteristics
(SDA and SCL).
Table 47. I2C characteristics
Symbol Parameter
Standard mode I2C(1)
1. Guaranteed by design, not tested in production.
Fast mode I2C(1)(2)
2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 1.3 µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100
ns
th(SDA) SDA data hold time 0 0 900(3)
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
tr(SDA)
tr(SCL)
SDA and SCL rise time 1000 20 + 0.1Cb300
tf(SDA)
tf(SCL)
SDA and SCL fall time 300 300
th(STA) Start condition hold time 4.0 0.6
µs
tsu(STA)
Repeated Start condition
setup time 4.7 0.6
tsu(STO) Stop condition setup time 4.0 0.6 μs
tw(STO:STA)
Stop to Start condition time
(bus free) 4.7 1.3 μs
Cb
Capacitive load for each bus
line 400 400 pF
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
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Figure 20. I2C bus AC waveforms and measurement circuit
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 48. SCL frequency (fPCLK1= 32 MHz, VDD = 3.3 V)(1)(2)
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external
components used to design the application.
fSCL (kHz)
I2C_CCR value
RP = 4.7 kΩ
400 0x801B
300 0x8024
200 0x8035
100 0x00A0
50 0x0140
20 0x0320
ai17855
START
SD A
100
4.7k
I
2
C bus
4.7k
100
VDD
VDD
STM32L15xxx
SDA
SCL
tf(SDA) tr(SDA)
SCL
th(STA)
tw(SCKH)
tw(SCKL)
tsu(SDA)
tr(SCK) tf(SCK)
th(SDA)
S TART REPEATED
START
tsu(STA)
tsu(STO)
STOP tsu(STA:STO)
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SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Ta b l e 14.
Refer to Section 6.3.11: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 49. SPI characteristics(1)
1. The characteristics above are given for voltage range 1.
Symbol Parameter Conditions Min Max(2)
2. Based on characterization, not tested in production.
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode - 16
MHzSlave mode - 16
Slave transmitter - 12(3)
3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty
cycle (DuCy(SCK)) ranging between 40 to 60%.
tr(SCK)(2)
tf(SCK)(2)
SPI clock rise and fall
time Capacitive load: C = 30 pF - 6 ns
DuCy(SCK) SPI slave input clock duty
cycle Slave mode 30 70 %
tsu(NSS) NSS setup time Slave mode 4tHCLK -
ns
th(NSS) NSS hold time Slave mode 2tHCLK -
tw(SCKH)(2)
tw(SCKL)(2) SCK high and low time Master mode tSCK/2
−5
tSCK/2+
3
tsu(MI)(2)
Data input setup time Master mode 5 -
tsu(SI)(2) Slave mode 6 -
th(MI)(2)
Data input hold time Master mode 5 -
th(SI)(2) Slave mode 5 -
ta(SO)(4)
4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the
data.
Data output access time Slave mode 0 3tHCLK
tv(SO) (2) Data output valid time Slave mode - 33
tv(MO)(2) Data output valid time Master mode - 6.5
th(SO)(2)
Data output hold time Slave mode 17 -
th(MO)(2) Master mode 0.5 -
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 87/121
Figure 21. SPI timing diagram - slave mode and CPHA = 0
Figure 22. SPI timing diagram - slave mode and CPHA = 1(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
ai14134c
SCK Input
CPHA= 0
MOSI
INPUT
MISO
OUT P UT
CPHA= 0
MS B O UT
MSB IN
BI T6 OU T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
tSU(NSS)
tc(SCK)
th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI)
th(SI)
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUT P UT
CPHA=1
MS B O UT
MSB IN
BI T6 OU T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
tSU(NSS) tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI) th(SI)
NSS input
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
88/121 Doc ID 17659 Rev 8
Figure 23. SPI timing diagram - master mode(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
USB characteristics
The USB interface is USB-IF certified (full speed).
Table 50. USB startup time
Symbol Parameter Max Unit
tSTARTUP(1)
1. Guaranteed by design, not tested in production.
USB transceiver startup time 1 µs
ai14136
SCK Input
CPHA= 0
MOSI
OUTPUT
MISO
INP UT
CPHA= 0
MS BIN
M SB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
B I T1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
SCK Input
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 89/121
Figure 24. USB timings: definition of data signal rise and fall time
Table 51. USB DC electrical characteristics
Symbol Parameter Conditions Min.(1)
1. All the voltages are measured from the local ground potential.
Max.(1) Unit
Input levels
VDD USB operating voltage(2)
2. To be compliant with the USB 2.0 full speed electrical specification, the USB_DP (D+) pin should be pulled
up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.
3.0 3.6 V
VDI(3)
3. Guaranteed by characterization, not tested in production.
Differential input sensitivity I(USB_DP, USB_DM) 0.2
VVCM(3) Differential common mode range Includes VDI range 0.8 2.5
VSE(3) Single ended receiver threshold 1.3 2.0
Output levels
VOL(4)
4. Tested in production.
Static output level low RL of 1.5 kΩ to 3.6 V(5)
5. RL is the load connected on the USB drivers.
0.3 V
VOH(4) Static output level high RL of 15 kΩ to VSS(5) 2.8 3.6
Table 52. USB: full speed electrical characteristics
Driver characteristics(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Conditions Min Max Unit
trRise time(2)
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
CL = 50 pF 420ns
tfFall Time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf90 110 %
VCRS Output signal crossover voltage 1.3 2.0 V
ai14137
tf
Differen tial
Data L ines
VSS
V
CR S
tr
Crossover
points
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
90/121 Doc ID 17659 Rev 8
6.3.16 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Ta b l e 54 are guaranteed by design.
Table 53. ADC clock frequency
Symbol Parameter Conditions Min Max Unit
fADC
ADC clock
frequency
Voltage
range 1 & 2
2.4 V ≤ VDDA ≤ 3.6 V
VREF+ = VDDA
0.480
16
MHz
VREF+ < VDDA
VREF+ > 2.4 V 8
VREF+ < VDDA
VREF+ ≤ 2.4 V 4
1.8 V ≤ VDDA ≤ 2.4 V VREF+ = VDDA 8
VREF+ < VDDA 4
Voltage range 3 4
Table 54. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA Power supply 1.8 3.6
VVREF+ Positive reference voltage
2.4 V ≤ VDDA ≤ 3.6 V
VREF+ must be below
or equal to VDDA
1.8(1) VDDA
VREF- Negative reference voltage VSSA
IVDDA
Current on the VDDA input
pin 1000 1450 µA
IVREF(2) Current on the VREF input
pin
Peak 400 700
Average 450
VAIN Conversion voltage range(3) 0(4) VREF+ V
fS
12-bit sampling rate Direct channels 0.03 1 Msps
Multiplexed channels 0.03 0.76
10-bit sampling rate Direct channels 0.03 1.07 Msps
Multiplexed channels 0.03 0.8
8-bit sampling rate Direct channels 0.03 1.23 Msps
Multiplexed channels 0.03 0.89
6-bit sampling rate Direct channels 0.03 1.45 Msps
Multiplexed channels 0.03 1
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 91/121
tSSampling time
Direct channels
2.4 V ≤ VDDA ≤ 3.6 V 0.25
µs
Multiplexed channels
2.4 V ≤ VDDA ≤ 3.6 V 0.56
Direct channels
1.8 V ≤ VDDA ≤ 2.4 V 0.56
Multiplexed channels
1.8 V ≤ VDDA ≤ 2.4 V 1
4 384 1/fADC
tCONV Total conversion time
(including sampling time)
fADC = 16 MHz 1 24.75 µs
4 to 384 (sampling
phase) +12 (successive
approximation)
1/fADC
CADC Internal sample and hold
capacitor
Direct channels 16 pF
Multiplexed channels
fTRIG
External trigger frequency
Regular sequencer
12-bit conversions Tconv+1 1/fADC
6/8/10-bit conversions Tconv 1/fADC
fTRIG
External trigger frequency
Injected sequencer
12-bit conversions Tconv+2 1/fADC
6/8/10-bit conversions Tconv+1 1/fADC
RAIN External input impedance 50 kΩ
tlat Injection trigger conversion
latency
fADC = 16 MHz 219 281 ns
3.5 4.5 1/fADC
tlatr Regular trigger conversion
latency
fADC = 16 MHz 156 219 ns
2.5 3.5 1/fADC
tSTAB Power-up time 3.5 µs
1. The Vref+ input can be grounded iif neither the ADC nor the DAC are used (this allows to shut down an
external voltage reference).
2. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x
400 = 450 µA at 1Msps
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on
the package. Refer to Section 4: Pin descriptions for further details.
4. VSSA or VREF- must be tied to ground.
Table 54. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
92/121 Doc ID 17659 Rev 8
Table 55. ADC accuracy(1)(2)
Symbol Parameter Test conditions Min(3) Typ Max(3) Unit
ET Total unadjusted error
2.4 V ≤ VDDA ≤ 3.6 V
2.4 V ≤ VREF+ ≤ 3.6 V
fADC = 8 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
-24
LSB
EO Offset error - 1 2
EG Gain error - 1.5 3.5
ED Differential linearity error - 1 2
EL Integral linearity error - 1.7 3
ENOB Effective number of bits 2.4 V ≤ VDDA ≤ 3.6 V
VDDA = VREF+
fADC = 16 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
1 kHz ≤ Finput ≤ 100 kHz
9.2 10 - bits
SINAD Signal-to-noise and
distorsion ratio 57.5 62 -
dB
SNR Signal-to-noise ratio 57.5 62 -
THD Total harmonic distorsion -74 -75 -
ET Total unadjusted error
2.4 V ≤ VDDA ≤ 3.6 V
1.8 V ≤ VREF+ ≤ 2.4 V
fADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
-46.5
LSB
EO Offset error - 2 4
EG Gain error - 4 6
ED Differential linearity error - 1 2
EL Integral linearity error - 1.5 3
ET Total unadjusted error
1.8 V ≤ VDDA ≤ 2.4 V
1.8 V ≤ VREF+ ≤ 2.4 V
fADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
23
LSB
EO Offset error 1 1.5
EG Gain error 1.5 2
ED Differential linearity error 1 2
EL Integral linearity error 1 1.5
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.11 does not affect the ADC
accuracy.
3. Based on characterization, not tested in production.
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 93/121
Figure 25. ADC accuracy characteristics
Figure 26. Typical connection diagram using the ADC
1. Refer to Table 56: RAIN max for fADC = 16 MHz for the value of RAIN and Table 54: ADC characteristics for
the value of CADC
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
EO
EG
1LSB
IDEAL
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
4095
4094
4093
5
4
3
2
1
0
7
6
1234567 4093 4094 4095 4096
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
ai14395b
V
REF+
4096 (or depending on package)]
V
DDA
4096
[1LSB
IDEAL
=
ai17856c
STM32L15xxx
VDD
AINx
IL± 50 nA
0.6 V
VT
RAIN(1)
Cparasitic
VAIN
0.6 V
VT
12-bit
converter
CADC(1)
Sample and hold ADC
converter
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
94/121 Doc ID 17659 Rev 8
Figure 27. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 28 or Figure 29,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed as close as possible to the chip.
ADC clock
Sampling (n cycles) Conversion (12 cycles)
Iref+
300µA
700µA
Table 56. RAIN max for fADC = 16 MHz(1)
Ts
(cycles)
Ts
(µs)
RAIN max (kohm)
Multiplexed channels Direct channels
2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V
4 0.25 Not allowed Not allowed 0.7 Not allowed
9 0.5625 0.8 Not allowed 2.0 1.0
16 1 2.0 0.8 4.0 3.0
24 1.5 3.0 1.8 6.0 4.5
48 3 6.8 4.0 15.0 10.0
96 6 15.0 10.0 30.0 20.0
192 12 32.0 25.0 50.0 40.0
384 24 50.0 50.0 50.0 50.0
1. Guaranteed by design, not tested in production.
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 95/121
Figure 28. Power supply and reference decoupling (VREF+ not connected to VDDA)
1. VREF+ and VREF– inputs are available only on 100-pin packages.
Figure 29. Power supply and reference decoupling (VREF+ connected to VDDA)
1. VREF+ and VREF– inputs are available only on 100-pin packages.
VREF+
(see note 1)
STM32L15xxx
VDDA
VSSA /VREF–
(see note 1)
1 μF // 100 nF
1 μF // 100 nF
ai17857b
VREF+/VDDA
STM32L15xxx
1 μF // 100 nF
VREF–/VSSA
ai17858a
(See note 1)
(See note 1)
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
96/121 Doc ID 17659 Rev 8
6.3.17 DAC electrical specifications
Data guaranteed by design, not tested in production, unless otherwise specified.
Table 57. DAC characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage 1.8 3.6
V
VREF+ Reference supply voltage VREF+ must always be below
VDDA
1.8 3.6
VREF- Lower reference voltage VSSA
IDDVREF+(1)
Current consumption on
VREF+ supply
VREF+ = 3.3 V
No load, middle code (0x800) 130 220
µA
No load, worst code (0x000) 220 350
IDDA(1)
Current consumption on
VDDA supply
VDDA = 3.3 V
No load, middle code (0x800) 210 320
No load, worst code (0xF1C) 320 520
RL(2) Resistive load DAC output buffer ON 5kΩ
CL(2) Capacitive load 50 pF
ROOutput impedance DAC output buffer OFF 6 8 10 kΩ
VDAC_OUT Voltage on DAC_OUT
output
DAC output buffer ON 0.2 VDDA – 0.2 V
DAC output buffer OFF 0.5 VREF+ – 1LSB mV
DNL(1) Differential non linearity(3)
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON 1.5 3
LSB
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF 1.5 3
INL(1) Integral non linearity(4)
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON 24
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF 24
Offset(1) Offset error at code 0x800
(5)
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON ±10 ±25
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF ±5 ±8
Offset1(1) Offset error at code
0x001(6)
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF ±1.5 ±5
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 97/121
dOffset/dT(1) Offset error temperature
coefficient (code 0x800)
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer OFF
-20 -10 0
µV/°C
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer ON
020 50
Gain(1) Gain error(7)
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON +0.1 / -0.2% +0.2 / -0.5%
%
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF +0 / -0.2% +0 / -0.4%
dGain/dT(1) Gain error temperature
coefficient
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer OFF
-10 -2 0
µV/°C
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer ON
-40 -8 0
TUE(1) Total unadjusted error
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON 12 30
LSB
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF 812
tSETTLING
Settling time (full scale: for
a 12-bit code transition
between the lowest and
the highest input codes till
DAC_OUT reaches final
value ±1LSB
CL ≤ 50 pF, RL ≥ 5 kΩ712µs
Update rate
Max frequency for a
correct DAC_OUT change
(95% of final value) with 1
LSB variation in the input
code
CL ≤ 50 pF, RL ≥ 5 kΩ1 Msps
tWAKEUP
Wakeup time from off
state (setting the ENx bit
in the DAC Control
register)(8)
CL ≤ 50 pF, RL ≥ 5 kΩ915µs
PSRR+ VDDA supply rejection ratio
(static DC measurement) CL ≤ 50 pF, RL ≥ 5 kΩ-60 -35 dB
1. Data based on characterization results.
2. Connected between DAC_OUT and VSSA.
3. Difference between two consecutive codes - 1 LSB.
Table 57. DAC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
98/121 Doc ID 17659 Rev 8
Figure 30. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
6.3.18 Temperature sensor characteristics
4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and
last Code 4095.
5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
6. Difference between the value measured at Code (0x001) and the ideal value.
7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and
0xFFF when buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON.
8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
RLOAD
CLOAD
Buffered/Non-buffered DAC
DAC_OUTx
Buffer(1)
12-bit
digital to
analog
converter
ai17157V2
Table 58. Temperature sensor characteristics
Symbol Parameter Min Typ Max Unit
TL(1)
1. Guaranteed by characterization, not tested in production.
VSENSE linearity with temperature ±1±2°C
Avg_Slope(1) Average slope 1.48 1.61 1.75 mV/°C
V110 Voltage at 110°C ±5°C(2)
2. Measured at VDD = 3 V ±10 mV. V110 ADC conversion result is stored in the TSENSE_CAL2 byte.
612 626.8 641.5 mV
IDDA(TEMP)(3) Current consumption 3.4 6 µA
tSTART(3)
3. Guaranteed by design, not tested in production.
Startup time 10
µs
TS_temp(4)(3)
4. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading the
temperature 10
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 99/121
6.3.19 Comparator
Table 59. Comparator 1 characteristics
Symbol Parameter Conditions Min(1) Typ Max(1)
1. Based on characterization, not tested in production.
Unit
VDDA Analog supply voltage 1.65 3.6 V
R400K R400K value 400 kΩ
R10K R10K value 10
VIN
Comparator 1 input
voltage range 0.6 VDDA V
tSTART Comparator startup time 7 10 µs
td Propagation delay(2)
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
310
Voffset Comparator offset ±3±10 mV
dVoffse t/dt
Comparator offset
variation in worst voltage
stress conditions
VDDA = 3.6 V
VIN+ = 0 V
VIN- = VREFINT
TA = 25 °C
0 1.5 10 mV/1000 h
ICOMP1 Current consumption(3)
3. Comparator consumption only. Internal reference voltage not included.
160 260 nA
Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B
100/121 Doc ID 17659 Rev 8
Table 60. Comparator 2 characteristics
Symbol Parameter Conditions Min Typ Max(1)
1. Based on characterization, not tested in production.
Unit
VDDA Analog supply voltage 1.65 3.6 V
VIN Comparator 2 input voltage range 0 VDDA V
tSTART Comparator startup time Fast mode 15 20
µs
Slow mode 20 25
td slow Propagation delay(2) in slow mode
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
1.65 V ≤ VDDA ≤
2.7 V 1.8 3.5
2.7 V ≤ VDDA ≤ 3.6 V 2.5 6
td fast Propagation delay(2) in fast mode
1.65 V ≤ VDDA ≤
2.7 V 0.8 2
2.7 V ≤ VDDA ≤ 3.6 V 1.2 4
Voffset Comparator offset error ±4±20 mV
dThreshold/
dt
Threshold voltage temperature
coefficient
VDDA = 3.3V
TA = 0 to 50 °C
V- = VREF+, 3/4
VREF+,
1/2 VREF+, 1/4 VREF+.
15 30 ppm
/°C
ICOMP2 Current consumption(3)
3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.
Fast mode 3.5 5 µA
Slow mode 0.5 2
STM32L151x6/8/B, STM32L152x6/8/B Electrical characteristics
Doc ID 17659 Rev 8 101/121
6.3.20 LCD controller (STM32L152xx only)
The STM32L152xx embeds a built-in step-up converter to provide a constant LCD reference
voltage independently from the VDD voltage. An external capacitor Cext must be connected
to the VLCD pin to decouple this converter.
Table 61. LCD controller characteristics
Symbol Parameter Min Typ Max Unit
VLCD LCD external voltage 3.6
V
VLCD0 LCD internal reference voltage 0 2.6
VLCD1 LCD internal reference voltage 1 2.73
VLCD2 LCD internal reference voltage 2 2.86
VLCD3 LCD internal reference voltage 3 2.98
VLCD4 LCD internal reference voltage 4 3.12
VLCD5 LCD internal reference voltage 5 3.26
VLCD6 LCD internal reference voltage 6 3.4
VLCD7 LCD internal reference voltage 7 3.55
Cext VLCD external capacitance 0.1 2 µF
ILCD(1)
1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD
connected
Supply current at VDD = 2.2 V 3.3 µA
Supply current at VDD = 3.0 V 3.1
RHtot(2)
2. Guaranteed by design, not tested in production.
Low drive resistive network overall value 5.28 6.6 7.92 MΩ
RL(2) High drive resistive network total value 192 240 288 kΩ
V44 Segment/Common highest level voltage VLCD V
V34 Segment/Common 3/4 level voltage 3/4 VLCD
V
V23 Segment/Common 2/3 level voltage 2/3 VLCD
V12 Segment/Common 1/2 level voltage 1/2 VLCD
V13 Segment/Common 1/3 level voltage 1/3 VLCD
V14 Segment/Common 1/4 level voltage 1/4 VLCD
V0Segment/Common lowest level voltage 0
ΔVxx(3)
3. Based on characterization, not tested in production.
Segment/Common level voltage error
TA = -40 to 85 °C± 50 mV
Package characteristics STM32L151x6/8/B, STM32L152x6/8/B
102/121 Doc ID 17659 Rev 8
7 Package characteristics
7.1 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
STM32L151x6/8/B, STM32L152x6/8/B Package characteristics
Doc ID 17659 Rev 8 103/121
Figure 31. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline
1. Drawing is not to scale.
e
IDENTIFICATION
PIN 1
GAUGE PLANE
0.25 mm
SEATING
PLANE
D
D1
D3
E3
E1
E
K
ccc C
C
125
26
100
76
75 51
50
1L_ME_V3
A2
A
A1
L1
L
c
b
A1
Package characteristics STM32L151x6/8/B, STM32L152x6/8/B
104/121 Doc ID 17659 Rev 8
Figure 32. Recommended footprint
1. Dimensions are in millimeters.
Table 62. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical
data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 12.000 0.4724
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 12.000 0.4724
e 0.500 0.0197
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc 0.080 0.0031
75 51
5076 0.5
0.3
16.7 14.3
100 26
12.3
25
1.2
16.7
1
ai14906
STM32L151x6/8/B, STM32L152x6/8/B Package characteristics
Doc ID 17659 Rev 8 105/121
Figure 33. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline
1. Drawing is not to scale.
A1
A2
A
SEATING
PLANE
ccc C
b
C
c
A1
L
L1
K
GAUGE PLANE
0.25 mm
IDENTIFICATION
PIN 1
D
D1
D3
e
116
17
32
33
48
49
64
E3
E1
E
5W_ME_V2
Package characteristics STM32L151x6/8/B, STM32L152x6/8/B
106/121 Doc ID 17659 Rev 8
Figure 34. Recommended footprint
1. Dimensions are in millimeters.
Table 63. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.400 1.350 1.450 0.0551 0.0531 0.0571
b 0.220 0.170 0.270 0.0087 0.0067 0.0106
c 0.090 0.200 0.0035 0.0079
D 12.000 11.800 12.200 0.4724 0.4646 0.4803
D1 10.000 9.800 10.200 0.3937 0.3858 0.4016
D3 7.500 0.2953
E 12.000 11.800 12.200 0.4724 0.4646 0.4803
E1 10.000 9.800 10.200 0.3937 0.3858 0.4016
E3 7.500 0.2953
e 0.500 0.0197
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
ccc 0.080 0.0031
K 3.5 0.0 7.0 3.5 0.0 7.0
48
3249
64 17
116
1.2
0.3
33
10.3
12.7
10.3
0.5
7.8
12.7
ai14909
STM32L151x6/8/B, STM32L152x6/8/B Package characteristics
Doc ID 17659 Rev 8 107/121
Figure 35. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline
1. Drawing is not to scale.
5B_ME_V2
PIN 1
IDENTIFICATION
ccc C
C
D3
0.25 mm
GAUGE PLANE
b
A1
A
A2
c
A1
L1
L
D
D1
E3
E1
E
e
12
1
13
24
25
36
37
48
SEATING
PLANE
K
Package characteristics STM32L151x6/8/B, STM32L152x6/8/B
108/121 Doc ID 17659 Rev 8
Figure 36. Recommended footprint
1. Dimensions are in millimeters.
Table 64. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 5.500 0.2165
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 5.500 0.2165
e 0.500 0.0197
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0°3.5°7° 0°3.5°7°
ccc 0.080 0.0031
9.70 5.80 7.30
12
24
0.20
7.30
1
37
36
1.20
5.80
9.70
0.30
25
1.20
0.50
ai14911b
1348
STM32L151x6/8/B, STM32L152x6/8/B Package characteristics
Doc ID 17659 Rev 8 109/121
Figure 37. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline
1. Drawing is not to scale.
1. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
1. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
A0B9_ME_V3
D
Pin 1 indentifier
laser marking area
EE
DY
D2
E2
Exposed pad
area
Z
1
48
Detail Z
R 0.125 typ.
1
48
L
C 0.500x45°
pin1 corner
A
Seating
plane
A1
b
e
ddd
Detail Y
T
Package characteristics STM32L151x6/8/B, STM32L152x6/8/B
110/121 Doc ID 17659 Rev 8
Figure 38. Recommended footprint
1. Dimensions are in millimeters.
Table 65. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T 0.152 0.0060
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e 0.500 0.0197
7.30
7.30
0.20
0.30
0.55 0.50
5.80
6.20
6.20 5.60
5.60
5.80
0.75
ai15697
48
1
12
13 24
25
36
37
STM32L151x6/8/B, STM32L152x6/8/B Package characteristics
Doc ID 17659 Rev 8 111/121
Figure 39. UFBGA100 - 7 x 7 x 0.6 mm, 0.5 mm pitch, package outline
1. Drawing is not to scale.
Table 66. UFBGA100 - 7 x 7 x 0.6 mm, 0.5 mm pitch, package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 0.530 0.460 0.600 0.0209 0.0181 0.0236
A1 0.080 0.050 0.110 0.0031 0.0020 0.0043
A2 0.450 0.400 0.500 0.0177 0.0157 0.0197
A3 0.130 0.080 0.180 0.0051 0.0031 0.0071
A4 0.320 0.270 0.370 0.0126 0.0106 0.0146
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 7.000 6.950 7.050 0.2756 0.2736 0.2776
D1 5.500 5.450 5.550 0.2165 0.2146 0.2185
E 7.000 6.950 7.050 0.2756 0.2736 0.2776
E1 5.500 5.450 5.550 0.2165 0.2146 0.2185
e 0.500 0.0197
F 0.750 0.700 0.800 0.0295 0.0276 0.0315
ddd 0.100 0.0039
eee 0.150 0.0059
fff 0.050 0.0020
A0C2_ME_V2
Seating plane
A1
eF
F
D
M
Øb (100 balls)
A
E
TOP VIEWBOTTOM VIEW
112
A1 ball
identifier
e
A
A2
Y
X
Z
ddd Z
D1
E1
eee Z Y X
fff
Ø
Ø
M
MZ
A3
A4
A1 ball
index area
Package characteristics STM32L151x6/8/B, STM32L152x6/8/B
112/121 Doc ID 17659 Rev 8
Figure 40. TFBGA64 - 8.0x8.0x1.2 mm, 0.5 mm pitch, package outline
1. Drawing is not to scale.
Table 67. TFBGA64 - 8.0x8.0x1.2 mm, 0.5 mm pitch, package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 1.200 0.0472
A1 0.150 0.0059
A2 0.200 0.0079
A4 0.600 0.0236
b 0.300 0.250 0.350 0.0118 0.0098 0.0138
D 5.000 4.850 5.150 0.1969 0.1909 0.2028
D1 3.500 0.1378
E 5.000 4.850 5.150 0.1969 0.1909 0.2028
E1 3.500 0.1378
e 0.500 0.0197
F 0.750 0.0295
ddd 0.080 0.0031
eee 0.150 0.0059
fff 0.050 0.0020
R8_ME_V3
Seating plane
A1
eF
F
D
H
Øb (64 balls)
A
E
TOP VIEWBOTTOM VIEW
18
e
A
Y
X
Z
ddd Z
D1
E1
eee Z Y X
fff
Ø
Ø
M
MZ
A2
A4
A1 ball
identifier
A1 ball
index area
STM32L151x6/8/B, STM32L152x6/8/B Package characteristics
Doc ID 17659 Rev 8 113/121
Figure 41. Recommended PCB design rules for pads (0.5 mm pitch BGA)
1. Non solder mask defined (NSMD) pads are recommended
2. 4 to 6 mils solder paste screen printing process
Pitch 0.5 mm
D pad 0.27 mm
Dsm 0.35 mm typ (depends on
the soldermask registration
tolerance)
Solder paste 0.27 mm aperture diameter
Dpad
Dsm
ai15495
Package characteristics STM32L151x6/8/B, STM32L152x6/8/B
114/121 Doc ID 17659 Rev 8
7.2 Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
●TA max is the maximum ambient temperature in °C,
●ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
●PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
●PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 68. Thermal characteristics
Symbol Parameter Value Unit
ΘJA
Thermal resistance junction-ambient
BGA100 - 7 x 7 mm 59
°C/W
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm / 0.5 mm pitch 46
Thermal resistance junction-ambient
TFBGA64 - 5 x 5 mm 65
Thermal resistance junction-ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch 45
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch 55
Thermal resistance junction-ambient
UFQFPN48 - 7 x 7 mm / 0.5 mm pitch 16
STM32L151x6/8/B, STM32L152x6/8/B Package characteristics
Doc ID 17659 Rev 8 115/121
Figure 42. Thermal resistance
7.2.1 Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
PD (mW)
Te mperature(°C)
0.00
500.00
1000.00
1500.00
2000.00
2500.00
3000.00
100 75 50 25 0
UQFN48 7x7mm
LQFP48 7x7mm
LQFP64 10x10mm
LQFP100 14x14mm
UFBGA100 7x7mm
.47
'PSCJEEFOBSFB
5+5+NBY
Ordering information scheme STM32L151x6/8/B, STM32L152x6/8/B
116/121 Doc ID 17659 Rev 8
8 Ordering information scheme
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 69. Ordering information scheme
Example: STM32 L 151 C 8 T 6 D xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
L = Low power
Device subfamily
151: Devices without LCD
152: Devices with LCD
Pin count
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size
6 = 32 Kbytes of Flash memory
8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
Package
H = BGA
T = LQFP
U = UFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C
Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
No character = tray or tube
STM32L151x6/8/B, STM32L152x6/8/B Revision history
Doc ID 17659 Rev 8 117/121
9 Revision history
on
Table 70. Document revision history
Date Revision Changes
02-Jul-2010 1 Initial release.
01-Oct-2010 2
Removed 5 V tolerance (FT) from PA3, PB0 and PC3 in Ta bl e 9:
STM32L15xxx pin definitions on page 36
Updated Table 15: Embedded reset and power control block
characteristics on page 51
Updated Table 16: Embedded internal reference voltage on page 53
Added Table 53: ADC clock frequency on page 90
Updated Table 54: ADC characteristics on page 90
16-Dec-2010 3
Modified consumptions on page 1 and in Section 3.1: Low power
modes on page 13
LED_SEG8 removed on PB6
Updated Section 6: Electrical characteristics on page 47
VFQFPN48 replaced by UFQFPN48
25-Feb-2011 4
Features: updated value of Low-power sleep.
Section 3.3.2: Power supply supervisor: updated note.
Table 9: STM32L15xxx pin definitions: modified main function (after
reset) and alternate function for OSC_IN and OSC_OUT pins; modified
footnote 5; added footnote to OSC32_IN and OSC32_OUT pins; C1
and D1 removed on PD0 and PD1 pins (TFBGA64 column).
Section 3.11: DAC (digital-to-analog converter): updated bullet list.
Table 11: Voltage characteristics on page 49: updated footnote 3
regarding IINJ(PIN).
Table 12: Current characteristics on page 49: updated footnote 4
regarding positive and negative injection.
Table 15: Embedded reset and power control block characteristics on
page 51: updated typ and max values for TRSTTEMPO (VDD rising, BOR
enabled).
Table 17: Current consumption in Run mode, code with data
processing running from Flash on page 54: removed values for HSI
clock source (16 MHz), Range 3.
Table 18: Current consumption in Run mode, code with data
processing running from RAM on page 55: removed values for HSI
clock source (16 MHz), Range 3.
Table 19: Current consumption in Sleep mode on page 56: removed
values for HSI clock source (16 MHz), Range 3 for both RAM and
Flash; changed units.
Table 20: Current consumption in Low power run mode on page 57:
updated parameter and max value of IDD Max (LP Run).
Table : on page 58: updated symbol, parameter, and max value of IDD
Max (LP Sleep).
Table 18: Typical and maximum current consumptions in Stop mode:
updated values for IDD (Stop with RTC) - RTC clocked by LSE external
clock (32.768 kHz), regulator in LP mode, HSI and HSE OFF (no
independent watchdog).
Revision history STM32L151x6/8/B, STM32L152x6/8/B
118/121 Doc ID 17659 Rev 8
25-Feb-2011 4
cont’d
Updated Table 23: Typical and maximum current consumptions in
Standby mode on page 61 (IDD (WU from Standby) instead of (IDD (WU
from Stop).
Table 24: Typical and maximum timings in Low power modes on
page 62: updated condition for Wakeup from Stop mode, regulator in
Run mode; updated max values for Wakeup from Stop mode, regulator
in low power mode; updated max values for tWUSTDBY
.
Table 25: Peripheral current consumption on page 63: updated values
for column Low power sleep and run; updated Flash values; renamed
ADC1 to ADC; updated IDD (LCD) value; updated units; added values for
IDD (RTC) and IDD (IWDG); updated footnote 1 and 3; added foot note 2
concerning ADC.
Table 26: High-speed external user clock characteristics on page 65:
added min value for tw(HSE)/tw(HSE) OSC_IN high or low time; added
max value for tr(HSE)/tf(HSE) OSC_IN rise or fall time; updated IL for typ
and max values.
Table 27: Low-speed external user clock characteristics on page 66:
updated max value for IL.
Table 28: HSE 1-24 MHz oscillator characteristics on page 68:
renamed i2 as IHSE and updated max value; updated max values for
IDD(HSE).
Table 29: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 69:
updated max value for ILSE.
Table 30: HSI oscillator characteristics on page 71: updated some min
and max values for ACCHSI.
Table 32: MSI oscillator characteristics on page 72: updated parameter,
typ, and max values for DVOLT(MSI).
Table 35: Flash memory and data EEPROM characteristics on
page 74: updated typ values for tprog.
Table 44: I/O AC characteristics on page 81: updated some max values
for 01, 10, and 11; updated min value; updated footnotes.
Table 55: ADC accuracy on page 92: updated typ values and some of
the test conditions for ENOB, SINAD, SNR, and THD.
Table 57: DAC characteristics on page 96: updated footnote 7 and
added footnote 8.
Updated leakage value in Figure 26: Typical connection diagram using
the ADC.
Added Figure 27: Maximum dynamic current consumption on VREF+
supply pin during ADC conversion.
Added Ta bl e 5 6 : RAIN max for fADC = 16 MHz on page 94
Figure 28: Power supply and reference decoupling (VREF+ not
connected to VDDA): replaced all 10 nF capacitors with 100 nF
capacitors.
Figure 29: Power supply and reference decoupling (VREF+ connected to
VDDA): replaced 10 nF capacitor with 100 nF capacitor.
Table 70. Document revision history (continued)
Date Revision Changes
STM32L151x6/8/B, STM32L152x6/8/B Revision history
Doc ID 17659 Rev 8 119/121
17-June-2011 5
Modified 1st page (low power features)
Added STM32L15xC6 and STM32L15xR6 devices (32 Kbytes of Flash
memory).
Modified Section 3.6: GPIOs (general-purpose inputs/outputs) on
page 22
Modified Section 6.3: Operating conditions on page 50
Modified Table 55: ADC accuracy on page 92, Table 57: DAC
characteristics on page 96 and Table 59: Comparator 1 characteristics
on page 99
25-Jan-2012 6
Features: updated internal multispeed low power RC.
Table 2: Ultra-low-power STM32L15xxx device features and peripheral
counts: LCD 4x44 and 8x40 available for both 64- and 128-Kbyte
devices; two comparators available for all devices.
Figure 8: STM32L15xCx UFQFPN48 pinout: replaced VFQPN48 by
UFQFPN48 as name of package.
Table 9: STM32L15xxx pin definitions: replaced PH0/PH1 by
PC14/PC15.
Table 10: Alternate function input/output: removed EVENT OUT from
PH2 port, AFIO15 column.
Table 13: Functionalities depending on the operating power supply
range: added footnote 1.
Table 19: Current consumption in Sleep mode: updated MSI conditions
and fHCLK.
Table 20: Current consumption in Low power run mode: updated some
temperature conditions; added footnote 2.
Table : : updated some temperature conditions and one of the MSI
clock conditions.
Table 22: Typical and maximum current consumptions in Stop mode:
updated IDD (WU from Stop) parameter.
Table 23: Typical and maximum current consumptions in Standby
mode: updated IDD (WU from Standby) parameter.
Table 24: Typical and maximum timings in Low power modes: updated
fHCLK value for tWUSLEEP_LP; updated typical value of parameter
“Wakeup from Stop mode, regulator in Run mode”.
Table 25: Peripheral current consumption: replaced GPIOF by GPIOH.
Table 33: PLL characteristics: updated “PLL output clock”
Table 35: Flash memory and data EEPROM characteristics: updated all
information for IDD.
Figure 18: I/O AC characteristics definition: replaced the falling edge
“tr(IO)out” by “tf(IO)out”.
Table 47: I2C characteristics: amended footnote 2.
Table 54: ADC characteristics: updated fS max value for direct
channels, 6-bit sampling rate.
Table 55: ADC accuracy: Updated the first, third and fourth fADC test
condition.
Table 58: Temperature sensor characteristics: updated typ, min, and
max values of the TS_temp parameter.
Table 70. Document revision history (continued)
Date Revision Changes
Revision history STM32L151x6/8/B, STM32L152x6/8/B
120/121 Doc ID 17659 Rev 8
26-Oct-2012 7
Updated cover page
Updated Section 3.10: ADC (analog-to-digital converter)
Updated Table 3: Functionalities depending on the operating power
supply range, added Table 4: CPU frequency range depending on
dynamic voltage scaling and Table 5: Functionalities depending on the
working mode (from Run/active down to standby)
Updated Table 27: Low-speed external user clock characteristics
Added footnote 2. in Table 15: Embedded reset and power control block
characteristics
Updated Table 22: Typical and maximum current consumptions in Stop
mode and Table 23: Typical and maximum current consumptions in
Standby mode
Updated footnote 4. in Table 22: Typical and maximum current
consumptions in Stop mode
Updated Table 44: I/O AC characteristics
Updated Table 47: I2C characteristics
Updated Table 49: SPI characteristics
Updated Section 6.3.8: Memory characteristics
Updated “non-robust” Table 54: ADC characteristics
Removed the note “position of 4.7 µf capacitor” in Section 6.1.6: Power
supply scheme
Updated Table 65: UFQFPN48 7 x 7 mm, 0.5 mm pitch, package
mechanical data
Updated Table 64: LQFP48, 7 x 7 mm, 48-pin low-profile quad flat
package mechanical data
Added the resistance of TFBGA in Table 68: Thermal characteristics
Added Figure 42: Thermal resistance
07-Feb-2013 8
Removed AHB1/AHB2 in Figure 1: Ultra-low-power STM32L15xxx
block diagram
Added IWDG and WWDG rows in Table 5: Functionalities depending
on the working mode (from Run/active down to standby)
Updated IDD (Supply current during wakeup time from Standby mode)
in Table 23: Typical and maximum current consumptions in Standby
mode
The comment "HSE = 16 MHz(2) (PLL ON for fHCLK above 16 MHz)"
replaced by "fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2
above 16 MHz (PLL ON)(2)” in Table 19: Current consumption in Sleep
mode
Updated Stop mode current to 1.2 µA in Ultra-low-power platform
Updated entire Section 7: Package characteristics
Removed alternate function “I2C2_SMBA” for GPIO pin “PH2” in
Table 9: STM32L15xxx pin definitions
Updated Figure 26: Typical connection diagram using the ADC and
definition of symbol “RAIN” in Table 54: ADC characteristics
Removed first sentence in Section : I2C interface characteristics
Table 70. Document revision history (continued)
Date Revision Changes
STM32L151x6/8/B, STM32L152x6/8/B
Doc ID 17659 Rev 8 121/121
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