PIC12F675I/P - MICROCHIP TECHNOLOGY

1. General description

The UJA1061 fail-safe System Basis Chip (SBC) replaces basic discrete components that

are common in every Electronic Co ntrol Unit (ECU) with a Controller Area Network (CAN)

and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all

networking applications that control various power and sensor peripherals by usin g

fault-tolerant CAN as the main network interface an d LIN as a local sub-bus. The fail-safe

SBC contains the following integrated devices:

•ISO11898-3 compliant fault-tolerant CAN transceiver, interoperable with TJA1054,

TJA1054A and TJA1055

•LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3

•Advanced independent watchdog

•Dedicated voltage regulator s for microcontroller and CAN transceiver

•Serial peripheral interface (full duplex)

•Local wake-up input port

•Inhibit/limp-home output port

In addition to the advantage s of integ rating these common ECU functions in a single

package, the fail-safe SBC offers an intelligent combination of system-specific functions

such as:

•Advanced low-power concep t

•Safe and controlled system start-up behavior

•Advanced fail-safe syste m behavior that prevents any conceivable deadlock

•Detailed status reporting on system and subsystem levels

The UJA1061 is designed to be used in combination with a microcontroller that

incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is

always started up in a defined manner. In failure situations, the fail-safe SBC will maintain

microcontroller functionality for as long as possible to provide full monitoring and a

software-driven fall-back operation .

The UJA1061 is designed for 14 V single power supply architectures and for 14 V and

42 V dual power supply architectures.

UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Rev. 06 — 9 March 2010 Product data sheet

Product data sheet Rev. 06 — 9 March 2010 2 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

2. Features and benefits

2.1 General

Contains a full set of CAN and LIN ECU functions:

CAN transceiver and LIN transceiver

Voltage regulator for the microcontroller (3.3 V or 5.0 V)

Separate voltage regulator for the CAN transceiver (5 V)

Enhanced window watchdog w ith on-c hip oscillator

Serial Peripheral Interface (SPI) for the microcontroller

ECU power management system

Fully integrated autonomous fail-safe system

Designed for auto mo tiv e ap plic at ion s:

Supports 14 V, 24 V and 42 V ar ch itec tu re s

Excellent ElectroMagnetic Compatibility (EMC) performance

±8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for

off-board pins

±6 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 for off-board pins

±60 V short-circuit proof CAN/LIN-bus pins

Battery and CAN/LIN-bus pins are protected against transients in accordance with

ISO 7637

Very low sleep current

Supports remote flash programming via the CAN-bus

Small 6.1 mm × 11 mm HTSSOP32 package with low thermal resistance

2.2 CAN transceiver

ISO 11898-3 compliant fault-tolerant CAN transceiver

Enhanced error signalling and reporting

Dedicated low dropout voltage regulator for the CAN-bus:

Independent from microcontroller supply

Guarded by CAN-bus failure management

Significantly improves EMC performance

Partial networking option with global wake-up feature, allows selective CAN-bus

communication without waking up sleeping nodes

Bus connections are truly floating when power is off

Ground shift detection

2.3 LIN transceiver

LIN 2.0 compliant LIN transceiver

Enhanced error signalling and reporting

Downward compatible with LIN 1.3 and the TJA1020

Product data sheet Rev. 06 — 9 March 2010 3 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

2.4 Power management

Smart operating modes and power management modes

Cyclic wake-up capability in Standby and Sleep modes

Local wake-up input with cyclic supply feature

Remote wake-up capability via the CAN-bus and LIN-bus

External volt age regulators can easily be incorporated in the power supply system

(flexible and fail-safe)

42 V battery-related high-side switch for driving external loads such as relays and

wake-up switches

Intelligent maskable interrupt output

2.5 Fail-safe features

Safe and predictable behavior under all conditions

Programmable fail-safe coded window and time-out watchdog with on-chip oscillator,

guaranteeing autonomous fail-safe system supervision

Fail-safe coded 16-bit SPI interface for the microcontroller

Global enable pin for the control of safety-critical hardware

Detection and detailed reporting of failures:

On-chip oscillator failure and watchdog alerts

Voltage regulator undervoltages

CAN and LIN-bus failures (short-circuits and open-circuit bus wires)

TXD and RXD clamping situations and short-circuits

Clamped or open reset line

SPI message erro rs

Overtemperature warning

ECU ground shift (two selectable thresholds)

Rigorous erro r ha nd lin g ba se d on diag n os tics

23 bits of access-protected RAM is available e.g. for logging of cyclic problems

Reporting in a single SPI message; no assembly of multiple SPI frames needed

limp-home output signal for activating application hardware in case system enters

Fail-safe mode (e.g. for switching on warning lights)

Fail-safe coded activation of Sof tware development mode and Flash mode

Unique SPI readable device type identification

Software-initiated system reset

Product data sheet Rev. 06 — 9 March 2010 4 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

3. Ordering information

[1] UJA1061TW/5V0 is for the 5 V version; UJA1061TW/3V3 is for the 3.3 V version.

4. Block diagram

Table 1. Ordering information

Type number Package

Name Description Version

UJA1061TW[1] HTSSOP32 plastic thermal enhanced thin shrink small outline package; 32 leads;

body width 6.1 mm; lead pitch 0.65 mm; exposed die pad SOT549-1

Fig 1. Block diagram

BAT42

BAT14

SYSINH

INH/LIMP

INTN

TEST

SCK

SDI

SDO

SCS

RTLIN

LIN

TXDL

RXDL

GND

WAKE

RSTN

RTH

CANH

CANL

TXDC

RXDC

RTL

SBC

FAIL-SAFE

SYSTEM

V1 MONITOR

RESET/EN

WATCHDOG

OSCILLATOR

GND SHIFT

DETECTOR

BAT

MONITOR

FAULT

TOLERANT

CAN

TRANSCEIVER

LIN

SPI

CHIP

TEMPERATURE

WAKE

INH

BAT42

001aad803

UJA1061

Product data sheet Rev. 06 — 9 March 2010 5 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 2. Pin configuration

UJA1061

n.c. BAT42

n.c. RESERVED

TXDL V3

V1 SYSINH

RXDL n.c.

RSTN BAT14

INTN RTLIN

EN LIN

SDI RTH

SDO GND

SCK CANL

SCS CANH

TXDC V2

RXDC RTL

n.c. WAKE

TEST INH/LIMP

001aad604

Table 2. Pin description

Symbol Pin Description

n.c. 1 not connected

n.c. 2 not connected

TXDL 3 LIN transmit data input (LOW for dominant, HIGH for recessive)

V1 4 voltage regulator output for the microcontroller (3.3 V or 5 V depending on

the SBC version)

RXDL 5 LIN receive data output (LOW when dominant, HIGH when recessive)

RSTN 6 reset output to microcontroller (active LOW; will detect clamping situations)

INTN 7 interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin

to other ECU inte rrupt outputs)

EN 8 enable output (active HIGH; push-pull, LOW with every reset / watchdog

overflow)

SDI 9 SPI data input

SDO 10 SPI data output (floating when pin SCS is HIGH)

SCK 11 SPI clock input

SCS 12 SPI chip select input (active LOW)

TXDC 13 CAN transmit data input (LOW for dominant; HIGH for recessive)

RXDC 14 CAN receive data output (LOW when dominant; HIGH when recessive)

n.c. 15 not connected

TEST 16 test pin (should be connected to ground in ap plication)

Product data sheet Rev. 06 — 9 March 2010 6 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

The exposed die pad at the bottom of the package allows better dissipation of heat from

the SBC via the printed- circuit b oar d. The expose d d ie pad is not co nnecte d to any active

part of the IC and can be left floating, or can be connected to GND for the be st EMC

performance.

INH/LIMP 17 inhibit/limp-home output (BAT14 related, push-pull, default floating)

WAKE 18 local wake-up input (BAT42 related, continuous or cyclic sampling)

RTL 19 CAN termination resistor connection; in case of a CANL bus wire error this

line is terminated with a selectable impedance

V2 20 5 V voltage regulator output for CAN; connect a buffer capacitor to this pin

CANH 21 CANH bus line (HIGH in dominant state)

CANL 22 CANL bus line (LOW in dominant state)

GND 23 ground

RTH 24 CAN termination resistor connection; in case of a CANH bus wire error this

line is terminated with a selectable impedance

LIN 25 LIN bus line (LOW in dominant state)

RTLIN 26 LIN-bus termination resistor connection

BAT14 27 14 V battery supply input

n.c. 28 not connected

SYSINH 29 system inhibit output (BAT42 related; e.g. for controlling external DC-to-DC

converter)

V3 30 unregulated 42 V output (BAT42 related; continuous outp ut, or Cyclic mode

synchronized with local wake-up input)

reserved 31 must be connected to ground (GND)

BAT42 32 42 V battery supply input (connect this pin to BAT14 in 14 V applications)

Table 2. Pin description …continued

Symbol Pin Description

Product data sheet Rev. 06 — 9 March 2010 7 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6. Functional description

6.1 Introduction

The UJA1061 combines all peripheral functions around a microcontroller within typical

automotive netw or kin g ap p lications into one de dic at ed chip . The fu nct i on s ar e as fo llow s:

•Power supply for the microcontroller

•Power supply for the CAN transceiver

•Switched BAT42 output

•System reset

•Watchdog with Window mode and Time-out mode

•On-chip oscillator

•Fault-tolerant CAN and LIN transceivers for serial communication; suitable for 12 V

and 42 V applications

•SPI control interface

•Local wake-up input

•Inhibit or limp-ho m e ou tp u t

•System inhibit output port

•Compatibility with 42 V power supply systems

•Fail-safe behavior

6.2 Fail-safe system controller

The fail-safe system controller is th e core of the UJA1061 and is supervised by a

watchdog timer that is clocked directly by the dedicated on-chip oscillator. The system

controller manages the register configuration and controls all internal functions of the

SBC. Detailed device st atus information is collected and pr esen te d to the micr ocontr oller.

The system controller also provides the reset and interrupt signals.

The fail-safe system controller is a state machine. The different operating modes and the

transitions between these modes are illustrated in Figure 3. The following sections give

further details about the SBC operating modes.

Product data sheet Rev. 06 — 9 March 2010 8 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Fig 3. Main state diagram

001aad180

flash entry enabled (111/001/111 mode sequence)

OR mode change to Sleep with pending wake-up

OR watchdog not properly served

OR interrupt ignored > tRSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

wake-up detected with its wake-up interrupt disabled

OR mode change to Sleep with pending wake-up

OR watchdog time-out with watchdog timeout interrupt disabled

OR watchdog OFF and IV1 > IthH(V1) with reset option

OR interrupt ignored > tRSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

Start-up mode

V1: ON

SYSINH: HIGH

CAN: on-line/on-line listen/off-line

LIN: off-line

watchdog: start-up

INH/LIMP: HIGH/ LOW/float

EN: LOW

Restart mode

V1: ON

SYSINH: HIGH

CAN: on-line/on-line listen/off-line

LIN: off-line

watchdog: start-up

INH/LIMP: LOW/ float

EN: LOW

Sleep mode

V1: OFF

SYSINH: HIGH/float

CAN: on-line/on-line listen/off-line

LIN: off-line

watchdog: time-out/OFF

INH/LIMP: LOW/ float

RSTN: LOW

EN: LOW

Fail-safe mode

V1: OFF

SYSINH: HIGH/float

CAN: on-line/on-line listen/off-line

LIN: off-line

watchdog: OFF

INH/LIMP: LOW

RSTN: LOW

EN: LOW

Normal mode

V1: ON

SYSINH: HIGH

CAN: all modes available

LIN: all modes available

watchdog: window

INH/LIMP: HIGH/ LOW/float

EN: HIGH/LOW

Flash mode

V1: ON

SYSINH: HIGH

CAN: all modes available

LIN: all modes available

watchdog: time-out

INH/LIMP: HIGH/ LOW/float

EN: HIGH/LOW

Standby mode

V1: ON

SYSINH: HIGH

CAN: on-line/on-line listen/off-line

LIN: off-line

watchdog: time-out/OFF

INH/LIMP: HIGH/ LOW/float

EN: HIGH/LOW

mode change via SPImode change via SPI

mode change via SPI

wake-up detected

OR watchdog time-out

OR V3 overload detected

wake-up detected

AND oscillator ok

AND t > tret

t > tWD(init)

OR SPI clock count <> 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

t > tWD(init)

OR SPI clock count <> 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

leave Flash mode code

OR watchdog time-out

OR interrupt ignored > tRSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

init Flash mode via SPI

AND flash entry enabled

init Normal mode

via SPI successful

init Normal mode

via SPI successful

supply connected

for the first time

from any

mode

oscillator fail

OR RSTN externally clamped HIGH detected > tRSTN(CHT)

OR RSTN externally clamped LOW detected > tRSTN(CLT)

OR V1 undervoltage detected > tV1(CLT)

watchdog

trigger

watchdog

trigger

mode change via SPI

watchdog

trigger

Product data sheet Rev. 06 — 9 March 2010 9 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.2.1 Start-up mode

Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and

ground are connected for the first time. Start-up mode is also entered af ter any event th at

results in a system reset. The reset source information is provided by the SBC to support

different software initialization cycles that depend on the reset event.

It is also possible to enter Start-up mode via a wake-up from Standby mode, Sleep mode

or Fail-safe mode. Such a wa ke-u p can origin ate either from the CAN- bus, the LIN-bus or

from the local WAKE pin.

On entering Start-up mode a lengthened reset time tRSTNL is observed. This reset time is

either user-d efined (via the RLC bit in the System Configur ation register) or de faults to the

value as given in Section 6.13.12. During the reset lengthening time pin RSTN is held

LOW by the SBC.

When the reset time is completed (pin RSTN is released and goes HIGH) the watchdog

timer will wait for initialization. If the watchdog initialization is successful, the selected

operating mode (Normal mode or Flash mode) will be entered. Otherwise the Restart

mode will be entered.

6.2.2 Restart mode

The purpose of the Restart mode is to give the applicatio n a second chance to sta rt up,

should the first attempt from Start-up mode fail. Entering Restart mode will always set the

reset lengthening time tRSTNL to the higher value to guarantee the maximum reset length,

regardless of previous events.

If start-up from Restart mode is successful (the previous problems do not reoccur and

watchdog initialization is successful), then the selected operating mode will be entered.

From Restart mo de this must be Normal mode. If problems persist or if V1 fails to start up,

then Fail-safe mode will be entered.

6.2.3 Fail-safe mode

Severe fault situations will cause the SBC to enter Fail-safe mode. Fail-safe mode is also

entered if start-up from Restart mode fails. Fail-safe mode offers the lowest possible

system power consumption from the SBC and fr om the external components controlled by

the SBC.

A wake-up (via the CAN-bus, the LIN-bus or the WAKE pin) is needed to leave Fail-safe

mode. This is only possible if the on-chip oscillator is running correctly. The SBC restarts

from Fail-safe mode with a defined delay tret, to guarantee a discharged V1 before

entering Start-up mode. Regulator V1 will restart and the reset lengthening time tRSTNL is

set to the higher value; see Section 6.5.1.

6.2.4 Normal mode

Normal mode gives access to all SBC system resources, including CAN, LIN, INH/LIMP

and EN. Therefore in Normal mode the SBC watchdog runs in (programmable) Window

mode, for strictest software supervision. Whenever the watchdog is not proper ly served a

system reset is performed.

Interrupts from SBC to the host microcontroller are also monitored. A system reset is

performed if the host microcontroller does not respond within tRSTN(INT).

Product data sheet Rev. 06 — 9 March 2010 10 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Entering Normal mode does not activate the CAN or LIN transceiver automatically. The

CAN Mode Control (CMC) bit must be used to activate the CAN medium if required,

allowing local cyclic wake-up scenarios to be implemented without affecting the CAN-bus.

The LIN Mode Control (LMC) bit must be used to activate the LIN medium if required,

allowing local cyclic wake-up scenarios to be im ple m ente d with ou t affecting th e LIN -b us .

6.2.5 Standby mode

In Standby mode the system is set into a state with reduced current consumption.

Entering Standby mode overrides the CM C bit, allowing the CAN transceiver to enter the

low-power mode autonomously. The watchdog will, however, continue to monitor the

microcontroller (Time-out mode) since it is powered via pin V1.

In the event that the host microcontroller can provide a low-power mode with reduced

current consumption in it s Standby mode or Stop mode, the watchdog can be switched off

entirely in S tandby mode of the SBC. The SBC monitors the microcontroller supp ly current

to ensure that there is no unob served phase with disabled watchdog an d running

microcontroller. The watchdog will remain active until the supply current drops below

IthL(V1). Below this current limit the watchdog is disabled.

Should the curren t increase to IthH(V1), e.g. as result of a microcontroller wake-up from

application specific hardware, the watchdog will start operating again with the previously

used time-out period. If the watchdog is not triggered correctly, a system reset will occur

and the SBC will enter Start-up mode.

If Standby mode is entered from Normal mode with the selected watchdog OFF option,

the watchdog will use the maximum time-out as defined for Standby mode until the supply

current drops below the current detection threshold; the watchdog is now OFF. If the

current increases ag ain, the watchdog is immediately activated, again using the maximum

watchdog time-out period. If the watchdog OFF option is selected during Standby mode,

the last used watchdog period will define the time for the supply current to fall below the

current detection threshold. This allows the user to align the current supervisor function to

the application needs.

Generally, the microcontroller can be activated from Standby mode via a system reset or

via an interrupt without reset. This allows implementation of differentiated start-up

behavior from Standby mode, depending on the application needs:

•If the watchdog is still running during Standby mode, the watchdog can be used for

cyclic wake-up behavior of the system. A dedicated Watchdog Ti me-out Interrupt

Enable (WTIE) bit enables the microcontroller to decide whether to receive an

interrupt or a hardware reset upon overflow. The interrupt option will be cleared in

hardware automatically with each watchdog overflow to ensure that a failing main

routine is detected while the interrupt service still operates. So the application

software must set the interrupt beh avior each time before a standby cycle is entered.

•Any wake-up via the CAN-bus or the LIN-bus together with a local wake-up event will

force a system reset event or an interrupt to the microcontroller. So it is possible to

exit Standby mode without any system reset if required.

Product data sheet Rev. 06 — 9 March 2010 11 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

When an interrupt event occurs the application software has to read the Interrup t register

within tRSTN(INT). Otherwise a fail-safe system reset is forced and Start-up mode will be

entered. If the application has read out the Interrupt register within the specified time, it

can decide whether to switch into Normal mode via an SPI access or to stay in Standby

mode.

The following operations are possible from Standby mode:

•Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the

microcontroller is triggered periodically and checked for the correct response)

•Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;

the SBC provides info rm a tio n abou t th e re se t sou rce to allow different start

sequences after reset)

•Wake-up by activity on the CAN-bus or LIN-bus via an interrupt signal to the

microcontroller

•Wake-up by bus activity on the CAN-bus or LIN-bus via a reset signal

•Wake-up by increasi ng the mi croco n tro ller supply current without a reset signal

(where a stab le supply is needed for the microcontroller RAM contents to remain valid

and wake-up from an external application not connected to the SBC)

•Wake-up by increas ing the micr oco n troller supply current with a reset signal

•Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller

•Wake-up due to a falling edge at pin WAKE forcing a reset signal

6.2.6 Sleep mode

In Sleep mode the microcontroller power supply (V1) and the INH/LIMP controlled

external supplies are switched off entirely, resulting in minimum system power

consumption. In this mode, the watchdog runs in Time-out mode or is completely off.

Entering Sleep mode results in an immediate LOW level on pin RSTN, thus stopping any

operation of the mic ro co nt ro ller. The INH/LIMP output is floating in parallel and pin V1 is

disabled. Only pin SYSINH can remain active to support the V2 voltage supply; this

depends on the V2C bit. It is also po ssible for V3 to be On, Of f or i n Cyclic mode to supply

external wake- u p switc he s.

If the watchdog is not disabled in soft ware, it will continue to run and force a system reset

upon overflow of the prog rammed period time . The SBC enters Start-up mod e and pin V1

becomes active again. This behavior can be used for a cyclic wake-up from Sleep mode.

Depending on the application, the following operations can be selected from Sleep mode:

•Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed

periodically, the SBC provides information about the reset source to allow different

start sequences after reset

•Wake-up by activity on the CAN-bus, LIN-bus or falling edge at pin WAKE

•An overload on V3, only if V3 is in a cyclic or in continuously on mode

Product data sheet Rev. 06 — 9 March 2010 12 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.2.7 Flash mode

Flash mode can only be entered from Normal mode by entering a specific Flash mode

entry sequence. This fail-safe control sequence comprises three con secutive write

accesses to the Mode register, within the legal windows of the watchdog, using the

operating mode codes 111, 001 and 111 respectively. As a result of this sequence, the

SBC will enter Start-up mode and perform a system reset with the related reset source

information (bits RSS = 0110).

From Start-up mode the application software now has to en ter Flash mode within tWD(init)

by writing Operating Mode code 011 to the Mode register. This feeds back a successfully

received hardware reset (handshake between the SBC and the microcontroller). The

transition from Start-up mode to Flash mode is possible only once after completing the

Flash entry sequence.

The application can also decide not to enter Flash mode but to return to Normal mo de by

using the Operating Mode code 101 for handshaking. This erases the Flash mode entry

sequence.

The watchdog beha vior in Flash mode is similar to it s time- out behavior in Standby mode,

but Operating Mode code 111 must be used for serving the watchdog. If this code is not

used or if the wa tchdog overflows, the SBC immediately forces a reset and enters S t art-up

mode. Flash mode is properly exited using the Operating Mode code 110 (leave Flash

mode), which results in a system reset with the corresponding reset source information .

Other Mode register codes will cause a forced reset with reset source code ‘illegal Mode

6.3 On-chip oscillator

The on-chip oscillator provides the clock signal for all digital functions and is the timing

reference for the on-chip watchdog and the internal timers.

If the on-chip oscillator frequency is too low or the oscillator is not running at all, there is

an immediate transition to Fail-safe mode. The SBC will stay in Fail-safe mode until the

oscillator has recovered to its normal frequency and the system receives a wake-up

event.

6.4 Watchdog

The watchdog provides the following timing functions:

•Start-up mode; needed to give the software the op portunity to initialize the system

•Window mode; detects too early and too late accesses in Normal mode

•Time-out mode; detects a too late access, can also be used to restart or interrupt the

microcontroller from time to time (cyclic wake-up func tion )

•Off mode; fail-safe shut-down during operation thus preventing any blind spots in the

system supervision

The watchdog is clocked directly by the on-chip oscillator.

To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are

coded with redundant bits. Therefore, only certain codes are allowed for a proper

watchdog service.

Product data sheet Rev. 06 — 9 March 2010 13 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

The following corrupted watchdog accesses result in an immediate system reset:

•Illegal watchdog period coding; only ten different codes are valid

•Illegal operating mode coding; only six different codes are valid

Any microcontroller driven mode change is synchronize d with a watchdog access by

reading the mode information and the watchdog period information from the same

switching between different software modules.

6.4.1 Watchdog start-up behavior

Following any reset event the watchdog is used to monitor the ECU start-up procedur e. It

observes the behavior of the RSTN pin for any clamping condition or interrupted reset

wire. In case the watchdog is not properly served within tWD(init), another reset is forced

and the monitoring procedure is restarted. In case the watchdog is again not properly

served, the system enters Fail-safe mode (see also Figure 3, Start-up and Restart

modes).

6.4.2 Watchdog window behavior

Whenever the SBC enters Normal mo de, the Window mode of the watchdog is activated.

This ensures that the microcontroller operates within the required speed; a too fast as well

as a too slow operation will be detected. Watchdog triggering using the Window mode is

illustrated in Figure 4.

Fig 4. Watchdog triggering using Window mode

mce62

trigger window

trigger

window

too early

trigger

restarts

period

50 %

trigger

via SPI

trigger

via SPI

last

trigger point

earliest possible

trigger point

latest possible

trigger point

earliest

possible

trigger

point

latest

possible

trigger

point

too early

trigger restarts period

(with different duration if

desired)

period

100 %

50 % 100 %

new period

Product data sheet Rev. 06 — 9 March 2010 14 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

The SBC provides 10 dif ferent period timings, scalable with a 4-factor watchdog prescaler.

The period can be cha nged within any valid trigger window. Whenever the watchdog is

triggered within the window time, the timer will be reset to start a new period.

The watchdog window is defined to be between 50 % and 100 % of the nominal

programmed watchdog period. Any too early or too late watchdog access or wrong Mode

6.4.3 Watchdog time-out behavior

Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the

active watchdog operates in Time-out mode. The watchdog has to be triggered with i n the

actual programmed period time; see Figure 5. The T ime-ou t mode can be used to pr ovide

cyclic wake-up events to the host microcontroller from Standby and Sleep modes.

In S tan dby and in Flash mode the nominal periods can be changed with any SPI access to

the Mode register.

Any illegal watchdog trigger code results in an immediate system reset, entering Start-up

mode.

6.4.4 Watchdog OFF behavior

It is possible to switch the watchdog off completely In Standby and Sleep modes. For

fail-safe reasons this is only possible if the microcontroller has stopped program

execution. To ensure that there is no program execution, the V1 supply current is

monitored by the SBC while the watchdog is switched off.

When selecting the watchdog OFF code, the watchdog remains active until the

microcontroller supply curr ent has dropped b elow the current m onitoring thresh old IthL(V1).

After the supply current has dropped below the threshol d, the watchdog stops at the end

of the watchdog period. In case the supply current does not drop below the monitor ing

threshold, the watchdog stays active.

Fig 5. Watchdog triggering using Time-out mode

mce627

trigger

via SPI

earliest

possible

trigger

point

latest

possible

trigger

point

trigger restarts period

(with different duration if

desired)

new period

trigger range

trigger range time-out

time-out

period

Product data sheet Rev. 06 — 9 March 2010 15 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

If the microcont ro ller sup ply cu rr en t in cr ea se s ab ov e I thH(V1) while the watchdog is OFF,

the watchdog is restarted with the last used watchdog period time and a watchdog restart

interrupt is forced, if enabled.

In case of a direct mode change towards Standby mode with watchdog OFF selected, the

longest possible watchdog period is used. It should be noted that in Sleep mode V1

current monitoring is not active.

6.5 System reset

The reset function of the UJA1061 offers two signals to deal with reset events:

•RSTN; the global ECU system reset

•EN; a fail-safe global enable signal

6.5.1 RSTN pin

The system reset pin (RSTN) is a bidirectional input / output. Pin RSTN is active LOW

with selectable pulse length upon the following events; see Figure 3:

•Power-on (first battery connection) or VBAT42 below power-on reset thr eshold voltage

•Low V1 supply

•V1 current above threshold during Standby mode while watchdog OFF behavior is

selected

•V3 is down due to short-circuit condition during Sleep mode

•RSTN externally forced LOW, falling edge event

•Successful preparation for Flash mode completed

•Successful exit from Flash mode

•W ake-up from Standby mode via pins CAN, LIN or WAKE if programmed accordingly,

or any wake-up event from Sleep mode

•Wake-up event from Fail-safe mode

•Watchdog trigger failures (too early, overflow, wrong code)

•Illegal mode code via SPI applied

•Interrupt not served within tRSTN(INT)

All of these reset events have a dedicated reset source in the System Status register to

allow distinction be twe e n the di fferent even ts.

The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware

is properly reset. After the first battery connection, a short power- on reset of 1 ms is

provided after voltage V1 is present. Once started, the microcontroller can set the Reset

Length Control (RLC) bit within the System Configuration register; this allows the reset

pulse to be adjusted for future reset events. With this bit set, all reset events are

lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatica lly ( to 20 ms)

in Restart mode or Fail-safe mode. With this mechanism it is guaranteed that an

erroneously shortened reset pulse will restart any microcontroller, at least within the

second trial by using the long reset pulse.

Product data sheet Rev. 06 — 9 March 2010 16 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

The behavior of pin RSTN is illustrated in Figure 6. The duration of tRSTNL depends on the

setting of the RLC bit (defines the reset length). Once an external reset event is detected

the system controller enters the Start-up mode. The watchdog now starts to monitor pin

RSTN as illustrated in Figure 7. If the RSTN pin is not released in time then Fail-safe

mode is entered as shown in Figure 3.

Fig 6. Reset pin behavior

Fig 7. Reset timing diagram

VRSTN

power-up power-

down

under-

voltage

missing

watchdog

access

under-

voltage

spike

time

Vrel(UV)(V1)

Vdet(UV)(V1)

coa054

tRSTNL tRSTNL tRSTNL

001aad181

RSTN

externally

forced LOW

RSTN externally forced LOW

time

RSTN

RSTNL

WD(init)

RSTNL

WD(init)

Product data sheet Rev. 06 — 9 March 2010 17 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin

RSTN HIGH but pin RSTN level remains LOW for longer than tRSTN(CLT), the SBC

immediately enters Fail-safe mode since this indicates an application failure.

The SBC also detect s if pin RSTN is clamped HIGH. If the HIGH- l evel remain s on the pin

for longer than tRSTN(CHT) while pin RSTN is driven internally to a LOW-level by the SBC,

the SBC falls back immediately to Fail-safe mode since the microcontroller cannot be

reset any more. By ente ring Fail-safe mode, the V1 voltage regulator shuts down and the

microcontroller stops.

Additionally, chattering reset signals are handled by the SBC in such a way that the

system safely falls back to Fail-safe mode with the lowest possible power consumption.

6.5.2 EN output

Pin EN can be used to control external hardware such as power components or as a

general purpos e output if the system is run ning properly. Durin g all reset event s, when pin

RSTN is pulled LOW, the EN control bit will be cleared, pin EN will be pulled LOW and will

stay LOW after pin RSTN is released. In Normal mode and Flash mode of the SBC, the

microcontroller can set the EN control bit via the SPI. This results in releasing pin EN

which then returns to a HIGH-level.

6.6 Power supplies

6.6.1 BAT14, BAT42 and SYSINH

The SBC has two supply pins, pin BAT42 and pin BAT1 4. Pin BAT42 suppl ies most of the

SBC where pin BAT14 onl y supplies the linear volt age regulators and th e INH/LIMP output

pin. This supply architecture allows diff erent supply strategies including the use of

external DC-to-DC converters controlled by the pin SYSINH.

6.6.1.1 SYSINH output

The SYSINH output is a high- side switch from BAT42. It is acti vat ed whe ne ve r the SBC

requires supply voltage to pin BAT14, e.g. when V1 or V2 is on (see Figure 3 and

Figure 8). Otherwise pin SYSINH is floating. Pin SYSINH can be used to control e.g. an

external step-down voltage regulator to pin BAT14, to reduce power consumption in

low-power modes.

6.6.2 Voltage regulators V1 and V2

The UJA1061 has two independent voltage regula tors supplied out of the BAT14 pin.

Regulator V1 is intended to supply the microcontroller. Regulator V2 is reserved for the

CAN transceiver.

6.6.2.1 Voltage regulator V1

The V1 voltage is continuously monitored to provide the system reset signal when

undervoltage situations occur. Whenever the V1 voltage falls below one of the three

programmable thr esholds, a hardware reset is forced.

A dedicated V1 supply comparator (V1 Monitor) observes V1 for undervoltage events

lower than VUV(VFI). This allows the application to receive a supply warning interrupt in

case one of the lower V1 undervoltage reset thresholds is selected.

Product data sheet Rev. 06 — 9 March 2010 18 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

The V1 regulator is overload protected. The maximum outp ut current available from pin

V1 depends on the vol t age app lied at pin BAT14 (see Table 26). For thermal reasons, the

total power dissipation should be taken into accou nt.

6.6.2.2 Voltage regulator V2

V olt age regulator V2 provides a 5 V supply for the CAN transmitter. The pin V2 is intended

for the connection of external buffering capacitors.

V2 is controlled autonomously by the CAN transceiver control system and is activated on

any detected CAN-bus activity, or if the CAN transceiver is enabled by the application

microcontroller. V2 is short-circuit protected and will be disabled in case of an overload

situation. Dedicated bits in the System Diagnosis register and the Interrupt register

provide V2 status feedback to the application.

Besides the autonomous control of V2 there is a software accessible bit which allows

activation of V2 manually ( V2C). This allows V2 to be used for other ap plication purposes

when CAN is not actively used (e.g. while CAN is off-line). Generally, V2 should not be

used for other application hardware while CAN is in use.

If the regulator V2 is not able to start within the V2 clamped LOW time (> tV2(CLT)), or if a

short-circuit has been detected during an already activated V2, then V2 is disabled and

the V2D bit in the System Diagnosis register is cleared. Additionally the CTC bit in the

Physical Layer Control register is set and the V2C bit is cleared.

Reactivation of voltage regulator V2 can be done by:

•Clearing the CTC bit while CAN is in Active mode

•Wake-up via CAN while CAN is not in Active mode

•Setting the V2C bit

•When entering CAN Active mode

6.6.3 Switched battery output V3

V3 is a high-side switched BAT42-related output which is used to drive external loads

such as wake-up switches or relays. The features of V3 are as follows:

•Three application-controlled operating modes; On, Off and Cyclic.

•Two different cyclic modes allow the supply of external wake-up switches; these

switches are powered intermittently, th us reducing the system’s p ower consumption in

case a switch is continuously active; the wake-up input of the SBC is sync hr on ize d

with the V3 cycle time.

•The switch is protected against current overloads. If V3 is overloaded, pin V3 is

automatically disabled. The corresponding System Diagnosis register bit is reset and

an interrupt is forced (if enabled). During Sleep mode, a wake-up is forced and the

corresponding reset source code becomes available in the RSS bits of the System

Status register. This signals that the wake-up source via V3 supplied wake-up

switches has been lost.

Product data sheet Rev. 06 — 9 March 2010 19 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.7 CAN transceiver

The integrated fault-tolerant CAN transceiver of the UJA1061 is an advanced ISO11898-3

compliant transceiver and is interoperable with the TJA1054 and TJA1054A stand-alone

transceivers. In addition to standard fault-tolerant CAN transceivers the UJA1061

transceiver provides the following fe at ur es :

•Enhanced error handling and reporting of bus and RXD/TXD failures; these failures

are separately identifie d in the System Diagnosis register

•Integrated autonomous control system for determining the mode of the CAN

transceiver

•Ground shift detection with two selectable warning levels, to detect possible local

ground problems before the CAN communication is affected

•On-line Listen mode with global wake-up message filter allows partial networking

•Bus connections are truly floating when power is off

6.7.1 Mode control

The controller of the CAN transceiver provides four modes of operation: Active mode,

On-line mode, On-line Listen mode and Off-line mode; see Figure 8.

Product data sheet Rev. 06 — 9 March 2010 20 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

In the System Diagnosis register two dedicated CAN st atus bits (CANMD) are availa ble to

signal the mode of the transceiver.

6.7.1.1 Active mode

In Active mode the CAN transceiver can transmit data to and receive data from the CAN

bus. To enter Active mode the CMC bit must be set in the Physical Layer Control register

and the SBC must be in No rmal mode or Flash mode . In Active mode voltage regulator V2

is activated automatically.

The CTC bit can be used to set the CAN transceiver to a Listen-only mode. The

transmitter output stage is disabled in this mode.

After an overloa d condition on volt age regulator V2, the CTC bit must be cleared for

reactivating the CAN transmitter.

Fig 8. States of the CAN transceiver

001aaf003

On-line mode

V2 : ON/OFF (V2D)

transmitter: OFF

RXDC: wake-up (active LOW)

CANL bias V2/floating/(V2D)

CPNC = 0

Off-line mode

V2 : ON/OFF (V2C/V2D)

transmitter: OFF

RXDC: V1

CANL bias BAT42/floating/(V2D)

CPCN = 0 or 1

On-line Listen mode

V2 : ON/OFF (V2D)

transmitter: OFF

RXDC: V1

CANL bias V2/floating/(V2D)

CPCN = 1

Active mode

V2 : ON/OFF (V2D)

transmitter: ON/OFF (CTC)

RXDC: bit stream/HIGH (V2D)

CANL bias V2/floating/(V2D)

CPNC = 0 or 1

CMC = 0 AND CPNC = 0

CAN wake-up filter passed

AND CPNC = 1

no activity for t > toff-line

CPNC = 1

global wake-up message detected

OR CPNC = 0

power-on

CMC = 1

CMC = 0 AND CPNC = 1

SBS enters

Normal or

Flash mode

AND CMC = 1

CAN wake-up filter passed

AND CPNC = 0

Product data sheet Rev. 06 — 9 March 2010 21 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

When leaving Active mode the CAN transmitter is disabled and the CAN receiver is

monitoring the CAN-bus for a valid wake-up. The CAN termination is then working

autonomously.

6.7.1.2 On-line mode

In On-line mode the CAN b us pins and RTL and RTH p ins are biased to the norma l levels.

The CAN transmitter is deactivated and RXDC reflects the CAN wake-up status. A CAN

wake-up event is signalled to the microcontroller by setting pin RXDC to LOW.

If the bus stays continuously dominant or recessive for the Off-line time (toff-line), the

Off-line state will be entered.

6.7.1.3 On-line Listen mode

On-line Listen mode b ehaves similar to On-line mode, bu t all activity on the CAN-bu s, with

exception of a special global wake-up request, is ignored. The global wake-up request is

described in Section 6.7.2. Pin RXDC is kept HIGH.

6.7.1.4 Off-line mode

Off-line mode is the low-power mode of the CAN transceiver. The CAN transceiver is

disabled to save supply current and is high-ohmic terminated to ground.

The CAN off-line time is programmable in two steps with the CAN Off-line Timer Control

(COTC) bit. When entering On-line (Listen) mode from Of f-line mode the CAN off-line time

is temporarily extended to toff-line(ext).

6.7.2 CAN wake-up

To wake-up the UJA1061 via CAN it has to be distinguished between a conventional

wake-up and a global wake-up in case partial networking is enabled (bit CPNC = 1).

To pass the wake-up filter for a conventional wake-up a dominant, recessive, dominant

signal on the CAN-bus is needed.

For a global wake-up out of On-line Listen mode two distinct CAN data patterns are

required (shown in hexadecimal code here):

•In the Initial message: C6EE EEEE EEEE EEEF

•In the Global wake-up message: C6EE EEEE EEEE EE37

The second pa ttern must be received within ttimeout after receiving the first pattern. Any

CAN-ID can be used with these data pattern s.

If the CAN transceiver enters On-line Listen mode directly from Off-line mode the global

wake-up message is sufficient to wake-up the SBC. This pattern must be received within

ttimeout after entering On-line Listen mode. Should ttimeout elapse before receiving the

global wake-up message, then both messages are required for a CAN wake-up.

6.7.3 Termination control

In Active mode, On-line mode and On-line Listen mode, CANH is terminated to GND and

CANL is terminated to pin V2 via the external termination resistors applied to RTH and

RTL. In case of detected bus failures, the termination changes according to the ISO

11898-3 sta ndard. In Off-line mode pin CANH st ays termin ated to GND but with a d iode in

Product data sheet Rev. 06 — 9 March 2010 22 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

between (reverse supply protection) while pin CANL becomes terminated to pin BAT42

(via pin RTH and pin RTL). If pin V2 is disabled due to an overload condition RTH and

RTL become floating.

6.7.4 Bus, RXD and TXD failure detection

The UJA1061 can distinguish between bus, RXD and TXD failures as indicated in Table 3.

All failures are signalled separately in the CANFD bits in the System Diagnosis register.

Any change (detection and recovery) forces an interrupt to the microcontroller, if this

interrupt is enabled.

[1] CANL stays active with weak short-circuits to BAT due to wake-up requirements within large networks.

6.7.4.1 T XDC do mi na n t cla mp in g

If the TXDC pin is clamped dominant for longer than tTXDC(dom) the CAN transmitter is

disabled. After the TXDC pin becomes recessive the transmitter is reactivated

automatically when detecting bus activity or manually by setting and clearing the CTC bit.

6.7.4.2 RXDC recessive clamping

If the RXDC pin is clamped recessive while the CAN bus is dominant the CAN transmitter

is disabled. The transmitter is reactivated automatically when RXDC becomes dominant

or manually by setting and clearing the CTC bit.

Table 3. CAN-bus, RXD and TXD failure detection

Failure Description Driver and biasing circuit

disabling

HxVCC CANH to VCC (5 V) short-circuit CANH off, weak RTH

HxBAT CANH to BAT (14 V and 42 V) short-circuit CANH off, weak RTH

HxGND CANH to GND short-circuit none

LxBAT CANL to BAT (14 V and 42 V) short-circuit CANL off, weak RTL[1]

LxGND CANL to GND short-circuit CANL off, weak RTL

LxVCC CANL to VCC (5 V) short-circuit none

HxL CANH to CANL short-circuit CANL off, weak RTL

H// CANH interrupted none

L// CANL interrupted none

Bus Dom bus is continuously clamped dominant

(double failure); even with in Single-wire

mode the receiver remains dominant

CANL off, weak RTL

Bus Rec bus is continuously clamped recessive

(double failure); driving messages to the bus

is not possible even while the driver is active

none

TxDC Dom pin TXDC is continuously clamped dominant

(handles also RXDC to TXDC short-circuits) transmitter disabled but no change in

biasing

RxDC Rec pin RXDC is continuously clamped recessive transmitter disabled but no change in

biasing

RxDC Dom pin RXDC is continuously clamped dominant none

Product data sheet Rev. 06 — 9 March 2010 23 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.7.4.3 GND shift detection

The SBC can detect ground sh ifts in reference to the CAN bus. Two different ground shift

detection levels can be selected with the GSTH C bit in the System Configuration register.

The failure can be read out in the System Diagnosis register. Any detected or recovered

GND shift event is signalled with an interrupt, if enabled.

6.8 LIN transceiver

The integrated LIN transceiver of the UJA1061 is a LIN 2.0 compliant transceiver. The

transceiver has th e follo win g fe at ur es :

•SAE J2602 compliant and compatible with LIN revision 1.3

•Fail-safe LIN termination to BAT42 via dedicated RTLIN pin

•Enhanced error handling and reporting of bus and TXD failures; th ese failures are

separately identified in the System Diagnosis register

6.8.1 Mode control

The controller of the LIN transceiver provides two modes of operation: Active mode and

Off-line mode; see Figure 9. In Off- line mode the transmitter a nd receiver do not consume

current, but wake-up events will be recognized by the separate wake-up receiver.

6.8.1.1 Active mode

In Active mode the LIN transceiver can transmit data to and receive dat a from the LIN bus.

To enter Active mode the LMC bit must be set in the Physical Layer Control register and

the SBC must be in Normal mode or Flash mode.

Fig 9. States LIN transceiver

001aad1

power-on

Active mode

transmitter: ON/OFF (LTC)

receiver: ON

RXDL: bitstream

RTLIN: ON/75 μA

Off-line mode

transmitter: OFF

receiver: wake-up

RXDL: wake-up status

RTLIN: 75 μA/OFF

SBC enters

Stand-by, Start-up,

Restart or Fail-safe mode

OR LMC = 0

SBC enters

Normal or Flash mode

AND LMC = 1

SBC enters

Fail-safe mode

Product data sheet Rev. 06 — 9 March 2010 24 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

The LTC bit can be used to se t th e L IN transcei ver to a L isten -o nly mode. Th e tra nsmitter

output stage is disabled in this mode.

When leaving Active mode the LIN transmitter is disabled and the LIN receiver is

monitoring the LIN-bus for a valid wake-up.

6.8.1.2 Off-line mode

Off-line mode is the low power mode of the LIN transceiver. The LIN transceiver is

disabled to save supply cu rre n t. Pin RXDL ref lects any wake-up event at the LI N-b u s.

6.8.2 LIN wake-up

For a remote wake-up via LIN a LIN-b us signal is required as shown in Figure 10.

6.8.3 Termination control

The RTLIN pin is in one of 3 different states: RTLIN = on, RTLIN = off or RTLIN = 75 μA;

see Figure 11.

During Active mode, with no short-circuit between the LIN-bus and GND, pin RTLIN

provides an internal switch to BAT42. For master and slave operation an external resistor ,

1kΩ or 30 kΩ respectively, can be applied between pins RTLIN and LIN. An external

diode in series with the termination resistor is not required due to the incorpor ated internal

diode.

Fig 10. LIN wake-up timing diagram

001aad44

tBUS(LIN)

LIN

wake-up

Product data sheet Rev. 06 — 9 March 2010 25 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.8.4 LIN slope control

The LSC bit in the Physical Layer Control register offers a choice between two LIN slope

times, allowing communication up to 20 kbit/s (normal) or up to 10.4 kbit/s (low slope).

6.8.5 LIN driver capability

Setting the LDC bit in the Physical Layer Control register will increase the driver capability

of the LIN output stage. This feature is used in auto-addressing systems, where the

standard LIN 2.0 drive capability is insufficient.

6.8.6 Bus and TXDL failure detection

The SBC handles and reports the following LIN-bus related failures:

•LIN-bus shorted to ground

•LIN-bus shorted to VBAT14 or VBAT42; the transmitter is disabled

•TXDL clamped dominant; the transmitter is disabled

These failure event s force an interrupt to the microcontroller whenever the status ch anges

and the corresponding interrupt is enabled.

6.8.6.1 TXDL dominant clamping

If the TXDL pin is clamped dominant for longer than tTXDL(dom)(dis) the LIN transmitter is

disabled. After the TXDL pin becomes recessive the transmitter is reactivated

automatically when detecting bus activity or manually by setting and clearing the LTC bit.

6.8.6.2 LIN dominant clamping

When the LIN-bus is clamped dominant for longer than tLIN(dom)(det) (which is longer than

tTXDL(dom)(dis)), the state of the LIN termination is changed accordin g to Figure 11.

Fig 11. States of the RTLIN pin

001aad183

RTLIN = OFF

power-on

RTLIN = ON

supplied directly

out of BAT42

RTLIN = 75 μA

supplied directly

out of BAT42

Off-line mode

AND receiver dominant > tLIN(dom)(det)

Off-line mode

AND receiver recessive > tLIN(dom)(rec)

Active mode and receiver recessive > tLIN(dom)(rec)

OR mode change to Active mode

Active mode and receiver dominant > tLIN(dom)(det)

OR Off-line mode

mode change to Active mode

Product data sheet Rev. 06 — 9 March 2010 26 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.8.6.3 LIN recessive clamping

If the LIN bus pin is clamped recessive wh ile TXDL is driven dominant the LIN transmitter

is disabled. The transmitter is reactivated automatically when the LIN bus becomes

dominant or manually by setting and clearing the LTC bit.

6.9 Inhibit and limp-home output

The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for

an extra (external) voltage regulator, or as a ‘limp-home’ output. The pin is controlled via

the ILEN bit and ILC bit in the System Configuration register; see Figure 12.

When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a

default LOW level. The pin can be set to HIGH according to the state di agram.

When pin INH/LIMP is used as limp-home output, a pull-up resistor to VBAT42 ensures a

default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe

mode.

6.10 Wake-up input

The W AKE input compar ator is triggered by negative edges on pin WAKE. Pin W AKE has

an internal pull- up resistor to BAT42. It can be operated in two sampling modes which ar e

selected via the WAKE Sample Control bit (WSC):

•Continuous sampling (with an internal clock) if the bit is set

•Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see Figure 13.

This is to save bias current within the external switches in low-power operation. Two

repetition times are possible, 16 ms an d 32 ms.

Fig 12. States of the INH/LIMP pin

001aad178

INH/LIMP:

HIGH

ILEN = 1

ILC = 1

INH/LIMP:

floating

ILEN = 0

ILC = 1/0

ILEN = 1

ILC = 0

INH/LIMP:

LOW

state change via SPI

OR enter Fail-safe mode

state change via SPI

OR (enter Start-up mode after

wake-up reset, external reset

or V1 undervoltage)

OR enter Restart mode

OR enter Sleep mode

state change via SPI

power-on

state change via SPI

OR enter Fail-safe mode

Product data sheet Rev. 06 — 9 March 2010 27 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

If V3 is continuously ON, the WAKE input will be sampled continuously, regardless of the

level of bit WSC.

The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the

System Status register reflect the actual status of pin WAKE. The WAKE port can be

disabled by clearing the WEN bit in the System Configuration register.

6.11 Interrupt output

Pin INTN is an open-drain interrupt output. It is forced LOW whenever at least one bit in

the Interrupt register is set. By reading the Interrupt register all bits are cleared. The

Interrupt register will also be cleared during a system reset (RSTN LOW).

As the microcontroller operates typically with an edge-sensitive interrupt port, pin INTN

will be HIGH for at least tINTN after each read- out of the Interrupt register. Without further

interrupts within tINTN pin INTN stays HIGH, otherwise it will revert to LOW again.

To prevent the microcontroller from being slowed down by repetitive interrupts, in Norma l

mode some interr up ts are only allo we d to oc cu r on ce per watchd og per iod ; se e

Section 6.13.7.

If an interrupt is not read out within tRSTN(INT) a system reset is performed.

6.12 Temperature protection

The temperature of the SBC chip is monitored as long as the microcontroller voltage

regulator V1 is active. To avoid an unexpected shutdown of the applic at ion by the SB C,

the temperature protection will not switch-off any part of the SBC or activate a defined

system stop of its own accord. If the temperature is too high it generates an inter rupt to

the microcontroller (μC), if enabled, and the corresponding status bit will be set. The

microcontroller can then decide whether to switch-off parts of the SBC to decrease the

chip temperature.

Fig 13. Pin WAKE, cyclic sampling via V3

sample

active

VWAKE

flip flop

VINTN

ton(CS)

tw(CS)

tsu(CS) approximately 70 %

signal already HIGH

due to biasing (history)

signal remains LOW

due to biasing (history)

button pushed button released

001aac30

Product data sheet Rev. 06 — 9 March 2010 28 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.13 SPI interface

The Serial Peripheral Interface (SPI) provides the communication link with the

microcontroller, supporting multi-slave and multi-master operation. The SPI is configured

for full duplex data transf er, so status information is return ed whe n ne w contr ol da ta is

shifted in. The interface also offers a read -only access option, allowing registers to be

read back by the application without changing the register content.

The SPI uses four interface signals for synchronization and data transfer:

•SCS - SPI chip select; active LOW

•SCK - SPI clock; default level is LOW due to low-power concept

•SDI - SPI data input

•SDO - SPI data output; floating when pin SCS is HIGH

Bit sampling is performed on the falling clock edge and data is shif ted on the rising clock

edge; see Figure 14.

To protect against wrong or illegal SPI instructions, the SBC detects the following SPI

failures:

•SPI clock count failure (wrong number of clock cycles during one SPI access): only

16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock

cycles results in an SPI failure interrupt, if enabled . The access is ignored by the SBC.

In Start-up and Restart mode a reset is forced instead of an interrupt

•Forbidden mode changes according to Figure 3 result in an immediate system reset

•Illegal Mode register code. Undefined operating mode or watchdog period coding

results in an immediate system reset; see Section 6.13.3

6.13.1 SPI register mapping

Any control bit which can be set by software is readable by the application. This allows

software deb ugging as well as control algorithms to be implemented.

Watchdog serving and mode setting is performed within the same access cycle; this only

allows an SBC mode change whilst serving the watchdog.

Fig 14. SPI timing prot oc ol

SCS

SCK 01

sampled

floating floating

mce6

MSB 14 13 12 01 LSB

SDI

SDO

02 03 04 15 16

Product data sheet Rev. 06 — 9 March 2010 29 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Each register carries 12 data bits; the other 4 bits are used for register selection and

read/write definition.

6.13.2 Register overview

The SPI interface gives access to all SBC registers; see Table 4. The first two bit s (A1 and

A0) of the message header define the register address, the third bit is the read register

select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO)

allows ‘read only’ access to one of the feedback registers. Which of the SBC registers can

be accessed also depends on the SBC operating mode.

6.13.3 Mode register

In the Mode register the watchdog is defined and re-triggered, and the SBC operating

mode is selected. The Mode register also contains the global enable output bit (EN) and

the Software Development Mode (SDM) control bit. During system operation cyclic

access to the Mode register is requ ired to serve the watchdog. This regi ster can be written

to in all modes.

At system start-up the Mode register must be written to within tWD(init) from releasing

RSTN (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and

system mode coding. If an illegal code is detected, access is ignored by the SBC and a

system reset is forced in accordance with the state diagram of the system controller; see

Figure 3.

Table 4. Register overview

address bits

(A1, A0)

Operating

mode Write access (RO = 0) Read access (RO = 0 or RO = 1)

Read Register Select

(RRS) bit = 0 Read Register Select

(RRS) bit = 1

00 all modes Mode register System Status register System Diagnosis register

01 Normal mode;

St andby mode;

Flash mode

Interrupt Enable register Interrupt Enable Feedback

Start-up mode ;

Restart mode Special Mode register Interrupt Enable Feedback

10 Normal mode;

Standby mode System Configuration

Feedback register General Purpose Feedback

Start-up mode ;

Restart mode;

Flash mode

General Purpose register 0 System Configuration

Feedback register General Purpose Feedback

11 Normal mode ;

Standby mode Physical Layer Control

Feedback register General Purpose Feedback

Start-up mode ;

Restart mode;

Flash mode

General Purpose register 1 Physical Layer Control

Feedback register General Purpose Feedback

Product data sheet Rev. 06 — 9 March 2010 30 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

[1] Flash mode can be entered only with the watchdog service sequence ‘Normal mode to Flash mode to Normal mode to Flash mode’,

while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up

mode to prepare the microcontroller for flash memory download. The four RSS bits in the System S t atus register reflect the reset source

information, confirming the Flash entry sequence. By using the Initializing Flash mode (within tWD(init) after system reset) the SBC will

now successfully enter Flash mode.

[2] See Section 6.14.1.

Table 5. Mode register bit description (bits 15 to 12 and 5 to 0)

Bit Symbol Description Value Function

15 and 14 A1, A0 register address 00 select Mode register

13 RRS Read Register

Select 1 read System Diagnosis register

0 read System Status register

12 RO Read Only 1 read selected register without writing to Mode register

0 read selected register and write to Mode register

11 to 6 NWP[5:0] see Table 6

5 to 3 OM[2:0] Operating Mode 001 Normal mode

010 Standby mode

011 initialize Flash mode[1]

100 Sleep mode

101 initialize Normal mode

110 leave Flash mode

111 Flash mode[1]

2 SDM Software

Development

Mode

1 Software Development mode enabled[2]

0 normal watchdog, interrupt, reset monitoring and fail-safe

behavior

1 EN Enable 1 EN outp ut pin HIGH

0 EN output pin LOW

0 - reserved 0 reserved for future use; should remain cleared to ensure

compatibility with future functi ons which might use this bit

Table 6. Mode register bit description (bits 11 to 6)[1]

Bit Symbol Description Value Time

Normal

mode (ms) Standby

mode (ms) Flash mode

(ms) Sleep mode

(ms)

11 to 6 NWP[5:0] Nominal

Watchdog Period

WDPRE = 00 (as

set in the S pecial

Mode register)

00 1001 4 20 20 160

00 1100 8 40 40 320

01 0010 16 80 80 640

01 0100 32 160 160 1024

01 1011 40 320 320 2048

10 0100 48 640 640 3072

10 1101 56 1024 1024 4096

11 0011 64 2048 2048 6144

11 0101 72 4096 4096 8192

11 0110 80 OFF[2] 8192 OFF[3]

Product data sheet Rev. 06 — 9 March 2010 31 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

[1] The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for fosc = 512 kHz.

[2] See Section 6.4.4.

[3] The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is

immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry

without dips on V1; see Section 6.4.4.

11 to 6 NWP[5:0] Nominal

Watchdog Period

WDPRE = 01 (as

set in the S pecial

Mode register)

00 1001 6 30 30 240

00 1100 12 60 60 480

01 0010 24 120 120 960

01 0100 48 240 240 1536

01 1011 60 480 480 3072

10 0100 72 960 960 4608

10 1101 84 1536 1536 6144

11 0011 96 3072 3072 9216

11 0101 108 6144 6144 12288

11 0110 120 OFF[2] 12288 OFF[3]

Nominal

Watchdog Period

WDPRE = 10 (as

set in the S pecial

Mode register)

00 1001 10 50 50 400

00 1100 20 100 100 800

01 0010 40 200 200 1600

01 0100 80 400 400 2560

01 1011 100 800 800 5120

10 0100 120 1600 1600 7680

10 1101 140 1560 1560 10240

11 0011 160 5120 5120 15360

11 0101 180 10240 10240 20480

11 0110 200 OFF[2] 20480 OFF[3]

Nominal

Watchdog Period

WDPRE = 1 1 (as

set in the S pecial

Mode register)

001001 14 70 70 560

001100 28 140 140 1120

010010 56 280 280 2240

010100 112 560 560 3584

011011 140 1120 1120 7168

100100 168 2240 2240 10752

101101 196 3584 3584 14336

110011 224 7168 7168 21504

110101 252 14336 14336 28672

110110 280 OFF[2] 28672 OFF[3]

Table 6. Mode register bit description (bits 11 to 6)[1] …continued

Bit Symbol Description Value Time

Normal

mode (ms) Standby

mode (ms) Flash mode

(ms) Sleep mode

(ms)

Product data sheet Rev. 06 — 9 March 2010 32 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.13.4 System Status register

This register allows sta tus information to be read back from the SBC. This register ca n be

read in all modes.

Table 7. System Status register bit descriptio n

Bit Symbol Description Value Function

15 and 14 A1, A0 regi ster address 00 read System Status register

13 RRS Read Register Select 0

12 RO Read Only 1 read System Status register without writing to Mode

0 read System Status register and write to Mode register

11 to 8 RSS[3:0] Reset Source[1] 0000 power-on reset; first connection of BAT42 or BAT42 below

power-on voltage threshold or RSTN was forced LOW

externally

0001 cyclic wake-up out of Sleep mode

0010 low V1 supply; V1 has dropped below the selected reset

threshold

0011 V1 current above threshold within Standby mode while

watchdog OFF behavior and reset option (V1CMC bit) are

selected

0100 V3 voltage is down due to overload occurring during Sleep

mode

0101 SBC successfully left Flash mode

0110 SBC ready to ente r Flash mode

0111 CAN wake-up event

1000 LIN wake-up event

1001 local wake-up event (via pin WAKE)

1010 wake-up out of Fail-safe mode

1011 watchdog overflow

1100 watchdog not initialized in time; tWD(init) exceeded

1101 watchdog triggered too early; window missed

1110 illegal SPI access

1111 interrupt not served within tRSTN(INT)

7 CWS CAN Wake-up Status 1 CAN wake-up detected; cleared upon read

0 no CAN wake-up

6 LWS LIN Wake-up Status 1 LIN wake-up detected; cleared upon read

0 no LIN wake-up

5 EWS Edge Wake-up Status 1 pin WAKE negative edge detected; clea red upon read

0 pin WAKE no edge detected

4 WLS WAKE Level Status 1 pin WAKE above threshold

0 pin WAKE below threshold

3 TWS Temperature Warning

Status 1 chip temperature exceeds the warning limit

0 chip temperature is below the warning limit

2 SDMS Software Development

Mode Status 1 Software Development mode on

0 Software Development mode off

Product data sheet Rev. 06 — 9 March 2010 33 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

[1] The RSS bits are updated with each reset event and not cleared. The last reset event is captured.

6.13.5 System Diagnosis register

This register allows diagnosis informatio n to be read back from the SBC. This register can

be read in all modes.

1 ENS Enable status 1 pin EN output activated (V1-related HIGH level)

0 pin EN output released (LOW level)

0 PWONS Power-on reset Status 1 power-o n reset; cleared after a successfully entered

Normal mode

0 no power-on reset

Table 7. System Status register bit descriptio n …continued

Bit Symbol Description Value Function

Table 8. System Diagnosis register bit description

Bit Symbol Description Value Function

15 and 14 A1, A0 regi ster address 00 read System Diagnosis register

13 RRS Read Register Select 1

12 RO Read Only 1 read Syste m Diagnosis register without writing to Mode

0 read System Diagnosis register and write to Mode register

11 GSD Ground Shift Diagnosis 1 system GND shift is outside selected threshold

0 system GND shif t is w it hin selected threshold

10 to 7 CANFD

[3:0] CAN failure diagnosis 1111 TXDC is clamped dominant

1110 RXDC is clamped dominant

1100 BUS is clamped dominant (dual failure situation)

1101 RXDC is clamped recessive

1011 BUS is clamped recessive (dual failure situation)

1010 reserved

1001 CANH is shorted to CANL (failure case 7)

1000 CANL is shorted to VCC (failure case 6a)

0111 CANL is shorted to VBAT (failure case 6)

0110 CANH is shorted to GND (failure case 5)

0101 CANL is shorted to GND (failure case 4)

0100 CANH is shorted to VCC (failure case 3a)

0011 CANH is shorted to VBAT (failure case 3)

0010 CANL wire is interrupted (failure case 2)

0001 CANH wire is interrupted (failure case 1)

0000 no failure

6 and 5 LINFD[1 :0] LIN failure diagnosis 11 TXDL is clamped dominant

10 LIN is shorted to GND (do mi n ant clamped)

01 LIN is shorted to VBAT (recessive clamped)

00 no failure

4 V3D V3 diagnosis 1 OK

0 fail; V3 is disabled due to an overload situation

Product data sheet Rev. 06 — 9 March 2010 34 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

[1] V2D will be set when V2 is reactivated after a failure. See Section 6.6.2.2.

6.13.6 Interrupt Enable register and Interrupt Enable Feedback register

These registers allow setting, clearing and reading back the interrupt enable bits of the

SBC.

3 V2D V2 diagnosis 1 OK [1]

0 fail; V2 is disabled due to an overload situation

2 V1D V1 diagnosis 1 OK; V1 always above VUV(VFI) since last read access

0 fail; V1 was below VUV(VFI) since last read access; bit is set

again with read access

1 and 0 CANMD

[1:0] CAN Mode Diagnosis 11 CAN is in Active mode

10 CAN is in On-line mode

01 CAN is in On-line Listen mode

00 CAN is in Off-line mode, or V2 is not active

Table 8. System Diagnosis register bit description …continued

Bit Symbol Description Value Function

Table 9. Interrupt Enable register and Interrupt Enable Feedb ack register bit description

Bit Symbol Description Value Function

15 and 14 A1, A0 regi ster address 01 select the Interrupt Enable register

13 RRS Read Register Select 1 read the Interrupt register

0 read the Interrupt Enable Feedback register

12 RO Read Only 1 r ead the register selected by RRS without writing to

Interrupt Enable register

0 read the register selected by RRS and write to Interrupt

Enable register

11 WTIE Watchdog Time-out

Interrupt Enable[1] 1 a watchdog overflow during Standby causes an interrupt

instead of a reset event (interrupt based cyclic wake-up

feature)

0 no interrupt forced on watchdog overflow; a reset is forced

instead

10 OTIE Over-Temperature

Interrupt Enable 1 exceeding or dropping below the temperature warning limit

causes an interrupt

0 no interrupt forced

9 GSIE Ground Shift Interrupt

Enable 1 exceeding or dropping below the GND shift limit causes an

interrupt

0 no interrupt forced

8 SPIFIE SPI clock count Failure

Interrupt Enable 1 wrong number of CLK cycles (more than, or less than 16)

forces an interrupt; from S t art-up mode and Restart mode a

reset is performed instead of an interrupt

0 no interrup t forced; SPI access is ignored if the number of

cycles does not equal 16

7 - reserved 0 should always be set to logic 0

6 VFIE V olt age Failure Interrupt

Enable 1 clearing of V1D, V2D or V3D forces an interrupt

0 no interrupt forced

Product data sheet Rev. 06 — 9 March 2010 35 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

[1] This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required

(fail-safe behavior).

[2] WEN (in the System Configuration register) has to be set to activate the WAKE port function globally.

6.13.7 Interrupt register

The Interrupt register allows the cause of an interrupt event to be read. The register is

cleared upon a read access and upon any reset event. Hardware ensures that no interrupt

event is lost in case there is a new in terrupt forced while re ading the register. After reading

the Interrupt register pin INTN is released for tINTN to guarantee an edge event at pin

INTN.

The interrupts can be classified into two groups:

•Timing critical interrupts which require immediate reaction (SPI clock count failure

which needs a new SPI command to be resent immediately, and a BAT failure which

needs critical data to be saved immediately into the nonvolatile memory)

•Interrupts which do not require an immediate reaction (overtemperature , Ground Shift,

CAN and LIN failures, V1, V2 and V3 failures and the wake-ups via CAN, LIN and

WAKE. These interrupts will be signalled in Normal mode to the microcontroller once

per watchdog period (maximum); this prevents overloading the microcontroller with

unexpected interrupt events (e.g. a chattering CAN failure). However , these interrupts

are reflected in the Interrupt re gist er

5 CANFIE CAN Failure Interrupt

Enable 1 any change of the CAN Failure status bits forces an

interrupt

0 no interrupt forced

4 LINFIE LIN Failure Interrupt

Enable 1 any change of the LIN Failure status bits forces an interrupt

0 no interrupt forced

3 WIE WAKE Interrupt

Enable[2] 1 a negative edge at pin WAKE generates an interrupt in

Normal mode, Flash mode or Standby mode

0 a negative edge at pin W AKE generates a reset in Standby

mode; No interrupt in any other mode

2 WDRIE Watchdog Restart

Interrupt Enable 1 a watchdog restart during watchdog OFF generates an

interrupt

0 no interrupt forced

1 CANIE CAN Interrupt Enable 1 CAN-bus event results in a wake-up interrupt in Standby

mode and in Normal or Flash mode (unless CAN is in

Active mode alre a dy)

0 CAN-bus even t results in a reset in Standby mode; No

interrupt in any other mode

0 LINIE LIN Interrupt Enable 1 LIN-bus event results in a wake-up interrupt in Standby

mode and in Normal or Flash mode (unless LIN is in Active

mode already)

0 LIN-bus event results in a reset in Standby mode; no

interrupt in any other mode

Table 9. Interrupt Enable register and Interrupt Enable Feedb ack register bit description …continued

Bit Symbol Description Value Function

Product data sheet Rev. 06 — 9 March 2010 36 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Table 10. Interrupt regis t er bit desc ription

Bit Symbol Description Value Function

15 and 14 A1, A0 register address 01 read Interrupt register

13 RRS Read Register Select 1

12 RO Read Only 1 read the Inte rrupt register without writing to the Interrupt

Enable register

0 read the Interrupt register and write to the Interrupt Enable

11 WTI Watchdog Time-out

Interrupt 1 a watchdog overflow during Standby mode has caused an

interrupt (interrupt-based cyclic wake-up feature)

0 no interrupt

10 OTI OverTemperature

Interrupt 1 the temperature warning status (TWS) has changed

0 no interrupt

9 GSI Ground Shift Interrupt 1 the ground shift diagnosis bit (GSD) has changed

0 no interrupt

8 SPIFI SPI clock count Failure

Interrupt 1 wrong number of CLK cycles (more than, or less than 16)

during SPI access

0 no interrup t; SPI access is ignore d if the number of CLK

cycles does not equal 16

7 - reserved 0 should always be set to logic 0

6 VFI Voltage Failure Interrupt 1 V1D, V2D or V3D has been clea red

0 no interrup t

5 CANFI CAN Failure Interrupt 1 CAN failure status has changed

0 no interrupt

4 LINFI LIN Failure Interrupt 1 LIN failure status has changed

0 no interrupt

3 WI Wake-up Interrupt 1 a negative edge at WAKE has been detected

0 no interrupt

2 WDRI Watchdog Restart

Interrupt 1 A watchdog restart during watchd og OFF has caused an

interrupt

0 no interrup t

1 CANI CAN Wake-u p In te rru p t 1 CAN wake-up ev en t ha s cau se d an int err up t

0 no interrupt

0 LINI LIN Wake-up Interrupt 1 LIN wake-up event has caused an interrupt

0 no interrupt

Product data sheet Rev. 06 — 9 March 2010 37 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.13.8 System Configuration register and System Configuration Feedback register

These registers allow configuration of the behavior of the SBC, and allow the settings to

be read back.

[1] RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure

situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached.

[2] If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and WLS within the System Status register .

Table 1 1. System Configuration register and System Configuration Feed back register bit description

Bit Symbol Description Value Function

15 and 14 A1, A0 register address 10 select System Configuration register

13 RRS Read Register Select 1 read the General Purp ose Feedback register 0

0 read the System Configuration Feedback register

12 RO Read Only 1 read register selected by RRS without writing to System

Configuration register

0 read register selected by RRS and write to System

Configuration register

11 and 10 - reserved 0 reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

9 GSTHC GND Shift Threshold

Control 1V

det(GSD)(CANH) widened threshold

det(GSD)(CANH) normal threshold

8 RLC Reset Length Control 1[1] tRSTNL long reset lengthening time selected

RSTNL short reset lengthening time selected

7 and 6 V3C[1:0] V3 Control 11 Cyclic mode 2; tw(CS) long period; see Figure 13

10 Cyclic mode 1; tw(CS) short perio d; see Figure 13

01 continuously ON

00 OFF

5 - reserved 0 reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

4 V1CMC V1 Current Monitor

Control 1 an increasing V1 current causes a reset if the watchdog

was disabled during Standby mode

0 an increa sing V1 current just re activates the watch dog

during Standby mode

3 WEN WAKE Enable[2] 1 W AKE pin enabled

0 WAKE pin disabled

2 WSC WAKE Sample Control 1 WAKE mode cyclic sample

0 WAKE mode continuous sample

1 ILEN INH/LIMP Enable 1 INH/LIMP pin active (see ILC bit)

0 INH /LIMP pin floating

0 ILC INH/LIMP Control 1 INH/LIMP pin HIGH if ILEN bit is set

0 INH /LIMP pin LOW if ILEN bit is set

Product data sheet Rev. 06 — 9 March 2010 38 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.13.9 Physical Layer Control register and Physical Layer Control Feedback

These registers allow configu ration of the CAN transceiver and LIN transceiver of the SBC

and allow the settings to be read back.

[1] For the CAN transceiver to enter Off-Line mode from On-line or On-line Listen mode a minimum time without bus activity is needed. This

minimum time toff-line is defined by COTC; see Section 6.7.1.4.

[2] In case of an RXDC / TXDC interfacing failure the CAN transmitter is disabled without setting CTC. Recovery from such a failure is

automatic when CAN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and

clearing the CTC bit under software control.

Table 12. Physical Layer Control register and Physical Layer Control Feedback reg ister bit description

Bit Symbol Description Value Function

15 and 14 A1, A0 register address 11 select Physical Layer Control register

13 RRS Read Register Select 1 read the General Purpose Feedback register 1

0 read the Physical Layer Control Feedback register

12 RO Read Only 1 read the register selected by RRS without writing to the

Physical Layer Control register

0 read the register selected by RRS and write to Physical

Layer Control register

11 V2C V2 Control 0 V2 is OFF in CAN Off-line mode

1 V2 remains active in CAN Off-line mode

10 CPNC CAN Partial Networking

Control 1 CAN transceiver enters On-line Listen mode instead of

On-line mode; cleared whenever th e SBC enters On-line

mode or Active mode

0 On-l ine Listen mode disabled

9 COTC CAN Off-line Time

Control[1] 1t

off-line long period (extended to toff-line(ext) after wake-up)

off-line short period (extended to toff-line(ext) after wake-up)

8 CTC CAN Transmitter

Control[2] 1 CAN transmitter is disabled

0 CAN tran smitter is enabled

7 CRC CAN Receiver Control 1 TXD signal is forwarded directly to RXD for self-test

purposes (loopback behavior); only if CTC = 1

0 TXD signal is not forwarded to RXD (normal behavior)

6 CMC CAN Mode Control 1 CAN Active mode (in Normal mode and Flash mode only)

0 CAN Active mode disabled

5 - reserved 0 reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

4 LMC LIN Mode Control 1 LIN Active mode (in Normal mode and Flash mode only)

0 LIN Active mode disabled

3 LSC LIN Slope Control 1 up to 10.4 kbit/s (low slope)

0 up to 20 kbit/s (normal)

2 LDC LIN Driver Control 1 increased LIN driver curre nt capability

0 LIN driver in conformance with the LIN 2.0 standard

1 LWEN LIN Wake-up Enable 1 Wake-up via the LIN-bus enabled

0 Wake-up via the LIN-bus disabled

0 LTC LIN Transmitter

Control[3] 1 LIN transmitter is disabled

0 LIN transmitter is enabled

Product data sheet Rev. 06 — 9 March 2010 39 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

[3] In case of an RXDC / TXDC interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is

automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing

the LTC bit under software control.

6.13.10 Special Mode register and Special Mode Feedback register

These registers allow configuration o f global SBC p arameters during st art-up o f a system,

and allow the settings to be read back.

[1] See Section 6.14.1.

[2] Not supported in the UJA1061TW/3V3 version.

Table 13. Special Mode register and Special Mode Feedback register bit des cription

Bit Symbol Description Value Function

15 and 14 A1, A0 register address 01 select Special Mode register

13 RRS Read Register Select 0 read the Interrupt Enable Feedback register

1 r ead the Special Mode Feedback register

12 RO Read Only 1 read the register selected by RRS without writing to the

Special Mode register

0 read the register selected by RRS and write to the Special

Mode register

11 and 10 - reserved 0 reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

9 ISDM Initialize Software

Development Mode[1] 1 initialization of Software Development mode

0 normal watchdog interrupt, reset monitoring and fa il-safe

behavior

8 ERREM Error-pin Emulation

Mode 1 pin EN reflects the status of the CANFD bits:

EN is set if CANFD = 0000 (no error)

EN is cleared if CANFD is not 0000 (error)

0 pin EN behaves as an enable pin; see Section 6.5.2

7 - reserved 0 reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

6 and 5 WDPRE

[1:0] Watchdog Prescaler 00 watchdog prescale factor 1

01 watchdog prescale factor 1.5

10 watchdog prescale factor 2.5

11 watchdog prescale factor 3.5

4 and 3 V1RTHC

[1:0] V1 Reset Threshold

Control 11 V1 reset threshold = 0.9 ×VV1(nom)

10 V1 reset threshold = 0.7 ×VV1(nom)[2]

01 V1 reset threshold = 0.8 ×VV1(nom)

00 V1 reset threshold = 0.9 ×VV1(nom)

2 to 0 - reserved 0 reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

Product data sheet Rev. 06 — 9 March 2010 40 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.13.11 General Purpose registers and General Purpose Feedback registers

The UJA1061 offers two 12-bit General Purpose registers (and accompanying Gener al

Purpose Feedback registers) with no predefined bit definition. These registers can be

used by the microcontroller for advanced system diagnosis, or for storing critical system

status information outside the microcontroller. After Po wer-up Gen eral Pur pose r egister 0

will contain a ‘Device Identification Code’ consisting of the SBC type and SBC version.

This code is available until it is overwritten by the microcontroller ( as indicated by the DIC

bit).

[1] The Device Identification Control bit is cleared during power-up of the SBC, indicating that General Purpose register 0 is loaded with the

Device Identification Code. Any write access to General Purpose register 0 will set the DIC bit, regardless of the value written to DIC.

[2] During power-up the General Purpose register 0 is loaded with a ‘Device Identification Code’ consisting of the SBC type and SBC

version, and the DIC bit is cleared.

Table 14. General Purpose register 0 and General Purpo se Feedback register 0 bit description

Bit Symbol Description Value Function

15, 14 A1, A0 register address 10 select General Purpose Feedback register 0

13 RRS Read Register Select 1 read the General Purpose Feedback register 0

0 read the System Configuration Feedback register

12 RO Read Only 1 read the register selected by RRS without writing to the

General Purpose register 0

0 read the register selected by RRS and write to the General

Purpose register 0

11 DIC Device Identification

Control[1] 1 General Purpose register 0 contains user-defined bits

0 Gen eral Purpose register 0 contains the Device

Identification Code

10 to 0 GP0[10:0] General Purpose bits[2] 1 user-defined

0 user-defined

Table 15. General Purpose register 1 and General Purpo se Feedback register 1 bit description

Bit Symbol Description Value Function

15 and 14 A1, A0 register address 11 select General Purpose re gister 1

13 RRS Read Register Select 1 read the General Purpose Feedback register 1

0 read the Physical Layer Control Feedback register

12 RO Read Only 1 read the register selected by RRS without writing to the

General Purpose register 1

0 read the register selected by RRS and write to the General

Purpose register 1

11 to 0 GP1[11:0] General Purpose bits 1 user-defined

0 user-defined

Product data sheet Rev. 06 — 9 March 2010 41 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.13.12 Register configurations at reset

At power-on, Start-up and Restart the setting of the SBC registers is predefined.

[1] Depends on history.

[2] In case the ERREM bit in the Special Mode register is 0. Otherwise ENS shows the actual CAN failure status.

Table 16. System Status register: status at reset

Symbol Name Power-on Start-up[1] Restart[1]

RSS Reset Source Status 0000 (power-on reset) any value except 1100 0000 or 0010 or 1100

or 1110

CWS CAN Wake-up S tatus 0 (no CAN wake-up) 1 if reset is caused by a

CAN wake-up,

otherwise no change

no change

L WS LIN Wake-up S tatus 0 (no LIN wake-up) 1 if reset is caused by a

LIN wake-up,

otherwise no change

no change

EWS Edge Wake-up Status 0 (no edge detected) 1 if reset is caused by a

wake-up via pin WAKE,

otherwise no change

no change

WLS WAKE Leve l Status actual status actual status actual status

TWS Temperature Warning

Status 0 (no warning) actual status actual status

SDMS Software Development

Mode Status actual status actual status actual status

ENS Enable Status 0 (EN = LOW)[2] 0(EN=LOW)

[2] 0(EN=LOW)

[2]

PWONS Power-on Status 1 (power-on reset) no change no change

Table 17. System Diagn osis register: status at reset

Symbol Name Power-on Start-up Restart

GSD Ground Shift Diagnosis 0 (OK) actual status actual status

CANFD CAN Failure Diagnosis 0000 (no failure) actual status actual status

LINFD LIN Failure Diagnosis 00 (no failure) actual status actual status

V3D V3 Diagnosis 1 (OK) actual status actual status

V2D V2 Diagnosis 1 (OK) actual status actual status

V1D V1 Diagnosis 0 (fail) actual status actual status

CANMD CAN Mode Diagnosis 00 (Off-line) actual status actual status

Table 18. Interrupt Enab le reg iste r and Interrupt Enable Feedback registe r: status at reset

Symbol Name Power-on Start-up Restart

All all bits 0 (interrupt disabled) no change no change

Table 19. Interrupt register: status at reset

Symbol Name Power-on Start-up Restart

All all bits 0 (no interrupt) 0 (no interrupt) 0 (no interrupt)

Product data sheet Rev. 06 — 9 March 2010 42 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Table 20. System Configuration register and System Configuration Feedback register: status at reset

Symbol Name Power-on Start-up Restart Fail-safe

GSTHC GND Shift level

Threshold Control 0 (normal) no change no change no change

RLC Reset Length

Control 0 ( short) no change 1 (long) 1 (long)

V3C V3 Control 00 (off) no change no change no change

V1CMC V1 Current Monitor

Control 0 (watchdog

restart) no change no change no change

WEN Wake Enable 1 (enabled) no change no chan ge no change

WSC Wake Sam ple

Control 0 ( control) no change no change no change

ILEN INH/LIMP Enable 0 (floating) see Figure 12 if

ILC = 1, otherwise

no change

0 (floating) if

ILC = 1, otherwise

no change

1 (active)

ILC INH/LIMP Control 0 (LOW) no change no change 0 (LOW)

Table 21. Physical Layer Control register and Physical Layer Control Feedback reg ister: status at reset

Symbol Name Power-on Start-up Restart Fail-safe

V2C V2 Control 0 (auto) no change no change 0 (auto)

CPNC CAN Partial

Networking Control 0 (On-line Listen

mode disabled) 0 if reset is caused

by a CAN

wake-up,

otherwise no

change

no change 0 (On-line Listen

mode disabled)

COTC CAN Off-line Time

Control 1 (long) no change no change no change

CTC CAN Transmitter

Control 0 (on) no change no change no change

CRC CAN Receive r

Control 0 (normal) no change no change no change

CMC CAN Mode Control 0 (Active mode

disabled) no change no change no chan ge

LMC LIN Mode Control 0 (Active mode

disabled) no change no change no chan ge

LSC LIN Slope Control 0 (normal) no change no change no change

LDC LIN Driver Control 0 (LIN 2.0) no change no change no change

LWEN LIN Wake-up

Enable 1 (enabled) no change no change no change

LTC LIN Transmitter

Control 0 (on) no change no change no change

Product data sheet Rev. 06 — 9 March 2010 43 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

6.14 Test modes

6.14.1 Software Development mode

The Software Development mode is inte nded to support software developers in writing

and pretesting application software without having to work around watchdog trigg ering

and without unwanted jumps to Fail-safe mode.

In Software Development mode the following events do not force of a system reset:

•Watchdog overflow in Normal mode

•Watchdog window miss

•Interrupt time-out

•Elapsed start-up time

However, in case of a watchdog trigger failure the reset source information is still provided

in the System Status register as if there was a real reset event.

The exclusion of watchdog related resets allows simplified software testing, because

possible problems in th e watchdog triggering can be indicated by interrupts instead of

resets. The SDM bit does not affect the watchdog behavior in Standby and Sleep mode.

This allows the cyclic wake-up behavior to be evaluated during Standby and Sleep mode

of the SBC.

All transitions to Fail-safe mode are disabled. This allows working with an external

emulator that clamps the reset line LOW in debugging mode. A V1 undervoltage of more

than tV1(CLT) is the only exception that results in entering Fail-safe mo de (to protect the

SBC). Transitions from Start-up mode to Restart mode are still possible.

Table 22. Special Mode register: status at reset

Symbol Name Power-on Start-up Restart

ISDM Initialize Software Development Mode 0 (no) no change no change

ERREM Error pin emulation mode 0 (EN function) no change no change

WDPRE Watchdog Prescale Factor 00 (factor 1) no change no change

V1RTHC V1 Reset Threshold Control 00 (90 %) no change 00 (90 %)

Table 23. General Purpose register 0 and Gener al Purpose Feedback regis t er 0: status at reset

Symbol Name Power-on Start-up Restart

DIC Device Identification Control 0 (Device ID) no change no change

GP0[10:7] gene ral purpose bits 10 to 7 (version) Mask version no change no change

GP0[6:0] general purpose bits 6 t o 0 (SBC type) 000 0001

(UJA1061) no change no change

Table 24. General Purpose register 1 and Gener al Purpose Feedback regis t er 1: status at reset

Symbol Name Power-on Start-up Restart

GP1[11:0] general purpose bits 11 to 0 0000 0000 0000 no change no change

Product data sheet Rev. 06 — 9 March 2010 44 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

There are two possibilities to enter Software Development mode. One is by setting the

ISDM bit via the Special Mode register; possible only once after a first battery connection

while the SBC is in Start-up mode. The second possibility to enter Software Development

mode is by applying the correct Vth(TEST) input voltage at pin TEST before the battery is

applied to pin BAT42.

To stay in Soft ware Development mode the SDM bit in the Mode register has to be set

with each Mode register access (i.e. watchdog triggering) regardless of how Software

Development mode was entered.

The Sof tware Development mode can be e xited at any time by clearing the SDM bit in th e

Mode register. Reentering the Software Development mode is only possible by

reconnecting the battery supply (pin BAT42), thereby forcing a new power-on reset.

6.14.2 Forced Normal mode

For system evaluation purpose s the UJA1061 of fers the Force d Normal mode. This mode

is strictly for evaluation purposes only. In this mode the characteristics as defined in

Section 9 and Section 10 cannot be guaranteed.

In Forced normal mode the SBC behaves as follows:

•SPI access (writing and reading) is blocked

•Watchdog disabled

•Interrupt monitoring disabled

•Reset monitoring disabled

•Reset lengthening disabled

•All transitions to Fail-safe mode are disabled, except a V1 undervoltage for more than

tV1(CLT)

•V1 is started with the long reset time tRSTNL. In case of a V1 undervoltage, a reset is

performed until V1 is restored (normal be havior), and the SBC stays in Forced Normal

mode; in case of a continuous overload at V1 > tV1(CLT) Fail-safe mode is entered

•V2 is on; overload protection active

•V3 is on; overload protection active

•CAN and LIN are in Active mode and cannot switch to Off-line mode

•INH/LIMP pin is HIGH

•SYSINH is HIGH

•EN pin at same level as RSTN pin

Forced Normal mode is activated by applying the correct Vth(TEST) input voltage at the

TEST pin during first battery connection.

Product data sheet Rev. 06 — 9 March 2010 45 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

7. Limiting values

[1] Only relevant if VWAKE < VGND − 0.3 V; current will flow into pin GND.

[2] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj =T

amb +P

d×Rth(vj-amb), where Rth(vj-amb)

is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (Pd) and

ambient temperature (Tamb).

[3] Human Body Model (HBM): C = 100 pF; R = 1.5 kΩ.

[4] ESD performance according to IEC 61000-4-2 (C = 150 pF, R = 330 Ω) of pins CANH, CANL, RTH, RTL, LIN, RTLIN, WAKE, BAT42

and V3 with respect to GND was verified by an external test house. Following results were obtained:

a) equal or better than ±6 kV (unaided).

b) equal or better than ±20 kV (using external ESD protection: NXP Semiconductors PESD1CAN and PESD1LIN diode).

[5] Machine Model (MM): C = 200 pF; L = 0.75 μH; R = 10 Ω.

Table 25. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.

Symbol Parameter Conditions Min Max Unit

VBAT42 BAT42 supply volta g e −0.3 +60 V

load dump; t ≤500 ms - 60 V

VBAT14 BAT14 supply voltage VBAT42 ≥ VBAT14 − 1 V

continuous −0.3 +33 V

load dump; t ≤500 ms - 45 V

VDC(n) DC voltages on pins

V1 and V2 −0.3 +5.5 V

V3 and SYSINH −1.5 VBAT42 + 0.3 V

WAKE −1.5 +60 V

INH/LIMP −0.3 VBAT42 + 0.3 V

CANH, CANL, RTH, RTL LIN and

RTLIN; with respect to any other

−60 +60 V

TXDC, RXDC, TXDL, RXDL, SDO,

SDI, SCK, SCS, RSTN, INTN and

−0.3 VV1 +0.3 V

TEST −0.3 +15 V

Vtrt transient voltage at pins CANH, CANL and LIN; in

accordance with ISO 7637-3 −150 +100 V

IWAKE DC current at pin WAKE [1] −15 - mA

Tstg storage temperature −55 +150 °C

Tamb ambient temperature −40 +125 °C

Tvj virtual junction temperature [2] −40 +150 °C

Vesd electrostatic discharge voltage HBM [3]

at pins CANH, CANL, RTH, RTL,

LIN, RTLIN, WAKE, BAT42, V3;

with respect to GND

[4] −8.0 +8.0 kV

at any other pin −2.0 +2.0 kV

MM; at any pin [5] −200 +200 V

Product data sheet Rev. 06 — 9 March 2010 46 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

8. Thermal characteristics

Fig 15. Thermal model of the HTSSOP32 p ackage

Rth(c-a)

Tcase(heat sink)

Tamb 001aac32

V1 dissipation V2 dissipation V3 dissipation other dissipation

6 K/W 20 K/W 23 K/W 6 K/W

6 K/W

Tvj

Product data sheet Rev. 06 — 9 March 2010 47 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

9. Static characteristics

Table 26. Static characteristics[1]

Tvj =

−

C to +150

C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Supply; pin BAT42

IBAT42 BAT42 sup ply current V1, V2 and V3 off; CAN and

LIN in Off-line mode; OTIE =

BATFIE = 0; ISYSINH = IWAKE =

IRTLIN =I

LIN = 0 mA

VBAT42 = 8.1 V to 52 V - 50 70 μA

VBAT42 = 5.5 V to 8.1 V - 70 93 μA

IBAT42(add) additional BAT42

supply current V1 and / or V2 on;

ISYSINH =0mA -5376μA

V3 in cyclic mode; IV3 =0mA - 0 1 μA

V3 continuously on; IV3 =0mA - 30 50 μA

Tvj warning enabled; OTIE = 1 - 20 40 μA

CAN in Active mode; CMC = 1 - 100 400 μA

LIN in Active mode; LMC = 1;

VTXDL = VV1;

IRTLIN =I

LIN =0mA

- 650 1300 μA

LIN in Active mode; LMC = 1;

VTXDL = 0 V (t < tLIN(dom)(det));

IRTLIN =I

LIN =0mA;

VBAT42 =12 V

-1.55mA

LIN in Active mode; LMC = 1;

VTXDL = 0 V (t < tLIN(dom)(det));

IRTLIN =I

LIN =0mA;

VBAT42 =27 V

-310mA

VPOR(BAT42) BAT42 voltage level

for Power-on reset

status bit change

for setting PWONS

PWONS = 0; VBAT42 falling 4.45 - 5 V

for clearing PWONS

PWONS = 1; VBAT42 rising 4.75 - 5.5 V

Supply; pin BAT14

VBAT14 BA T14 supply voltage normal output current capability

at V1 9- 27V

high output current capability

at V1 6- 8V

IBAT14 BAT14 sup ply current V1 and V2 off; CAN and LIN in

Off-line mode;

ILEN = CSC = 0;

IINH/LIMP =0mA

-25μA

Product data sheet Rev. 06 — 9 March 2010 48 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

IBAT14(add) additional BAT14

supply current V1 on; IV1 = 0 mA - 200 300 μA

V1 on; IV1 =0mA;

VBAT14 =12V - 150 200 μA

V2 on; IV2 = 0 mA - 200 320 μA

V2 on; IV2 =0mA;

VBAT14 =12V - 200 250 μA

INH/LIMP enabled; ILEN = 1;

IINH/LIMP = 0 mA -12μA

CAN in Active mode; CMC = 1;

ICANH =I

CANl = 0 mA;

VTXD =0V

Differential mode - 10 20 mA

Single-ended mode - 13 25 mA

CAN in Active mode; CMC = 1;

VTXD =V

Differential mode - 5 10 mA

Single-ended mo de - 8 15 mA

Voltage source; pin V1[2]; see also Figure 16 to 22

Vo(V1) output voltage VBAT14 =5.5V to18V;

IV1 =−120 mA to −5mA;

Tj=25°C

VV1(nom)

−0.1 VV1(nom) VV1(nom)

+0.1 V

VBAT14 =14V; I

V1 =−5mA;

Tj=25°CVV1(nom)

−0.025 VV1(nom) VV1(nom)

+0.025 V

ΔVV1 supply voltage

regulation VBAT14 =9V to16V;

IV1 =−5mA; T

j=25°C-125mV

load regul at i on VBAT14 =14V; I

V1 =−50 mA

to −5mA; T

j=25°C-525mV

voltage drift with

temperature VBAT14 =14V; I

V1 =−5mA;

Tj=−40 °C to +150 °C[3] - - 200 ppm/K

Vdet(UV)(V1) undervoltage

detection and reset

activation level

VBAT14 =14V;

V1RTHC = 00 or 11 0.90 ×

VV1(nom)

0.92 ×

VV1(nom)

0.95 ×

VV1(nom)

VBAT14 = 14 V; V1RTHC = 01 0.80 ×

VV1(nom)

0.82 ×

VV1(nom)

0.85 ×

VV1(nom)

VBAT14 = 14 V; V1RTHC = 10 0.70 ×

VV1(nom)

0.72 ×

VV1(nom)

0.75 ×

VV1(nom)

Vrel(UV)(V1) undervoltage

detection release

level

VBAT14 =14V;

V1RTHC = 00 or 11 - 0.94 ×

VV1(nom)

-V

VBAT14 = 14 V; V1R T HC = 01 - 0.84 ×

VV1(nom)

-V

VBAT14 = 14 V; V1R T HC = 10 - 0.74 ×

VV1(nom)

-V

VUV(VFI) undervoltage level for

generating a VFI

interrupt

VBAT14 = 14 V; VFIE = 1 0.90 ×

VV1(nom)

0.93 ×

VV1(nom)

0.97 ×

VV1(nom)

Table 26. Static characteristics[1] …continued

Tvj =

−

C to +150

C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 06 — 9 March 2010 49 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

IthH(V1) undercurrent

threshold for

watchdog enable

−10 −5−2mA

IthL(V1) undercurrent

threshold for

watchdog disable

−6−3−1.5 mA

IV1 output current

capability VBAT14 = 9 V to 27 V;

δVV1 = 0.05 × VV1(nom)

−200 −135 −120 mA

VBAT14 =9V to27V;

V1 shorted to GND −200 −110 - mA

VBAT14 =8V to9V;

δVV1 = 0.05 × VV1(nom)

--−120 mA

VBAT14 = 5.5 V to 8 V;

δVV1 =0.05×VV1(nom)

--−150 mA

Zds(on) regulator impedance

between pins BAT14

and V1

VBAT14 = 4 V to 5 V - 3 5 Ω

Voltage source; pin V2[4]

Vo(V2) output voltage VBAT14 =9V to16V;

IV2 =−50 mA to −5mA 4.8 5.0 5.2 V

VBAT14 =14V; I

V2 =−10 mA;

Tj=25°C4.95 5.0 5.05 V

ΔVV2 supply voltage

regulation VBAT14 =9V to16V;

IV2 =−10 mA; Tj=25°C-125mV

load regul at i on VBAT14 =14V; I

V2 =−50 mA

to −5mA; T

j=25°C--50mV

voltage drift with

temperature VBAT14 =14V; I

V2 =−10 mA;

−40 °C<T

j<150°C[3] - - 200 ppm/K

IV2 output current

capability VBAT14 = 9 V to 27 V;

δVV2 = 300 mV −200 - −120 mA

VBAT14 = 9 V to 27 V; V2

shorted to GND −300 - - mA

VBAT14 =6V to8V;

δVV2 = 300 mV --−80 mA

VBAT14 =5.5V; δVV2 =300mV - - −50 mA

Vdet(UV)(V2) undervoltage

detection threshold VBAT14 = 14 V 4.5 4.6 4.8 V

Voltage source; pin V3

VBAT42-V3(drop) VBAT42 to VV3 voltage

drop VBAT42 =9V to52V;

IV3 =−20 mA --1.0V

Idet(OL)(V3) overload current

detection threshold VBAT42 =9V to52V −165 - −60 mA

Table 26. Static characteristics[1] …continued

Tvj =

−

C to +150

C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 06 — 9 March 2010 50 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

System inhibit output; pin SYSINH

VBAT42-SYSINH(drop) VBAT42 to VSYSINH

voltage drop ISYSINH =−0.2 mA - 1.0 2.0 V

|IL|leakage current VSYSINH =0V - - 5 μA

Inhibit / limp-home output; pin INH/LIMP

VBAT14-INH(drop) VBAT14 to VINH voltage

drop IINH/LIMP =−10 μA;

ILEN=ILC=1 -0.71.0V

IINH/LIMP =−200 μA;

ILEN=ILC=1 -1.22.0V

Io(INH/LIMP) output current

capability VINH/LIMP = 0.4 V; ILEN = 1;

ILC = 0 0.8 - 4 mA

|IL|leakage current VINH/LIMP = 0 V to VBAT14;

ILEN = 0 --5μA

Wake input; pin WAKE

Vth(WAKE) WAKE voltage

threshold 2.0 3.3 5.2 V

IWAKE(pu) pull-up input current VWAKE =0V −25 - −1.3 μA

Serial peripheral interface inputs; pins SDI, SCK and SCS

VIH(th) HIGH-level input

threshol d vo ltage 0.7 × VV1 -V

V1 + 0.3 V

VIL(th) LOW-level input

threshol d vo ltage −0.3 - 0.3 × VV1 V

Rpd(SCK) pull-down resistor at

pin SCK VSCK =2V; V

V1 ≥2 V 50 130 400 kΩ

Rpu(SCS) pull-up resistor at

pin SCS VSCS =1V; V

V1 ≥2 V 50 130 400 kΩ

ILI(SDI) input leakage current

at pin SDI VSDI =0V toV

V1 −5- +5μA

Serial peripheral interface data output; pin SDO

IOH HIGH-level output

current VO=V

V1 −0.4 V; VSCS = 0 V −50 - −1.6 mA

IOL LOW-level output

current VO= 0.4 V; VSCS = 0 V 1.6 - 20 mA

ILO(off) OFF-state output

leakage current VO=0V toV

V1; VSCS = VV1 −5- +5μA

Reset output with clamping detection; pin RSTN

IOH HIGH-level output

current VRSTN =0.7 × VV1(nom) −1000 - −50 μA

IOL LOW-level output

current VRSTN = 0.9 V 1 - 5 mA

VOL LOW-level output

voltage VV1 = 1.5 V to 5.5 V; pull-up

resistor to V1 = ≥ 4 kΩ0 - 0.2 × VV1 V

VIH(th) HIGH-level input

threshol d vo ltage 0.7 × VV1 -V

V1 + 0.3 V

Table 26. Static characteristics[1] …continued

Tvj =

−

C to +150

C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 06 — 9 March 2010 51 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

VIL(th) LOW-level input

threshol d vo ltage −0.3 - +0.3 ×

VV1

Enable output; pin EN

IOH HIGH-level output

current VOH =V

V1 −0.4 V −20 - −1.6 mA

IOL LOW-level output

current VOL = 0.4 V 1.6 - 20 mA

VOL LOW-level output

voltage IOL =20μA; VV1 = 1.2 V 0 - 0.4 V

Interrupt output; pin INTN

IOL LOW-level output

current VOL = 0.4 V 1.6 - 15 mA

CAN transmit data input; pin TXDC

VIH HIGH-level input

voltage 0.7 × VV1 -V

V1 + 0.3 V

VIL LOW-level input

voltage −0.3 - +0.3 ×

VV1

RTXDC(pu) TXDC pull-up resistor VTXDC = 0 V 5 12 25 kΩ

CAN receive data output; pin RXDC

IOH HIGH-level output

current VOH =V

V1 −0.4 V −25 - −1.6 mA

IOL LOW-level output

current VOL = 0.4 V 1.6 - 25 mA

Fault-tolerant CAN-bus lines; pins CANH and CANL

Vdif(CANH-CANL) differential receiver

threshol d vo ltage Active mode, On-line, Partial

Networking or On-Line Listen

mode; VV2 = 5 V; no failures

and bus failures H//, L//,

HxGND and LxVCC

−3.5 −3.2 −2.9 V

Vse(CANH) pin CANH single

ended receiver

threshol d vo ltage

Active mode, On-line, Partial

Networking or On-Line Listen

mode; VV2 = 5 V; bus failures

LxGND, LxBAT and HxL

1.5 1.7 1.85 V

Vse(CANL) pin CANL single

ended receiver

threshol d vo ltage

Active mode, On-line, Partial

Networking or On-Line Listen

mode; VV2 = 5 V; bus failures

HxBAT and HxVCC

3.15 3.3 3.45 V

Vdet(HxBAT),

Vdet(LxBAT)

detection threshold

voltage for bus

failures HxBAT and

LxBAT

Active mode, On-line, Partial

Networking or On-Line Listen

mode; VV2 =5V

6.5 7.1 8.0 V

Vdet(GSD)(CANH) pin CANH ground

shift detection

threshol d vo ltage

Active mode; VV2 =5V

SPI bit GSTHC = logic 0 −1.25 −0.75 −0.25 V

SPI bit GSTHC = logic 1 −2.0 −1.5 −1.0 V

Table 26. Static characteristics[1] …continued

Tvj =

−

C to +150

C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 06 — 9 March 2010 52 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Vwu(CANH) pin CANH wake-up

threshol d vo ltage off-line 2.5 3.2 3.9 V

Vwu(CANL) pin CANL wake-up

threshol d vo ltage off-line 1.1 1.8 2.5 V

ΔVwu(CANH-CANL) wake-up threshold

difference voltage CANH to CANL; off-line 0.8 1.4 - V

VO(reces) CANH recessive

output voltage Active mode, On-line, Partial

Networking or On-Line Listen

mode; VV2 = 4.75 V to 5.25 V;

VTXDC =V

V2; RRTH < 4 kΩ

--0.2V

CANL recessive

output voltage Active mode, On-line, Partial

Networking or On-Line Listen

mode; VV2 = 4.75 V to 5.25 V;

VTXDC =V

V2; RRTL < 4 kΩ

VV2 − 0.2 - - V

VO(dom) CANH dominant

output voltage Active mode, On-line, Partial

Networking or On-Line Listen

mode; VTXDC =0V; V

V2 =5V;

ICANH =−40 mA

VV2 − 1.4 - - V

CANL dominant

output voltage Active mode, On-line, Partial

Networking or On-Line Listen

mode; VTXDC =0V; V

V2 =5V;

ICANL =40mA

--1.4V

IO(CANH) pin CANH output

current Active mode; VCANH =0V;

VTXDC =0V; V

V2 =5V −110 −75 −45 mA

Auto mode; VCANH =0V;

VBAT14 =14V -−0.25 - μA

IO(CANL) pin CANL output

current Active mode; VCANL =5V;

VTXDC =0V; V

V2 =5V 45 75 110 mA

Auto mode; VCANL =14V;

VBAT14 =14V -0-μA

CAN termination resistor (pin RTH)

Rsw(RTH) switch-on resistance m easured between RTH and

GND; Active mode, On-line or

Selective Sleep; ⏐Io⏐=10mA;

VTXDC =5V

-40100Ω

VO(RTH) output voltage off-line; IO=100μA-0.71.0 V

IO(RTH) pin CANH output

current duri n g bu s

failure

Active mode;

VRTH =V

CANH =V

V2 =5V -95-μA

CAN termination resistor (pin RTL)

Rsw(RTL) switch-on resistance Active mode, On-line or

Selective Sleep; ⏐Io⏐=10mA;

VTXDC =5V; V

V2 =5V

-40100µΩ

IO(RTL) output current off-line; VRTL =0V −1.50 −0.65 −0.1 mA

during bus failure at CANL;

Active mode;

VRTL =V

CANL =0V; V

V2 =5V

-−95 - μA

Table 26. Static characteristics[1] …continued

Tvj =

−

C to +150

C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 06 — 9 March 2010 53 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

LIN transmit data input; pin TXDL

VIL LOW-level input

voltage −0.3 - 0.3 × VV1 V

VIH HIGH-level input

voltage 0.7 × VV1 -V

V1 + 0.3 V

RTXDL(pu) TXDL pull-up resistor VTXDL = 0 V 5 12 25 kΩ

LIN receive data output; pi n RXDL

IOH HIGH-level output

current VRXDL =V

V1 −0.4 V −50 - −1.6 mA

IOL LOW-level output

current VRXDL = 0.4 V 1.6 - 20 mA

LIN-bus line; pin LIN

Vo(dom) LIN dominant output

voltage Active mode; VBAT42 =7V to

18 V; LDC = 0;

t<t

TXDL(dom)(dis); VTXDL =0V;

RBAT42-LIN =500Ω

0 - 0.20 ×

VBAT42

Active mode; VBAT42 =7.6V

to 18 V; LDC = 1;

t<t

TXDL(dom)(dis); VTXDL =0V;

ILIN =40mA

0.7 1.4 2.1 V

ILIH HIGH-level input

leakage current VLIN =V

BAT42; VTXDL =V

V1 −10 0 +10 μA

VBAT42 =8V;

VLIN =8Vto18V; V

TXDL =V

−10 - +10 μA

ILIL LOW-level input

leakage current VBAT42 =12V; V

LIN =0V;

VTXDL =V

−100 - - μA

Io(sc) short-circuit output

current Active mode;

VLIN =V

BAT42 =12V;

VTXDL =0V; t<t

TXDL(dom)(dis);

LDC = 0

27 40 60 mA

Active mode;

VLIN =V

BAT42 =18V;

VTXDL =0V; t<t

TXDL(dom)(dis);

LDC = 0

40 60 90 mA

Vth(dom) receiver dominant

state VBAT42 = 7 V to 27 V - - 0.4 ×

VBAT42

Vth(reces) receiver recessive

state VBAT42 = 7 V to 27 V 0.6 ×

VBAT42

--V

Vth(hyst) receiver threshold

voltage hysteresis VBAT42 = 7 V to 27 V 0.05 ×

VBAT42

-0.175×

VBAT42

Vth(cen) receiver threshold

voltage centre VBAT42 = 7 V to 27 V 0.475 ×

VBAT42

0.500 ×

VBAT42

0.525 ×

VBAT42

Cin input capacitance [3] --10pF

ILleakage current VLIN = 0 V to 18 V; VBAT42 =0V −50 +5μA

VLIN = 0 V to 18 V;

VBAT42 =V

GND = 12 V (loss of

ground)

−10 - +10 μA

Table 26. Static characteristics[1] …continued

Tvj =

−

C to +150

C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 06 — 9 March 2010 54 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

[1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at Tamb = 125 °C on

wafer level (pretesting). Cased products are 100 % tested at Tamb =25°C (final testing). Both pretesting and final testing use correlated

test conditions to cover the specified temperature and power supply voltage range.

[2] VV1(nom) is 3.3 V or 5 V, depending on the SBC version.

[3] Not tested in production.

[4] V2 internally supplies the SBC CAN transceiver. The supply current needed for the CAN transceiver reduces the pin V2 output

capability. The performance of the CAN transceiver can be impaired if V2 is also used to supply other circuitry while the CAN transceiver

is in use.

LIN-bus termination resistor connection; pin RTLIN

VRTLIN RTLIN output voltage Active mode; IRTLIN =−10 μA;

VBAT42 =7V to27V VBAT42

−1.0 VBAT42

−0.7 VBAT42

−0.2 V

Off-line mode; I RTLIN =−10 μA;

VBAT42 =7V to27V VBAT42

−1.2 VBAT42

−1.0 -V

ΔVRTLIN RTLIN load regulation Active mode;

IRTLIN =−10 μAto−10 mA;

VBAT42 =7V to27V

-0.652V

IRTLIN(pu) RTLIN pull-up current Active mode;

VRTLIN =V

LIN =0V

(t > tLIN(dom)(det))

−150 −60 −35 μA

Off-line mode;

VRTLIN =V

LIN =0V

(t < tLIN(dom)(det))

−150 −60 −35 μA

ILIL LOW-level input

leakage current Of f- line mode;

VRTLIN =V

LIN =0V

(t > tLIN(dom)(det))

−10 0 +10 μA

TEST input; pin TEST

Vth(TEST) input threshold

voltage for entering Software

Development mode; Tj=25°C158V

for entering Forced Normal

mode; Tj= 25 °C21013.5V

R(pd)TEST pull-down resistor between pin TEST and GND 2 4 8 kΩ

Temperature dete ction

Tj(warn) high junction

temperature warning

level

160 175 190 °C

Table 26. Static characteristics[1] …continued

Tvj =

−

C to +150

C; VBAT42 = 5.5 V to 52 V;VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 06 — 9 March 2010 55 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

a. Tj= 25 °C.

b. Tj= 150 °C.

Fig 16. V1 output vo ltage (dropout) as a function of battery voltage

VBAT14 (V)

2 76453

015aaa055

VV1

(V)

type 5V0

IV1 =

−100 μA

−50 mA

−120 mA

−250 mA

type 3V3

VBAT14 (V)

2 76453

015aaa056

VV1

(V)

type 5V0

IV1 =

−100 μA

−50 mA

−120 mA

−250 mA

type 3V3

Product data sheet Rev. 06 — 9 March 2010 56 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

(1) Types 5V0 and 3V3.

(2) Type 5V0 only.

a. At Tj= −40 °C, +25 °C and +150 °C.

(1) Types 5V0 and 3V3.

(2) Type 3V3 only.

b. At Tj= −40 °C to +150 °C.

Fig 17. V1 quiescent current as a function of output current

IV1 (mA)

0−250−200−100 −150−50

001aaf246

IBAT14 − IV1

(mA)

Tj = +150 °C

5.5 V(2)

VBAT14 = 8 V(1)

Tj = −40 °C

+25 °C

−40 °C

+25 °C

+150 °C

IV1 (mA)

0−250−200−100 −150−50

001aaf247

IBAT14 − IV1

(mA)

VBAT14 = 9 V to 27 V(1)

5.5 V(2)

Product data sheet Rev. 06 — 9 March 2010 57 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

VBAT14 = 9 V to 27 V.

Tj= 25 °C to 125 °C.

Fig 18. V1 output voltage as a function of output current

IV1 = −120 mA.

(1) Type 5V0 only.

Fig 19. V1 power supply ripple rejection as a function of frequency

015aaa057

IV1 (mA)

0−160−120−80−40

VV1

(V)

type 5V0

type 3V3

001aaf248

f (Hz)

1 103

102

120

160

PSRR

(dB)

Tj = 25 °C

150 °C

25 °C to 150 °C

150 °C

VBAT14 = 14 V

14 V

5.5 V

5.5 V(1)

Product data sheet Rev. 06 — 9 March 2010 58 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

IV1 = −5 mA; C = 1 μF; ESR = 0.01 Ω; Tj= 25 °C.

a. Line transient response

VBAT14 = 14 V; C = 1 μF; ESR = 0.01 Ω; Tj = 25 °C.

b. Load transient response

Fig 20. V1 transient response as a function of time

t (μs)

0 500400200 300100

001aaf250

100

200

VBAT14

(V)

−100

ΔVV1

(mV)

ΔVV1

VBAT14

t (μs)

0 500400200 300100

001aaf251

−25

−75

IV1

(mA)

ΔVV1

(mV)

ΔVV1

IV1

200

400

−200

Product data sheet Rev. 06 — 9 March 2010 59 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Fig 21. V1 output stability related to ESR value of output capacitor

001aaf249

10−1

10−2

ESR

(Ω)

10−3

IV1 (mA)

0−120−80−40

stable operation area

unstable operation area

Product data sheet Rev. 06 — 9 March 2010 60 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

a. Switch-on test circuit.

b. Behavior at Tj= 25 °C.

c. Behavior at Tj= 85 °C.

Fig 22. Switch-o n be ha v io r of V V1

001aaf5

100

100 μF/

0.1 Ω

47 μF/

0.1 Ω

BAT42

BAT14

GND

SBC

VBAT Rload

Iload = 30 mA

015aaa058

t (ms)

0 2.01.60.8 1.20.4

(V)

BAT

= 8 V

type 5V0

type 3V3

BAT

= 5.5 V

BAT

= 12 V

015aaa059

t (ms)

0 2.01.60.8 1.20.4

(V)

BAT

= 8 V

type 5V0

type 3V3

BAT

= 5.5 V

BAT

= 12 V

Product data sheet Rev. 06 — 9 March 2010 61 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

10. Dynamic characteristics

Table 27. Dynamic characteristics[1]

Tvj =

−

C to + 150

C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see Figure 27)[2]

Tcyc clock cycle time 960 - - ns

tlead enable lead time clock is low when SPI select

falls 240 - - ns

tlag enable lag time clock is low when SPI select

rises 240 - - ns

tSCKH clock HIGH time 480 - - ns

tSCKL clock LOW time 480 - - ns

tsu input data setup time 80 - - ns

thinput data hold time 400 - - ns

tDOV output data valid time pin SDO; CL= 10 pF - - 400 ns

tSSH SPI select HIGH time 480 - - ns

CAN transceiver (pins CANL, CANH, TXDC and RXDC)

tt(rec-dom) output transition time

recessive to dominant between 10 % to 90 %;

RCAN_L =R

CAN_H = 125 Ω;

CCAN_L =C

CAN_H =1nF;

see Figure 23 and Figure 24

0.3 0.4 - μs

tt(dom-rec) o utput transition time

dominant to recessive between 10 % to 90 %;

RCAN_L =R

CAN_H = 125 Ω;

CCAN_L =C

CAN_H =1nF;

see Figure 23 and Figure 24

0.3 0.6 - μs

tPHL propagation delay

TXDC to RXDC

(HIGH to LOW

transition)

between 10 % to 90 %;

RCAN_L =R

CAN_H = 125 Ω;

CCAN_L =C

CAN_H =1nF;

see Figure 23 and Figure 24

--1.5μs

tPLH propagation delay

TXDC to RXDC

(LOW to HIGH

transition)

between 10 % to 90 %;

RCAN_L =R

CAN_H = 125 Ω;

CCAN_L =C

CAN_H =1nF;

see Figure 23 and Figure 24

-1.21.9μs

tBUS(fail)(det) bus failure detection

time bus failure HxBAT; Active

mode, On-line and Selective

Sleep mode; VV2 =5V

7- 38μs

bus failure HxVCC 1.6 - 8.0 ms

bus failures LxGND and HxL 0.3 - 1.6 ms

bus failure LxBAT; Active

mode, On-line and Selective

Sleep mode; VV2 =5V

0.3- 1.6ms

continuously dominant

clamped CAN-bus detection

time (start after detecting

HxVCC); Active mode, On-line

and Selective Sleep mode;

VV2 =5V

0.3- 1.6ms

Product data sheet Rev. 06 — 9 March 2010 62 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

tBUS(fail)(recover) bus failure recovery

time bus failure HxBAT 125 - 750 μs

bus failure HxVCC 0.3 - 1.6 ms

bus failures LxGND and HxL;

Active mode, On-line and

Selective Sleep mode;

VV2 =5V

7- 38μs

bus failures LxGND and HxL 0.3 - 1.6 ms

bus failure LxBAT; Active

mode, On-line and Selective

Sleep mode; VV2 =5V

125 - 750 μs

continuously dominant

clamped CAN-bus Active

mode, On-line and Selective

Sleep mode; VV2 =5V

1- 5μs

tTXDC(dom) TXDC permanent

dominant disable time Active mode, On-line and

Selective Sleep mode;

VV2 =5V; TXDC=logic0V

1.5 - 6 ms

tCANH(d1),

tCANL(d1)

minimum dominant

time first pulse for

wake-up on pins

CANH, CANL

off-line 7 - 38 μs

tCANH(rec),

tCANL(rec)

minimum recessive

time pulse (after first

dominant) for

wake-up on pins

CANH, CANL

off-line 3 - 10 μs

tCANH(d2),

tCANL(d2)

minimum dominant

time second pulse for

wake-up on pins

CANH, CANL

off-line 0 - 4 μs

tCANL(dom) CANL dominant time

entering Normal

mode and TXDC

goes dominant

VCANL > 8 V, first dominant bit

after entering Active mode 3- 10μs

ttimeout time-out period

between wake-up

message and confirm

message

On-line Listen mode 115 - 285 ms

toffline required recessive or

dominant time for

entering off-line

On-line or Selective Sleep

mode; COTC = logic 0;

CMC = logic 0

50 - 66 ms

On-line or Selective Sleep

mode; COTC = logic 1;

CMC = logic 0

200 - 265 ms

toff-line(ext) extended minimum

time before entering

Off-line mode

On-line or On-line Listen mode

after CAN wake-up event;

TXDC = VV1; V2D = 1; no bus

activity

400 - 530 ms

Table 27. Dynamic characteristics[1] …continued

Tvj =

−

C to + 150

C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 06 — 9 March 2010 63 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

tCANH, tCANL ground shift sampling

time required for

CANH, CANL voltage

level

Active mode, On-line and

Selective Sleep mode;

VV2 = 5 V; TXDC recessive

20 - 80 μs

ΔtPC pulse coun t

difference between

CANH and CANL for

failure detection

bus failures H//, L/ /, HxGND

and LxVCC; Active mode,

On-line and Selective Sleep

mode; VV2 =5V

-4-pulses

dominant pulse count

on CANH and CANL

for failure recovery

bus failures H//, L/ /, HxGND

and LxVCC; Active mode,

On-line and Selective Sleep

mode; VV2 =5V

-4-pulses

LIN transceiver; pins LIN, TXDL and RXDL[3]

δ1 duty cycle 1 Vth(reces)(max) = 0.744 ×VBAT42;

Vth(dom)(max) = 0.581 ×VBAT42;

LSC = 0; tbit =50μs;

VBAT42 =7V to18V

[4] 0.396 - -

δ2 duty cycle 2 Vth(reces)(min) = 0.422 ×VBAT42;

Vth(dom)(min) =0.284×VBAT42;

LSC = 0; tbit =50μs;

VBAT42 =7.6V to18V

[5] --0.581

δ3 duty cycle 3 Vth(reces)(max) = 0.778 ×VBAT42;

Vth(dom)(max) = 0.616 ×VBAT42;

LSC = 1; tbit =96μs;

VBAT42 =7V to27V

[4] 0.417 - -

δ4 duty cycle 4 Vth(reces)(min) = 0.389 ×VBAT42;

Vth(dom)(min) =0.251×VBAT42;

LSC = 1; tbit =96μs;

VBAT42 =7.6V to27V

[5] --0.590

tp(rx) propagation delay of

receiver CRXDL =20pF --6μs

tp(rx)(sym) symmetry of receiver

propagation delay rising edge with respect to

falling edge; CRXDL =20pF −2- +2μs

tBUS(LIN) minimum dominant

time for wake-up of

the LIN-transce ive r

Off-l i n e mode 30 - 150 μs

tLIN(dom)(det) continuously

dominant clamped

LIN-bus detection

time

Active mode; LIN = 0 V 40 - 160 ms

tLIN(dom)(rec) continuously

dominant clamped

LIN-bus recovery

time

Active mode 0.8 - 2.2 ms

tTXDL(dom)(dis) TXDL permanent

dominant disable time Active mode; TXDL = 0 V 20 - 80 ms

Table 27. Dynamic characteristics[1] …continued

Tvj =

−

C to + 150

C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 06 — 9 March 2010 64 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Battery monitoring

tBAT42(L) BAT42 LOW time for

setting PWONS 5- 20μs

Power supply V1; pin V 1

tV1(CLT) V1 clamped LOW

time during ramp-up

of V1

Start-up mode; V1 active 229 - 283 ms

Power supply V2; pin V 2

tV2(CLT) V2 clamped LOW

time during ramp-up

of V2

V2 active 28 - 36 ms

Power supply V3; pin V 3

tW(CS) cyclic sense period V3C = 10; see Figure 13 14 - 18 ms

V3C = 11; see Figure 13 28 - 36 ms

ton(CS) cyclic sense on-time V3C = 10; see Figure 13 345 - 423 μs

V3C = 11; see Figure 13 345 - 423 μs

Wake-up input; pin WAKE

tWU(ipf) input port filter time VBAT42 = 5 V to 27 V 5 - 120 μs

VBAT42 =27V to52V 30 - 250 μs

tsu(CS) cyclic sense sample

setup time V3C = 11 or 10; see Figure 13 310 - 390 μs

Watchdog

tWD(ETP) earliest watchdog

trigger point programmed Nominal

Watchdog Period (NWP);

Normal mode

0.45 ×

NWP -0.55 ×

NWP

tWD(LTP) latest watchdog

trigger point programmed nominal

watchdog period; Normal

mode, Standby mode and

Sleep mode

0.9 × NWP - 1.1 × NWP

tWD(init) watchdog initializing

period watchdog time-out in Start-up

mode 229 - 283 ms

Fail-safe mode

tret retention time Fail-safe mode; wake-up

detected 1.31.51.7s

Reset output; pin RSTN

tRSTN(CHT) clamped HIGH time,

pin RSTN RSTN driven LOW internally

but RSTN pin remains HIGH 115 - 141 ms

tRSTN(CLT) clamped LOW time,

pin RSTN RSTN driven HIGH internally

but RSTN pin remains LOW 229 - 283 ms

tRSTN(INT) interrupt monitoring

time INTN = 0 229 - 283 ms

Table 27. Dynamic characteristics[1] …continued

Tvj =

−

C to + 150

C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 06 — 9 March 2010 65 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

[1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at Tamb = 125 °C on

wafer level (pretesting). Cased products are 100 % tested at Tamb =25°C (final testing). Both pretesting and final testing use correlated

test conditions to cover the specified temperature and power supply voltage range.

[2] SPI timing is guaranteed for VBAT42 voltages down to 5 V. For VBAT42 voltages down to 4.5 V the guaranteed SPI timing values double,

so at these lower voltages a lower maximum SPI communication speed must be observed.

[3] tbit = selected bit time, depends on LSC-bit; 50 μs or 96 μs (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R1/R2/C1):

1kΩ/1 kΩ/10nF; 1kΩ/1 kΩ/6.8 nF; 1 kΩ/open/1 nF; see Figure 25 and Figure 26.

[4]

[5]

tRSTNL reset lengthening

time after internal or external reset

has been released; RLC = 0 0.9- 1.1ms

after internal or external reset

has been released; RLC =1 18 - 22 ms

Interrupt output; pin INTN

tINTN interrupt release after SPI has read out the

Interrupt register 2- - μs

Oscillator

fosc oscillator input

frequency 460.8 512 563.2 kHz

Table 27. Dynamic characteristics[1] …continued

Tvj =

−

C to + 150

C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42

≥

VBAT14

−

1 V; unless otherwise specified. All

voltages are defined with respect to ground. Positive currents flow into the IC.

Symbol Parameter Conditions Min Typ Max Unit

δ1δ3,tbus rec()min()

bit

-------------------------------

δ2δ4,tbus rec()max()

bit

--------------------------------

Fig 23. Timing test circuit for CAN transceiver

001aad80

RCAN_L

CCAN_L

RCAN_H

CCAN_H

RRTH

500 Ω

RRTL

500 Ω

10 pF

UJA1061 FAILURE

GENERATION

BAT

BAT42

RXDC

TXDC

CANL

CANH

BAT14

RTL

RTH

2732

GND

Product data sheet Rev. 06 — 9 March 2010 66 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Fig 24. Timing diagram CAN transceiver

Fig 25. Timing test circuit for LIN transceiver

VRXDC

Vdif(CANH-CANL)

VCANH

VCANL

VTXDC

mce636

tt(rec-dom) tt(dom-rec)

tPHL tPLH

50 %50 %

90 %

10 %

90 %

10 %

90 %

10 %

90 %

10 %

50 % 50 %

5 V

3.6 V

1.4 V

0 V

2.2 V

−3.2 V

−5 V

001aad179

SBC

BAT42

GND

LIN

RTLIN

TXDL

20 pF R2

RXDL

Product data sheet Rev. 06 — 9 March 2010 67 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Fig 26. Timing diagram LIN tran sc e iv e r

001aaa346

TXDL

LIN BUS

signal

receiving

node 1

receiving

node 2

BAT42

RXDL1

RXDL2

bit

bus(dom)(max)

bus(rec)(min)

th(reces)(max)

thresholds of

receiving node 1

th(dom)(max)

th(reces)(min)

th(dom)(min)

bus(dom)(min)

p(rx)r

p(rx)f

p(rx)r

p(rx)f

bus(rec)(max)

bit

thresholds of

receiving node 2

Fig 27. SPI timing

001aaf04

SCS

SCK

SDI

SDO X

X X

MSB LSB

tDOV

floating floating

tsu

tSCKL

tSCKH

tlead Tcyc tlag tSSH

Product data sheet Rev. 06 — 9 March 2010 68 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

11. Test information

11.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

Product data sheet Rev. 06 — 9 March 2010 69 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

12. Package outline

Fig 28. Package outline SOT549-1 (HTSSOP32)

UNIT A1A2A3bpcD

(1) E(2) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.1

DIMENSIONS (mm are the original dimensions).

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

SOT549-1 03-04-07

05-11-02

detail X

exposed die pad side

(A3)

0.25

116

32 17

0.95

0.85

0.30

0.19

5.1

4.9

3.6

3.4

0.20

0.09

11.1

10.9

6.2

6.0

8.3

7.9

0.65 1 0.2 0.78

0.48

0.1

0.75

0.50

vMA

HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;

ody width 6.1 mm; lead pitch 0.65 mm; exposed die pad SOT549-

max.

1.1

2.5

5 mm

scale

pin 1 index

MO-153

Product data sheet Rev. 06 — 9 March 2010 70 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering pro cess is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperatur e profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orie ntation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 06 — 9 March 2010 71 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

13.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 29) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 28 and 29

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

St udies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 29.

Table 28. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 29. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 06 — 9 March 2010 72 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 29. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 06 — 9 March 2010 73 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

14. Revision history

Table 30. Revision history

Document ID Release date Data sheet status Change notice Supersedes

UJA1061_6 20100309 Product data sheet - UJA1061_5

Modifications: •3.0 V version (UJA1061TW/3V0) discontinued

•Table 26: updated conditions for VO(reces) - CANL recessive output voltage

•Section 6.2.5: text of third paragraph revised

•Table 11: text of bit 4, V1CMC, revised

•Section 11.1: text revised

•Section 2.1: text revised

UJA1061_5 20071122 Product data sheet - UJA1061_4

UJA1061_4 20070427 Product data sheet - UJA1061_3

UJA1061_3 20060627 Prelimi nary data sheet - UJA1061_2

UJA1061_2

(9397 750 14201) 20051122 Objective data sheet - UJA1061_1

UJA1061_1

(9397 750 11708) 20040322 Objective specification - -

Product data sheet Rev. 06 — 9 March 2010 74 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full dat a

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental ,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulat ive liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or application s and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on a weakness or default in the

customer application /use or t he application/use of customer’s third party

customer(s) (hereinafter both referred to as “Application”). It is customer’s

sole responsibility to check whether the NXP Semiconductors product is

suitable and fit for the Appl ica tion plann ed. Customer has to do all necessary

testing for the Application in order to avoid a default of the Application and t he

product. NXP Semiconductors does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property right s.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly

states that t his specific NXP Semiconductors product is automotive qualified,

the product is not suit ab le for aut omotive u se. It is neit her qua lifi ed n or test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclu sio n and/or use of

non-automotive qualifie d products in automotive equipment or applications.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data fro m the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 06 — 9 March 2010 75 of 77

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting fr om customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 06 — 9 March 2010 76 of 77

continued >>

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2

2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2

2.3 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.4 Power management . . . . . . . . . . . . . . . . . . . . . 3

2.5 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 3

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 4

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Functional description . . . . . . . . . . . . . . . . . . . 7

6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.2 Fail-safe system controller . . . . . . . . . . . . . . . . 7

6.2.1 Start-up mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.2.2 Restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.2.3 Fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.2.4 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.2.5 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10

6.2.6 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.2.7 Flash mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.3 On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 12

6.4 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.4.1 Watchdog start-up behavior . . . . . . . . . . . . . . 13

6.4.2 Watchdog window behavior . . . . . . . . . . . . . . 13

6.4.3 Watchdog time-out behavior. . . . . . . . . . . . . . 14

6.4.4 Watchdog OFF behavior. . . . . . . . . . . . . . . . . 14

6.5 System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.5.1 RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.5.2 EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.6 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 17

6.6.1 BAT14, BAT42 and SYSINH. . . . . . . . . . . . . . 17

6.6.1.1 SYSINH output. . . . . . . . . . . . . . . . . . . . . . . . 17

6.6.2 Voltage regulators V1 and V2. . . . . . . . . . . . . 17

6.6.2.1 Voltage regulator V1. . . . . . . . . . . . . . . . . . . . 17

6.6.2.2 Voltage regulator V2. . . . . . . . . . . . . . . . . . . . 18

6.6.3 Switched battery output V3. . . . . . . . . . . . . . . 18

6.7 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . 19

6.7.1 Mode control. . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.7.1.1 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.7.1.2 On-line mode . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.7.1.3 On-line Listen mode . . . . . . . . . . . . . . . . . . . . 21

6.7.1.4 Off-line mode . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.7.2 CAN wake-up . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.7.3 Termination control . . . . . . . . . . . . . . . . . . . . . 21

6.7.4 Bus, RXD and TXD failure detection . . . . . . . 22

6.7.4.1 TXDC dominant clamping . . . . . . . . . . . . . . . 22

6.7.4.2 RXDC recessive clamping. . . . . . . . . . . . . . . 22

6.7.4.3 GND shift detection . . . . . . . . . . . . . . . . . . . . 23

6.8 LIN transceiver. . . . . . . . . . . . . . . . . . . . . . . . 23

6.8.1 Mode control . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.8.1.1 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.8.1.2 Off-line mode . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.8.2 LIN wake-up. . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.8.3 Termination control. . . . . . . . . . . . . . . . . . . . . 24

6.8.4 LIN slope control . . . . . . . . . . . . . . . . . . . . . . 25

6.8.5 LIN driver capability . . . . . . . . . . . . . . . . . . . . 25

6.8.6 Bus and TXDL failure detection. . . . . . . . . . . 25

6.8.6.1 TXDL dominant clamping. . . . . . . . . . . . . . . . 25

6.8.6.2 LIN dominant clamping . . . . . . . . . . . . . . . . . 25

6.8.6.3 LIN recessive clamping . . . . . . . . . . . . . . . . . 26

6.9 Inhibit and limp-home output . . . . . . . . . . . . . 26

6.10 Wake-up input . . . . . . . . . . . . . . . . . . . . . . . . 26

6.11 Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 27

6.12 Temperature protection . . . . . . . . . . . . . . . . . 27

6.13 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.13.1 SPI register mapping . . . . . . . . . . . . . . . . . . . 28

6.13.2 Register overview . . . . . . . . . . . . . . . . . . . . . 29

6.13.3 Mode register. . . . . . . . . . . . . . . . . . . . . . . . . 29

6.13.4 System Status register. . . . . . . . . . . . . . . . . . 32

6.13.5 System Diagnosis register. . . . . . . . . . . . . . . 33

6.13.6 Interrup t Enab le register and Interrupt

Enable Feedback register . . . . . . . . . . . . . . . 34

6.13.7 Interrupt register. . . . . . . . . . . . . . . . . . . . . . . 35

6.13.8 System Configuration register and System

Configuration Feedback register . . . . . . . . . . 37

6.13.9 Physical Layer Control register and Physical

Layer Control Feedback register . . . . . . . . . . 38

6.13.10 Special Mode register and Special Mode

Feedback register . . . . . . . . . . . . . . . . . . . . . 39

6.13.11 General Purpose registers and General

Purpose Feedback registers . . . . . . . . . . . . . 40

6.13.12 Register configurations at reset. . . . . . . . . . . 41

6.14 Test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.14.1 Software Development mode. . . . . . . . . . . . . 43

6.14.2 Forced Normal mode. . . . . . . . . . . . . . . . . . . 44

7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 45

8 Thermal characteristics . . . . . . . . . . . . . . . . . 46

9 Static characteristics . . . . . . . . . . . . . . . . . . . 47

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 61

11 Test information . . . . . . . . . . . . . . . . . . . . . . . 68

11.1 Quality information. . . . . . . . . . . . . . . . . . . . . 68

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 69

NXP Semiconductors UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 9 March 2010

Document identifier: UJA1061_6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

13 Soldering of SMD packages . . . . . . . . . . . . . . 70

13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 70

13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 70

13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 70

13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 71

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 73

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 74

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 74

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 74

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 75

16 Contact information. . . . . . . . . . . . . . . . . . . . . 75

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76