September 2013 Doc ID 16009 Rev 11 1/33
1
VNH5050A-E
Automotive fully integrated H-bridge motor driver
Features
■
Output current: 30 A
■
3 V CMOS compatible inputs
■
Undervoltage and overvoltage shutdown
■
Overvoltage clamp
■
Thermal shutdown
■
Cross-conduction protection
■
Current and power limitation
■
Very low standby power consumption
■
PWM operation up to 20 KHz
■
Protection against loss of ground and loss of
V
CC
■
Current sense output proportional to motor
current
■
Output protected against short to ground and
short to V
CC
■
Package: ECOPACK
®
Description
The VNH5050A-E is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic high-side driver and two low-side
switches. All switches are designed using
STMicroelectronics
®
well known and proven
proprietary VIPower
®
M0 technology that allows
to efficiently integrate on the same die a true
Power MOSFET with an intelligent
signal/protection circuitry. The three dies are
assembl ed in a PowerS SO - 36 TP package on
electrically isolated lead frames. This package,
specifically designed for the harsh automotive
environment offers improved thermal
performance thanks to exposed die pads.
More over, i ts fu lly symm etric al mecha nical design
allows superior manufacturability at board level.
The input signals IN
A
and IN
B
can directly
interface to the microcontroller to select the motor
direction and the brake condition. The DIAG
A
/EN
A
or DIAG
B
/EN
B
, when connected to an external
pull-up resistor, enables one leg of the bridge.
Each DIAG
A
/EN
A
provides a digital diagnostic
feedback signal as well. The normal operating
condition is explained in the truth table. The CS
pin allows monitoring the motor current by
delivering a current proportional to its value when
CS_DIS pin is driven low or left open. When
CS_DIS is driven high, CS pin is in high
impedance condition. The PWM, up to 20 KHz,
allows to control the speed of the motor in all
possible conditions. In all cases, a low level state
on the PWM pin turns off both the LS
A
and LS
B
switches.
Type R
DS(on)
I
out
V
ccmax
VNH5050A-E 50 mΩ max
(per leg) 30 A 41 V
PowerSSO-36 TP
Table 1. Device summary
Package Order codes
Tube Tape and reel
PowerSSO-36 TP VNH5050A-E VNH5050ATR-E
www.st.com
Contents VNH5050A-E
2/33 Doc ID 16009 Rev 11
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Elect rical char acteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.1 Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.2 Thermal resistances definition (values according to the PCB heatsink
area) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.3 Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 ECOPACK
®
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 PowerSSO-36 TP package information . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3 PowerSSO-36 TP packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VNH5050A-E List of tables
Doc ID 16009 Rev 11 3/33
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Pin definitions and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Pin functions description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Logic inputs (IN
A
, IN
B
, EN
A
, EN
B
, PWM, CS_DIS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Switching (V
CC
=13V, R
LOAD
= 1.5 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 12. Current sense (9 V < V
CC
< 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 13. Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 14. Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. Electrical transient requirements (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 16. Electrical transient requirements (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 17. Electrical transient requirements (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 18. Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 25
Table 19. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. PowerSSO-36 TP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
List of figures VNH5050A-E
4/33 Doc ID 16009 Rev 11
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 16
Figure 8. Definition of delay response time of sense current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Waveforms in full-bridge operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Waveforms in full-bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit protection . . . . . 21
Figure 12. Behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. PowerSSO-36™ PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. Auto and mutual R
thj-amb
vs PCB copper area in open box free air condition . . . . . . . . . . 25
Figure 18. Detailed chipset configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 19. PowerSSO-36 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 27
Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 27
Figure 21. Thermal fitting model of an H-bridge in PowerSSO-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22. PowerSSO-36 TP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 23. PowerSSO-36 TP tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 24. PowerSSO-36 TP tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VNH5050A-E Block diagram and pin description
Doc ID 16009 Rev 11 5/33
1 Block diagram and pin description
Figure 1. Block diagram
Table 2. Block description
Name Description
Logic control Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the truth table.
Undervoltage/overvoltage Shuts down the device for battery voltage outside the range
(4,5...24V).
High-side and low-side clamp voltage Protect the high-side and the low-side switches from high
voltage on the battery line.
High-side and low-side driver Drive the gate of the concerned switch to allow a proper
R
DS(on)
for the leg of the bridge.
Current limitation Limits the motor current in case of short circuit.
High-si de and low -si de
overtemperature protection
In case of short-circuit with the increase of the junction
temperature, it shuts down the concerned driver to prevent
degradation and to protect the die.
Low-si de overload de tector Detects when low-side current exceeds shutdown current
and latches off the concerned low-side.
Fault detection Signalizes an abnormal condition of the switch (output
shorted to ground or output shorted to battery) by pulling
down the concerned ENx/DIAGx pin.
Power limitation Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.
SOURCE_HS
A
1/K
SIGNAL
CLAMP
POWER
LIMITATION
FAULT
DETECTION
O
V
+ U
V
LS
B
_OVERTEMPERATURE
HS
B
_OVERTEMPERATUREHS
A
_OVERTEMPERATURE
LS
A
_OVERTEMPERATURE
LOGIC
CLAMP_LS
A
DRIVER
HS
A
CLAMP_HS
A
CURRENT
LIMITATION_A
HS
A
DRIVER
LS
A
LS
A
GND
A
OVERLOAD
DETECTOR_A
V
CC
DIAG
A
/EN
A
IN
A
CS CS_DIS PWM IN
B
DIAG
B
/EN
B
DRIVER
HS
B
HS
B
CLAMP_HS
B
CURRENT
LIMITATION_B
CLAMP_LS
B
LS
B
GND
B
DRIVER
LS
B
OVERLOAD
DETECTOR_B
SOURCE_HS
B
1/K
DRAIN_LS
A
DRAIN_LS
B
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Block diagram and pin description VNH5050A-E
6/33 Doc ID 16009 Rev 11
Figure 2. Configuration diagram (top view)
Table 3. Suggested connections for unused and not connected pins
Connection / pin Current sense N.C. SOURCE_HSx DRAIN_LSx INPUTx, PWM
DIAGx/ENx
CS_DIS
Floating Not allowed X X X X
To ground Through 1 kΩ
resistor XNot allowed X Through 10 kΩ
resistor
Table 4. Pin definitions and functions
Pin N° Symbol Function
13, 24 V
CC
, Heat
slug1 Drain of high-side switches and power supply voltage.
18 NC Not connected.
15 IN
A
Clockwise input.
16 EN
A
/DIAG
A
Status of high-side and low-side switches A;
Open drain output.
17 IN_PWM PWM input.
19 CS Output of current sense.
1
CS
19
EN
A
/DIAG
A
GND_B
EN
B
/DIAG
B
CS_DIS
18
INA
SOURCE HS
B
GND_B
Slug1
Slug2 Slug3
36
SOURCE HS
A
DRAIN LS
A
SOURCE HS
A
SOURCE HS
A
V
CC
V
CC
SOURCE HS
B
SOURCE HS
B
DRAIN LS
B
GND_B
GND_B
DRAIN LS
B
GND_A
IN_PWM
NC
SOURCE HS
B
GND_B
GND_B
DRAIN LS
A
GND_A
GND_A
GND_A
GND_A
GND_A
SOURCE HS
A
SOURCE HS
B
IN
B
SOURCE HS
A
VNH5050A-E Block diagram and pin description
Doc ID 16009 Rev 11 7/33
20 CS_DIS Active h igh CMOS co mpatible pin to d is able cur r ent se ns e
pin.
21 EN
B
/DIAG
B
Status of high-side and low-side switches B;
Open drain output.
22 IN
B
Counter clockwise input.
23, 25, 26, 27, 28, 29, 35 OUT
B
,
Heat
Slug3 Source of high-side switch B / drain of low-side switch B.
30, 31, 32, 33, 34,36 GND_B Source of low-side switch B.
2, 8, 9, 10, 11, 12, 14 OUT
A,
Heat
Slug2 Source of high-side switch A / drain of low-side switch A.
1, 3, 4, 5, 6, 7 GND_A Source of low-side switch A.
Table 5. Pin functions description
Name Description
V
CC
Battery connection.
GND Power ground.
OUT
A
OUT
B
Power connections to the motor.
IN
A
IN
B
Voltage controlled input pins with hysteresis, CMOS compatible. These two pins
control the state of the bridge in normal operation according to the truth table (brake
to V
CC
, Brake to GND, clockwise and counterclockwise).
PWM Voltage controlled input pin with hysteresis, CMOS compatible.Gates of low-side
FETS ge t m od ula ted by th e PW M signal d uri ng the ir o n p has e allowing spe ed co ntrol
of the motor.
EN
A
/DIAG
A
EN
B
/DIAG
B
Open drain bidirectional logic pins.These pins must be connected to an external pull
up resis tor . Whe n external ly pulled low, they dis able half-bridg e A or B. In case of fault
detection (thermal shutdown of a high-side FET or excessive on-state voltage drop
across a low-side FET), th ese pins ar e pull ed low by the devi ce (see t ruth t able in fault
condition).
CS Analog current sense output. This output delivers a current proportional to the motor
current if CS_DIS is low or left open. The information can be read back as an analog
voltage across an external res istor.
CS_DIS Active high CMOS compatible pin to disable the current sense pin.
Table 4. Pin definitions and functions (continued)
Pin N° Symbol Function
Electrical specifications VNH5050A-E
8/33 Doc ID 16009 Rev 11
2 Electrical specifications
Figure 3. Current and voltage conventions
2.1 Absolute maximum ratings
V
CC
IN
A
I
S
I
OUTA
I
INA
V
INA
V
CC
V
OUTA
I
SENSE
V
OUTB
DIAG
A
/EN
A
I
ENA
I
GND
I
OUTB
IN
B
I
INB
DIAG
B
/EN
B
I
ENB
V
ENB
V
ENA
V
INB
V
SENSE
OUT
A
OUT
B
PWM
CS
I
pw
V
pw
GND
V
CSD
I
CSD
CS_DIS
Table 6. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
Supply voltage + 41 V
I
max
DC output current Internally limited A
I
R
Reverse output current (continuous)
(1)
1. Based on the internal wires capability.
25 A
I
IN
Input current (IN
A
and IN
B
pins ) +/- 10 mA
I
EN
Enable input current (DIAG
A
/EN
A
and DIAG
B
/EN
B
pins) +/- 10 mA
I
pw
PWM Input current +/- 10 mA
I
CS_DIS
CS_DIS input current +/- 10 mA
V
CS
Current sense maximum voltage V
CC
-41/+V
CC
V
V
ESD
Electrostatic discharge
(Human body model: R = 1.5 kΩ, C = 100 pF) 2kV
T
c
Jun c tion operating temperature -40 to 150 °C
T
STG
Storage temperature -55 to 150 °C
I
GND
DC reverse ground pin current 200 mA
Electrical specifications VNH5050A-E
10/33 Doc ID 16009 Rev 11
2.3 Electrical characteristics
V
CC
= 9 V up to 18 V; -40 °C < T
j
< 150 °C, unless otherwise specified.
Table 8. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CC
Operati ng supply voltage 5.5 18 V
I
S
Supply current
Off-state with all fault cleared
and ENx = 0 (standb y)
IN
A
=IN
B
=PWM=0;
T
j
=25°C; V
CC
=13V
36µA
Off-state with all fault cleared
and ENx = 0 (standb y)
V
CC
=13V;
IN
A
=IN
B
=PWM=0;
T
j
= -40 °C to 150 °C
10 µA
Of f-state (no standby)
IN
A
=IN
B
=PWM=0;
ENx = 5 V;
T
j
= -40 °C to 150 °C
5mA
On-state:
IN
A
or IN
B
= 5V; no PWM 36mA
On-state:
IN
A
or IN
B
=5V;
PWM = 20 kHz 8mA
R
ONHS
Static high-side
resistance
I
OUT
= 8.5 A; T
j
= -40 °C 17 mΩ
OUT
= 8.5 A; T
j
=25°C 26 mΩ
I
OUT
= 8.5 A; T
j
= 150 °C 52 mΩ
I
OUT
= 8.5 A;
T
j
=- 40 °C
to
150 °C 60 mΩ
R
ONLS
Static low-side resistance I
OUT
= 8.5 A; T
j
=25°C 20 mΩ
I
OUT
= 8.5 A;
T
j
=- 40 °C
to
150 °C 40 mΩ
V
f
High-side free-wheeling
diode forward voltage I
OUT
=-8.5A; T
j
= 150 °C 0.7 0.9 V
I
L(off)
High-side off-state output
current (per channel)
T
j
=25°C; V
CC
=13V;
V
OUTX
=EN
X
=0V 03µA
T
j
=125°C; V
CC
=13V;
V
OUTX
=EN
X
=0V 05µA
I
RM
Dynamic cross-
conduction current I
OUT
= 8.5 A (see Figure 7)1A
VNH5050A-E Electrical specifications
Doc ID 16009 Rev 11 11/33
Table 9. Logic inputs (IN
A
, IN
B
, EN
A
, EN
B
, PWM, CS_DIS)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low level voltage Normal operation
(DIAG
X
/EN
X
pin a cts as an
input pin) 0.9 V
V
IH
Input high level voltage Normal operation
(DIAG
X
/EN
X
pin a cts as an
input pin) 2.1 V
V
IHYST
Input hysteresis voltage Normal operation
(DIAG
X
/EN
X
pin a cts as an
input pin) 0.15 V
V
ICL
Input clamp voltage I
IN
= 1 mA 5.5 6.3 7.5 V
I
IN
= -1 mA -1.0 -0.7 -0.3 V
I
INL
Input current V
IN
=0.9 V 1 µA
I
INH
Input current V
IN
=2.1 V 10 µA
V
DIAG
Enable output low level
voltage
Fault operation
(DIAG
X
/EN
X
pin a cts as an
output pin); I
EN
=1mA 0.4 V
Table 10. Switching (V
CC
=13V, R
LOAD
= 1.5 Ω)
Symbol Parameter Test conditions Min. Typ. Max. Unit
f PWM freq uen cy 0 20 kHz
t
d(on)
Turn-on delay time Input rise time < 1µs
(see Figure 6)250 µs
t
d(off)
Turn-o f f del ay time Input rise time < 1µs
(see Figure 6)250 µs
t
r
Rise time See Figure 5 12µs
t
f
Fall time See Figure 5 12µs
t
DEL
Delay time during change
of operating mode See Figure 4 200 400 1600 µs
t
rr
High-side free wheeling
diode reverse recovery
time See Figure 7 100 ns
Table 11. Protections and diagnostics
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
USD
Undervo lt age shut do w n 3 5 V
V
USDhyst
Undervo lt age shut do w n
hysteresis 0.5 V
V
OV
V
CC
overvo lt age shut down 24 27 30 V
I
LIM_H
High-side current limitation 30 42 60 A
Electrical specifications VNH5050A-E
12/33 Doc ID 16009 Rev 11
I
SD_LS
Shutdown LS current 30 50 70 A
V
CLP
Total clamp voltage
(V
CC
to GND) I
OUT
=8.5A 41 46 52 V
V
CLPH
High-side clamp voltage
(V
CC
to OUT
A
=0 or
OUT
B
=0) I
OUT
=8.5A 41 46 52 V
T
SD_LS
Time to shutdown for the
low-side 10 µs
V
CLPLS
Low-si de clamp voltage
(OUT
A
=V
CC
or
OUT
B
=V
CC
to GND) I
OUT
=8.5A 25 28 31 V
T
TSD(1)
Thermal shutdown
temperature V
IN
= 2.1 V 150 175 200 °C
T
TR(2)
Thermal reset temperature 135 °C
T
HYST(2)
Thermal hyst eresis
(T
SD
-T
R
)16 °C
T
TSD_LS
Low-side thermal
shutdown temperature V
IN
= 0 V 150 175 200 °C
1. T
TSD
is the minimum threshold temperature between HS and LS
2. Valid for both HSD and LSD.
Table 12. Current sense (9 V < V
CC
<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K
1
I
OUT
/I
SENSE
I
OUT
= 5 A; V
SENSE
=0.8V;
V
CSD
=0V;
T
j
=- 40°C
to
150 °C 4350 5100 6270
K
2
I
OUT
/I
SENSE
I
OUT
=10A;
V
SENSE
=1.6V; V
CSD
=0V;
T
j
=- 40°C
to
150 °C 4350 5030 5870
K
3
I
OUT
/I
SENSE
I
OUT
=25A; V
SENSE
=4V;
V
CSD
=0V;
T
j
=- 40°C
to
150 °C 4100 4930 5490
dK
1
/K
1(1)
Analog sense current
drift
I
OUT
= 5 A; V
SENSE
=0.8V;
V
CSD
=0V;
T
j
=- 40°C
to
150°C -14 14 %
dK
2
/K
2(1)
Analog sense current
drift
I
OUT
=10 A
;
V
SENSE
=1.6V;
V
CSD
=0V;
T
j
=- 40°C
to
150°C -13 13 %
dK
3
/K
3(1)
Analog sense current
drift
I
OUT
= 2 5 A; V
SENSE
=4V;
V
CSD
=0V;
T
j
=- 40°C
to
150 °C -13 13 %
Table 11. Protections and diagnostics (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VNH5050A-E Electrical specifications
Doc ID 16009 Rev 11 13/33
V
SENSE
Max analog sense
output voltage I
OUT
=10A; V
CSD
=0V;
R
SENSE
=800Ω5V
I
SENSETYP_500
Typical analog sense
I
OUT
=500mA; V
CC
=13V;
T
j
=- 40 °C 87 µA
I
OUT
=500mA; V
CC
=13V;
T
j
=25°C 91 µA
I
OUT
=500mA; V
CC
=13V;
T
j
=150°C 100 µA
I
SENSE0
Analog sense leakage
current
I
OUT
= 0 A; V
SENSE
=0V;
V
CSD
=5V; V
IN
=0V;
T
j
=- 40°C
to 150°C 05µA
V
CSD
=0V; V
IN
=5V;
T
j
= - 40 °C to 150 °C 0180µA
V
CSD
=5V; V
IN
=5V;
I
OUT
=8.5A 05µA
t
DSENSEH
Delay re sp on se tim e
from falling edge of
CS_DIS pin
V
IN
=5V; V
SENSE
<4V,
I
OUT
=8.5A;
I
SENSE
=90% of I
SENSEmax
(see Figure 8)
50 µs
t
DSENSEL
Delay re sp on se tim e
from rising edge of
CS_DIS pin
V
IN
=5V; V
SENSE
<4V;
I
OUT
= 8.5 A;
I
SENSE
=10% of I
SENSEmax
(see Figure 8)
20 µs
1. Analog sense current drift is deviation of factor K for a given device over (-40°C to 150°C and
9V < V
CC
< 18 V) with respect to its value measured at T
j
= 25 °C, V
CC
= 13 V.
Table 12. Current sense (9 V < V
CC
< 18 V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical specifications VNH5050A-E
14/33 Doc ID 16009 Rev 11
Figure 4. Definition of the delay times measurement
t
t
V
INB
V
INA
t
PWM
t
I
LOAD
t
DEL
t
DEL
VNH5050A-E Electrical specifications
Doc ID 16009 Rev 11 15/33
Figure 5. Definition of the low-side switching times
Figure 6. Definition of the high-side switching times
t
f
PWM
t
t
V
OUTA, B
20%
90% 80%
10%
t
r
t
t
V
OUTA
V
INA
90%
10%
t
D(on)
t
D(off)
Electrical specifications VNH5050A-E
16/33 Doc ID 16009 Rev 11
Figure 7. Definition of dynamic cross conduction current during a PWM operation
Figure 8. Definition of delay response time of sense current
t
t
I
MOTOR
PWM
t
V
OUTB
t
I
CC
t
rr
I
RM
IN
A
= 1, IN
B
=0
SENSE CURRENT
INPUT
LOAD CURREN T
CS_DIS
t
DSENSEH
t
DSENSEL
VNH5050A-E Electrical specifications
Doc ID 16009 Rev 11 17/33
Note: In normal operating conditions the DIAG
X
/EN
X
pin is consider ed as an input pin by the
device. This pin must be externally pulled high.
Table 13. Truth table in normal operating conditions
IN
A
IN
B
DIAG
A
/EN
A
DIAG
B
/EN
B
OUT
A
OUT
B
CS Operating mode
11
11
HH High Imp. Brake to V
CC
0L
I
SENSE
=I
OUT
/K Clockwise (CW)
01LH Counterclockwise (CCW)
0 L High Imp. Brake to GND
Table 14. Truth table in fault conditions (detected on OUT
A
)
IN
A
IN
B
DIAG
A
/EN
A
DIAG
B
/EN
B
OUT
A
OUT
B
CS
(V
CSD
=0V)
11
01OPEN
HHigh
impedance
0L
01HI
OUTB
/K
0L
High
impedance
X X 0 OPEN
Fault Information Protection Action
Electrical specifications VNH5050A-E
18/33 Doc ID 16009 Rev 11
Table 15. Electrical transient requirements (part 1/3)
ISO 7637 -2:
2004(E)
Test pulse
Test levels
(1)
1. The above test levels must be considered referred to V
CC
= 13.5V except for pulse 5b.
Number of
pulses or
test times
Burst cycle/p ulse
repetition time Delays and
Impedance
III IV Min. Max.
1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω
2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω
3a -100 V -150V 1h 90ms 100ms 0. 1µs, 50Ω
3b +75V +100 V 1h 90ms 100ms 0. 1µs, 50Ω
4 -6V -7V 1 pulse 100ms, 0.01Ω
5b
(2)
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
+65V +87V 1 pulse 400ms, 2Ω
Table 16. Electrical transient requirements (part 2/3)
ISO 763 7-2:
2004E
Test pulse
Test level results
III VI
1C C
2a C C
3a C C
3b C C
4C C
5b
(1)
1. Valid in case of external load dump clamp: 40V maximum referred to ground.
CC
Table 17. Electrical transient requirements (part 3/3)
Class Contents
C All functions of the device performed as designed after exposure to disturbance.
EOne or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
VNH5050A-E Electrical specifications
Doc ID 16009 Rev 11 19/33
2.4 Waveforms
Figure 9. Waveforms in full-bridge operation
NORMAL OPERATION (DIAG
A
/EN
A
=1, DIAG
B
/EN
B
=1)
IN
A
IN
B
PWM
OUT
A
OUT
B
I
OUTA
->
OUTB
DIAG
A
/EN
A
DIAG
B
/EN
B
DIAG
B
/EN
B
IN
A
IN
B
PWM
OUT
A
OUT
B
DIAG
A
/EN
A
NORMAL OPE RATION (DIAG
A
/EN
A
=1, DIAG
B
/EN
B
=0 and DIAG
A
/EN
A
=0, DIAG
B
/EN
B
=1)
CS (*)
CS
I
OUTA
->
OUTB
t
DEL
t
DEL
LOAD CONNECTED BETWEEN OUT
A
, OUT
B
LOAD CONNECTED BETWEEN OUT
A
, OUT
B
(*) CS BEHAVIOUR DURING PWM MODE DEPENDS ON PWM FREQUEN C Y AND DUT Y CYCL E
CS_DIS
CS_DIS
IN
A
IN
B
T
jHSA
DIAG
A
/EN
A
DIAG
B
/EN
B
I
LIM
T
TSD_HSA
T
TR_HSA
T
j
> T
TR
CURRENT LIMITATI O N/THERMAL SHUTD OW N or OUT
A
SHORTED TO GROUND
CS
I
OUTA
->
OUTB
normal operation OUT
A
shorted to ground normal operation
CS_DIS
T
j
< T
TSD
T
j
=T
TSD
power limitation
limitation
current
Electrical specifications VNH5050A-E
20/33 Doc ID 16009 Rev 11
Figure 10. Waveforms in full-bridge operation (c ontinued)
norma l ope ra tion OUT
A
softly shorted to V
CC
normal operation undervoltage shutdown
IN
A
IN
B
OUT
A
OUT
B
DIAG
B
/EN
B
DIAG
A
/EN
A
OUT
A
shorted to V
CC
(resistive short) and undervoltage shutdown
CS V<nominal
I
OUTA
->
OUTB
CS_DIS
T
j_LSA
T
TSD_LS
normal operation OUT
A
hardly shorted to V
CC
normal operation undervoltage shutdown
IN
A
IN
B
OUT
A
OUT
B
DIAG
B
/EN
B
DIAG
A
/EN
A
OUT
A
shorted to V
CC
(pure short) and undervoltage shutdown
CS V<nominal
I
OUTA
->
OUTB
CS_DIS
I
LSA
I
SD_LS
I
LSA
I
SD_LS
T
j_LSA
T
TSD_LS
VNH5050A-E Application information
Doc ID 16009 Rev 11 21/33
3 Application information
In normal operating conditions the DIAG
X
/EN
X
pin is consider ed as an input pin by the
device. This pin must be externally pulled high.
PWM pin usage: In all cases, a “0” on the PWM pin turns off both LS
A
and LS
B
switches.
When PWM rises back to “1”, LS
A
or LS
B
turn on again depending on the input pin state.
Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit
protection
Note: The value of the blocking capacitor (C) depends on the application conditions and defines
voltage and current ripple on supply line at PWM operation. Stored energy of the motor
inductance may fly back into the blocking capacitor, if the bridge driver goes into 3-state.
This causes a hazardous overvoltage if the capacitor is not big enough. As basic orientation,
500µF per 10A load current is recommended.
In case of a fault condition the DIAG
X
/EN
X
pin is considered as an output pin by the device.
The fault conditions are:
– Overtemperature on one or both high-sides
– Short to battery condition on the output (over current detection on the low-side
Power M O SFET)
Possible origins of fault conditions may be:
OUT
A
is shorted to ground → overtemperature detection on high-side A
OUT
A
is shorted to V
CC
→
low-side P ower MOSFET over current detection
When a fault condition is detected, the user can identify which power element is in fault by
monitoring the IN
A
, IN
B
, DIAG
A
/EN
A
and DIAG
B
/EN
B
pins.
M
μC
Reg 5V + 5V
HS
A
HS
B
LS
A
LS
B
V
CC
DIAG
A
/EN
A
CS
IN
A
PWM
OUT
A
OUT
B
D
S
Gb) N MOSFET
3.3K
1K
1K
1K
10K
33nF 1.5K
V
CC
100K
DIAG
B
/EN
B
+5V
1K
3.3K
IN
B1K
GND
A
GND
B
C
Application i nformation VNH5050A-E
22/33 Doc ID 16009 Rev 11
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the
respective output (OUT
X
) again, the input signal must rise from low to high level.
Figure 12. Behavior in fault condition (how a fault can be cleared)
Note: In case of the fault condition is not removed, the procedure for unlatching and sending the
device in Stby mode is:
- Clear the fault in the device (toggle: IN
A
if EN
A
= 0 or IN
B
if EN
B
=0)
- Pull low all inputs, PWM and Diag/EN pins within t
DEL
.
If the Diag/En pins are already low, PWM = 0, the fault can be cleared simply toggling the
input. The device enters in stby mode as soon as the fault is cleared.
3.1 Reverse battery protection
Three possible solutions can be considered:
– A Schottky diode
D
connected to V
CC
pin
– An N-channe l MO SF ET co nnec te d to the GND pin (see Figure 11)
– A P-channel MOSFET connected to the V
CC
pin
The device sustains no more than -25 A in reverse battery conditions because of the two
body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH5050A-E is pulled down to the V
CC
line (approximately -1.5 V).
VNH5050A-E Application information
Doc ID 16009 Rev 11 23/33
Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If
I
Rmax
is the maximum target reverse current through µC I/Os, series resistor is:
Figure 13. Half-bridge configuration
Note: The VNH5050A-E can be used as a high power half-bridge driver.
Figure 14. Multi-motors configuration
Note: The VNH5050A-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor has to be driven at a time. DIAG
X
/EN
X
pins allow
to put unused half-bridges in high impedance.
RVIOs VCC
–
IRmax
---------------------------------=
M
OUT
A
OUT
A
OUT
B
OUT
B
V
CC
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
GND GND
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
M
2
OUT
A
OUT
A
OUT
B
OUT
B
V
CC
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
GND GND
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
M
1
M
3
Package and PCB thermal data VNH5050A-E
24/33 Doc ID 16009 Rev 11
4 Package and PCB thermal data
4.1 PowerSSO-36 thermal data
Figure 15. PowerSSO-36™ PC board
Note: Board finish thickness 1.6 mm +/- 10%, Board double layers and four layers, Board
dimension 129x60, Board Material FR4, Cu thickness 0.070mm (front and back side),
Thermal vias spaced on a 1.2 mm x 1.2 mm grid, Vias pad clearance thickness 0.2 mm,
Thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 0.025 mm, Footprint
dimension 4.1 mm x 6.5 mm.
Double layers: footprint
Double layers: 2cm
2
of Cu
Double layers: 8cm
2
of Cu
Four layers: Cu on top layer: 16 cm
2
; Cu on bottom layer: 32 cm
2
; Cu on middle layer: total coverage
VNH5050A-E Package and PCB thermal data
Doc ID 16009 Rev 11 25/33
Figure 16. Chipset configuration
Figure 17. Auto and mutual R
thj-amb
vs PCB copper area in open box free air
condition
4.1.1 Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode
4.1.2 Thermal resistances def inition (values accord ing to the PCB h eatsink
area)
R
thHS
= R
thHSA
= R
thHSB
= Hi gh Side Ch ip Ther mal Res ist an ce Junc tio n to Amb ien t ( HS
A
or
HS
B
in ON state)
R
thLS
= R
thLSA
= R
thLSB
= Low Side Chip Thermal Resistance Junction to Ambient
HIGH SIDE
CHIP
HS
AB
LOW SIDE
CHIP A LOW SIDE
CHIP B
LS
A
LS
B
0
10
20
30
40
50
60
70
80
024681012
cm
2
of Cu Area (refer to PCB layout)
°C/W
RthA
RthB = R thC
RthAB = RthAC
RthBC
Table 18. Thermal cal culation in clockwise and anti-clockwise opera tion in steady-
state mode
HS
A
HS
B
LS
A
LS
B
T
jHSAB
T
jLSA
T
jLSB
ON OFF OFF ON P
dHSA
x R
thHS
+ P
dLSB
x R
thHSLS
+ T
amb
P
dHSA
x R
thHSLS
+
P
dLSB
x R
thLSLS
+ T
amb
P
dHSA
x R
thHSLS
+ P
dLSB
x R
thLS
+ T
amb
OFF ON ON OFF P
dHSB
x R
thHS
+ P
dLSA
x R
thHSLS
+ T
amb
P
dHSB
x R
thHSLS
+
P
dLSA
x R
thLS
+ T
amb
P
dHSB
x R
thHSLS
+ P
dLSA
x R
thLSLS
+ T
amb
Package and PCB thermal data VNH5050A-E
26/33 Doc ID 16009 Rev 11
R
thHSLS
= R
thHSALSB
= R
thHSBLSA
= Mutual Thermal Resistance Junction to Ambient
between High Side and Low Side Chips
R
thLSLS
= R
thLSALSB
= Mutual Thermal Resistance Junction to Ambient between Low Side
Chips
4.1.3 Th erm al calculation in transient mode
(a)
T
jHSAB
= Z
thHS
x P
dHSAB
+ Z
thHSLS
x (P
dLSA
+ P
dLSB
) + T
amb
T
jLSA
= Z
thHSLS
x P
dHSAB
+ Z
thLS
x P
dLSA
+ Z
thLSLS
x P
dLSB
+ T
amb
T
jLSB
= Z
thHSLS
x P
dHSAB
+ Z
thLSLS
x P
dLSA
+ Z
thLS
x P
dLSB
+ T
amb
Single pulse thermal impedance definition (values according to the PCB heatsink area).
Z
thHS
= High Side Chip Thermal Impedance Junction to Ambient
Z
thLS
= Z
thLSA
= Z
thLSB
= Low Side Chip Thermal Impedance Junction to Ambient
Z
thHSLS
= Z
thHSABLSA
= Z
thHSABLSB
= Mutual Thermal Impedance Junction to Ambient
between High Side and Low Side Chips
Z
thLSLS
= Z
thLSALSB
= Mutual Thermal Impedance Junction to Ambient between Low Side
Chips
Figure 18. Detailed chipset configuration
Equation 1: pulse calculation formula
a. Calculation is valid in any dynamic operating condition. P
d
values set by user.
CHIP 1
Z
hs
CHIP 2 CHIP 3
Z
ls
Z
ls
Z
hsls
Z
hsls
Z
lsls
ZTH
δRTH δZTHtp 1δ
–
()+()•=
where δtpT⁄=
VNH5050A-E Package and PCB thermal data
Doc ID 16009 Rev 11 27/33
Figure 19. PowerSSO-36 HSD thermal impedance junction ambient single pulse
Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse
0.1
1
10
100
0.001 0.01 0.1 1 10 100 1000
time (sec)
°C/W
HSD-footprint
HSD-2 cm^2 Cu
HSD-8 cm^2 Cu
HSD- 4 Layer
HsLsD-footprint
HsLsD-2 cm^2 Cu
HsLsD-8 cm^2 Cu
HsLsD-4 Layer
0.1
1
10
100
0.001 0.01 0.1 1 10 100 1000
time (sec)
°C/W
LSD-footprint
LSD-2 cm^2 Cu
LSD-8 cm^2 Cu
LSD-4 Layer
LsLsD-footprint
LsLsD-2 cm^2 Cu
LsLsD-8 cm^2 Cu
LsLsD-4 Layer
Z
ls
Z
lsls
Package and PCB thermal data VNH5050A-E
28/33 Doc ID 16009 Rev 11
Figure 21. Thermal fitting model of an H-bridge in PowerSSO-36
Table 19. Thermal parameters
(1)
1. The blank space means that the value is the same as the previous one.
Area/island (cm
2
) Footprint 2 8 4L
R1 = R7 (°C/W) 0.4
R2 = R8 (°C/W) 2
R3 (°C/W) 8
R4 (°C/W) 30 16 16 10
R5 (°C/W) 40 22 12 5
R6 (°C/W) 36 28 10 6
R9 = R15 (°C/W) 0.1
R10 = R16 (°C/W) 3.6
R11 = R17 (°C/W) 22 14 14 14
R12 = R18 (°C/W) 49 30 30 20
R13 = R19 (°C/W) 52 36 28 16
R14 = R20 (°C/W) 50 32 26 18
R21 = R22 (°C/W) 80 60 50 40
R23 (°C/W) 80 50 45 30
C1 = C7 = C9 = C15 (W.s/°C) 0.0005
C2 = C8 (W.s/°C) 0.008
C3 (W.s/°C) 0.09
C4 (W.s/°C) 0.5 0.8 0.8 0.8
C5 (W.s/°C) 0.8 1.4 2 3
C6 (W.s/°C) 5 6 8 10
C10 = C16 (W.s/°C) 0.009
C11 = C17 (W.s/°C) 0.07
C12 = C18 ( W.s/°C) 0.45 0.4 5 0.45 0.6
C13 = C19 (W.s/°C) 0.8 1 1 .2 2.5
C14 = C20 (W.s/°C) 4 5 6 8
C21 = C22 = C23 (W.s/°C) 0.01 0.006 0.005 0.005
VNH505 0A-E Package and packing information
Doc ID 16009 Rev 11 29/33
5 Package and packing information
5.1 ECOPACK
®
pa ckages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
5.2 PowerSSO-36 TP package information
Figure 22. PowerSSO-36 TP package dimensions
Package and packing information VNH5050A-E
30/33 Doc ID 16009 Rev 11
Table 20. PowerSSO-36 TP mechanical data
Symbol Millimeters
Min. Typ. Max.
A2.15-2.47
A2 2.15 - 2.40
a1 0 - 0.1
b0.18-0.36
c0.23-0.32
D 10.10 - 10.50
E 7.4 - 7.6
e-0.5-
e3 - 8.5 -
F2.3
G- -0.1
H10.1-10.5
h--0.4
k 0 deg 8 deg
L0.6- 1
M4.3
N--10 deg
O1.2
Q0.8
S2.9
T3.65
U1.0
X1 1.85 2.35
Y1 3 3.5
X2 1.85 2.35
Y2 3 3.5
X3 4.7 - 5.2
Y3 3 - 3.5
Z1 0.4
Z2 0.4
VNH505 0A-E Package and packing information
Doc ID 16009 Rev 11 31/33
5.3 PowerSSO-36 TP packing information
Figure 23. PowerSSO-36 TP tube shipment (no suffix)
Figure 24. PowerSSO-36 TP tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Qty 49
Bulk Qty 1225
Tube length (±0.5) 532
A3.5
B13.8
C (±0.1) 0.6
A
CB
Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F20.2
G (+2 / -0) 24.4
N (min) 100
T (max ) 30.4
Reel dimensions
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 12
Hole Diameter D (±0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (±0.1) 11.5
Compartment D ep th K (max) 2.85
Hole Spacing P1 (±0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500m m m i n 500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
Revision history VNH5050A-E
32/33 Doc ID 16009 Rev 11
6 Revision history
Table 21. Document revision history
Date Revision Description of changes
06-Jul-2009 1 Initial release.
15-Sep-2009 2
Updated
Figure 1: Block diagram
.
Updated following tables:
–
Table 2: Block description
–
Table 6: Absolute maximum ratings
–
Table 8: Power section
–
Table 11: Protections and diagnostics
–
Table 12: Current sense (9 V < V
CC
<18V)
–
Table 14: Truth table in fault conditions (detected on OUTA)
Updated
Chapter 3: Application information
.
Modified
Table 12: Current sense (9 V < V
CC
<18V)
.
02-Dec-2009 3
Updated following tables:
–
Table 8: Power section
–
Table 10: Switching (V
CC
=13V, R
LOAD
= 1.5
Ω
)
–
Table 11: Protections and diagnostics
–
Table 12: Current sense (9 V < V
CC
<18V)
Added
Chapter 4: Package and PCB thermal data
16-Dec-2009 4 Updated
Table 4: Pin definitions and functions
02-Mar-2010 5 Updated
Table 14: Truth table in fault conditions (detected on
OUTA)
.
30-Apr-2010 6 Updated following tables:
–
Table 10: Switching (V
CC
=13V, R
LOAD
= 1.5
Ω
)
–
Table 11: Protections and diagnostics
30-Jun-2010 7
Updated following tables:
–
Table 7: Thermal data
–
Table 8: Power section
–
Table 12: Current sense (9 V < V
CC
<18V)
05-Jul-2010 8 Updated
Table 19: Thermal parameters
.
19-Oct-2010 9 Updated
Table 12: Current sense (9 V < V
CC
<18V)
Updated
Section 4.1.3: Thermal calculation in transient mode
Added
Figure 18: Detailed chipset configuration
22-Dec-2011 10
Updated
Figure 1: Block diagram
Added
Table 3: Suggested connections for unused and not
connected pins
Table 11: Protections and diagnostics
:
–T
TSD
, T
TR
, T
HYST
: added note
Updated
Figure 9: Waveforms in full-bridge operation
and
Figure 10: Waveforms in full-bridge operation (continued)
19-Sep-2013 11 Updated Disclaimer.
VNH5050A-E
Doc ID 16009 Rev 11 33/33
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