5-91
5
MODULATORS AND
UPCONVERTERS
Preliminary
Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS
üSiGe HBT Si CMOS
1VGC
2VCC2
3MOD+
4MOD-
5
ISIG+
6
ISIG-
7
QSIG+
8
QSIG-
9 LO-
10 LO+
12 NC
13
VCC1
14
AGC DEC
15
ISET
16
PD
Gain Control
S
Quad
/2
11 BG OUT
RF9678
W-CDMA TRANSMIT MODULATOR AND IF AGC
• W-CDMA Systems
• EDGE Systems • CDMA Systems
• TDMA Systems
The RF9678 is an integrated complete quadrature modu-
lator and IF AGC amplifier designed for the transmit sec-
tion of W-CDMA applications. It is designed to modulate
baseband I and Q signals, and amplify the resulting IF
signals while providing 55dB of gain control range. This
circuit is designed as part of RFMD’s single mode
W-CDMA Chipset, which also includes the RF2679
W-CDMA Receive IF AGC and Demodulator. The IC is
manufactured on an advanced Silicon Bi-CMOS process,
and is supplied in a16-pin leadless chip carrier.
• Digitally Controlled Power Down Modes
• 2.7V to 3.3V Operation
• Digital LO Quadrature Divider
• AGC Linearity/Current Consumption Var.
•IFAGCAmpwith55dBGainControl
RF9678 W-CDMA Transmit Modulator and IF AGC
RF9678 PCBA Fully Assembled Evaluation Board
5
Rev A4 010622
Dimensions in mm.
1.85
1.55 sq.
.60
.24 typ
.75
.50 .23
.13
4 PLCS
.65
.30
4 PLCS
4.00
sq.
2.35
.23
.65
.05
.01
12°
max
1.00
0.85
.80
.65
NOTES:
Shaded Pin is Lead 1.1
5 Die thickness allowable: 0.305 mm max.
Package Warpage: 0.05 max.
4
Pin 1 identifier must exist on top surface of package by identification mark or
feature on the package body. Exact shape and size is optional.
3
Dimension applies to plated terminal and is measured between 0.02 mm and
0.25 mm from terminal end.
2
Package Style: LCC, 16-Pin, 4x4
Preliminary
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MODULATORS AND
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Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage -0.5 to +5 VDC
Power Down Voltage (VPD) -0.5toV
CC+0.7 V
I and Q Levels, per pin 1.2 VPP
LO1 Level, balanced +3 dBm
Operating Ambient Temperature -40 to +85 °C
Storage Temperature -40 to +150 °C
Parameter Specification Unit Condition
Min. Typ. Max.
Overall T=25°C, VCC=3.0V; ZLOAD=200Ω;
I=Q=500mVPP, 1000mVPP Differential;
Output externally matched
I/Q Input Frequency Range 0 to 10 MHz Balanced
I/Q Input Impedance 20 kΩBalanced
I/Q Input Reference Level 1.3 VDC Per Pin
LO1 Frequency Range 0 to 1200 MHz
LO1 Input Level -15 -8 -5 dBm Specifications
LO1 Input Impedance 200 ΩBalanced (Evaluation Board Schematic)
2kΩBalanced, IC input
Sideband Suppression 45 50 dBc I/Q Amplitude adjusted to within ±20mV
25 30 dBc Unadjusted
Carrier Suppression 45 50 dBc I/Q DC Offset adjusted to within ±20mV
20 28 dBc Unadjusted
IF=380MHz I=Q=500mVPP, 1000mVPP Differential;
LO1=760MHz; Output externally matched
Max Output Power, W-CDMA
Mode -6 -4.5 -3 dBm W-CDMA ACPR=-50dBc, VGC=2.4VDC,
T=-20°C to+85°C
Min Output Power, CDMA Mode -63 -59 -56 dBm VGC=0.2VDC
Output Power Accuracy -3 +3 dB T=-20 to +85°C, Ref=25°C
Adjacent Channel Power Rejec-
tion @ 5MHz -46 dBc W-CDMA Modulation, VGC=0.2VDC to
2.4VDC
Adjacent Channel Power Rejec-
tion @ 10MHz -56 dBc W-CDMA Modulation, VGC=0.2VDC to
2.4VDC
Output Noise Power -135 dBm/Hz @ 20MHz offset, VGC=2.4VDC
Output Impedance 200 ΩBalanced
IF=570MHz I=Q=700mVPP, 1400mVPP Differential;
LO1=1140MHz; Output externally matched
Max Output Power, W-CDMA
Mode -4 dBm W-CDMA ACPR=-50dBc, VGC=2.4VDC,
T=-20°C to+85°C
Adjacent Channel Power Rejec-
tion @ 5MHz -46 dBc W-CDMA Modulation, VGC=0.2VDC to
2.4VDC
Adjacent Channel Power Rejec-
tion @ 10MHz -56 dBc W-CDMA Modulation, VGC=0.2VDC to
2.4VDC
Power Supply
Supply Voltage 2.7 3.0 3.3 V
Current Consumption 30 39 46 mA Over temperature
Power Down Current <10 µA
VPD HIGH Voltage VCC-1.0 V
VPD LOW Voltage 0.9 V
Gain Control Range 0.2 2.4 V
VGC Current 40 µA
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Preliminary
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MODULATORS AND
UPCONVERTERS
Pin Function Description Interface Schematic
1VGC
Analog gain control for AGC amplifiers. Valid control voltage ranges are
from 0.2VDC to 2.4VDC. The gain range for the AGC is 55dB. These
voltages are valid ONLY for a 39kΩsource impedance. A DC voltage
less than or equal to the maximum allowable VCC may be applied to
this pin when no voltage is applied to the VCC pins.
2VCC2
DC supply. This pin should be bypassed to ground with a 10nF capaci-
tor.
3MOD+
Same as pin 4, except complementary output. See pin 4.
4MOD-
One half of the balanced AGC output port. The impedance of this port
is 200Ωbalanced. This pin requires an inductor to VCC to achieve full
dynamic range. In order to maximize gain, this inductor should be a
high-Q type and should be parallel resonated out with a capacitor (see
application schematic). This pin is NOT DC blocked. A blocking capaci-
tor of 2200pF is needed when this pin is connected to a DC path. An
appropriate matching network may be needed if an IF filter is used.
5 I SIG+ One half of the balanced baseband input to the I mixer. This pin is DC-
coupled and must be supplied with 1.3VDC to bias the input transistor.
Input impedance of this pin is 10kΩminimum. For maximum carrier
suppression, DC voltage on this pin relative to ISIG- DC voltage may be
adjusted. (In case a balun is needed, a seperate balun board (RD0102
PCBA) could be ordered as an accessory.)
See pin 8.
6 I SIG- One half of the balanced baseband input to the I mixer. This pin is DC-
coupled and must be supplied with 1.3VDC to bias the input transistor.
Input impedance of this pin is 10kΩminimum. For maximum carrier
suppression, DC voltage on this pin relative to ISIG+ DC voltage may
be adjusted.
7 Q SIG+ One half of the balanced baseband input to the Q mixer. This pin is DC-
coupled and must be supplied with 1.3VDC to bias the input transistor.
Input impedance of this pin is 10kΩminimum. For maximum carrier
suppression, DC voltage on this pin relative to QSIG- DC voltage may
be adjusted.
See pin 10.
8 Q SIG- One half of the balanced baseband input to the Q mixer. This pin is DC-
coupled and must be supplied with 1.3VDC to bias the input transistor.
Input impedance of this pin is 10kΩminimum. For maximum carrier
suppression, DC voltage on this pin relative to QSIG+ DC voltage may
be adjusted.
9LO-
One half of the balanced modulator LO1 input. In single-ended applica-
tions (100Ωinput impedance), this pin is AC grounded with a 1nF
capacitor.
See pin 10.
10 LO+ One half of the balanced modulator LO1 input. The other half of the
input, LO1-, is AC grounded for single-ended input applications. The
frequency on these pins is divided by a factor of 2, hence the carrier
frequency for the modulator becomes one half of the applied frequency.
The single-ended input impedance is 1kΩ(balanced is 2kΩ). This pin
is NOT internally DC blocked. An external blocking capacitor (1nF rec-
ommended) must be provided if the pin is connected to a device with
DC present.
11 BG OUT Bandgap voltage reference. This voltage, constant over temperature
and supply variation, is used to bias internal circuits. A 10nF external
bypass capacitor is required.
12 NC No connection.
13 VCC1 DC supply. This pin should be bypassed to ground with a 10nF capaci-
tor.
14 AGC DEC AGC decoupling pin. An external bypass capacitor of 10nF capacitor is
required. The trace length between the pin and the bypass capacitors
should be minimized. The ground side of the bypass capacitors should
connect immediately to ground plane.
VGC
BIAS
BIAS BIAS
MOD OUT-
MOD OUT+
I SIG-I SIG+
Q SIG-Q SIG+
LO1+,
FM+ LO1-,
FM-
BIAS BIAS
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MODULATORS AND
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Pin Function Description Interface Schematic
15 ISET Connected to ground through an external resistor. The value can be
varied to change the current in the AGC for optimum linearity and cur-
rent consumption.
16 PD Power down control for overall circuit. When logic “high” (≥VCC-0.7V),
all circuits are operating; when logic “low” (≤0.5V), all circuits are
turned off. The input impedance of this pin is >10kΩ. A DC voltage less
than or equal to the maximum allowable VCC may be applied to this pin
when no voltage is applied to the VCC pins.
Pkg
Base GND Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias.
PD
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MODULATORS AND
UPCONVERTERS
Application Notes
Quadrature modulator performance can be correlated to a set of specifications known as Carrier and Sideband Suppres-
sion. In addition, Sideband Suppression can be correlated with the amplitude and phase balance of the In-Phase (I) and
Quadrature (Q) signals and Carrier Suppression can be correlated to the DC offset between the I and Q signals (see Fig-
ure 1). For a more thorough discussion of the theory and mathematics behind these specifications refer to RF Micro
Devices application note AN0001.
Effects of Carrier Suppression and Sideband Suppression on W-CDMA (QPSK) Modulation
W-CDMA signals may be displayed on a vector signal analyzer as a collection of points called a constellation. Each point
in the constellation is called a symbol and is representative of a bit sequence. In QPSK modulation, there are four sym-
bols and each symbol is representative of two data bits (see Figure 2). The I and Q signals are added together to create
a vector of precise phase and amplitude. The vector is then sampled at a rate called the symbol rate and it's position at
these intervals corresponds to the target symbol locations. Errors in the phase and amplitude of the I and Q signals will
translate to errors in the vector's phase and amplitude. This phase and amplitude error will result in a displacement of the
vector from it's target symbol point. A measurement of this error is called the Error Vector Magnitude (EVM) and it repre-
sents the magnitude of the displacement of the actual vector from it's target location.
QPSK constellation points exist on a circle of constant radius around the origin. Amplitude errors result in symbol points
being displaced either inside or outside of their target locations on this circle. Phase errors result in symbol points being
displaced on an arc either to the left or right of their target location. Finally, DC offset errors cause the origin to shift,
resulting in a constant I and Q offset of all target points (see Figure 3).
Σ
In-Phase Signal
Quadrature Signal
LO Signal
RF Output Signal
0° 90°
Figure 1. Quadrature Modulator Block Diagram
Ref Lvl
0dBm
0dBm
Ref Lvl
0dBm
0dBm
A
-1.875 1.875REAL
CF 380 MHz Meas Signal
Constellation
Constellation
IMAG
T1 EXT
SR 3.84 MHz Demod QPSK
-1.5
1.5
Date: 6.FEB.2001 01:20:38
Figure 2. W-CDMA (QPSK) Constellation
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MODULATORS AND
UPCONVERTERS
As is shown above, the EVM performance of a modulator can be correlated to it's carrier and sideband suppression per-
formance.
Unadjusted Performance
A Wideband CDMA signal is a noise-like signal occupying a channel bandwidth of 3.84MHz. When viewed on a spec-
trum analyzer the channel appears as a plateau raised above the noise floor (see Figure 4). In some cases, it is normal
to see a spike over the center of the W-CDMA plateau. This will occur when the absolute power level of the unadjusted
carrier feedthrough is higher than that of the W-CDMA channel level. The cause of this phenomenon can be understood
by examining the relative powers of the carrier signal and the W-CDMA channel power.
For Example, a 1Hz channel with a power of 0dBm has an absolute power level of 0dBm when viewed on a spectrum
analyzer. When that 0dBm channel power is spread over a 3.84MHz channel, as in W-CDMA, it results in an absolute
channel power level of -65.8dBm (-10*log (BW)). The absolute channel level displayed on the spectrum analyzer will
increase with the resolution bandwidth setting on the instrument although the integrated channel power will remain con-
stant. A resolution bandwidth (RBW) of 30kHz will increase the displayed power level by 44.7dB (+10*log(RBW)) to -
21.0dBm. With a desired signal output power of +2.0dBm and a carrier suppression of >20dBc, the absolute carrier level
canbeashighas-18.0dBm(P
OUT-Suppression=Carrier Level). This will result in a 3dB carrier spike above the W-
CDMA channel level (see Figure 4). (Note: The relative height of the carrier spike above the W-CDMA channel level is
directly related to the RBW of the spectrum analyzer being used. The example above assumes a 30kHz RBW.)
The following equations may be used to calculate W-CDMA channel and carrier feedthrough levels.
W-CDMA Channel Level=Channel Power (Integrated over BW)-[10*log*(BW)]+[10*log*(RBW)]
Carrier Feedthrough=POUT (Desired Sideband)-Carrier Suppression
The next section describes a procedure that may be used to dramatically reduce carrier feedthrough by tuning or opti-
mizing the modulator input signals.
A
CF 380 MHz
SR 3.84 MHz Meas Signal
Constellation
Constellation
Demod QPS
K
IMAG
T1
-1.875 1.875REAL
EXT
Ref Lvl
0dBm
0dBm
Ref Lvl
0dBm
0dBm
-1.5
1.5
Date: 6.FEB.2001 00:38:12
Figure 3. DC Offset Error (Carrier Feedthrough)
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MODULATORS AND
UPCONVERTERS
Adjusted Performance
In theory, an ideal quadrature modulator will completely suppress the carrier and sideband signals. In practice, due to
process and packaging effects, real quadrature modulators lack the balance necessary to completely cancel the carrier
and sideband signals. The imbalance caused by process and packaging effects is usually very small and may be cor-
rected by preadjusting the input signals to the modulator. This process of adjusting the input signals to minimize the car-
rier and sideband suppression is known as optimization.
Sideband suppression results from the summing together of the I and Q channel mixer outputs. In an ideal quadrature
modulator, at the summing point the sideband signals from the I and Q mixers are 180° out of phase and have equal
magnitudes. In a real modulator, the amplitude and phase are not exactly balanced and 100% cancellation does not
occur. The problem is corrected by introducing amplitude and phase corrections before applying a signal to the modula-
tor. Maximum sideband suppression is achieved when the amplitude and phase errors introduced by the modulator are
compensated for.
Complete carrier suppression occurs when there is no DC offset between the mixer signal input and the mixer reference
voltage (i.e., ISIG+ and ISIG-). In real devices, zero DC offset is difficult to achieve. This problem is corrected by intro-
ducing a DC offset of equal and opposite magnitude before applying the signal to the modulator. The internal error is
thereby canceled and maximum carrier suppression is achieved.
A
SWT 2 s Unit dBm
1R
M
RBW 30 kHz
VBW 300 kHzRef Lvl
-3 dBm
Ref Lvl
-3 dBm
RF Att 20 dB
1.46848 MHz/Center 380 MHz Span 14.6848 MHz
EXT
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
1
Marker 1 [T1]
-21.97 dBm
380.01503006 MHz
1 [T1] -21.97 dBm
380.01503006 MHz
CH PWR -2.62 dBm
ACP Up -50.30 dB
ACP Low -49.72 dB
cu1 cu1
cl1 cl1 C0 C0
Date: 6.FEB.2001 00:47:49
Figure 4. W-CDMA Spectral Plot
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UPCONVERTERS
Procedure for RF9678 Quadrature Modulator/AGC Optimization
1) Configure the test bench as shown in Figure 5.
2) Apply VCC to the part. (VCC=3.0V)
3) Set gain control to maximum. (VGC=2.4V)
4) Apply the LO signal. (760MHz@-5dBm, for an IF out of 380MHz)
5) Apply the I+ and Q+ signals: (Single Ended)
I Signal: 150kHz@ 500mVp, Phase=0°, 1.3V DC Offset
Q signal: 150kHz@ 500mVp, Phase =90°, 1.3V DC Offset
6) Set the DC levels at ISIG-andQ
SIG- input pins to the nominal value (1.3V). The output spectrum should look similar to
Figure 6.
HP6624A or Equiv
DC Power Supply
Output 3
(VGC)
HPE4422B or Equiv
Analog Signal
Generator
(LO)
HP8904 or Equiv
Multifunction Signal
Generator
(Sine, I+ and Q+)
HP66332A or Equiv
DC Power Supply
(VCC, PD)
Rhode and
Schwartz FSIQ7 or
Equiv, Spectrum
Analyzer
9678410
MOD
OUT
LO Q-
I-
I+
Q+
VGC
VCC
HP6624A or Equiv
DC Power Supply
Outputs 1 and 2
(VREF)
PD
Figure 5. RF9678 Test Setup
A
SWT 2 s Unit dBm
1R
M
Ref Lvl
15 dBm
Ref Lvl
15 dBm
RF Att 40 dB
32.5 kHz/Center 380 MHz Span 325 kHz
EXT
RBW 5 kHz
VBW 50 kHz
-80
-70
-60
-50
-40
-30
-20
-10
0
10
Date: 6.FEB.2001 00:54:00
Figure 6. Unassigned Single Sideband Output
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MODULATORS AND
UPCONVERTERS
Carrier Suppression Optimization
7) While maintaining a constant DC level (1.3V) on the "ISIG-" pin, adjust the DC level of the "ISIG+" input in as small an
increment (~1.0mV) as the test equipment will allow. Observe the output on the spectrum analyzer. Adjust the DC level
until the carrier signal is at a minimum. Typically, the minimum will occur within a ±20mV window of the reference voltage
(1.3±0.02V).
8) While maintaining a constant DC level (1.3V) on the "QSIG-" pin, adjust the DC level of the "QSIG+" input in as small
an increment as the test equipment will allow (1.0mV). Observe the output on the spectrum analyzer. Adjust the DC level
until the carrier signal is at a minimum. Typically, the minimum will occur within a ±20mV window of the reference voltage
(1.3±0.02V).
9) Repeating Steps 7 and 8 may yield slightly better suppression. The output spectrum should look similar to Figure 7.
(Note the suppressed carrier signal.)
Sideband Suppression Optimization
10) Adjust the AC amplitude of the "ISIG+" signal in as small an increment as the test equipment will allow (~1mV).
Observe the output of the spectrum analyzer. Adjust the AC amplitude of the signal until the sideband signal is at a mini-
mum. The minimum sideband signal level should occur within ±20mV adjustment. (0.500±0.02V)
11) Adjust the AC amplitude of the "QSIG+" signal in as small an increment as the test equipment will allow (~1mV).
Observe the output of the spectrum analyzer. Adjust the AC amplitude of the signal until the sideband signal is at a mini-
mum. The minimum sideband signal level should occur within ±20mV adjustment (0.500±0.02V).
12) Adjust the phase of the "QSIG+" signal in as small an increment as the test equipment will allow (`0.1°). Observe the
output of the spectrum analyzer. Adjust the phase of the "QSIG+" signal until the sideband suppression is at a minimum.
The sideband signal should reach a minimum within ±1° of adjustment (90±1°).
13) The device is now optimized for maximum carrier and sideband suppression. The output spectrum should look simi-
lar to Figure 8. (Note the suppressed carrier and sideband signals.)
A
Unit dBm
1R
M
Ref Lvl
15 dBm
Ref Lvl
15 dBm
RF Att 40 dB
32.5 kHz/Center 380 MHz Span 325 kHz
EXT
RBW 5 kHz
VBW 50 kHz
SWT 33 ms
-80
-70
-60
-50
-40
-30
-20
-10
0
10
1
Marker 1 [T1]
0.22 dBm
379.84987475 MHz
Date: 6.FEB.2001 00:55:31
Figure 7. Optimized Carrier Suppression
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MODULATORS AND
UPCONVERTERS
A
Unit dBm
1R
M
Ref Lvl
15 dBm
Ref Lvl
15 dBm
RF Att 40 dB
32.5 kHz/Center 380 MHz Span 325 kHz
EXT
RBW 5 kHz
VBW 50 kHz
SWT 33 ms
-80
-70
-60
-50
-40
-30
-20
-10
0
10
1
Marker 1 [T1]
0.21 dBm
379.84987475 MHz
Date: 6.FEB.2001 00:57:07
Figure 8. Optimized Carrier and Sideband Suppression
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Pin Out
Application Schemat i c
1VGC
2VCC2
3MOD+
4MOD-
5
ISIG+
6
ISIG-
7
QSIG+
8
QSIG-
9 LO-
10 LO+
12 NC
13
VCC1
14
AGC DEC
15
ISET
16
PD
11 BG OUT
10 nF
VCC
10 pF15 nH
2200 pF
MOD+
VCC
10 pF
2200 pF
MOD-
VCC
39 kΩ
VGC
1nF
VPD
1500
Ω10 nF VCC
10 nF
10 nF
1nF
1nF LO IN
ISIG+
15 nH QSIG+
1
2
3
4
5 6 7 8
9
10
11
12
13141516
Gain Control
Σ
Quad
/2
QSIG-
ISIG-
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MODULATORS AND
UPCONVERTERS
Evaluat ion Board Schemat ic
(Download Bill of Materials from www.rfmd.com.)
C1
R1
39 kΩ
VGC
VPD
R3
1500 ΩC4
10 nF
C3
10 nF
VCC
T1
1:4
VCCNC
50 Ωµstrip
J1
MOD
T2
4:1 50 Ωµstrip J6
LO IN
R2
200 Ω
C2
10 nF
50 Ωµstrip J5
QSIG-
50 Ωµstrip J4
QSIG+
50 Ωµstrip
J2
ISIG+
50 Ωµstrip
J3
ISIG-
GND
P1-2 VCC1
P1-1 PD
P1
1
2
3
CON3
GND
GND
P2-1 VGC
P2
1
2
3
CON3
1
2
3
4
5 6 7 8
9
10
11
12
13141516
Gain Control
Σ
Qua
d
/2
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UPCONVERTERS
Evaluation Board Layout
Board Size 2.0” x 2.0”
Board Thickness 0.031”, Board Material FR-4
Preliminary
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UPCONVERTERS
ICC versus VGC
(1 VP-P, 380 MHz)
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
0.0 0.5 1.0 1.5 2.0 2.5
VGC (VDC)
I
CC
(mA)
+25C
POUT versus VIN
(VGC =2.4V
DC
,
380 Mhz, W-CDMA)
-16
-14
-12
-10
-8
-6
-4
-2
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VIN (VPDifferential)
P
OUT
(dbm)
(25°C)
Performance versus VBIAS
VIN=300mVPP (Differential)
0.00
10.00
20.00
30.00
40.00
50.00
60.00
1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10
VBIAS (VDC)
ACPR (dBc)
-30.00
-25.00
-20.00
-15.00
-10.00
-5.00
0.00
Channel Power Out (dBm)
ACPup (dbc)
ACPlow (dbc)
ALTup (dbc)
ALTlow (dbc)
ChPout (dbm)
ACPR versus VGC (W-CDMA, 3GPP, Temp. +25oC, - 40oC, +85oC)
(LO Freq. 760MHz@-8dBm, VCC=3.0V, VGC=2.4 to 0.2V)
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC (V)
Adjacent Channel Power (dBc)
ACPR [dBc]@ +25C
ACPR [dBc]@ - 40C
ACPR [dBc]@ +85C
Channel Output Power versus VGC
(W-CDMA-3GPP, Temp. +25oC)
(LO Freq. 760MHz@-8dBm,VCC=2.7, 3.0, 3.3V, VGC=2.4 to 0.2V)
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC (V)
Channel Output Power (dBm)
Ch.Power out [dBm] @ 3V
Ch.Power out [dBm] @ 2.7V
Ch.Power out [dBm] @ 3.3V
Altr. Channel Power versus VGC
(W-CDMA-3GPP, Temp. +25oC, -40oC,+85oC)
(LO Freq. 760MHz@-8dBm, VCC=3.0V, VGC=2.4V to 0.2V)
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC (V)
Alternate Channel Power (dBc)
ALTR.Ch.Power [dBc] @ +25C
ALTR.Ch.Power[dBc] @ - 40C
ALTR.Ch.Power[dBc] @ +85C
Preliminary
5-105
RF9678
Rev A4 010622
5
MODULATORS AND
UPCONVERTERS
IGC versus VGC
(LO Freq. 760MHz@-8dBm, VCC=VPD=3.0V, VGC=2.4 to 0.2V)
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
5.0
10.0
15.0
20.0
25.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC (V)
I
GC
(uA)
Igc [uA]
Channel Output Power versus VGC
(W-CDMA 3GPP, Temp.+25oC, -40oC,+85oC)
(LO Freq. 760MHz@-8dBm, VCC=3.0V, VGC=2.4 to 0.2V)
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC (V)
Channel Output Power (dBm)
Ch.Power out [dBm]@ +25C
Ch.Power out [dBm]@ - 40C
Ch.Power out [dBm]@ +85C
EVM versus VGC
(W-CDMA-3GPP, Temp. +25oC, - 40oC, +85oC)
(LO Freq. 760MHz@-8dBm, VCC=3.0V, VGC=2.4 to 1.0V)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
1.01.21.41.61.82.02.22.4
VGC (V)
EVM (%)
EVM [%] @ +25C
EVM [%] @ - 40C
EVM [%] @ +85C
Preliminary
5-106
RF9678
Rev A4 010622
5
MODULATORS AND
UPCONVERTERS
