RF9678 Preliminary 5 W-CDMA TRANSMIT MODULATOR AND IF AGC Typical Applications * W-CDMA Systems * CDMA Systems * EDGE Systems * TDMA Systems 1.00 0.85 .80 .65 The RF9678 is an integrated complete quadrature modulator and IF AGC amplifier designed for the transmit section of W-CDMA applications. It is designed to modulate baseband I and Q signals, and amplify the resulting IF signals while providing 55dB of gain control range. This circuit is designed as part of RFMD's single mode W-CDMA Chipset, which also includes the RF2679 W-CDMA Receive IF AGC and Demodulator. The IC is manufactured on an advanced Silicon Bi-CMOS process, and is supplied in a16-pin leadless chip carrier. 4.00 sq. .60 .24 typ .65 .30 4 PLCS .35 2 .23 1.85 1.55 sq. .75 .50 12 max .05 .01 .23 .13 .65 4 PLCS Dimensions in mm. NOTES: 1 Shaded Pin is Lead 1. Dimension applies to plated terminal and is measured between 0.02 mm and 2 0.25 mm from terminal end. 3 Pin 1 identifier must exist on top surface of package by identification mark or feature on the package body. Exact shape and size is optional. 4 Package Warpage: 0.05 max. 5 Die thickness allowable: 0.305 mm max. Optimum Technology Matching(R) Applied Si BJT GaAs MESFET SiGe HBT Si CMOS ISET AGC DEC VCC1 16 15 14 13 VGC 1 Gain Control VCC2 2 S MOD+ 3 Package Style: LCC, 16-Pin, 4x4 Features * Digitally Controlled Power Down Modes PD uSi Bi-CMOS GaAs HBT * 2.7V to 3.3V Operation * Digital LO Quadrature Divider 12 NC * AGC Linearity/Current Consumption Var. 11 BG OUT * IF AGC Amp with 55dB Gain Control 10 LO+ Quad /2 5 6 7 8 I SIG- Q SIG+ Q SIG- 9 LO- I SIG+ MOD- 4 Functional Block Diagram Rev A4 010622 Ordering Information RF9678 RF9678 PCBA W-CDMA Transmit Modulator and IF AGC Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA 5 MODULATORS AND UPCONVERTERS Product Description Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 5-91 RF9678 Preliminary Absolute Maximum Ratings Parameter Supply Voltage Power Down Voltage (VPD) I and Q Levels, per pin LO1 Level, balanced Operating Ambient Temperature Storage Temperature Parameter MODULATORS AND UPCONVERTERS 5 Rating Unit -0.5 to +5 -0.5 to VCC + 0.7 1.2 +3 -40 to +85 -40 to +150 VDC V VPP dBm C C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit Overall I/Q Input Frequency Range I/Q Input Impedance I/Q Input Reference Level LO1 Frequency Range LO1 Input Level LO1 Input Impedance Sideband Suppression Carrier Suppression 0 to 10 20 1.3 MHz k VDC 45 25 45 20 0 to 1200 -8 200 2 50 30 50 28 -6 -4.5 -3 dBm -63 -3 -59 -56 +3 -46 dBm dB dBc -56 dBc -15 -5 MHz dBm k dBc dBc dBc dBc IF=380MHz Max Output Power, W-CDMA Mode Min Output Power, CDMA Mode Output Power Accuracy Adjacent Channel Power Rejection @ 5MHz Adjacent Channel Power Rejection @ 10MHz Output Noise Power Output Impedance -135 200 dBm/Hz -4 dBm IF=570MHz Max Output Power, W-CDMA Mode Adjacent Channel Power Rejection @ 5MHz Adjacent Channel Power Rejection @ 10MHz -46 dBc -56 dBc 3.3 46 <10 V mA A V V V A Condition T=25 C, VCC =3.0V; ZLOAD =200; I=Q=500mVPP, 1000mVPP Differential; Output externally matched Balanced Balanced Per Pin Specifications Balanced (Evaluation Board Schematic) Balanced, IC input I/Q Amplitude adjusted to within 20mV Unadjusted I/Q DC Offset adjusted to within 20mV Unadjusted I=Q=500mVPP, 1000mVPP Differential; LO1=760MHz; Output externally matched W-CDMA ACPR=-50dBc, VGC =2.4VDC, T=-20C to +85C VGC =0.2VDC T=-20 to +85 C, Ref=25 C W-CDMA Modulation, VGC =0.2VDC to 2.4VDC W-CDMA Modulation, VGC =0.2VDC to 2.4VDC @ 20MHz offset, VGC =2.4VDC Balanced I=Q=700mVPP, 1400mVPP Differential; LO1=1140MHz; Output externally matched W-CDMA ACPR=-50dBc, VGC =2.4VDC, T=-20C to +85C W-CDMA Modulation, VGC =0.2VDC to 2.4VDC W-CDMA Modulation, VGC =0.2VDC to 2.4VDC Power Supply Supply Voltage Current Consumption Power Down Current VPD HIGH Voltage VPD LOW Voltage Gain Control Range VGC Current 5-92 2.7 30 3.0 39 VCC-1.0 0.2 0.9 2.4 40 Over temperature Rev A4 010622 RF9678 Preliminary Function VGC 2 VCC2 3 4 MOD+ MOD- 5 I SIG+ 6 I SIG- 7 Q SIG+ 8 Q SIG- 9 LO- 10 LO+ 11 BG OUT 12 13 NC VCC1 14 AGC DEC Rev A4 010622 Description Interface Schematic Analog gain control for AGC amplifiers. Valid control voltage ranges are from 0.2VDC to 2.4VDC. The gain range for the AGC is 55dB. These voltages are valid ONLY for a 39k source impedance. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. BIAS VGC DC supply. This pin should be bypassed to ground with a 10nF capacitor. Same as pin 4, except complementary output. See pin 4. One half of the balanced AGC output port. The impedance of this port is 200 balanced. This pin requires an inductor to VCC to achieve full dynamic range. In order to maximize gain, this inductor should be a high-Q type and should be parallel resonated out with a capacitor (see application schematic). This pin is NOT DC blocked. A blocking capacitor of 2200pF is needed when this pin is connected to a DC path. An appropriate matching network may be needed if an IF filter is used. One half of the balanced baseband input to the I mixer. This pin is DCcoupled and must be supplied with 1.3VDC to bias the input transistor. Input impedance of this pin is 10k minimum. For maximum carrier suppression, DC voltage on this pin relative to ISIG- DC voltage may be adjusted. (In case a balun is needed, a seperate balun board (RD0102 PCBA) could be ordered as an accessory.) One half of the balanced baseband input to the I mixer. This pin is DCcoupled and must be supplied with 1.3VDC to bias the input transistor. Input impedance of this pin is 10k minimum. For maximum carrier suppression, DC voltage on this pin relative to ISIG+ DC voltage may be adjusted. BIAS BIAS MOD OUTMOD OUT+ 5 See pin 8. I SIG+ One half of the balanced baseband input to the Q mixer. This pin is DC- See pin 10. coupled and must be supplied with 1.3VDC to bias the input transistor. Input impedance of this pin is 10k minimum. For maximum carrier suppression, DC voltage on this pin relative to QSIG- DC voltage may be adjusted. One half of the balanced baseband input to the Q mixer. This pin is DCcoupled and must be supplied with 1.3VDC to bias the input transistor. Q SIG+ Input impedance of this pin is 10k minimum. For maximum carrier suppression, DC voltage on this pin relative to QSIG+ DC voltage may be adjusted. One half of the balanced modulator LO1 input. In single-ended applica- See pin 10. tions (100 input impedance), this pin is AC grounded with a 1nF capacitor. One half of the balanced modulator LO1 input. The other half of the BIAS input, LO1-, is AC grounded for single-ended input applications. The LO1+, frequency on these pins is divided by a factor of 2, hence the carrier FM+ frequency for the modulator becomes one half of the applied frequency. The single-ended input impedance is 1k (balanced is 2k). This pin is NOT internally DC blocked. An external blocking capacitor (1nF recommended) must be provided if the pin is connected to a device with DC present. Bandgap voltage reference. This voltage, constant over temperature and supply variation, is used to bias internal circuits. A 10nF external bypass capacitor is required. No connection. MODULATORS AND UPCONVERTERS Pin 1 I SIG- Q SIG- BIAS LO1-, FM- DC supply. This pin should be bypassed to ground with a 10nF capacitor. AGC decoupling pin. An external bypass capacitor of 10nF capacitor is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. 5-93 RF9678 Pin 15 Function ISET 16 PD Pkg Base GND Preliminary Description Connected to ground through an external resistor. The value can be varied to change the current in the AGC for optimum linearity and current consumption. Power down control for overall circuit. When logic "high" (VCC -0.7V), all circuits are operating; when logic "low" (0.5V), all circuits are turned off. The input impedance of this pin is >10k. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. Interface Schematic PD Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. MODULATORS AND UPCONVERTERS 5 5-94 Rev A4 010622 RF9678 Preliminary Application Notes Quadrature modulator performance can be correlated to a set of specifications known as Carrier and Sideband Suppression. In addition, Sideband Suppression can be correlated with the amplitude and phase balance of the In-Phase (I) and Quadrature (Q) signals and Carrier Suppression can be correlated to the DC offset between the I and Q signals (see Figure 1). For a more thorough discussion of the theory and mathematics behind these specifications refer to RF Micro Devices application note AN0001. In-Phase Signal RF Output Signal Quadrature Signal 90 Figure 1. Quadrature Modulator Block Diagram Effects of Carrier Suppression and Sideband Suppression on W-CDMA (QPSK) Modulation W-CDMA signals may be displayed on a vector signal analyzer as a collection of points called a constellation. Each point in the constellation is called a symbol and is representative of a bit sequence. In QPSK modulation, there are four symbols and each symbol is representative of two data bits (see Figure 2). The I and Q signals are added together to create a vector of precise phase and amplitude. The vector is then sampled at a rate called the symbol rate and it's position at these intervals corresponds to the target symbol locations. Errors in the phase and amplitude of the I and Q signals will translate to errors in the vector's phase and amplitude. This phase and amplitude error will result in a displacement of the vector from it's target symbol point. A measurement of this error is called the Error Vector Magnitude (EVM) and it represents the magnitude of the displacement of the actual vector from it's target location. CF SR Ref Lvl 0 dBm 380 MHz Meas Signal 3.84 MHz Constellation Demod QPSK 1.5 A IMAG T1 EXT -1.5 -1.875 Date: REAL 6.FEB.2001 1.875 01:20:38 Figure 2. W-CDMA (QPSK) Constellation QPSK constellation points exist on a circle of constant radius around the origin. Amplitude errors result in symbol points being displaced either inside or outside of their target locations on this circle. Phase errors result in symbol points being displaced on an arc either to the left or right of their target location. Finally, DC offset errors cause the origin to shift, resulting in a constant I and Q offset of all target points (see Figure 3). Rev A4 010622 5-95 MODULATORS AND UPCONVERTERS 5 0 LO Signal RF9678 Preliminary CF SR Ref Lvl 0 dBm 380 MHz Meas Signal 3.84 MHz Constellation Demod QPSK 1.5 A IMAG T1 EXT -1.5 -1.875 MODULATORS AND UPCONVERTERS 5 Date: REAL 6.FEB.2001 1.875 00:38:12 Figure 3. DC Offset Error (Carrier Feedthrough) As is shown above, the EVM performance of a modulator can be correlated to it's carrier and sideband suppression performance. Unadjusted Performance A Wideband CDMA signal is a noise-like signal occupying a channel bandwidth of 3.84MHz. When viewed on a spectrum analyzer the channel appears as a plateau raised above the noise floor (see Figure 4). In some cases, it is normal to see a spike over the center of the W-CDMA plateau. This will occur when the absolute power level of the unadjusted carrier feedthrough is higher than that of the W-CDMA channel level. The cause of this phenomenon can be understood by examining the relative powers of the carrier signal and the W-CDMA channel power. For Example, a 1Hz channel with a power of 0dBm has an absolute power level of 0dBm when viewed on a spectrum analyzer. When that 0 dBm channel power is spread over a 3.84MHz channel, as in W-CDMA, it results in an absolute channel power level of -65.8 dBm (-10*log (BW)). The absolute channel level displayed on the spectrum analyzer will increase with the resolution bandwidth setting on the instrument although the integrated channel power will remain constant. A resolution bandwidth (RBW) of 30kHz will increase the displayed power level by 44.7dB (+10*log(RBW)) to 21.0dBm. With a desired signal output power of +2.0dBm and a carrier suppression of >20dBc, the absolute carrier level can be as high as -18.0dBm (POUT-Suppression=Carrier Level). This will result in a 3dB carrier spike above the WCDMA channel level (see Figure 4). (Note: The relative height of the carrier spike above the W-CDMA channel level is directly related to the RBW of the spectrum analyzer being used. The example above assumes a 30kHz RBW.) The following equations may be used to calculate W-CDMA channel and carrier feedthrough levels. W-CDMA Channel Level=Channel Power (Integrated over BW)-[10*log*(BW)]+[10*log*(RBW)] Carrier Feedthrough=POUT (Desired Sideband)-Carrier Suppression The next section describes a procedure that may be used to dramatically reduce carrier feedthrough by tuning or optimizing the modulator input signals. 5-96 Rev A4 010622 RF9678 Preliminary Ref Lvl -3 dBm Marker 1 [T1] -21.97 dBm 380.01503006 MHz RBW VBW SWT 30 kHz 300 kHz 2 s 1 [T1] 20 dB Unit -21.97 380.01503006 CH PWR -2.62 ACP Up -50.30 ACP Low -49.72 -10 1 -20 RF Att dBm dBm A MHz dBm dB dB -30 1RM -40 EXT -50 -60 -70 -80 C0 C0 -90 cl1 cl1 cu1 cu1 Center 380 MHz Date: 6.FEB.2001 1.46848 MHz/ 5 Span 14.6848 MHz 00:47:49 Figure 4. W-CDMA Spectral Plot Adjusted Performance In theory, an ideal quadrature modulator will completely suppress the carrier and sideband signals. In practice, due to process and packaging effects, real quadrature modulators lack the balance necessary to completely cancel the carrier and sideband signals. The imbalance caused by process and packaging effects is usually very small and may be corrected by preadjusting the input signals to the modulator. This process of adjusting the input signals to minimize the carrier and sideband suppression is known as optimization. Sideband suppression results from the summing together of the I and Q channel mixer outputs. In an ideal quadrature modulator, at the summing point the sideband signals from the I and Q mixers are 180 out of phase and have equal magnitudes. In a real modulator, the amplitude and phase are not exactly balanced and 100% cancellation does not occur. The problem is corrected by introducing amplitude and phase corrections before applying a signal to the modulator. Maximum sideband suppression is achieved when the amplitude and phase errors introduced by the modulator are compensated for. Complete carrier suppression occurs when there is no DC offset between the mixer signal input and the mixer reference voltage (i.e., ISIG+ and ISIG-). In real devices, zero DC offset is difficult to achieve. This problem is corrected by introducing a DC offset of equal and opposite magnitude before applying the signal to the modulator. The internal error is thereby canceled and maximum carrier suppression is achieved. Rev A4 010622 5-97 MODULATORS AND UPCONVERTERS -100 RF9678 Preliminary Procedure for RF9678 Quadrature Modulator/AGC Optimization 1) Configure the test bench as shown in Figure 5. HPE4422B or Equiv Analog Signal Generator (LO) HP8904 or Equiv Multifunction Signal Generator (Sine, I+ and Q+) Q- LO Q+ HP66332A or Equiv DC Power Supply (VCC, PD) VCC PD 9678410 VGC I- I+ MOD OUT HP6624A or Equiv DC Power Supply Outputs 1 and 2 (VREF) MODULATORS AND UPCONVERTERS 5 Rhode and Schwartz FSIQ7 or Equiv, Spectrum Analyzer HP6624A or Equiv DC Power Supply Output 3 (VGC) Figure 5. RF9678 Test Setup 2) Apply VCC to the part. (VCC =3.0V) 3) Set gain control to maximum. (VGC =2.4V) 4) Apply the LO signal. (760MHz@-5dBm, for an IF out of 380MHz) 5) Apply the I+ and Q+ signals: (Single Ended) I Signal: 150kHz@ 500mVp, Phase=0, 1.3V DC Offset Q signal: 150kHz@ 500mVp, Phase =90, 1.3V DC Offset 6) Set the DC levels at ISIG- and QSIG- input pins to the nominal value (1.3V). The output spectrum should look similar to Figure 6. RBW VBW SWT Ref Lvl 15 dBm 5 kHz 50 kHz 2 s RF Att Unit 40 dB dBm A 10 0 -10 1RM -20 -30 EXT -40 -50 -60 -70 -80 Center 380 MHz Date: 6.FEB.2001 32.5 kHz/ Span 325 kHz 00:54:00 Figure 6. Unassigned Single Sideband Output 5-98 Rev A4 010622 RF9678 Preliminary Carrier Suppression Optimization 7) While maintaining a constant DC level (1.3V) on the "ISIG-" pin, adjust the DC level of the "ISIG+" input in as small an increment (~1.0mV) as the test equipment will allow. Observe the output on the spectrum analyzer. Adjust the DC level until the carrier signal is at a minimum. Typically, the minimum will occur within a 20mV window of the reference voltage (1.30.02V). 8) While maintaining a constant DC level (1.3V) on the "QSIG-" pin, adjust the DC level of the "QSIG+" input in as small an increment as the test equipment will allow (1.0mV). Observe the output on the spectrum analyzer. Adjust the DC level until the carrier signal is at a minimum. Typically, the minimum will occur within a 20mV window of the reference voltage (1.30.02V). 9) Repeating Steps 7 and 8 may yield slightly better suppression. The output spectrum should look similar to Figure 7. (Note the suppressed carrier signal.) Ref Lvl 15 dBm Marker 1 [T1] 0.22 dBm 379.84987475 MHz RBW VBW SWT 5 kHz 50 kHz 33 ms RF Att Unit 40 dB dBm 5 A 10 MODULATORS AND UPCONVERTERS 1 0 -10 1RM -20 -30 EXT -40 -50 -60 -70 -80 Center 380 MHz Date: 6.FEB.2001 32.5 kHz/ Span 325 kHz 00:55:31 Figure 7. Optimized Carrier Suppression Sideband Suppression Optimization 10) Adjust the AC amplitude of the "ISIG+" signal in as small an increment as the test equipment will allow (~1mV). Observe the output of the spectrum analyzer. Adjust the AC amplitude of the signal until the sideband signal is at a minimum. The minimum sideband signal level should occur within 20mV adjustment. (0.5000.02V) 11) Adjust the AC amplitude of the "QSIG+" signal in as small an increment as the test equipment will allow (~1mV). Observe the output of the spectrum analyzer. Adjust the AC amplitude of the signal until the sideband signal is at a minimum. The minimum sideband signal level should occur within 20mV adjustment (0.5000.02V). 12) Adjust the phase of the "QSIG+" signal in as small an increment as the test equipment will allow (0.1). Observe the output of the spectrum analyzer. Adjust the phase of the "QSIG+" signal until the sideband suppression is at a minimum. The sideband signal should reach a minimum within 1 of adjustment (901). 13) The device is now optimized for maximum carrier and sideband suppression. The output spectrum should look similar to Figure 8. (Note the suppressed carrier and sideband signals.) Rev A4 010622 5-99 RF9678 Preliminary Ref Lvl 15 dBm Marker 1 [T1] 0.21 dBm 379.84987475 MHz RBW VBW SWT 5 kHz 50 kHz 33 ms RF Att Unit 40 dB dBm A 10 1 0 -10 1RM -20 -30 EXT -40 -50 -60 -70 -80 MODULATORS AND UPCONVERTERS 5 Center 380 MHz Date: 6.FEB.2001 32.5 kHz/ Span 325 kHz 00:57:07 Figure 8. Optimized Carrier and Sideband Suppression 5-100 Rev A4 010622 RF9678 Preliminary PD ISET AGC DEC VCC1 Pin Out 16 15 14 13 VGC 1 12 NC VCC2 2 11 BG OUT MOD+ 3 10 LO+ MOD- 4 9 LO8 5 MODULATORS AND UPCONVERTERS Q SIG- 7 Q SIG+ 6 I SIG- I SIG+ 5 Application Schematic VPD 1 nF VCC 1500 10 nF VGC 10 nF 39 k VCC 16 1 15 14 13 12 Gain Control 10 nF 10 nF 2 VCC 11 2200 pF 15 nH 1 nF 3 10 Quad /2 10 pF 1 nF 4 MOD+ 9 5 VCC LO IN 6 7 8 Q SIG- 2200 pF MOD- Rev A4 010622 15 nH 10 pF Q SIG+ I SIGI SIG+ 5-101 RF9678 Preliminary Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) P1 P2 P1-1 1 PD 1 VGC P1-2 2 VCC1 2 GND 3 GND 3 GND P2-1 VPD CON3 VCC C3 10 nF CON3 R3 1500 16 MODULATORS AND UPCONVERTERS 5 VGC 1 R1 39 k J1 MOD T1 1:4 50 strip C4 10 nF 15 J3 I SIG- 5-102 C2 10 nF 11 Qua d /2 4 J2 I SIG+ 12 2 VCC C1 13 Gain Control 3 NC 14 5 6 10 9 7 T2 4:1 50 strip J6 LO IN R2 200 8 50 strip 50 strip 50 strip 50 strip J5 Q SIGJ4 Q SIG+ Rev A4 010622 RF9678 Preliminary Evaluation Board Layout Board Size 2.0" x 2.0" Board Thickness 0.031", Board Material FR-4 MODULATORS AND UPCONVERTERS 5 Rev A4 010622 5-103 RF9678 Preliminary ICC versus VGC (1 VP-P, 380 MHz) 50.0 POUT versus VIN (VGC = 2.4VDC, 380 Mhz, W-CDMA) 0 5 -2 40.0 -4 35.0 -6 POUT (dbm) ICC (mA) +25C 45.0 30.0 -8 25.0 -10 20.0 -12 15.0 -14 10.0 -16 (25C) MODULATORS AND UPCONVERTERS 0.0 0.5 1.0 1.5 2.0 2.5 0 0.1 0.2 VGC (VDC) 0.3 0.4 0.5 0.6 0.7 VIN (VP Differential) ACPR versus VGC (W-CDMA, 3GPP, Temp. +25oC, - 40oC, +85oC) (LO Freq. 760MHz@-8dBm, VCC=3.0V, VGC=2.4 to 0.2V) Performance versus VBIAS VIN=300mVPP (Differential) 60.00 0.00 0.0 ACPR [dBc] @ +25C 50.00 -5.00 40.00 -10.00 30.00 -15.00 -40.0 20.00 -20.00 -50.0 10.00 ACPR [dBc] @ - 40C -20.0 -30.0 -60.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 ACPup (dbc) ACPlow (dbc) ALTup (dbc) ALTlow (dbc) ChPout (dbm) 0.00 1.00 1.10 2.4 -25.00 -30.00 1.20 1.30 1.40 1.50 VGC (V) 1.60 1.70 1.80 1.90 2.00 2.10 VBIAS (VDC) Altr. Channel Power versus VGC o o Channel Output Power versus VGC (W-CDMA-3GPP, Temp. +25oC) (LO Freq. 760MHz@-8dBm,VCC=2.7, 3.0, 3.3V, VGC=2.4 to 0.2V) o (W-CDMA-3GPP, Temp. +25 C, -40 C, +85 C) (LO Freq. 760MHz@-8dBm, VCC=3.0V, VGC=2.4V to 0.2V) 0.0 Channel Power Out (dBm) ACPR [dBc] @ +85C ACPR (dBc) Adjacent Channel Power (dBc) -10.0 0.0 Ch.Power out [dBm] @ 3V ALTR.Ch.Power [dBc] @ +25C Ch.Power out [dBm] @ 2.7V -10.0 -10.0 Ch.Power out [dBm] @ 3.3V ALTR.Ch.Power[dBc] @ +85C -20.0 Channel Output Power (dBm) Alternate Channel Power (dBc) ALTR.Ch.Power[dBc] @ - 40C -30.0 -40.0 -50.0 -60.0 -20.0 -30.0 -40.0 -50.0 -70.0 -60.0 -80.0 -90.0 -70.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VGC (V) 5-104 1.4 1.6 1.8 2.0 2.2 2.4 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VGC (V) Rev A4 010622 RF9678 Preliminary IGC versus VGC Channel Output Power versus VGC (LO Freq. 760MHz@-8dBm, VCC=VPD=3.0V, VGC=2.4 to 0.2V) (W-CDMA 3GPP, Temp.+25 C, -40 C, +85 C) (LO Freq. 760MHz@-8dBm, VCC=3.0V, VGC=2.4 to 0.2V) o 25.0 0.0 20.0 Igc [uA] o Ch.Power out [dBm] @ +25C -10.0 Channel Output Power (dBm) 15.0 10.0 5.0 IGC (uA) o 0.0 -5.0 -10.0 -15.0 Ch.Power out [dBm] @ - 40C Ch.Power out [dBm] @ +85C -20.0 -30.0 -40.0 -50.0 -20.0 -60.0 -25.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VGC (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VGC (V) EVM versus VGC (W-CDMA-3GPP, Temp. +25oC, - 40oC, +85oC) (LO Freq. 760MHz@-8dBm, VCC=3.0V, VGC=2.4 to 1.0V) 12.0 EVM [%] @ +25C EVM [%] @ - 40C EVM [%] @ +85C 10.0 EVM (%) 8.0 6.0 4.0 2.0 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VGC (V) Rev A4 010622 5-105 MODULATORS AND UPCONVERTERS 5 -70.0 -30.0 RF9678 Preliminary MODULATORS AND UPCONVERTERS 5 5-106 Rev A4 010622