INNOVATIVE IM1225Y-150 8K X 8 Nonvolatile SRAM FEATURES Data Retention in the absence of power * Pin configuration Automatic data protection during power failure * Data Retention over 10 years * Unlimited write cycles * Conventional SRAM write cycles * Low power CMOS - only 225mW active * Equal read/write cycle times * +5V only read/write * Operating voltage range +10% * Direct replacement for 8K X 8 SRAM NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 or EPROM * Standard 28 pin DIP JEDEC Pinout PIN NAMES Functional Description The IM 1225Y-150 is a 65,536 bit, fully static NP RAM organized as 8K X 8 using CMOS and an internal lithium energy source. This `NO POWER' RAM has all the normal characteristics of a CMOS static RAM with an important benefit of data being retained in the absence of power. Data retention current is so small that a miniature lithium cell contained within the package provides an energy source to preserve data. Protection against data loss has also been incorporated to maintain data integrity during power on/off conditions. The IM 1225Y-150 RAM can be directly used in place of existing static RAMs. There is no limit to the number of write cycles that can be executed and no additional support circuitry is required for interface to a microprocessor. NC OE Gnd I/O0 - I/O7 Vcc WE A0 - A12 No Connection Output Enable Ground Data in/ Data Out Power Supply +5V Write Enable Address Inputs CE Chip Enable INNOVATIVE MICROTECHNOLOGY INC.Phone/Fax-440-322-8083.Website:www.innovativemicrotechnology.com INNOVATIVE IM1225Y-150 8K X 8 Nonvolatile SRAM READ MODE The IM 1225Y-150 performs a read cycle whenever WE high and CE low. The unique address specified by the 13 address inputs A0-A12 defines which of the 8,192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within access time tACC after the last address input is stable, provided that CE and OE access times are satisfied. If OE or CE access times are not satisfied, data access will be measured from the limiting parameter (tCO or tOE), rather than address.The state of the eight data I/O lines is controlled by the OE and CE control signals. The data lines may be in an indeterminate state between tOH and tAA but the data lines will always have valid data at tAA. WRITE MODE The IM 1225Y-150 is in the write mode whenever CE and WE inputs are held low. The latter occurring falling edge of either CE or WE determines the start of a write cycle. A write is terminated by the earlier rising edge of CE or WE. The address must be held valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another Read or Write cycle can be initiated. CE or WE is high during power on to protect memory after Vcc reaches Vcc (min) but before the processor stabilizes. DATA RETENTION The IM 1225Y-150 provides full functional capability for Vcc greater than 4.5V and write protects at 4.25V. Data is retained in the absence of Vcc without any additional support circuitry. The SRAM constantly monitors Vcc. The moment Vcc decays, the RAM automatically write protects itself. All inputs to the RAM become "don't care" and all outputs are in high impedance-state. As Vcc falls below approximately 3.0V the power switching circuit connects the lithium energy source to RAM to retain data. During power-on, when Vcc rises above approximately 3.0V the power switching circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc becomes greater than 4.5V. Maximum Ratings Operating Temperature....0oC to 70oC Storage Temperature.......0oC to 70oC Soldering Temperature And Time......................260oC for 10 sec Supply Voltage...................0V to 7.0V Input Voltage..................-0.3V to 7.0V Input/ Output Voltage.......-0.3V to Vcc + 0.3V Power Dissipation............1.0W Recommended D.C. Operating Conditions Parameter Symbol Min. Supply Voltage Vcc 4.5 Gnd 0 Input Voltage Typ 5.0 - Max. 5.5 0 Unit V V Vcc +0.3 0.8 V V VIH 2.2 - VIL 0 - INNOVATIVE IM1225Y-150 8K X 8 Nonvolatile SRAM DC Electrical Characeteristics Parameter Description IIL IOCA Input Leakage Vi = 0 to Vcc Average operating Current CE = VIH CE = VIH,IIO = 0mA Operating Supply current CE = VIL, IIO = 0mA Output Leakage CE = VIH or Vcc Vi/o = Gnd to Vcc High level output voltage IOH = - 1.0 mA Low level output voltage IOL = 2.1 mA Write protection voltage -I Ivcc ILO VOH VOL VTP Test conditons Min. Typ Max Unit -1 -1 45 1 - 1 80 3 45 1 A A mA mA A 2.4 4.25 Vcc - 0.1 0.2 0.4 4.37 4.49 V V V Notes 1. Typical values are measured at Ta = 25o C and Vcc = 5V Capacitance Parameter Description Test conditons Min. Typ Max Unit CADD CI CI/O Address capacitance Input capacitance I/O capacitance VADD = 0V Vi =0V VIO = 0V - 3 5 6 5 6 7 pF pF pF INNOVATIVE IM1225Y-150 8K X 8 Nonvolatile SRAM Switching Characteristics over the operating range Parameter Description Min Max tRC tACC tOE tCO tCOE tOD tOH 150 5 5 150 60 150 40 - ns ns ns ns ns ns ns 150 0 70 10 35 - ns ns ns ns ns ns ns ns tWC tAW tWP tWR tODW tOEW tDS tDH Read cycle time Address access time Output enable access time CE to output valid OE or CE to output valid Output High Z from Deselection Output hold from adds change Write cycle time Address setup time Write pulse-width Write recovery time Output High Z from WE Output Active from WE Input data setup time Input data hold time 5 50 10 Unit INNOVATIVE IM1225Y-150 8K X 8 Nonvolatile SRAM READ CYCLE tRC VIH VIH Address VIL VIL tACC tOH tCO VIH CE VIH VIL tOD tOE VIH OE VIH VIL tOD tCOE DOUT VOH VOH tCOE OUTPUT DATA VALID VOL VOL WRITE CYCLE 1 tWC ADDRESS VIH VIH VIL VIL tAW CE VIL VIL tWP WE VIH VIL tODW tWR VIL tOEW High Impedance DOUT tDS VIH DIN VIL tDH VIH Data In Stable VIL INNOVATIVE IM1225Y-150 8K X 8 Nonvolatile SRAM tWC WRITE CYCLE 2 ADDRESSES VIH VIH VIL VIL tAW tWR2 tWP CE VIH WE VIL VIL VIL VIL tCOE tODW DOUT tDS VIH DIN VIL FIG. D VIH tDH Data In Stable VIH VIL POWER - DOWN/ POWER -ON CONDITION 4.75V -------------------------------------------------------------------------------------------------- tF tR 3.2V ---------------------------------------------------------------------------------------------------- tPD LI Cell Leakage Current tREC Data Retention Time tDR Notes: 1. 2. 3. WE is to be high during read cycle. During write cycle that is controlled by CE, output buffer is in high impedance state irrespective of whether OE is high or low level. During write cycle that is controlled by WE, output buffer is in high impedance state if OE is high. INNOVATIVE IM1225Y-150 8K X 8 Nonvolatile SRAM INNOVATIVE IM 1225Y - 150 NO POWER SRAM mm - yy B J H A C F G D DIM IN INCHES MIN. MAX. A B C D E F G H J 1.54 0.72 0.415 0.13 0.021 0.16 0.11 0.63 0.012 1.52 0.695 0.395 0.1 0.015 0.12 0.09 0.59 0.008 E