1/40June 2003
M29W160ET
M29W160EB
16 Mbit (2Mb x8 or 1Mb x16, Boot Block)
3V S uppl y Fl ash Memory
FEATURES SUMM ARY
SUPPLY VOLTAGE
–V
CC = 2.7V to 3.6V for Program, Erase and
Read
ACCESS TIME: 70, 90ns
PRO GRAMMING TI ME
10µs per Byte/Word typical
35 MEMORY BLOCKS
1 Boot Block (Top or Bottom Locat ion)
2 Parameter and 32 Main Blocks
PROGRAM/E RA SE CONTROLLER
Embedded Byt e/Word Program algorithms
ERASE SUSPEND and RESUM E MOD ES
Read and Program another Block during
Erase Su spend
UNLOCK BYPASS PROGRAM COMMAND
Fas ter Production/Batc h Prog ramm ing
TEMPORARY BLOCK UNPROT ECTION
MODE
COMMON FLASH INTE RFACE
64 bit Security Code
LOW POWER CONSUM PTION
Standby and Autom atic Standby
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
Manufacturer Code: 0020h
Top Device Code M29W160ET: 22C4h
Bottom Device Code M29W160EB : 2249h
Figure 1. Packages
TSOP48 (N)
12 x 20mm
TFBGA48 (ZA)
6 x 8mm
FBGA
M29W160ET, M29W160EB
2/40
TABLE OF CONT ENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TFBGA Connect ions (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
Addre ss Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
D ata Inputs/Ou tputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
D ata Inputs/Ou tputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
D ata Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Out put Enabl e (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
W rite Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
R eady/Busy Out put (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
Byte/W ord Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VCC Supply Volt age. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Disab le. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Autom at ic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Special Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ele ctronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Protection and Blocks Unp rotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Bus Operations, BYTE = V IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
R ead/Res et Comm and.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Auto Se lect Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
C hip Erase Comm and. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase S uspend Com ma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
3/40
M29W160ET, M29W160EB
R ead CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Table 4. Comm and s, 16-bit mode, BYT E = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Comm and s, 8-bit mode, B Y TE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Program , Erase Times and Prog ram, Erase Enduranc e Cyc les . . . . . . . . . . . . . . . . . . . . 17
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Toggl e Bit (DQ6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8
Alternative Tog gle Bit (DQ2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9
Figure 8. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Operating and AC M easurem ent Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Device Capacitanc e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
Figure 12. Write AC Wav eforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. Write AC Characteristics, Ch ip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PAC KAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 26
Table 16. TSOP48 – 48 lead Plast ic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 26
Figure 16. TFBGA4 8 6x8mm - 6x8 ball array, 0.80 mm pitch, Packag e Outline. . . . . . . . . . . . . . . 27
Table 17. TF BG A48 6x8 mm - 6x8 ball array, 0.80 mm pitch, Package Mechan ical Data. . . . . . . . 27
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 19. Top Boot Block Addres ses, M29 W160E T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20. Bottom Boot Block Addresses, M29W160 EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
M29W160ET, M29W160EB
4/40
APPENDIX B. COMMON FLASH INTER FACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 22. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 23. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 24. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 25. Pri mary Algorithm -Spe cific Extende d Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 26. Secu rity Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
APPENDIX C. BLOCK PROTEC TION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Programmer Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
In-System Techniq ue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4
Table 27. Prog ramm er Techni que Bu s Operations , BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. Progra mmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. Programmer Equipment Chip Unprotect Flowcha rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20. In-System Equipment Chip Unprotect Flowcha rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 28. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5/40
M29W160ET, M29W160EB
SUMMARY DESCRIPTION
The M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is pos sible to preserv e
valid data while old dat a is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. P rogram and Eras e com m ands are wri t-
ten to the Com mand Interface of t he memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of al l of the special operations that are
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Figures 5 and 6, Block Addresses.
The first or last 64 KBy tes have been divided into
four additional blocks. The 16 KByte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 KByte Parameter
Blocks can be us ed for parameter st orage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic .
The memory is offered TSOP48 (12 x 20mm) and
TFBGA48 (0.8mm pitch) packages. The memory
is supplied with all the bits erased (set to ’1’).
Figu re 2. Lo gi c D iag ram Tab le 1. S i gn a l Nam es
AI06849B
20
A0-A19
W
DQ0-DQ14
VCC
M29W160ET
M29W160EB
E
VSS
15
G
RP
DQ15A–1
RB
BYTE
A0-A19 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
EChip Enable
GOutput Enable
WWrite Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
M29W160ET, M29W160EB
6/40
Figure 3. TSOP Connections
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A8
A9 DQ13
A17
A10 DQ14
A2
DQ12
DQ10
DQ15A–1
VCC
DQ4
DQ5
A7
DQ7
NC
NC
AI06850
M29W160ET
M29W160EB
12
1
13
24 25
36
37
48
DQ8
NC
A19
A1
A18
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
BYTE
A15
A14 VSS
E
A0
RP
VSS
7/40
M29W160ET, M29W160EB
Figure 4. TFBGA Connec tions (Top v iew through package)
AI02985B
654321
VSS
DQ15
A–1
A15
A14
A12
A13
DQ3
DQ11
DQ10
A18
NC
RB
DQ1
DQ9
DQ8
DQ0
A6
A17
A7
G
E
A0
A4
A3
DQ2
DQ6
DQ13
DQ14
A10
A8
A9
DQ4
VCC
DQ12
DQ5
A19
NC
RP
W
A11
DQ7
A1
A2
VSS
A5 NC
A16
BYTE
G
F
E
B
A
D
C
H
M29W160ET, M29W160EB
8/40
Figure 5. Block Addresses (x8)
Note: Also see A ppendix A, T ables 19 and 20 for a f ul l l is t i ng of the Bl ock Add resses .
AI06851
16 KByte
1FFFFFh
1FC000h
64 KByte
01FFFFh
010000h
64 KByte
00FFFFh
000000h
M29W160ET
Top Boot Block Addresses (x8)
32 KByte
1F7FFFh
1F0000h
64 KByte
1E0000h
1EFFFFh
Total of 31
64 KByte Blocks
16 KByte
1FFFFFh
1F0000h 64 KByte
64 KByte
003FFFh
000000h
M29W160EB
Bottom Boot Block Addresses (x8)
32 KByte
1EFFFFh
01FFFFh 64 KByte
1E0000h
010000h
Total of 31
64 KByte Blocks
00FFFFh
008000h
8 KByte
8 KByte
1FBFFFh
1FA000h
1F9FFFh
1F8000h
8 KByte
8 KByte
007FFFh
006000h
005FFFh
004000h
9/40
M29W160ET, M29W160EB
Figure 6. Block Addresses (x16)
Note: Also see A ppendix A, T ables 19 and 20 for a f ul l l is t i ng of the Bl ock Add resses .
AI06852
8 KWord
FFFFFh
FE000h
32 KWord
0FFFFh
08000h
32 KWord
07FFFh
00000h
M29W160ET
Top Boot Block Addresses (x16)
16 KWord
FBFFFh
F8000h
32 KWord
F0000h
F7FFFh
Total of 31
32 KWord Blocks
8 KWord
FFFFFh
F8000h 32 KWord
32 KWord
01FFFh
00000h
M29W160EB
Bottom Boot Block Addresses (x16)
16 KWord
F7FFFh
0FFFFh 32 KWord
F0000h
08000h
Total of 31
32 KWord Blocks
07FFFh
04000h
4 KWord
4 KWord
FDFFFh
FD000h
FCFFFh
FC000h
4 KWord
4 KWord
03FFFh
03000h
02FFFh
02000h
M29W160ET, M29W160EB
10/40
SIGNA L DESCRIPTIONS
See Figure 2, Logic Diag ram, and T able 1, Sign al
Names, for a brief overview of the s ignals connect -
ed to this device.
Address Inputs (A0-A19). The Address Inputs
select the cell s in the memory arra y to access dur-
ing Bus Read operations. During Bus Writ e opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the Program/
Erase Controller.
Data Inputs/Output s (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operati on when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bit s. When reading t he Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behav es as an address
pin; DQ15A–1 Low wil l select t he LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the t ext consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to inclu de this pin when B YTE is Low e xcept
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memor y, allowing Bus Read and Bus Wr ite op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols th e Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
ma nd Inte r face .
Reset/Block Temporary Unpro tect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardwar e Reset to the memory or
to temporarily u nprotect al l Block s that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, V IH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/ Busy
Output section, Table 15 and Figure 14, Reset/
Temporary Unprot ect AC Characte ristics for more
details.
Holding RP at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V OL. Ready/Busy is high-im-
pedance during Read mode, Auto Select mode
and Erase Suspend m ode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes h igh-impeda nc e. See Tabl e 15 and Figure
14, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain out put allows the Ready/
Busy pins from several memor ies to be connected
to a single pull-up resistor. A Low will then indicate
that one, or m ore, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch bet ween t he 8-bit and 16-bit Bus m odes of
the memory. When Byte/Word Organization Se-
lect is Low, VIL, the memory is in 8-bit mode, when
it is High , V IH, th e me mory is in 16 - bit mo de .
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is dis abled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevent s Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being alt ered will be invalid.
A 0.1µF capacitor should be connected between
the V CC Supply Voltage pin and the VSS Ground
pin to decoupl e the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operat ions, ICC3.
VSS Ground. The VSS Ground is the referenc e for
all v olt age measurements. The two VSS pins of the
device must be connected to the sy stem ground.
11/40
M29W160ET, M29W160EB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Wri te, Out-
put Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chi p Enable
or Write Enable are ignored by the memory and do
not affec t bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desi red address on the Address
Inputs, appl ying a Low s ig nal, VIL, to C hip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Input s/Ou tputs will outp ut the
value, see Figure 11, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desire d address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Dat a Input s/Outpu ts a re latched by the Com -
mand Interface on the rising edge of Chip Enab le
or Write Enable, whichever occurs first. Output En-
able must remai n High, VIH, du ring the whole Bus
Write operat ion. See Figures 12 and 13, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Outp ut Disable . The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For t he Standby current
level see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations un-
til the operat ion com pletes .
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operati ons. Additional bus opera-
tions can be pe rformed to read the Electronic Sig-
nature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming eq uipment and are not usu-
ally used in applications. They require VID to be
applied to some pins.
Electronic Sign atur e. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These co des can be re ad by app lying the signals
listed in T able s 2 and 3, Bus Operations.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Block Protect and Blocks Unprotect opera-
tions are described in Appendix C.
Table 2. Bus Operations, BYTE = VIL
No te: X = VIL or VIH.
Operation E G W Address Inputs
DQ15A–1, A0-A19 Data Inputs/Outputs
DQ14-DQ8 DQ7-DQ0
Bus Read VIL VIL VIH Cell Address Hi-Z Data Output
Bus Write VIL VIH VIL Command Address Hi-Z Data Input
Output Disable X VIH VIH X Hi-Z Hi-Z
Standby VIH X X X Hi-Z Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH Hi-Z 20h
Read Device Code VIL VIL VIH A0 = V IH, A1 = VIL, A9 = V ID,
Others VIL or VIH Hi-Z C4h (M29W160ET)
49h (M29W160EB)
M29W160ET, M29W160EB
12/40
Table 3. Bus Operations, BYTE = VIH
No te: X = VIL or VIH.
COMMAND INTERFACE
All Bus Write operations t o the memory are in ter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a vali d sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes de-
pending on whether the mem ory is in 16-bit or 8-
bit mode. See e ither Table 4, or 5, depending on
the configuration that is being used, for a summary
of the com m ands .
Read/Reset Comm and. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other-
wise s tated. It also resets t he errors in the S tatus
Register. Either one or three Bus Write operations
can be used to is sue the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or eras e o perati on
has started the Read/Res et comm and is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select com-
mand i s us ed to read the Man ufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored .
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A 0 = VIL and A1 = VIL. The other address bits
may be set to eith er VIL or VIH. The Ma nufa cturer
Code for STMicroelectronics is 0020h.
The Device Code can b e read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either V IL or VIH. The
Device Code for the M29W160ET is 22C4h and
for th e M 29W160EB is 2249h.
Th e Block P rotect ion St atus of each bloc k can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A12 -A 1 9 s p ecifyi ng th e addr ess of
th e block. The other address bits may be set to ei-
ther VIL or VIH. If th e addr ess ed bloc k is p rot ecte d
then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Progra m Command . The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data, and starts
the Program/ Erase Controll er.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the me mory will ig-
nore all co mmands. I t is not poss ible t o issue any
command to abort or pause the operation. Typical
program times are given in T able 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
Operation E G W Address Inputs
A0-A19 Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Bus Read VIL VIL VIH Cell Address Data Output
Bus Write VIL VIH VIL Command Address Data Input
Output Disable X VIH VIH X Hi-Z
Standby VIH X X X Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH 0020h
Read Device Code VIL VIL VIH A0 = V IH, A1 = VIL, A9 = V ID,
Others VIL or VIH 22C4h (M29W160ET)
2249h (M29W160EB)
13/40
M29W160ET, M29W160EB
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be i ssued to re-
set th e error condition and return to Read mode.
Note that t he Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Comman d. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program c ommand to program the memo-
ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass comm and.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Prog ram Comm an d. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data,
and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program c ommand behaves identically to the Pro-
gram operation using the Program command. A
protected block cannot be program m ed; the oper-
ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, w hich l eaves the de vice in Unlo ck By-
pass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Comman d. The Unlock
Bypass Re se t command can be used to ret urn to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected th en these are ig nored
and all the other blocks are erased. If all of the
blocks a re p rote cted the Chip Erase op erat i on ap-
pears to start but will terminate within about 100µs,
leaving the data unchange d. No error co ndition is
given when protected blocks are ignored.
During the erase operation the memory wi ll ignore
all commands. It is not poss ible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase opera tion has com pleted the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be i ssued to re-
set th e error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Wr ite operation using the addres s of the
additional block. The Bl ock Erase operation st arts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer r estarts when an additional block is select ed.
The Status Register can be read after the sixth
Bus Write operati on. See the Stat us Register sec-
tion for details on how to identify if the Program/
Erase Controller has started the Block Erase oper-
ation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to s tart but will
terminate within about 100µs, l eaving the data un-
changed. No error condition is given when protect-
ed blocks are igno red.
During the Blo ck Erase ope ra tion the me mory will
ignore all commands except the Erase Suspend
and Read/Reset commands. Typical block erase
times are given in Table 6. All Bus Read opera-
tions du ri ng the B lock Erase o peration will ou tput
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be i ssued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selec ted blocks to ’1’. All previous
data in the selected blocks is lost.
M29W160ET, M29W160EB
14/40
Erase Suspend Comm and. The Erase Suspend
Comman d may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Prog ram/Eras e Controlle r will sus pend within
the Erase Suspend Latency Time (refer t o Table 6
for value) of the Erase Suspend Com mand being
issued. Once the Program/Erase Controller has
stopped the memory will be set t o Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is susp ended i mmedi ately and wi ll start im-
mediately when the Erase Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protec ted bl ock or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condi tio n is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be i ssued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
Erase Resum e Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and res umed more than once.
Read CFI Query Comman d . The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
command is valid when the device i s in the Read
Array mode, or when the device is i n Autoselected
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequen t Bus Read ope ratio ns read from
the Common Flash Interface Memory Area .
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Aut oselect-
ed mode.
See Appendix B, Tables 21, 22, 23, 24, 25 and 26
for details on the information contained in the
Common Flash Interface (CFI) memory area.
15/40
M29W160ET, M29W160EB
Table 4. Commands, 16- bit mode, BYTE = VIH
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the tabl e are in he xadeci m al .
Th e Com ma nd In terf ace o nl y us es A –1, A0-A 10 a nd DQ 0-DQ7 t o ver ify t he com man ds; A1 1-A 19, DQ 8-DQ1 4 a nd DQ 15 ar e Don’ t
Care. DQ15A–1 i s A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Read/Reset. After a Read/Reset co m m and, read the m em ory a s normal until an other command is iss ued.
Auto Select. Aft er an Auto S elec t c om mand, read Manufact urer ID , Device ID or Block Protection Sta tus.
Pro gram , Unl ock By pass Progra m, Ch ip E rase, Blo ck Eras e . A fter these com mands read the S tatus Regi st er until t he Program /
Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional
Bus Write Operations until T i meout Bit is set.
Unlo ck Bypas s. After th e Unlock Bypas s command issue Unloc k B ypass Progr am or Unlo ck Bypa ss Reset commands.
Unlo ck Bypas s Re s et. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-
mands on no n-era sing bloc ks as nor m al .
Erase Resume. Af t er the Erase Resume comman d the suspended Er ase operati on resum es, read the Status Register until th e Pro-
gram/ Eras e Cont roll e r c o m pl e t es an d the mem o ry retur n s t o Re ad Mode.
CFI Qu e r y. Command is valid when devi ce is re ady to read array data or when de vice is in autose l ected m ode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program 2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 55 98
M29W160ET, M29W160EB
16/40
Table 5. Commands, 8-bi t mode, BYTE = VIL
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the tabl e are in he xadeci m al .
Th e Com ma nd In terf ace o nl y us es A –1, A0-A 10 a nd DQ 0-DQ7 t o ver ify t he com man ds; A1 1-A 19, DQ 8-DQ1 4 a nd DQ 15 ar e Don’ t
Care. DQ15A–1 i s A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Read/Reset. After a Read/Reset co m m and, read the m em ory a s normal until an other command is iss ued.
Auto Select. Aft er an Auto S elec t c om mand, read Manufact urer ID , Device ID or Block Protection Sta tus.
Pro gram , Unl ock By pass Progra m, Ch ip E rase, Blo ck Eras e . A fter these com mands read the S tatus Regi st er until t he Program /
Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional
Bus Write Operations until T i meout Bit is set.
Unlo ck Bypas s. After th e Unlock Bypas s command issue Unloc k B ypass Progr am or Unlo ck Bypa ss Reset commands.
Unlo ck Bypas s Re s et. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-
mands on no n-era sing bloc ks as nor m al .
Erase Resume. Af t er the Erase Resume comman d the suspended Er ase operati on resum es, read the Status Register until th e Pro-
gram/ Eras e Cont roll e r c o m pl e t es an d the mem o ry retur n s t o Re ad Mode.
CFI Qu e r y. Command is valid when devi ce is re ady to read array data or when de vice is in autose l ected m ode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
Program 2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 AA 98
17/40
M29W160ET, M29W160EB
Table 6. Program , Erase Times and Progra m , Erase Endu ran ce Cycles
No te : 1. Typ i cal values mea sured at room tempera tu re and no minal v ol tages.
2. Sampled, but not 100% tested.
3. Max imum valu e measu red at worst case conditions for both tem pera ture and V CC after 100,000 program/erase cycles .
4. Max imum valu e measu red at worst case conditions for both tem pera ture and V CC.
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is acce ssed .
The bits in the Status Register are s um marized in
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is re ad.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read oper ations from t he ad-
dress just programmed output DQ7, not its com-
plement.
During Erase ope rations the Data Po lling Bit out-
puts ’0’, the complement of the erased state of
DQ7. Aft er s uc cessful completion of the Erase op-
eration the memory returns to R ead Mod e.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change f rom a ’0’ to a ’1’ when the Program/Erase
Controller has sus pe nded the Erase operat ion.
Figure 7, Data Polling Flowcha rt, gives an exam-
ple of how to use the Data Polling Bit. A V alid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Togg le Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is re ad.
During Program and Erase operations the Toggle
Bit changes f rom ’0 ’ to ’ 1’ to ’ 0’, et c., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is ma de to erase a protected bl ock,
the o peration is aborted, no error i s sig nalled and
DQ6 toggles for approximately 100µs. If any at-
tempt is made to program a protected block or a
suspended b lock, the operatio n is aborted, no er-
ror is signalled and DQ6 toggles for approxi mately
1µs.
Figure 8 , Data Toggle Flowchart, g ives an exam-
ple of how to u se the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Rea d/Re se t comm and must be iss ued
before other command s are issued. The Error bit
is output on DQ5 when the Status Register is read.
Parameter Min Typ (1,2) Max(2) Unit
Chip Erase 29 120 (3) s
Block Erase (64 KBytes) 0.8 6 (4) s
Erase Suspend Latency Time 20 25 (4) µs
Program (Byte or Word) 13 200 (3) µs
Chip Program (Byte by Byte) 26 120 (3) s
Chip Program (Word by Word) 13 60 (3) s
Program/Erase Cycles (per Block) 100,000 cycles
Data Retention 20 years
M29W160ET, M29W160EB
18/40
Note that t he Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dres s w ill s how the bit is s ti ll ‘0’. On e of the E r as e
commands must be used to set all the bits in a
block or in the w hole m emo ry from ’0’ to ’1’
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Ti mer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional block s to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative T oggle Bit (D Q2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is re ad.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Re ad operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will ou tput
the memory cell data as i f in Read mode.
After an Erase operation that c auses t he Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or bl ocks have caused t he er-
ror. The Altern ative Toggle Bit ch anges from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
Table 7. Status Register Bits
No te : Unspecified da ta bits should be i gnore d.
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 ––0
Program During Erase
Suspend Any Address DQ7 Toggle 0 0
Program Error Any Address DQ7 Toggle 1 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Block Erase Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erase Suspend Erasing Block 1 No Toggle 0 Toggle 1
Non-Erasing Block Data read as normal 1
Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0
Faulty Block Address 0 Toggle 1 1 Toggle 0
19/40
M29W160ET, M29W160EB
Figu re 7. Da ta Po lli ng Fl owch a rt Fi gure 8. Dat a Toggle Flowchar t
MAX I MUM R A TI N G
Stressing the device ab ove t he rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above t hose indicat -
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Ratings
Note: 1. Minim um voltage may undershoot to –2V during transi tion and fo r l ess than 20ns duri ng trans i tions.
2. Max imum voltage may overshoot to V CC +2V duri ng trans i tion an d fo r l ess tha n 20ns duri ng transitions.
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
at VALID ADDRESS
FAIL PASS
AI03598
DQ7
=
DATA YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA YES
NO
READ DQ6
START
READ DQ6
TWICE
FAIL PASS
AI01370C
DQ6
=
TOGGLE NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
Symbol Parameter Min Max Unit
TBIAS Temperature Under Bias –50 125 °C
TSTG Storage Temperature –65 150 °C
VIO Input or Output Voltage (1,2) –0.6 VCC +0.6 V
VCC Supply Voltage –0.6 4 V
VID Identification Voltage –0.6 13.5 V
M29W160ET, M29W160EB
20/40
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, a nd the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 9, Operating and
AC Measurement Conditions. Designers should
check t hat the operating cond itions in their circuit
match the operating conditions when relying on
the quot ed parameters.
Table 9. Operating and AC Measurem en t Conditions
Figure 9. AC Measurement I/O Wavefo rm Figure 10. AC Measure ment Lo ad Circuit
Table 10. Device Capacitance
No te : Sam pled o n l y, not 100% tested.
Parameter
M29W160E
Unit70 90
Min Max Min Max
VCC Supply Voltage 2.7 3.6 2.7 3.6 V
Ambient Operati ng Temperatur e 4085–408C
Load Capacitance (CL)30 30 pF
Input Rise and Fall Times 10 10 ns
Input Pulse Voltages 0 to VCC 0 to VCC V
Input and Output Timing Ref. Voltages VCC/2 VCC/2 V
AI04498
VCC
0V
VCC/2
AI04499
CL
CL includes JIG capacitance
DEVICE
UNDER
TEST
25k
VCC
25k
VCC
0.1µF
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6pF
C
OUT Output Capacitance VOUT = 0V 12 pF
21/40
M29W160ET, M29W160EB
Table 11. DC Characteristics
Not e: 1. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Typ Max Unit
ILI Input Leakage Current 0V VIN VCC ±1 µA
ILO Output Leak age Curren t 0V VOUT VCC ±1 µA
ICC1 Supply Curre nt (Read) E = VIL, G = VIH,
f = 6MHz 4.5 10 mA
ICC2 Supply Curre nt (Standby) E = VCC ±0.2V,
RP = VCC ±0.2V 35 100 µA
ICC3 (1) Su pply Curre nt
(Program/Erase) Program/Erase
Controller active 20 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7VCC VCC +0.3 V
VOL Output Low Voltage IOL = 1.8mA 0.45 V
VOH Output High Voltage IOH = –100µAVCC –0.4 V
VID Identification Voltage 11.5 12.5 V
IID Identification Current A9 = VID 100 µA
VLKO Program/Erase Lockout
Supply Voltage 1.8 2.3 V