© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 3
1Publication Order Number:
NCP702/D
NCP702
200 mA, Ultra-Low Quiescent
Current, Ultra-Low Noise, LDO
Linear Voltage Regulator
Noise sensitive applications such as Phase Locked Loops,
Oscillators, Frequency Synthesizers, Low Noise Amplifiers and other
Precision Instrumentation require very clean power supplies. The
NCP702 is a 200 mA LDO that provides the engineer with a very
stable, accurate voltage with ultra−low noise and very high Power
Supply Rejection Ratio (PSRR), making it suitable for RF
applications. The device doesn’t require an additional noise bypass
capacitor to achieve ultra−low noise performance. In order to optimize
performance for battery operated portable applications, the NCP702
employs an Adaptive Ground Current feature for ultra−low ground
current consumption during light−load conditions.
Features
•Operating Input Voltage Range: 2.0 V to 5.5 V
•Available in Fixed Voltage Options: 0.8 to 3.5 V
Contact Factory for Other Voltage Options
•Output Voltage Trimming Step: 2.5 mV
•Ultra−Low Quiescent Current of Typ. 10 mA
•Ultra−Low Noise: 11 mVRMS from 100 Hz to 100 kHz
•Very Low Dropout: 140 mV Typical at 200 mA
•±2% Accuracy Over Full Load/Line/Temperature
•High PSRR: 68 dB at 1 kHz
•Thermal Shutdown and Current Limit Protections
•Internal Soft−Start to Limit the Turn−On Inrush Current
•Stable with a 1 mF Ceramic Output Capacitor
•Available in TSOP−5 and XDFN 1.5 x 1.5 mm Package
•Active Output Discharge for Fast Output Turn−Off
•These are Pb−Free Devices
Typical Applicaitons
•PDAs, Mobile Phones, GPS, Smartphones
•Wireless Handsets, Wireless LAN, Bluetooth, Zigbee
•Portable Medical Equipment
•Other Battery Powered Applications
Figure 1. Typical Application Schematic
IN
EN
OUT
GND
NCP702
1 mF
1 mFCOUT
VOUT
CIN
VIN
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See detailed ordering, marking and shipping information in the
package dimensions section on page 18 of this data sheet.
ORDERING INFORMATION
TSOP−5
SN SUFFIX
CASE 483
1
5
X, XXX = Specific Device Code
M = Date Code
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
1
5
XXXAYW
G
MARKING DIAGRAMS
XDFN−6
MX SUFFIX
CASE 711AE
X M
G
1
1
PIN CONNECTIONS
5−Pin TSOP−5
(Top View)
6−Pin XDFN 1.5 x 1.5 mm
(Top View)
OUT
N/C
N/C
IN
EN
GND
IN
EN
N/C
OUT
GND
1
1
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Figure 2. Simplified Schematic Block Diagram
IN
OUT
ACTIVE
DISCHARGE
THERMAL
SHUTDOWN
UVLO
ENABLE
LOGIC
GND
EN
EN
BANDGAP
REFERENCE
MOSFET
DRIVER WITH
CURRENT LIMIT
AUTO LOW
POWER MODE
INTEGRATED
SOFT−START
EEPROM
−
+
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
XDFN 6
Pin No.
TSOP−5
Pin
Name Description
1 5 OUT Regulated output voltage pin. A small 1 mF ceramic capacitor is needed from this pin to ground
to assure stability.
2 4 N/C Not connected. This pin can be tied to ground to improve thermal dissipation.
3 2 GND Power supply ground.
4 3 EN Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into
shutdown mode.
5 N/C Not connected. This pin can be tied to ground to improve thermal dissipation.
6 1 IN Input pin. It is recommended to connect a 1 mF ceramic capacitor close to the device pin.
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
Input Voltage (Note 1) VIN −0.3 V to 6 V V
Output Voltage VOUT −0.3 V to VIN + 0.3 V V
Enable Input VEN −0.3 V to VIN + 0.3 V V
Output Short Circuit Duration tSC Indefinite s
Maximum Junction Temperature TJ(MAX) 150 °C
Storage Temperature TSTG −55 to 150 °C
ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V
ESD Capability, Machine Model (Note 2) ESDMM 200 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
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Table 3. THERMAL CHARACTERISTICS (Note 3)
Rating Symbol Value Unit
Thermal Characteristics, TSOP−5,
Thermal Resistance, Junction−to−Air
Thermal Characterization Parameter, Junction−to−Lead (Pin 2)
qJA
yJA
224
115
°C/W
Thermal Characteristics, XDFN6 1.5 x 1.5 mm
Thermal Resistance, Junction−to−Air
Thermal Characterization Parameter, Junction−to−Board
qJA
yJB
149
81
°C/W
3. Single component mounted on 1 oz, FR4 PCB with 645 mm2 Cu area.
Table 4. ELECTRICAL CHARACTERISTICS
−40°C ≤ TJ ≤ 125°C; VIN = VOUT(NOM) + 0.3 V or 2.0 V, whichever is greater; VEN = 0.9 V, IOUT = 10 mA, CIN = COUT = 1 mF.
Typical values are at TJ = +25°C. Min/Max values are specified for TJ = −40°C and TJ = 125°C respectively. (Note 4)
Parameter Test Conditions Symbol Min Typ Max Unit
Operating Input Voltage VIN 2.0 5.5 V
Undervoltage lock−out VIN rising UVLO 1.2 1.6 1.9 V
Output Voltage Accuracy VOUT + 0.3 V ≤ VIN ≤ 5.5 V, IOUT = 0 − 200 mA VOUT −2 +2 %
Line Regulation VOUT + 0.3 V ≤ VIN ≤ 4.5 V, IOUT = 10 mA RegLINE 290 mV/V
VOUT + 0.3 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA RegLINE 440 mV/V
Load Regulation IOUT = 0 mA to 200 mA RegLOAD 13 mV/mA
Dropout voltage (Note 5) IOUT = 200 mA, VOUT(nom) = 2.5 V VDO 140 200 mV
Output Current Limit VOUT = 90% VOUT(nom) ICL 220 385 550 mA
Quiescent current IOUT = 0 mA IQ10 16 mA
Ground current IOUT = 2 mA IGND 60 mA
IOUT = 200 mA IGND 160 mA
Shutdown current (Note 6) VEN ≤ 0.4 V IDIS 0.005 mA
VEN ≤ 0.4 V, VIN = 4.5 V IDIS 0.01 1 mA
EN Pin Threshold Voltage
High Threshold
Low Threshold
VEN Voltage increasing
VEN Voltage decreasing
VEN_HI
VEN_LO
0.9
0.4
V
EN Pin Input Current VEN = VIN = 5.5 V IEN 110 500 nA
Turn−On Time (Note 7) COUT = 1.0 mF, IOUT = 1 mA tON 300 ms
Output Voltage Overshoot on
Start−up (Note 8)
VEN = 0 V to 0.9 V, 0 ≤ IOUT ≤ 200 mA DVOUT 2 %
Load Transient IOUT = 1 mA to 200 mA or
IOUT = 200 mA to 1 mA in 10 ms, COUT = 1 mF
DVOUT −30/+30 mV
Power Supply Rejection Ratio VIN = 3 V, VOUT = 2.5 V
IOUT = 150 mA
f = 100 Hz
f = 1 kHz
f = 10 kHz
PSRR 70
68
53
dB
Output Noise Voltage VOUT = 2.5 V, VIN = 3 V, IOUT = 200 mA
f = 100 Hz to 100 kHz
VN11 mVrms
Active Discharge Resistance VEN < 0.4 V RDIS 1kW
Thermal Shutdown Temperature Temperature increasing from TJ = +25°C TSD 160 °C
Thermal Shutdown Hysteresis Temperature falling from TSD TSDH −20 −°C
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TJ = TA
= 25_C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
5. Characterized when VOUT falls 100 mV below the regulated voltage at VIN = VOUT(NOM) + 0.3 V.
6. Shutdown Current is the current flowing into the IN pin when the device is in the disable state.
7. Turn−On time is measured from the assertion of EN pin to the point when the output voltage reaches 0.98 VOUT(NOM)
8. Guaranteed by design.
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TYPICAL CHARACTERISTICS
Figure 3. Output Voltage Noise Spectral Density for VOUT = 0.8 V, COUT = 1 mF
FREQUENCY (Hz)
10M1M100k10k1k10010
0.001
0.01
0.1
1
10
Figure 4. Output Voltage Noise Spectral Density for VOUT = 0.8 V, COUT = 4.7 mF
Figure 5. Output Voltage Noise Spectral Density for VOUT = 0.8 V, COUT = 10 mF
OUTPUT VOLTAGE NOISE (mV/rtHz)
VIN = 2.0 V
VOUT = 0.8 V
CIN = COUT = 1 mF
MLCC, X5R,
0402 size
IOUT = 1 mA
IOUT = 10 mA
IOUT = 200 mA
1 mA 21.74 21.17
10 mA 14.62 14.07
200 mA 10.74 10.02
10 Hz − 100 kHz 100 Hz − 100 kHz
RMS Output Noise
IOUT
FREQUENCY (Hz)
10M1M100k10k1k10010
0.001
0.01
0.1
1
10
OUTPUT VOLTAGE NOISE (mV/rtHz)
VIN = 2.0 V
VOUT = 0.8 V
CIN = COUT = 4.7 mF
MLCC, X7R,
1206 size
IOUT = 1 mA
IOUT = 10 mA
IOUT = 200 mA
1 mA 14.16 13.43
10 mA 14.20 13.70
200 mA 10.99 10.48
10 Hz − 100 kHz 100 Hz − 100 kHz
RMS Output Noise
IOUT
FREQUENCY (Hz)
0.001
0.01
0.1
1
10
OUTPUT VOLTAGE NOISE (mV/rtHz)
VIN = 2.0 V
VOUT = 0.8 V
CIN = COUT = 10 mF
MLCC, X7R,
1206 size
IOUT = 1 mA
IOUT = 10 mA
IOUT = 200 mA
1 mA 12.94 12.11
10 mA 12.78 12.25
200 mA 11.33 10.83
10 Hz − 100 kHz 100 Hz − 100 kHz
RMS Output Noise
IOUT
10M1M100k10k1k10010
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TYPICAL CHARACTERISTICS
Figure 6. Output Voltage Noise Spectral Density for VOUT = 3.3 V, COUT = 1 mF
FREQUENCY (Hz)
10M1M100k10k1k10010
0.001
0.01
0.1
1
10
Figure 7. Output Voltage Noise Spectral Density for VOUT = 3.3 V, COUT = 4.7 mF
Figure 8. Output Voltage Noise Spectral Density for VOUT = 3.3 V, COUT = 10 mF
OUTPUT VOLTAGE NOISE (mV/rtHz)
VIN = 3.8 V
VOUT = 3.3 V
CIN = COUT = 1 mF
MLCC, X5R,
0402 size
IOUT = 1 mA IOUT = 10 mA
IOUT = 200 mA
1 mA 20.28 17.87
10 mA 16.73 13.90
200 mA 13.70 10.21
10 Hz − 100 kHz 100 Hz − 100 kHz
RMS Output Noise
IOUT
FREQUENCY (Hz)
0.001
0.01
0.1
1
10
OUTPUT VOLTAGE NOISE (mV/rtHz)
VIN = 3.8 V
VOUT = 3.3 V
CIN = COUT = 4.7 mF
MLCC, X7R,
1202 size
IOUT = 1 mA IOUT = 10 mA
IOUT = 200 mA
1 mA 15.76 11.82
10 mA 17.09 13.88
200 mA 14.51 11.47
10 Hz − 100 kHz 100 Hz − 100 kHz
RMS Output Noise
IOUT
FREQUENCY (Hz)
0.001
0.01
0.1
1
10
OUTPUT VOLTAGE NOISE (mV/rtHz)
VIN = 3.8 V
VOUT = 3.3 V
CIN = COUT = 10 mF
MLCC, X7R,
1206 size
IOUT = 1 mA
IOUT = 10 mA
IOUT = 200 mA
1 mA 14.87 10.57
10 mA 16.00 12.65
200 mA 14.89 11.84
10 Hz − 100 kHz 100 Hz − 100 kHz
RMS Output Noise
IOUT
10M1M100k10k1k10010
10M1M100k10k1k10010
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TYPICAL CHARACTERISTICS
Figure 9. Power Supply Rejection Ratio,
VOUT = 0.8 V, COUT = 1 mF
Figure 10. Power Supply Rejection Ratio,
VOUT = 0.8 V, COUT = 4.7 mF
FREQUENCY (Hz) FREQUENCY (Hz)
0
10
20
40
60
70
90
100
Figure 11. Power Supply Rejection Ratio,
VOUT = 3.3 V, COUT = 1 mF
Figure 12. Power Supply Rejection Ratio,
VOUT = 3.3 V, COUT = 4.7 mF
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 13. Power Supply Rejection Ratio,
VOUT = 3.3 V, COUT = 10 mF
Figure 14. PSRR vs. Voltage Differential,
COUT = 4.7 mF, I OUT = 200 mA
FREQUENCY (Hz) VIN − VOUT VOLTAGE DIFFERENTIAL (V)
1.41.21.00.80.60.40.20
0
10
30
40
50
60
80
90
PSRR (dB)
PSRR (dB)
PSRR (dB)
PSRR (dB)
PSRR (dB)
PSRR (dB)
20
70
VOUT = 3.3 V
COUT = 4.7 mF
CIN = none
f = 100 Hz
f = 1 kHz
f = 100 kHz
f = 1 MHz
f = 10 kHz
IOUT = 200 mA
MLCC, X7R,
1206 size
30
50
80
VIN = 2.0 V
VOUT = 0.8 V
COUT = 1 mF
CIN = none
MLCC, X5R,
0402 size
0
10
20
40
60
70
90
100
30
50
80
0
10
20
40
60
70
90
100
30
50
80
VIN = 3.8 V
VOUT = 3.3 V
COUT = 10 mF
CIN = none
MLCC, X7R,
1206 size
0
10
20
40
60
70
90
30
50
80
VIN = 3.8 V
VOUT = 3.3 V
COUT = 4.7 mF
CIN = none
MLCC, X7R,
1206 size
0
10
20
40
60
70
90
110
30
50
80
100
IOUT = 1 mA
IOUT = 10 mA
IOUT = 50 mA
IOUT = 150 mA
IOUT = 200 mA
IOUT = 1 mA
IOUT = 10 mA
IOUT = 50 mA
IOUT = 150 mA
IOUT = 200 mA
IOUT = 1 mA
IOUT = 10 mA
IOUT = 50 mA
IOUT = 150 mA
IOUT = 200 mA
IOUT = 1 mA
IOUT = 10 mA
IOUT = 50 mA
IOUT = 150 mA
IOUT = 200 mA
IOUT = 1 mA
IOUT = 10 mA
IOUT = 50 mA
IOUT = 150 mA
IOUT = 200 mA
VIN = 3.8 V
VOUT = 3.3 V
COUT = 1 mF
CIN = none
MLCC, X5R,
0402 size
VIN = 2.0 V
VOUT = 0.8 V
COUT = 4.7 mF
CIN = none
MLCC, X7R,
1206 size
10M1M100k10k1k10010 10M1M100k10k1k10010
10M1M100k10k1k10010 10M1M100k10k1k10010
10M1M100k10k1k10010
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TYPICAL CHARACTERISTICS
Figure 15. PSRR vs. Voltage Differential,
COUT = 4.7 mF, I OUT = 10 mA
Figure 16. Quiescent Current vs. Input Voltage,
VOUT = 3.3 V
VIN − VOUT VOLTAGE DIFFERENTIAL (V) VIN, INPUT VOLTAGE (V)
1.41.21.00.80.60.2 0.40
0
10
20
30
50
60
70
80
5.54.03.53.02.01.00.50
0
2
4
6
8
10
12
Figure 17. Quiescent Current vs. Input Voltage,
VOUT = 0.8 V
Figure 18. Dropout Voltage vs. Output Current,
VOUT = 3.3 V
VIN, INPUT VOLTAGE (V) IOUT
, OUTPUT CURRENT (mA)
180140100806040200
0
20
40
60
80
100
120
140
Figure 19. Dropout Voltage vs. Output Current,
VOUT = 2.5 V
Figure 20. Output Voltage vs. Temperature,
VOUT = 0.8 V
IOUT
, OUTPUT CURRENT (mA) TJ, JUNCTION TEMPERATURE (°C)
1801401201006040200
0
20
60
80
100
140
180
200
1201008040200−20−40
0.781
0.785
0.789
0.797
0.801
0.805
0.813
0.817
PSRR (dB)
IQ, QUIESCENT CURRENT (mA)
IQ, QUIESCENT CURRENT (mA)
VDROP
, DROPOUT VOLTAGE (mV)
VDROP
, DROPOUT VOLTAGE (mV)
VOUT
, OUTPUT VOLTAGE (V)
40
f = 1 kHz
f = 100 kHz
f = 1 MHz
f = 10 kHz
VOUT = 3.3 V
COUT = 4.7 mF
CIN = none
IOUT = 10 mA
MLCC, X7R,
1206 size
1.5 2.5 4.5 5.0
TJ = 25°C
TJ = −40°C
TJ = 125°C
VOUT = 3.3 V
IOUT = 0 mA
COUT = 1 mF
TJ = 25°C
TJ = −40°C
TJ = 125°C
VOUT = 0.8 V
IOUT = 0 mA
COUT = 1 mF
120 160 200
TJ = 25°C
TJ = −40°C
TJ = 125°C
VOUT(nom) = 3.3 V
CIN = COUT = 1 mF
80 160 200
40
120
160
TJ = 25°C
TJ = −40°C
TJ = 125°C
VOUT(nom) = 2.5 V
CIN = COUT = 1 mF
60 140
0.793
0.809
VIN = 2.0 V
VOUT(nom) = 0.8 V
IOUT = 10 mA
COUT = COUT = 1 mF
0
2
4
6
8
10
12
0123456
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TYPICAL CHARACTERISTICS
Figure 21. Output Voltage vs. Temperature,
VOUT = 1.8 V
Figure 22. Output Voltage vs. Temperature,
VOUT = 3.3 V
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
1201008040200−20−40
1.780
1.784
1.788
1.796
1.800
1.808
1.812
1.816
Figure 23. Load Regulation vs. Temperature,
VOUT = 0.8 V
Figure 24. Load Regulation vs. Temperature,
VOUT = 1.8 V
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
1201008040200−20−40
0
1
2
4
6
7
9
10
Figure 25. Load Regulation vs. Temperature,
VOUT = 3.3 V
Figure 26. Line Regulation vs. Temperature,
VOUT = 0.8 V
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
VOUT
, OUTPUT VOLTAGE (V)
VOUT
, OUTPUT VOLTAGE (V)
REGLOAD, LOAD REGULATION (mV)
REGLINE, LINE REGULATION (mV/V)
60 140
1.792
1.804
VIN = 2.1 V
VOUT = 1.8 V
IOUT = 10 mA
COUT = COUT = 1 mF
1201008040200−20−40
3.285
3.289
3.293
3.301
3.309
3.313
60 140
3.297
3.305
VIN = 3.8 V
VOUT = 3.3 V
IOUT = 10 mA
COUT = COUT = 1 mF
3.317
60 140
3
5
8
VIN = 2.0 V
VOUT = 0.8 V
IOUT = 0 mA … 200 mA
COUT = COUT = 1 mF
1201008040200−20−40
0
1
2
4
6
7
9
10
REGLOAD, LOAD REGULATION (mV)
60 140
3
5
8
VIN = 2.1 V
VOUT = 1.8 V
IOUT = 0 mA … 200 mA
COUT = COUT = 1 mF
1201008040200−20−40
0
1
2
4
6
7
9
10
REGLOAD, LOAD REGULATION (mV)
60 140
3
5
8
VIN = 3.6 V
VOUT = 3.3 V
IOUT = 0 mA … 200 mA
COUT = COUT = 1 mF
1201008040200−20−40
0
100
200
400
600
700
900
1000
60 140
300
500
800
VOUT = 0.8 V
IOUT = 10 mA
COUT = COUT = 1 mF
VIN = 2.0 V … 5.5 V
VIN = 2.0 V … 4.5 V
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TYPICAL CHARACTERISTICS
Figure 27. Line Regulation vs. Temperature,
VOUT = 1.8 V
Figure 28. Line Regulation vs. Temperature,
VOUT = 3.3 V
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
1201006040200−20−40
0
100
300
400
600
700
900
1000
Figure 29. Disable Current vs. Temperature,
VOUT = 1.8 V
Figure 30. Disable Current vs. Temperature,
VOUT = 3.3 V
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
1201008040200−20−40
−0.05
0
0.10
0.15
0.25
0.35
0.45
0.50
Figure 31. Disable Current vs. Temperature,
VOUT = 0.8 V
Figure 32. Output Current Limit vs.
Temperature, VOUT = 0.8 V
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
REGLINE, LINE REGULATION (mV/V)IDIS, DISABLE CURRENT (mA)IDIS, DISABLE CURRENT (mA)
IOUT
, OUTPUT CURRENT (mA)
80 140
200
500
800
VIN = VEN = 2 V
VOUT(nom) = 0.8 V
CIN = COUT = 1 mF
Output Short Circuit
VOUT = 0 V
Output Current Limit
VOUT = VOUT(nom) − 0.1 V
VOUT = 1.8 V
IOUT = 10 mA
COUT = COUT = 1 mF
VIN = 2.1 V … 5.5 V
VIN = 2.1 V … 4.5 V
1201006040200−20−40
0
100
300
400
600
700
900
1000
REGLINE, LINE REGULATION (mV/V)
80 140
200
500
800
VOUT = 3.3 V
IOUT = 10 mA
COUT = COUT = 1 mF
VIN = 3.6 V … 5.5 V
VIN = 3.6 V … 4.5 V
60 140
0.05
0.20
0.30
0.40
VIN = 5.5 V
VOUT = 1.8 V
VEN = 0 V
COUT = COUT = 1 mF
1201008040200−20−40
−0.05
0
0.10
0.15
0.25
0.35
0.45
0.50
IDIS, DISABLE CURRENT (mA)
60 140
0.05
0.20
0.30
0.40
VIN = 5.5 V
VOUT = 3.3 V
VEN = 0 V
COUT = COUT = 1 mF
1201008040200−20−40
−0.05
0
0.10
0.15
0.25
0.35
0.45
0.50
60 140
0.05
0.20
0.30
0.40
VIN = 5.5 V
VOUT = 0.8 V
VEN = 0 V
COUT = COUT = 1 mF
250
270
290
310
330
350
370
390
410
430
450
−40 −20 0 20 40 60 80 100 120 140
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TYPICAL CHARACTERISTICS
Figure 33. Output Current Limit vs.
Temperature, VOUT = 3.3 V
Figure 34. Enable Low Threshold Voltage
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 35. Enable High Threshold Voltage Figure 36. Enable Turn−On Response,
VOUT = 3.3 V, COUT = 1 mF
TJ, JUNCTION TEMPERATURE (°C)
1201006040200−20−40
0.2
0.3
0.4
0.5
0.7
0.8
0.9
1.0
Figure 37. Enable Turn−On Response,
VOUT = 3.3 V, COUT = 3 mF
Figure 38. Enable Turn−On Response,
VOUT = 0.8 V, COUT = 1 mF
IOUT
, OUTPUT CURRENT (mA)VEN_HI, EN HIGH THRESHOLD (V)
80 140
0.6
1201006040200−20−40
0.2
0.3
0.4
0.5
0.7
0.8
0.9
1.0
VEN_LOW, EN LOW THRESHOLD (V)
80 140
0.6
VOUT(nom) = 3.3 V
VIN = 3.6 V
IOUT = 10 mA
COUT = COUT = 1 mF
VOUT(nom) = 3.3 V
VIN = 3.6 V
IOUT = 10 mA
COUT = COUT = 1 mF
VIN = VEN = 3.6 V
VOUT(nom) = 3.3 V
CIN = COUT = 1 mFOutput Short Circuit
VOUT = 0 V
Output Current Limit
VOUT = VOUT(nom) − 0.1 V
290
310
330
350
370
390
410
430
450
470
490
−40 −20 0 20 40 60 80 100 120 140
VIN = 3.6 V
VOUT(nom) = 3.3 V
COUT = 1 mF
CIN = none
IOUT = 1 mA
TA = 25°C
OUT
EN
IINRUSH IINRUSH = 60 mA
100 ms/div
1 V/div1 V/div
50 mA/div
IINRUSH = 115 mA
VIN = 3.6 V
VOUT(nom) = 3.3 V
COUT = 3 mF
CIN = none
IOUT = 1 mA
TA = 25°C
OUT
EN
IINRUSH
1 V/div1 V/div
50 mA/div
0.5 V/div1 V/div
VIN = 2.0 V
VOUT(nom) = 0.8 V
COUT = 1 mF
CIN = none
IOUT = 1 mA
TA = 25°C
50 mA/div
100 ms/div
IINRUSH = 20 mA
100 ms/div
NCP702
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11
TYPICAL CHARACTERISTICS
Figure 39. Enable Turn−On Response,
VOUT = 0.8 V, COUT = 3 mF
0.5 V/div1 V/div
VIN = 2.0 V
VOUT(nom) = 0.8 V
COUT = 3 mF
CIN = none
IOUT = 1 mA
TA = 25°C
50 mA/div
IINRUSH = 45 mA
100 ms/div
0
40
80
120
160
200
1 1.5 2 2.5 3 3.5 4 4.5 5
COUT
, OUTPUT CAPACITANCE (mF)
IINRUSH, INRUSH CURRENT (mA)
Figure 40. Turn−On Inrush Current vs. Output
Capacitance
VIN = VOUT + 0.3 V or 2 V
whichever is greater
VEN = 0 V to 1 V
CIN = none, TJ = 25°C
IOUT = 1 mA
VOUT = 3.3 V
VOUT = 0.8 V
Figure 41. Enable Turn−Off Response,
VOUT = 3.3 V, COUT = 1 mF
Figure 42. Enable Turn−Off Response,
VOUT = 3.3 V, COUT = 4.7 mF
Figure 43. Enable Turn−Off Response,
VOUT = 3.3 V, COUT = 10 mF
Figure 44. Slow Input Voltage
Turn−On/Turn−Off, VOUT = 3.3 V
NCP702
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12
TYPICAL CHARACTERISTICS
Figure 45. Line Transient Response −
Rising Edge, VOUT = 3.3 V
Figure 46. Line Transient Response −
Falling Edge, VOUT = 3.3 V
Figure 47. Load Transient Response − Rising
Edge, IOUT = 1 mA − 200 mA, VOUT = 0.8 V
Figure 48. Load Transient Response − Falling
Edge, IOUT = 1 mA − 200 mA, VOUT = 0.8 V
Figure 49. Load Transient Response − Rising
Edge, IOUT = 1 mA − 200 mA, COUT = 1.0 mF
Figure 50. Load Transient Response − Falling
Edge, IOUT = 1 mA − 200 mA, COUT = 1.0 mF
NCP702
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13
TYPICAL CHARACTERISTICS
Figure 51. Load Transient Response − Rising
Edge, IOUT = 1 mA − 200 mA, COUT = 4.7 mF
Figure 52. Load Transient Response − Falling
Edge, IOUT = 1 mA − 200 mA, COUT = 4.7 mF
Figure 53. Load Transient Response − Rising
Edge, IOUT = 1 mA − 200 mA, COUT = 10 mF
Figure 54. Load Transient Response − Falling
Edge, IOUT = 1 mA − 200 mA, COUT = 10 mF
Figure 55. Output Short Circuit Response Figure 56. Cycling between Output Short
Circuit and Thermal Shutdown
NCP702
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TYPICAL CHARACTERISTICS
Figure 57. Ground Current vs. Output Current,
IOUT = 0 mA to 5 mA
Figure 58. Ground Current vs. Output Current,
IOUT = 0 mA to 200 mA
IOUT
, OUTPUT CURRENT (mA) IOUT
, OUTPUT CURRENT (mA)
1601401201006040200
0
20
40
60
100
120
160
180
IGND, GROUND CURRENT (mA)
IGND, GROUND CURRENT (mA)
VIN = 3.6 V
VOUT = 3.3 V
CIN = COUT = 1 mF
MLCC, X7R,
1206 size
TJ = 25°C
TJ = −40°C
TJ = 125°C
80 180 200
80
140
VIN = 3.6 V
VOUT = 3.3 V
CIN = COUT = 1 mF
MLCC, X7R,
1206 size
TJ = 25°C
TJ = −40°C
TJ = 125°C
0
10
20
30
40
50
60
70
80
00.511.522.533.544.5
Figure 59. EN Pin Input Current vs. Enable Pin
Voltage
Figure 60. Output Capacitor ESR vs. Output
Current
VEN, ENABLE VOLTAGE (V) IOUT
, OUTPUT CURRENT (mA)
4.54.03.52.52.01.00.50
0
0.02
0.04
0.06
0.08
0.10
0.12
180140100806040200
0.001
0.01
0.1
1
10
IEN, EN PIN INPUT CURRENT (mA)
ESR (W)
120 160 2001.5 3.0 5.0 5.5
VIN = 5.5 V
VOUT = 1.8 V
IOUT = 10 mA
TJ = 25°C
CIN = COUT = 1 mF
VIN = VOUT(nom) + 0.3 V or 2 V
COUT = CIN = 1 mF
TA = 25°C
Unstable Operation
Stable Operation
VOUT = 0.8 V
VOUT = 3.3 V
NCP702
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APPLICATIONS INFORMATION
General
The NCP702 is a high performance 200 mA Low Dropout
Linear Regulator. This device delivers excellent noise and
dynamic performance.
Thanks to its adaptive ground current feature the device
consumes only 10 mA of quiescent current at no−load
condition.
The regulator features ultra−low noise of 11 mVRMS,
PSRR of 68 dB at 1 kHz and very good load/line transient
performance. Such excellent dynamic parameters and small
package size make the device an ideal choice for powering
the precision analog and noise sensitive circuitry in portable
applications. The LDO achieves this ultra low noise level
output without the need for a noise bypass capacitor.
A logic EN input provides ON/OFF control of the output
voltage. When the EN is low the device consumes as low as
typ. 10 nA from the IN pin.
The LDO achieves ultra−low output voltage noise without
the need for additional noise bypass capacitor.
The device is fully protected in case of output overload,
output short circuit condition and overheating, assuring a
very robust design.
Input Capacitor Selection (CIN)
It is recommended to connect a minimum of 1 mF Ceramic
X5R or X7R capacitor close to the IN pin of the device. This
capacitor will provide a low impedance path for unwanted
AC signals or noise modulated onto constant input voltage.
There is no requirement for the min./max. ESR of the
input capacitor but it is recommended to use ceramic
capacitors for their low ESR and ESL. A good input
capacitor will limit the influence of input trace inductance
and source resistance during sudden load current changes.
Larger input capacitor may be necessary if fast and large
load transients are encountered in the application.
Output Decoupling (COUT)
The NCP702 is designed to be stable with a small 1.0 mF
ceramic capacitor on the output. To assure proper operation
it is strongly recommended to use min. 1.0 mF capacitor with
the initial tolerance of ±10%, made of X7R or X5R dielectric
material types.
There is no requirement for the minimum value of
Equivalent Series Resistance (ESR) for the COUT but the
maximum value of ESR should be less than 700 mW.
Larger output capacitors could be used to improve the load
transient response or high frequency PSRR as shown in
typical characteristics. The initial tolerance requirements
can be wider than ±10% when using capacitors larger than
1mF.
It is not recommended to use tantalum capacitors on the
output due to their large ESR. The equivalent series
resistance of tantalum capacitors is also strongly dependent
on the temperature, increasing at low temperature. The
tantalum capacitors are generally more costly than ceramic
capacitors.
The table on this page lists the capacitors which were used
during the IC evaluation.
No−load Operation
The regulator remains stable and regulates the output
voltage properly within the ±2% tolerance limits even with
no external load applied to the output.
IN
EN
OUT
GND
C2
C1 NCP702
2 V ... 5.5 V 0 mA ... 200 mA
U1
Figure 61. Typical Applications Schematics
VOUT
VIN
LIST OF CAPACITORS USED DURING THE NCP702 EVALUATION:
Symbol Manufacturer Part Number Description
C1, C2
Kemet C0402C105K8PACTU 1 mF Ceramic ±10%, 10 V, 0402, X5R
TDK C1005X5R1A105K −||−
Murata GRM155R61A105KE15D −||−
AVX 0402ZD105KAT2A −||−
Multicomp MCCA000571 1 mF Ceramic ±10%, 50 V, 1206, X7R
Panason − ECG ECJ−0EB0J475M 4.7 mF Ceramic ±20%, 6.3 V, 0402, X5R
NCP702
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APPLICATIONS INFORMATION
Enable Operation
The NCP702 uses the EN pin to enable/disable its output
and to deactivate/activate the active discharge function.
If the EN pin voltage is <0.4 V the device is guaranteed to
be disabled. The pass transistor is turned−off so that there is
virtually no current flow between the IN and OUT. The
active discharge transistor is active so that the output voltage
VOUT is pulled to GND through a 1 kW resistor. In the
disable state the device consumes as low as typ. 10 nA from
the VIN.
If the EN pin voltage >0.9 V the device is guaranteed to
be enabled. The NCP702 regulates the output voltage and
the active discharge transistor is turned−off.
The EN pin has internal pull−down current source with
typ. value of 110 nA which assures that the device is
turned−off when the EN pin is not connected. A build in
2 mV of hysteresis in the EN prevents from periodic on/off
oscillations that can occur due to noise.
In the case where the EN function isn’t required the EN
pin should be tied directly to IN.
Undervoltage Lockout
The internal UVLO circuitry assures that the device
becomes disabled when the VIN falls below typ. 1.5 V. When
the VIN voltage ramps−up the NCP702 becomes enabled, if
VIN rises above typ. 1.6 V. The 100 mV hysteresis prevents
on/off oscillations that can occur due to noise on VIN line.
Reverse Current
The PMOS pass transistor has an inherent body diode
which will be forward biased in the case that VOUT > VIN.
Due to this fact in cases where the extended reverse current
condition is anticipated the device may require additional
external protection.
Output Current Limit
Output Current is internally limited within the IC to a
typical 380 mA. The NCP702 will source this amount of
current measured with the output voltage 100 mV lower than
the nominal VOUT. If the Output Voltage is directly shorted
to ground (VOUT = 0 V), the short circuit protection will
limit the output current to 390 mA (typ). The current limit
and short circuit protection will work properly up to VIN =
5.5 V at TA = 25°C. There is no limitation for the short circuit
duration.
Thermal Shutdown
When the die temperature exceeds the Thermal Shutdown
threshold (TSD − 160°C typical), Thermal Shutdown event
is detected and the device is disabled. The IC will remain in
this state until the die temperature decreases below the
Thermal Shutdown Reset threshold (TSDU − 140°C typical).
Once the IC temperature falls below the 140°C the LDO is
enabled again. The thermal shutdown feature provides
protection from a catastrophic device failure due to
accidental overheating. This protection is not intended to be
used as a substitute for proper heat sinking.
Power Dissipation
As power dissipated in the NCP702 increases, it might
become necessary to provide some thermal relief. The
maximum power dissipation supported by the device is
dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part. For reliable operation junction temperature
should be limited to +125°C.
The maximum power dissipation the NCP702 can handle
is given by:
PD(MAX) +ƪ125 *TAƫ
qJA
(eq. 1)
The power dissipated by the NCP702 for given
application conditions can be calculated from the following
equations:
PD[VINǒIGND@IOUTǓ)IOUTǒVIN *VOUTǓ(eq. 2)
Figure 62. qJA and PD(MAX) vs. Copper Area (TSOP5)
PCB COPPER AREA (mm2)
600500400 7003002001000
150
170
190
230
250
270
310
330
qJA, JUNCTION TO AMBIENT
THERMAL RESISTANCE (°C/W)
210
290
0.20
0.25
0.30
0.40
0.45
0.50
0.60
0.65
0.35
0.55
PD(MAX), MAXIMUM POWER
DISSIPATION (W)
qJA, 2 OZ CU
qJA, 1 OZ CU
PD(MAX), TA = 25°C, 1 OZ CU
PD(MAX), TA = 25°C, 2 OZ CU
NCP702
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Figure 63. qJA and PD(MAX) vs. Copper Area (XDFN6)
PCB COPPER AREA (mm2)
600500400 8003002001000
50
100
200
250
350
400
qJA, JUNCTION TO AMBIENT
THERMAL RESISTANCE (°C/W)
150
300
0.1
0.2
0.3
0.5
0.7
0.8
0.4
0.6
PD(MAX), MAXIMUM POWER
DISSIPATION (W)
qJA, 2 OZ CU
qJA, 1 OZ CU
PD(MAX), TA = 25°C, 1 OZ CU
PD(MAX), TA = 25°C, 2 OZ CU
700
Load Regulation
The NCP702 features very good load regulation of
maximum 2.6 mV in the 0 mA to 200 mA range. In order to
achieve this very good load regulation a special attention to
PCB design is necessary. The trace resistance from the OUT
pin to the point of load can easily approach 100 mΩ which
will cause a 20 mV voltage drop at full load current,
deteriorating the excellent load regulation.
Line Regulation
The IC features very good line regulation of 0.44 mV/V
measured from VIN = VOUT + 0.3 V to 5.5 V. For battery
operated applications it may be important that the line
regulation from VIN = VOUT + 0.3 V up to 4.5 V is only
0.29 mV/V.
Power Supply Rejection Ratio
The NCP702 features very good Power Supply Rejection
ratio. If desired the PSRR at higher frequencies in the range
100 kHz – 10 MHz can be tuned by the selection of COUT
capacitor and proper PCB layout.
Output Noise
The IC is designed for ultra−low noise output voltage.
Figures 3 – 8 illustrate the noise performance for different
VOUT, IOUT, COUT. Generally the noise performance in the
indicated frequency range improves with increasing output
current, although even at IOUT = 1 mA the noise levels are
below 22 mVRMS.
Turn−On Time
The turn−on time is defined as the time period from EN
assertion to the point in which VOUT will reach 98% of its
nominal value. This time is dependent on VOUT(NOM),
COUT, TA. The turn−on time temperature dependence is
shown below:
Figure 64. Turn−On Time vs. Temperature
TJ, JUNCTION TEMPERATURE (°C)
EN, TURN−ON TIME (ms)
VOUT = 0.8 V
VOUT = 3.3 V
VOUT = 1.8 V
VIN = VOUT + 0.3 V or 2 V
IOUT = 10 mA
CIN = COUT = 1 mF
VEN = 0 V −> 0.9 V
0
40
80
120
160
200
240
280
320
360
400
−40 −20 0 20 40 60 80 100 120 140
Internal SoftStart
The Internal Soft−Start circuitry will limit the inrush
current during the LDO turn-on phase. Please refer to
Figure 43 for typical inrush current values for given output
capacitance.
The soft−start function prevents from any output voltage
overshoots and assures monotonic ramp-up of the output
voltage.
PCB Layout Recommendations
To obtain good transient performance and good regulation
characteristics place CIN and COUT capacitors close to the
device pins and make the PCB traces wide. In order to
minimize the solution size use 0402 capacitors. Larger
copper area connected to the pins will also improve the
device thermal resistance. The actual power dissipation can
be calculated by the formula given in Equation 2.
NCP702
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18
ORDERING INFORMATION
Device Voltage Option Marking Package Shipping †
NCP702MX18TCG 1.8 V P
XDFN6
(Pb−Free) 3000 / Tape & Reel
NCP702MX28TCG 2.8 V 2
NCP702MX30TCG 3.0 V 3
NCP702MX33TCG 3.3 V 4
NCP702SN18T1G 1.8 V A7J
TSOP5
(Pb−Free) 3000 / Tape & Reel
NCP702SN28T1G 2.8 V AD2
NCP702SN30T1G 3.0 V A7R
NCP702SN31T1G 3.1 V A7P
NCP702SN33T1G 3.3 V A7T
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP702
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19
PACKAGE DIMENSIONS
ÍÍÍ
ÍÍÍ
ÍÍÍ
ÍÍÍ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20mm FROM TERMINAL TIP.
C
A
SEATING
PLANE
D
E
0.10 C
A3
A1
2X
2X 0.10 C
XDFN6 1.5x1.5, 0.5P
CASE 711AE
ISSUE A
DIM
A
MIN MAX
MILLIMETERS
0.35 0.45
A1 0.00 0.05
A3 0.13 REF
b0.20 0.30
D
E
e
L
PIN ONE
REFERENCE
0.05 C
0.05 C
A0.10 C
NOTE 3
L2
e
b
B
3
6
6X
1
4
0.05 C
MOUNTING FOOTPRINT*
L1
1.50 BSC
1.50 BSC
0.50 BSC
0.40 0.60
--- 0.15
BOTTOM VIEW
L
5X
DIMENSIONS: MILLIMETERS
0.73
6X 0.35
5X
1.80
0.50
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
ÉÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
DETAIL B
DETAIL A
L2 0.50 0.70
TOP VIEW
B
SIDE VIEW
RECOMMENDED
0.83
A
NCP702
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20
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE K NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
DIM MIN MAX
MILLIMETERS
A3.00 BSC
B1.50 BSC
C0.90 1.10
D0.25 0.50
G0.95 BSC
H0.01 0.10
J0.10 0.26
K0.20 0.60
M0 10
S2.50 3.00
123
54 S
A
G
B
D
H
C
J
__
0.7
0.028
1.0
0.039
ǒmm
inchesǓ
SCALE 10:1
0.95
0.037
2.4
0.094
1.9
0.074
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.20
5X
CAB
T0.10
2X
2X T0.20
NOTE 5
CSEATING
PLANE
0.05
K
M
DETAIL Z
DETAIL Z
TOP VIEW
SIDE VIEW
A
B
END VIEW
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copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NCP702/D
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