NCP702 200 mA, Ultra-Low Quiescent Current, Ultra-Low Noise, LDO Linear Voltage Regulator Noise sensitive applications such as Phase Locked Loops, Oscillators, Frequency Synthesizers, Low Noise Amplifiers and other Precision Instrumentation require very clean power supplies. The NCP702 is a 200 mA LDO that provides the engineer with a very stable, accurate voltage with ultra-low noise and very high Power Supply Rejection Ratio (PSRR), making it suitable for RF applications. The device doesn't require an additional noise bypass capacitor to achieve ultra-low noise performance. In order to optimize performance for battery operated portable applications, the NCP702 employs an Adaptive Ground Current feature for ultra-low ground current consumption during light-load conditions. http://onsemi.com 5 1 MARKING DIAGRAMS Features * Operating Input Voltage Range: 2.0 V to 5.5 V * Available in Fixed Voltage Options: 0.8 to 3.5 V * * * * * * * * * * * * 5 Contact Factory for Other Voltage Options Output Voltage Trimming Step: 2.5 mV Ultra-Low Quiescent Current of Typ. 10 mA Ultra-Low Noise: 11 mVRMS from 100 Hz to 100 kHz Very Low Dropout: 140 mV Typical at 200 mA 2% Accuracy Over Full Load/Line/Temperature High PSRR: 68 dB at 1 kHz Thermal Shutdown and Current Limit Protections Internal Soft-Start to Limit the Turn-On Inrush Current Stable with a 1 mF Ceramic Output Capacitor Available in TSOP-5 and XDFN 1.5 x 1.5 mm Package Active Output Discharge for Fast Output Turn-Off These are Pb-Free Devices X, XXX = Specific Device Code M = Date Code A = Assembly Location Y = Year W = Work Week G = Pb-Free Package PIN CONNECTIONS CIN 1 mF EN GND COUT OUT GND EN N/C 5-Pin TSOP-5 (Top View) 1 OUT N/C GND VOUT OUT 1 IN NCP702 IN XM G 1 PDAs, Mobile Phones, GPS, Smartphones Wireless Handsets, Wireless LAN, Bluetooth, Zigbee Portable Medical Equipment Other Battery Powered Applications VIN 1 XXXAYW G Typical Applicaitons * * * * 1 XDFN-6 MX SUFFIX CASE 711AE TSOP-5 SN SUFFIX CASE 483 1 mF IN N/C EN 6-Pin XDFN 1.5 x 1.5 mm (Top View) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 18 of this data sheet. Figure 1. Typical Application Schematic (c) Semiconductor Components Industries, LLC, 2013 July, 2013 - Rev. 3 1 Publication Order Number: NCP702/D NCP702 IN ENABLE LOGIC EN - BANDGAP REFERENCE THERMAL SHUTDOWN UVLO INTEGRATED SOFT-START + MOSFET DRIVER WITH CURRENT LIMIT OUT AUTO LOW POWER MODE ACTIVE DISCHARGE EEPROM EN GND Figure 2. Simplified Schematic Block Diagram Table 1. PIN FUNCTION DESCRIPTION Pin No. XDFN 6 Pin No. TSOP-5 Pin Name 1 5 OUT Regulated output voltage pin. A small 1 mF ceramic capacitor is needed from this pin to ground to assure stability. 2 4 N/C Not connected. This pin can be tied to ground to improve thermal dissipation. 3 2 GND Power supply ground. 4 3 EN Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode. N/C Not connected. This pin can be tied to ground to improve thermal dissipation. 5 6 1 IN Description Input pin. It is recommended to connect a 1 mF ceramic capacitor close to the device pin. Table 2. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit VIN -0.3 V to 6 V V Output Voltage VOUT -0.3 V to VIN + 0.3 V V Enable Input VEN -0.3 V to VIN + 0.3 V V Output Short Circuit Duration tSC Indefinite s TJ(MAX) 150 C TSTG -55 to 150 C ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V ESD Capability, Machine Model (Note 2) ESDMM 200 V Input Voltage (Note 1) Maximum Junction Temperature Storage Temperature Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC-Q100-002 (EIA/JESD22-A114) ESD Machine Model tested per AEC-Q100-003 (EIA/JESD22-A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78. http://onsemi.com 2 NCP702 Table 3. THERMAL CHARACTERISTICS (Note 3) Symbol Value Thermal Characteristics, TSOP-5, Thermal Resistance, Junction-to-Air Thermal Characterization Parameter, Junction-to-Lead (Pin 2) qJA yJA 224 115 Thermal Characteristics, XDFN6 1.5 x 1.5 mm Thermal Resistance, Junction-to-Air Thermal Characterization Parameter, Junction-to-Board qJA yJB 149 81 Rating Unit C/W C/W 3. Single component mounted on 1 oz, FR4 PCB with 645 mm2 Cu area. Table 4. ELECTRICAL CHARACTERISTICS -40C TJ 125C; VIN = VOUT(NOM) + 0.3 V or 2.0 V, whichever is greater; VEN = 0.9 V, IOUT = 10 mA, CIN = COUT = 1 mF. Typical values are at TJ = +25C. Min/Max values are specified for TJ = -40C and TJ = 125C respectively. (Note 4) Parameter Test Conditions Operating Input Voltage Symbol Min Typ Max Unit 5.5 V 1.9 V +2 % VIN 2.0 Undervoltage lock-out VIN rising UVLO 1.2 Output Voltage Accuracy VOUT + 0.3 V VIN 5.5 V, IOUT = 0 - 200 mA VOUT -2 Line Regulation VOUT + 0.3 V VIN 4.5 V, IOUT = 10 mA RegLINE 290 mV/V VOUT + 0.3 V VIN 5.5 V, IOUT = 10 mA RegLINE 440 mV/V Load Regulation IOUT = 0 mA to 200 mA RegLOAD 13 mV/mA Dropout voltage (Note 5) IOUT = 200 mA, VOUT(nom) = 2.5 V VDO Output Current Limit VOUT = 90% VOUT(nom) ICL Quiescent current IOUT = 0 mA Ground current Shutdown current (Note 6) 1.6 140 200 mV 385 550 mA IQ 10 16 mA IOUT = 2 mA IGND 60 mA IOUT = 200 mA IGND 160 mA VEN 0.4 V IDIS 0.005 mA 0.01 220 VEN 0.4 V, VIN = 4.5 V IDIS EN Pin Threshold Voltage High Threshold Low Threshold 1 VEN Voltage increasing VEN Voltage decreasing VEN_HI VEN_LO EN Pin Input Current VEN = VIN = 5.5 V IEN 110 Turn-On Time (Note 7) COUT = 1.0 mF, IOUT = 1 mA tON 300 Output Voltage Overshoot on Start-up (Note 8) VEN = 0 V to 0.9 V, 0 IOUT 200 mA DVOUT Load Transient IOUT = 1 mA to 200 mA or IOUT = 200 mA to 1 mA in 10 ms, COUT = 1 mF DVOUT -30/+30 mV Power Supply Rejection Ratio VIN = 3 V, VOUT = 2.5 V IOUT = 150 mA PSRR 70 68 53 dB Output Noise Voltage VOUT = 2.5 V, VIN = 3 V, IOUT = 200 mA f = 100 Hz to 100 kHz VN 11 mVrms Active Discharge Resistance VEN < 0.4 V RDIS 1 kW Thermal Shutdown Temperature Temperature increasing from TJ = +25C TSD 160 C Thermal Shutdown Hysteresis Temperature falling from TSD TSDH mA V f = 100 Hz f = 1 kHz f = 10 kHz 0.9 0.4 500 ms 2 - 20 nA - % C 4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TJ = TA = 25_C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 5. Characterized when VOUT falls 100 mV below the regulated voltage at VIN = VOUT(NOM) + 0.3 V. 6. Shutdown Current is the current flowing into the IN pin when the device is in the disable state. 7. Turn-On time is measured from the assertion of EN pin to the point when the output voltage reaches 0.98 VOUT(NOM) 8. Guaranteed by design. http://onsemi.com 3 NCP702 OUTPUT VOLTAGE NOISE (mV/rtHz) TYPICAL CHARACTERISTICS 10 VIN = 2.0 V VOUT = 0.8 V CIN = COUT = 1 mF MLCC, X5R, 0402 size 1 IOUT IOUT = 1 mA 0.1 IOUT = 200 mA 0.01 RMS Output Noise 10 Hz - 100 kHz 100 Hz - 100 kHz 21.17 1 mA 21.74 10 mA 14.62 14.07 200 mA 10.74 10.02 IOUT = 10 mA 0.001 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) OUTPUT VOLTAGE NOISE (mV/rtHz) Figure 3. Output Voltage Noise Spectral Density for VOUT = 0.8 V, COUT = 1 mF 10 VIN = 2.0 V VOUT = 0.8 V CIN = COUT = 4.7 mF MLCC, X7R, 1206 size 1 IOUT = 1 mA IOUT IOUT = 10 mA 0.1 IOUT = 200 mA RMS Output Noise 10 Hz - 100 kHz 100 Hz - 100 kHz 1 mA 14.16 13.43 10 mA 14.20 13.70 200 mA 10.99 10.48 0.01 0.001 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) OUTPUT VOLTAGE NOISE (mV/rtHz) Figure 4. Output Voltage Noise Spectral Density for VOUT = 0.8 V, COUT = 4.7 mF 10 1 IOUT = 1 mA VIN = 2.0 V VOUT = 0.8 V CIN = COUT = 10 mF MLCC, X7R, 1206 size IOUT IOUT = 10 mA 0.1 1 mA IOUT = 200 mA RMS Output Noise 10 Hz - 100 kHz 100 Hz - 100 kHz 12.94 12.11 10 mA 12.78 12.25 200 mA 11.33 10.83 0.01 0.001 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 5. Output Voltage Noise Spectral Density for VOUT = 0.8 V, COUT = 10 mF http://onsemi.com 4 NCP702 OUTPUT VOLTAGE NOISE (mV/rtHz) TYPICAL CHARACTERISTICS 10 VIN = 3.8 V VOUT = 3.3 V CIN = COUT = 1 mF MLCC, X5R, 0402 size 1 IOUT = 1 mA 0.1 IOUT = 10 mA IOUT = 200 mA 0.01 0.001 IOUT 10 100 1k 10k 100k 1M RMS Output Noise 10 Hz - 100 kHz 100 Hz - 100 kHz 17.87 1 mA 20.28 10 mA 16.73 13.90 200 mA 13.70 10.21 10M FREQUENCY (Hz) OUTPUT VOLTAGE NOISE (mV/rtHz) Figure 6. Output Voltage Noise Spectral Density for VOUT = 3.3 V, COUT = 1 mF 10 VIN = 3.8 V VOUT = 3.3 V CIN = COUT = 4.7 mF MLCC, X7R, 1202 size 1 IOUT = 1 mA 0.1 IOUT IOUT = 10 mA IOUT = 200 mA RMS Output Noise 10 Hz - 100 kHz 100 Hz - 100 kHz 1 mA 15.76 11.82 10 mA 17.09 13.88 200 mA 14.51 11.47 0.01 0.001 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) OUTPUT VOLTAGE NOISE (mV/rtHz) Figure 7. Output Voltage Noise Spectral Density for VOUT = 3.3 V, COUT = 4.7 mF 10 VIN = 3.8 V VOUT = 3.3 V CIN = COUT = 10 mF MLCC, X7R, 1206 size 1 IOUT = 1 mA 0.1 IOUT IOUT = 10 mA 100 Hz - 100 kHz 14.87 10.57 10 mA 16.00 12.65 200 mA 14.89 11.84 1 mA IOUT = 200 mA RMS Output Noise 10 Hz - 100 kHz 0.01 0.001 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 8. Output Voltage Noise Spectral Density for VOUT = 3.3 V, COUT = 10 mF http://onsemi.com 5 NCP702 TYPICAL CHARACTERISTICS 100 60 80 50 40 IOUT = 1 mA IOUT = 10 mA IOUT = 50 mA IOUT = 150 mA IOUT = 200 mA 30 20 10 0 10 100 1k 10k 20 1M 10 0 10 10M 100k 1M 10M 60 80 70 50 40 IOUT = 1 mA IOUT = 10 mA IOUT = 50 mA IOUT = 150 mA IOUT = 200 mA 30 20 100 1k 10k 60 50 40 30 20 10 100k 1M 0 10 10M VIN = 3.8 V VOUT = 3.3 V COUT = 4.7 mF CIN = none MLCC, X7R, 1206 size 100 IOUT = 1 mA IOUT = 10 mA IOUT = 50 mA IOUT = 150 mA IOUT = 200 mA 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. Power Supply Rejection Ratio, VOUT = 3.3 V, COUT = 1 mF Figure 12. Power Supply Rejection Ratio, VOUT = 3.3 V, COUT = 4.7 mF 100 90 90 80 80 70 PSRR (dB) 70 60 50 10 0 10 10k 90 VIN = 3.8 V VOUT = 3.3 V COUT = 1 mF CIN = none MLCC, X5R, 0402 size 70 20 1k Figure 10. Power Supply Rejection Ratio, VOUT = 0.8 V, COUT = 4.7 mF 80 30 100 Figure 9. Power Supply Rejection Ratio, VOUT = 0.8 V, COUT = 1 mF 90 40 IOUT = 1 mA IOUT = 10 mA IOUT = 50 mA IOUT = 150 mA IOUT = 200 mA FREQUENCY (Hz) 110 PSRR (dB) 40 FREQUENCY (Hz) 100 10 0 10 60 50 30 100k CIN = none MLCC, X7R, 1206 size 70 PSRR (dB) PSRR (dB) 70 VIN = 2.0 V VOUT = 0.8 V COUT = 4.7 mF 90 PSRR (dB) 80 PSRR (dB) 100 VIN = 2.0 V VOUT = 0.8 V COUT = 1 mF CIN = none MLCC, X5R, 0402 size 90 VIN = 3.8 V VOUT = 3.3 V COUT = 10 mF CIN = none MLCC, X7R, 1206 size 100 IOUT = 1 mA IOUT = 10 mA IOUT = 50 mA IOUT = 150 mA IOUT = 200 mA 1k 10k 100k 1M f = 100 Hz f = 1 kHz 60 f = 10 kHz 50 f = 100 kHz 40 f = 1 MHz 30 20 VOUT = 3.3 V COUT = 4.7 mF CIN = none 10 10M 0 0 0.2 0.4 0.6 0.8 IOUT = 200 mA MLCC, X7R, 1206 size 1.0 1.2 1.4 FREQUENCY (Hz) VIN - VOUT VOLTAGE DIFFERENTIAL (V) Figure 13. Power Supply Rejection Ratio, VOUT = 3.3 V, COUT = 10 mF Figure 14. PSRR vs. Voltage Differential, COUT = 4.7 mF, IOUT = 200 mA http://onsemi.com 6 NCP702 TYPICAL CHARACTERISTICS 80 70 f = 1 kHz PSRR (dB) 60 f = 10 kHz 50 f = 100 kHz 40 f = 1 MHz VOUT = 3.3 V COUT = 4.7 mF CIN = none IOUT = 10 mA MLCC, X7R, 1206 size 30 20 10 0 IQ, QUIESCENT CURRENT (mA) 12 0 0.2 0.4 0.6 0.8 1.0 1.2 TJ = -40C 6 4 VOUT = 3.3 V IOUT = 0 mA COUT = 1 mF 2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN, INPUT VOLTAGE (V) Figure 15. PSRR vs. Voltage Differential, COUT = 4.7 mF, IOUT = 10 mA Figure 16. Quiescent Current vs. Input Voltage, VOUT = 3.3 V 140 VDROP, DROPOUT VOLTAGE (mV) IQ, QUIESCENT CURRENT (mA) 8 VIN - VOUT VOLTAGE DIFFERENTIAL (V) 12 TJ = 125C 10 TJ = 25C 8 TJ = -40C 6 4 VOUT = 0.8 V IOUT = 0 mA COUT = 1 mF 2 0 TJ = 25C 0 1.4 TJ = 125C 10 0 1 2 3 4 5 120 TJ = 25C 80 60 TJ = -40C 40 VOUT(nom) = 3.3 V CIN = COUT = 1 mF 20 0 6 TJ = 125C 100 0 20 VIN, INPUT VOLTAGE (V) 180 0.813 160 140 TJ = 125C TJ = 25C 60 TJ = -40C 40 20 0 VOUT(nom) = 2.5 V CIN = COUT = 1 mF 0 20 40 60 80 100 120 140 VOUT, OUTPUT VOLTAGE (V) VDROP, DROPOUT VOLTAGE (mV) 0.817 80 80 100 120 140 160 180 200 Figure 18. Dropout Voltage vs. Output Current, VOUT = 3.3 V 200 100 60 IOUT, OUTPUT CURRENT (mA) Figure 17. Quiescent Current vs. Input Voltage, VOUT = 0.8 V 120 40 0.809 0.805 0.801 0.797 0.793 VIN = 2.0 V VOUT(nom) = 0.8 V IOUT = 10 mA COUT = COUT = 1 mF 0.789 0.785 0.781 -40 -20 160 180 200 0 20 40 60 80 100 120 140 IOUT, OUTPUT CURRENT (mA) TJ, JUNCTION TEMPERATURE (C) Figure 19. Dropout Voltage vs. Output Current, VOUT = 2.5 V Figure 20. Output Voltage vs. Temperature, VOUT = 0.8 V http://onsemi.com 7 NCP702 TYPICAL CHARACTERISTICS 1.804 1.800 1.796 1.792 1.788 1.784 0 20 40 60 80 100 120 140 8 7 3.297 3.293 3.289 3.285 -40 -20 0 20 40 60 80 100 120 140 Figure 22. Output Voltage vs. Temperature, VOUT = 3.3 V VIN = 2.0 V VOUT = 0.8 V IOUT = 0 mA ... 200 mA COUT = COUT = 1 mF 4 3 2 1 0 -40 -20 0 20 40 60 80 100 120 140 10 9 8 7 VIN = 2.1 V VOUT = 1.8 V IOUT = 0 mA ... 200 mA COUT = COUT = 1 mF 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 120 140 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 23. Load Regulation vs. Temperature, VOUT = 0.8 V Figure 24. Load Regulation vs. Temperature, VOUT = 1.8 V 10 7 3.301 Figure 21. Output Voltage vs. Temperature, VOUT = 1.8 V 5 8 3.305 TJ, JUNCTION TEMPERATURE (C) 6 9 3.309 TJ, JUNCTION TEMPERATURE (C) 10 9 VIN = 3.8 V VOUT = 3.3 V IOUT = 10 mA COUT = COUT = 1 mF 3.313 REGLOAD, LOAD REGULATION (mV) REGLOAD, LOAD REGULATION (mV) VOUT, OUTPUT VOLTAGE (V) 1.808 1.780 -40 -20 REGLOAD, LOAD REGULATION (mV) 3.317 VIN = 2.1 V VOUT = 1.8 V IOUT = 10 mA COUT = COUT = 1 mF 1.812 1000 REGLINE, LINE REGULATION (mV/V) VOUT, OUTPUT VOLTAGE (V) 1.816 VIN = 3.6 V VOUT = 3.3 V IOUT = 0 mA ... 200 mA COUT = COUT = 1 mF 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 120 140 VOUT = 0.8 V IOUT = 10 mA COUT = COUT = 1 mF 900 800 700 600 500 VIN = 2.0 V ... 5.5 V 400 300 VIN = 2.0 V ... 4.5 V 200 100 0 -40 -20 0 20 40 60 80 100 120 140 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 25. Load Regulation vs. Temperature, VOUT = 3.3 V Figure 26. Line Regulation vs. Temperature, VOUT = 0.8 V http://onsemi.com 8 NCP702 TYPICAL CHARACTERISTICS 1000 REGLINE, LINE REGULATION (mV/V) REGLINE, LINE REGULATION (mV/V) 1000 VOUT = 1.8 V IOUT = 10 mA COUT = COUT = 1 mF 900 800 700 600 500 VIN = 2.1 V ... 5.5 V 400 300 VIN = 2.1 V ... 4.5 V 200 100 0 -40 -20 0 20 40 60 80 100 120 140 0.35 0.15 0.10 0.05 0 -0.05 -40 -20 300 VOUT = 3.3 V IOUT = 10 mA COUT = COUT = 1 mF 200 100 0 -40 -20 0 20 40 60 80 100 120 0.45 0 20 40 60 80 100 120 140 0.40 0.35 VIN = 5.5 V VOUT = 3.3 V VEN = 0 V COUT = COUT = 1 mF 0.30 0.25 0.20 0.15 0.10 0.05 0 -0.05 -40 -20 140 0 20 40 60 80 100 120 140 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 29. Disable Current vs. Temperature, VOUT = 1.8 V Figure 30. Disable Current vs. Temperature, VOUT = 3.3 V 450 0.50 VIN = 5.5 V VOUT = 0.8 V VEN = 0 V COUT = COUT = 1 mF IOUT, OUTPUT CURRENT (mA) IDIS, DISABLE CURRENT (mA) 400 0.50 VIN = 5.5 V VOUT = 1.8 V VEN = 0 V COUT = COUT = 1 mF 0.20 0.35 VIN = 3.6 V ... 4.5 V Figure 28. Line Regulation vs. Temperature, VOUT = 3.3 V 0.25 0.40 600 500 Figure 27. Line Regulation vs. Temperature, VOUT = 1.8 V 0.30 0.45 VIN = 3.6 V ... 5.5 V 700 TJ, JUNCTION TEMPERATURE (C) IDIS, DISABLE CURRENT (mA) IDIS, DISABLE CURRENT (mA) 0.40 800 TJ, JUNCTION TEMPERATURE (C) 0.50 0.45 900 0.30 0.25 0.20 0.15 0.10 0.05 0 -0.05 -40 -20 0 20 40 60 80 100 120 430 410 390 370 350 Output Current Limit VOUT = VOUT(nom) - 0.1 V 330 310 VIN = VEN = 2 V VOUT(nom) = 0.8 V CIN = COUT = 1 mF 290 270 250 -40 140 Output Short Circuit VOUT = 0 V -20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 31. Disable Current vs. Temperature, VOUT = 0.8 V Figure 32. Output Current Limit vs. Temperature, VOUT = 0.8 V http://onsemi.com 9 120 140 NCP702 TYPICAL CHARACTERISTICS 470 450 430 VIN = VEN = 3.6 V VOUT(nom) = 3.3 V CIN = COUT = 1 mF VEN_LOW, EN LOW THRESHOLD (V) IOUT, OUTPUT CURRENT (mA) 490 Output Short Circuit VOUT = 0 V 410 390 Output Current Limit VOUT = VOUT(nom) - 0.1 V 370 350 330 310 290 -40 -20 0 20 40 60 80 100 120 140 1.0 VOUT(nom) = 3.3 V VIN = 3.6 V IOUT = 10 mA COUT = COUT = 1 mF 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 -40 -20 0 20 40 60 80 100 120 140 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 33. Output Current Limit vs. Temperature, VOUT = 3.3 V Figure 34. Enable Low Threshold Voltage OUT IINRUSH IINRUSH = 60 mA 0.6 0.5 0.4 0.3 0.2 -40 -20 0 20 40 60 80 100 120 EN 140 100 ms/div TJ, JUNCTION TEMPERATURE (C) VIN = 2.0 V VOUT(nom) = 0.8 V COUT = 1 mF CIN = none IOUT = 1 mA TA = 25C 0.5 V/div VIN = 3.6 V VOUT(nom) = 3.3 V COUT = 3 mF CIN = none IOUT = 1 mA TA = 25C IINRUSH = 115 mA IINRUSH IINRUSH = 20 mA EN 1 V/div 1 V/div Figure 36. Enable Turn-On Response, VOUT = 3.3 V, COUT = 1 mF 50 mA/div 1 V/div Figure 35. Enable High Threshold Voltage OUT 50 mA/div 0.7 VIN = 3.6 V VOUT(nom) = 3.3 V COUT = 1 mF CIN = none IOUT = 1 mA TA = 25C 100 ms/div 100 ms/div Figure 37. Enable Turn-On Response, VOUT = 3.3 V, COUT = 3 mF Figure 38. Enable Turn-On Response, VOUT = 0.8 V, COUT = 1 mF http://onsemi.com 10 50 mA/div 0.8 1 V/div VOUT(nom) = 3.3 V VIN = 3.6 V IOUT = 10 mA COUT = COUT = 1 mF 0.9 1 V/div VEN_HI, EN HIGH THRESHOLD (V) 1.0 NCP702 TYPICAL CHARACTERISTICS IINRUSH = 45 mA IINRUSH, INRUSH CURRENT (mA) 1 V/div 0.5 V/div VIN = 2.0 V VOUT(nom) = 0.8 V COUT = 3 mF CIN = none IOUT = 1 mA TA = 25C 50 mA/div 200 VIN = VOUT + 0.3 V or 2 V whichever is greater VEN = 0 V to 1 V CIN = none, TJ = 25C IOUT = 1 mA 160 120 VOUT = 3.3 V 80 VOUT = 0.8 V 40 0 100 ms/div 1 1.5 2 2.5 3 3.5 4 4.5 COUT, OUTPUT CAPACITANCE (mF) Figure 39. Enable Turn-On Response, VOUT = 0.8 V, COUT = 3 mF Figure 40. Turn-On Inrush Current vs. Output Capacitance Figure 41. Enable Turn-Off Response, VOUT = 3.3 V, COUT = 1 mF Figure 42. Enable Turn-Off Response, VOUT = 3.3 V, COUT = 4.7 mF Figure 43. Enable Turn-Off Response, VOUT = 3.3 V, COUT = 10 mF Figure 44. Slow Input Voltage Turn-On/Turn-Off, VOUT = 3.3 V http://onsemi.com 11 5 NCP702 TYPICAL CHARACTERISTICS Figure 45. Line Transient Response - Rising Edge, VOUT = 3.3 V Figure 46. Line Transient Response - Falling Edge, VOUT = 3.3 V Figure 47. Load Transient Response - Rising Edge, IOUT = 1 mA - 200 mA, VOUT = 0.8 V Figure 48. Load Transient Response - Falling Edge, IOUT = 1 mA - 200 mA, VOUT = 0.8 V Figure 49. Load Transient Response - Rising Edge, IOUT = 1 mA - 200 mA, COUT = 1.0 mF Figure 50. Load Transient Response - Falling Edge, IOUT = 1 mA - 200 mA, COUT = 1.0 mF http://onsemi.com 12 NCP702 TYPICAL CHARACTERISTICS Figure 51. Load Transient Response - Rising Edge, IOUT = 1 mA - 200 mA, COUT = 4.7 mF Figure 52. Load Transient Response - Falling Edge, IOUT = 1 mA - 200 mA, COUT = 4.7 mF Figure 53. Load Transient Response - Rising Edge, IOUT = 1 mA - 200 mA, COUT = 10 mF Figure 54. Load Transient Response - Falling Edge, IOUT = 1 mA - 200 mA, COUT = 10 mF Figure 55. Output Short Circuit Response Figure 56. Cycling between Output Short Circuit and Thermal Shutdown http://onsemi.com 13 NCP702 TYPICAL CHARACTERISTICS IGND, GROUND CURRENT (mA) 70 60 50 TJ = -40C 40 TJ = 25C 30 VIN = 3.6 V VOUT = 3.3 V CIN = COUT = 1 mF MLCC, X7R, 1206 size 20 10 0 0.12 IEN, EN PIN INPUT CURRENT (mA) 180 TJ = 125C 0 0.5 1 1.5 2 2.5 3 3.5 4 TJ = 125C TJ = 25C 160 140 TJ = -40C 120 100 80 VIN = 3.6 V VOUT = 3.3 V CIN = COUT = 1 mF MLCC, X7R, 1206 size 60 40 20 0 4.5 0 20 40 60 80 100 120 140 160 180 200 IOUT, OUTPUT CURRENT (mA) IOUT, OUTPUT CURRENT (mA) Figure 57. Ground Current vs. Output Current, IOUT = 0 mA to 5 mA Figure 58. Ground Current vs. Output Current, IOUT = 0 mA to 200 mA 10 VOUT = 0.8 V 0.10 Unstable Operation 1 VOUT = 3.3 V 0.08 ESR (W) IGND, GROUND CURRENT (mA) 80 0.06 VIN = 5.5 V VOUT = 1.8 V IOUT = 10 mA TJ = 25C CIN = COUT = 1 mF 0.04 0.02 0 0 0.5 1.0 1.5 2.0 2.5 Stable Operation 0.1 0.01 3.0 3.5 4.0 4.5 5.0 5.5 0.001 VIN = VOUT(nom) + 0.3 V or 2 V COUT = CIN = 1 mF TA = 25C 0 20 40 60 80 100 120 140 160 180 200 VEN, ENABLE VOLTAGE (V) IOUT, OUTPUT CURRENT (mA) Figure 59. EN Pin Input Current vs. Enable Pin Voltage Figure 60. Output Capacitor ESR vs. Output Current http://onsemi.com 14 NCP702 APPLICATIONS INFORMATION General capacitor will limit the influence of input trace inductance and source resistance during sudden load current changes. Larger input capacitor may be necessary if fast and large load transients are encountered in the application. The NCP702 is a high performance 200 mA Low Dropout Linear Regulator. This device delivers excellent noise and dynamic performance. Thanks to its adaptive ground current feature the device consumes only 10 mA of quiescent current at no-load condition. The regulator features ultra-low noise of 11 mVRMS, PSRR of 68 dB at 1 kHz and very good load/line transient performance. Such excellent dynamic parameters and small package size make the device an ideal choice for powering the precision analog and noise sensitive circuitry in portable applications. The LDO achieves this ultra low noise level output without the need for a noise bypass capacitor. A logic EN input provides ON/OFF control of the output voltage. When the EN is low the device consumes as low as typ. 10 nA from the IN pin. The LDO achieves ultra-low output voltage noise without the need for additional noise bypass capacitor. The device is fully protected in case of output overload, output short circuit condition and overheating, assuring a very robust design. Output Decoupling (COUT) The NCP702 is designed to be stable with a small 1.0 mF ceramic capacitor on the output. To assure proper operation it is strongly recommended to use min. 1.0 mF capacitor with the initial tolerance of 10%, made of X7R or X5R dielectric material types. There is no requirement for the minimum value of Equivalent Series Resistance (ESR) for the COUT but the maximum value of ESR should be less than 700 mW. Larger output capacitors could be used to improve the load transient response or high frequency PSRR as shown in typical characteristics. The initial tolerance requirements can be wider than 10% when using capacitors larger than 1 mF. It is not recommended to use tantalum capacitors on the output due to their large ESR. The equivalent series resistance of tantalum capacitors is also strongly dependent on the temperature, increasing at low temperature. The tantalum capacitors are generally more costly than ceramic capacitors. The table on this page lists the capacitors which were used during the IC evaluation. Input Capacitor Selection (CIN) It is recommended to connect a minimum of 1 mF Ceramic X5R or X7R capacitor close to the IN pin of the device. This capacitor will provide a low impedance path for unwanted AC signals or noise modulated onto constant input voltage. There is no requirement for the min./max. ESR of the input capacitor but it is recommended to use ceramic capacitors for their low ESR and ESL. A good input VIN 2 V ... 5.5 V C1 IN EN No-load Operation The regulator remains stable and regulates the output voltage properly within the 2% tolerance limits even with no external load applied to the output. OUT NCP702 VOUT 0 mA ... 200 mA C2 GND U1 Figure 61. Typical Applications Schematics LIST OF CAPACITORS USED DURING THE NCP702 EVALUATION: Symbol C1, C2 Manufacturer Part Number Description Kemet C0402C105K8PACTU 1 mF Ceramic 10%, 10 V, 0402, X5R TDK C1005X5R1A105K -||- Murata GRM155R61A105KE15D -||- AVX 0402ZD105KAT2A -||- Multicomp MCCA000571 1 mF Ceramic 10%, 50 V, 1206, X7R Panason - ECG ECJ-0EB0J475M 4.7 mF Ceramic 20%, 6.3 V, 0402, X5R http://onsemi.com 15 NCP702 APPLICATIONS INFORMATION Enable Operation the nominal VOUT. If the Output Voltage is directly shorted to ground (VOUT = 0 V), the short circuit protection will limit the output current to 390 mA (typ). The current limit and short circuit protection will work properly up to VIN = 5.5 V at TA = 25C. There is no limitation for the short circuit duration. The NCP702 uses the EN pin to enable/disable its output and to deactivate/activate the active discharge function. If the EN pin voltage is <0.4 V the device is guaranteed to be disabled. The pass transistor is turned-off so that there is virtually no current flow between the IN and OUT. The active discharge transistor is active so that the output voltage VOUT is pulled to GND through a 1 kW resistor. In the disable state the device consumes as low as typ. 10 nA from the VIN. If the EN pin voltage >0.9 V the device is guaranteed to be enabled. The NCP702 regulates the output voltage and the active discharge transistor is turned-off. The EN pin has internal pull-down current source with typ. value of 110 nA which assures that the device is turned-off when the EN pin is not connected. A build in 2 mV of hysteresis in the EN prevents from periodic on/off oscillations that can occur due to noise. In the case where the EN function isn't required the EN pin should be tied directly to IN. Thermal Shutdown When the die temperature exceeds the Thermal Shutdown threshold (TSD - 160C typical), Thermal Shutdown event is detected and the device is disabled. The IC will remain in this state until the die temperature decreases below the Thermal Shutdown Reset threshold (TSDU - 140C typical). Once the IC temperature falls below the 140C the LDO is enabled again. The thermal shutdown feature provides protection from a catastrophic device failure due to accidental overheating. This protection is not intended to be used as a substitute for proper heat sinking. Power Dissipation As power dissipated in the NCP702 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. For reliable operation junction temperature should be limited to +125C. The maximum power dissipation the NCP702 can handle is given by: Undervoltage Lockout The internal UVLO circuitry assures that the device becomes disabled when the VIN falls below typ. 1.5 V. When the VIN voltage ramps-up the NCP702 becomes enabled, if VIN rises above typ. 1.6 V. The 100 mV hysteresis prevents on/off oscillations that can occur due to noise on VIN line. Reverse Current The PMOS pass transistor has an inherent body diode which will be forward biased in the case that VOUT > VIN. Due to this fact in cases where the extended reverse current condition is anticipated the device may require additional external protection. P D(MAX) + P D [ V INI GND@I OUT ) I OUTV IN * V OUT 330 0.65 310 0.60 290 0.55 PD(MAX), TA = 25C, 2 OZ CU 250 0.50 0.45 230 qJA, 1 OZ CU 210 qJA, 2 OZ CU 190 P D(MAX), TA = 25C, 1 OZ CU 170 0.40 0.35 0.30 0.25 0 100 200 300 400 500 600 0.20 700 PCB COPPER AREA (mm2) Figure 62. qJA and PD(MAX) vs. Copper Area (TSOP5) http://onsemi.com 16 PD(MAX), MAXIMUM POWER DISSIPATION (W) qJA, JUNCTION TO AMBIENT THERMAL RESISTANCE (C/W) Output Current is internally limited within the IC to a typical 380 mA. The NCP702 will source this amount of current measured with the output voltage 100 mV lower than 150 q JA (eq. 1) The power dissipated by the NCP702 for given application conditions can be calculated from the following equations: Output Current Limit 270 125 * T A (eq. 2) NCP702 0.8 350 0.7 PD(MAX), TA = 25C, 2 OZ CU 300 0.6 250 200 0.4 qJA, 1 OZ CU 150 0.3 qJA, 2 OZ CU 100 50 0.5 PD(MAX), TA = 25C, 1 OZ CU 0 100 200 300 400 500 700 600 0.2 PD(MAX), MAXIMUM POWER DISSIPATION (W) qJA, JUNCTION TO AMBIENT THERMAL RESISTANCE (C/W) 400 0.1 800 PCB COPPER AREA (mm2) Figure 63. qJA and PD(MAX) vs. Copper Area (XDFN6) 400 The NCP702 features very good load regulation of maximum 2.6 mV in the 0 mA to 200 mA range. In order to achieve this very good load regulation a special attention to PCB design is necessary. The trace resistance from the OUT pin to the point of load can easily approach 100 m which will cause a 20 mV voltage drop at full load current, deteriorating the excellent load regulation. 360 EN, TURN-ON TIME (ms) Load Regulation Line Regulation The IC features very good line regulation of 0.44 mV/V measured from VIN = VOUT + 0.3 V to 5.5 V. For battery operated applications it may be important that the line regulation from VIN = VOUT + 0.3 V up to 4.5 V is only 0.29 mV/V. VOUT = 3.3 V 320 280 240 VOUT = 0.8 V 200 VOUT = 1.8 V 160 120 VIN = VOUT + 0.3 V or 2 V IOUT = 10 mA CIN = COUT = 1 mF VEN = 0 V -> 0.9 V 80 40 0 -40 -20 0 20 40 60 80 100 120 140 TJ, JUNCTION TEMPERATURE (C) Figure 64. Turn-On Time vs. Temperature Power Supply Rejection Ratio The NCP702 features very good Power Supply Rejection ratio. If desired the PSRR at higher frequencies in the range 100 kHz - 10 MHz can be tuned by the selection of COUT capacitor and proper PCB layout. Internal SoftStart The Internal Soft-Start circuitry will limit the inrush current during the LDO turn-on phase. Please refer to Figure 43 for typical inrush current values for given output capacitance. The soft-start function prevents from any output voltage overshoots and assures monotonic ramp-up of the output voltage. Output Noise The IC is designed for ultra-low noise output voltage. Figures 3 - 8 illustrate the noise performance for different VOUT, IOUT, COUT. Generally the noise performance in the indicated frequency range improves with increasing output current, although even at IOUT = 1 mA the noise levels are below 22 mVRMS. PCB Layout Recommendations To obtain good transient performance and good regulation characteristics place CIN and COUT capacitors close to the device pins and make the PCB traces wide. In order to minimize the solution size use 0402 capacitors. Larger copper area connected to the pins will also improve the device thermal resistance. The actual power dissipation can be calculated by the formula given in Equation 2. Turn-On Time The turn-on time is defined as the time period from EN assertion to the point in which VOUT will reach 98% of its nominal value. This time is dependent on VOUT(NOM), COUT, TA. The turn-on time temperature dependence is shown below: http://onsemi.com 17 NCP702 ORDERING INFORMATION Device Voltage Option Marking NCP702MX18TCG 1.8 V P NCP702MX28TCG 2.8 V 2 NCP702MX30TCG 3.0 V 3 NCP702MX33TCG 3.3 V 4 NCP702SN18T1G 1.8 V A7J NCP702SN28T1G 2.8 V AD2 NCP702SN30T1G 3.0 V A7R NCP702SN31T1G 3.1 V A7P NCP702SN33T1G 3.3 V A7T Package Shipping XDFN6 (Pb-Free) 3000 / Tape & Reel TSOP5 (Pb-Free) 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 18 NCP702 PACKAGE DIMENSIONS XDFN6 1.5x1.5, 0.5P CASE 711AE ISSUE A D L A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.10 AND 0.20mm FROM TERMINAL TIP. L1 PIN ONE REFERENCE 0.10 C 2X 2X 0.10 C III III III III DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D E e L L1 L2 EEE EEE EXPOSED Cu TOP VIEW MOLD CMPD DETAIL B ALTERNATE CONSTRUCTIONS A DETAIL B A3 0.05 C A1 RECOMMENDED MOUNTING FOOTPRINT* 0.05 C C SIDE VIEW DETAIL A e 1 MILLIMETERS MIN MAX 0.35 0.45 0.00 0.05 0.13 REF 0.20 0.30 1.50 BSC 1.50 BSC 0.50 BSC 0.40 0.60 --0.15 0.50 0.70 SEATING PLANE 6X 0.35 5X 0.73 5X L 3 1.80 L2 0.83 0.50 PITCH DIMENSIONS: MILLIMETERS 6 4 6X 0.10 C A BOTTOM VIEW *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. b 0.05 C B NOTE 3 http://onsemi.com 19 NCP702 PACKAGE DIMENSIONS TSOP-5 CASE 483-02 ISSUE K 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. D 5X NOTE 5 0.20 C A B 0.10 T M 2X 0.20 T B 5 1 4 2 B S 3 K DETAIL Z G A A TOP VIEW DIM A B C D G H J K M S DETAIL Z J C 0.05 H SIDE VIEW C SEATING PLANE END VIEW MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 0_ 10 _ 2.50 3.00 SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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