1. General description
The 74LVC1G3157 provides one analog multiplexer/demultiplexer with one digital select
input (S), two independent inputs/outputs (Y0, Y1) and a common in put/output (Z).
Schmitt trigger action at the select input makes the circuit tolerant of slower input rise and
fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 (typical) at VCC =2.7V
6.5 (typical) at VCC =3.3V
6 (typical) at VCC =5V
Switch current capability of 32 mA
Break-before-make switching
High noise immunity
CMOS low power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD 78 Class I
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Control input acc ep ts voltages up to 5.5 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
74LVC1G3157
2-channel analog multiplexer/demultiplexer
Rev. 4 — 6 December 2011 Product data sheet
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 2 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Tabl e 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC1G3157GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363
74LVC1G3157GV 40 C to +125 C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457
74LVC1G3157GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm SOT886
74LVC1G3157GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 10.5 mm SOT891
74LVC1G3157GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm SOT1115
74LVC1G3157GS 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm SOT1202
Table 2. Marking
Type number Marking code[1]
74LVC1G3157GW YJ
74LVC1G3157GV YJ
74LVC1G3157GM YJ
74LVC1G3157GF YJ
74LVC1G3157GN YJ
74LVC1G3157GS YJ
Fig 1. Logic symbol Fig 2. Logic diagra m
001aac354
Y0
Y1 6
4
S
Z
1
3
001aac355
ZS
Y1
Y0
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Product data sheet Rev. 4 — 6 December 2011 3 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level.
Fig 3. Pin configuration SOT363
and SOT457 Fig 4. Pin configuration SOT886 Fig 5. Pin configuration SOT891,
SOT1115 and SOT 1202
74LVC1G3157
Y1 S
GND
Y0 Z
001aac356
1
2
3
6
V
CC
5
4
74LVC1G3157
Z
V
CC
S
Y0
GND
Y1
001aac357
34
25
16
Transparent top view
74LVC1G3157
GND
001aaf546
Y1
Y0
VCC
S
Z
Transparent top view
2
3
1
5
4
6
Table 3. Pin description
Symbol Pin Description
Y1 1 independent input or output
GND 2 ground (0 V)
Y0 3 independent input or output
Z 4 common output or input
VCC 5 supply voltage
S 6 select input
Table 4. Function table[1]
Input S Channel on
LY0
HY1
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Product data sheet Rev. 4 — 6 December 2011 4 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
8. Limiting values
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3] For SC-88 and SC-74 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
[1] To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit
for the voltage drop across the switch.
[2] Applies to control signal levels.
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
VIinput voltage [1] 0.5 +6.5 V
IIK input clamping current VI<0.5 V or VI>V
CC + 0.5 V 50 - mA
ISK switch clamping current VI<0.5 V or VI>V
CC + 0.5 V - 50 mA
VSW switch voltage enable and disable mode [2] 0.5 VCC + 0.5 V
ISW switch current VSW >0.5 V or VSW < VCC + 0.5 V - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 Cto+125C[3] - 250 mW
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 5.5 V
VIinput voltage 0 - 5.5 V
VSW switch voltage enable and disable mode [1] 0- V
CC V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and fall rate VCC =1.65Vto2.7V [2] --20ns/V
VCC = 2.7 V to 5.5 V [2] --10ns/V
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 5 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
10. Static characteristics
[1] Typical values are measured at Tamb = 25 C.
[2] These typical values are measured at VCC =3.3V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.65 V to 1.95 V 0.65VCC - - 0.65VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 3 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC -V
VIL LOW-level
input voltage VCC = 1.65 V to 1.95 V - - 0.35VCC -0.35V
CC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 3 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3VCC 0.3VCC V
IIinput leakage
current pin S; VI=5.5VorGND;
VCC =0Vto5.5V [2] -0.1 2-10 A
IS(OFF) OFF-state
leakage
current
VCC = 5.5 V; see Figure 6 [2] -0.1 5-20 A
IS(ON) ON-state
leakage
current
VCC = 5.5 V; see Figure 7 [2] -0.1 5-20 A
ICC supply current VI= 5.5 V or GND;
VSW =GNDorV
CC; VCC = 1.65 V
to 5.5 V
[2] -0.110 - 40A
ICC additional
supply current pin S; VI=V
CC 0.6 V;
VCC = 5.5 V; VSW = GND or VCC
[2] - 5 500 - 5000 A
CIinput
capacitance -2.5- - -pF
CS(OFF) OFF-state
capacitance -6.0- - -pF
CS(ON) ON-state
capacitance -18- - -pF
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 6 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
10.1 Test circuits
10.2 ON resistance
VI=V
CC or GND and VO=GNDor V
CC.
Fig 6. Test circuit for measuring OFF-state leakage current
I
S
001aac358
S
Z
Y0
Y1
V
CC
GND
switch
switch
1
12
2
V
IL
V
IH
S
V
IL
or V
IH
VIVO
VI=V
CC or GND and VO= open circuit.
Fig 7. Test circuit for measuring ON-state leakage current
IS
001aac359
S
Z
Y0
Y1
VCC
GND
switch
switch
1
12
2
VIL
VIH
S
VO
VIL or VIH
VI
Table 8. ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
RON(peak) ON resistance (peak) VI=GNDtoV
CC; see Figure 8
ISW =4mA;
VCC = 1.65 V to 1.95 V - 34.0 130 - 195
ISW =8mA; V
CC = 2.3 V to 2.7 V - 12.0 30 - 45
ISW =12mA; V
CC = 2.7 V - 10.4 25 - 38
ISW =24mA; V
CC = 3 V to 3.6 V - 7.8 20 - 30
ISW =32mA; V
CC = 4.5 V to 5.5 V - 6.2 15 - 23
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Product data sheet Rev. 4 — 6 December 2011 7 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
[1] Typical values are measured at Tamb = 25 C and nominal VCC.
[2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
RON(rail) ON resistance (rail) VI= GND; see Figure 8
ISW =4mA;
VCC = 1.65 V to 1.95 V -8.218 - 27
ISW =8mA; V
CC = 2.3 V to 2.7 V - 7.1 16 - 24
ISW =12mA; V
CC = 2.7 V - 6.9 14 - 21
ISW =24mA; V
CC = 3 V to 3.6 V - 6.5 12 - 18
ISW =32mA; V
CC = 4.5 V to 5.5 V - 5.8 10 - 15
VI=V
CC; see Figure 8
ISW =4mA;
VCC = 1.65 V to 1.95 V - 10.4 30 - 45
ISW =8mA; V
CC = 2.3 V to 2.7 V - 7.6 20 - 30
ISW =12mA; V
CC = 2.7 V - 7.0 18 - 27
ISW =24mA; V
CC = 3 V to 3.6 V - 6.1 15 - 23
ISW =32mA; V
CC = 4.5 V to 5.5 V - 4.9 10 - 15
RON(flat) ON resistance
(flatness) VI=GNDtoV
CC [2]
ISW =4mA;
VCC = 1.65 V to 1.95 V -26.0- - -
ISW =8mA; V
CC = 2.3 V to 2.7 V - 5.0 - - -
ISW =12mA; V
CC =2.7V - 3.5 - - -
ISW =24mA; V
CC =3Vto3.6V - 2.0 - - -
ISW =32mA; V
CC = 4.5 V to 5.5 V - 1.5 - - -
Table 8. ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
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Product data sheet Rev. 4 — 6 December 2011 8 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
10.3 ON resistance test circuit and graphs
RON =V
SW / ISW.(1)V
CC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5) VCC = 5.0 V.
Fig 8. Test circuit for measuring ON resistance Fig 9. Typical ON resistance as a function of input
voltage; Tamb = 25 C
001aac360
S
Z
Y0
Y1
VCC
GND
switch
switch
1
12
2
VIH
VIL
S
VIL or VIH
VI
ISW
VSW
V
VI (V)
054231
mna673
20
10
30
40
RON
(Ω)
0
(1)
(2)
(3)
(4) (5)
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
Fig 10. ON resistance as a function of input voltage;
VCC =1.8V Fig 11. ON resistance as a function of input voltage;
VCC =2.5V
VI (V)
0 2.01.60.8 1.20.4
001aaa712
25
35
15
45
55
RON
(Ω)
5
(4)
(3)
(2)
(1)
VI (V)
0 2.52.01.0 1.50.5
001aaa708
9
11
7
13
15
RON
(Ω)
5
(1)
(2)
(3)
(4)
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Product data sheet Rev. 4 — 6 December 2011 9 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
Fig 12. ON resistance as a function of input voltage;
VCC =2.7V Fig 13. ON resistance as a function of input voltage;
VCC =3.3V
001aaa709
VI (V)
0 3.02.01.0 2.51.50.5
9
7
11
13
RON
(Ω)
5
(1)
(2)
(3)
(4)
VI (V)
04312
001aaa710
6
8
10
RON
(Ω)
4
(1)
(2)
(3)
(4)
(1) Tamb = 125 C.
(2) Tamb =85C.
(3) Tamb =25C.
(4) Tamb =40 C.
Fig 14. ON resistance as a function of input voltage; VCC =5.0V
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Product data sheet Rev. 4 — 6 December 2011 10 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25C and nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPLZ and tPHZ.
[6] Break-before-make specified by design.
Table 9. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay Z to Yn or Yn to Z; see Figure 15 [2][3]
VCC = 1.65 V to 1.95 V - - 2 - 3.0 ns
VCC = 2.3 V to 2.7 V - - 1.2 - 2.0 ns
VCC = 2.7 V - - 1.0 - 1.5 ns
VCC = 3 V to 3.6 V - - 0.8 - 1.5 ns
VCC = 4.5 V to 5.5 V - - 0.6 - 1.0 ns
ten enable time S to Yn; see Figure 16 [4]
VCC = 1.65 V to 1.95 V 1.0 8.7 14 1.0 14.0 ns
VCC = 2.3 V to 2.7 V 1.0 5.3 7.5 1.0 7.5 ns
VCC = 2.7 V 1.0 4.9 6.0 1.0 6.0 ns
VCC = 3 V to 3.6 V 0.5 4.0 5.5 0.5 5.5 ns
VCC = 4.5 V to 5.5 V 0.5 3.0 4.0 0.5 4.0 ns
tdis disable time S to Yn; see Figure 16 [5]
VCC = 1.65 V to 1.95 V 2.5 6.0 8.5 2.5 8.5 ns
VCC = 2.3 V to 2.7 V 2.0 4.4 6.0 2.0 6.0 ns
VCC = 2.7 V 1.5 4.2 5.0 1.5 5.0 ns
VCC = 3 V to 3.6 V 1.5 3.6 4.5 1.5 4.5 ns
VCC = 4.5 V to 5.5 V 0.8 2.9 3.5 0.8 3.5 ns
tb-m break-before-make
time see Figure 17 [6]
VCC = 1.65 V to 1.95 V 0.5 - - 0.5 - ns
VCC = 2.3 V to 2.7 V 0.5 - - 0.5 - ns
VCC =2.7V 0.5 - - 0.5 - ns
VCC =3Vto3.6V 0.5 - - 0.5 - ns
VCC = 4.5 V to 5.5 V 0.5 - - 0.5 - ns
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 11 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
11.1 Waveforms and test circuits
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 15. Inpu t (Yn or Z) to output (Z or Yn) prop a ga t io n de la y s
t
PLH
t
PHL
V
M
V
M
V
M
V
M
GND
V
I
V
OH
V
OL
Yn or Z
input
Z or Yn
output
001aac361
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Enable and disable times
tPLZ
tPHZ
switch
disabled switch
enabled
switch
enabled
output
LOW to OFF
OFF to LOW
output
HIGH to OFF
OFF to HIGH
S input
Yn
Yn
VI
VOL
VOH
VCC
VM
VM
VX
VY
VM
GND
GND
tPZL
tPZH
001aac362
Table 10. Measurement poin ts
Supply voltage Input Output
VCC VMVMVXVY
1.65 V to 5.5 V 0.5VCC 0.5VCC VOL +0.3V V
OH 0.3 V
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Product data sheet Rev. 4 — 6 December 2011 12 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
a. Test circuit
b. Input and output measurement points
Fig 17. Test circuit for measu ring break-before-make timing
VO
VI
001aac367
S
Z
Y0
Y1
RLCL
0.5VCC
VCC
GND
G
001aag572
VI
tb-m
VO
0.9VO
0.9VO
0.5VI
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 18. Test circuit for measuring switching times
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
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Product data sheet Rev. 4 — 6 December 2011 13 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
11.2 Additional dynamic characteristics
Table 11. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ
1.65 V to 1.95 V VCC 2.0ns 50pF 500open GND 2VCC
2.3 V to 2.7 V VCC 2.0ns 50pF 500open GND 2VCC
2.7 V VCC 2.5ns 50pF 500open GND 2VCC
3 V to 3.6 V VCC 2.5ns 50pF 500open GND 2VCC
4.5 V to 5.5 V VCC 2.5ns 50pF 500open GND 2VCC
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb =25
C.
Symbol Parameter Conditions Min Typ Max Unit
THD tot al ha rmo n ic distortion fi= 6 00 Hz to 20 kHz; RL= 600 ;
CL=50pF; V
I= 0.5 V (p-p);
see Figure 19
VCC =1.65V - 0.260 - %
VCC = 2.3 V - 0.078 - %
VCC = 3.0 V - 0.078 - %
VCC = 4.5 V - 0.078 - %
f(-3dB) 3 dB frequency response RL=50; CL= 5 pF; see Figure 20
VCC =1.65V - 200 - MHz
VCC =2.3V - 300 - MHz
VCC =3.0V - 300 - MHz
VCC =4.5V - 300 - MHz
iso isolation (OFF-state) RL=50; CL=5pF; f
i=10MHz;
see Figure 21
VCC =1.65V - 42 - dB
VCC =2.3V - 42 - dB
VCC =3.0V - 40 - dB
VCC =4.5V - 40 - dB
Qinj charge injection CL= 0.1 nF; Vgen =0V; R
gen =0;
fi= 1 MHz; RL=1 M; see Figure 22
VCC = 1.8 V - 3.3 - pC
VCC = 2.5 V - 4.1 - pC
VCC = 3.3 V - 5.0 - pC
VCC = 4.5 V - 6.4 - pC
VCC = 5.5 V - 7.5 - pC
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 14 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
11.3 Test circuits
Fig 19. Test circuit for measu ring total harmonic distortion
D
001aac363
600 Ω
10 μF
0.1 μF
S
Z
Y0
Y1
V
CC
0.5V
CC
GND
C
L
R
L
switch
switch
1
12
2
V
IH
V
IL
S
f
i
V
IL
or V
IH
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3dB.
Fig 20. Test circuit for measuring the frequency response when switch is in ON-state
dB
001aac364
50 Ω
0.1 μF
S
Z
Y0
Y1
V
CC
0.5V
CC
GND
C
L
R
L
switch
switch
1
12
2
V
IH
V
IL
S
f
i
V
IL
or V
IH
Adjust fi voltage to obtain 0 dBm level at input.
Fig 21. Test circuit for measuring is ol ati on (OFF-state)
dB
001aac365
50 Ω
0.1 μF
S
Z
Y0
Y1
V
CC
0.5V
CC
GND
CL
RL
0.5V
CC
RL
switch
switch
1
12
2
V
IL
V
IH
S
fi
V
IL
or V
IH
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Product data sheet Rev. 4 — 6 December 2011 15 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
a. Test circuit
b. Input and output pulse definitions
Qinj =VO CL.
VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 22. Test circuit for measuring charge injection
001aac366
S
Z
Y0
Y1
RL
VICL
V
CC
GND
Rgen
Vgen
switch
1
2
V
O
G
001aac478
ΔVO
offonoff
logic
input
VO
(S)
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Product data sheet Rev. 4 — 6 December 2011 16 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
12. Package outline
Fig 23. Package outline SOT363 (SC-88)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT363 SC-88
wBM
bp
D
e1
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
456
Plastic surface-mounted package; 6 leads SOT363
UNIT A1
max bpcDEe1HELpQywv
mm 0.1 0.30
0.20 2.2
1.8
0.25
0.10 1.35
1.15 0.65
e
1.3 2.2
2.0 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.25
0.15
A
1.1
0.8
04-11-08
06-03-16
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 17 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
Fig 24. Package outline SOT457 (SC-74)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT457 SC-74
wBM
bp
D
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
scale
c
X
132
4
56
0 1 2 mm
Plastic surface-mounted package (TSOP6); 6 leads SOT457
UNIT A1bpcDEHELpQywv
mm 0.1
0.013 0.40
0.25 3.1
2.7
0.26
0.10 1.7
1.3
e
0.95 3.0
2.5 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2 0.33
0.23
A
1.1
0.9
05-11-07
06-03-16
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 18 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
Fig 25. Package outline SOT886 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT886 MO-252
SOT886
04-07-15
04-07-22
DIMENSIONS (mm are the original dimensions)
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17 1.5
1.4 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
6
2
5
3
4
6×
(2)
4×
(2)
A
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 19 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
Fig 26. Package outline SOT891 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT891
SOT891
05-04-06
07-05-15
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm 0.20
0.12 1.05
0.95 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.350.55
A
max
0.5 0.04
1
6
2
5
3
4
A
6×
(1)
4×
(1)
Note
1. Can be visible in some manufacturing processes.
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 20 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
Fig 27. Package outline SOT1115 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1115
sot1115_po
10-04-02
10-04-07
Unit
mm max
nom
min
0.35 0.04 0.95
0.90
0.85
1.05
1.00
0.95 0.55 0.3 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
L1
b
321
6 5 4
(6×)(2) A1A
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 21 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
Fig 28. Package outline SOT1202 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1202
sot1202_po
10-04-02
10-04-06
Unit
mm max
nom
min
0.35 0.04 1.05
1.00
0.95
1.05
1.00
0.95 0.55 0.35 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
b
123
L1
6 5 4
(6×)(2)
A
A1
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 22 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
13. Abbreviations
14. Revision history
Table 13. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
TTL Tr ansistor-Trans istor Logic
HBM Human Body Model
ESD ElectroStatic Discharge
MM Machine Mo del
DUT Device Under Test
Table 14. Revision history
Document ID Release date Dat a sheet status Change notice Supersedes
74LVC1 G3157 v.4 20111206 Product data sheet - 74LVC1G3157 v.3
Modifications: Legal pages updated.
Figure 17: Graphic b replaced.
74LVC1 G3157 v.3 2010 0916 Product data sheet - 74LVC1G3157 v.2
74LVC1 G3157 v.2 2007 0918 Product data sheet - 74LVC1G3157 v.1
74LVC1 G3157 v.1 2005 0207 Product data sheet - -
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 23 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full informatio n see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsisten cy or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio nThe information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property right s.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Develop ment This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 6 December 2011 24 of 25
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applicati ons.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC1G3157
2-channel analog multiplexer/demultiplexer
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 December 2011
Document identifie r : 74LVC1G3157
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
10.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
10.3 ON resistance test circuit and graphs. . . . . . . . 8
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
11.1 Waveforms and test circuits . . . . . . . . . . . . . . 11
11.2 Additional dynamic characteristics . . . . . . . . . 13
11.3 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
16 Contact information. . . . . . . . . . . . . . . . . . . . . 24
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25