Audio Dual Matched PNP Transistor SSM2220 Data Sheet PIN CONNECTION DIAGRAM Low voltage noise at 100 Hz, 1 nV/Hz maximum High gain bandwidth: 190 MHz typical Gain at IC = 1 mA, 165 typical Tight gain matching: 3% maximum Outstanding logarithmic conformance: rBE = 0.3 typical Low offset voltage: 200 V maximum APPLICATIONS SSM2220 TOP VIEW (Not to Scale) C1 1 8 C2 B1 2 7 B2 E1 3 6 E2 NC 4 5 NC NOTES 1. NC = NO CONNECT. THIS PIN IS NOT CONNECTED INTERNALLY. Microphone preamplifiers Tape head preamplifiers Current sources and mirrors Low noise precision instrumentation Voltage controlled amplifiers/multipliers 03096-001 FEATURES Figure 1. GENERAL DESCRIPTION The SSM2220 is a dual, low noise, matched PNP transistor, which has been optimized for use in audio applications. The ultralow input voltage noise of the SSM2220 is typically only 0.7 nV/Hz over the entire audio bandwidth of 20 Hz to 20 kHz. The low noise, high bandwidth (190 MHz), and offset voltage of (200 V maximum) make the SSM2220 an ideal choice for demand ing, low noise preamplifier applications. The SSM2220 also offers excellent matching of the current gain (hFE) to about 0.5%, which helps to reduce the high order amplifier harmonic distortion. In addition, to ensure the long-term stability of the matching parameters, internal protection diodes Rev. C across the base to emitter junction were used to clamp any reverse base to emitter junction potential. This prevents a base to emitter breakdown condition, which can result in degradation of gain and matching performance due to excessive breakdown current. Another feature of the SSM2220 is its very low bulk resistance of 0.3 typical, which assures accurate logarithmic conformance. The SSM2220 is offered in 8-lead plastic dual inline (PDIP) and 8-lead standard small outline (SOIC), and its performance and characteristics are guaranteed over the extended industrial temperature range of -40C to +85C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com SSM2220 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................5 Applications ....................................................................................... 1 Applications Information .................................................................8 Pin Connection Diagram ................................................................ 1 Super Low Noise Amplifier ..........................................................8 General Description ......................................................................... 1 Low Noise Microphone Preamplifier .........................................9 Specifications..................................................................................... 3 Noise Measurement ................................................................... 10 Electrical Characteristics ............................................................. 3 Current Sources .......................................................................... 10 Absolute Maximum Ratings............................................................ 4 Outline Dimensions ....................................................................... 12 Thermal Resistance ...................................................................... 4 Ordering Guide .......................................................................... 12 ESD Caution .................................................................................. 4 REVISION HISTORY 4/13--Rev. B to Rev. C Updated Format .................................................................. Universal Changes to Features Section and Figure 1..................................... 1 Change to Endnote 2 and Endnote 4, Table 1............................... 3 Changed Breakdown Voltage Parameter, Table 2 to Breakdown Voltage (Collector to Emitter), Table 2 ................ 3 Changes to Table 3 ............................................................................ 4 Changes to Figure 8 Caption, Figure 9 Caption, and Figure 12 ..................................................................................... 6 Change to Figure 15 ......................................................................... 7 Changes to Super Low Noise Amplifier Section, Figure 16, and Figure 17 Caption ............................................................................. 8 Change to Figure 18 ......................................................................... 9 Changes to Figure 19 and Noise Measurement Section ............ 10 Changes to Current Sources and Current Matching Sections .......................................................................... 11 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 11/03--Rev. A to Rev. B Changes to Ordering Guide .............................................................1 Updated Outline Dimensions ..........................................................9 Rev. C | Page 2 of 12 Data Sheet SSM2220 SPECIFICATIONS TA = 25C, unless otherwise noted. Table 1. Parameter CURRENT GAIN 1 Current Gain Matching 2 NOISE VOLTAGE DENSITY 3 OFFSET VOLTAGE 4 Offset Voltage Change vs. Collector Voltage Offset Voltage Change vs. Collector Current OFFSET CURRENT COLLECTOR TO BASE LEAKAGE CURRENT BULK RESISTANCE COLLECTOR SATURATION VOLTAGE 1 2 Symbol hFE Min Typ Max Unit 80 70 60 165 150 120 0.5 6 % 0.8 0.7 0.7 0.7 40 11 12 6 50 0.3 0.026 2 1 1 1 200 200 75 45 400 0.75 0.1 nV/Hz nV/Hz nV/Hz nV/Hz V V V nA pA V hFE en VOS VOS/VCB VOS/IC IOS ICBO rBE VCE(SAT) Test Conditions/Comments VCB = 0 V to 36 V IC = 1 mA IC = 100 A IC = 10 A IC = 100 A, VCB = 0 V IC = 1 mA, VCB = 0 V fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz VCB = 0 V, IC = 100 A IC = 100 A, VCB1 = 0 V, VCB2 = -36 V VCB = 0 V, IC1 = 10 A, IC2 = 1 mA IC = 100 A, VCB = 0 V VCB = -36 V = VMAX VCB = 0 V, 10 A IC 1 mA IC = 1 mA, IB = 100 A Current gain is measured at collector to base voltages (VCB) swept from 0 V to VMAX at indicated collector current. Typicals are measured at VCB = 0 V. Current gain matching (hFE) is defined as follows: hFE = 100(I B )(h FE ) min IC Sample tested. Noise tested and specified as equivalent input voltage for each transistor. Offset voltage is defined as follows: VOS = VBE1 - VBE2 = KT ln I C1 q I C2 where VOS is the differential voltage for IC1 = IC2. 3 4 ELECTRICAL CHARACTERISTICS -40C TA +85C, unless otherwise noted. Table 2. Parameter CURRENT GAIN OFFSET VOLTAGE Offset Voltage Drift 1 OFFSET CURRENT BREAKDOWN VOLTAGE (COLLECTOR TO EMITTER) 1 Symbol hFE VOS TCVOS IOS BVCEO Min Typ Max Unit 60 50 40 125 105 90 30 0.3 10 265 1.0 200 V V/C nA V 36 Guaranteed by VOS test (TCVOS = VOS/T for VOS << VBE), where T = 298K for TA = 25C. Rev. C | Page 3 of 12 Test Conditions/Comments VCB = 0 V to 36 V IC = 1 mA IC = 100 A IC = 10 A IC = 100 A, VCB = 0 V IC = 100 A, VCB = 0 V IC = 100 A, VCB = 0 V SSM2220 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Breakdown Voltage of Collector to Base Voltage (BVCBO) Collector to Emitter Voltage (BVCEO) Collector to Collector Voltage (BVCC) Emitter to Emitter Voltage (BVEE) Current Collector (IC) Emitter (IE) Temperature Range Operating Storage Junction Lead Temperature (Soldering, 60 sec) Rating Table 4. Package Type 8-Lead PDIP 8-Lead SOIC 36 V 36 V 36 V 36 V 1 JC 43 43 Unit C/W C/W JA is specified for worst-case mounting conditions; that is, JA is specified for a device in a socket for the PDIP package, and a device soldered to a printed circuit board for SOIC packages. 20 mA 20 mA ESD CAUTION -40C to +85C -65C to +150C -65C to +150C +300C JA1 103 158 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 4 of 12 Data Sheet SSM2220 TYPICAL PERFORMANCE CHARACTERISTICS 250 VCE = 5V IC = 1mA TA = 25C TA = 25C VCB = 0V 1s RS RS 200 TOTAL NOISE (nV Hz) f = 1kHz 40nV 0V -40nV 150 RS = 100k 100 50 RS = 1k 0 100 10 1 1000 COLLECTOR CURRENT (A) Figure 2. Low Frequency Noise 14 Figure 5. Total Noise vs. Collector Current 6 VCE = 5V f = 1kHz NOISE VOLTAGE DENSITY (nV Hz) 12 RS = 1k NOISE FIGURE (dB) 03096-005 20mV RS = 10k 03096-002 VERTICAL = 40nV/DIV HORIZONTAL = 1s/DIV 10 8 RS = 100k 6 4 RS = 10k 2 TA = 25C VCB = 0V 5 4 10Hz 3 2 1 1 03096-003 0.1 0.01 COLLECTOR CURRENT (mA) 0 0 1k TA = 25C VCB = 0V 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 12 TA = 25C VCB = 0V 100 10 IC = 10A IC = 100A 1 IC = 1mA -0.5 10-8 10-7 10-6 10-5 10-4 COLLECTOR CURRENT (A) 10-3 0.1 0.1 1 10 100 1k 10k FREQUENCY (Hz) Figure 4. Emitter to Base Log Conformity Figure 7. Noise Voltage Density vs. Frequency Rev. C | Page 5 of 12 100k 03096-007 -0.4 03096-004 LOGGING ERROR (mV) 9 Figure 6. Noise Voltage Density vs. Collector Current NOISE VOLTAGE DENSITY (nV Hz) 0.4 6 COLLECTOR CURRENT (mA) Figure 3. Noise Figure vs. Collector Current 0.5 3 03096-006 100Hz 0 0.001 SSM2220 300 Data Sheet 10 VCB = 0V SATURATION VOLTAGE (V) 250 +25C 150 -55C 100 1 +125C +25C 0.1 50 1000 COLLECTOR CURRENT (A) 0.01 0.01 Figure 8. Current Gain (hFE) vs. Collector Current 0.70 CURRENT GAIN (hFE) 600 500 VCB = -36V 400 300 200 VCB = 0V -15 25 5 45 65 85 105 125 TEMPERATURE (C) 0.65 0.60 0.55 0.50 0.45 0.40 0.35 03096-009 100 -35 100 1000 10000 COLLECTOR CURRENT (A) Figure 12. Base to Emitter Voltage (VBE) vs. Collector Current 50 TA = 25C VCB = 0V TA = 25C 40 CAPACITANCE (pF) 100 10 30 20 1 10 0.1 0.001 0.01 0.1 1 10 COLLECTOR CURRENT (mA) 100 0 03096-010 fT - UNITY-GAIN BANDWIDTH PRODUCT (MHz) 10 1 Figure 9. Current Gain (hFE) vs. Temperature 1k 10 TA = 25C IC = 1mA 0 -55 1 Figure 11. Saturation Voltage vs. Collector Current BASE TO EMITTER VOLTAGE, VBE (V) 700 0.1 COLLECTOR CURRENT (mA) 03096-012 100 03096-008 0 10 03096-011 -55C 0 -5 -10 -15 -20 -25 -30 COLLECTOR-BASE VOLTAGE (V) Figure 13. Collector to Base Capacitance vs. VCB Figure 10. Gain Bandwidth vs. Collector Current Rev. C | Page 6 of 12 -35 03096-013 CURRENT GAIN (hFE) +125C 200 Data Sheet SSM2220 100 TA = 25C TA = 25C OUTPUT CONDUCTANCE, hoe (m) 100k 1k 1 10 100 1000 COLLECTOR CURRENT (A) Figure 14. Small Signal Input Resistance (hie) vs. Collector Current 03096-014 10k 10 1 0.1 0.01 1 10 100 COLLECTOR CURRENT (A) 1000 03096-015 hie - SMALL-SIGNAL INPUT RESISTANCE () 1M Figure 15. Small Signal Output Conductance (hoe) vs. Collector Current Rev. C | Page 7 of 12 SSM2220 Data Sheet APPLICATIONS INFORMATION PULSE RESPONSE -15V + 10F 0.001F AV = 10 CF = 30pF +15V 1.5k 0.01% 0.01F 1.5k 0.01% 7 2 AD8671 6 VOUT 3 4 0.01F 150 Q5 Q3 0.01F Q2 Q1 Q4 5V Q6 20s -15V + - LOW FREQUENCY NOISE SSM2220 PAIRS: Q1 - Q2 Q3 - Q4 Q5 - Q6 -15V 27k AV = 1000 VERT = 1nV/DIV Q7 RED LED 83 + 10F 0.001F 03096-016 +15V Figure 16. Super Low Noise Amplifier SUPER LOW NOISE AMPLIFIER This amplifier exhibits excellent full power ac performance, 0.08% THD into a 600 load, making it suitable for exacting audio applications (see Figure 17). 600 LOAD 0.01 NO LOAD 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 03096-017 The circuit in Figure 16 is a super low noise amplifier, with equivalent input voltage noise of 0.32 nV/Hz. By paralleling SSM2220 matched pairs, a reduction of the base spreading resistance by a factor of 3 results in a further reduction of amplifier noise by a factor of 3. Additionally, the shot noise contribution is reduced by maintaining a high collector current (2 mA/device), which reduces the dynamic emitter resistance and decreases voltage noise. The voltage noise is inversely proportional to the square root of the stage current, whereas current noise increases proportionally. Accordingly, this amplifier capitalizes on voltage noise reduction techniques at the expense of increasing the current noise. However, high current noise is not usually important when dealing with low impedance sources. TOTAL HARMONIC DISTORTION (%) 0.1 Figure 17. Total Harmonic Distortion vs. Frequency of Circuit in Figure 16 Rev. C | Page 8 of 12 Data Sheet SSM2220 0.01F +15V R1 250 LED 10F + Q2 2N29007A 3 VIN 2 6 1 R6 100 7 Q1 SSM2220 R5 100 8 8 2 AD8671 1 C1 50pF VOUT 3 R2 27k R3 5k R4 5k 10F + 0.01F THD < 0.005% 20Hz TO 20kHz 0.5nV/ Hz 1/f CORNER < 1Hz -15V 03096-018 4 Figure 18. Low Noise Microphone Preamplifier LOW NOISE MICROPHONE PREAMPLIFIER Figure 18 shows a microphone preamplifier that consists of an SSM2220 and a low noise op amp. The input stage operates at a relatively high quiescent current of 2 mA per side, which reduces the SSM2220 transistor voltage noise. The 1/f corner is less than 1 Hz. Total harmonic distortion is under 0.005% for a 10 V p-p signal from 20 Hz to 20 kHz. The preamp gain is 100, but can be modified by varying R5 or R6 (VOUT/VIN = R5/R6 + 1). A total input stage emitter current of 4 mA is provided by Q2. The constant current in Q2 is set by using the forward voltage of a GaAsP LED as a reference. The difference between this voltage and the VBE of a silicon transistor is predictable and constant (to a few percent) over a wide temperature range. The voltage difference, approximately 1 V, is dropped across the 250 resistor, which produces a temperature stabilized emitter current. Rev. C | Page 9 of 12 SSM2220 Data Sheet +5V + 0.1F 10F 3 SSM2220 6 2 7 1 8 3 SSM2220 6 2 7 1 8 +15V 2mA ADJUST POT FOR 2mA (2V ACROSS 1k RES) 1k 500 3 2 0.01F 6 7 SSM2220 DUT 1 8 +15V 0.01F 2 2.2pF 7 AD8671 6 3 5k 1% 5k 1% 5k 10F 4 7 3 1k 10 0.01F en 6 AD8671 SPOT NOISE FOR EACH TRANSISTOR = 2 4 en 10,000 x 2 10k -15V 0.1F 0.01F 100 -15V 03096-019 + -15V Figure 19. Voltage Noise Measurement Circuit NOISE MEASUREMENT +V All resistive components and semiconductor junctions contribute to the system input noise. Resistive components produce Johnson noise (en2 = 4kTBR, or en = 0.13R nV/Hz, where R is in k). At semiconductor junctions, shot noise is caused by current flowing through a junction, producing voltage noise in series impedances such as transistor collector load resistors (In = 0.556I pA/Hz, where I is in A). The noise contribution of the AD8671 gain stages is also negligible, due to the gain in the signal path. The op amp stages amplify the input referred noise of the transistors, increasing the signal strength to allow the noise spectral density, (e n )input x 10,000, to be measured with a spectrum analyzer. Because equal noise contributions from each transistor in the SSM2220 are assumed, the output is divided by 2 to determine the input noise of a single transistor. Air currents cause small temperature changes that can appear as low frequency noise. To eliminate this noise source, the measurement circuit must be thermally isolated. Effects of extraneous noise sources must also be eliminated by totally shielding the circuit. Q3 SSM2220 Q1 Q2 IOUT = I R +V - 2VBE I= R 03096-020 Figure 19 illustrates a technique for measuring the equivalent input noise voltage of the SSM2220. A stage current of 1 mA is used to bias each side of the differential pair. The 5 k collector resistors noise contribution is insignificant compared to the voltage noise of the SSM2220. Because noise in the signal path is referred back to the input, this voltage noise is attenuated by the gain of the circuit. Consequently, the noise contribution of the collector load resistors is only 0.048 nV/Hz. This is considerably less than the typical 0.8 nV/Hz input noise voltage of the SSM2220 transistor. SSM2220 Q4 Figure 20. Cascode Current Source CURRENT SOURCES A fundamental requirement for accurate current mirrors and active load stages is matched transistor components. Due to the excellent VBE matching (the voltage difference between one VBE and another, which is required to equalize collector current) and gain matching, the SSM2220 can be used to implement a variety of standard current mirrors that can source current into a load such as an amplifier stage. The advantages of current loads in amplifiers vs. resistors are an increase of voltage gain due to higher impedances, larger signal range, and in many applications, a wider signal bandwidth. Figure 20 illustrates a cascode current mirror consisting of two SSM2220 transistor pairs. The cascode current source has a common base transistor in series with the output, which causes an increase in output impedance of the current source because VCE stays relatively constant. High frequency characteristics are improved due to a reduction of Miller capacitance. The small signal output impedance can be determined Rev. C | Page 10 of 12 Data Sheet SSM2220 by consulting Figure 15. Typical output impedance levels approach the performance of a perfect current source. (ro)Q3 = If the resistors and transistors are equal and the collector voltages are the same, then the collector currents match precisely. Investigating the current matching errors resulting from a nonzero VOS, IC is defined as the current error between the two transistors. 1 = 1 M 1.0 Mho Figure 22 describes the relationship of current matching errors vs. offset voltage for a specified average current, IC. Note that because the relative error between the currents is exponentially proportional to the offset voltage, tight matching is required to design high accuracy current sources. For example, if the offset voltage were 5 mV at 100 A collector current, the current matching error would be 20%. Additionally, temperature effects, such as offset drift (3 V/C per mV of VOS), degrade performance if Q1 and Q2 are not well matched. Q2 and Q3 are in series and operate at the same current level; therefore, the total output impedance is as follows: RO = hFE x (ro)Q3 (160)(1 M) = 160 M Current Matching The objective of current source or mirror design is generation of currents that either are matched or must maintain a constant ratio. However, mismatch of base emitter voltages causes output current errors. Consider the example of Figure 21. IC + IC 2 IC - IC 2 A CLOSELY MATCHED TRANSISTOR PAIR - VB R2 03096-021 R1 R1 = R2 = R Figure 21. Current Matching Circuit 1.2 IC = 10A IC = 100A 1.0 0.8 SSM2220 V OS PERFORMANCE 0.6 0.4 R = 3k hFE = 200 0.2 IC = IC = 1mA 0 0.001 0.01 0.1 1 I = IC1 - IC2 10 VOS (mV) Figure 22. Current Matching Accuracy vs. Offset Voltage Rev. C | Page 11 of 12 IC1 + IC2 2 03096-022 IC % IC + SSM2220 Data Sheet OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070606-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 23. 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 24. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 SSM2220PZ SSM2220S SSM2220SZ SSM2220SZ-REEL 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Z = RoHS Compliant Part. (c)2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03096-0-4/13(C) Rev. C | Page 12 of 12 Package Option N-8 R-8 R-8 R-8