© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 15
1Publication Order Number:
MC74VHC1GT66/D
MC74VHC1GT66
SPST (NO) Normally Open
Analog Switch
The MC74VHC1GT66 is a Single Pole Single Throw (SPST)
analog switch. It achieves high speed propagation delays and low ON
resistances while maintaining low power dissipation. This bilateral
switch controls analog and digital voltages that may vary across the
full power−supply range (from VCC to GND).
The MC74VHC1GT66 is compatible in function to a single gate of
the High Speed CMOS MC74VHCT4066 and the metal−gate CMOS
MC14066. The device has been designed so that the ON resistances
(RON) are much lower and more linear over input voltage than RON of
the metal−gate CMOS or High Speed CMOS analog switches.
The ON/OFF Control input is compatible with TTL−type input
thresholds allowing the device to be used as a logic−level translator
from 3 V CMOS logic to 5 V CMOS logic or from 1.8 V CMOS logic
to 3 V CMOS logic while operating at the high−voltage power supply.
The input protection circuitry on this device allows overvoltage
tolerance on the input, which provides protection when voltages of up
to 7 V are applied, regardless of the supply voltage. This allows the
MC74VHC1GT66 to be used to interface 5 V circuits to 3 V circuits.
Features
•High Speed: tPD = 20 ns (Typ) at VCC = 5 V
•Low Power Dissipation: ICC = 1.0 mA (Max) at TA = 25°C
•Diode Protection Provided on Inputs and Outputs
•Improved Linearity and Lower ON Resistance over Input Voltage
•On/Off Control Input Has OVT
•Chip Complexity: FETs = 11; Equivalent Gates = 3
•Pb−Free Packages are Available
PIN ASSIGNMENT
1
2
3 GND
IN/OUT XA
OUT/IN YA
4
5V
CC
ON/OFF CONTROL
FUNCTION TABLE
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
L
H
On/Off Control Input State of Analog Switch
Off
On
MARKING
DIAGRAMS
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SC−88A
DF SUFFIX
CASE 419A
TSOP−5
DT SUFFIX
CASE 483
1
5
1
5
1
5
VE MG
G
VE = Device Code
M = Date Code*
W = Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
1
5
VE MG
G
M
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2
VCC
IN/OUT XA
OUT/IN YA
ON/OFF
CONTROL
GND
Figure 1. Pinout Diagram
ON/OFF CONTROL
OUT/IN YA
1
U U
IN/OUT XA1
X 1
Figure 2. Logic Symbol
1
2
34
5
(SC−88A, TSOP−5)
MAXIMUM RATINGS
Symbol Characteristics Value Unit
VCC DC Supply Voltage −0.5 to +7.0 V
VIN DC Input Voltage −0.5 to +7.0 V
VIS Analog Output Voltage −0.5 to 7.0 V
IIK Input Diode Current −20 mA
ICC DC Supply Current, VCC and GND +25 mA
TSTG Storage Temperature Range *65 to )150 °C
TLLead Temperature, 1 mm from Case for 10 Seconds 260 °C
TJJunction Temperature Under Bias )150 °C
qJA Thermal Resistance SC70−5 (Note 1)
SOT23−5
350
230
°C/W
PDPower Dissipation in Still Air at 85°CSC70−5
SOT23−5
150
200
mW
MSL Moisture Sensitivity Level 1
FRFlammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
VESD ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
N/A
V
ILatchup Latchup Performance Above VCC and Below GND at 125°C (Note 5) $500 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
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RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
VCC DC Supply Voltage 2.0 5.5 V
VIN Digital Input Voltage GND 5.5 V
VIS Analog Input Voltage GND VCC V
TAOperating Temperature Range −55 +125 °C
tr , tfInput Rise and Fall Time VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
0
0
100
20
ns/V
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °CTime, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100 1000
TIME, YEARS
NORMALIZED FAILURE RATE
TJ= 130 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time Junction Temperature
TJ=120 C°
TJ=110 C°
TJ=100 C°
TJ= 90 C°
TJ= 80 C°
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DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
VCC
(V)
TA = 25°C TA ≤ 85°C−55°C ≤ TA ≤ 125°C
Unit
Min Max Min Max Min Max
VIH Minimum High−Level
Input Voltage
ON/OFF Control Input
RON = Per Spec
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
VIL Maximum Low−Level
Input Voltage
ON/OFF Control Input
RON = Per Spec
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
IIN Maximum Input
Leakage Current
ON/OFF Control Input
VIN = VCC or GND 0 to
5.5
±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent
Supply Current
VIN = VCC or GND
VIO = 0 V
5.5 1.0 20 40 mA
ICCT Quiescent
Supply Current
ON/OFF Control at
3.4 V
5.5 1.35 1.5 1.65 mA
RON Maximum ”ON”
Resistance
VIN = VIH
VIS = VCC or GND
|IIS| ≤ 10 mA (Figure 4)
3.0
4.5
5.5
60
45
40
70
50
45
100
60
55
W
IOFF Maximum Off−Channel
Leakage Current
VIN = VIL
VIS = VCC or GND
Switch Off (Figure 5)
5.5 0.1 0.5 1.0 mA
AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr/tf = 3.0 ns
Symbol Parameter Test Conditions
VCC
(V)
TA = 25°C TA ≤ 85°C−55°C ≤ TA ≤ 125°C
Unit
Min Typ Max Min Max Min Max
tPLH,
tPHL
Maximum Propagation
Delay, Input X to Y
YA = Open
(Figures 7, 14)
2.0
3.0
4.5
5.5
1
0.6
0.6
0.6
5
2
1
1
6
3
1
1
7
4
2
1
ns
tPLZ,
tPHZ
Maximum Propagation
Delay, ON/OFF Control
to Analog Output
RL = 1000 W
(Figures 8, 15)
2.0
3.0
4.5
5.5
32
28
24
20
40
35
30
25
45
40
35
30
50
45
40
35
ns
tPZL,
tPZH
Maximum Propagation
Delay, ON/OFF Control
to Analog Output
RL = 1000 W
(Figures 8, 15)
2.0
3.0
4.5
5.5
32
28
24
20
40
35
30
25
45
40
35
30
50
45
40
35
ns
CIN Maximum Input
Capacitance
ON/OFF Control Input 0.0 3 10 10 10 pF
Control Input = GND
Analog I/O
Feedthrough
5.0
4
4
10
10
10
10
10
10
CPD Power Dissipation Capacitance (Note 6)
Typical @ 25°C, VCC = 5.0 V
pF
18
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol Parameter Test Conditions VCC Limit 25°C Unit
BW Maximum On−Channel Bandwidth
or Minimum Frequency Response
(Figure 10)
fin = 1 MHz Sine Wave
Adjust fin voltage to obtain 0 dBm at VOS
Increase fin = frequency until dB meter reads −3 dB
RL = 50 W
3.0
4.5
5.5
150
175
180
MHz
ISOoff Off−Channel Feedthrough Isolation
(Figure 11)
fin = Sine Wave
Adjust fin voltage to obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 W
3.0
4.5
5.5
−80
−80
−80
dB
NOISEfeed Feedthrough Noise Control to
Switch
(Figure 12)
Vin ≤ 1 MHz Square Wave (tr = tf = 2ns)
RL = 600 W
3.0
4.5
5.5
45
60
130
mVPP
THD Total Harmonic Distortion
(Figure 13)
fin = 1 kHz, RL = 10 kW
THD = THDMeasured − THDSource
VIS = 3.0 VPP sine wave
VIS = 5.0 VPP sine wave
3.3
5.5
0.30
0.15
%
Figure 4. On Resistance Test Set−Up Figure 5. Maximum Off−Channel Leakage Current
Test Set−Up
51
2
43
Figure 6. Maximum On−Channel Leakage Current
Test Set−Up
Figure 7. Propagation Delay Test Set−Up
POWER
SUPPLY COMPUTER
DC PARAMETER
ANALYZER
VCC
+−
PLOTTER
51
2
43
VCC
VIL
VCC
VCC A
51
2
43
VCC
VIH
VCC
A
N/C
51
2
43
VCC
VIH
TEST
POINT
VIH
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6
Figure 8. Propagation Delay Output Enable/Disable
Test Set−Up
Figure 9. Power Dissipation Capacitance
Test Set−Up
51
2
43
VCC
VCC
VCC
2
1
2
1
RL
CL*
*Includes all probe and jig capacitance.
51
2
43
VCC
N/C
N/C
TEST POINT
Switch to Position 2 when testing tPLZ and tPZL
Switch to Position 1 when testing tPHZ and tPZH
A
Figure 10. Maximum On−Channel Bandwidth
Test Set−Up
Figure 11. Off−Channel Feedthrough Isolation
Test Set−Up
Figure 12. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set−Up
Figure 13. Total Harmonic Distortion Test Set−Up
51
2
43
VCC
*Includes all probe and jig capacitance.
dB
Meter
0.1 mF
VOS
fin 51
2
43
VCC
*Includes all probe and jig capacitance.
dB
Meter
0.1 mF
VOS
fin
RL
VIS
51
2
43
VCC
*Includes all probe and jig capacitance.
VOS
(VCC)/2
IS
RL
RL
GND
VIH
VIN v1MHz
tr+tf+2ns
51
2
43
VCC
*Includes all probe and jig capacitance.
0.1 mF
VIS
fin
VOS
To Distortion
Meter
(VCC)/2
RL
VIH
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7
VCC
VOH
1.5 V
50% VCC
XA
YA
tPHL
tPLH
Figure 14. Propagation Delay, Analog In to Analog Out Waveforms
Figure 15. Propagation Delay, ON/OFF Control
1.5 V
VOL
VIH
10%
50% VCC
Control
Analog Out
tPLZ
tPZL
50% VCC
1.5 V
tPHZ
tPZH
VOL
VOH
High
Impedance
High
Impedance
90%
trtf
90%
10%
ORDERING INFORMATION
Device Package Shipping†
M74VHC1GT66DFT1G SC−88A
(Pb−Free)
3000 / Tape & Reel
MC74VHC1GT66DFT2 SC−88A
M74VHC1GT66DFT2G SC−88A
(Pb−Free)
MC74VHC1GT66DTT1 TSOP−5
M74VHC1GT66DTT1G TSOP−5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
DIM
A
MIN MAX MIN MAX
MILLIMETERS
1.80 2.200.071 0.087
INCHES
B1.15 1.350.045 0.053
C0.80 1.100.031 0.043
D0.10 0.300.004 0.012
G0.65 BSC0.026 BSC
H--- 0.10---0.004
J0.10 0.250.004 0.010
K0.10 0.300.004 0.012
N0.20 REF0.008 REF
S2.00 2.200.079 0.087
B0.2 (0.008) MM
12 3
45
A
G
S
D 5 PL
H
C
N
J
K
−B−
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE K
ǒmm
inchesǓ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.65
0.025
0.65
0.025
0.50
0.0197
0.40
0.0157
1.9
0.0748
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9
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
DIM MIN MAX
MILLIMETERS
A3.00 BSC
B1.50 BSC
C0.90 1.10
D0.25 0.50
G0.95 BSC
H0.01 0.10
J0.10 0.26
K0.20 0.60
L1.25 1.55
M0 10
S2.50 3.00
123
54 S
A
G
L
B
D
H
C
J
__
0.7
0.028
1.0
0.039
ǒmm
inchesǓ
SCALE 10:1
0.95
0.037
2.4
0.094
1.9
0.074
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.20
5X
CAB
T0.10
2X
2X T0.20
NOTE 5
T
SEATING
PLANE
0.05
K
M
DETAIL Z
DETAIL Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
MC74VHC1GT66/D
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