CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
36-Mbit DDR II SRAM 2-Word
Burst Architecture
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-57827 Rev. *B Revised February 25, 2011
36-Mbit DDR II SRAM 2-Word Burst Architecture
Features
■36-Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)
■333 MHz clock for high bandwidth
■2-word burst for reducing address bus frequency
■Double data rate (DDR) interfaces
(data transferred at 666 MHz) at 333 MHz
■Two input clocks (K and K) for precise DDR timing
❐SRAM uses rising edges only
■Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■Synchronous internally self-timed writes
■DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
■Operates similar to DDR-I device with 1 cycle read latency
when DOFF is asserted LOW
■1.8 V core power supply with HSTL inputs and outputs
■Variable drive HSTL output buffers
■Expanded HSTL output voltage (1.4 V to VDD)
❐Supports both 1.5 V and 1.8 V IO supply
■Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■Offered in both Pb-free and non Pb-free packages
■JTAG 1149.1 compatible test access port
■Phase locked loop (PLL) for accurate data placement
Configurations
CY7C1416KV18 – 4 M × 8
CY7C1427KV18 – 4 M × 9
CY7C1418KV18 – 2 M × 18
CY7C1420KV18 – 1 M × 36
Functional Description
The CY7C1416KV18, CY7C1427KV18, CY7C1418KV18, and
CY7C1420KV18 are 1.8 V synchronous pipelined SRAM
equipped with DDR II architecture. The DDR II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1416KV18
and two 9-bit words in the case of CY7C1427KV18 that burst
sequentially into or out of the device. The burst counter always
starts with a “0” internally in the case of CY7C1416KV18 and
CY7C1427KV18. On CY7C1418KV18 and CY7C1420KV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1418KV18 and two 36-bit words in the case of
CY7C1420KV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit
Maximum operating frequency 333 300 250 200 167 MHz
Maximum operating current × 8 480 450 420 370 340 mA
× 9 480 450 420 370 340
× 18 490 460 430 380 340
× 36 600 560 490 430 380
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 2 of 32
Logic Block Diagram (CY7C1416KV18)
Logic Block Diagram (CY7C1427KV18)
Write
Reg
Write
Reg
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
8
16
8
NWS[1:0]
VREF
Write Add. Decode
8
21
C
C
8
LD
Control
R/W
DOFF
2M x 8 Array
2M x 8 Array
8
DQ[7:0]
8
CQ
CQ
Write
Reg
Write
Reg
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
9
18
9
BWS[0]
VREF
Write Add. Decode
9
21
C
C
9
LD
Control
R/W
DOFF
2M x 9 Array
2M x 9 Array
9
DQ[8:0]
9
CQ
CQ
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 3 of 32
Logic Block Diagram (CY7C1418KV18)
Logic Block Diagram (CY7C1420KV18)
Write
Reg
Write
Reg
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
18
36
18
BWS[1:0]
VREF
Write Add. Decode
18
21
C
C
18
LD
Control
Burst
Logic
A0
A(20:1)
R/W
DOFF
1M x 18 Array
1M x 18 Array
20
18
DQ[17:0]
18
CQ
CQ
Write
Reg
Write
Reg
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
36
72
36
BWS[3:0]
VREF
Write Add. Decode
36
20
C
C
36
LD
Control
Burst
Logic
A0
A(19:1)
R/W
DOFF
512K x 36 Array
512K x 36 Array
19
36
DQ[35:0]
36
CQ
CQ
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 4 of 32
Contents
Pin Configuration ............................................................. 5
165-ball FBGA (13 × 15 × 1.4 mm) pinout ..................5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Read Operations .........................................................9
Write Operations .........................................................9
Byte Write Operations .................................................9
Single Clock Mode ...................................................... 9
DDR Operation ............................................................ 9
Depth Expansion .........................................................9
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
PLL ............................................................................10
Application Example ...................................................... 10
Truth Table ...................................................................... 11
Burst Address Table
(CY7C1418KV18, CY7C1420KV18) ................................ 11
Write Cycle Descriptions ............................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port—Test Clock ................................... 13
Test Mode Select (TMS) ...........................................13
Test Data-In (TDI) ..................................................... 13
Test Data-Out (TDO) ................................................. 13
Performing a TAP Reset ........................................... 13
TAP Registers ...........................................................13
TAP Instruction Set ...................................................13
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Electrical Characteristics ...................................... 16
TAP AC Switching Characteristics ............................... 17
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Power Up Sequence in DDR II SRAM ........................... 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 23
Capacitance .................................................................... 24
Thermal Resistance ........................................................ 24
Switching Characteristics .............................................. 25
Switching Waveforms .................................................... 27
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagram ............................................................ 29
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC Solutions ......................................................... 32
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 5 of 32
Pin Configuration
The pin configurations for CY7C1416KV18, CY7C1427KV18, CY7C1418KV18, and CY7C1420KV18 follow.[1]
165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1416KV18 (4 M × 8)
12345678910 11
ACQ NC/72M A R/W NWS1KNC/144M LD AACQ
BNC NC NC A NC/288M K NWS0ANCNCDQ3
CNC NC NC VSS AAAV
SS NC NC NC
DNC NC NC VSS VSS VSS VSS VSS NC NC NC
ENC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2
FNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
GNC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC NC VDDQ VDD VSS VDD VDDQ NC DQ1 NC
KNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
LNC DQ6 NC VDDQ VSS VSS VSS VDDQ NC NC DQ0
MNC NC NC VSS VSS VSS VSS VSS NC NC NC
NNC NC NC VSS AAAV
SS NC NC NC
PNC NC DQ7 A A C A A NC NC NC
RTDOTCKAAACAAATMSTDI
CY7C1427KV18 (4 M × 9)
12345678910 11
ACQ NC/72M A R/W NC K NC/144M LD AACQ
BNC NC NC A NC/288M K BWS0ANCNCDQ3
CNC NC NC VSS AAAV
SS NC NC NC
DNC NC NC VSS VSS VSS VSS VSS NC NC NC
ENC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2
FNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
GNC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC NC VDDQ VDD VSS VDD VDDQ NC DQ1 NC
KNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
LNC DQ6 NC VDDQ VSS VSS VSS VDDQ NC NC DQ0
MNC NC NC VSS VSS VSS VSS VSS NC NC NC
NNC NC NC VSS AAAV
SS NC NC NC
PNC NC DQ7 A A C A A NC NC DQ8
RTDOTCKAAACAAATMSTDI
Note
1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 6 of 32
CY7C1418KV18 (2 M × 18)
12345678910 11
ACQ NC/72M A R/W BWS1KNC/144M LD AACQ
BNC DQ9 NC A NC/288M K BWS0ANCNCDQ8
CNC NC NC VSS AA0AV
SS NC DQ7 NC
DNC NC DQ10 VSS VSS VSS VSS VSS NC NC NC
ENC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6
FNC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5
GNC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC
KNC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3
LNC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2
MNC NC NC VSS VSS VSS VSS VSS NC DQ1 NC
NNC NC DQ16 VSS AAAV
SS NC NC NC
PNC NC DQ17 A A C A A NC NC DQ0
RTDOTCKAAACAAATMSTDI
CY7C1420KV18 (1 M × 36)
12345678910 11
ACQ NC/144M A R/W BWS2KBWS1LD ANC/72MCQ
BNC DQ27 DQ18 A BWS3KBWS
0ANCNCDQ8
CNC NC DQ28 VSS AA0AV
SS NC DQ17 DQ7
DNC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
ENC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6
FNC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5
GNC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4
KNC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3
LNC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2
MNC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1
NNC DQ35 DQ25 VSS AAAV
SS NC NC DQ10
PNC NC DQ26 A A C A A NC DQ9 DQ0
RTDOTCKAAACAAATMSTDI
Pin Configuration (continued)
The pin configurations for CY7C1416KV18, CY7C1427KV18, CY7C1418KV18, and CY7C1420KV18 follow.[1]
165-ball FBGA (13 × 15 × 1.4 mm) pinout
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 7 of 32
Pin Definitions
Pin Name I/O Pin Description
DQ[x:0] Input output-
synchronous
Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the C and C clocks during read operations or K and K when in single clock
mode. When read access is deselected, Q[x:0] are automatically tristated.
CY7C1416KV18 DQ[7:0]
CY7C1427KV18 DQ[8:0]
CY7C1418KV18 DQ[17:0]
CY7C1420KV18 DQ[35:0]
LD Input-
synchronous
Synchronous load. This input is brought LOW when a bus cycle sequence is defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data.
NWS0,
NWS1
Input-
synchronous
Nibble write select 0, 1 active LOW (CY7C1416KV18 only). Sampled on the rising edge of the K and
K clocks during write operations. Used to select which nibble is written into the device during the current
portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
Input-
synchronous
Byte write select 0, 1, 2, and 3 active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1427KV18 BWS0 controls D[8:0]
CY7C1418KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1420KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device.
A, A0 Input-
synchronous
Address inputs. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4 M × 8 (2 arrays each of 2 M × 8) for CY7C1416KV18 and 4 M × 9 (2 arrays each
of 2 M × 9) for CY7C1427KV18, 2 M × 18 (2 arrays each of 1 M × 18) for CY7C1418KV18, and 1 M × 36
(2 arrays each of 512 K × 36) for CY7C1420KV18.
CY7C1416KV18 – Since the least significant bit of the address internally is a “0,” only 21 external address
inputs are needed to access the entire memory array.
CY7C1427KV18 – Since the least significant bit of the address internally is a “0,” only 21 external address
inputs are needed to access the entire memory array.
CY7C1418KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
21 address inputs are needed to access the entire memory array.
CY7C1420KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
20 address inputs are needed to access the entire memory array. All the address inputs are ignored when
the appropriate port is deselected.
R/W Input-
synchronous
Synchronous read or write input. When LD is LOW, this input designates the access type (read when
R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
C Input clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from the
device. C and C can be used together to deskew the flight times of various devices on the board back to
the controller. See application example for further details.
CInput clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See application example for further details.
K Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and
to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K.
KInput clock Negative input clock input. K is used to capture synchronous data being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 8 of 32
CQ Output clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in the AC Timing table.
CQ Output clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in the AC Timing table.
ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DOFF Input PLL turn off active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
is connected to a pull-up through a 10 K or less pull-up resistor. The device behaves in DDR-I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR-I timing.
TDO Output TDO for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.
NC N/A Not connected to the die. Can be tied to any voltage level.
NC/72M Input Not connected to the die. Can be tied to any voltage level.
NC/144M Input Not connected to the die. Can be tied to any voltage level.
NC/288M Input Not connected to the die. Can be tied to any voltage level.
VREF Input-
reference
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
VDD Power supply Power supply Inputs to the core of the device.
VSS Ground Ground for the device.
VDDQ Power supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name I/O Pin Description
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 9 of 32
Functional Overview
The CY7C1416KV18, CY7C1427KV18, CY7C1418KV18, and
CY7C1420KV18 are synchronous pipelined burst SRAMs
equipped with a DDR interface, which operates with a read
latency of one and a half cycles when DOFF pin is tied HIGH.
When DOFF pin is set LOW or connected to VSS the device
behaves in DDR-I mode with a read latency of one clock cycle.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing is
referenced to the rising edge of the output clocks (C/C, or K/K
when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the output clocks (C/C, or K/K
when in single clock mode).
All synchronous control (R/W, LD, BWS[0:X]) inputs pass through
input registers controlled by the rising edge of the input clock (K).
CY7C1418KV18 is described in the following sections. The
same basic descriptions apply to CY7C1416KV18,
CY7C1427KV18, and CY7C1420KV18.
Read Operations
The CY7C1418KV18 is organized internally as a two arrays of
1 M × 18. Accesses are completed in a burst of 2 sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to address inputs is stored in
the read address register and the least significant bit of the
address is presented to the burst counter. The burst counter
increments the address in a linear fashion. Following the next K
clock rise, the corresponding 18-bit word of data from this
address location is driven onto the Q[17:0] using C as the output
timing reference. On the subsequent rising edge of C the next
18-bit data word from the address location generated by the
burst counter is driven onto the Q[17:0]. The requested data is
valid 0.45 ns from the rising edge of the output clock (C or C, or
K and K when in single clock mode, 200 MHz, 250 MHz, and
300 MHz device). To maintain the internal logic, each read
access must be allowed to complete. Read accesses can be
initiated on every rising edge of the positive input clock (K).
When read access is deselected, the CY7C1418KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the output following the next rising
edge of the positive output clock (C). This enables for a transition
between devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register and the least significant bit of the address is
presented to the burst counter. The burst counter increments the
address in a linear fashion. On the following K clock rise, the data
presented to D[17:0] is latched and stored into the 18-bit write
data register, provided BWS[1:0] are both asserted active. On the
subsequent rising edge of the Negative Input Clock (K) the
information presented to D[17:0] is also stored into the write data
register, provided BWS[1:0] are both asserted active. The 36 bits
of data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
the positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
When the write access is deselected, the device ignores all
inputs after the pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C1418KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate byte write select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the byte write select input during the
data portion of a write enables the data stored in the device for
that byte to remain unaltered. This feature is used to simplify
read, modify, or write operations to a byte write operation.
Single Clock Mode
The CY7C1418KV18 is used with a single clock that controls
both the input and output registers. In this mode, the device
recognizes only a single pair of input clocks (K and K) that control
both the input and output registers. This operation is identical to
the operation if the device had zero skew between the K/K and
C/C clocks. All timing parameters remain the same in this mode.
To use this mode of operation, the user must tie C and C HIGH
at power on. This function is a strap option and not alterable
during device operation.
DDR Operation
The CY7C1418KV18 enables high performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1418KV18 requires a single
No Operation (NOP) cycle during transition from a read to a write
cycle. At higher frequencies, some applications may require a
second NOP cycle to avoid contention.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information must be stored
because the SRAM cannot perform the last word write to the
array without conflicting with the read. The data stays in this
register until the next write cycle occurs. On the first write cycle
after the read(s), the stored data from the earlier write is written
into the SRAM array. This is called a posted write.
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 10 of 32
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ =1.5 V. The
output impedance is adjusted every 1024 cycles upon power-up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are
synchronized to the output clock of the DDR II. In single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in the
Switching Characteristics on page 25.
PLL
These chips use a PLL which is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in DDR-I mode (with one cycle latency and a longer
access time).
Application Example
Figure 1 shows two DDR II used in an application.
Figure 1. Application Example
Vterm = 0.75V
Vterm = 0.75V
R = 50ohms
R = 250ohms
LD# C C#R/W#
DQ
A KLD# C C#R/W#
DQ
A K
SRAM#1 SRAM#2
R = 250ohms
BUS
MASTER
(CPU
or
ASIC)
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
ZQ
CQ/CQ#
K#
ZQ
CQ/CQ#
K#
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 11 of 32
Truth Table
The truth table for the CY7C1416KV18, CY7C1427KV18, CY7C1418KV18, and CY7C1420KV18 follow.[2, 3, 4, 5, 6, 7]
Operation KLD R/W DQ DQ
Write cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
L–H L L D(A1) at K(t + 1) D(A2) at K(t + 1)
Read cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
L–H L H Q(A1) at C(t + 1)Q(A2) at C(t + 2)
NOP: No operation L–H H X High Z High Z
Standby: Clock stopped Stopped X X Previous state Previous state
Burst Address Table
(CY7C1418KV18, CY7C1420KV18)
First Address (External) Second Address (Internal)
X..X0 X..X1
X..X1 X..X0
Write Cycle Descriptions
The write cycle description table for CY7C1416KV18 and CY7C1418KV18 follows.[2, 8]
BWS0/
NWS0
BWS1/
NWS1
KKComments
L L L–H – During the data portion of a write sequence
CY7C1416KV18 both nibbles (D[7:0]) are written into the device.
CY7C1418KV18 both bytes (D[17:0]) are written into the device.
L L – L–H During the data portion of a write sequence
CY7C1416KV18 both nibbles (D[7:0]) are written into the device.
CY7C1418KV18 both bytes (D[17:0]) are written into the device.
L H L–H – During the data portion of a write sequence
CY7C1416KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1418KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H – L–H During the data portion of a write sequence
CY7C1416KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1418KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H – During the data portion of a write sequence
CY7C1416KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1418KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L – L–H During the data portion of a write sequence
CY7C1416KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1418KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. On CY7C1418KV18 and CY7C1420KV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses
sequence in the burst. On CY7C1416KV18 and CY7C1427KV18, “A1” represents A + ‘0’ and “A2” represents A + ‘1’.
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 12 of 32
Write Cycle Descriptions
The write cycle description table for CY7C1427KV18 follows. [9, 10]
BWS0K K
L L–H – During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L – L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H L–H – No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1420KV18 follows.[9, 10]
BWS0BWS1BWS2BWS3K K Comments
LLLLL–H–During the data portion of a write sequence, all four bytes (D
[35:0]) are written into
the device.
LLLL–L–HDuring the data portion of a write sequence, all four bytes (D
[35:0]) are written into
the device.
L H H H L–H – During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L H H H – L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H L H H L–H – During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H L H H – L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H H L H L–H – During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H L H – L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H H L L–H – During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H L – L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
HHHHL–H–No data is written into the device during this portion of a write operation.
HHHH–L–HNo data is written into the device during this portion of a write operation.
Notes
9. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
10. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 13 of 32
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull-up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up inter-
nally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and is performed when the SRAM is operating. At power
up, the TAP is reset internally to ensure that TDO comes up in a
high Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions are serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 16. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are
used to capture the contents of the input and output ring.
The Boundary Scan Order on page 19 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and is shifted out when the TAP controller is in the
Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 18.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 14 of 32
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a high Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
high Z condition.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift-register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is preset HIGH to enable the output
when the device is powered up, and also when the TAP controller
is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 15 of 32
TAP Controller State Diagram
The state diagram for the TAP controller follows.[11]
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
0
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
Note
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 16 of 32
TAP Controller Block Diagram
TAP Electrical Characteristics
Over the Operating Range[12, 13, 14]
Parameter Description Test Conditions Min Max Unit
VOH1 Output HIGH voltage IOH =2.0 mA 1.4 – V
VOH2 Output HIGH voltage IOH =100 A1.6–V
VOL1 Output LOW voltage IOL = 2.0 mA – 0.4 V
VOL2 Output LOW voltage IOL = 100 A–0.2V
VIH Input HIGH voltage 0.65 VDD VDD + 0.3 V
VIL Input LOW voltage –0.3 0.35 VDD V
IXInput and output load current GND VI VDD –5 5 A
0
012..29
3031
Boundary Scan Register
Identification Register
012..
.
.108
012
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI TDO
TCK
TMS
Notes
12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
13. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2).
14. All voltage referenced to ground.
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 17 of 32
TAP AC Switching Characteristics
Over the Operating Range[15, 16]
Parameter Description Min Max Unit
tTCYC TCK clock cycle time 50 – ns
tTF TCK clock frequency – 20 MHz
tTH TCK clock HIGH 20 – ns
tTL TCK clock LOW 20 – ns
Setup Times
tTMSS TMS setup to TCK clock rise 5 – ns
tTDIS TDI setup to TCK clock rise 5 – ns
tCS Capture setup to TCK rise 5 – ns
Hold Times
tTMSH TMS hold after TCK clock rise 5 – ns
tTDIH TDI hold after clock rise 5 – ns
tCH Capture hold after clock rise 5 – ns
Output Times
tTDOV TCK clock LOW to TDO valid – 10 ns
tTDOX TCK clock LOW to TDO invalid 0 – ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions.[16]
Figure 2. TAP Timing and Test Conditions
t
TL
t
TH
(a)
TDO
C
L
= 20 pF
Z
0
= 50
GND
0.9V
50
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
Test Mode Select
TCK
TMS
Test Data In
TDI
Test Data Out
t
TCYC
t
TMSH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
TDO
Notes
15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
16. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 18 of 32
Identification Register Definitions
Instruction Field Value Description
CY7C1416KV18 CY7C1427KV18 CY7C1418KV18 CY7C1420KV18
Revision number
(31:29)
000 000 000 000 Version number.
Cypress device ID
(28:12)
11010100010000111 11010100010001111 11010100010010111 11010100010100111 Defines the type of
SRAM.
Cypress JEDEC ID
(11:1)
00000110100 00000110100 00000110100 00000110100 Allows unique
identification of
SRAM vendor.
ID register
presence (0)
1 1 1 1 Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary scan 109
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the input and output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 19 of 32
Boundary Scan Order
Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID
0 6R 28 10G 56 6A 84 1J
16P299G575B852J
2 6N 30 11F 58 5A 86 3K
3 7P 31 11G 59 4A 87 3J
47N 329F 605C 882K
5 7R 33 10F 61 4B 89 1K
6 8R 34 11E 62 3A 90 2L
7 8P 35 10E 63 2A 91 3L
8 9R 36 10D 64 1A 92 1M
9 11P 37 9E 65 2B 93 1L
10 10P 38 10C 66 3B 94 3N
11 10N 39 11D 67 1C 95 3M
12 9P 40 9C 68 1B 96 1N
13 10M 41 9D 69 3D 97 2M
14 11N 42 11B 70 3C 98 3P
15 9M 43 11C 71 1D 99 2N
16 9N 44 9B 72 2C 100 2P
17 11L 45 10B 73 3E 101 1P
18 11M 46 11A 74 2D 102 3R
19 9L 47 10A 75 2E 103 4R
20 10L 48 9A 76 1E 104 4P
21 11K 49 8B 77 2F 105 5P
22 10K 50 7C 78 3F 106 5N
23 9J 51 6C 79 1G 107 5R
24 9K 52 8A 80 1F 108 Internal
25 10J 53 7A 81 3G
26 11J 54 7B 82 2G
27 11H 55 6B 83 1H
[+] Feedback
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 20 of 32
Power Up Sequence in DDR II SRAM
DDR II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
■Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐Apply VDD before VDDQ.
❐Apply VDDQ before VREF or at the same time as VREF
.
❐Drive DOFF HIGH.
■Provide stable DOFF (HIGH), power and clock (K, K) for 20 s
to lock the PLL.
PLL Constraints
■PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■The PLL functions at frequencies down to 120 MHz.
■If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 s of stable clock to
relock to the desired clock frequency.
Figure 3. Power Up Waveforms
> 20Ps Stable clock
Start Normal
Operation
DOFF
Stable(< +/- 0.1V DC per 50ns )
Fix HIGH (or tie to V
DDQ)
K
K
DDQDD
VV
/DDQDD
VV
/
Clock Start (Clock Starts after Stable)
DDQ
DD
VV
/
~
~
~
~
Unstable Clock
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CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
Document Number: 001-57827 Rev. *B Page 21 of 32
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with power applied . –55 °C to +125 °C
Supply voltage on VDD relative to GND........–0.5 V to +2.9 V
Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD
DC applied to outputs in high Z .........–0.5 V to VDDQ + 0.3 V
DC input voltage[17] ............................. –0.5 V to VDD + 0.3 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage (MIL-STD-883, M 3015)... > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Range Ambient
Temperature (TA) VDD[18] VDDQ[18]
Commercial 0 °C to +70 °C 1.8 ± 0.1 V 1.4 V to
VDD
Industrial –40 °C to +85 °C
Neutron Soft Error Immunity
Parameter Description Test
Conditions Typ Max* Unit
LSBU Logical
single-bit
upsets
25 °C 197 216 FIT/
Mb
LMBU Logical
multi-bit
upsets
25 °C 00.01 FIT/
Mb
SEL Single event
latch-up
85 °C 00.1 FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to
Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation
of Terrestrial Failure Rates”
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range[19]
Parameter Description Test Conditions Min Typ Max Unit
VDD Power supply voltage 1.7 1.8 1.9 V
VDDQ IO supply voltage 1.4 1.5 VDD V
VOH Output HIGH voltage Note 20 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V
VOL Output LOW voltage Note 21 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V
VOH(LOW) Output HIGH voltage IOH =0.1 mA, nominal impedance VDDQ – 0.2 – VDDQ V
VOL(LOW) Output LOW voltage IOL = 0.1 mA, nominal impedance VSS –0.2 V
VIH Input HIGH voltage VREF + 0.1 – VDDQ + 0.3 V
VIL Input LOW voltage –0.3 – VREF – 0.1 V
IXInput leakage current GND VI VDDQ 5 – 5 A
IOZ Output leakage current GND VI VDDQ, output disabled 5 – 5 A
VREF Input reference voltage[22] Typical value = 0.75 V 0.68 0.75 0.95 V
Notes
17. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2).
18. Power-up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
19. All voltage referenced to ground.
20. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175 < RQ < 350 .
21. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 < RQ < 350 .
22. VREF(min) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF(max) = 0.95 V or 0.54 VDDQ, whichever is smaller.
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Document Number: 001-57827 Rev. *B Page 22 of 32
IDD[23] VDD operating supply VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
333 MHz (× 8) – – 480 mA
(× 9) – – 480
(× 18) – – 490
(× 36) – – 600
300 MHz (× 8) – – 450 mA
(× 9) – – 450
(× 18) – – 460
(× 36) – – 560
250 MHz (× 8) – – 420 mA
(× 9) – – 420
(× 18) – – 430
(× 36) – – 490
200 MHz (× 8) – – 370 mA
(× 9) – – 370
(× 18) – – 380
(× 36) – – 430
167 MHz (× 8) – – 340 mA
(× 9) – – 340
(× 18) – – 340
(× 36) – – 400
Electrical Characteristics (continued)
DC Electrical Characteristics
Over the Operating Range[19]
Parameter Description Test Conditions Min Typ Max Unit
Note
23. The operation current is calculated with 50% read cycle and 50% write cycle.
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Document Number: 001-57827 Rev. *B Page 23 of 32
ISB1 Automatic power-down
current
Max VDD,
both ports deselected,
VIN VIH or VIN VIL
f = fMAX = 1/tCYC,
inputs static
333 MHz (× 8) – – 280 mA
(× 9) – – 280
(× 18) – – 280
(× 36) – – 280
300 MHz (× 8) – – 270 mA
(× 9) – – 270
(× 18) – – 270
(× 36) – – 270
250 MHz (× 8) – – 260 mA
(× 9) – – 260
(× 18) – – 260
(× 36) – – 260
200 MHz (× 8) – – 250 mA
(× 9) – – 250
(× 18) – – 250
(× 36) – – 250
167 MHz (× 8) – – 250 mA
(× 9) – – 250
(× 18) – – 250
(× 36) – – 250
AC Electrical Characteristics
Over the Operating Range[24]
Parameter Description Test Conditions Min Typ Max Unit
VIH Input HIGH voltage VREF + 0.2 – – V
VIL Input LOW voltage – – VREF – 0.2 V
Electrical Characteristics (continued)
DC Electrical Characteristics
Over the Operating Range[19]
Parameter Description Test Conditions Min Typ Max Unit
Note
24. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2).
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Document Number: 001-57827 Rev. *B Page 24 of 32
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V 4 pF
COOutput capacitance 4pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions 165 FBGA
Package Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
13.7 °C/W
JC Thermal resistance
(junction to case)
3.73 °C/W
Figure 4. AC Test Loads and Waveforms
1.25 V
0.25 V
R = 50
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
Device RL= 50
Z0= 50
VREF = 0.75 V
VREF = 0.75 V
[25]
0.75 V
Under
Tes t
0.75 V
Device
Under
Te s t
OUTPUT
0.75 V
VREF
VREF
OUTPUT
ZQ
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
(b)
RQ =
250
Note
25. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, VREF = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse
levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
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Document Number: 001-57827 Rev. *B Page 25 of 32
Switching Characteristics
Over the Operating Range[26, 27]
Cypress
Parameter
Consortium
Parameter Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit
Min Max Min Max Min Max Min Max Min Max
tPOWER VDD(typical) to the first access[28] 1–1–1–1–1–ms
tCYC tKHKH K clock and C clock cycle time 3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns
tKH tKHKL Input clock (K/K and C/C) HIGH 1.20 – 1.32 – 1.6 – 2.0 – 2.4 – ns
tKL tKLKH Input clock (K/K and C/C) LOW 1.20–1.32–1.6–2.0–2.4– ns
tKHKHtKHKHK clock rise to K clock rise and C to
C rise (rising edge to rising edge)
1.35 – 1.49 – 1.8 – 2.2 – 2.7 – ns
tKHCH tKHCH K/K clock rise to C/C clock rise
(rising edge to rising edge)
0.0 1.30 0.0 1.45 0.0 1.8 0.0 2.2 0.0 2.7 ns
Setup Times
tSA tAVKH Address set-up to K clock rise 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
tSC tIVKH Control set-up to K clock rise
(LD, R/W)
0.4–0.4–0.5–0.6–0.7– ns
tSCDDR tIVKH Double data rate control set-up to
clock (K/K) rise
(BWS0, BWS1, BWS2, BWS3)
0.3–0.3–0.35–0.4–0.5– ns
tSD tDVKH D[X:0] set-up to clock (K/K) rise 0.3–0.3–0.35–0.4–0.5– ns
Hold Times
tHA tKHAX Address hold after K clock rise 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
tHC tKHIX Control hold after K clock rise
(LD, R/W)
0.4–0.4–0.5–0.6–0.7– ns
tHCDDR tKHIX Double data rate control hold after
clock (K/K) rise
(BWS0, BWS1, BWS2, BWS3)
0.3–0.3–0.35–0.4–0.5– ns
tHD tKHDX D[X:0] hold after clock (K/K) rise 0.3–0.3–0.35–0.4–0.5– ns
Notes
26. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, VREF = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse
levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
27. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated
and outputs data with the output timings of that frequency range.
28. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD min initially before a read or write operation can be initiated.
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Document Number: 001-57827 Rev. *B Page 26 of 32
Output Times
tCO tCHQV C/C clock rise (or K/K in single clock
mode) to data valid
– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tDOH tCHQX Data output hold after output C/C
clock rise (active to active)
–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
tCCQO tCHCQV C/C clock rise to echo clock valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tCQOH tCHCQX Echo clock hold after C/C clock rise –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
tCQD tCQHQV Echo clock high to data valid – 0.25 – 0.27 – 0.30 – 0.35 – 0.40 ns
tCQDOH tCQHQX Echo clock high to data invalid –0.25 – –0.27 – –0.30 – –0.35 – –0.40 – ns
tCQH tCQHCQL Output clock (CQ/CQ) HIGH[29] 1.25 – 1.40 – 1.75 – 2.25 – 2.75 – ns
tCQHCQHtCQHCQHCQ clock rise to CQ clock rise
(rising edge to rising edge)[29] 1.25 – 1.40 – 1.75 – 2.25 – 2.75 – ns
tCHZ tCHQZ Clock (C/C) rise to high Z
(active to high Z)[30, 31] – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tCLZ tCHQX1 Clock (C/C) rise to low Z[30, 31] –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
PLL Timing
tKC Var tKC Var Clock phase jitter – 0.20 – 0.20 – 0.20 – 0.20 – 0.20 ns
tKC lock tKC lock PLL lock time (K, C)[32] 20–20–20–20–20– s
tKC Reset tKC Reset K static to PLL reset 30–30–30–30–30– ns
Switching Characteristics (continued)
Over the Operating Range[26, 27]
Cypress
Parameter
Consortium
Parameter Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit
Min Max Min Max Min Max Min Max Min Max
Notes
29. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
30. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured 100 mV from steady-state voltage.
31. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
32. For frequencies 300 MHz or below, the Cypress QDR II devices surpass the QDR consortium specification for PLL lock time (tKC lock) of 20 µs (min. spec.) and will
lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version.
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Document Number: 001-57827 Rev. *B Page 27 of 32
Switching Waveforms
Figure 5. Read/Write/Deselect Sequence[33, 34, 35]
READ READREAD NOP NOP WRITEWRITE
NOP
12345678 910
Q40
tKHCH
tCO
ttHC
ttHA
tSD
tHD
tKHCH
tSD
tHD
DON’T CARE UNDEFINED
tCLZ tDOH tCHZ
SC
tKH tKHKH
tKL tCYC
A0
D20 D21 D30 D31
Q00 Q11Q01 Q10
A1 A2 A3 A4
Q41
tCCQO
tCQOH
tCCQO
tCQOH
tKL tCYC
K
K
LD
R/W
A
DQ
C
C#
CQ
CQ#
SA
tKH tKHKH
tCQD
tCQDOH
tCQH tCQHCQH
Notes
33. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
34. Outputs are disabled (high Z) one clock cycle after a NOP.
35. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
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Document Number: 001-57827 Rev. *B Page 28 of 32
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz) Ordering Code
Package
Diagram Package Type
Operating
Range
333 CY7C1418KV18-333BZC 51-85180 165-ball Fine-pitch Ball Grid Array (13 × 15 × 1.4 mm) Commercial
CY7C1420KV18-333BZC
CY7C1420KV18-333BZI Industrial
CY7C1420KV18-333BZXI 165-ball Fine-pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free
300 CY7C1418KV18-300BZC 51-85180 165-ball Fine-pitch Ball Grid Array (13 × 15 × 1.4 mm) Commercial
CY7C1418KV18-300BZXC 165-ball Fine-pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free
CY7C1420KV18-300BZXC
250 CY7C1418KV18-250BZC 51-85180 165-ball Fine-pitch Ball Grid Array (13 × 15 × 1.4 mm) Commercial
CY7C1420KV18-250BZC
CY7C1418KV18-250BZXC 165-ball Fine-pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free
CY7C1420KV18-250BZXC
CY7C1418KV18-250BZI 165-ball Fine-pitch Ball Grid Array (13 × 15 × 1.4 mm) Industrial
CY7C1420KV18-250BZI
CY7C1420KV18-250BZXI 165-ball Fine-pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free
Ordering Code Definitions
Temperature Range: X = C or I
C = Commercial = 0 C to +70 C; I = Industrial = –40 C to +85 C
X = Pb-free; X Absent = Leaded
Package Type:
BZ = 165-ball FBGA
Speed Grade: XXX = 333 MHz / 250 MHz
V18 = 1.8 V VDD
Process Technology 65 nm
14XX = 1418 or 1420 = Part Identifier
Marketing Code: 7C = SRAMs
Company ID: CY = Cypress
CY 14XX K - XXX BZ XV18 X7C
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Document Number: 001-57827 Rev. *B Page 30 of 32
Acronyms Document Conventions
Units of Measure
Acronym Description
DDR double data rate
FBGA fine-pitch ball grid array
HSTL high-speed transceiver logic
I/O input/output
JTAG joint test action group
LSB least significant bit
MSB most significant bit
PLL phase locked loop
QDR quad data rate
SRAM static random access memory
TAP test access port
TCK test clock
TMS test mode select
TDI test data-in
TDO test data-out
TQFP thin quad flat pack
Symbol Unit of Measure
ohms
% percent
µs micro seconds
ms milli seconds
ns nano seconds
VVolts
µA micro Amperes
mA milli Amperes
mm milli meter
MHz Mega Hertz
pF pico Farad
WWatts
°C degree Celcius
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Document Number: 001-57827 Rev. *B Page 31 of 32
Document History Page
Document Title: CY7C1416KV18/CY7C1427KV18/CY7C1418KV18/CY7C1420KV18, 36-Mbit DDR II SRAM 2-Word Burst
Architecture
Document Number: 001-57827
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 2816620 VKN/AESA 11/27/2009 New Data Sheet
*A 3018546 NJY 10/21/2010 Converted from Preliminary to Final.
Added Ordering Code Definitions.
Updated Package Diagram.
Minor edits and updated in new template.
*B 3165654 NJY 02/08/2011 Added Note 32.
Updated Ordering Information.
Added Acronyms and Units of Measure.
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Document Number: 001-57827 Rev. *B Revised February 25, 2011 Page 32 of 32
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document
may be the trademarks of their respective holders.
CY7C1416KV18, CY7C1427KV18
CY7C1418KV18, CY7C1420KV18
© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive cypress.com/go/automotive
Clocks & Buffers cypress.com/go/clocks
Interface cypress.com/go/interface
Lighting & Power Control cypress.com/go/powerpsoc
cypress.com/go/plc
Memory cypress.com/go/memory
Optical & Image Sensing cypress.com/go/image
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
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