HI-3200PCI - Holt Integrated Circuits, Inc.

GENERAL DESCRIPTION

The HI-3200 from Holt Integrated Circuits is a single chip

CMOS data management IC capable of managing, storing

and forwarding avionics data messages between eight

ARINC 429 receive channels, four ARINC 429 transmit

channels and a single CAN / ARINC 825 data bus.

The ARINC 429 and CAN buses may be operated inde-

pendently, allowing a host CPU to send and receive data

on multiple buses, or the HI-3200 can be programmed to

automatically re-format, re-label, re-packetize and re-

transmit data from ARINC 429 receive buses to ARINC

429 transmit buses, as well as from ARINC 429 to CAN or

CAN to ARINC 429.

A 32K x 8 on-board memory allows received data to be

logically organized and automatically updated as new

ARINC 429 labels or CAN frames are received.

An auto-initialization feature allows configuration informa-

tion to be up-loaded from an external EEPROM on reset to

facilitate rapid start-up or operation without a host CPU.

The HI-3200 interfaces directly with Holt’s HI-8448 octal

ARINC 429 receiver IC, HI-8596 or HI-8592 ARINC 429

line drivers and HI-3110 integrated CAN controller /

transceiver.

The HI-3201 is identical to the HI-3200 except it comes in

an 80-pin PQFP package with eight instead of two ARINC

429 bit monitor pins.

FEATURES

Eight ARINC 429 Receive channels

Four ARINC 429 Transmit channels

CAN Bus / ARINC 825 Interface

32KB on chip user-configurable data storage

memory

Programmable received data filtering for ARINC 429

and CAN buses

Flexible protocol bridge ARINC 429 to CAN and

CAN to ARINC 429

Programmable transmission schedulers for periodic

ARINC 429 and CAN message broadcasting

SPI Host CPU interface

Auto-initialization feature allows power-on

configuration or independent operation without CPU

(DS3200 Rev. F) 11/13

AVIONICS DATA MANAGEMENT ENGINE /

ARINC 429 - CAN BUS BRIDGE

November 2013

HI-3200, HI-3201

CPU

CAN Bus

ARINC 429

8 x Receive

ARINC 429

4 x Transmit

HI-3110

HI-8448

HI-3200

APPLICATION

PIN CONFIGURATION

64 - Pin Plastic Quad Flat Pack (PQFP)

(See ordering information for additional pin configurations)

HI-3200PQI

HI-3200PQT

AACK 1

CGP2 2

AINT 3

CSTAT 4

SCANSHIFT 5

ARX2N 6

ARX3P 7

VDD 8

GND 9

ARX3N 10

ARX4P 11

ARX4N 12

ARX5P 13

ARX5N 14

ARX6P 15

ARX6N 16

48 CMROUT

47 ATXSLP0

46 ATX0N

45 ATX0P

44 ATX1N

43 ATX1P

42 ATXSLP1

41 VDD

40 GND

39 COSC

38 ATXSLP2

37 ATX2N

36 ATX2P

35 ATX3N

34 ATX3P

33 ATXSLP3

64 ARX2P

63 ARX1N

62 ARX1P

61 ARX0N

60 ARX0P

59 SCANEN

58 CMISO

57 READY

56 ESCLK

55 EMOSI

53 EMISO

52 RUN

50 ATXMSK

49 MRST

ECSB

CCSB

ARX7P 17

ARX7N 18

MODE0 19

CMOSI 20

MODE1 21

MCLK 22

MODE2 23

ARXBIT0 24

ARXBIT1 25

HMISO 26

HSCLK 27

HMOSI 28

CSCLK 30

MINT 31

MINTACK 32

HCSB

HI-3200, HI-3201

HOLT INTEGRATED CIRCUITS

BLOCK DIAGRAM

ARINC 825 (CAN)

FILTER

ARINC 825 / CAN

FILTER / MASK

TABLE HI-3110

Configuration

& Control

HI-3110

Data

Interfacel

ARINC 429

RECEIVE DATA

MEMORY 0

1K x 8

ARINC 825 / CAN Bus

CCSB

CSCLK

CMOSI

CMISO

HI-3110

Transceiver

CMROUT

COSC

CGP2

CSTAT

ARINC 825 (CAN)

TRANSMIT

SCHEDULER

ARINC 825 (CAN)

Descriptor Table

TRANSMIT TIMER

8 x ARINC 429 Receive Buses

RECEIVER 0

Message 32

“

Message 2

Message 1

LABEL

FILTER

TABLE 0

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

32 x 32 FIFO

4 x ARINC 429 Transmit Buses

HI-3200

TRANSMITTER 0

TRANSMIT TIMER

ARINC 429

TRANSMIT

SCHEDULER 0

ARINC 429

Descriptor Table 0

SPI

HCSB

HSCLK

HMOSI

HMISO

Host CPU

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

ARINC825 / CAN

RECEIVE DATA

MEMORY

4Kx8

EEPROM

SPI

ECSB

ESCLK

EMOSI

EMISO

Auto-Initialization

EEPROM

ARINC 429

Interrupt Handler

ARINC 825 (CAN)

Interrupt Handler

AACK

AINT

MINT

MINTACK

ARINC 429

BIT MATCH

ARXBIT4

ARXBIT3

ARXBIT2

ARXBIT1

ARXBIT6

ARXBIT5

ARXBIT7

ARXBIT0

HI-3200, HI-3201

HOLT INTEGRATED CIRCUITS

APPLICATION OVERVIEW

The HI-3200 is a flexible device for managing ARINC 429

and ARINC 825 communications and data storage in

many avionics applications. The device architecture

centers around a 32K x 8 static RAM used for data

storage, data filtering tables and table-driven

transmission schedulers. Once configured, the device

can operate autonomously without a host CPU, negating

the need for software development or DO-178

certification. Configuration data may be uploaded into the

device from an external EEPROM, following system

reset.

The device supports up to eight ARINC 429 receive

channels. Received data is stored in on-chip RAM

organized by channel number and label. The data table

continually updates as new labels arrive. Programmable

interrupts and filters alert the host subsystem to labels of

interest.

Each ARINC 429 receive channel also includes a 32

message deep FIFO allowing selected label data to be

queued for subsequent host access.

The HI-3200 includes four independent ARINC 429

transmit channels. Transmission may be controlled

entirely by an external CPU, or autonomously by

programming one or more of the four on-chip ARINC 429

transmit schedulers. These allow periodic transmission

to occur without CPU. Source data for transmission may

be selected from RAM based tables of constants and / or

from the received channel data. Powerful options exist for

constructing ARINC 429 labels as well as controlling their

timing and conditional transmission.

Even when running under the control of schedulers, the

host CPU may insert new labels for transmission at will.

The HI-3200 also supports ARINC 825 (CAN)

communication. An external HI-3110 CAN controller

automatically handles the CAN bus protocol and physical

interface. The HI-3200 configures the HI-3110 at system

initialization and manages all traffic to and from the CAN

bus.

As with ARINC 429, ARINC 825 received data may be

filtered and stored in on-chip RAM, organized by ID field

filters. ARINC 825 frame transmission may be directly

controlled by a host CPU or by an on-chip transmission

scheduler. CAN frames may be built and conditionally

transmitted using the scheduler’s flexible instruction set.

Source data for CAN frames can be from CPU, stored

constants or from received ARINC 429 data tables.

The following examples show eight possible

configurations of how the HI-3200 may be used:

Example 1. ARINC 429 Data reception using on-chip RAM

8K x 8 RAM

8 x ARINC 429

Receive Buses

SPI

Channel 0, Label FF

“

Channel 0, Label 01

Channel 0, Label 00

Channel 1, Label FF

“

Channel 1, Label 01

Channel 1, Label 00

Channel 2, Label FF

“

Channel 2, Label 01

Channel 2, Label 00

Channel 3, Label FF

“

Channel 3, Label 01

Channel 3, Label 00

Channel 4, Label FF

“

Channel 4, Label 01

Channel 4, Label 00

Channel 5, Label FF

“

Channel 5, Label 01

Channel 5, Label 00

Channel 6, Label FF

“

Channel 6, Label 01

Channel 6, Label 00

Channel 7, Label FF

“

Channel 7, Label 01

Channel 7, Label 00

ARINC 429

RECEIVE

INTERRUPT

TABLE

AINT

AACK

HCSB

HSCLK

HMOSI

HMISO

RECEIVER 7

RECEIVER 6

RECEIVER 5

RECEIVER 4

RECEIVER 3

RECEIVER 2

RECEIVER 1

RECEIVER 0

Host CPU

HI-3200

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Example 3. ARINC 429 Data transmission directly from CPU

TRANSMITTER 0

SPI

HCSB

HSCLK

HMOSI

HMISO

TRANSMITTER 2

TRANSMITTER 1

TRANSMITTER 3

Host CPU 4 x ARINC 429

Transmit Buses

HI-3200

8 x ARINC 429

Receive Buses

RECEIVER 0

FIFO STATUS

HI-3200

Message 32

“

Message 2

Message 1

LABEL

FILTER

TABLE 0

SPI

ARINC 429

RECEIVE FIFO

INTERRUPT

CONTROL

AINT

AACK

HCSB

HSCLK

HMOSI

HMISO

Host CPU

FIFO EMPTY

FIFO THRESHOLD

FIFO FULL

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

32x32FIFO

Example 2. ARINC 429 Data reception using on-chip filters and FIFOs

Example 4. ARINC 429 Data transmission using on-chip schedulers

TRANSMIT

SCHEDULER 0

RAM

Descriptor Table 3

4 x ARINC 429

Transmit Buses

TRANSMITTER 0

Descriptor Table 2

Descriptor Table 1

Descriptor Table 0

TRANSMIT TIMER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

EEPROM

SPI

ECSB

ESCLK

EMOSI

EMISO

Auto-Initialization

EEPROM

HI-3200

SPI

HCSB

HSCLK

HMOSI

HMISO

Host CPU

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Example 5. Autonomous ARINC 429 Data Concentrator / Repeater

TRANSMIT

SCHEDULER 3

4 x ARINC 429

Transmit Buses

TRANSMITTER 3

Descriptor Table 3

TRANSMIT TIMER

EEPROM

SPI

ECSB

ESCLK

EMOSI

EMISO

Auto-Initialization

EEPROM

HI-3200

8 x ARINC 429

Receive Buses

Channel 0, Label FF

“

Channel 0, Label 01

Channel 0, Label 00

Channel 1, Label FF

“

Channel 1, Label 01

Channel 1, Label 00

Channel 2, Label FF

“

Channel 2, Label 01

Channel 2, Label 00

Channel 3, Label FF

“

Channel 3, Label 01

Channel 3, Label 00

Channel 4, Label FF

“

Channel 4, Label 01

Channel 4, Label 00

Channel 5, Label FF

“

Channel 5, Label 01

Channel 5, Label 00

Channel 6, Label FF

“

Channel 6, Label 01

Channel 6, Label 00

Channel 7, Label FF

“

Channel 7, Label 01

Channel 7, Label 00

RECEIVER 7

RECEIVER 6

RECEIVER 5

RECEIVER 4

RECEIVER 3

RECEIVER 2

RECEIVER 1

RECEIVER 0

TRANSMIT

SCHEDULER 2

TRANSMITTER 2

Descriptor Table 2

TRANSMIT TIMER

TRANSMIT

SCHEDULER 1

TRANSMITTER 1

Descriptor Table 1

TRANSMIT TIMER

TRANSMIT

SCHEDULER 0

TRANSMITTER 0

Descriptor Table 0

TRANSMIT TIMER

Example 6. ARINC 825 (CAN) bus Monitor / Receiver

ARINC 825 / CAN Bus

HI-3200

ARINC825 / CAN

FILTER

ARINC 825 / CAN

FILTER / MASK

TABLE

SPI

ARINC 825 / CAN

INTERRUPT

CONTROL

MINT

MINTACK

HCSB

HSCLK

HMOSI

HMISO

Host CPU

CCSB

CSCLK

CMOSI

CMISO

HI-3110

Transceiver

CMROUT

COSC

CGP2

CSTAT

HI-3110

Configuration

& Control

HI-3110

Data

Interface

ARINC825 / CAN

RECEIVE DATA

MEMORY

4Kx8

ARINC 825 / CAN

INTERRUPT ENABLE

TABLE

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Example 7. ARINC 825 (CAN) Terminal / Data Manager

ARINC825 / CAN

FILTER

ARINC 825 / CAN

FILTER / MASK

TABLE

ARINC 825 / CAN

INTERRUPT

CONTROL

HI-3110

Configuration

& Control

HI-3110

Data

Interfacel

ARINC825 / CAN

RECEIVE DATA

MEMORY

4Kx8

ARINC 825 / CAN

INTERRUPT ENABLE

TABLE

ARINC 825 / CAN Bus

HI-3200

SPI

MINT

MINTACK

HCSB

HSCLK

HMOSI

HMISO

Host CPU

CCSB

CSCLK

CMOSI

CMISO

HI-3110

Transceiver

CMROUT

COSC

CGP2

CSTAT

ARINC 825 / CAN

TRANSMITTER

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Example 8. ARINC 429 - ARINC 825 (CAN) Autonomous Bridge

4 x ARINC 429

Transmit Buses

TRANSMITTER 3

ARINC 429

Descriptor Table 3

TRANSMIT TIMER

EEPROM

SPI

ECSB

ESCLK

EMOSI

EMISO

Auto-Initialization

EEPROM

HI-3200

8 x ARINC 429

Receive Buses

Channel 0, Label FF

“

Channel 0, Label 01

Channel 0, Label 00

Channel 1, Label FF

“

Channel 1, Label 01

Channel 1, Label 00

Channel 2, Label FF

“

Channel 2, Label 01

Channel 2, Label 00

Channel 3, Label FF

“

Channel 3, Label 01

Channel 3, Label 00

Channel 4, Label FF

“

Channel 4, Label 01

Channel 4, Label 00

Channel 5, Label FF

“

Channel 5, Label 01

Channel 5, Label 00

Channel 6, Label FF

“

Channel 6, Label 01

Channel 6, Label 00

Channel 7, Label FF

“

Channel 7, Label 01

Channel 7, Label 00

RECEIVER 7

RECEIVER 6

RECEIVER 5

RECEIVER 4

RECEIVER 3

RECEIVER 2

RECEIVER 1

RECEIVER 0

ARINC 429

TRANSMIT

SCHEDULER 1

TRANSMITTER 2

TRANSMIT TIMER

TRANSMITTER 1

TRANSMIT TIMER

TRANSMITTER 0

TRANSMIT TIMER

ARINC 825 (CAN)

FILTER

ARINC 825 / CAN

FILTER / MASK

TABLE HI-3110

Configuration

& Control

HI-3110

Data

Interfacel

ARINC825 / CAN

RECEIVE DATA

MEMORY

4Kx8

ARINC 825 / CAN Bus

CCSB

CSCLK

CMOSI

CMISO

HI-3110

Transceiver

CMROUT

COSC

CGP2

CSTAT

ARINC 429

TRANSMIT

SCHEDULER 2

ARINC 429

TRANSMIT

SCHEDULER 3

ARINC 429

TRANSMIT

SCHEDULER 0

ARINC 429

Descriptor Table 2

ARINC 429

Descriptor Table 1

ARINC 429

Descriptor Table 0

ARINC 825 (CAN)

TRANSMIT

SCHEDULER

ARINC 825 (CAN)

Descriptor Table

TRANSMIT TIMER

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

PIN DESCRIPTIONS

SIGNAL FUNCTION DESCRIPTION

AACK INPUT ARINC 429 Receiver Interrupt Acknowledge

AINT OUTPUT ARINC 429 Receiver Interrupt

ARX0N INPUT ARINC 429 Rx negative data input for channel 0

ARX0P INPUT ARINC 429 Rx positive data input for channel 0

ARX1N INPUT ARINC 429 Rx negative data input for channel 1

ARX1P INPUT ARINC 429 Rx positive data input for channel 1

ARX2N INPUT ARINC 429 Rx negative data input for channel 2

ARX2P INPUT ARINC 429 Rx positive data input for channel 2

ARX3N INPUT ARINC 429 Rx negative data input for channel 3

ARX3P INPUT ARINC 429 Rx positive data input for channel 3

ARX4N INPUT ARINC 429 Rx negative data input for channel 4

ARX4P INPUT ARINC 429 Rx positive data input for channel 4

ARX5N INPUT ARINC 429 Rx negative data input for channel 5

ARX5P INPUT ARINC 429 Rx positive data input for channel 5

ARX6N INPUT ARINC 429 Rx negative data input for channel 6

ARX6P INPUT ARINC 429 Rx positive data input for channel 6

ARX7N INPUT ARINC 429 Rx negative data input for channel 7

ARX7P INPUT ARINC 429 Rx positive data input for channel 7

ARXBIT0-1 OUTPUTS ARINC 429 received payload bit monitor pins 0 and 1

ARXBIT2-7 OUTPUTS ARINC 429 received payload bit monitor pins 2 through 7 (HI-3201 only)

ATX0N OUTPUT ARINC 429 Tx channel 0 negative data output to line driver

ATX0P OUTPUT ARINC 429 Tx channel 0 positive data output to line driver

ATX1N OUTPUT ARINC 429 Tx channel 1 negative data output to line driver

ATX1P OUTPUT ARINC 429 Tx channel 1 positive data output to line driver

ATX2N OUTPUT ARINC 429 Tx channel 2 negative data output to line driver

ATX2P OUTPUT ARINC 429 Tx channel 2 positive data output to line driver

ATX3N OUTPUT ARINC 429 Tx channel 3 negative data output to line driver

ATX3P OUTPUT ARINC 429 Tx channel 3 positive data output to line driver

ATXMSK INPUT Turn off ARINC 429 Transmit pins (Holds TXnA/B pins zero)

ATXSLP0 OUTPUT ARINC 429 Tx channel 0 data rate select output. 1 = high speed, 0 = low speed

ATXSLP1 OUTPUT ARINC 429 Tx channel 1 data rate select output. 1 = high speed, 0 = low speed

ATXSLP2 OUTPUT ARINC 429 Tx channel 2 data rate select output. 1 = high speed, 0 = low speed

ATXSLP3 OUTPUT ARINC 429 Tx channel 3 data rate select output. 1 = high speed, 0 = low speed

OUTPUT SPI chip select for HI-3110 CAN Controller / Transceiver

CGP2 INPUT Signal from HI-3110 CAN Controller / Transceiver indicating CAN Rx data is available

CMISO INPUT SPI serial data input from HI-3110 CAN Controller / Transceiver

CMOSI OUTPUT SPI serial data output to HI-3110 CAN Controller / Transceiver

CMROUT OUTPUT Master Reset signal to HI-3110 CAN Controller / Transceiver

COSC OUTPUT 24 MHz CAN reference clock output to HI-3110 CAN Controller / Transceiver

CSCLK OUTPUT SPI clock for HI-3110 CAN Controller / Transceiver

CSTAT INPUT Signal from HI-3110 CAN Controller / Transceiver indicating CAN Tx FIFO is full

OUTPUT SPI chip select for auto-initialization EEPROM

EMISO INPUT SPI serial data input from auto-inialization EEPROM

EMOSI OUTPUT SPI serial data output to auto-initialization EEPROM

ESCLK OUTPUT SPI clock for auto-initialization EEPROM

GND POWER Chip 0V supply

INPUT Chip select. Data is shifted into HMOSI and out of HMISO when HCSB is low

HMISO OUTPUT Host CPU SPI interface serial data output

HMOSI INPUT Host CPU SPI interface serial data input

HSCLK INPUT SPI Clock. Data is shifted into or out of the SPI interface using HSCLK

MCLK INPUT Master 48 MHZ and reference clock for ARINC 429 and CAN bus bit timing

MINT OUTPUT Programmable event interrupt output

MINTACK INPUT Programmable event interrupt acknowledge

MODE2:0 INPUTS MODE2 through MODE0 define HI-3200 start-up and initialization mode

MRST INPUT Master Reset to HI-3200 Active High

PROG (MODE0) INPUT Multiplexed with MODE0 pin, PROG initiates HI-3200 Auto-Initialization EEPROM programming routine

READY OUTPUT READY goes high when post-RESET initialization is complete

RUN INPUT Master enable signal for ARINC 429 and CAN transmit schedulers

SCANEN RESERVED Connect to GND

SCANSHIFT RESERVED Connect to GND

VDD POWER 3.3V power supply

CCSB

ECSB

HCSB

HI-3200 MEMORY MAP

HOLT INTEGRATED CIRCUITS

ARINC 429

Receive

Data

CAN Bus

Receive

Data

CAN Bus

Receive

Filters

ARINC 429 TX0

Transmit Schedule

Table

CAN Bus

Transmit Schedule

Table

Look-up Tables

0x0000

0x2000

0x1FFF

0x2FFF

0x3000

0x33FF

0x3400

0x3FFF

0x4000

0x47FF

ARINC 429 TX1

Transmit Schedule

Table

ARINC 429 TX2

Transmit Schedule

Table

ARINC 429 Log FIFO Space

ARINC 429 TX3

Transmit Schedule

Table

0x4800

0x4FFF

0x5000

0x57FF

0x5800

0x5FFF

0x6000

0x79BF

0x7BFF

Configuration Registers

0x8000

0x8XXX

ARINC 429 RX Enable Map

ARINC 429 RX Interrupt Map

CAN Bus RX Enable Map

Can Bus RX Interrupt Map

0x7A00

0x7AFF

0x7B00

0x7BFF

0x79C0

0x79DF

0x79E0

0x79FF

Shaded Area

User - Programmed

Non-shaded Area

Data Storage

CAN TX ID Look-Up Table

0x7C00

0x7FFF

0x79C0

HI-3200, HI-3201

HI-3200 REGISTER MAP

ADDRESS R/W REGISTER MNEMONIC DESCRIPTION

0x8000 R* ARINC 429 Rx PENDING INTERRUPT APIR Defines channel(s) with pending Interrupt

0x8001 R ARINC 429 Rx INTERRUPT ADDRESS 0 AIAR0 ARINC 429 Interrupt Vector channel 0

0x8002 R ARINC 429 Rx INTERRUPT ADDRESS 1 AIAR1 ARINC 429 Interrupt Vector channel 1

0x8003 R ARINC 429 Rx INTERRUPT ADDRESS 2 AIAR2 ARINC 429 Interrupt Vector channel 2

0x8004 R ARINC 429 Rx INTERRUPT ADDRESS 3 AIAR3 ARINC 429 Interrupt Vector channel 3

0x8005 R ARINC 429 Rx INTERRUPT ADDRESS 4 AIAR4 ARINC 429 Interrupt Vector channel 4

0x8006 R ARINC 429 Rx INTERRUPT ADDRESS 5 AIAR5 ARINC 429 Interrupt Vector channel 5

0x8007 R ARINC 429 Rx INTERRUPT ADDRESS 6 AIAR6 ARINC 429 Interrupt Vector channel 6

0x8008 R ARINC 429 Rx INTERRUPT ADDRESS 7 AIAR7 ARINC 429 Interrupt Vector channel 7

0x8009 - RESERVED

0x800A R* PENDING INTERRUPT REGISTER PIR Indicates Interrupt type

0x800B R INTERRUPT ADDRESS REGISTER CIAR CAN bus Interrupt vector

0x800C R MUXED FIFO FLAGS AMFF ARINC 429 Multiplexed FIFO flags

0x800D R ARINC 429 TX READY BITS ATRB ARINC 429 Transmitter Ready flags

0x800E R MASTER STATUS REGISTER MSR Indicates HI-3200 current status

0x800F R/W MASTER CONTROL REGISTER MCR HI-3200 global configuration

0x8010 R/W ARINC 429 RX CONTROL REGISTER 0 ARXC0 Configures ARINC 429 receive channel 0

0x8011 R/W ARINC 429 RX CONTROL REGISTER 1 ARXC1 Configures ARINC 429 receive channel 1

0x8012 R/W ARINC 429 RX CONTROL REGISTER 2 ARXC2 Configures ARINC 429 receive channel 2

0x8013 R/W ARINC 429 RX CONTROL REGISTER 3 ARXC3 Configures ARINC 429 receive channel 3

0x8014 R/W ARINC 429 RX CONTROL REGISTER 4 ARXC4 Configures ARINC 429 receive channel 4

0x8015 R/W ARINC 429 RX CONTROL REGISTER 5 ARXC5 Configures ARINC 429 receive channel 5

0x8016 R/W ARINC 429 RX CONTROL REGISTER 6 ARXC6 Configures ARINC 429 receive channel 6

0x8017 R/W ARINC 429 RX CONTROL REGISTER 7 ARXC7 Configures ARINC 429 receive channel 7

0x8018 R/W ARINC 429 TX CONTROL REGISTER 0 ATXC0 Configures ARINC 429 transmit channel 0

0x8019 R/W ARINC 429 TX CONTROL REGISTER 1 ATXC1 Configures ARINC 429 transmit channel 1

0x801A R/W ARINC 429 TX CONTROL REGISTER 2 ATXC2 Configures ARINC 429 transmit channel 2

0x801B R/W ARINC 429 TX CONTROL REGISTER 3 ATXC3 Configures ARINC 429 transmit channel 3

0x801C R/W ARINC 429 TX REPETITION RATE 0 ATXRR0 Sets sequence repeat time for ARINC TX0

0x801D R/W ARINC 429 TX REPETITION RATE 1 ATXRR1 Sets sequence repeat time for ARINC TX1

0x801E R/W ARINC 429 TX REPETITION RATE 2 ATXRR2 Sets sequence repeat time for ARINC TX2

0x801F R/W ARINC 429 TX REPETITION RATE 3 ATXRR3 Sets sequence repeat time for ARINC TX3

0x8020 R/W ARINC 429 Rx INTERRUPT MASK AIMR Enables Interrupts on AINT pin

0x8021 R/W ARINC 429 Rx FIFO THRESHOLD VALUE AFTV Sets flag value for ARINC 429 Receive FIFO

0x8022 R/W ARINC 429 LOOPBACK ALOOP Sets loop-back self-test mode

0x8029 R ARINC 429 Rx FIFO FULL FLAG AFFF Indicates which FIFOs are full

0x802A R ARINC 429 Rx FIFO THRESHOLD FLAG AFTF Indicates which FIFOs hold > (thresh) messages

0x802B R ARINC 429 Rx FIFO NOT EMPTY FLAG FFNE Indicates which receive FIFOs hold data

0x802C R ARINC 429 TX SEQUENCE POINTER 0 ATXSP0 Current address of ARINC transmit sequence 0

0x802D R ARINC 429 TX SEQUENCE POINTER 1 ATXSP1 Current address of ARINC transmit sequence 1

0x802E R ARINC 429 TX SEQUENCE POINTER 2 ATXSP2 Current address of ARINC transmit sequence 2

0x802F R ARINC 429 TX SEQUENCE POINTER 3 ATXSP3 Current address of ARINC transmit sequence 3

0x8030 R/W CAN BUS BIT TIMING REGISTER 0 CANBTR0 Sets bit timing parameters for CAN bus

0x8031 R/W CAN BUS BIT TIMING REGISTER 1 CANBTR1 Sets bit timing parameters for CAN bus

0x8032 R/W CAN TRANSMIT CONTROL REGISTER CANTXC Controls CAN bus transmit scheduler

0x8033 R/W CAN TX REPETITION RATE CANTXRR Sets sequence repeat time for CAN transmitter

0x8034 R/W PENDING INTERRUPT ENABLE REGISTER IMR Enables Interrupts on MINT pin

0x8035 R/W ARINC 429 TX READY INT ENABLE ATRIE Enables ARINC 429 TX Ready Interrupts

0x803E R CAN TX SEQUENCE POINTER MSB CANTXSPH High order CAN transmit sequence counter

0x803F R CAN TX SEQUENCE POINTER LSB CANTXSPL Low order CAN transmit sequence counter

Fast Access Registers * Register is cleared when read (auto clear)

Memory mapped register access only

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

HOLT INTEGRATED CIRCUITS

ADDRESS R/W REGISTER MNEMONIC DESCRIPTION

0x805F R/W PINS ARXBIT[7:0] ARXBIT Values of pins ARXBIT[7:0]

0x8060 R/W PIN ARXBIT0 CONFIG REG 1 ARX0CR1 ARINC 429 bit Monitor 0 channel & bit select

0x8061 R/W PIN ARXBIT0 CONFIG REG 2 ARX0CR2 ARINC 429 bit Monitor 0 label select

0x8062 R/W PIN ARXBIT1 CONFIG REG 1 ARX1CR1 ARINC 429 bit Monitor 1 channel & bit select

0x8063 R/W PIN ARXBIT1 CONFIG REG 2 ARX1CR2 ARINC 429 bit Monitor 1 label select

0x8064 R/W PIN ARXBIT2 CONFIG REG 1 ARX2CR1 ARINC 429 bit Monitor 2 channel & bit select

0x8065 R/W PIN ARXBIT2 CONFIG REG 2 ARX2CR2 ARINC 429 bit Monitor 2 label select

0x8066 R/W PIN ARXBIT3 CONFIG REG 1 ARX3CR1 ARINC 429 bit Monitor 3 channel & bit select

0x8067 R/W PIN ARXBIT3 CONFIG REG 2 ARX3CR2 ARINC 429 bit Monitor 3 label select

0x8068 R/W PIN ARXBIT4 CONFIG REG 1 ARX4CR1 ARINC 429 bit Monitor 4 channel & bit select

0x8069 R/W PIN ARXBIT4 CONFIG REG 2 ARX4CR2 ARINC 429 bit Monitor 4 label select

0x806A R/W PIN ARXBIT5 CONFIG REG 1 ARX5CR1 ARINC 429 bit Monitor 5 channel & bit select

0x806B R/W PIN ARXBIT5 CONFIG REG 2 ARX5CR2 ARINC 429 bit Monitor 5 label select

0x806C R/W PIN ARXBIT6 CONFIG REG 1 ARX6CR1 ARINC 429 bit Monitor 6 channel & bit select

0x806D R/W PIN ARXBIT6 CONFIG REG 2 ARX6CR2 ARINC 429 bit Monitor 6 label select

0x806E R/W PIN ARXBIT7 CONFIG REG 1 ARX7CR1 ARINC 429 bit Monitor 7 channel & bit select

0x806F R/W PIN ARXBIT7 CONFIG REG 2 ARX7CR2 ARINC 429 bit Monitor 7 label select

0x8070 R BIST CONTROL/STATUS BISTS Built-In Self-Test

0x8071 R BIST FAIL ADDRESS [7:0] BISTFL Low-order failing BIST memory address

0x8072 R BIST FAIL ADDRESS [12:8] BISTFH High-order failing BIST memory address

0x8073 R AUTO-INIT FAIL LS ADDRESS [7:0] AIFL Auto-initialization fail address (low-byte)

0x8074 R AUTO-INIT FAIL MS ADDRESS [15:8] AIFH Auto-initialization fail address (high byte)

HI-3200, HI-3201

HI-3200 SYSTEM CONFIGURATION

Bit Name

7 A429RX

6 A429TX

5 CANRX

4 CANTX R/W

3 AFLIP

R/W Default Description

R/W 0 This bit must be set to a “1” to allow the HI-3200 to receive ARINC 429 data on any of the eight

channels. If set to a zero, the HI-3200 will not respond to any ARINC 429 receive bus,

regardless of the state of theARINC 429 Receive channel Control Registers.

R/W 0 This bit must be set to a “1” to allow the HI-3200 to transmit ARINC 429 data on any of the four

channels. If set to a zero, the HI-3200 will not output ARINC 429 data and the ARINC 429

transmit sequencers will remain in their reset state.

R/W 0 This bit must be set to a “1” to allow the HI-3200 to receive CAN Frames from the HI-3110

controller. If set to a zero, the HI-3200 will not respond to any received CAN frames, regardless

of the state of the CAN Bus Control Register.

0 This bit must be set to a “1” to allow the HI-3200 to transmit CAN frames. If set to a zero, the

HI-3200 will not output CAN frames and the CAN transmit sequencer will remain in its reset

state.

R/W 0 When set to a “1”, this bit switches the bit order of the ARINC 429 label byte in both receive and

transmit channels.

R/W 0 Not Used

76543210

MSB LSB

CANTX

AFLIP

CANRX

A429TX

A429RX

MASTER CONTROL REGISTER

(Address 0x800F)

Starting at memory address 0x8000, the HI-3200

contains a set of registers that are used to configure the

HI-3200 device and, if used, its associated HI-3110

integrated CAN controller / transceiver.

The user needs only to program the HI-3200

configuration registers to completely define the full

system operation.

Configuration information for the HI-3110 is automatically

transferred from the HI-3200 to the HI-3110 immediately

after the RUN input is asserted.

The following registers define the HI-3200 top-level configuration:

HI-3200 Global Configuration

An SPI by-pass mode allows the user to directly access

the HI-3110, but it is highly recommended that this is

used solely for design debugging purposes and is locked

out in the final design implementation. By-pass mode is

enabled by setting the state of the MODE2:0 pins during

reset. See the Reset and Start-Up Configuration section

for more details.

The configuration registers are divided into four

categories, as follows;

1. HI-3200 global configuration

2. ARINC 429 Receive channel configuration

3. ARINC 429 Transmit channel configuration

4. CAN Bus bit timing configuration

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

XXX

76543210

MSB LSB

BRP4

BRP3

BRP2

BRP1

BRP0

BRP5

SJW0

SJW1

CANBTR0

(Address 0x8030)

CAN Bus Timing Configuration

CANBTR0 defines the value of the Re-synchronization Jump Width (SJW) and the Baud Rate Prescaler (BRP).

Bit Name

7:6 SJW1:0

5:0 BRP5:0

R/W Default Description

R/W 0 These bits are used to compensate for phase shifts between different oscillators on the CAN

bus. They define the maximum number of time quanta (Tq) a bit can be shortened or

lengthened to allow the node to achieve re-synchronization to the edge of an incoming signal.

Note that the time quantum (Tq) is the single unit of time within a bit time.

R/W 0 The baud rate prescaler relates the HI-3110 OSCIN clock frequency, fosc, to the CAN bit time

as described in the HI-3110 data sheet.

BRP bits <5:0>

000000: BRP=1

000001: BRP=2

000010: BRP=3

000011: BRP=4

etc.

111111: BRP=64

76543210

MSB LSB

TSEG2-0

TSEG1-3

TSEG1-2

TSEG1-1

TSEG1-0

TSEG2-1

TSEG2-2

SAMP

CANBTR1

(Address 0x8031)

CANBTR1 configures the CAN protocol bit timing segments in terms of time quanta (Tq) and sets the number of

sampling points.

Bit Name

7 SAMP

5:0 TSEG2-2:0

R/W Default Description

R/W 0 This bit configures how many samples are taken per bit. 1 = three samples/bit, 0 = one

sample/bit. Bit sampling occurs at the end of Phase Seg 1.

Note: ARINC825 states that there shall be only one sample per bit

R/W 0 Time segment 2 length. Tseg2 = Phase Seg2 of the CAN bit timing specification. Bits

TSEG2-2:0 specify the number of time quanta in Phase Seg2.

Note: Not all combinations are valid, since Phase Seg2 must be greater than SJW.

TSEG2 bits <2:0>

000: Not valid

001: TSeg2 = 2 Tq clock cycles

010: TSeg2 = 3 Tq clock cycles

etc.

111: TSeg2 = 8 Tq clock cycles

Two registers must be programmed to define the CAN

bus data rate and bit sampling segment times. This

information is transferred directly to the HI-3110 CAN

controller’s BTR0 and BTR1 registers following the rising

edge of the RUN input.

The HI-3110 OSCIN clock frequency must be set to

achieve the desired bit rate. The HI-3200 COSC output

signal provides a convenient 24MHz clock source for the

HI-3110. For a full description of CAN Bus timing

requirements, please refer to the Holt HI-3110 data sheet.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

CANBTR1 cont.

Bit Name

5:0 TSEG1-3:0

R/W Default Description

R/W 0 Time segment 1 length. Tseg1 = Prop Seg + Phase Seg 1 of the CAN protocol bit timing

specification. Bits TSEG1-3:0 specify the number of time quanta in Prop Seg + Phase Seg1.

Note: Not all combinations are valid since Prop Seg = Phase Seg1 >= Phase Seg2.

Note ARINC 825 states that the sample point shall not be less than 75% of the bit time. In this

case, TSeg1 should be a minimum of 5Tq for Phase Seg2 (TSeg2) = 2Tq and SJW = 1Tq.

TSEG2 bits <2:0>

0000: Not valid

0001: TSeg1 = 2 Tq clock cycles

0010: TSeg1 = 3 Tq clock cycles

etc.

1111: TSeg1 = 16 Tq clock cycles

The CAN

protocol states that the minimum number of Tq in a bit time shall be 8.

Bit Name

7 READY

6 ACTIVE

5 SAFE

4 RAM BUSY R

3 PROG

2 AUTOINIT

0 HI-3110

R/W Default Description

R 0 This bit is high, when the READY output pin is high, indicating that the part is able to accept and

respond to host CPU SPI commands

R 0 This bit is high after RUN is asserted and the HI-3200 is in normal operating mode.

R 0 This bit goes high when the part enters safe mode as a result of a Built-in Self-test fail or auto-

initialization fail.

0 This is high during the time the RAM Integrity Check is running and RAM is clearing

R 0 Indicates that the HI-3200 is currently in the EEPROM programming cycle. Note that READY

stays low until the cycle is complete.

R 0 The HI-3200 is currently loading internal memory, registers and look-up tables from the Auto-

initialization EEPROM

R 0 Not used

R 0 The HI-3200 has detected the presence of an HI-3110 device connected to the CAN SPI

port. Only valid when RUN = 1 and CANTX and/or CANRX are enabled. After HI-3110

initialization this bit is not updated in Mode 6 or 7.

Note:

76543210

MSB LSB

RAM BUSY

PROG

AUTOINIT

HI-3110

SAFE

ACTIVE

READY

MASTER STATUS REGISTER

(Address 0x800E)

The Master Status Register may be read at any time to determine the current operational state of the HI-3200:

HI-3200 Operational Status Information

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

ARINC 429 Receive Channel Configuration

Each of the eight possible ARINC 429 Receive channels is configured using its own Control Register. Register address

0x8010 controls ARINC 429 Receive channel #0, register address 0x8011 controls channel #1 and so on. ARINC 429

Receive Control Registers may be read at any time, but can only be written when the device is in the IDLE state (RUN

input = “0”, READY output = “1”).

Bit Name

7 ENABLE

6/LO

5 PARITYEN

4 DECODER R/W

3 SD10

2 SD9

1-0 FFS1:0

R/W Default Description

R/W 0 This bit must be set to a “1” to enable ARINC 429 data reception on this channel.

R/W 0 Selects the ARINC 429 bit rate for the ARINC 429 receive channel. A “0” selects high-speed

(100Kb/s) and a “1” selects low-speed (12.5Kb/s).

R/W 0 When this bit is a one, the 32nd received ARINC bit is overwritten with a parity flag. The flag bit

is set to a zero when the received ARINC word, including its parity bit has an odd number of

ones. When PARITYEN is a zero, all 32-bits are received without parity checking.

0 When DECODER is a “1”, bits 9 and 10 of ARINC 429 words received on this channel must

match the SD9 and SD10 bits in the register. ARINC words received that do not match the SD

conditions are ignored.

R/W 0 If DECODER is set to a “1”, then this bit must match the received ARINC word bit 10 for the

word to be accepted.

R/W 0 If DECODER is set to a “1”, then this bit must match the received ARINC word bit 9 for the

word to be accepted.

R/W 0 FFS1 and FFS0 define when this channel’s FIFO Flag is set, as shown below.

76543210

MSB LSB

DECODER

SD10

SD9

FFS1

FFS0

PARITYEN

RATE

ENABLE

ARINC 429 RX CONTROL REGISTER0-7

(Address 0x8010 - 0x8017)

ARINC 429 RECEIVE OPERATION

The HI-3200 can receive ARINC 429 messages from up to eight ARINC 429 receive buses. External

analog line receivers handle the physical layer connection

0 0 FLAG never set

0 1 Set FLAG if FIFO NOT EMPTY bit = “1”

1 0 Set FLAG if FIFO > Threshold value

1 1 Set FLAG is FIFO FULL bit “1”

FFS1 FFS0 FLAG set condition

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

ARINC 429 Received Data Management

The HI-3200 supports eight ARINC 429 receive buses

using on-chip receivers to handle the protocol validation.

The eight ARINC 429 RX Control Registers, ARXC0 - 7,

define the characteristics of each receive channel.

The ARINC 429 receive function of the HI-3200 is acti-

vated by setting the A429RX bit in the Master Control

When an ARINC 429 message is received by the HI-3200

on any bus, it is checked for protocol compliance. Mes-

sages with incorrect encoding are rejected.

The HI-3200 contains an 8K byte memory for storing

ARINC 429 received data. The memory is organized by

channel number and ARINC 429 label value. Four bytes of

memory are dedicated to each channel / label to store the

32-word ARINC 429 message.

A look-up table is used to enable an interrupt on receipt of a

new ARINC 429 message. Look-up table bit positions pre-

loaded with a “1” will cause an Interrupt to be generated.

When a message is received that triggers an Interrupt, that

channel’s Interrupt bit is set in the ARINC 429 Receive

Pending Interrupt Register. If this bit is unmasked in the

ARINC 429 Receive Interrupt Mask Register, the AINT

output pin is asserted. The label number of the ARINC 429

message causing the interrupt is loaded into that chan-

nel’s ARINC 429 Receive Interrupt Address Register

(AIAR0 - AIAR7).

Because the ARINC Receive Memory is organized by

label value, it is not necessary to store the received label

value (first eight bits of the ARINC message) in the

memory. Instead, the first byte is used to store a status

byte.

The six active bits of the status byte are set to “1” when a

new ARINC word is stored in the memory. These bits flag

the ARINC word as new when the location is interrogated

by the host CPU, any of the four ARINC 429 transmit

schedulers or the CAN Bus transmit scheduler.

ARINC 429 Received Data Memory Organization

Block 1

Channel 0, Label 00

Block 2

Channel 0, Label 01

Block 3

Channel 0, Label 02

Block 2048

Channel 7, Label FF

Status Byte

ARINC data byte 2

ARINC data byte 3

ARINC data byte 4

0x0000 0x0000

0x0003

0x0004

0x0007

0x0008

0x000B

0x1FFC

0x1FFF

0x0001

0x0002

0x0003

Etc.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Bit Name

5 NEWHOST

4 NEWCAN R/W

3 NEW

2 NEW

1 NEW

0 NEW

R/W Default Description

R/W 0 Not used

R/W 0 This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when

the host CPU executes SPI instruction 0xC0 - 0xFF to read the block.

0 This bit is set when a new ARINC 429 word is received and stored in this block.It is reset when

the CAN Transmit scheduler reads any bytes from the block.

TX3 R/W 0 This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when

theARINC 429 Transmit scheduler #3 reads any bytes from the block.

TX2 R/W 0 This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when

theARINC 429 Transmit scheduler #2 reads any bytes from the block.

TX1 R/W 0 This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when

theARINC 429 Transmit scheduler #1 reads any bytes from the block.

TX0 R/W 0 This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when

theARINC 429 Transmit scheduler #0 reads any bytes from the block.

76543210

MSB LSB

NEWCAN

NEWTX3

NEWTX2

NEWTX1

NEWTX0

NEWHOST

STATUS BYTE

ARINC 429 Received Data Status Byte Definition

ARINC 429 Received Data Interrupt Look-Up Table

Interrupt Look-Up Table

Channel 0

Interrupt Look-Up Table

Channel 1

Interrupt Look-Up Table

Channel 7

76543210

0x7B00

0x7B1F

0x7B20

0x7B3F

0x7BE0

0x7BFF

Label = 0x00

Label = 0x01

Label = 0x07

Label = 0x08

Label = 0x0F

Label = 0xFF Label = 0xF8

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

ARINC 429 Received Data Log FIFO

A 1K x 8 block of memory located between 0x3000 and

0x33FF is reserved for a set of eight ARINC 429 received

data FIFOs. There is one FIFO for each ARINC 429

received data channel. Each FIFO can hold up to 32 ARINC

429 32-bit messages.

A look-up table driven filter defines which ARINC 429

messages are stored in each FIFO. The look-up table is

pre-loaded with a “1” for each bit position corresponding to

a selected channel / label combination. The look-up table is

located at memory address 0x7A00.

When a new ARINC 429 message is received that meets

the programmed conditions for acceptance (Enable look-

up table bit = “1”), it is written into the channel’s Receive

Data FIFO. The contents of the FIFO may be read by the

host CPU using dedicated FIFO read SPI Instructions.

The status of each channel’s FIFOs is monitored by three

FIFO status registers: FIFO NOT EMPTY, FIFO

THRESHOLD, and FIFO FULL. One bit of each register

reflects the current status of each FIFO.

The FIFOs are empty following Reset. All three status

registers are cleared. When an ARINC 429 message is

written to a FIFO, its FIFO NOT EMPTY bit is set to a “1”.

When the FIFO contains more than the user-defined

number of messages as programmed in the ARINC FIFO

THRESHOLD VALUE register, its FIFO THRESHOLD bit is

set. If the FIFO is allowed to accumulate 32 messages, its

FIFO FULL bit is set. Once a FIFO is full, subsequent

messages continue to be written to the FIFO, and the oldest

message is lost.

The user may generate an Interrupt by enabling one of the

three FIFO status register bits to assert the FLAG bit in the

Pending Interrupt Register. ARINC 429 Control Register

bits 1:0 select the condition to trigger the FLAG interrupt.

The FIFO feature is particularly useful if the application

wishes to accumulate sequential ARINC 429 messages of

the same label value before reading them. The regular

ARINC 429 receive data memory will, of course, overwrite

messages of the same label value if a new message is

received before the host CPU extracts the data.

ARINC 429 Received Data FIFO (x8)

Data read by

Host CPU

SPI Instruction

ARINC 429

received

message

Message 1 (32-bits)

Message 2 (32-bits)

0 - 32 Messages (32-bits)

A FNEn

AFHFn

A FFn

Select FLAGn

FIFO NOT EMPTY

FIFO THRESHOLD

FIFO FULL

ARXCn <1:0>

OR PIR

FLAG

}

From

Other

Channels

ARINC 429 Received Data Enable Look-Up Table

Filter Look-Up Table

Channel 0

Filter-Look-Up Table

Channel 1

Filter Look-Up Table

Channel 7

76543210

0x7A00

0x7A1F

0x7A20

0x7A3F

0x7AE0

0x7AFF

Label = 0x00

Label = 0x01

Label = 0x07

Label = 0x08

Label = 0x0F

Label = 0xFF Label = 0xF8

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Bit Name

7 AFNE7

6 AFNE6

5 AFNE5

4 AFNE4 R

3 AFNE3

2 AFNE2

1 AFNE

0 AFNE

R/W Default Description

R 0 This bit is set to “1” if FIFO #7 contains at least one ARINC 429 message

R 0 This bit is set to “1” if FIFO #6 contains at least one ARINC 429 message

R 0 This bit is set to “1” if FIFO #5 contains at least one ARINC 429 message

0 This bit is set to “1” if FIFO #4 contains at least one ARINC 429 message

R 0 This bit is set to “1” if FIFO #3 contains at least one ARINC 429 message

R 0 This bit is set to “1” if FIFO #2 contains at least one ARINC 429 message

1 R 0 This bit is set to “1” if FIFO #1 contains at least one ARINC 429 message

0 R 0 This bit is set to “1” if FIFO #0 contains at least one ARINC 429 message

76543210

MSB LSB

AFNE4

AFNE3

AFNE2

AFNE1

AFNE0

AFNE5

AFNE6

AFNE7

FIFO NOT EMPTY REGISTER

(Address 0x802B)

ARINC 429 Received Data FIFO Status Registers

Bit Name

7 AFTF7

6 AFTF6

5 AFTF5

4 AFTF4 R

3 AFTF3

2 AFTF2

1 AFTF

0 AFTF

R/W Default Description

R 0 This bit is set to “1” if FIFO #7 contains > threshold number of ARINC 429 messages

R 0 This bit is set to “1” if FIFO #6 contains > threshold number of ARINC 429 messages

R 0 This bit is set to “1” if FIFO #5 contains > threshold number of ARINC 429 messages

0 This bit is set to “1” if FIFO #4 contains > threshold number of ARINC 429 messages

R 0 This bit is set to “1” if FIFO #3 contains > threshold number of ARINC 429 messages

R 0 This bit is set to “1” if FIFO #2 contains > threshold number of ARINC 429 messages

1 R 0 This bit is set to “1” if FIFO #1 contains > threshold number of ARINC 429 messages

0 R 0 This bit is set to “1” if FIFO #0 contains > threshold number of ARINC 429 messages

76543210

MSB LSB

AFTF4

AFTF3

AFTF2

AFTF1

AFTF0

AFTF5

AFTF6

AFTF7

FIFO THRESHOLD REGISTER

(Address 0x802A)

Bit Name

7 AFFF7

6 AFFF6

5 AFFF5

4 AFFF4 R/W

3 AFFF3

2 AFFF2

1 AFFF

0 AFFF

R/W Default Description

R/W 0 This bit is set to “1” if FIFO #7 contains 32 ARINC 429 messages

R/W 0 This bit is set to “1” if FIFO #6 contains 32 ARINC 429 messages

R/W 0 This bit is set to “1” if FIFO #5 contains 32 ARINC 429 messages

0 This bit is set to “1” if FIFO #4 contains 32 ARINC 429 messages

R/W 0 This bit is set to “1” if FIFO #3 contains 32 ARINC 429 messages

R/W 0 This bit is set to “1” if FIFO #2 contains 32 ARINC 429 messages

1 R/W 0 This bit is set to “1” if FIFO #1 contains 32ARINC 429 messages

0 R/W 0 This bit is set to “1” if FIFO #0 contains 32ARINC 429 messages

76543210

MSB LSB

AFFF4

AFFF3

AFFF2

AFFF1

AFFF0

AFFF5

AFFF6

AFFF7

FIFO FULL REGISTER

(Address 0x8029)

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Threshold Value Description

00000 Threshold flag is set if at least 1 message is in FIFO (Same as FIFO NOT EMPTY FLAG)

00001 Threshold flag is set if more than one message are in the FIFO

00010 Threshold flag is set if more than two messages are in the FIFO

00011 Threshold flag is set if more than three messages are in the FIFO

10000 Threshold flag is set if more than sixteen messages are in the FIFO (default)

11111 Threshold flag is set if 32 messages are in the FIFO (Same as FIFO FULL FLAG)

76543210

MSB LSB

FIFO THRESHOLD VALUE

(Address 0x8021)

ARINC 429 FIFO Threshold Value Register

Threshold

000

ARINC 429 Loop-back Self-Test

The HI-3200 includes an ARINC 429 loop-back feature,

which allows users to exercise the ARINC 429 transmit and

receive channels for self-test purposes. The ARINC 429

Loop-Back register, ALOOP defines which receiver

channels are in loop-back mode. When a “1” is

programmed in the ALOOP bit position for a receiver, then

its ARINC 429 bus connection to the external pins is broken

and instead the input is connected to one of the four ARINC

429 transmit channels. Transmit channel 0 is connected to

receive channel 0 and 1, transmit channel 1 is connected to

receive channels 2 and 3, and so on.

When in loop-back mode, incoming ARINC 429 messages

are ignored by the HI-3200. When running in loop-back

mode the ARINC 429 transmit pins may be disabled by

pulling the TXMSK input high. This prevents test messages

from being output to the external ARINC 429 transmit

buses.

Bit Name

7 ALOOP7

6A 6

5A 5

4 A 4 R/W

3A 3

2A 2

R/W Default Description

R/W 0 This bit is set to “1” to loop-back transmit channel 3 to receiver 7

LOOP R/W 0 This bit is set to “1” to loop-back transmit channel 3 to receiver 6

LOOP R/W 0 This bit is set to “1” to loop-back transmit channel 2 to receiver 5

LOOP 0 This bit is set to “1” to loop-back transmit channel 2 to receiver 4

LOOP R/W 0 This bit is set to “1” to loop-back transmit channel 1 to receiver 3

LOOP R/W 0 This bit is set to “1” to loop-back transmit channel 1 to receiver 2

LOOP1 R/W 0 This bit is set to “1” to loop-back transmit channel 0 to receiver 1

LOOP0 R/W 0 This bit is set to “1” to loop-back transmit channel 0 to receiver 0

76543210

MSB LSB

ALOOP4

ALOOP3

ALOOP2

ALOOP1

ALOOP0

ALOOP5

ALOOP6

ALOOP7

ARINC 429 LOOPBACK

(Address 0x8022)

HOLT INTEGRATED CIRCUITS

Default = 0x10

HI-3200, HI-3201

ARINC 429 Bit ordering

ARINC 429 messages consist of a 32-bit sequence as

shown below. The first eight bits that appear on the ARINC

429 bus are the label byte. The next twenty three bits

comprise a data field which presents data in a variety of

formats defined in the ARINC 429 specification. The last bit

transmitted is an odd parity bit.

The HI-3200 stores the received message as four bytes.

The bytes are stored in memory in little-endian order. That

is to say, the label byte (or status byte) is stored at the

lowest memory address, the byte representing received

bits 9 through 16 is stored at the next address, the byte

representing bits 17 through 24 at the next address and the

byte representing bits 25 though 32 at the highest address.

The ARINC 429 specifies the MSB of the label as ARINC bit

1. Conversely, the data field MSB is bit 31. So the bit

significance of the label byte and data fields are opposite.

The HI-3200 may be programmed to “flip” the bit ordering of

the label byte as soon as it is received and immediately prior

to transmission. This is accomplished by setting the AFLIP

bit to a “1” in the Master Control Register. Note that once the

label byte has been flipped, the HI-3200 handles the flipped

data byte “post-flip” for the purpose of label interrupt

matching, filtering and storage.

21 8

LSB

ARINC 429 Message as received / transmitted on the ARINC 429 serial bus

910

11 12 13 14 15 16

SDI

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PARITY

LABEL DATA

MSB LSB MSB

time

21 8

16 15 14 13 12 11 10 9

24 23 22 21 20 19 18 17

32 31 30 29 28 27 26 25

7654321

ARINC 429 Message as stored in HI-3200 memory

Byte 0

Byte 1

Byte 2

Byte 3

AFLIP = “0” AFLIP = “1”

16 15 14 13 12 11 10 9

24 23 22 21 20 19 18 17

32 31 30 29 28 27 26 25

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

HOLT INTEGRATED CIRCUITS

ARINC 429 Bit Monitor Pins

76543210

MSB LSB

ARXBIT4

ARXBIT3

ARXBIT2

ARXBIT1

ARXBIT0

ARXBIT5

ARXBIT6

ARXBIT7

PINS ARXBIT[7:0] REGISTER

(Address 0x805F)

Bit Name

7:0 ARXBIT[7:0]

R/W Default Description

R/W 0 These bits reflect the value of the corresponding pins ARXBIT[7:0]. After reset, all values are

zero. When a monitored ARINC 429 bit changes, this register is updated with the value, which

is reflected on the corresponding pin. The purpose of this register is to allow the user to preset

the ARXBIT values after chip reset.

76543210

MSB LSB

ARXCR14

ARXCR13

ARXCR12

ARXCR11

ARXCR10

ARXCR15

ARXCR16

ARXCR17

PIN ARXBIT0 CONFIGURATION REGISTER 1

(Address 0x8060)

Bit Name

7:5 ARXCR1[7:5]

R/W Default Description

R/W 0 These bits select which receive channel (0 through 7) will have bits monitored and reflected on

the pinARXBIT0.

4:0 ARXCR1[4:0] R/W 0 These bits select which bit (8 through 31) of the ARINC payload will be reflected on the pin

ARXBIT0. The receiver is specified by bits ARX0CR1[7:5] and the target label is specified

by pin ARXBIT0 Configuration Register 2 described below. Note that bits 0 through 7 of the

ARINC payload are not monitored and selecting these bits results in no effect.

76543210

MSB LSB

ARXCR24

ARXCR23

ARXCR22

ARXCR21

ARXCR20

ARXCR25

ARXCR26

ARXCR27

PIN ARXBIT0 CONFIGURATION REGISTER 2

(Address 0x8061)

Bit Name

7:0 ARXCR2[7:0]

R/W Default Description

R/W 0 These bits select which label (0 through 255) will have bits monitored and reflected on

the pin ARXBIT0. The receive channel and specific bits monitored are specified in ARXBIT0

Configuration Register 1 described above.

Each pin ARXBIT1 through ARXBIT7 are also specified by a pair of configuration registers similar to ARXBIT0 described above.

Functionality is exactly the same. The register addresses for each pin specification are listed in the Register Map section (see page

11). Note that HI-3200 provides external monitoring of two bits through pins ARXBIT1 and ARXBIT0, whereas the HI-3201 provides

external monitoring of eight bits through pinsARXBIT7 toARXBIT0.

PINS ARXBIT1 Through ARXBIT7 CONFIGURATION REGISTERS

(Addresses 0x8062 to 0x806F)

HI-3200, HI-3201

The HI-3200 has the capability of externally monitoring any

ARINC 429 received payload bit through the pins

ARXBIT[7:0] ( The HI-3200 provides external

monitoring of two bits through pins ARXBIT1 and ARXBIT0,

whereas the HI-3201 provides external monitoring of eight

bits through pins ARXBIT7 to ARXBIT0). When the

appropriate ARINC 429 receiver is enabled and the target

label is received, the monitored bit value will be reflected on

the pin. This allows the user to monitor any ARINC 429

Note:

received payload bit without performing any host SPI reads.

The following registers configure the functionality of these

monitor pins. Note that all these control register bits are

RESET to zero.

CAN Received Data Management

The HI-3200 interfaces to a CAN bus using an external HI-

3110 CAN Controller / Transceiver IC. Communication

between the HI-3200 and HI-3110 is handled by a

dedicated high speed serial SPI link. Configuration

parameters are automatically downloaded to the HI-3110

following a positive edge of the RUN input signal.

The HI-3110 handles all aspects of the CAN protocol as well

as the physical layer interface to the CAN bus.

Received CAN frames are passed to the HI-3200 for

filtering and storage. Each incoming frame’s ID and first two

data bytes is compared against a bank of up to 256 user-

defined acceptance filters. If the frame meets the filter’s

acceptance criteria, it is stored in the CAN Received Data

Memory. Each acceptance filter consists of a 6-byte match

unmasked bits match the corresponding bits in the frame.

The frame is then written into the CAN received data

memory location corresponding to the filter number.

Mask bits are defined as 1 = care and 0 = don’t care. So for

any given CAN frame bit to generate a filter pass condition,

the received frame bit must equal the filter bit if the mask bit

is “1”, or any value if the mask bit is “0”.

The number of filters active at any time is specified by

writing a “1” into the corresponding bit position of the CAN

Filter Enable look-up table. Only those filters identified as

active in the table will be used to determine whether the

frame is accepted.

A CAN Receive Interrupt look-up table mirrors the active

filter table. When a frame is accepted, and its

corresponding Interrupt enable look-up bit is a one, then the

CAN Interrupt bit is set in the Pending Interrupt Register. If

the Interrupt Mask Register does not mask the CAN

Interrupt, then the INT output signal will be asserted on

frame reception and the CAN filter number will be loaded

into the Interrupt Address Register.

It is possible that a received CAN frame may meet the

acceptance criteria for more than one filter. In this case,

only the first (lowest filter number) filter is used to qualify

and store the incoming CAN frame.

The CAN Filter Enable look-up table, CAN Interrupt Enable

look-up table, Filter and Mask definition tables must be

loaded prior to turning on the CAN receiver, either via the

host CPU interface or from the auto-initialization EEPROM.

CAN frames are stored as sixteen-byte blocks as shown in

the following diagram. Each block starts with a CAN frame

Status Byte.

CAN Bus Received Data Filter Enable Look-Up Table

CAN Bus Received Data Filter

Enable Look-Up Table

76543210

Filter 0x00

Filter 0x01

Filter 0x07

Filter 0x08

Filter 0x0F

Filter 0xFF Filter 0xF8

76543210

0x79C0

0x79DF

Filter 0x00

Filter 0x01

Filter 0x07

Filter 0x08

Filter 0x0F

Filter 0xFF Filter 0xF8

CAN BUS RECEIVE OPERATION

The HI-3200 can receive CAN frames from a single CAN bus using an external HI-3110 IC to handle the CAN bus

protocol and physical layer connection

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

CAN Received Data Filter, Filter Mask and Data Storage Organization

CAN

RECEIVE

DATA

RAM

(4Kx8)

CAN

FILTER

Block 0

Filter 0 Frame

Block 1

Filter 1 Frame

Block 2

Filter 2 Frame

Block 255

Filter 255 Frame

CAN Frame Status Byte

Time Tag Upper Byte

Time Tag Lower Byte

ID28 to ID21

CAN

FILTER / MAP

TABLE

(3072 x 8)

CAN data byte 7

CAN data byte 6

CAN data byte 5

CAN data byte 4

CAN data byte 3

CAN data byte 2

CAN data byte 1

r0, r1,DLC3 to DLC0

ID20 to ID18, SRR, IDE, ID17 to ID15

ID14 to ID7

ID6 to ID0, RTR

CAN data byte 8

0x2000

Acceptance Filter 0

Mask 0

Acceptance Filter 1

0x3400

Mask 1

Acceptance Filter 2

Mask 2

Acceptance Filter 255

Mask 255

ID28 to ID21

CAN data byte 2

CAN data byte 1

ID20 to ID18, SRR, IDE, ID17 to ID15

ID14 to ID7

ID6 to ID0, RTR

ID28 to ID21

CAN data byte 2

CAN data byte 1

ID20 to ID18, SRR, IDE, ID17 to ID15

ID14 to ID7

ID6 to ID0, RTR

0x200F

0x2010

0x201F

0x2020

0x202F

0x2FF0

0x2FFF

0x3406

0x340C

0x3412

0x3418

0x341E

0x3FF4

0x3FFF

CAN Bus Received Data Interrupt Enable Look-Up Table

CAN Bus Received Data Interrupt

Enable Look-Up Table

76543210

0x79E0

0x79FF

Filter 0x00

Filter 0x01

Filter 0x07

Filter 0x08

Filter 0x0F

Filter 0xFF Filter 0xF8

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Bit Name

5 NEWHOST

4 NEWCAN R/W

3 NEW

2 NEW

1 NEW

0 NEW

R/W Default Description

R/W 0 Not used

R/W 0 This bit is set when a new CAN frame is received and stored in this block. It is reset when

the host CPU executes SPI instruction 0x9C to read the block.

0 This bit is set when a new CAN frame is received and stored in this block. It is reset when

the CAN Transmit scheduler reads any bytes from the block.

TX3 R/W 0 This bit is set when a new CAN frame is received and stored in this block. It is reset when

theARINC 429 Transmit scheduler #3 reads any bytes from the block.

TX2 R/W 0 This bit is set when a new CAN frame is received and stored in this block. It is reset when

theARINC 429 Transmit scheduler #2 reads any bytes from the block.

TX1 R/W 0 This bit is set when a new CAN frame is received and stored in this block. It is reset when

theARINC 429 Transmit scheduler #1 reads any bytes from the block.

TX0 R/W 0 This bit is set when a new CAN frame is received and stored in this block. It is reset when

theARINC 429 Transmit scheduler #0 reads any bytes from the block.

76543210

MSB LSB

NEWCAN

NEWTX3

NEWTX2

NEWTX1

NEWTX0

NEWHOST

CAN RECEIVED DATA BLOCK STATUS BYTE

CAN Bus Received Data Status Byte Definition

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

ARINC 429 Transmit Channel Configuration

Each of the four available ARINC 429 Transmit channels is configured using its own register. Register address 0x8018

controls ARINC 429 Transmit channel #0, register address 0x8019 controls channel #1 and so on. The ATXCn

registers may be written or read at any time.

ARINC 429 TX CONTROL REGISTER0-3

(Address 0x8018 - 0x801B) 76543210

MSB LSB

EVEN / ODD

SKIP

PARITY / DATA

HI / LO

RUN / STOP

Bit Name

7 RUN /

6/LO

5 PARITY /

4 EVEN / R/W

3 SKIP

R/W Default Description

STOP

DATA

ODD

R/W 0 When zero, transmission from this ARINC 429 transmit channel is suspended after the

currently transmitting label is sent. When this bit is taken high, transmission starts at the

beginning of the descriptor table for this channel.

R/W 0 Selects the transmission rate for the ARINC 429 transmit channel. A “0” selects high-speed

(100Kb/s) and a “1” selects low-speed (12.5Kb/s).

R/W 0 When this bit is a one, the 32nd transmitted ARINC bit is overwritten with a parity flag. When

this bit is a zero, all 32-bits are transmitted as data.

0 When PARITY / DATA is a “1”, this bit defines whether th 32nd transmitted bit is set for Even or

Odd Parity. A“1” selects even parity and a “0” selects odd parity.

R/W 0 When set a “1’ instructs the transmit sequencer to wait for the next Repetition Rate Counter

rollover before beginning a new transmission cycle. A “0” causes an immediate restart of the

cycle following completion of the prior cycle.

R/W 0 Not Used

ARINC 429 TRANSMIT OPERATION

The HI-3200 has four on-board ARINC 429 transmit channels which directly drive ARINC 429 differential line drivers

such as the Holt HI-8570. ARINC 429 words may be written to the transmitters either directly, using an SPI instruction,

or be generated automatically using the four ARINC 429 message schedulers.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

XXX

ARINC 429 Transmit Scheduler

Each of the four ARINC 429 transmit channels has its

own transmit controller. The controller is user-

programmed to output ARINC labels in a predefined

order and repetition rate. A sequence of up to 256 ARINC

labels may be transmitted before repeating the sequence.

A descriptor table with up to 256 entries (descriptors) is

compiled by the user to define the sequence of ARINC

429 messages transmitted on each channel. When the

RUN/ bit in the ARINC TX Control Register is

asserted, the controller compiles the first 32-bit ARINC

word from the instructions given by the first descriptor

and then transmits it. A Transmit Sequence Pointer then

increments to the next descriptor in the table and the

process is repeated for Descriptor number 2.

ARINC 429 messages continue to be compiled and

transmitted until the last descriptor in the table. The end

of the table is marked by a special descriptor if not all 256

entries are needed. The Sequence Pointer is then reset

to zero.

A Repetition Rate Counter is used to time the start of the

next transmission cycle.

STOP

The user is responsible for construction of the descriptor

table and for setting the Repetition Rate prior to asserting

RUN/STOP. Facilities exist for immediate cycle repetition

and for single-cycle operation.

The byte content of each ARINC 429 message

transmitted is user defined by the descriptor contents.

Data bytes may be sourced from the host CPU / auto-

initialization EEPROM (immediate data) or from the

ARINC 429 receive memory (ARINC indexed) or CAN

bus receiver memory (CAN indexed). This allows

received ARINC data to be re-transmitted on another bus

with or without filtering, label byte re-assignment or data

modification. It allows data received on the CAN bus to

be re-formatted and re-labelled for automatic ARINC 429

transmission. It also allows data from multiple ARINC 429

receive buses and the CAN bus to be re-packetized into

new ARINC 429 transmitted messages.

Conditional transmission control allows sequenced words

to be skipped if no new data is available.

Each ARINC 429 transmit channel is independently

configured with its own ARINC 429 TX Control Register,

ATXCR0-3, as previously described.

ARINC 429 Transmit Descriptor table

Sequence 0 Descriptor Frame

0x4000

Action Byte 1

Repetion Rate

Repetition rate

counter

Sequence

pointer 000

Sequence 1 Descriptor Frame

Sequence 2 Descriptor Frame

Sequence 3 Descriptor Frame

Sequence 4 Descriptor Frame

Sequence 5 Descriptor Frame

Sequence 254 Descriptor Frame

Sequence 255 Descriptor Frame

Value Byte 1

Action Byte 2

Action Byte 3

Action Byte 4

Value Byte 2

Value Byte 3

Value Byte 4

0x4008

0x4010

0x4018

0x4020

0x4028

0x47F0

0x47F8

0x47FF

(Memory Addresses shown

for ARINC Tx channel 0)

The value of each ARINC 429 label transmitted in the

sequence is defined by its eight-byte descriptor. The

descriptor consists of one “Action byte” and one “Value”

byte for each of the four bytes that make up the ARINC

429 transmitted label.

The four pairs of Action and Value bytes describe where

the data for each byte may be found. Different op-codes

allow the data source to be host CPU populated fixed

values, or values from specific locations within the ARINC

429 receive memory or CAN bus receive memory. Action

byte 1 also has one additional op-code to facilitate

sequence flow control.

The construction of Action and Value bytes are described in

the next section.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

76543210

MSB LSB

TRANSMIT SEQUENCE POINTERS 0 -3

(Address 0x802C - 0x802F)

Current Sequence number

76543210

MSB LSB

REPETITION RATE REGISTER

(Address 0x801C - 0x801F)

Channel Repetition Period

The transmit sequence pointer is set to zero on Master

Reset. Once the Control Register RUN / bit goes

high, sequence execution begins at sequence count

zero. After the first word is sent, the pointer is

incremented by one descriptor (counts descriptor

frames).

STOP

This continues until the programmed sequence is

complete. The sequence pointer is then reset to the

beginning of the descriptor table and program execution

begins as soon the channel repetition rate counter time

elapses.

The Repetition rate register value defines the time

interval between successive starts of the programmed

transmit sequence for each ARINC 429 transmit channel.

The value is set in binary, with the LSB representing 10

ms. Repetition rate time periods may therefore be set

from 0 ms to 2.55 seconds

If the repetition rate is shorter than the minimum time

needed to transmit all ARINC 429 words in the sequence

(but not zero), the transmit sequence will begin again

immediately if the Control Register SKIP bit is a zero. If

the SKIP bit is a one, the sequencer will wait until the

next rollover of the Repetition Rate Counter before

starting a new cycle.

When the Repetition Rate counter is programmed to zero

(default), the transmit sequence shall execute one time

only. A zero - to - one transition of the RUN/STOP bit will

cause the transmit sequence to start. One-time execution

of the sequencer is useful when transmitting ARINC 429

words directly from the host CPU. One or more

immediate-mode descriptors can be written into the

sequence table, transmitted, and then refreshed for the

next cycle.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

ARINC 429 BYTE 1 DESCRIPTOR

76543210

MSB LSB

Index

Index ValueOp-Code Description

000 XXXXX XXXXXXXX End of sequence. When op-code 000 is encountered by the sequencer

before it reaches sequence number 255, the sequencer resets to zero and

begins the next transmission cycle starting at descriptor number 0 as soon

as the repitition rate counter rolls over. Note that the descriptor table is

cleared following Master Reset, so no ARINC 429 transmissions are

possible until the sequence table has been configured.

001 XXXXX XXXXXXXX No-operation. This descriptor is ignored and the sequencer increments to

the next descriptor in the sequence. This opcode may be used to temporarily

suspend transmission of a particular message in the sequence, without

having to modify the remaining bit fields of the descriptor or reloading the

entire descriptor block in order to delete the entry.

010 XXXXX LLLLLLLL Immediate data. The value contained in the descriptor value data byte is

loaded into byte 1 (the ARINC 429 “label” byte) of the ARINC

429 label to be transmitted.

011 CCCXX LLLLLLLL Immediate data conditional. The NEWTXn bit corresponding to the ARINC

Data RAM location defined by channel “CCC” and label block “LLLLLLLL” is

read. LLLLLLLL is used as Byte 1 if NEWTXn is set for this

within this descriptor frame. If NEWTXn = 0 for all

conditional op codes (within this descriptor frame) then no transmission

occurs for this frame and the sequencer increments to the next descriptor

frame. The NEWTXn bit for the referencedARINC RAM block is reset.

100 CCCBB LLLLLLLL Indexed data. The value of ARINC Data RAM location defined by channel

“CCC”, label block “LLLLLLLL” and byte number “BB” is loaded into byte 1 of

theARINC 429 label to be transmitted.

101 CCCBB LLLLLLLL Indexed data conditional. The NEWTXn bit corresponding to the ARINC

Data RAM location defined by channel “CCC”, label block “LLLLLLLL” and

byte number “BB” is read. The corresponding byte is used as Byte 1 if

NEWTXn is set for this within this

descriptor frame. If NEWTXn = 0 for all conditional op codes (within this

descriptor frame) then no transmission occurs for this frame and the

sequencer increments to the next descriptor frame. The NEWTXn bit for the

referencedARINC RAM block is reset.

110 XBBBB NNNNNNNN CAN byte. The value of the byte at CAN RAM address filter block

“NNNNNNNN”, byte number “BBBB” is loaded into the ARINC buffer byte 1

position to be transmitted.

111 XBBBB NNNNNNNN CAN byte conditional. The NEWTXn bit corresponding to the CAN RAM

address filter block “NNNNNNNN”, byte number “BBBB” is read. The

corresponding byte is used as Byte 1 if NEWTXn is set for this

within this descriptor frame. If NEWTXn = 0 for all

conditional op codes (within this descriptor frame) then ARINC word

construction is terminated, no transmission occurs for this frame and the

sequencer increments to the next descriptor frame. The NEWTXn bit for the

referenced CAN RAM address filter block is reset.

or any other

conditional opcode

or any other conditional opcode

or any other

conditional opcode

76543210

MSB LSB

Value

Op-Code

ACTION BYTE VALUE BYTE

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Index Value

000

Op-Code Description

XXXXX XXXXXXXX No-Op op-code. ARINC 429 word construction will be terminated and the

sequencer will move on to the next descriptor in the table.

001 XXXXX XXXXXXXX No-Op op-code. ARINC 429 word construction will be terminated and the

sequencer will move on to the next descriptor in the table.

010 XXXXX LLLLLLLL Immediate data. The value contained in the descriptor value data byte is

loaded into this byte position of the ARINC 429 32-bit message to be

transmitted.

011 CCCXX LLLLLLLL Immediate data conditional. The NEWTXn bit corresponding to the ARINC

Data RAM location defined by channel “CCC” and label block “LLLLLLLL” is

read. LLLLLLLL is used if NEWTXn is set for this

within this descriptor frame. If NEWTXn = 0 for all

conditional op codes (within this descriptor frame) then no transmission

occurs for this frame and the sequencer increments to the next descriptor

frame. The NEWTXn bit for the referencedARINC RAM block is reset.

100 CCCBB LLLLLLLL Indexed data. The value of ARINC Data RAM location defined by channel

“CCC”, label block “LLLLLLLL” and byte number “BB” is loaded into this byte

position of theARINC 429 label to be transmitted.

101 CCCBB LLLLLLLL Indexed data conditional. The NEWTXn bit corresponding to the ARINC

Data RAM location defined by channel “CCC”, label block “LLLLLLLL” and

byte number “BB” is read. The corresponding byte is used if

NEWTXn is set for this within this

descriptor frame. If NEWTXn = 0 for all conditional op codes (within this

descriptor frame) then no transmission occurs for this frame and the

sequencer increments to the next descriptor frame. The NEWTXn bit for the

referencedARINC RAM block is reset.

110 XBBBB NNNNNNNN CAN byte. The value of the byte at CAN RAM address filter block

“NNNNNNNN”, byte number “BBBB” is loaded into the ARINC buffer byte

position to be transmitted.

111 XBBBB NNNNNNNN CAN byte conditional. The NEWTXn bit corresponding to the CAN RAM

address filter block “NNNNNNNN”, byte number “BBBB”

is read. The corresponding byte is used if NEWTXn is set for this

within this descriptor frame. If NEWTXn = 0 for

all conditional op codes (within this descriptor frame) then ARINC word

construction is terminated, no transmission occurs for this frame and the

sequencer increments to the next descriptor frame. The NEWTXn bit for the

referenced CAN RAM address filter block is reset.

or any other

conditional opcode

or any other conditional opcode

or any

other conditional opcode

ARINC 429 BYTES2-4DESCRIPTOR

76543210

MSB LSB

Index

76543210

MSB LSB

Value

Op-Code

ACTION BYTE VALUE BYTE

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

ARINC 429 Immediate Transmit Option

The Host CPU may instruct the HI-3200 to transmit an

ARINC 429 message immediately using a special SPI

command. The SPI command selects the transmit

channel and provides the four bytes of data to be sent as

a 32-bit ARINC 429 message.

If the transmit channel’s sequencer is not running (ATCR

bit RUN/ = “0”), or the sequencer is waiting for the

repetition rate counter to rollover, then the new ARINC

429 message is transmitted without delay.

STOP

If the transmit sequencer for the selected channel is

active, then the new message is transmitted as soon as

the current message has been sent. The sequencer then

resumes operation at the next location in the queue.

Both the RUN input and the Master Control Register

A429TX bit must be high to enable any ARINC 429

transmission.

Table 1 lists the host CPU SPI instruction format.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

CAN BUS Transmit Scheduler

Bit Name

7 RUN /

6 SKIP

5 COSC_MASK

4 - R/W

R/W Default Description

STOP R/W 0 When zero, transmission from the CAN Bus transmit channel is suspended after the

currently transmitting frame is sent. When this bit is taken high, transmission starts at the

beginning of the descriptor table.

R/W 0 When set to “1” instructs the transmit sequencer to wait for the next Repetition Rate Counter

rollover before beginning a new transmission cycle. A “0” causes an immediate restart of the

cycle following completion of the prior cycle.

R/W 0 When set to “1” this bit masks off the COSC pin.

0 Not Used

R/W 0 Not Used

76543210

MSB LSB

COSC_MASK

SKIP

RUN / STOP

CAN TRANSMIT CONTROL REGISTER

(Address 0x8032)

76543210

MSB LSB

CAN TRANSMIT SEQUENCE POINTER

(Address 0x803E/F)

Current Sequence pointer (MSB)

76543210

MSB LSB

Current Sequence pointer (LSB)

CAN frames to be transmitted are constructed and

launched from the CAN Bus transmit scheduler. The

scheduler is user programmed using a descriptor table to

output CAN frames in a predefined order and repetition

rate. To make best use of available memory space, three

different types (Type 1-3) of descriptor tables entry

formats are available. The user may mix descriptor types

in the table.

The CAN Indentifier ID and data byte content of each

frame transmitted is user defined and may be sourced

from the host CPU / auto-initialization EEPROM

(immediate data) or bytes from the ARINC 429 receive

memory (ARINC indexed) or CAN bus receiver memory

(CAN indexed). This allows received ARINC and / or CAN

bus data to be re-formated and re-transmited on the CAN

bus. Conditional transmission control allows sequenced

words to be skipped if no new data is available. CAN

frames are constructed and transmitted until an end of

sequence marker or RAM location 0x79BF is reached.

Note that if 0x79BF is reached before the frame is

completely constructed, that frame will be discarded.

Note that because the CAN bus bandwidth is shared

between all terminals on the bus, sufficient bandwidth to

transmit the entire programmed sequence of frames may

not be available in the time slot programmed. In such

circumstances the user may choose to repeat the

sequence immediately upon completion, or wait until the

next multiple of the programmed repetition rate elapses.

The CAN sequencer operation is controlled by the CAN

Transmit control Register:

The transmit sequence pointer is set to 0x6000 on Master

Reset. Once the RUN / bit goes high, sequence

execution begins at sequence count zero (Memory

Address 0x6000). After the first word is sent, the pointer

is incremented to the address of the next descriptor in the

STOP

sequence table. This continues until the programmed

sequence is complete. The sequence pointer is then

reset to zero and program execution begins as soon the

CAN repetition rate counter time elapses.

CAN BUS TRANSMIT OPERATION

The HI-3200 is able to transmit CAN frames via an external HI-3110 CAN controller / transceiver IC. CAN frames

may be loaded for immediate transmission from the host CPU, or in a pre-programmed sequence using the integrated

CAN frame scheduler.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

XXXXX

76543210

MSB LSB

CAN REPETITION RATE REGISTER

(Address 0x8033)

Channel Repetition Period

The Repetition rate register value defines the time

interval between successive starts of the programmed

CAN transmit sequence. The value is set in binary, with

the LSB representing 10 ms.

If the repetition rate is shorter than the minimum time

needed to transmit all CAN frames in the sequence (but

not zero), the transmit sequence will begin again

immediately if the CAN Control Register SKIP bit is a

zero. If the SKIP bit is a one, the sequencer will wait until

the next rollover of the Repetition Rate Counter before

starting a new cycle.

When the Repetition Rate counter is programmed to zero

(default), the transmit sequence shall execute one time

only. A zero - to - one transition of the RUN/STOP bit will

cause the transmit sequence to start. One-time execution

of the sequencer is useful when transmitting CAN frames

directly from the host CPU. One or more immediate-

mode (Type 1) descriptors can be written into the

sequence table, transmitted, and then refreshed for the

next cycle.

CAN Bus Transmit Descriptor Table

Transmit Frame Descriptor 0

0x6000

Descriptor Header

Repetion Rate

Repetition rate

counter

Sequence

pointer

Transmit Frame Descriptor 1

Transmit Frame Descriptor 2

Transmit Frame Descriptor 3

Transmit Frame Descriptor 4

Transmit Frame Descriptor 5

End of Sequence marker

Descriptor Byte 1

Descriptor Byte 2

Descriptor Byte n

Transmit Frame Descriptor n

}

0 - 24 Bytes

0x79BF

The contents of each CAN frame transmitted in the

sequence is defined by its Frame Descriptor. Each

descriptor consists of one “Descriptor Header Byte” and

from 0 to 24 additional descriptor bytes depending upon,

the descriptor type (type1-3)andthedata payload

length. A special descriptor header marks the end of the

descriptor table.

The three different descriptor types allow the user to

make best use of the available descriptor table memory

space while still allowing complete flexibility in defining

frame content and data source. The Descriptor header

byte is of a common format for all three descriptor types.

The CAN Transmit sequence pointer uses information in

the header byte to determine the length of the descriptor

and thus the address of the next descriptor block in the

sequence table.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Type 1 CAN Transmit Descriptor Frame Format

Type 1 CAN transmit descriptors are used when transmitting frames using CAN Identifier and Data payload values

defined explicitly by the HI-3200 Host CPU or Auto-initialization EEPROM.

The descriptor format is as follows:

Type 1 Descriptor Header Byte

ID28 to ID21

ID20 to ID18, SRR, IDE, ID17 to ID15

ID14 to ID7

ID6 to ID0, r0

CAN Data Byte 1

CAN Data Byte n

}

0 - 8 Bytes

CAN TRANSMIT DESCRIPTOR HEADER BYTE

76543210

MSB LSB

DLC

Type

RTR

Type RTR DLC Description

X XXXX End of sequence marker.

0 NNNN Type 1 descriptor CAN Data frame. Data Length Code (DLC) indicates the number of data bytes

in the CAN frame 0 - 8. DLC values >8 always have eight data bytes. The number of descriptor

bytes D is given by D=1+(4+N),where N is the DLC value or 8 if DLC>8.

01 1 XXXX Type 1 descriptor CAN Remote frame. The number of bytes in the descriptor is 5.

10 0 NNNN Type 2 descriptor CAN Data frame. The number of descriptor bytes is D=2+(2 x N), where N is the

DLC value or 8 if DLC>8.

10 1 XXXX Type 2 descriptor CAN Remote Frame. The number of descriptor bytes is 2.

11 0 NNNN Type 3 descriptor CAN Data frame. The number of descriptor bytes is D=9+(2 x N), where N is the

DLC value or 8 if DLC>8.

11 1 XXXX Type 3 descriptor CAN Remote frame. The number of descriptor bytes is 9.

NOTE: Bit 7 should be set to the value of the reserved bit “r1” of the CAN frame.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Type 3 CAN Transmit Descriptor Frame Format

Type 3 Descriptor Block

Type 3 Descriptor Header Byte

CAN ID1 Action Byte

CAN ID1 Value Byte

Data Byte n Action Byte

}

0 - 16 Bytes

Data Byte n Value Byte

CAN ID2 Action Byte

CAN ID2 Value Byte

CAN ID3 Action Byte

CAN ID3 Value Byte

CAN ID4 Action Byte

CAN ID4 Value Byte

Data Byte 1 Action Byte

Data Byte 1 Value Byte

}

ID28 to ID21

ID20 to ID18, SRR, IDE, ID17 to ID15

ID14 to ID7

ID6 to ID0, r0

Source pointer for

Type 2 CAN Transmit Descriptor Frame Format

Type 2 CAN transmit descriptors use a pre-loaded 256

entry common look-up table to define the CAN ID field of

the transmitted frame.

CAN Data Byte values may be directly loaded from the

host CPU / Auto-initialization EEPROM, or are read from

the ARINC 429 Received Data RAM or CAN Bus

Received Data RAM as indexed by the two data source

descriptor bytes (op-code byte and index byte).

ID28 to ID21

ID20 to ID18, SRR, IDE, ID17 to ID15

ID14 to ID7

ID6 to ID0, r0

Type 2 Descriptor Header Byte

ID Table Entry # (0 - FF)

Data Byte 1 Action Byte

Data Byte 1 Value Byte

Data Byte 2 Action Byte

Data Byte 2 Value Byte

Data Byte n Action Byte

}

0 - 16 Bytes

Data Byte n Value Byte

Type 2 Descriptor Block

ID Entry 0

ID Entry 1

ID Entry 2

ID Entry 255

Type 2 ID Look-up Table Type 2 ID Table Entry

0x7C00

0x7C04

0x7C08

0x7FF8

0x7FFF

Type 3 CAN transmit descriptors are used when

transmitting frames using CAN Identifier and Data

payload extracted from the ARINC 429 Received Data

RAM, CAN Bus Received Data RAM, or host CPU / Auto-

initialization EEPROM loaded values.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Type 2 and 3 CAN Transmit Descriptor Opcode and Index Bytes

Type 2 and 3 CAN Transmit Discriptor Op-Code and Index byte pairs specify the source of data for their corresponding

CAN frame ID bits and data bytes. Their format and operation is similar to the ARINC 429 descriptor byte pairs:

Index ValueOp-Code Description

0X0 XXXXX LLLLLLLL Immediate data. The value contained in the descriptor value data byte is

loaded into this byte position of the CAN Frame to be transmitted.

0X1 CCCXX LLLLLLLL Immediate data conditional. The NEWCAN bit corresponding to the ARINC

Data RAM location defined by channel “CCC” and label block “LLLLLLLL” is

read. LLLLLLLL is used if NEWCAN is set for this

within this descriptor frame. If NEWCAN = 0 for all

conditional op codes (within this descriptor frame) then no transmission

occurs for this frame and the sequencer increments to the next descriptor

frame. The NEWCAN bit for the referencedARINC RAM block is reset.

100 CCCBB LLLLLLLL Indexed data. The value of ARINC Data RAM location defined by channel

“CCC”, label block “LLLLLLLL” and byte number “BB” is loaded into this byte

position of the CAN frame to be transmitted.

101 CCCBB LLLLLLLL Indexed data conditional. The NEWCAN bit corresponding to the ARINC

Data RAM location defined by channel “CCC”, label block “LLLLLLLL” and

byte number “BB” is read. The corresponding byte is used if

NEWCAN is set for this within this

descriptor frame. If NEWCAN = 0 for all conditional op codes (within this

descriptor frame) then no transmission occurs for this frame and the

sequencer increments to the next descriptor frame. The NEWCAN bit for the

referencedARINC RAM block is reset.

110 XBBBB NNNNNNNN CAN byte. The value of the byte at CAN RAM address filter block

“NNNNNNNN”, byte number “BBBB” is loaded into the CAN transmit buffer

byte position to be transmitted.

111 XBBBB NNNNNNNN CAN byte conditional. The NEWCAN bit corresponding to the CAN RAM

address filter block “NNNNNNNN”, byte number “BBBB”

is read. The corresponding byte is used if NEWCAN is set for this

within this descriptor frame. If NEWCAN = 0 for

all conditional op codes (within this descriptor frame) then ARINC word

construction is terminated, no transmission occurs for this frame and the

sequencer increments to the next descriptor frame. The NEWCAN bit for

the referenced CAN RAM address filter block is reset.

or any other

conditional opcode

or any other conditional opcode

or any

other conditional opcode

CAN TRANSMIT OPCODE - INDEX BYTE PAIR

76543210

MSB LSB

Index

76543210

MSB LSB

Value

Op-Code

ACTION BYTE VALUE BYTE

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

CAN Bus Immediate Transmit Option

The Host CPU may instruct the HI-3200 to transmit an

CAN frame immediately using a special SPI command.

The SPI command describes the CAN frame with 5 to 13

SPI data bytes. The bit format of the data bytes is exactly

the same as a Type 1 transmit descriptor, except the

Type Field of the header byte is “don’t care”.

If the CAN transmit sequencer is not running (CTCR bit

RUN/ = “0”), or the sequencer is waiting for the

repetition rate counter to rollover, then the new CAN

frame is transmitted without delay.

STOP

If the CAN transmit sequencer is active, then the new

frame is transmitted to HI-3110 as soon as the current

frame has been sent. The sequencer then resumes

operation at the next location in the queue.

Both the RUN input pin and the Master Control Register

CANTX bit must be high to enable any CAN frame

transmission.

Table 1 lists the host CPU SPI instruction format.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

After power-on, the HI-3200 is in an undefined state. The

RESET pin must be taken high to begin device

initialization. The RESET pin may be asserted at any

time. Taking RESET high immediately stops all execution

and sets the READY output low indicating that the part is

in the reset state.

On the falling edge of RESET, the HI-3200 samples the

state of the MODE2-0 input pins. This is the only

occasion these inputs are sampled. The state of the

MODE pins determines one of eight possible initialization

sequences (Mode 0 through Mode 7) as shown in the

following diagram. These eight initialization modes allow

the user to customize the start-up configuration of the

device.

Once the initialization is complete, the device enters the

Idle State when the ready pin goes high. In Idle State, the

host CPU may communicate with the HI-3200 memory

and registers using the host CPU SPI link. Note that

when Mode 6 is selected, the host CPU SPI by-passes

the HI-3200 and instead communicates directly with the

HI-3110 CAN controller, if used. When in the Idle State,

The HI-3200 does not transmit or receive any messages

on either the ARINC 429 buses or the CAN bus.

To begin data bus operation, the user must transition the

RUN input from a low to high state. Immediately following

the rising edge of RUN, the HI-3200 configures the HI-

3110 CAN controller, if used, according to the MODE

selection. The part then enters the Active State and bus

message processing begins.

During initialization, various device configuration tasks

are performed according to the Mode selection set at the

MODE2:0 input pins. The available options are:

he part enters the “Safe”

state, in which the HI-3200 is able to accept and respond

to Host CPU SPI Instructions, but cannot enter Normal

Operating mode until the RESET input is taken high to

repeat the initialization sequence.

1. RAM Integrity Check

In Modes 2 and 3, the HI-3200 performs a RAM integrity

check. A read/write check is performed on the entire

RAM space. An incrementing pattern is written to

sequential RAM locations then this pattern is read and

verified. Each RAM location is re-written with the 1s

complement of its current contents then this pattern is

read and verified. The incrementing pattern followed by

its 1s complement ensures that each RAM location can

store both a 1 and 0 state. If the RAM integrity check

fails, the MINT pin is asserted and the Pending Interrupt

The RAMFAIL Interrupt

is not maskable.

2. Clear Data Memory

3. Initialize Registers and Clear all memory

4. Auto-Initialize from EEPROM

In Modes 0, 1, 2, 3, 5, 6, and 7, the HI-3200 automatically

clears all memory locations in the address range 0x0000

to 0x33FF. This is the space reserved for ARINC 429 and

CAN message data. Configuration tables and HI-3200

registers are not affected.

In addition to clearing data memory (0x0000 to 0x33FF),

Modes 0, 1, 2, and 3 also clear all configuration and look-

up tables (0x3400 to 0x7FFF) as well as setting all

registers (0x8000 to 0x807F) to their default states. All

registers default to zero unless otherwise noted.

The contents of the Auto-Initialization EEPROM are

copied into the HI-3200 memory and registers via the

EEPROM SPI interface. The part verifies the integrity of

the data transfer from the EEPROM by running through a

byte-by-byte compare routine and a checksum validation.

Once initialization is complete, the part enters the Idle

state. The host CPU may read and write HI-3200 internal

memory and registers in Modes 0, 1, 2, 3, 4, 5, and 7. If

not using the auto-initizarion feature, the host CPU

should configure the device at this time.

If a compare error is detected, the AUTOERR bit is set in

the Pending Interrupt Register, the MINT output is

asserted, the location of the error is captured in the

AUTO-INIT FAIL ADDRESS registers 0x8073 (Auto-Init

Fail LS address) and 0x8074 (Auto-Init Fail MS address)

and the part enters the Safe state. If a checksum error is

detected, the CHKERR bit is set in the Pending Interrupt

the Safe state. The AUTOERR and the CHKERR

interrupts are not maskable.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

RESET AND START-UP

OPERATION

5 Enable SPI By-Pass

6. HI-3110 Initialize

In Mode 6, the host CPU SPI interface completely by-

passes the HI-3200, and all communication is directed to

the HI-3110 SPI bus such that the user may directly

access registers within the HI-3110. This “by-pass’ mode

is intended as an aid to debugging only and is not

recommended in the final system design implementation.

By-pass mode is exited at the first rising edge of the RUN

pin. Further toggling of the RUN pin will not re-engage

the by-pass mode. Since the host does not have access

to internal HI-3200 registers prior to RUN going high, the

user must first initialize these registers prior to entering

Mode 6.

In Modes 0 through 5, as soon as the RUN input is

transitioned from low to high, the contents of the CAN

bus configuration registers (CANBTR0, CANBTR1) is

transferred to the HI-3110 and other HI-3110 reset and

initialization tasks are performed.

The following values are written to the HI-3110 registers

in the sequence outlined below.

Write 0x88 to HI-3110 CTRL1 Register

Write Register 0x8030 to HI-3110 BTR0 Register

Write Register 0x8031 to HI-3110 BTR1 Register

Write 0x40 to HI-3110 STATE Register

Write 0x65 to HI-3110 GPINE Register

Write 0x07 to HI-3110 CTRL0 Register

The HI-3200 communicates with the HI-3110 over its

dedicated SPI bus.

Following HI-3110 initialization, the HI-3200 enters the

ACTIVE state and bus message processing begins.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Reset and Start-up Operation

RESET driven to “1”

Stop execution, READY => 0

RESET driven to “0”

Sample MODE2:0 inputs

RAM Pass

Copy OK

Set AUTOERROR

INT = 1

SAFE STATE

Set RAMFAIL

INT = 1

Yes

RESET STATE

MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7

Perform

RAM Integrity Check No No Yes Yes No No No No

Clear data memory Yes Yes Yes Yes No Yes Yes Yes

(0x0000 - 0x33FF)

Initialize Registers and Yes Yes Yes Yes No No No No

Clear Configuration Tables

(0x3400 - 0xFFFF)

Auto-Initialize from No Yes No Yes No No No No

EEPROM

Enable SPI By-Pass No No No No No No Yes No

READY => 1

RUN driven0-1

IDLE STATE

MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7

HI-3110 Initialize Yes Yes Yes Yes Yes Yes No No

Disable SPI By-Pass n/a n/a n/a n/a n/a n/a Yes n/a

ACTIVE STATE

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

INTERRUPT HANDLING

The HI-3200 includes a simple, user-selectable Interrupt

Handler. Two types of Interrupt are possible - Message

Event Driven (ARINC 429 or CAN Bus), and Fault Driven.

As described earlier, the user can elect to generate an

interrupt upon receipt of an ARINC 429 message on any

combination of the eight available channels and for any

of the possible 256 label byte (ARINC message bits 1-8)

values. Interrupts are enabled when the ARINC 429 Rx

Interrupt look-up bit is a “1”.

When a message arrives that is flagged to generate an

Interrupt, that channel’s bit is set in the ARINC 429

Receiver Pending Interrupt Register APIR. The ARINC

429 Interrupt Address Register (AIAR) for that channel is

updated with the ARINC 429 8-bit label value.

For example, if ARINC Receive channel 7 is enabled for

Interrupts when messages with ARINC label 0xD4 arrive,

then on receipt of such a message, APIR bit 7 is set to a

“1” and the value 0xD4 is written to AIAR7.

If the corresponding bit in the ARINC 429 Receive

Interrupt Mask Register is a “1” the AINT interrupt output

will go high and stay high until the AACK input pin is

driven high. Driving AACK high, causes the AINT pin to

return to zero.

A special Indexed SPI read instruction is available to

allow the host to efficiently retrieve ARINC 429 messages

which have Interrupts Enabled (see SPI instruction set

section).

Note that if AACK is tied high permanently, the AINT pin

will go high for approximately 1 us before returning to

zero. A host CPU read of the APIR register reads the

current value and resets APIR to 0x00.

ARINC 429 Receive Interrupts

CAN Bus Interrupts

Fault Interrupts

An interrupt is generated on receipt of a CAN frame

whose corresponding Filter and Interrupt look-up table

bits are a “1”. The CANRX bit is set in the Pending

Interrupt Register PIR, and the filter number which

accepted the CAN frame is written to the CAN Interrupt

Address Register CIAR. For example, if filter # 0xA1

accepts the frame, the value 0xA1 is written to CIAR.

The Interrupt output, MINT, is asserted if the Interrupt

Mask Register CANRX bit is a “1”.

A special SPI Instruction allows the user to extract the

received frame information from the CAN receive

memory without having to first determine its sixteen-bit

absolute address. The CIAR value is used as a relative

address pointer.

There are four fault Interrupt bits in the PIR. Fault

Interrupts are not maskable, and their Interrupt Mask bits

are fixed at a “1”.

COPYERR is set when the HI-3200 detects a mismatch

between RAM and EEPROM after attempting to program

the Auto-initialization EEPROM.

AUTOERR is set when the Auto-Initialization EEPROM

read verification cycle detects a mismatch between the

on-chip memory and EEPROM following auto-

initialization.

CHKERR is set when an auto-initialization checksum

error is detected.

The RAMFAIL bit is set if the Built-In Self Test sequence

fails.

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Bit Name R/W Default Description

7:0 APIR[7:0] R 0 When a message is received on a given channel that triggers an interrupt, that channel’s

corresponding bit is set, e.g. if a message received on Rx channel 5 triggers an interrupt, the

bit APIR5 will be set. If this bit is unmasked in the ARINC 429 Receive Interrupt Mask Register

(see below), theAINT output pin is asserted.

This register is automatically cleared when read.Note:

76543210

MSB LSB

APIR4

APIR3

APIR2

APIR1

APIR0

APIR5

APIR6

APIR7

ARINC 429 RECEIVE PENDING INTERRUPT REGISTER

(Address 0x8000)

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

76543210

MSB LSB

AIMR4

AIMR3

AIMR2

AIMR1

AIMR0

AIMR5

AIMR6

AIMR7

ARINC 429 RECEIVE INTERRUPT MASK REGISTER

(Address 0x8020)

Bit Name R/W Default Description

7:0 AIMR[7:0] R/W 0 Each bit in this register, AIMR[7:0], is a mask for a corresponding bit in the ARINC 429 Receive

Pending Interrupt Register (APIR[7:0], described above). Writing a “1” to an AIMR bit

results in assertion of the AINT output pin when the corresponding APIR bit is set (ARINC 429

message received). Writing a “0” to an AIMR bit will mask the corresponding APIR bit in the

ARINC 429 Receive Pending Interrupt Register, resulting in non-assertion of the AINT pin

when an ARINC 429 message is received.

Bit Name R/W Default Description

7:0 AIAR0[7:0] R 0 The label number of the ARINC 429 message causing an interrupt is loaded into this

(AIAR0 -AIAR7).

ARINC 429 RECEIVE INTERRUPT ADDRESS REGISTERS0-7

(Address 0x8001 - 0x8008) 76543210

MSB LSB

AIARn4

AIARn3

AIARn2

AIARn1

AIARn0

AIARn5

AIARn6

AIARn7

n=0-7

Bit Name

3 FLAGIE

0 CTXRDYIE R/W

R/W Default Description

7 COPYERR R 1 COPYERR is not maskable

6 AUTOERR R 1 AUTOERR is not maskable

5 CHKERR R 1 CHKERR is not maskable

4 RAMFAIL R 1 RAMFAIL is not maskable

R/W 0 MINT pin is asserted if this bit is a “1” and the Pending Interrupt Register FLAG bit is set

2 ATXRDYIE R/W 0 MINT pin is asserted if this bit is a “1” and the Pending Interrupt RegisterATXRDY bit is set

1 CANRXIE R/W 0 MINT pin is asserted if this bit is a “1” and the Pending Interrupt Register CANRX bit is set

0 MINT pin is asserted if this bit is a “1” and the Pending Interrupt Register CTXRDY bit is set

76543210

MSB LSB

RAMFAIL

FLAGIE

ATXRDYIE

CANRXIE

CTXRDYIE

CHKERR

AUTOERR

COPYERR

PENDING INTERRUPT ENABLE REGISTER

(Address 0x8034)

The MINT will be asserted when any of the bits in this register are set.

3 FLAG

1 CANRX

0 CTXRDY R

Bit Name R/W Default Description

7 COPYERR R 0 EE copy error. RAM - EEPROM mismatch

6 AUTOERR R 0 Auto-inititailization RAM read error

5 CHKERR R 0 Auto-initialization checksum fail

4 RAMFAIL R 0 Power-On Reset RAM Integrity Check fail

R 0 Logical OR of ARINC 429 Receive FIFO FLAG signals

2 ATXRDY R 0 ARINC 429 Host TX ready. Used with Host SPI op-code 100101TT (see Table 1). Interrupt

when any of the fourARINC 429 transmitters are ready for the next 32-bit word from the host

R 0 CAN Bus received frame Interrupt

0 CAN Host Tx ready. Used with host SPI opcode 10010000. Interrupt when ready for next CAN

frame from host.

76543210

MSB LSB

RAMFAIL

FLAG

ATXRDY

CANRX

CTXRDY

CHKERR

AUTOERR

COPYERR

PENDING INTERRUPT REGISTER

(Address 0x800A)

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Bit Name

3 ATXIE3

0 R/W

R/W Default Description

7 - R/W 0 Not Used

6 - R/W 0 Not Used

5 - R/W 0 Not Used

4 - R/W 0 Not Used

R/W 0 Setting this bit generates an interrupt when ARINC 429 Transmitter 3 is ready to receive the

next 32-bit word from the host for transmission. The ATXRDY bit in the Pending

Interrupt Register will be set and the MINT pin will be asserted if the ATXRDYIE bit is set in the

Pending Interrupt Enable Register.

2 ATXIE2 R/W 0 Setting this bit generates an interrupt when ARINC 429 Transmitter 2 is ready to receive the

next 32-bit word from the host for transmission. The ATXRDY bit in the Pending

Interrupt Register will be set and the MINT pin will be asserted if the ATXRDYIE bit is set in the

Pending Interrupt Enable Register.

1 ATXIE1 R/W 0 Setting this bit generates an interrupt when ARINC 429 Transmitter 1 is ready to receive the

next 32-bit word from the host for transmission. The ATXRDY bit in the Pending

Interrupt Register will be set and the MINT pin will be asserted if the ATXRDYIE bit is set in the

Pending Interrupt Enable Register.

ATXIE0 0 Setting this bit generates an interrupt when ARINC 429 Transmitter 0 is ready to receive the

next 32-bit word from the host for transmission. The ATXRDY bit in the Pending

Interrupt Register will be set and the MINT pin will be asserted if the ATXRDYIE bit is set in the

Pending Interrupt Enable Register.

76543210

MSB LSB

ATXIE3

ATXIE2

ATXIE1

ATXIE0

ARINC 429 TX READY INT ENABLE

(Address 0x8035)

76543210

MSB LSB

CAN INTERRUPT ADDRESS REGISTER

(Address 0x800B)

CIAR

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

XXXX

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

RAM BUILT-IN SELF-TEST

The HI-3200 offers a built-in self-test (BIST) feature which can be used to check RAM integrity. The BIST Control/Status

Register is used to control the BIST function.All tests are destructive, overwriting data present before test commencement.

76543210

MSB LSB

RBSEL0

RBSTART

RBFAIL

RBPASS

RBSEL1

RBSEL2

RBFAIL

BIST CONTROL/STATUS REGISTER

(Address 0x8070)

This register controls RAM built-in self-test. Bits 0,1 are Read Only. The remaining bits in this register are Read-Write but can

be written only in MODE2:0 = 0x04.

BIST Control Register bits provide a means for the host to perform RAM self-test at other times. Register bits 6:4 select RAM

test type. Then bit 3 starts the selected RAM test, and bits 1:0 report a fail/pass result after test completion.

7 RBFFAIL RAM BIST Force Failure.

When this bit is asserted, RAM test failure is forced to verify that RAM BIST logic is functional.

6:4 RBSEL2-0 RAM BIST Select Bits 2-0.

This 3-bit field selects the RAM BIST test mode applied when the RBSTART bit is set:

000 Idle

001 Pattern Test, described below

010 Write 0x00 to RAM address range 0x0000 - 0x7FFF

011 Read and verify 0x00 over RAM address range 0x0000 - 0x7FFF

100 Write 0xFF to RAM address range 0x0000 - 0x7FFF

101 Read and verify 0xFF over RAM address range 0x0000 - 0x7FFF

110 Inc / Dec Test performs only steps5-8ofthePattern Test below

111 Idle

1. Write 0x00 to all RAM locations, 0x0000 through 0x7FFF

2. Repeat the following sequence for each RAM location from 0x0000 through 0x7FFF:

a. Read and verify 0x00

b. Write then read and verify 0x55

c. Write then read and verify 0xAA

d. Write then read and verify 0x33

e. Write then read and verify 0xCC

f. Write then read and verify 0x0F

g. Write then read and verify 0xF0

h. Write then read and verify 0x00

I. Write then read and verify 0xFF

j. Write 0x00 then increment RAM address and go to step (a)

3. Write 0xFF to all RAM locations, 0x0000 through 0x7FFF

4. Repeat the following sequence for each RAM location from 0x0000 through 0x7FFF:

a. Read and verify 0xFF

b. Write then read and verify 0x55

c. Write then read and verify 0xAA

d. Write then read and verify 0x33

e. Write then read and verify 0xCC

Bit No. Mnemonic Interrupt Type

RBSEL2:0 SELECTED RAM TEST

Description of the RAM BIST “PATTERN” test selected when register bits RBSEL2:0 =

001:

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

f. Write then read and verify 0x0F

g. Write then read and verify 0xF0

h. Write then read and verify 0x00

I. Write then read and verify 0xFF

j. Write 0xFF then increment RAM address and go to step (a)

5. Write an incrementing pattern into sequential RAM locations from 0x0000 to 0x7FFF

6. Read each memory location from 0x0000 to 0x7FFF and verify the contents

7. Write 1s complement of each cell’s current contents, into each RAM location (same addr range)

8. Read each memory location and verify the contents

3 RBSTRT RAM BIST Start.

Writing logic 1 to this bit initiates the RAM BIST test selected by register bits RBSEL2:0. The RBSTRT

bit can only be set in MODE2:0 = 0x04. This bit is automatically cleared upon test completion.

2 --------- Not Used.

1 RBFAIL RAM BIST Fail.

Device logic asserts this bit when failure occurs while performing the selected RAM test. This bit is

automatically cleared when RBSTRT bit 3 is set. When BIST failure occurs, a clue to the failing RAM

address can be read at register addresses 0x8071 and 0x8072. For speed, the RAM BIST

concurrently tests four consecutive RAM addresses in parallel. If a test failure occurs, register

addresses 0x8071 and 0x8072 can be used to determine the four RAM addresses tested.

0 RBPASS RAM BIST Pass.

Device logic asserts this bit when the selected RAM test completes without error. This bit is

automatically cleared when RBSTRT bit 3 is set.

76543210

MSB LSB

LOWER BIST FAIL ADDRESS REGISTER

(Address 0x8071)

BISTFL

13 12 11 10 9 8

MSB LSB

UPPER BIST FAIL ADDRESS REGISTER

(Address 0x8072)

BISTFH

15 14

In the HI-3200, internal RAM and registers occupy a (32K +

128) x 8 address space. The lowest 32K addresses access

RAM locations and the remaining addresses access

registers. Timing is identical for register operations and

RAM operations via the serial peripheral interface, and

read and write operations have likewise identical timing.

Host access is only allowed when the part is READY or in

SAFE mode. writes will be blocked and reads will

return the Master Status Register value until either of these

modes occur.

CPOL-

CPHA

A rising edge on chip

select terminates the serial transfer and reinitializes the

HI-3200 SPI for the next transfer. If goes high before a

full byte is clocked by SCK, the incomplete byte clocked

into the device SI pin is discarded.

In the general case, both master and slave simultaneously

send and receive serial data (full duplex) as shown in

Figure 1 below. When the HI-3200 is sending data on SO

during read operations, activity on its SI input is ignored.

Figures 2 and 3 show actual behavior for the HI-3200 SO

output.

NOTE:

Serial Peripheral Interface (SPI) Basics CS

The HI-3200 uses an SPI synchronous serial interface for

host access to registers and RAM. Host serial

communication is enabled through the Chip Select ( )

pin, and is accessed via a three-wire interface consisting of

Serial Data Input (SI) from the host, Serial Data Output

(SO) to the host and Serial Clock (SCK). All programming

cycles are completely self-timed, and no erase cycle is

required before write.

The SPI (Serial Peripheral Interface) protocol specifies

master and slave operation; the HI-3200 Host CPU

interface operates as an SPI slave.

The SPI protocol defines two parameters, CPOL (clock

polarity) and CPHA (clock phase). The possible

combinations define four possible "SPI Modes."

Without describing details of the SPI modes, the HI-3200

operates in the two modes where input data for each

device ( master and slave) is clocked on the rising edge of

SCK, and output data for each device changes on the

falling edge. These are known as SPI Mode 0 (CPHA = 0,

CPOL = 0) and SPI Mode 3 (CPHA = 1, CPOL = 1). Be sure

to set the host SPI logic for one of these modes.

As seen in Figure 1, the difference between SPI Modes 0

and 3 is the idle state for the SCK signal. There is no

configuration setting in the HI-3200 to select SPI Mode 0 or

Mode 3 because compatibility is automatic. Beyond this

point, the HI-3200 data sheet only shows the SPI Mode 0

SCK signal in timing diagrams.

The SPI protocol transfers serial data as 8-bit bytes. Once

chip select is asserted, the next 8 rising edges on SCK

latch input data into the master and slave devices, starting

with each byte’s most-significant bit. The HI-3200 SPI can

be clocked at 20 MHz.

Multiple bytes may be transferred when the host holds

low after the first byte transferred, and continues to clock

SCK in multiples of 8 clocks.

HOST SERIAL PERIPHERAL INTERFACE

MSB LSB

MSB LSB High Z

High Z

01234567

SCK (SPI Mode 3)

01234567

SCK (SPI Mode 0)

FIGURE 1. Generalized Single-Byte Transfer Using SPI Protocol, SCK is Shown for SPI Modes 0 and 3

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

FIGURE 2. Single-Byte Read From RAM or a Register

SCK

SPI Mode 0

MSB LSB

01234567

High Z High Z

01234567

MSB LSB MSB

LSB

Data Byte

Command Byte

Host may continue to assert

here to read sequential byte(s)

when allowed by the instruction.

Each byte needs 8 SCK clocks.

HOLT INTEGRATED CIRCUITS

FIGURE 3. 2-Byte Write To RAM or a Register Pair

SCK

SPI Mode 0

MSB LSB

012345670123456701234567

MSB LSB MSB LSB

Data Byte 0 Data Byte 1

Command Byte

Host may continue to assert

here to write sequential byte(s)

when allowed by the SPI instruction.

Each byte needs 8 SCK clocks.

High Z

HI-3200, HI-3201

HI-3200 SPI COMMANDS

For the HI-3200, each SPI read or write operation begins

with an 8-bit command byte transferred from the host to the

device after assertion of . Since HI-3200 command byte

reception is half-duplex, the host discards the dummy byte

it receives while serially transmitting the command byte.

The SPI command set includes directly-addressed read

and write commands for registers 0 through 15 (Memory

Address 0x8000 to 0x800F). The 8-bit pattern for these

commands has the general form

0-W-R-R-R-R-0-0

where RRRR is the 4-bit register number, and W signifies

Write when 1, or Read when 0.

Figures 2 and 3 show read and write timing as it appears

for fast-access register operations. The command byte is

immediately followed by a data byte comprising the 8-bit

data word read or written. For a single register read or

write, is negated after the data byte is transferred.

Multiple register read or write cycles may be performed by

transferring more than one byte before is negated.

Multiple register access occur in address order starting

with the register specified in the SPI instruction.

Note: Register locations not shown in table 1 are

“reserved” and cannot be written using any SPI command.

Further, these register addresses will not provide

meaningful data in response to read commands.

Refer to the HI-3200 SPI command set shown in Table 1.

SPI commands other than fast-access use an address

pointer to indicate the address for read or write

transactions. This sixteen-bit memory address pointer

(MAP) must be initialized before any non-fast-access read

or write operation. Two dedicated SPI instructions are

used to write and read the MAP. SPI Instruction 0x8C

followed by two data bytes is used to write MAP. SPI

instruction 0x88 reads two data bytes from MAP. The first

byte is the most significant eight bytes of the address. For

example, SPI sequence 0x8C, 0x12, 0x34 write the value

0x1234 into the MAP.

Two SPI instructions read and write data bytes to memory

or registers using the MAP as an address pointer. Single or

multi-byte reads and writes may be performed. MAP is

incremented after each byte access.

; must be

negated after the command, then reasserted for the

following Read or Write command.

Two single-byte SPI commands use the current address

pointer value in MAP without first loading or otherwise

modifying it:

0x80 read location addressed by pointer value

0x84 write location addressed by pointer value

Using a single-byte SPI command, the address pointer can

be directly loaded with the memory address for the last

received ARINC 429 message which triggered an

interrupt.

The HI-3200 will retrieve the current ARINC Receive

Interrupt Vector for a given channel (RRR), calculate t h e

memory address for the first word of the c o r r e s ponding

receive memory data block and write it to the Memory

Address pointer (MAP). Read the location addressed by

the new pointer value.

This command can be used to read just the most recent

ARINC 429 Receive Status Byte, or may be used to start a

four-byte read because memory pointer auto-increment

occurs after the Status Byte is read.

The HI-3200 will retrieve the current ARINC Receive

Interrupt Vector for a given channel (RRR), calculate the

memory address for the first word of the corresponding

receive memory data block and write it to the Memory

Address Pointer (MAP). Output the value of the Receive

Interrupt Vector (ARINC 429 label byte).

This command can be used to read just the most recent

ARINC 429 label value received, or may be used to start a

four-byte read to output the entire four-byte ARINC

Fast Access Commands for Registers 0-15

RAM and Register Indirect Addressing

Two command bytes cannot be “chained”

Command Read Operation

Command Write Operation

Op Code 110RRR00

Op Code 111RRR00

Note: When the primary or fast-access address pointer is

used for auto-incrementing multi-word read/write and

reaches the top of the memory address range (0x7FFF), or

the top of the register address range (0xFFFF) attempts to

read further bytes will result the terminal address (0x7FFF

or 0xFFFF) being output again. The host should avoid this

situation.

Either of these commands can be used to read or write a

single location, or may be used when starting a multi-byte

read or write by using the pointer’s auto-increment feature.

Several other HI-3200 SPI commands load or otherwise

modify the memory address pointer before initiating a read

or write process. These commands are designed to allow

speedy access to messages received on the ARINC 429 or

CAN buses.

Special Purpose Commands

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

message, because memory pointer auto-increment

occurs after the label byte is output.

This command can be used to read just the most recent

CAN frame Information byte received, or may be used to

start a sixteen-byte read to output the entire sixteen-byte

received CAN frame memory block, because memory

pointer auto-increment occurs after the first byte is output.

Writes a CAN frame to the CAN transmit scheduler for

immediate transmission.

Writes an ARINC 429 message to ARINC 429 transmit

scheduler TT for immediate transmission, where TT

represents the channel number.

Op Code 0x9C

Op Code 0x90

Op Code 100101TT

TABLE 1. DEFINED INSTRUCTIONS

DESCRIPTION

Fast Register Read from register RRRR

Fast Register Write to register RRRR

Read memory at address MAP

Write memory at address MAP

Read ARINC block at receive channel RRR, label <ARIn>

Read

Read MAP

Write MAP

Transmit CAN Frame

Transmit ARINC 429 message on transmit bus TT

Read CAN Frame at filter block <CIAR>

Read ARINC 429 FIFO # RRR. Reads exactly four bytes

ARINC message at receive channel RRR, label <ARIn>

Auto

Increment

Yes

OP CODE

Hex

0x00 - 0x3C

0x40 - 0x7C

0x80

0x84

0x9C

0xA0 - 0xBC

0xC0 - 0xDC

0xE0 - 0xFC

0x88

0x8C

0x90

0x94 - 0x97

OP CODE

Binary

00RRRR00

01RRRR00

110RRR00

111RRR00

10000000

10000100

10001000

10001100

10010000

100101TT

10011100

101RRR00

Number of

Data Bytes

1++

5-13

4, 8, 12...

COMMAND BITS HEX FAST-ACCESS

76543210 BYTE WRITE

01000000 0x40 N/A (Read only)

01000100 0x44 N/A (Read only)

01001000 0x48 N/A (Read only)

01001100 0x4C N/A (Read only)

01010000 0x50 N/A (Read only)

01010100 0x54 N/A (Read only)

01011000 0x58 N/A (Read only)

01011100 0x5C N/A (Read only)

01100000 0x60 N/A (Read only)

01100100 0x64 Reserved

01101000 0x68 N/A (Read only)

01101100 0x6C N/A (Read only)

01110000 0x70 N/A (Read only)

01110100 0x74 N/A (Read only)

01111000 0x78 N/A (Read only)

01111100 0x7C Write MCR

COMMAND BITS HEX FAST-ACCESS

76543210 BYTE READ

00000000 0x00 Read APIR

00000100 0x04 Read AIAR0

00001000 0x08 Read AIAR1

00001100 0x0C Read AIAR2

00010000 0x10 Read AIAR3

00010100 0x14 Read AIAR4

00011000 0x18 Read AIAR5

00011100 0x1C Read AIAR6

00100000 0x20 Read AIAR7

00100100 0x24 Reserved

00101000 0x28 Read PIR

00101100 0x2C Read CIAR

00110000 0x30 Read AMFF

00110100 0x34 Read ATRB

00111000 0x38 Read MSR

00111100 0x3C Read MCR

FAST-ACCESS SPI COMMANDS FOR REGISTERS 0-15

Command Bits 5:2 Convey the 4-Bit Register Address

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

When the HI-3200 is reset and initialization Mode 6 is

selected (by setting MODE2:0 inputs to “110”), the SPI by-

pass function is enabled when the device is in the idle

state. SPI By-Pass allows the host CPU to communicate

directly with the HI-3110 CAN controller via its dedicated

SPI interface, by-passing the HI-3200. SPI command

sequences from the host CPU may then directly

interrogate or program the attached HI-3110.

In normal operation, the HI-3200 handles all HI-3110

control functions. SPI By-Pass is intended only as a

system debugging aid.

For a full description of the HI-3110 and its SPI instruction

set, please refer to the latest revision of the HI-3110 data

sheet.

SPI By-Pass mode is disabled as soon as the RUN input is

taken high and the device enters the ACTIVE state. Any

further toggling of the RUN pin will not re-initiate SPI by-

pass mode.

HOST SPI BY-PASS

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Following reset, the HI-3200 may be completely

configured by automatically copying the contents of an

external EEPROM into HI-3200 memory and registers. An

SPI enabled 64KByte EEPROM is used for this purpose.

The EEPROM memory space is mapped to the HI-3200 as

shown in the diagram below.

All configuration memory blocks are copied. The ARINC

429 Received Data Memory contents, ARINC 429 Receive

log FIFO contents, and CAN Bus Received Data Memory

contents are not copied to or from the EEPROM.

The HI-3200 can be used to program the Auto-Initialization

EEPROM. When the HI-3200 is in its IDLE state (RUN

input = “0”), a three step sequence must be performed to

begin the EEPROM programming cycle:

1. Write data value 0x5A to HI-3200 memory address

0x8FFF.

2. Write data value 0xA5 to HI-3200 memory address

0x8FFF.

3. Apply a positive pulse to the PROG input pin of at least 1

ms.

If the three-step sequence is interrupted by any intervening

host activity between steps 1 and 2, or 2 and 3, or if the

PROG pulse is less than 1 ms, the programming cycle will

not start and the device remains in the IDLE state.

Taking the PROG pin low initiates the cycle. The READY

pin goes low, and the contents of the HI-3200 memory and

registers are copied to the EEPROM. When copying is

complete, the HI-3200 executes a byte-by-byte

comparison of the EEPROM and its own register / memory

contents. If the verification completes successfully, the

READY pin goes high.

A 2’s complement of the checksum is also written to the

EEPROM at location 0x807F. The total read back

checksum should be zero. The following locations are

excluded from the checksum because they are either read-

only or unused locations: 0x8000 thru 0x800e, 0x8023 thru

0x802f, 0x8036 thru 0x805e, 0x8070 thru 0x807e.

If the comparison of the EEPROM contents and HI-3200

memory / register contents results in a discrepancy, the HI-

3200 enters the SAFE state, the PROGERR bit is set in the

Pending Error Register and the INT output is asserted.

The user must clear the PROGERR issue before normal

operation can resume.

PROGRAMMING THE AUTO-INITIALIZATION EEPROM.

HI-3200 Memory EEPROM

ARINC 429 / CAN

Receive Data

CAN Bus

Receive Filters

ARINC 429 TX0

Transmit Schedule

Table

CAN Bus

Transmit Schedule

Table

Look-up Tables

0x0000

0x2FFF

0x3000

0x3400

0x3FFF

0x4000

0x47FF

ARINC 429 TX1

Transmit Schedule

Table

ARINC 429 TX2

Transmit Schedule

Table

ARINC 429 Log FIFO Space

ARINC 429 TX3

Transmit Schedule

Table

0x4800

0x4FFF

0x5000

0x57FF

0x5800

0x5FFF

0x6000

0x79BF

0x79C0

0x7BFF

Configuration Registers

0x8000

0x8XXX

CAN TX ID Look-Up Table

0x7C00

0x7FFF

0x0000

0x3FFF

0x3400

0x3FFF

0x4000

0x47FF

0x4800

0x4FFF

0x5000

0x57FF

0x5800

0x5FFF

0x6000

0x79BF

0x7C00

0x7BFF

0x7C00

0x7FFF

0x8000

0x8XXX

0x33FF

CAN Bus

Receive Filters

CAN TX ID Look-Up Table

ARINC 429 TX0

Transmit Schedule

Table

CAN Bus

Transmit Schedule

Table

Look-up Tables

ARINC 429 TX1

Transmit Schedule

Table

ARINC 429 TX2

Transmit Schedule

Table

ARINC 429 TX3

Transmit Schedule

Table

Configuration Registers

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

Operating Supply Voltage

Temperature Range

Industrial ......................... -40°C to +85°C

Extended ....................... -55°C to +125°C

VDD....................................... 3.3 VDC ±5%

Operating

Supply voltage (

Logic input voltage range

Power dissipation at 25°C 1.0 W

Reflow Solder Temperature 260°C

Junction Temperature 175°C

Storage Temperature -65°C to +150°C

VDD) -0.3 V to +5.0 V

-0.3 V DC to +3.6 V

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

Operating Voltage VDD 3.15 3.30 3.45 V

Supply Current IDD 50 mA

Min. Input Voltage (HI) V Digital inputs 70% V

Max. Input Voltage (LO) V Digital inputs 30% V

Pull-Up / Pull-Down Current Digital inputs and data bus 30

Min. Output Voltage (HI) V I = -1.0mA, Digital outputs 90% V

Max. Output Voltage (LO) V I = 1.0mA, Digital outputs 10% V

OH OUT

IH OUT

I µAPUD

VDD = 3.3 V, GND = 0V, T = Operating Temperature Range (unless otherwise specified).A

DC ELECTRICAL CHARACTERISTICS

NOTE: Stresses above absolute maximum ratings or

outside recommended operating conditions may cause

permanent damage to the device. These are stress

ratings only. Operation at the limits is not recommended.

RECOMMENDED CONDITIONSABSOLUTE MAXIMUM RATINGS

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

AC ELECTRICAL CHARACTERISTICS

LIMITS

PARAMETER SYMBOL UNITS

MIN TYP MAX

SPI Host Bus Interface

SCK clock period t 50 ns

hold time after last SCK falling edge t 25 ns

inactive between SPI instructions t

CYC

CEH

set-up time to first SCK rising edge t 25 ns

100 ns

SPI SI Data set-up time to SCK rising edge t 10 ns

SPI SI Data hold time after SCK rising edge t 10 ns

SCK high time t 25 ns

SCK low time t 25 ns

SO valid after SCK falling edge t 20 ns

SO high-impedance after inactive t 75 ns

CES

CPH

SCKH

SCKL

CHZ

SERIAL OUTPUT TIMING DIAGRAM

SCLK

CHZ

Hi Impedance

SCKH

tDV

LSB

CPH

tSCKL

MSB Hi Impedance

SERIAL INPUT TIMING DIAGRAM

SCLK

MSB

CES

LSB

CPH

CEH

VDD = 3.3 V, GND = 0V, T = Operating Temperature Range (unless otherwise specified).A

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

PIN CONFIGURATION FOR HI-3200, 64-PIN QFN PACKAGE

Notes

1 . All VDD and GND pins must be connected.

2. See data sheet page 1 for HI-3200, 64-Pin PQFP Package Configuration.

HOLT INTEGRATED CIRCUITS

TOP VIEW

48 CMROUT

46 ATX0N

45 ATX0P

44 ATX1N

43 ATX1P

42 ATXSLP1

41 VDD

40 GND

39 COSC

38 ATXSLP2

37 ATX2N

36 ATX2P

35 ATX3N

34 ATX3P

33 ATXSLP3

47 ATXSLP0

ARX7P 17

ARX7N 18

MODE0 19

CMOSI 20

MODE1 21

MODE2 23

ARXBIT0 24

ARXBIT1 25

HMISO 26

HSCLK 27

HMOSI 28

CSCLK 30

MINT 31

MCLK 22

MINTACK 32

HCSB

AACK 1

CGP2 2

AINT 3

CSTAT 4

SCANSHIFT 5

ARX2N 6

ARX3P 7

VDD 8

GND 9

ARX3N 10

ARX4P 11

ARX4N 12

ARX5P 13

ARX5N 14

ARX6P 15

ARX6N 16

HI-3200PCx

64 ARX2P

61 ARX0N

60 ARX0P

59 SCANEN

58 CMISO

57 READY

56 ESCLK

55 EMOSI

53 EMISO

50 ATXMSK

49 MRST

63 ARX1N

62 ARX1P

RUN

ECSB

CCSB

HI-3200, HI-3201

PIN CONFIGURATION FOR HI-3201, 80-PIN PQFP PACKAGE

Notes

1 . All VDD and GND pins must be connected.

2. See data sheet page 1 for HI-3200, 64-Pin PQFP Package Configuration.

HOLT INTEGRATED CIRCUITS

HI-3201PQI

HI-3201PQT

AACK 1

ARXBIT6 2

CGP2 3

AINT 4

ARXBIT7 5

CSTAT 6

SCANSHIFT 7

ARX2N 8

ARX3P 9

VDD 10

VDD 11

GND 12

GND 13

ARX3N 14

ARX4P 15

ARX4N 16

ARX5P 17

ARX5N 18

ARX6P 19

ARX6N 20

60 CMROUT

59 ARXBIT3

58 ATXSLP0

57 ATX0N

56 ATX0P

55 ATX1N

54 ATX1P

53 ATXSLP1

52 VDD

51 VDD

50 GND

49 GND

48 COSC

47 ARXBIT2

46 ATXSLP2

45 ATX2N

44 ATX2P

43 ATX3N

42 ATX3P

41 ATXSLP3

80 ARX2P

79 ARX1N

78 ARX1P

77 ARX0N

76 ARX0P

75 SCANEN

74 ARXBIT5

73 CMISO

72 READY

71 VDD

70 GND

69 ESCLK

68 EMOSI

66 EMISO

65 RUN

63 ARXBIT4

62 ATXMSK

61 MRST

ECSB

CCSB

ARX7P 21

ARX7N 22

MODE0 23

CMOSI 24

MODE1 25

MCLK 26

MODE2 27

ARXBIT0 28

VDD 29

VDD 30

GND 31

GND 32

ARXBIT1 33

HMISO 34

HSCLK 35

HMOSI 36

CSCLK 38

MINT 39

MINTACK 40

HCSB

HI-3200, HI-3201

PART PACKAGE

NUMBER DESCRIPTION

PQ 64 THIN PIN PLASTIC QUAD FLAT PACK TQFP (64PQTS)

PC 64-PIN PLASTIC CHIP-SCALE PACKAGE QFN (64PCS)

PART TEMPERATURE BURN

NUMBER RANGE FLOW IN

I -40°C TO +85°C I No

T -55°C TO +125°C T No

M -55°C TO +125°C M Yes

PART PACKAGE

NUMBER DESCRIPTION

Blank Tin / Lead (Sn / Pb) Solder

F 100% Matte Tin (Pb-free RoHS compliant)

HI-3200xx x x

ORDERING INFORMATION

HOLT INTEGRATED CIRCUITS

PART TEMPERATURE BURN

NUMBER RANGE FLOW IN

I -40°C TO +85°C I No

T -55°C TO +125°C T No

M -55°C TO +125°C M Yes

PART PACKAGE

NUMBER DESCRIPTION

F 100% Matte Tin (Pb-free RoHS compliant)

HI-3201PQ Fx

HI-3200, HI-3201

PART PACKAGE

NUMBER DESCRIPTION

PQ 80 THIN PIN PLASTIC QUAD FLAT PACK TQFP (80PTQS)

Document Rev. Date Description of Change

DS3200 New 5/4/11 Initial Release.

A 1/25/12 Corrected typo in ordering information.

B 4/16/12 Corrected fonts in numerous block diagrams.

C 5/7/13 Added description for register 0x8035, “ARINC 429 TX Ready INT Enable”. Updated

QFN package dimensions.

D 8/13/13 Updated Programming for Auto-Initialization EEPROM section. Update Reflow Solder

Temperature.

E 10/21/13 Added description of ARINC 429 Receive Pending Interrupt Register, ARINC 429

Receive Interrupt Mask Register and ARINC 429 Receive Interrupt Address Registers.

F 11/4/13 Reverse direction of signals on EEPROM in Block Diagram and Examples 4, 5 and 8.

Add “bar” (active low) to CCSB, ECSB and HCSB signals in Pin Descriptions. Updated

PQFP-64, QFN-64 and PQFP-80 package drawings.

REVISION HISTORY

HOLT INTEGRATED CIRCUITS

HI-3200, HI-3201

HOLT INTEGRATED CIRCUITS

PACKAGE DIMENSIONS

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

9.00

(0.354) BSC

1.00

(0.039) max

0.20

(0.008) typ

0.50

(0.0197)BSC

0.25

(0.10) typ

0.40 ± 0.10

(0.016 )± 0.004

7.25 ± 0.50

(0.285 ± 0.020)

Bottom

View

Top View

9.00

(0.354) BSC

Package Type: 64PCS

millimeters (inches)

64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)

Electrically isolated heat

sink pad on bottom of

package

Connect to any ground or

power plane for optimum

thermal dissipation

7.25 ± 0.50

(0.285 )± 0.020

64 PIN PLASTIC QUAD FLAT PACK (PQFP) millimeters (inches)

Package Type: 64PQTS

12.00

(0.472) BSC SQ

1.60

(0.063

0.50

(0.0197)

0.22 0.05±

(0.009 ± 0.002)

0.20

(0.008)

.1.40 0.05±

(0.055 ± 0.002)

0.10 0.05±

(0.004 ± 0.002)

10.00

(0.394)

See Detail A

Detail A

0° 7°£ Q £

BSC SQ

max

R max

0.08

(0.003)R min

BSC

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

HOLT INTEGRATED CIRCUITS

PACKAGE DIMENSIONS

80 PIN PLASTIC QUAD FLAT PACK (PQFP) millimeters (inches)

Package Type: 80PTQS

12.00

(0.472) BSC SQ

1.60

(0.630)

0.40

(0.0157)

0.22 0.05±

(0.009 ± 0.002)

0.60 .15±0

(0.024 .006)±0

1.40 0.05±

(0.055 ± 0.002)

0.10 0.05±

(0.004 ± 0.002)

10.00

(0.394)

See Detail A

Detail A

BSC SQ

max

BSC

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)