OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
1.5A, 24V, 17MHz
POWER OPERATIONAL AMPLIFIER
Check for Samples: OPA564-Q1
1FEATURES DESCRIPTION
23•Qualified for Automotive Applications The OPA564-Q1 is a low-cost, high-current
•High Output Current: 1.5A operational amplifier that is ideal for driving up to
•Wide Power-Supply Range: 1.5A into reactive loads. The high slew rate provides
–Single Supply: +7V to +24V 1.3MHz full-power bandwidth and excellent linearity.
–Dual Supply: ±3.5V to ±12V These monolithic integrated circuits provide high
reliability in demanding powerline communications
•Large Output Swing: 20VPP at 1.5A and motor control applications.
•Fully Protected: The OPA564-Q1 operates from a single supply of 7V
–Thermal Shutdown to 24V, or dual power supplies of ±3.5V to ±12V. In
–Adjustable Current Limit single-supply operation, the input common-mode
•Diagnostic Flags: range extends to the negative supply. At maximum
–Over-Current output current, a wide output swing provides a 20VPP
–Thermal Shutdown (IOUT = 1.5A) capability with a nominal 24V supply.
•Output ENABLE/SHUTDOWN Control The OPA564-Q1 is internally protected against
•High Speed: over-temperature conditions and current overloads. It
is designed to provide an accurate, user-selected
–Gain-Bandwidth Product: 17MHz current limit. Two flag outputs are provided; one
–Full-Power Bandwidth at 10VPP: 1.3MHz indicates current limit and the second shows a
–Slew Rate: 40V/μsthermal over-temperature condition. It also has an
•Diode for Junction Temperature Monitoring Enable/Shutdown pin that can be forced low to shut
•HSOP-20 PowerPAD™Package down the output, effectively disconnecting the load.
(Bottom- and Top-Side Thermal Pad Versions) The OPA564-Q1 is housed in a thermally-enhanced,
surface-mount PowerPAD™package (HSOP-20) with
APPLICATIONS the choice of the thermal pad on either the top side or
•Powerline Communications the bottom side of the package.
•Valve, Actuator Driver OPA564-Q1 RELATED PRODUCTS
•VCOM Driver FEATURES DEVICE
•Motor Driver Zerø-Drift PGA with 2-Channel Input Mux and
•Audio Power Amplifier PGA112
SPI
•Power-Supply Output Amplifier Zerø-Drift Operational Amplifier, 50MHz, RRI/O, OPA365
•Test Equipment Amplifier Single-Supply
Quad Operational Amplifier, JFET Input , Low
•Transducer Excitation TL074
Noise
•Laser Diode Driver Power Operational Amplifier, 1.2A, 15V, OPA561
•General-Purpose Linear Power Booster 17MHz, 50V/μs
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments, Inc.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PACKAGE
PRODUCT PACKAGE-LEAD DESIGNATOR PACKAGE MARKING
HSOP-20 (PowerPAD on bottom) DWP OPA564AQ
OPA564-Q1 HSOP-20 (PowerPAD on top) DWD PREVIEW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted). OPA564-Q1 UNIT
Supply Voltage, VS= (V+) –(V–) +26 V
Voltage(2) (V–)–0.4 to (V+)+0.4 V
Signal Input Current Through ESD Diodes(2) ±10 mA
Terminals Maximum Differential Voltage Across Inputs(3) 0.5 V
Voltage (V–)–0.4 to (V+)+0.4 V
Signal Output
Terminals Current(4) ±10 mA
Output Short-Circuit(5) Continuous
Operating Junction Temperature, TJ–40 to +125 °C
Storage Temperature, TA–55 to +150 °C
Junction Temperature, TJ+150 °C
Latch-up per JESD78B Class 1 Level B
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Input terminals are diode-clamped to the power-supply rails. Signals that can swing more than 0.4V beyond the supply rails should be
current limited to 10mA or less.
(3) Refer to Figure 43 for information on input protection. See Input Protection section.
(4) Output terminals are diode-clamped to the power-supply rails. Input signals forcing the output terminal more than 0.4V beyond the
supply rails should be current limited to 10mA or less.
(5) Short-circuit to ground within SOA. See Power Dissipation and Safe Operating Area for more information.
2Copyright ©2011, Texas Instruments Incorporated
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
ELECTRICAL CHARACTERISTICS
At TCASE = +25°C, VS=±12V, RLOAD = 20kΩto GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted.
OPA564-Q1
PARAMETERS CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Input Offset Voltage VOS VCM = 0V ±2±20 mV
vs Temperature dVOS/dT TA=–40°C to 125°C±10 μV/°C
vs Power Supply PSRR VCM = 0V, VS=±3.5V to ±13V 10 150 μV/V
INPUT BIAS CURRENT
Input Bias Current(1) IBVCM = 0V 10 100 pA
vs Temperature TA=–40°C to 125°C See Figure 10,Typical Characteristics
Input Offset Current(1) IOS 10 100 pA
NOISE
Input Voltage Noise Density enf = 1kHz 102.8 nV/√Hz
f = 10kHz 20 nV/√Hz
f = 100kHz 8 nV/√Hz
Input Current Noise Inf = 1kHz 4 fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range: VCM Linear Operation (V–) (V+)–3 V
Common-Mode Rejection Ratio CMRR VCM = (V–) to (V+)–3V 70 80 dB
vs Temperature TA=–40°C to 125°C See Figure 9,Typical Characteristics
INPUT IMPEDANCE
Differential Ω|| pF
1012 || 16
Common-Mode Ω|| pF
1012 || 9
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL VOUT = 20VPP, RLOAD = 1kΩ80 108 dB
VOUT = 20VPP, RLOAD = 10Ω93 dB
FREQUENCY RESPONSE
Gain-Bandwidth Product(1) GBW RLOAD = 5Ω17 MHz
Slew Rate SR G = 1, 10V Step 40 V/μs
Full Power Bandwidth G = +2, VOUT = 10VPP 1.3 MHz
Settling Time ±0.1% G = +1, 10V Step, CLOAD = 100pF 0.6 μs
±0.01% G = +1, 10V Step, CLOAD = 100pF 0.8 μs
Total Harmonic Distortion + Noise THD+N f = 1kHz, RLOAD = 5Ω, G = +1, VOUT = 5VP0.003 %
OUTPUT
Voltage Output: VOUT
Positive IOUT = 0.5A (V+)–1 (V+)–0.4 V
Negative IOUT =–0.5A (V–)+1 (V–)+0.3 V
Positive IOUT = 1.5A (V+)–2 (V+)–1.5 V
Negative IOUT =–1.5A (V–)+2 (V–)+1.1 V
(1) See Typical Characteristics.
Copyright ©2011, Texas Instruments Incorporated 3
I 20000 x
LIM @1.2V
5000 + RSET
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At TCASE = +25°C, VS=±12V, RLOAD = 20kΩto GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted.
OPA564-Q1
PARAMETERS CONDITIONS MIN TYP MAX UNIT
OUTPUT, continued
Maximum Continuous Current, dc IOUT 1.5(2) A
Output Impedance, closed loop ROf = 100kHz 10 Ω
Output Impedance, open loop ZOG = +2, f = 100kHz See Figure 24,Typical Characteristics
Output Current Limit Range(3) ±0.4 to ±2.0 A
Current Limit Equation ILIM A
(4) (5)
Solved for RSET (Current Limit) RSET ≅(24k/ILIM)–5kΩ Ω
Current Limit Accuracy ILIM = 1.5A 10 %
Current Limit Overshoot(6) (7) VIN = 5V Pulse (200ns tr), G = +2 50 %
Output Shut Down
Output Impedance(8) 6 || 120 GΩ|| pF
Capacitive Load Drive CLOAD See Figure 6,Typical Characteristics
DIGITAL CONTROL
Enable/Shutdown Mode INPUT VDIG = +3.3V to +5.5V referenced to V–
VE/S High (output enabled) E/S Pin Open or Forced High (V–)+2 (V–)+VDIG V
VE/S Low (output shut down) E/S Pin Forced Low (V–) (V–)+0.8 V
IE/S High (output enabled) E/S Pin Indicates High 10 μA
IE/S Low (output shut down) E/S Pin Indicates Low 1 μA
Output Shutdown Time 1 μs
Output Enable Time 3 μs
Current Limit Flag Output
Normal Operation Sinking 10μA 0 (V–)+0.8 V
Current-Limited Sourcing 20μA (V–)+2 VDIG V
Thermal Shutdown
Normal Operation Sinking 200μA 0 (V–)+0.8 V
Thermally Shutdown(9) Sourcing 200μA (V–)+2 VDIG V
+140 to
Junction Temperature at Shutdown(10) °C
+157
Hysteresis(10) 15 to 19 °C
TSENSE
Diode Ideality Factor η1.033
(2) Under safe operating conditions. See Power Dissipation and Safe Operating Area for safe operating area (SOA) information.
(3) Minimum current limit is 0.4A. See Adjustable Current Limit in the Applications section.
(4) Quiescent current increases when the current limit is increased (see Typical Characteristics).
(5) RSET (current limit) can range from 55kΩ(IOUT = 400mA) to 10kΩ(IOUT = 1.6A typ). See Adjustable Current Limit in the Applications
section.
(6) See Typical Characteristics.
(7) Transient load transition time must be ≥200ns.
(8) See Enable/Shutdown (E/S) Pin in the Applications section.
(9) When sourcing, the VDIG supply must be able to supply the current.
(10) Characterized, but not production tested.
4Copyright ©2011, Texas Instruments Incorporated
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
ELECTRICAL CHARACTERISTICS (continued)
At TCASE = +25°C, VS=±12V, RLOAD = 20kΩto GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted.
OPA564-Q1
PARAMETERS CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY(11)
Specified Voltage Range VS±12 V
Operating Voltage Range 7 24 V
Quiescent Current(12) IQIOUT = 0 39 50 mA
Over Temperature TA=–40°C to 125°C 50 mA
Quiescent Current in Shutdown Mode IQSD 5 mA
Specified Voltage for Digital VDIG (V–) + 3.0 (V–) + 5.5 V
Digital Quiescent Current IDIG VDIG = 5V 43 100 μA
TEMPERATURE RANGE
Operating Range –40 +125(13) °C
Thermal Resistance
HSOP-20 DWP PowerPAD (Pad Down) θJA High K Board 33 °C/W
θJC 50 °C/W
θJP 1.83 °C/W
θJB 22 °C/W
HSOP-20 DWD PowerPAD (Pad Up)(14) θJA High K Board 45.5 °C/W
θJC 6.3 °C/W
θJB 22 °C/W
(11) Power-supply sequencing requirements must be observed. See Power Supplies section for more information.
(12) Quiescent current increases when the current limit is increased (see Typical Characteristics).
(13) The OPA564-Q1 typically goes into thermal shutdown at a junction temperature above +140°C.
(14) Thermal modeling of the DWD-20 package was done based on a 1-inch AAVID Thermalloy heatsink (Thermalloy part no. 65810).
Copyright ©2011, Texas Instruments Incorporated 5
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V-
V+PWR
V+PWR
V+PWR
VOUT
VOUT
V PWR-
V PWR-
TSENSE
V-
V-
V+
TFLAG
E/S
+IN
-IN
VDIG
IFLAG
ISET
V-
PowerPAD
HeatSink
(Locatedon
topside)
(2)
(2)PowerPADisinternallyconnectedtoV .-
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V-
V+
TFLAG
E/S
+IN
-IN
VDIG
IFLAG
ISET
V-
V-
V+PWR
V+PWR
V+PWR
VOUT
VOUT
V PWR-
V PWR-
TSENSE
V-
PowerPAD
HeatSink
(Locatedon
bottomside)
(1)
(1)PowerPADisinternallyconnectedtoV ,
Soldering the PowerPAD to the PCB is
always required, even with applications that
havelowpowerdissipation.
-
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
PIN CONFIGURATIONS
DWP PACKAGE DWD PACKAGE
PowerPAD on Bottom PowerPAD on Top
PIN DESCRIPTIONS
DWP DWD
(PAD DOWN) (PAD UP)
PIN NO. PIN NO. NAME DESCRIPTION
1, 10, 11, 20 1, 10, 11, 20 V– –Supply for Amplifier, PWR Out, and Metal PowerPAD
2 19 V+ +Supply for Signal Amplifier
Thermal Over Temperature Flag; flag is high when alarmed and device has
3 18 TFLAG gone into thermal shutdown.
4 17 E/S Enable/Shutdown Output Stage; take E/S low to shut down output
5 16 +IN Noninverting Op Amp Input
6 15 –IN Inverting Op Amp Input
+Supply for Digital Flag and E/S (referenced to V–).
7 14 VDIG Valid Range is (V–) + 3.0V ≤VDIG ≤(V–) + 5.5V.
8 13 IFLAG Current Limit Flag; Active High
9 12 ISET Current Limit Set (see Applications Section)
12 9 TSENSE Temperature Sense Pin for use with TMP411
13, 14 7, 8 V–PWR –Supply for Power Output Stage
15, 16 5, 6 VOUT Output Voltage; ROis high impedance when shut down
17, 18, 19 3, 4, 2 V+ PWR +Supply for Power Output Stage
6Copyright ©2011, Texas Instruments Incorporated
Enable/Shutdown
V-
Current
Limit
Flag
Thermal
Flag
VDIG
V+
Enable/Shutdown
Current
Limit
Flag
Thermal
Flag
VDIG
V+
-IN
+IN
OPA564AIDWP OPA564AIDWD
Current
Limit
Set
RSET
TSENSE
VOUT
(2)
(19)
(17, 18)
(6)
(5)
(1, 10, 11, 20)
(13, 14)
(7)
(3)
(8)
(4)
(12)
(9)
(15, 16)
V-
-IN
+IN
Current
Limit
Set
RSET
TSENSE
VOUT
(19)
(2)
(3, 4)
(15)
(16)
(1, 10, 11, 20)
(7, 8)
(14)
(18)
(13)
(17)
(9)
(12)
(5, 6)
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
FUNCTIONAL PIN DIAGRAM
Copyright ©2011, Texas Instruments Incorporated 7
14
12
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
0 0.2
Output Current (A)
Output Voltage (V)
1.60.4 0.6 0.8 1.0 1.2 1.4
V = 3.5V
S±
V = 12V
S±
+125 C°
+25 C°
- °40 C
R = 7.5k
SET W
1ms Current Pulses
V = 12V
S±
50
48
46
44
42
40
38
36
34
32
30
Quiescent Current (mA)
6 10 20 24
Supply Voltage (V)
8 12 14 16 18 22
R = 7.5k
SET W
R = 40k
SET W
R = 100k
SET W
2V/div
Time(250ns/div)
Input
Output
Unloaded
G=+1
V =9V
IN PP
2V/div
Time(250ns/div)
Input
Output
5 Load
G=+1
V =9V
W
IN PP
Time(250ns/div)
10mV/div
R =
C =0pF
LOAD
LOAD
NoLoad
G= 1
-
VOUT
VIN
60
50
40
30
20
10
0
Overshoot(%)
10 100 1k 10k 100k
Capacitance(pF)
V = 12V
S±G=+1
G=+10
G= 10-
G= 1-
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS
At TCASE = +25°C, VS=±12V, RLOAD = 20kΩto GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted.
QUIESCENT CURRENT vs SUPPLY VOLTAGE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
Figure 1. Figure 2.
LARGE−SIGNAL STEP RESPONSE, NO LOAD LARGE−SIGNAL STEP RESPONSE
Figure 3. Figure 4.
SMALL−SIGNAL STEP RESPONSE SMALL−SIGNAL OVERSHOOT vs LOAD CAPACITANCE
Figure 5. Figure 6.
8Copyright ©2011, Texas Instruments Incorporated
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
200-
InputBiasCurrent(pA)
-75 -50 -25 0 25 50 75 100 125
Temperature( C)
°
IB+
IB-
IOS
300
250
200
150
100
50
0
50
100
150
200
250
300
-
-
-
-
-
-
Common-ModeRejectionRatio,Power-Supply
RejectionRatio,Open-LoopGain( V/V)m
-75 -50 -25 0 25 50 75 100 125
Temperature( C)
°
CMRR PSRR
AOL
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
TYPICAL CHARACTERISTICS (continued)
At TCASE = +25°C, VS=±12V, RLOAD = 20kΩto GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted.
IQvs TEMPERATURE OFFSET VOLTAGE vs TEMPERATURE
Figure 7. Figure 8.
AOL, PSRR, AND CMRR vs TEMPERATURE IBvs TEMPERATURE
Figure 9. Figure 10.
IQ, SHUTDOWN vs TEMPERATURE IDIG vs TEMPERATURE
Figure 11. Figure 12.
Copyright ©2011, Texas Instruments Incorporated 9
120
100
80
60
40
20
0
Frequency(Hz)
Gain(dB)
0
-45
-90
-135
-180
Phase( )°
10k 100k 1M 10M 40M
V = 12V
R =1k
S
LOAD
±
W
Gain
Phase
10 100 1k
100
80
60
40
20
0
CMRR,PSRR(dB)
10 100 10k1k 100k
Frequency(Hz)
V = 12V
S±
CMRR
-PSRR
+PSRR
15.0
12.5
10.0
7.5
5.0
2.5
0
OutputVoltage(V )
PP
10k 100k 1M 10M 100M
Frequency(Hz)
10W
100W
V = 12V
G=+1
S±
25
20
15
10
5
0
OutputVoltage(V )
PP
10k 100k 1M 10M 100M
Frequency(Hz)
100W
10W
V = 12V
G=+1
S±
0.01 0.1 110 100
1
0.1
0.01
0.001
0.0001
TotalHarmonicDistortion+Noise(%)
R =10
LOAD W
R =5
LOAD W
R =60
LOAD WR =
NoLoad
LOAD
V Amplitude(V )
OUT P
V = 12V
S
f=1kHz
G=+1
±
0.01 0.1 110 100
1
0.1
0.01
0.001
0.0001
TotalHarmonicDistortion+Noise(%)
R =
10
LOAD
W
R =5
LOAD W
R =60
LOAD WR =
NoLoad
LOAD
V Amplitude(V )
OUT P
V = 12V
S
f=1kHz
G= 10-
±
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TCASE = +25°C, VS=±12V, RLOAD = 20kΩto GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted.
COMMON-MODE REJECTION RATIO AND
GAIN AND PHASE vs FREQUENCY POWER-SUPPLY REJECTION RATIO vs FREQUENCY
Figure 13. Figure 14.
OUTPUT VOLTAGE SWING vs FREQUENCY OUTPUT VOLTAGE SWING vs FREQUENCY
Figure 15. Figure 16.
TOTAL HARMONIC DISTORTION + NOISE vs AMPLITUDE TOTAL HARMONIC DISTORTION + NOISE vs AMPLITUDE
Figure 17. Figure 18.
10 Copyright ©2011, Texas Instruments Incorporated
0.01 0.1 110 100
V Amplitude(V )
OUT P
1
0.1
0.01
0.001
0.0001
TotalHarmonicDistortion+Noise(%)
V = 12V
S±
f=1kHz
G=+10
R =
10
LOAD
W
R =5
LOAD W
R =60
LOAD WR =
NoLoad
LOAD
10 100 1k 10k 100k
Frequency(Hz)
1
0.1
0.01
0.001
0.0001
TotalHarmonicDistortion+Noise(%)
G=+10
V =8V
OUT P
R =
LOAD 10W
R =
LOAD 5W
R =
LOAD 60W
R =
LOAD NoLoad
10 100 1k 10k 100k
Frequency(Hz)
1
0.1
0.01
0.001
0.0001
TotalHarmonicDistortion+Noise(%)
G= 10
V =8V
-
OUT P
R =
LOAD 10W
R =
LOAD 5W
R =
LOAD 60W
R =
LOAD
NoLoad
10 100 1k 10k 100k
Frequency(Hz)
1
0.1
0.01
0.001
0.0001
TotalHarmonicDistortion+Noise(%)
G=+1
V =5V
OUT P
R =
LOAD 10W
R =
LOAD 5W
R =
LOAD
60W
R =
LOAD
NoLoad
1k
100
10
1
1k
100
10
1
VoltageNoise(nV/ )Hz
Ö
CurrentNoise(fA/ )HzÖ
10 100 1k 10k 100k
Frequency(Hz)
V = 12V
S±
VoltageNoise
CurrentNoise
10k
1k
100
10
1
Impedance( )W
1 10 100 1k 10k 100k 1M 10M 100M
Frequency(Hz)
I =0Adc
OUT
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
TYPICAL CHARACTERISTICS (continued)
At TCASE = +25°C, VS=±12V, RLOAD = 20kΩto GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE vs AMPLITUDE TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
Figure 19. Figure 20.
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
Figure 21. Figure 22.
INPUT VOLTAGE SPECTRAL NOISE AND
CURRENT NOISE vs FREQUENCY OPEN-LOOP OUTPUT IMPEDANCE (No Load)
Figure 23. Figure 24.
Copyright ©2011, Texas Instruments Incorporated 11
10k
1k
100
10
1
0.1
0.01
Impedance( )W
10 100 1k 10k 100k 1M 10M 100M
Frequency(Hz)
I =0Adc
Gain=1V/V
OUT
50
40
30
20
10
0
10-
InputBiasCurrent(pA)
-12 -10 -8-6-4-202 4 6 8 10
Common-ModeVoltage(V )
CM
2V/div
Time(100ns/div)
R =10k
R =100
V = 6V
W
W
-
F
LOAD
OUT
VOUT
E/S
V-
0V
VOUT
CH1:
0V
CH2:
0V
E/S
Time(500 s/div)m
1V/div
R =100 ,G=+1
LOAD W
V =1V
IN
R =10k
R =100
V = 6V
W
W
-
F
LOAD
OUT
2V/div
Time(1 s/div)m
VOUT
E/S
V-
0V
60
50
40
30
20
10
0
10
20
30
40
-
-
-
-
Current Limit Error (%)
10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k
R ( )W
SET
Mean
Mean +3
Mean 3
s
- s
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TCASE = +25°C, VS=±12V, RLOAD = 20kΩto GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted.
INPUT BIAS CURRENT vs
CLOSED-LOOP OUTPUT IMPEDANCE (No Load) COMMON-MODE VOLTAGE
Figure 25. Figure 26.
ENABLE RESPONSE
RLOAD = 100ΩSHUTDOWN TIME (INVERTING CONFIGURATION)
Figure 27. Figure 28.
ENABLE TIME (INVERTING CONFIGURATION) CURRENT LIMIT PERCENT ERROR vs RSET
Figure 29. Figure 30.
12 Copyright ©2011, Texas Instruments Incorporated
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Output Current Limit (A)
10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k
R ( )W
SET
Mean
Mean 3
Mean +3
Calculated Value
- s
s
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Output Current Limit (A)
10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k
R ( )W
SET
Mean
Mean 3
Mean +3
Calculated Value
- s
s
5
4
3
2
1
0
I Increase (mA)
Q
5k 15k 25k 45k35k 55k 65k 75k
R ( )W
SET
Population
-18.0
-16.2
-14.4
-12.6
-10.8
-9.0
-7.2
-5.4
-3.6
-1.8
0
1.8
3.6
5.4
7.2
9.0
10.8
12.6
14.4
16.2
18.0
OffsetVoltage(mV)
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
TYPICAL CHARACTERISTICS (continued)
At TCASE = +25°C, VS=±12V, RLOAD = 20kΩto GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted.
OUTPUT CURRENT LIMIT vs RSET OUTPUT CURRENT LIMIT vs RSET
(SOURCING CURRENT) (SINKING CURRENT)
Figure 31. Figure 32.
QUIESCENT CURRENT INCREASE vs RSET OFFSET VOLTAGE PRODUCTION DISTRIBUTION
Figure 33. Figure 34.
Copyright ©2011, Texas Instruments Incorporated 13
E/S (2)
RSET
(1)
47 Fm
0.1 Fm
VO
VIN
V-
ISET
OPA564
47 Fm
0.1 Fm
VDIG
(3)
V+
Voltage(V)
Time(s)
Voltage(V)
Time(s)
Voltage(V)
Time(s)
(A) Sequencenotallowed(1)
(B) Sequenceallowed
(C) Sequenceallowed
VSUPPLY
VSUPPLY
VSUPPLY
VDIGITAL
VDIGITAL
VDIGITAL
SeeNote1
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
APPLICATION INFORMATION
Sequencing of power supplies must assure that the
BASIC CONFIGURATION digital supply voltage (VDIG) be applied before the
supply voltage to prevent damage to the OPA564-Q1.
Figure 35 shows the OPA564-Q1 connected as a Figure 36 shows acceptable versus unacceptable
basic noninverting amplifier. However, the power-supply sequencing.
OPA564-Q1 can be used in virtually any op amp
configuration.
Power-supply terminals should be bypassed with low
series impedance capacitors. The technique of using
ceramic and tantalum capacitors in parallel is
recommended. Power-supply wiring should have low
series impedance.
(1) RSET sets the current limit value from 0.4A to 1.5A.
(2) E/S pin forced low shuts down the output.
(3) VDIG must not exceed (V–) + 5.5V; see Figure 56 for examples
of generating a signal for VDIG.
Figure 35. Basic Noninverting Amplifier
POWER SUPPLIES
The OPA564-Q1 operates with excellent performance
from single (+7V to +24V) or dual (±3.5V to ±12V)
analog supplies and a digital supply of +3.3V to
+5.5V (referenced to the V–pin). Note that the
analog power-supply voltages do not need to be
symmetrical, as long as the total voltage remains
below 24V. For example, the positive supply could be
set to 14V with the negative supply at –10V. Most (1) The power-supply sequence illustrated in (A) is not allowed.
behaviors remain constant across the operating This power-supply sequence causes damage to the device.
voltage range. Parameters that vary significantly with
operating voltage are shown in the Typical Figure 36. Power-Supply Sequencing
Characteristics.
14 Copyright ©2011, Texas Instruments Incorporated
RSET @24k
I
W
LIM
-5kW
I 20000 x
LIM @1.2V
5000 + RSET
I 20,000
LIM ISET
@ ´
RSET
OPA564
5kW
ILIM @1.2V
R + 5kW
CL
( ) ´20k
V-
ISET
1.2V
Bandgap
I I
OUT LIM
£
1nF
(optional, for noisy
environments)
(1)
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
Setting the Current Limit
ADJUSTABLE CURRENT LIMIT Leaving the ISET pin unconnected damages the
The OPA564-Q1 provides over-current protection to device. Connecting ISET directly to V–is not
the load through its accurate, user-adjustable current recommended because it programs the current limit
limit (ISET pin). The current limit value, ILIM, can be set far beyond the 1.5A capability of the device and
from 0.4A to 1.5A by controlling the current through causes excess power dissipation. The minimum
the ISET pin. Setting the current limit does not require recommended value for RSET is 7.5kΩ, which
special power resistors. The output current does not programs the maximum current limit to approximately
flow through the ISET pin. 1.9A. The maximum value for RSET is 55kΩ, which
A simple resistor to the negative rail is sufficient for a programs the minimum current limit to approximately
general, coarse limit of the output current. Figure 30 0.4A. The simplest method for adjusting the current
exhibits the percent of error in the transfer function limit (ILIM) uses a resistor or potentiometer connected
between ISET and IOUT versus the current limit set between the ISET pin and V–, according to Equation 1.
resistor, RSET;Figure 31 and Figure 32 show how this If ILIM has been defined, RSET can be solved by
error translates to variation in IOUT versus RSET. The rearranging Equation 1 into Equation 3:
dotted line represents the ideal output current setting
which is determined by the following equation:
(3)
(1) RSET in combination with a 5kΩinternal resistor
determines the magnitude of a small current that sets
The mismatch errors between the current limit set the desired output current limit.
mirror and the output stage are primarily a result of
variations in the ~1.2V bandgap reference, an internal Figure 37 shows a simplified schematic of the
5kΩresistor, the mismatch between the current limit OPA564-Q1 current limit architecture.
and the output stage mirror, and the tolerance and
temperature coefficient of the RSET resistor
referenced to the negative rail. Additionally, an
increase in junction temperature can induce added
mismatch in accuracy between the ISET and IOUT
mirror. See Figure 53 for a method that can be used
to dynamically change the current limit setting using a
simple, zero drift current source. This approach
simplifies the current limit equation to the following:
(2)
The current into the ISET pin is determined by the
NPN current source. Therefore, the errors contributed
by the internal 1.2V bandgap reference and the 5kΩ
resistor mismatch are eliminated, thus improving the
overall accuracy of the transfer function. In this case,
the primary source of error in ISET is the RSET resistor
tolerance and the beta of the NPN transistor.
It is important to note that the primary intent of the
current limit on the OPA564-Q1 is coarse protection (1) At power-on, this capacitor is not charged. Therefore, the
of the output stage; therefore, the user should OPA564-Q1 is programmed for maximum output current. Capacitor
exercise caution when attempting to control the values >1nF are not recommended.
output current by dynamically toggling the current Figure 37. Adjustable Current Limit
limit setting. Predictable performance is better
achieved by controlling the output voltage through the
feedback loop of the OPA564-Q1.
Copyright ©2011, Texas Instruments Incorporated 15
Optocoupler
4N38
E/S
V+
(a) +5V (b) HCTorTTLIn
HCTor
TTLIn
(a) (b)
OPA564
(1)
V-
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
ENABLE/SHUTDOWN (E/S) PIN logic signal and the OPA564-Q1 shutdown pin are
referenced to the same potential. In this configuration,
The output of the OPA564-Q1 shuts down when the the logic pin and the OPA564-Q1 enable can simply
E/S pin is forced low. For normal operation (output be connected together. Shutdown occurs for voltage
enabled), the E/S pin must be pulled high (at least 2V levels of less than 0.8V. The OPA564-Q1 is enabled
above V–). To enable the OPA564-Q1 permanently, at logic levels greater than 2V. In dual-supply
the E/S pin can be left unconnected. The E/S pin has operation, the logic pin remains referenced to a logic
an internal 100kΩpull-up resistor. When the output is ground. However, the shutdown pin of the
shut down, the output impedance of the OPA564-Q1 OPA564-Q1 continues to be referenced to V–.
is 6GΩ|| 120pF. The output shutdown output voltage
versus output current is shown in Figure 42. Although Thus, in a dual-supply system, to shut down the
the output is high-impedance when shut down, there OPA564-Q1 the voltage level of the logic signal must
is still a path through the feedback network into the be level-shifted by some means. One way to shift the
input stage to ground; see Figure 43. To prevent logic signal voltage level is by using an optocoupler,
damage to the OPA564-Q1, ensure that the voltage as Figure 38 shows.
across the input terminals +IN and –IN does not
exceed 0.5V, and that the current flowing through the
input terminals does not exceed 10mA when
operated beyond the supply rails, V–and V+. Refer
to the Input Protection section.
Input Protection
Electrostatic discharge (ESD) protection followed by
back-to-back diodes and input resistors (see
Figure 43) are used for input protection on the
OPA564-Q1. Exceeding the turn-on threshold of
these diodes, as in a pulse condition, can cause
current to flow through the input protection diodes
because of the finite slew rate of the amplifier. If the
input current is not limited, the back-to-back diodes
and the input devices can be destroyed. Sources of
high input current can also cause subtle damage to
the amplifier. Although the unit may still be functional, (1) Optional; may be required to limit leakage current of
important parameters such as input offset voltage, optocoupler at high temperatures.
drift, and noise may shift. Figure 38. Shutdown Configuration for Dual
When using the OPA564-Q1 as a unity-gain buffer Supplies (Using Optocoupler)
(follower), as an inverting amplifier, or in shutdown
mode, the input voltage between the input terminals
(+IN and –IN) must be limited so that the voltage To shut down the output, the E/S pin is pulled low, no
does not exceed 0.5V. This condition must be greater than 0.8V above V–. This function can be
maintained across the entire common-mode range used to conserve power during idle periods. To return
from V–to V+. If the inputs are taken above either the output to an enabled state, the E/S pin should be
supply rail, the current must be limited to 10mA pulled to at least 2.0V above V–.Figure 27 shows the
through the ESD protection diodes. During excursions typical enable and shutdown response times. It
past the rails, it is still necessary to limit the voltage should be noted that the E/S pin does not affect the
across the input terminals. If necessary, external internal thermal shutdown.
back-to-back diodes should be added between +IN When the OPA564-Q1 will be used in applications
and –IN to maintain the 0.5V requirement between where the device shuts down, special care should be
these connections. taken with respect to input protection. Consider the
following two examples.
Output Shutdown
The shutdown pin (E/S) is referenced to the negative
supply (V–). Therefore, shutdown operation is slightly
different in single-supply and dual-supply
applications. In single-supply operation, V–typically
equals common ground. Therefore, the shutdown
16 Copyright ©2011, Texas Instruments Incorporated
1.6kW
1.6kW
100W
6GW120pF
V+
V+
V+
V+
V-
V-
V-
V-VOUT
I1I2
+IN
-IN
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
Figure 39 shows the amplifier in a follower When the device shuts down in this situation, the load
configuration. The load is connected midway between pulls VOUT to ground. Little or no current then flows
the supplies, V+ and V–. through the input of the OPA564-Q1.
Figure 39. Shutdown Equivalent Circuit with Load Connected Midway Between Supplies
Copyright ©2011, Texas Instruments Incorporated 17
1.6kW
1.6kW
100W
6GW120pF
V+
V+
V+
V+
V-
V-
V-
V-VOUT
I1I2
+IN
-IN
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
Now consider Figure 40. Here, the load is connected This current flow produces a voltage across the
to V–. When the device shuts down, current flows inputs which is much greater than 0.5V, which
from the positive input +IN through the first 1.6kΩdamages the OPA564-Q1. A similar problem would
resistor through an input protection diode, then occur if the load is connected to the positive supply.
through the second 1.6kΩresistor, and finally through
the 100Ωresistor to V–.
CAUTION
This configuration damages the device.
Figure 40. Shutdown Equivalent Circuit with Load Connected to V–:
Voltage Across Inputs During DIsable Exceeds Input Requirements
18 Copyright ©2011, Texas Instruments Incorporated
1.6kW
1.6kW
100W
6GW120pF
V+
V+
V+
V+
V-
V-
V-
V-VOUT
I1I2
+IN
-IN
External protection diodes
required; use Skyworks
Solutions Inc. # SMS3922-004LF
or equivalent
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
The solution is to place external protection diodes
across the OPA564-Q1 input. Figure 41 illustrates
this configuration.
NOTE
This configuration protects the input during shutdown.
Figure 41. Shutdown Equivalent Circuit with Load Connected to V–:
Protected Input Configuration
Copyright ©2011, Texas Instruments Incorporated 19
500
450
400
350
300
250
200
150
100
50
0
OutputCurrent(pA)
-10 -8-6-4-2 0 2 46 8 10
OutputVoltage(V)
V = 12V
S±
OUTPUTSHUTDOWNOUTPUTVOLTAGEvsOUTPUTCURRENT
OPA564
E/ =Low(OutputShutdown)S
VOUT
IOUT
TestCircuit
RF
1.6kW
1.6kW
6GW
R1
120pF
V+
V+
V+
V+
V-
V-
V-
V-VOUT
External protection
diodes as needed
I1I2
+IN
-IN
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
Ensuring Microcontroller Compatibility within the optocoupler. A high logic level causes the
OPA564-Q1 to be enabled, and a low logic level
Not all microcontrollers output the same logic state shuts the OPA564-Q1 down. In the configuration of
after power-up or reset. 8051-type microcontrollers, Figure 38(b), with the logic signal applied on the
for example, output logic high levels while other anode side, a high level causes the OPA564-Q1 to
models power up with logic low levels after reset. In shut down, and a low level enables the op amp.
the configuration of Figure 38(a), the shutdown signal
is applied on the cathode side of the photodiode
Figure 42. Output Shutdown Output Impedance
Figure 43. OPA564-Q1: Output Shutdown Equivalent Circuit (with External Feedback)
20 Copyright ©2011, Texas Instruments Incorporated
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
MaxI (A)
OUT
-50 -25 0 25 50 75 100 125
T ( C)
J°
MaxI (dc)
MaxI (RMS)
OUT
OUT
MAXIMUMOUTPUTCURRENTvsJUNCTIONTEMPERATURE
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
CURRENT LIMIT FLAG Depending on load and signal conditions, the thermal
protection circuit may cycle on and off. This cycling
The OPA564-Q1 features a current limit flag (IFLAG)limits the amplifier dissipation, but may have
that can be monitored to determine if the load current undesirable effects on the load. Any tendency to
is operating within or exceeding the current limit set activate the thermal protection circuit indicates
by the user. The output signal of IFLAG is compatible excessive power dissipation or an inadequate
with standard CMOS logic and is referenced to the heatsink. For reliable, long-term, continuous
negative supply pin (V–). A voltage level of + 0.8V or operation, with IOUT at the maximum output of 1.5A,
less with respect to V–indicates that the amplifier is the junction temperature should be limited to +85°C
operating within the limits set by the user. A voltage maximum. Figure 44 shows the maximum output
level of +2.0V or greater with respect to V–indicates current versus junction temperature for dc and RMS
that the OPA564-Q1 is operating above (exceeds) the signal outputs. To estimate the margin of safety in a
current limit set by the user. See Setting the Current complete design (including heatsink), increase the
Limit for proper current limit operation. ambient temperature until the thermal protection
triggers. Use worst-case loading and signal
OUTPUT STAGE COMPENSATION conditions. For good, long-term reliability, thermal
protection should trigger more than 35°C above the
The complex load impedances common in power op maximum expected ambient condition of the
amp applications can cause output stage instability. application.
For normal operation, output compensation circuitry is
typically not required. However, if the OPA564-Q1 is The internal protection circuitry of the OPA564-Q1
intended to be driven into current limit, an R/C was designed to protect against overload conditions;
network (snubber) may be required. A snubber circuit it was not intended to replace proper heatsinking.
such as the one shown in Figure 54 may also Continuously running the OPA564-Q1 into thermal
enhance stability when driving large capacitive loads shutdown degrades reliability.
(greater than 1000pF) or inductive loads (for
example, motors or loads separated from the
amplifier by long cables). Typically, 3Ωto 10Ωin
series with 0.01μF to 0.1μF is adequate. Some
variations in circuit value may be required with certain
loads.
OUTPUT PROTECTION
The output structure of the OPA564-Q1 includes ESD
diodes (see Figure 43). Voltage at the OPA564-Q1
output must not be allowed to go more than 0.4V
beyond either supply rail to avoid damaging the
device. Reactive and electromagnetic field
(EMF)-generation loads can return load current to the
amplifier, causing the output voltage to exceed the
power-supply voltage. This damaging condition can
be avoided with clamping diodes from the output
terminal to the power supplies, as Figure 54 and Figure 44. Maximum Output Current vs Junction
Figure 55 illustrate. Schottky rectifier diodes with a 3A Temperature
or greater continuous rating are recommended.
THERMAL PROTECTION USING TSENSE FOR MEASURING JUNCTION
The OPA564-Q1 has thermal sensing circuitry that TEMPERATURE
helps protect the amplifier from exceeding The OPA564-Q1 includes an internal diode for
temperature limits. Power dissipated in the junction temperature monitoring. The η-factor of this
OPA564-Q1 causes the junction temperature to rise. diode is 1.033. Measuring the OPA564-Q1 junction
Internal thermal shutdown circuitry disables the temperature can be accomplished by connecting the
output when the die temperature reaches the thermal TSENSE pin to a remote-junction temperature sensor,
shutdown temperature limit. The OPA564-Q1 output such as the TMP411 (see Figure 57).
remains shut down until the die has cooled
sufficiently; see the Electrical Characteristics,
Thermal Shutdown section.
Copyright ©2011, Texas Instruments Incorporated 21
10.0
1.0
0.1
OutputCurrent(A)
0 2 46 8 10 12 14 16 18 20 22 24 26
(V+) V , (V )(V)-OUT VOUT - -
SAFEOPERATINGAREAATROOMTEMPERATURE
Copper,Soldered
withoutForcedAir
Copper,Soldered
with200LFMAirflow
10.0
1.0
0.1
0.01
OutputCurrent(A)
0 2 46 8 10 12 14 16 18 20 22 24 26
SAFEOPERATINGAREAATVARIOUSAMBIENTTEMPERATURES
(PowerPADSoldered)
T = 40 C-
A
T =0 C
T =+25 C
T =+85 C
T =+125 C
A
A
A
A
°
°
°
°
°
(V+) V , (V )(V)-OUT VOUT - -
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
POWER DISSIPATION AND SAFE Once the heatsink area has been selected,
OPERATING AREA worst-case load conditions should be tested to ensure
proper thermal protection.
Power dissipation depends on power supply, signal,
and load conditions. For dc signals, power dissipation space
is equal to the product of output current (IOUT) and the
voltage across the conducting output transistor
[(V+) –VOUT when sourcing; VOUT –(V–) when
sinking]. Dissipation with ac signals is lower.
Application Bulletin AB-039, Power Amplifier Stress
and Power Handling Limitations (SBOA022, available
for download from www.ti.com) explains how to
calculate or measure power dissipation with unusual
signals and loads.
Figure 45 shows the safe operating area at room
temperature with various heatsinking efforts. Note
that the safe output current decreases as (V+) –VOUT
or VOUT –(V–) increases. Figure 46 shows the safe
operating area at various temperatures with the
PowerPAD being soldered to a 2oz copper pad.
The power that can be safely dissipated in the
package is related to the ambient temperature and Figure 45. Safe Operating Area at Room
the heatsink design. The PowerPAD package was Temperature
specifically designed to provide excellent power
dissipation, but board layout greatly influences the
heat dissipation of the package. Refer to the
Thermally-Enhanced PowerPAD Package section for
further details.
The relationship between thermal resistance and
power dissipation can be expressed as:
TJ= TA+ TJA
TJA = PD× θJA
Combining these equations produces:
TJ= TA+ PD× θJA
where:
TJ= Junction temperature (°C)
TA= Ambient temperature (°C)
θJA = Junction-to-ambient thermal resistance (°C/W) PowerPAD soldered to a 2oz copper pad.
PD= Power dissipation (W) Figure 46. Safe Operating Area at Various
Ambient Temperatures
To determine the required heatsink area, required
power dissipation should be calculated and the
relationship between power dissipation and thermal
resistance should be considered to minimize
shutdown conditions and allow for proper long-term
operation (junction temperature of +85°C or less).
22 Copyright ©2011, Texas Instruments Incorporated
45
40
35
30
25
20
ThermalResistance, ( C/W)°
JA
0 1
q
2 3 4 5
CopperArea(inches )
2
OPA564
SurfaceMountPackage
2ozcopper
THERMALRESISTANCEvsCIRCUITBOARDCOPPERAREA
6
5
4
3
2
1
0
PowerDissipationinPackage(W)
0 25 50 75 100 125
Temperature( C)
°
NoCopper
Copper,Soldered
withoutForcedAir
Copper,Soldered
with200LFMAirflow
MAXIMUMPOWERDISSIPATIONvsTEMPERATURE
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
For applications with limited board size, refer to THERMALLY-ENHANCED PowerPAD
Figure 47 for the approximate thermal resistance PACKAGE
relative to heatsink area. Increasing heatsink area The OPA564-Q1 uses the HSOP-20 PowerPAD DWP
beyond 2in2provides little improvement in thermal and DWD packages, which are thermally-enhanced,
resistance. To achieve the 33°C/W shown in the standard size IC packages. These packages enhance
Electrical Characteristics, a 2oz copper plane size of power dissipation capability significantly and can be
9in2was used. The PowerPAD package is well-suited easily mounted using standard printed circuit board
for continuous power levels from 2W to 4W, (PCB) assembly techniques, and can be removed
depending on ambient temperature and heatsink and replaced using standard repair procedures.
area. The addition of airflow also influences maximum
power dissipation, as Figure 48 illustrates. Higher The DWP PowerPAD package is designed so that
power levels may be achieved in applications with a the leadframe die pad (or thermal pad) is exposed on
low on/off duty cycle, such as remote meter reading. the bottom of the IC, as shown in Figure 49a; the
DWD PowerPAD package has the exposed pad on
the top side of the package, as shown in Figure 49b.
The thermal pad provides an extremely low thermal
resistance (θJC) path between the die and the exterior
of the package.
PowerPAD packages with exposed pad down are
designed to be soldered directly to the PCB, using
the PCB as a heatsink. Texas Instruments does not
recommend the use of the of a PowerPAD package
without soldering it to the PCB because of the risk of
lower thermal performance and mechanical integrity.
In addition, through the use of thermal vias, the
bottom-side thermal pad can be directly connected to
a power plane or special heatsink structure designed
into the PCB. The PowerPAD should be at the same
voltage potential as V–. Soldering the bottom-side
PowerPAD to the PCB is always required, even with
applications that have low power dissipation. It
Figure 47. Thermal Resistance vs Circuit Board provides the necessary thermal and mechanical
Copper Area connection between the leadframe die and the PCB.
Pad-up PowerPAD packages should have
appropriately designed heatsinks attached. Because
of the variation and flexible nature of this type of heat
sink, additional details should come from the specific
manufacturer of the heatsink.
Figure 48. Maximum Power Dissipation vs
Temperature
Copyright ©2011, Texas Instruments Incorporated 23
Mold Compound (Epoxy)
Leadframe Die Pad
Exposed at Base of the Package
Leadframe (Copper Alloy)
(a) DWP PowerPAD cross-section view (b) DWD PowerPAD cross-section view
IC (Silicon) Die Attach (Epoxy)
Board
External Heatspreader
Power Transistor
Chip
Die
Attach
Thermal
Paste
Die
Pad
WeborSpokeViaSolidVia
NOTRECOMMENDEDRECOMMENDED
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
Figure 49. Cross-Section Views
holes under the PowerPAD package should be
Bottom-Side PowerPAD Assembly Process connected to the internal plane with a complete
1. The PowerPAD must be connected to the most connection around the entire circumference of the
negative supply of the device, V–. plated through-hole.
2. Prepare the PCB with a top side etch pattern, as 7. The top-side solder mask should leave exposed
shown in the attached thermal land pattern the terminals of the package and the thermal pad
mechanical drawing. There should be etch for the area. The thermal pad area should leave the
leads as well as etch for the thermal land. 13mil holes exposed. The larger 25mil holes
outside the thermal pad area should be covered
3. Place the recommended number of holes (or with solder mask.
thermal vias) in the area of the thermal pad, as
seen in the attached thermal land pattern 8. Apply solder paste to the exposed thermal pad
mechanical drawing. These holes should be area and all of the package terminals.
13mils (.013in, or 330.2μm) in diameter. They are 9. With these preparatory steps completed, the
kept small so that solder wicking through the PowerPAD IC is simply placed in position and run
holes is not a problem during reflow. through the solder reflow operation as any
4. It is recommended, but not required, to place a standard surface-mount component. This
small number of the holes under the package and processing results in a part that is properly
outside the thermal pad area. These holes installed.
provide an additional heat path between the For detailed information on the PowerPAD package
copper land and ground plane and are 25mils including thermal modeling considerations and repair
(.025in, or 635μm) in diameter. They may be procedures, see Technical Brief SLMA002,
larger because they are not in the area to be PowerPAD Thermally Enhanced Package, available
soldered, so wicking is not a problem. This at www.ti.com.
configuration is illustrated in the attached thermal
land pattern mechanical drawing.
5. Connect all holes, including those within the
thermal pad area and outside the pad area, to the
internal plane that is at the same voltage potential
as V–.
6. When connecting these holes to the internal
plane, do not use the typical web or spoke via
connection methodology (as Figure 50 shows).
Web connections have a high thermal resistance
connection that is useful for slowing the heat
transfer during soldering operations. This
configuration makes the soldering of vias that
have plane connections easier. However, in this Figure 50. Via Connection Methods
application, low thermal resistance is desired for
the most efficient heat transfer. Therefore, the
24 Copyright ©2011, Texas Instruments Incorporated
OPA564
ISET
47mF
R2
1kW
R1
20kW
R4
1kW
R4
20kW
R5
50mW
VO
-5V
+1V/+1A
VDIG +5V
0.1 Fm
0.1 Fm
47 Fm
RSET
R3
OPA564
C5
+
C6
R1
C1
C
10pF
4
RF
CF
C
47 Fm
3
C
0.1 Fm
2
34
6
1
T1
D1
(3)
SMBJ12CA
or
SMBJ6.0CA
VS
VDIG
INPUT
1/2 VS
E/S
GND
S2
(1)
R4
(4)
S1
(1) S3
(1)
S4
(1)
L1
(2)
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
APPLICATIONS CIRCUITS
The high output current and low supply of the
OPA564-Q1 make it a good candidate for driving
laser diodes and thermoelectric coolers. Figure 51
shows an improved Howland current pump circuit.
POWERLINE COMMUNICATION
Powerline communication (PLC) applications require
some form of signal transmission over an existing ac
power line. A common technique used to couple
these modulated signals to the line is through a signal
transformer. A power amplifier is often needed to
provide adequate levels of current and voltage to
drive the varying loads that exist on today’s
powerlines. One such application is shown in
Figure 52. The OPA564-Q1 is used to drive signals
used in frequency modulation schemes such as FSK
(Frequency-Shift Keying) or OFDM (Orthogonal
Frequency-Division Multiplexing) to transmit digital
information over the powerline. The power output
capabilities of the OPA564-Q1 are needed to drive
the current requirements of the transformer that is
shown in the figure, coupled to the ac power line via
a coupling capacitor. Circuit protection is often
needed or required to prevent excessive line voltages
(1) See Figure 35 for an example of a basic noninverting amplifier
with VDIG not exceeding 5.5V. or current surges from damaging the active circuitry
in the power amplifier and application circuitry.
Figure 51. Improved Howland Current Pump
(1) S1, S2, S3, and S4are Schottky diodes. S1and S2are B350 or equivalent. S3and S4are BAV99T or equivalent.
(2) L1should be small enough so that it does not interfere with the bandwidth of interest but large enough to suppress transients that could
damage the OPA564-Q1.
(3) D1is a transient suppression diode. For 24V supplies, use SMBJ12CA. For 12V supplies, use SMBJ6.0CA. Voltage rating of transient
voltage suppressor should be half the supply rating or less.
(4) The minimum recommended value for R4is 7.5kΩ.
Figure 52. Powerline Communication Line Coupling
Copyright ©2011, Texas Instruments Incorporated 25
R1RF
T1
2N2923
+
+5V
V+
V-
ISET
ISET
IOUT
VOUT
VIN
VSET
RLOAD
OPA564
OPA333
R
5k
SET
W
C
100pF
1
V
100mV
SET
V (1 + )
IN
R
R
F
1
RLOAD
I =
OUT £ILIM
I I
LIM SET
20,000
@ ´
ISET @I
20,000
LIM
ISET (0.4A to 1.5A) = 20 A to 75 Am m
VSET (0.4A to 1.5A) = 100mV to 375mV
and
G= -=-4
R2
R1
VIN
V+
VDIG
V-
R1
5kW
R2
20kW
OPA564
10W
(Non-
inductive) Motor
0.01 Fm
Z1
(1)
Z2
S2
S1
(1)
(2)
(2)
C
0.1 F
1
m
C
0.1 F
1
m
C
47 F
2
m
C
47 F
2
m
Note(3)
Note(3)
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
PROGRAMMABLE POWER SUPPLY For more information on this circuit, see the
Application Bulletin DC Motor Speed Controller:
Figure 53 shows the OPA333 used to control ISET in Control a DC Motor without Tachometer Feedback
order to adjust the current limit of the OPA564-Q1. (SBOA043), available for download at the TI web site.
Figure 54 shows a basic motor speed driver but does Figure 56 shows two examples of generating the
not include any control over the motor speed. For signal for VDIG.Figure 56auses an 1N4732A zener to
applications where good control of the speed of the bias the VDIG to precisely 4.7V above V–.Figure 56b
motor is desired, but the precision of a tachometer uses a high-voltage subregulator to derive the VDIG
control is not required, the circuit in Figure 55 voltage. Figure 58 illustrates a detailed powerline
provides control by using feedback of the current communication circuit.
consumption to adjust the motor drive.
Figure 53. Programmable Current Limit Option
(1) Z1, Z2= zener diodes (IN5246 or equivalent). Select Z1and Z2diodes that are capable of the maximum anticipated surge current.
(2) S1, S2= Schottky diodes (STPS1L40 or equivalent).
(3) C1= high-frequency bypass capacitors; C2= low-frequency bypass capacitors (minimum of 10μF for every 1A peak current)
Figure 54. Motor Drive Circuit
26 Copyright ©2011, Texas Instruments Incorporated
+12V
-12V
RM
R = 12W
M
dc
Motor
R2
10kW
R1
1kW
RSET
VIN
EMF
RS
1W
OPA564
VDIG
(1)
C
0.1 F
1
m
C
0.1 F
1
m
C
47 F
2
m
C
47 F
2
m
R
5k
3
W
Z2
S2
Z1
S1
(2)
(2)
(3)
(3)
Note (4)
Note (4)
V+
V-
VDIG
10kW
4.7V
Zener
1N4732A
(a) (b)
2
51
4
3
IN
C
1000 Fm
I1 C
100nF
I2 C
22 Fm
OUT
IIN
IRO
VRD
VOUT
IOUT
REXT
5kW
VIN
ID,c ID,d
IGND
VD
CD
47nF
DELAY
GND
RESET
OUT
TLE4275-Q1
OPA564-Q1
www.ti.com
SBOS567 –JUNE 2011
(1) IFLAG and TFLAG connections are not shown.
(2) Z1, Z2= zener diodes (IN5246 or equivalent). Select Z1and Z2diodes that are capable of the maximum anticipated surge current.
(3) S1, S2= Schottky diodes (STPS1L40 or equivalent).
(4) C1= high-frequency bypass capacitors; C2= low-frequency bypass capacitors (minimum of 10μF for every 1A peak current).
Figure 55. DC Motor Speed Controller (without Tachometer)
Figure 56. Circuits for Generating VDIG
Copyright ©2011, Texas Instruments Incorporated 27
TSENSE
50W
V-
50pF
D-
D+ SCL
SDA
ALERTTHERM2/
THERM
GND
V+
+5V
0.1 Fm10k
(typ)
W10k
(typ)
W10k
(typ)
W10k
(typ)
W
SMBus
Controller
Over-Temperature
Fault
OPA564
TMP411
1
8
7
6
4
5
3
2
-IN
V+
VDIG
+IN
VOUT
4
3
1
5
2
U5
OPA365
AVDD
1
CH1
2
CH0/VCAL
3
Vref
4
Vout
5GND 6
SCLK 7
DIO 8
NOT CS 9
DVDD 10
U10
PGA112
V-
1
V+
2
TFLG
3
E/S
4
+IN
5
-IN
6
VDIG
7
IFLAG
8
ISET
9
V-
10 V- 11
TSENSE 12
V-pwr 13
V-pwr 14
Vout 15
Vout 16
V+pwr 17
V+pwr 18
V+pwrSence 19
V- 20
Gnd
21
Gnd
22
Gnd
23
Gnd
24
Gnd
25
Gnd
26
Gnd
27
Gnd
28 Gnd 29
Gnd 30
Gnd 31
Gnd 32
Gnd 33
Gnd 34
Gnd 35
Power PadOPA564
U4
OPA564AIDWP
1
2
3
4
5
6
7
8
9
10
11
12
J2
12 HEADER
1
2
3
4
5
6
7
8
9
10
11
12
J3
12 HEADER
R8
30k
R11
30k
R13
6.8k
R6
15k
R10
3.3k
R14
1.47k
R7
2.67k
C1
150pF
C11
100nF
C7
820pf
C5
82pF
C8
10nF
C9
1.0uF
C2 0.1uF
R16
10.0k
R19
2.49k
R18
12.0k
R23
10.0k
R22
10.0k
R21
1.0 ohms
C13 0.1uF
C16
0.1uF
C17
0.1uF
C19
10uF
C18
0.1uF
C20
0.1uF
R17
16.5k
R20
0 ohm
R25
10k
R24
10k
C14
10 uF
L1 1uH, 1.075A
LB3218T1ROM
D5
B350A-13-F or equivalent
D4
B350A-13-F
Test Point 1
TP1
TEST POINT
Test Point 1
TP8
TEST POINT
Test Point
1
TP2
TEST POINT
Test Point 1
TP3
TEST POINT
Test Point 1
TP4
TEST POINT
1
2
JP5
JUMPER
R31
3.83k
R34
3.83k
R28
15.4k R32
4.4k
R35
4.4k
R29
4.4k
R41
0.0 ohm
C23
470pf
C29
82pf
C24
1500pf
C30
82pf
C26
0.1uF
C36
0.1uF
C37
0.1uF
D6
B350A-13-F
D7
B350A-13-F
GND
GND
D2
LED
D3
LED
D1
LED
R4
228 ohm
R3
228 ohm
R5
228 ohm
GND
C12
2700pF
C15
100nF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PWM2_GPIO02
PWM1_GPIO00
ADCIN
ADCIN
GND
+15V SPISTEA_GPIO19
SPICLKA_GPIO18
TXRX
TXDRVEN_GPIO32
LED GPIO20
LED GPIO21
LED GPIO22
R26
150 ohm
C21
33nf
L2
330uH
R27
150 ohm
C22
22nf
L3
470uH
GND
TXRX
C40
10uF
SPISIMOA_GPIO16
SPISOMIA_GPIO17
R45
0 ohm
R47
10k
R46
10k
R48
10k
R49
10k
SPISTEA_GPIO19
SPICLKA_GPIO18
TXDRVEN_GPIO32
SPISIMOA_GPIO16
SPISOMIA_GPIO17
Test Point
1
TP6
TEST POINT
Test Point
1
TP7
TEST POINT
Test Point
1
TP5
TEST POINT
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+15V
+15V
GND
Test Point 1
Gnd
TEST POINT
R50
10k
4
3
1
5
2
U2
OPA365
C6 0.1uF
GND
GND
+3.3V
4
3
1
5
2
U1
OPA365
4
3
1
5
2
U6
OPA365
4
3
1
5
2
U7
OPA365
C25 0.1uF
GND
GND
+3.3V
Pad 1
P1
FREE PAD
Pad 1
P2
FREE PAD GND
Heat sink Pads
C99
50pF
1SMB5930 or equivalent
GND
OPA564-Q1
SBOS567 –JUNE 2011
www.ti.com
Figure 57. Temperature Measurement Using TSENSE and TMP411
Figure 58. Detailed Powerline Communication Circuit
28 Copyright ©2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OPA564AQDWPRQ1 ACTIVE SO PowerPAD DWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA564-Q1 :
•Catalog: OPA564
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA564AQDWPRQ1 SO
Power
PAD
DWP 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA564AQDWPRQ1 SO PowerPAD DWP 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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