OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com 1.5A, 24V, 17MHz POWER OPERATIONAL AMPLIFIER Check for Samples: OPA564-Q1 FEATURES 1 * * * 23 * * * * * * * Qualified for Automotive Applications High Output Current: 1.5A Wide Power-Supply Range: - Single Supply: +7V to +24V - Dual Supply: 3.5V to 12V Large Output Swing: 20VPP at 1.5A Fully Protected: - Thermal Shutdown - Adjustable Current Limit Diagnostic Flags: - Over-Current - Thermal Shutdown Output ENABLE/SHUTDOWN Control High Speed: - Gain-Bandwidth Product: 17MHz - Full-Power Bandwidth at 10VPP: 1.3MHz - Slew Rate: 40V/s Diode for Junction Temperature Monitoring HSOP-20 PowerPADTM Package (Bottom- and Top-Side Thermal Pad Versions) APPLICATIONS * * * * * * * * * * Powerline Communications Valve, Actuator Driver VCOM Driver Motor Driver Audio Power Amplifier Power-Supply Output Amplifier Test Equipment Amplifier Transducer Excitation Laser Diode Driver General-Purpose Linear Power Booster DESCRIPTION The OPA564-Q1 is a low-cost, high-current operational amplifier that is ideal for driving up to 1.5A into reactive loads. The high slew rate provides 1.3MHz full-power bandwidth and excellent linearity. These monolithic integrated circuits provide high reliability in demanding powerline communications and motor control applications. The OPA564-Q1 operates from a single supply of 7V to 24V, or dual power supplies of 3.5V to 12V. In single-supply operation, the input common-mode range extends to the negative supply. At maximum output current, a wide output swing provides a 20VPP (IOUT = 1.5A) capability with a nominal 24V supply. The OPA564-Q1 is internally protected against over-temperature conditions and current overloads. It is designed to provide an accurate, user-selected current limit. Two flag outputs are provided; one indicates current limit and the second shows a thermal over-temperature condition. It also has an Enable/Shutdown pin that can be forced low to shut down the output, effectively disconnecting the load. The OPA564-Q1 is housed in a thermally-enhanced, surface-mount PowerPADTM package (HSOP-20) with the choice of the thermal pad on either the top side or the bottom side of the package. OPA564-Q1 RELATED PRODUCTS FEATURES DEVICE Zero-Drift PGA with 2-Channel Input Mux and SPI PGA112 Zero-Drift Operational Amplifier, 50MHz, RRI/O, Single-Supply OPA365 Quad Operational Amplifier, JFET Input , Low Noise Power Operational Amplifier, 1.2A, 15V, 17MHz, 50V/s TL074 OPA561 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING HSOP-20 (PowerPAD on bottom) DWP OPA564AQ HSOP-20 (PowerPAD on top) DWD PREVIEW PRODUCT OPA564-Q1 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). Supply Voltage, VS = (V+) - (V-) Voltage (2) Signal Input Terminals Signal Output Terminals Current Through ESD Diodes (2) Maximum Differential Voltage Across Inputs (3) Voltage Current (4) OPA564-Q1 UNIT +26 V (V-)-0.4 to (V+)+0.4 V 10 mA 0.5 V (V-)-0.4 to (V+)+0.4 V 10 mA Output Short-Circuit (5) Continuous Operating Junction Temperature, TJ -40 to +125 C Storage Temperature, TA -55 to +150 C +150 C Junction Temperature, TJ Latch-up per JESD78B (1) (2) (3) (4) (5) 2 Class 1 Level B Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Input terminals are diode-clamped to the power-supply rails. Signals that can swing more than 0.4V beyond the supply rails should be current limited to 10mA or less. Refer to Figure 43 for information on input protection. See Input Protection section. Output terminals are diode-clamped to the power-supply rails. Input signals forcing the output terminal more than 0.4V beyond the supply rails should be current limited to 10mA or less. Short-circuit to ground within SOA. See Power Dissipation and Safe Operating Area for more information. Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS At TCASE = +25C, VS = 12V, RLOAD = 20k to GND, RSET = 7.5k, and E/S pin enabled, unless otherwise noted. OPA564-Q1 PARAMETERS CONDITIONS MIN TYP MAX 20 UNIT OFFSET VOLTAGE Input Offset Voltage vs Temperature vs Power Supply VOS dVOS/dT PSRR VCM = 0V 2 TA = -40C to 125C 10 VCM = 0V, VS = 3.5V to 13V 10 150 V/V 10 100 pA mV V/C INPUT BIAS CURRENT Input Bias Current (1) IB VCM = 0V TA = -40C to 125C vs Temperature Input Offset Current (1) See Figure 10, Typical Characteristics IOS 10 100 pA NOISE Input Voltage Noise Density en Input Current Noise In f = 1kHz 102.8 nV/Hz f = 10kHz 20 nV/Hz f = 100kHz 8 nV/Hz f = 1kHz 4 fA/Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range: VCM Common-Mode Rejection Ratio CMRR Linear Operation (V-) VCM = (V-) to (V+)-3V 70 TA = -40C to 125C vs Temperature (V+)-3 80 V dB See Figure 9, Typical Characteristics INPUT IMPEDANCE 1012 || 16 Differential 12 Common-Mode 10 || 9 || pF || pF OPEN-LOOP GAIN Open-Loop Voltage Gain AOL 108 dB VOUT = 20VPP, RLOAD = 10 VOUT = 20VPP, RLOAD = 1k 80 93 dB MHz FREQUENCY RESPONSE Gain-Bandwidth Product (1) GBW Slew Rate SR Full Power Bandwidth Settling Time 0.1% 0.01% Total Harmonic Distortion + Noise THD+N RLOAD = 5 17 G = 1, 10V Step 40 V/s G = +2, VOUT = 10VPP 1.3 MHz G = +1, 10V Step, CLOAD = 100pF 0.6 s G = +1, 10V Step, CLOAD = 100pF 0.8 s f = 1kHz, RLOAD = 5, G = +1, VOUT = 5VP 0.003 % OUTPUT Voltage Output: (1) VOUT Positive IOUT = 0.5A (V+)-1 (V+)-0.4 V Negative IOUT = -0.5A (V-)+1 (V-)+0.3 V Positive IOUT = 1.5A (V+)-2 (V+)-1.5 V Negative IOUT = -1.5A (V-)+2 (V-)+1.1 V See Typical Characteristics. Copyright (c) 2011, Texas Instruments Incorporated 3 OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TCASE = +25C, VS = 12V, RLOAD = 20k to GND, RSET = 7.5k, and E/S pin enabled, unless otherwise noted. OPA564-Q1 PARAMETERS CONDITIONS MIN TYP MAX UNIT OUTPUT, continued Maximum Continuous Current, dc IOUT Output Impedance, closed loop RO f = 100kHz Output Impedance, open loop ZO G = +2, f = 100kHz A 10 See Figure 24, Typical Characteristics Output Current Limit Range (3) 0.4 to 2.0 Current Limit Equation ILIM @ 20000 x ILIM (7) A 1.2V 5000 + RSET A (4) (5) RSET (24k/ILIM) - 5k Solved for RSET (Current Limit) Current Limit Accuracy Current Limit Overshoot (6) 1.5 (2) ILIM = 1.5A 10 % VIN = 5V Pulse (200ns tr), G = +2 50 % Output Shut Down Output Impedance (8) 6 || 120 Capacitive Load Drive CLOAD G || pF See Figure 6, Typical Characteristics DIGITAL CONTROL Enable/Shutdown Mode INPUT VDIG = +3.3V to +5.5V referenced to V- VE/S High (output enabled) VE/S Low (output shut down) E/S Pin Open or Forced High (V-)+2 (V-)+VDIG E/S Pin Forced Low (V-) (V-)+0.8 V V IE/S High (output enabled) E/S Pin Indicates High 10 A IE/S Low (output shut down) E/S Pin Indicates Low 1 A Output Shutdown Time 1 s Output Enable Time 3 s Current Limit Flag Output Normal Operation Sinking 10A Current-Limited Sourcing 20A 0 (V-)+0.8 V (V-)+2 VDIG V (V-)+2 VDIG V +140 to +157 C 15 to 19 C Thermal Shutdown Normal Operation Sinking 200A Thermally Shutdown (9) Junction Temperature at Shutdown Hysteresis Sourcing 200A (10) (10) 0 (V-)+0.8 V TSENSE Diode Ideality Factor 1.033 (2) (3) (4) (5) Under safe operating conditions. See Power Dissipation and Safe Operating Area for safe operating area (SOA) information. Minimum current limit is 0.4A. See Adjustable Current Limit in the Applications section. Quiescent current increases when the current limit is increased (see Typical Characteristics). RSET (current limit) can range from 55k (IOUT = 400mA) to 10k (IOUT = 1.6A typ). See Adjustable Current Limit in the Applications section. (6) See Typical Characteristics. (7) Transient load transition time must be 200ns. (8) See Enable/Shutdown (E/S) Pin in the Applications section. (9) When sourcing, the VDIG supply must be able to supply the current. (10) Characterized, but not production tested. 4 Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TCASE = +25C, VS = 12V, RLOAD = 20k to GND, RSET = 7.5k, and E/S pin enabled, unless otherwise noted. OPA564-Q1 PARAMETERS CONDITIONS MIN TYP MAX UNIT POWER SUPPLY (11) Specified Voltage Range 12 VS Operating Voltage Range Quiescent Current (12) 7 IQ 39 TA = -40C to 125C Over Temperature Quiescent Current in Shutdown Mode IQSD Specified Voltage for Digital VDIG Digital Quiescent Current IOUT = 0 IDIG (V-) + 3.0 VDIG = 5V 43 V 24 V 50 mA 50 mA 5 mA (V-) + 5.5 V 100 A +125 (13) C TEMPERATURE RANGE -40 Operating Range Thermal Resistance HSOP-20 DWP PowerPAD (Pad Down) HSOP-20 DWD PowerPAD (Pad Up) (14) (11) (12) (13) (14) 33 C/W JC JA 50 C/W JP 1.83 C/W JB 22 C/W 45.5 C/W JC 6.3 C/W JB 22 C/W JA High K Board High K Board Power-supply sequencing requirements must be observed. See Power Supplies section for more information. Quiescent current increases when the current limit is increased (see Typical Characteristics). The OPA564-Q1 typically goes into thermal shutdown at a junction temperature above +140C. Thermal modeling of the DWD-20 package was done based on a 1-inch AAVID Thermalloy heatsink (Thermalloy part no. 65810). Copyright (c) 2011, Texas Instruments Incorporated 5 OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com PIN CONFIGURATIONS DWP PACKAGE PowerPAD on Bottom DWD PACKAGE PowerPAD on Top V- 1 20 V- V+ 2 TFLAG 3 E/S 4 V- 1 20 V- 19 V+ PWR V+ PWR 2 19 V+ 18 V+ PWR V+ PWR 3 18 TFLAG 17 V+ PWR V+ PWR 4 (1) +IN 5 -IN 6 VDIG 7 IFLAG ISET PowerPAD Heat Sink (Located on bottom side) 17 E/S (2) PowerPAD Heat Sink (Located on top side) 16 VOUT VOUT 5 15 VOUT VOUT 6 14 V- PWR V- PWR 7 14 VDIG 8 13 V- PWR V- PWR 8 13 IFLAG 9 12 TSENSE TSENSE 9 12 ISET V- 10 11 V- 15 -IN 11 V- V- 10 (1) PowerPAD is internally connected to V-, Soldering the PowerPAD to the PCB is always required, even with applications that have low power dissipation. 16 +IN (2) PowerPAD is internally connected to V-. PIN DESCRIPTIONS 6 DWP (PAD DOWN) PIN NO. DWD (PAD UP) PIN NO. NAME 1, 10, 11, 20 1, 10, 11, 20 V- -Supply for Amplifier, PWR Out, and Metal PowerPAD 2 19 V+ +Supply for Signal Amplifier 3 18 TFLAG 4 17 E/S Enable/Shutdown Output Stage; take E/S low to shut down output 5 16 +IN Noninverting Op Amp Input 6 15 -IN Inverting Op Amp Input 7 14 VDIG +Supply for Digital Flag and E/S (referenced to V-). Valid Range is (V-) + 3.0V VDIG (V-) + 5.5V. 8 13 IFLAG Current Limit Flag; Active High 9 12 ISET Current Limit Set (see Applications Section) 12 9 TSENSE 13, 14 7, 8 V- PWR 15, 16 5, 6 VOUT 17, 18, 19 3, 4, 2 V+ PWR DESCRIPTION Thermal Over Temperature Flag; flag is high when alarmed and device has gone into thermal shutdown. Temperature Sense Pin for use with TMP411 -Supply for Power Output Stage Output Voltage; RO is high impedance when shut down +Supply for Power Output Stage Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com FUNCTIONAL PIN DIAGRAM Current Thermal Limit V+ VDIG Flag Flag Enable/Shutdown (2) (19) (17, 18) Current Thermal Limit V+ VDIG Flag Flag Enable/Shutdown (19) (2) (3, 4) (7) (6) (14) (15) (3) -IN (18) -IN (13) (8) (17) (4) (15, 16) VOUT OPA564AIDWP (5, 6) VOUT OPA564AIDWD (9) (12) +IN (9) (5) Current Limit Set (1, 10, 11, 20) (13, 14) TSENSE +IN (12) (16) Current Limit Set (1, 10, 11, 20) (7, 8) RSET RSET V- Copyright (c) 2011, Texas Instruments Incorporated TSENSE V- 7 OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS At TCASE = +25C, VS = 12V, RLOAD = 20k to GND, RSET = 7.5k, and E/S pin enabled, unless otherwise noted. QUIESCENT CURRENT vs SUPPLY VOLTAGE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 50 46 Output Voltage (V) Quiescent Current (mA) 48 44 42 RSET = 7.5kW 40 38 RSET = 40kW 36 RSET = 100kW 34 32 30 6 8 10 12 14 16 18 20 22 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 24 RSET = 7.5kW VS = 12V VS = 3.5V +125C +25C -40C VS = 12V 1ms Current Pulses 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Output Current (A) Supply Voltage (V) Figure 1. Figure 2. LARGE-SIGNAL STEP RESPONSE, NO LOAD LARGE-SIGNAL STEP RESPONSE 2V/div 5W Load G = +1 VIN = 9VPP 2V/div Unloaded G = +1 VIN = 9VPP Input Output Input Output Time (250ns/div) Time (250ns/div) Figure 3. Figure 4. SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 60 VS = 12V G = +1 Overshoot (%) 10mV/div 50 VOUT VIN RLOAD = No Load G = -1 CLOAD = 0pF G = -1 40 30 G = -10 20 G = +10 10 0 Time (250ns/div) 10 100 1k 10k 100k Capacitance (pF) Figure 5. 8 Figure 6. Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TCASE = +25C, VS = 12V, RLOAD = 20k to GND, RSET = 7.5k, and E/S pin enabled, unless otherwise noted. IQ vs TEMPERATURE OFFSET VOLTAGE vs TEMPERATURE 50 20 RSET = 7.5kW 15 Offset Voltage (mV) Quiescent Current (mA) 45 40 35 30 25 10 5 0 -5 -10 -15 -20 20 -75 -50 -25 0 25 50 75 100 125 -75 -50 -25 Temperature (C) 0 Figure 7. 75 100 125 IB vs TEMPERATURE 2200 300 250 200 150 100 2000 1800 CMRR 50 0 -50 Input Bias Current (pA) Common-Mode Rejection Ratio, Power-Supply Rejection Ratio, Open-Loop Gain (mV/V) 50 Figure 8. AOL, PSRR, AND CMRR vs TEMPERATURE PSRR AOL -100 -150 -200 -250 -300 1600 1400 1200 1000 800 IOS 600 IB- 400 200 0 IB+ -200 -75 -50 0 -25 25 50 75 100 -75 125 -50 -25 0 25 75 100 125 75 100 125 50 Temperature (C) Temperature (C) Figure 9. Figure 10. IQ, SHUTDOWN vs TEMPERATURE IDIG vs TEMPERATURE 2.0 100 80 1.5 Digital Current (mA) Quiescent Current, Shutdown (mA) 25 Temperature (C) 1.0 0.5 60 40 20 0 0 -75 -50 -25 0 25 50 Temperature (C) Figure 11. Copyright (c) 2011, Texas Instruments Incorporated 75 100 125 -75 -50 -25 0 25 50 Temperature (C) Figure 12. 9 OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TCASE = +25C, VS = 12V, RLOAD = 20k to GND, RSET = 7.5k, and E/S pin enabled, unless otherwise noted. COMMON-MODE REJECTION RATIO AND POWER-SUPPLY REJECTION RATIO vs FREQUENCY GAIN AND PHASE vs FREQUENCY 120 100 0 VS = 12V RLOAD = 1kW 80 -45 Phase -90 60 Gain Phase () Gain (dB) 80 40 -135 CMRR, PSRR (dB) 100 10 100 10k 1k 100k -180 10M 40M 1M 60 -PSRR +PSRR 40 20 20 0 CMRR VS = 12V 0 10 100 Frequency (Hz) Figure 13. OUTPUT VOLTAGE SWING vs FREQUENCY OUTPUT VOLTAGE SWING vs FREQUENCY 20 Output Voltage (VPP) Output Voltage (VPP) 100k 25 12.5 10.0 7.5 10W 5.0 100W 100W 15 10 10W 5 2.5 VS = 12V G = +1 0 10k VS = 12V G = +1 0 100k 1M 10M 100M 10k 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure 15. Figure 16. TOTAL HARMONIC DISTORTION + NOISE vs AMPLITUDE TOTAL HARMONIC DISTORTION + NOISE vs AMPLITUDE 1 0.1 RLOAD = 5W 0.01 RLOAD = 10W 0.001 VS = 12V f = 1kHz G = +1 0.0001 0.01 RLOAD = No Load RLOAD = 60W 0.1 1 VOUT Amplitude (VP) Figure 17. 10 100 Total Harmonic Distortion + Noise (%) 1 Total Harmonic Distortion + Noise (%) 10k Figure 14. 15.0 10 1k Frequency (Hz) 0.1 RLOAD = 5W 0.01 RLOAD = 10W 0.001 VS = 12V f = 1kHz G = -10 0.0001 0.01 RLOAD = No Load RLOAD = 60W 0.1 1 10 100 VOUT Amplitude (VP) Figure 18. Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TCASE = +25C, VS = 12V, RLOAD = 20k to GND, RSET = 7.5k, and E/S pin enabled, unless otherwise noted. TOTAL HARMONIC DISTORTION + NOISE vs AMPLITUDE TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 Total Harmonic Distortion + Noise (%) Total Harmonic Distortion + Noise (%) 1 RLOAD = 10W 0.1 RLOAD = 5W 0.01 0.001 VS = 12V f = 1kHz G = +10 0.0001 0.01 RLOAD = 60W RLOAD = No Load G = +10 VOUT = 8VP RLOAD = 5W 0.1 RLOAD = 10W 0.01 RLOAD = 60W 0.001 RLOAD = No Load 0.0001 0.1 10 1 100 10 100 VOUT Amplitude (VP) Figure 20. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 G = -10 VOUT = 8VP Total Harmonic Distortion + Noise (%) Total Harmonic Distortion + Noise (%) 100k Figure 19. 1 0.1 RLOAD = 5W 0.01 RLOAD = 60W RLOAD = 10W 0.001 RLOAD = No Load 0.0001 G = +1 VOUT = 5VP 0.1 RLOAD = 5W 0.01 0.001 RLOAD = No Load 100 10k 1k 100k 10 Figure 21. Figure 22. 100 10 10 1 1k Frequency (Hz) Figure 23. Copyright (c) 2011, Texas Instruments Incorporated 10k 1 100k 10k Current Noise (fA/OHz) Current Noise Voltage Noise 100k OPEN-LOOP OUTPUT IMPEDANCE (No Load) 1k IOUT = 0A dc 1k Impedance (W) VS = 12V 100 10k 1k Frequency (Hz) 1k 10 100 Frequency (Hz) INPUT VOLTAGE SPECTRAL NOISE AND CURRENT NOISE vs FREQUENCY 100 RLOAD = 60W RLOAD = 10W 0.0001 10 Voltage Noise (nV/OHz) 10k 1k Frequency (Hz) 100 10 1 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Figure 24. 11 OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TCASE = +25C, VS = 12V, RLOAD = 20k to GND, RSET = 7.5k, and E/S pin enabled, unless otherwise noted. INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE CLOSED-LOOP OUTPUT IMPEDANCE (No Load) Impedance (W) 1k 50 IOUT = 0A dc Gain = 1V/V 40 Input Bias Current (pA) 10k 100 10 1 30 20 10 0.1 0 0.01 -10 10 100 1k 10k 100k 1M 10M 100M -12 -10 -8 Frequency (Hz) -4 -2 0 2 4 6 8 10 Common-Mode Voltage (VCM) Figure 25. Figure 26. ENABLE RESPONSE RLOAD = 100 SHUTDOWN TIME (INVERTING CONFIGURATION) VOUT RF = 10kW RLOAD = 100W VOUT = -6V 0V CH1: 0V VOUT 2V/div RLOAD = 100W, G = +1 VIN = 1V 1V/div -6 E/S E/S V- CH2: 0V Time (100ns/div) Time (500ms/div) Figure 27. Figure 28. ENABLE TIME (INVERTING CONFIGURATION) CURRENT LIMIT PERCENT ERROR vs RSET 60 Mean Mean +3s Mean -3s 50 0V RF = 10kW RLOAD = 100W VOUT = -6V E/S VTime (1ms/div) Current Limit Error (%) 2V/div VOUT 40 30 20 10 0 -10 -20 -30 -40 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k RSET (W) Figure 29. 12 Figure 30. Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TCASE = +25C, VS = 12V, RLOAD = 20k to GND, RSET = 7.5k, and E/S pin enabled, unless otherwise noted. OUTPUT CURRENT LIMIT vs RSET (SINKING CURRENT) 1.8 1.8 1.6 1.6 1.4 1.4 Output Current Limit (A) Output Current Limit (A) OUTPUT CURRENT LIMIT vs RSET (SOURCING CURRENT) 1.2 1.0 0.8 0.6 Mean Mean -3s Mean +3s Calculated Value 0.4 0.2 1.2 1.0 0.8 0.6 Mean Mean -3s Mean +3s Calculated Value 0.4 0.2 0 0 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k RSET (W) RSET (W) Figure 31. Figure 32. QUIESCENT CURRENT INCREASE vs RSET OFFSET VOLTAGE PRODUCTION DISTRIBUTION 5 Population IQ Increase (mA) 4 3 2 1 5k 15k 25k 35k 45k RSET (W) 55k 65k 75k -18.0 -16.2 -14.4 -12.6 -10.8 -9.0 -7.2 -5.4 -3.6 -1.8 0 1.8 3.6 5.4 7.2 9.0 10.8 12.6 14.4 16.2 18.0 0 Offset Voltage (mV) Figure 33. Copyright (c) 2011, Texas Instruments Incorporated Figure 34. 13 OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com APPLICATION INFORMATION Figure 35 shows the OPA564-Q1 connected as a basic noninverting amplifier. However, the OPA564-Q1 can be used in virtually any op amp configuration. Power-supply terminals should be bypassed with low series impedance capacitors. The technique of using ceramic and tantalum capacitors in parallel is recommended. Power-supply wiring should have low series impedance. Sequencing of power supplies must assure that the digital supply voltage (VDIG) be applied before the supply voltage to prevent damage to the OPA564-Q1. Figure 36 shows acceptable versus unacceptable power-supply sequencing. VSUPPLY Voltage (V) BASIC CONFIGURATION See Note 1 VDIGITAL V+ 47mF (3) VDIG Time (s) 0.1mF (A) Sequence not allowed VO OPA564 VSUPPLY ISET VIN (1) (1) E/S (2) 0.1mF Voltage (V) RSET VDIGITAL 47mF V- Time (s) (B) Sequence allowed (1) RSET sets the current limit value from 0.4A to 1.5A. (2) E/S pin forced low shuts down the output. (3) VDIG must not exceed (V-) + 5.5V; see Figure 56 for examples of generating a signal for VDIG. VSUPPLY POWER SUPPLIES The OPA564-Q1 operates with excellent performance from single (+7V to +24V) or dual (3.5V to 12V) analog supplies and a digital supply of +3.3V to +5.5V (referenced to the V- pin). Note that the analog power-supply voltages do not need to be symmetrical, as long as the total voltage remains below 24V. For example, the positive supply could be set to 14V with the negative supply at -10V. Most behaviors remain constant across the operating voltage range. Parameters that vary significantly with operating voltage are shown in the Typical Characteristics. 14 Voltage (V) Figure 35. Basic Noninverting Amplifier VDIGITAL Time (s) (C) Sequence allowed (1) The power-supply sequence illustrated in (A) is not allowed. This power-supply sequence causes damage to the device. Figure 36. Power-Supply Sequencing Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com ADJUSTABLE CURRENT LIMIT Setting the Current Limit The OPA564-Q1 provides over-current protection to the load through its accurate, user-adjustable current limit (ISET pin). The current limit value, ILIM, can be set from 0.4A to 1.5A by controlling the current through the ISET pin. Setting the current limit does not require special power resistors. The output current does not flow through the ISET pin. Leaving the ISET pin unconnected damages the device. Connecting ISET directly to V- is not recommended because it programs the current limit far beyond the 1.5A capability of the device and causes excess power dissipation. The minimum recommended value for RSET is 7.5k, which programs the maximum current limit to approximately 1.9A. The maximum value for RSET is 55k, which programs the minimum current limit to approximately 0.4A. The simplest method for adjusting the current limit (ILIM) uses a resistor or potentiometer connected between the ISET pin and V-, according to Equation 1. A simple resistor to the negative rail is sufficient for a general, coarse limit of the output current. Figure 30 exhibits the percent of error in the transfer function between ISET and IOUT versus the current limit set resistor, RSET; Figure 31 and Figure 32 show how this error translates to variation in IOUT versus RSET. The dotted line represents the ideal output current setting which is determined by the following equation: 1.2V ILIM @ 20000 x 5000 + RSET RSET @ (1) The mismatch errors between the current limit set mirror and the output stage are primarily a result of variations in the ~1.2V bandgap reference, an internal 5k resistor, the mismatch between the current limit and the output stage mirror, and the tolerance and temperature coefficient of the RSET resistor referenced to the negative rail. Additionally, an increase in junction temperature can induce added mismatch in accuracy between the ISET and IOUT mirror. See Figure 53 for a method that can be used to dynamically change the current limit setting using a simple, zero drift current source. This approach simplifies the current limit equation to the following: ILIM @ 20,000 ISET (2) The current into the ISET pin is determined by the NPN current source. Therefore, the errors contributed by the internal 1.2V bandgap reference and the 5k resistor mismatch are eliminated, thus improving the overall accuracy of the transfer function. In this case, the primary source of error in ISET is the RSET resistor tolerance and the beta of the NPN transistor. It is important to note that the primary intent of the current limit on the OPA564-Q1 is coarse protection of the output stage; therefore, the user should exercise caution when attempting to control the output current by dynamically toggling the current limit setting. Predictable performance is better achieved by controlling the output voltage through the feedback loop of the OPA564-Q1. Copyright (c) 2011, Texas Instruments Incorporated If ILIM has been defined, RSET can be solved by rearranging Equation 1 into Equation 3: 24kW - 5kW ILIM (3) RSET in combination with a 5k internal resistor determines the magnitude of a small current that sets the desired output current limit. Figure 37 shows a simplified schematic of the OPA564-Q1 current limit architecture. 1.2V Bandgap IOUT ILIM 5kW ILIM @ OPA564 (R 1.2V CL + 5kW ) 20k ISET RSET (1) 1nF (optional, for noisy environments) V- (1) At power-on, this capacitor is not charged. Therefore, the OPA564-Q1 is programmed for maximum output current. Capacitor values > 1nF are not recommended. Figure 37. Adjustable Current Limit 15 OPA564-Q1 SBOS567 - JUNE 2011 ENABLE/SHUTDOWN (E/S) PIN The output of the OPA564-Q1 shuts down when the E/S pin is forced low. For normal operation (output enabled), the E/S pin must be pulled high (at least 2V above V-). To enable the OPA564-Q1 permanently, the E/S pin can be left unconnected. The E/S pin has an internal 100k pull-up resistor. When the output is shut down, the output impedance of the OPA564-Q1 is 6G || 120pF. The output shutdown output voltage versus output current is shown in Figure 42. Although the output is high-impedance when shut down, there is still a path through the feedback network into the input stage to ground; see Figure 43. To prevent damage to the OPA564-Q1, ensure that the voltage across the input terminals +IN and -IN does not exceed 0.5V, and that the current flowing through the input terminals does not exceed 10mA when operated beyond the supply rails, V- and V+. Refer to the Input Protection section. www.ti.com logic signal and the OPA564-Q1 shutdown pin are referenced to the same potential. In this configuration, the logic pin and the OPA564-Q1 enable can simply be connected together. Shutdown occurs for voltage levels of less than 0.8V. The OPA564-Q1 is enabled at logic levels greater than 2V. In dual-supply operation, the logic pin remains referenced to a logic ground. However, the shutdown pin of the OPA564-Q1 continues to be referenced to V-. Thus, in a dual-supply system, to shut down the OPA564-Q1 the voltage level of the logic signal must be level-shifted by some means. One way to shift the logic signal voltage level is by using an optocoupler, as Figure 38 shows. (a) +5V (b) HCT or TTL In V+ Input Protection Electrostatic discharge (ESD) protection followed by back-to-back diodes and input resistors (see Figure 43) are used for input protection on the OPA564-Q1. Exceeding the turn-on threshold of these diodes, as in a pulse condition, can cause current to flow through the input protection diodes because of the finite slew rate of the amplifier. If the input current is not limited, the back-to-back diodes and the input devices can be destroyed. Sources of high input current can also cause subtle damage to the amplifier. Although the unit may still be functional, important parameters such as input offset voltage, drift, and noise may shift. When using the OPA564-Q1 as a unity-gain buffer (follower), as an inverting amplifier, or in shutdown mode, the input voltage between the input terminals (+IN and -IN) must be limited so that the voltage does not exceed 0.5V. This condition must be maintained across the entire common-mode range from V- to V+. If the inputs are taken above either supply rail, the current must be limited to 10mA through the ESD protection diodes. During excursions past the rails, it is still necessary to limit the voltage across the input terminals. If necessary, external back-to-back diodes should be added between +IN and -IN to maintain the 0.5V requirement between these connections. Output Shutdown OPA564 E/S (1) 4N38 Optocoupler V(a) HCT or TTL In (b) (1) Optional; may be required to limit leakage current of optocoupler at high temperatures. Figure 38. Shutdown Configuration for Dual Supplies (Using Optocoupler) To shut down the output, the E/S pin is pulled low, no greater than 0.8V above V-. This function can be used to conserve power during idle periods. To return the output to an enabled state, the E/S pin should be pulled to at least 2.0V above V-. Figure 27 shows the typical enable and shutdown response times. It should be noted that the E/S pin does not affect the internal thermal shutdown. When the OPA564-Q1 will be used in applications where the device shuts down, special care should be taken with respect to input protection. Consider the following two examples. The shutdown pin (E/S) is referenced to the negative supply (V-). Therefore, shutdown operation is slightly different in single-supply and dual-supply applications. In single-supply operation, V- typically equals common ground. Therefore, the shutdown 16 Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com Figure 39 shows the amplifier in a follower configuration. The load is connected midway between the supplies, V+ and V-. When the device shuts down in this situation, the load pulls VOUT to ground. Little or no current then flows through the input of the OPA564-Q1. V+ V+ 1.6kW -IN V+ VV+ VOUT I1 100W I2 6GW 120pF V1.6kW +IN V- V- Figure 39. Shutdown Equivalent Circuit with Load Connected Midway Between Supplies Copyright (c) 2011, Texas Instruments Incorporated 17 OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com Now consider Figure 40. Here, the load is connected to V-. When the device shuts down, current flows from the positive input +IN through the first 1.6k resistor through an input protection diode, then through the second 1.6k resistor, and finally through the 100 resistor to V-. This current flow produces a voltage across the inputs which is much greater than 0.5V, which damages the OPA564-Q1. A similar problem would occur if the load is connected to the positive supply. CAUTION This configuration damages the device. V+ V+ 1.6kW -IN V+ VV+ VOUT I1 100W I2 6GW 120pF V1.6kW +IN V- V- Figure 40. Shutdown Equivalent Circuit with Load Connected to V-: Voltage Across Inputs During DIsable Exceeds Input Requirements 18 Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com The solution is to place external protection diodes across the OPA564-Q1 input. Figure 41 illustrates this configuration. NOTE This configuration protects the input during shutdown. V+ V+ External protection diodes required; use Skyworks Solutions Inc. # SMS3922-004LF or equivalent 1.6kW -IN V+ VV+ VOUT I1 100W I2 6GW 120pF V1.6kW +IN V- V- Figure 41. Shutdown Equivalent Circuit with Load Connected to V-: Protected Input Configuration Copyright (c) 2011, Texas Instruments Incorporated 19 OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com Ensuring Microcontroller Compatibility within the optocoupler. A high logic level causes the OPA564-Q1 to be enabled, and a low logic level shuts the OPA564-Q1 down. In the configuration of Figure 38(b), with the logic signal applied on the anode side, a high level causes the OPA564-Q1 to shut down, and a low level enables the op amp. Not all microcontrollers output the same logic state after power-up or reset. 8051-type microcontrollers, for example, output logic high levels while other models power up with logic low levels after reset. In the configuration of Figure 38(a), the shutdown signal is applied on the cathode side of the photodiode OUTPUT SHUTDOWN OUTPUT VOLTAGE vs OUTPUT CURRENT 500 450 Test Circuit VS = 12V E/S = Low (Output Shutdown) Output Current (pA) 400 IOUT 350 300 OPA564 250 200 VOUT 150 100 50 0 -10 -8 -4 -6 -2 0 2 4 6 8 10 Output Voltage (V) Figure 42. Output Shutdown Output Impedance RF V+ V+ 1.6kW -IN External protection diodes as needed V+ V- R1 V+ VOUT I1 I2 6GW 120pF V1.6kW +IN V- V- Figure 43. OPA564-Q1: Output Shutdown Equivalent Circuit (with External Feedback) 20 Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com CURRENT LIMIT FLAG The OPA564-Q1 features a current limit flag (IFLAG) that can be monitored to determine if the load current is operating within or exceeding the current limit set by the user. The output signal of IFLAG is compatible with standard CMOS logic and is referenced to the negative supply pin (V-). A voltage level of + 0.8V or less with respect to V- indicates that the amplifier is operating within the limits set by the user. A voltage level of +2.0V or greater with respect to V- indicates that the OPA564-Q1 is operating above (exceeds) the current limit set by the user. See Setting the Current Limit for proper current limit operation. OUTPUT STAGE COMPENSATION The complex load impedances common in power op amp applications can cause output stage instability. For normal operation, output compensation circuitry is typically not required. However, if the OPA564-Q1 is intended to be driven into current limit, an R/C network (snubber) may be required. A snubber circuit such as the one shown in Figure 54 may also enhance stability when driving large capacitive loads (greater than 1000pF) or inductive loads (for example, motors or loads separated from the amplifier by long cables). Typically, 3 to 10 in series with 0.01F to 0.1F is adequate. Some variations in circuit value may be required with certain loads. Depending on load and signal conditions, the thermal protection circuit may cycle on and off. This cycling limits the amplifier dissipation, but may have undesirable effects on the load. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable, long-term, continuous operation, with IOUT at the maximum output of 1.5A, the junction temperature should be limited to +85C maximum. Figure 44 shows the maximum output current versus junction temperature for dc and RMS signal outputs. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection triggers. Use worst-case loading and signal conditions. For good, long-term reliability, thermal protection should trigger more than 35C above the maximum expected ambient condition of the application. The internal protection circuitry of the OPA564-Q1 was designed to protect against overload conditions; it was not intended to replace proper heatsinking. Continuously running the OPA564-Q1 into thermal shutdown degrades reliability. MAXIMUM OUTPUT CURRENT vs JUNCTION TEMPERATURE 1.6 1.4 The output structure of the OPA564-Q1 includes ESD diodes (see Figure 43). Voltage at the OPA564-Q1 output must not be allowed to go more than 0.4V beyond either supply rail to avoid damaging the device. Reactive and electromagnetic field (EMF)-generation loads can return load current to the amplifier, causing the output voltage to exceed the power-supply voltage. This damaging condition can be avoided with clamping diodes from the output terminal to the power supplies, as Figure 54 and Figure 55 illustrate. Schottky rectifier diodes with a 3A or greater continuous rating are recommended. THERMAL PROTECTION The OPA564-Q1 has thermal sensing circuitry that helps protect the amplifier from exceeding temperature limits. Power dissipated in the OPA564-Q1 causes the junction temperature to rise. Internal thermal shutdown circuitry disables the output when the die temperature reaches the thermal shutdown temperature limit. The OPA564-Q1 output remains shut down until the die has cooled sufficiently; see the Electrical Characteristics, Thermal Shutdown section. Copyright (c) 2011, Texas Instruments Incorporated Max IOUT (A) 1.2 OUTPUT PROTECTION 1.0 0.8 0.6 0.4 Max IOUT (dc) Max IOUT (RMS) 0.2 0 -50 -25 0 25 50 75 100 125 TJ (C) Figure 44. Maximum Output Current vs Junction Temperature USING TSENSE FOR MEASURING JUNCTION TEMPERATURE The OPA564-Q1 includes an internal diode for junction temperature monitoring. The -factor of this diode is 1.033. Measuring the OPA564-Q1 junction temperature can be accomplished by connecting the TSENSE pin to a remote-junction temperature sensor, such as the TMP411 (see Figure 57). 21 OPA564-Q1 SBOS567 - JUNE 2011 Power dissipation depends on power supply, signal, and load conditions. For dc signals, power dissipation is equal to the product of output current (IOUT) and the voltage across the conducting output transistor [(V+) - VOUT when sourcing; VOUT - (V-) when sinking]. Dissipation with ac signals is lower. Application Bulletin AB-039, Power Amplifier Stress and Power Handling Limitations (SBOA022, available for download from www.ti.com) explains how to calculate or measure power dissipation with unusual signals and loads. Figure 45 shows the safe operating area at room temperature with various heatsinking efforts. Note that the safe output current decreases as (V+) - VOUT or VOUT - (V-) increases. Figure 46 shows the safe operating area at various temperatures with the PowerPAD being soldered to a 2oz copper pad. Once the heatsink area has been selected, worst-case load conditions should be tested to ensure proper thermal protection. space SAFE OPERATING AREA AT ROOM TEMPERATURE 10.0 Output Current (A) POWER DISSIPATION AND SAFE OPERATING AREA www.ti.com 0.1 0 TJ = TA + PD x JA 6 8 10 12 14 16 18 20 22 24 26 Figure 45. Safe Operating Area at Room Temperature Output Current (A) Combining these equations produces: 4 2 (V+) - VOUT, VOUT - (V-) (V) The relationship between thermal resistance and power dissipation can be expressed as: TJA = PD x JA Copper, Soldered with 200LFM Airflow Copper, Soldered without Forced Air The power that can be safely dissipated in the package is related to the ambient temperature and the heatsink design. The PowerPAD package was specifically designed to provide excellent power dissipation, but board layout greatly influences the heat dissipation of the package. Refer to the Thermally-Enhanced PowerPAD Package section for further details. TJ = TA + TJA 1.0 SAFE OPERATING AREA AT VARIOUS AMBIENT TEMPERATURES (PowerPAD Soldered) 10.0 TA = -40C TA = 0C TA = +25C TA = +85C 1.0 TA = +125C 0.1 where: TJ = Junction temperature (C) TA = Ambient temperature (C) JA = Junction-to-ambient thermal resistance (C/W) PD = Power dissipation (W) To determine the required heatsink area, required power dissipation should be calculated and the relationship between power dissipation and thermal resistance should be considered to minimize shutdown conditions and allow for proper long-term operation (junction temperature of +85C or less). 22 0.01 0 2 4 6 8 10 12 14 16 18 20 22 24 26 (V+) - VOUT, VOUT - (V-) (V) PowerPAD soldered to a 2oz copper pad. Figure 46. Safe Operating Area at Various Ambient Temperatures Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com For applications with limited board size, refer to Figure 47 for the approximate thermal resistance relative to heatsink area. Increasing heatsink area beyond 2in2 provides little improvement in thermal resistance. To achieve the 33C/W shown in the Electrical Characteristics, a 2oz copper plane size of 9in2 was used. The PowerPAD package is well-suited for continuous power levels from 2W to 4W, depending on ambient temperature and heatsink area. The addition of airflow also influences maximum power dissipation, as Figure 48 illustrates. Higher power levels may be achieved in applications with a low on/off duty cycle, such as remote meter reading. THERMAL RESISTANCE vs CIRCUIT BOARD COPPER AREA Thermal Resistance, q JA (C/W) 45 The OPA564-Q1 uses the HSOP-20 PowerPAD DWP and DWD packages, which are thermally-enhanced, standard size IC packages. These packages enhance power dissipation capability significantly and can be easily mounted using standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard repair procedures. The DWP PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of the IC, as shown in Figure 49a; the DWD PowerPAD package has the exposed pad on the top side of the package, as shown in Figure 49b. The thermal pad provides an extremely low thermal resistance (JC) path between the die and the exterior of the package. 40 35 30 OPA564 Surface Mount Package 2oz copper 25 20 0 1 2 3 4 5 2 Copper Area (inches ) Figure 47. Thermal Resistance vs Circuit Board Copper Area MAXIMUM POWER DISSIPATION vs TEMPERATURE 6 Power Dissipation in Package (W) THERMALLY-ENHANCED PowerPAD PACKAGE No Copper Copper, Soldered without Forced Air Copper, Soldered with 200LFM Airflow 5 4 PowerPAD packages with exposed pad down are designed to be soldered directly to the PCB, using the PCB as a heatsink. Texas Instruments does not recommend the use of the of a PowerPAD package without soldering it to the PCB because of the risk of lower thermal performance and mechanical integrity. In addition, through the use of thermal vias, the bottom-side thermal pad can be directly connected to a power plane or special heatsink structure designed into the PCB. The PowerPAD should be at the same voltage potential as V-. Soldering the bottom-side PowerPAD to the PCB is always required, even with applications that have low power dissipation. It provides the necessary thermal and mechanical connection between the leadframe die and the PCB. Pad-up PowerPAD packages should have appropriately designed heatsinks attached. Because of the variation and flexible nature of this type of heat sink, additional details should come from the specific manufacturer of the heatsink. 3 2 1 0 0 25 50 75 100 125 Temperature (C) Figure 48. Maximum Power Dissipation vs Temperature Copyright (c) 2011, Texas Instruments Incorporated 23 OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com Leadframe (Copper Alloy) IC (Silicon) Die Attach (Epoxy) Die Pad External Heatspreader Die Attach Chip Thermal Paste Power Transistor Leadframe Die Pad Exposed at Base of the Package Board Mold Compound (Epoxy) (b) DWD PowerPAD cross-section view (a) DWP PowerPAD cross-section view Figure 49. Cross-Section Views Bottom-Side PowerPAD Assembly Process 1. The PowerPAD must be connected to the most negative supply of the device, V-. 2. Prepare the PCB with a top side etch pattern, as shown in the attached thermal land pattern mechanical drawing. There should be etch for the leads as well as etch for the thermal land. 3. Place the recommended number of holes (or thermal vias) in the area of the thermal pad, as seen in the attached thermal land pattern mechanical drawing. These holes should be 13mils (.013in, or 330.2m) in diameter. They are kept small so that solder wicking through the holes is not a problem during reflow. 4. It is recommended, but not required, to place a small number of the holes under the package and outside the thermal pad area. These holes provide an additional heat path between the copper land and ground plane and are 25mils (.025in, or 635m) in diameter. They may be larger because they are not in the area to be soldered, so wicking is not a problem. This configuration is illustrated in the attached thermal land pattern mechanical drawing. 5. Connect all holes, including those within the thermal pad area and outside the pad area, to the internal plane that is at the same voltage potential as V-. 6. When connecting these holes to the internal plane, do not use the typical web or spoke via connection methodology (as Figure 50 shows). Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This configuration makes the soldering of vias that have plane connections easier. However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore, the 24 holes under the PowerPAD package should be connected to the internal plane with a complete connection around the entire circumference of the plated through-hole. 7. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area. The thermal pad area should leave the 13mil holes exposed. The larger 25mil holes outside the thermal pad area should be covered with solder mask. 8. Apply solder paste to the exposed thermal pad area and all of the package terminals. 9. With these preparatory steps completed, the PowerPAD IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This processing results in a part that is properly installed. For detailed information on the PowerPAD package including thermal modeling considerations and repair procedures, see Technical Brief SLMA002, PowerPAD Thermally Enhanced Package, available at www.ti.com. Solid Via RECOMMENDED Web or Spoke Via NOT RECOMMENDED Figure 50. Via Connection Methods Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com APPLICATIONS CIRCUITS R2 1kW The high output current and low supply of the OPA564-Q1 make it a good candidate for driving laser diodes and thermoelectric coolers. Figure 51 shows an improved Howland current pump circuit. VDIG +5V 47mF 0.1mF POWERLINE COMMUNICATION R1 20kW OPA564 Powerline communication (PLC) applications require some form of signal transmission over an existing ac power line. A common technique used to couple these modulated signals to the line is through a signal transformer. A power amplifier is often needed to provide adequate levels of current and voltage to drive the varying loads that exist on today's powerlines. One such application is shown in Figure 52. The OPA564-Q1 is used to drive signals used in frequency modulation schemes such as FSK (Frequency-Shift Keying) or OFDM (Orthogonal Frequency-Division Multiplexing) to transmit digital information over the powerline. The power output capabilities of the OPA564-Q1 are needed to drive the current requirements of the transformer that is shown in the figure, coupled to the ac power line via a coupling capacitor. Circuit protection is often needed or required to prevent excessive line voltages or current surges from damaging the active circuitry in the power amplifier and application circuitry. VO ISET RSET 0.1mF R5 50mW 47mF -5V R4 20kW R4 1kW +1V/+1A (1) See Figure 35 for an example of a basic noninverting amplifier with VDIG not exceeding 5.5V. Figure 51. Improved Howland Current Pump VS CF VDIG C1 R1 RF S1 (1) S3 (1) INPUT L1 (2) C2 0.1mF C3 + 47mF R3 C5 C6 OPA564 1/2 VS 1 E/S T1 6 (3) S2 R4 (4) C4 10pF (1) S4 (1) D1 SMBJ12CA or SMBJ6.0CA 3 4 GND (1) S1, S2, S3, and S4 are Schottky diodes. S1 and S2 are B350 or equivalent. S3 and S4 are BAV99T or equivalent. (2) L1 should be small enough so that it does not interfere with the bandwidth of interest but large enough to suppress transients that could damage the OPA564-Q1. (3) D1 is a transient suppression diode. For 24V supplies, use SMBJ12CA. For 12V supplies, use SMBJ6.0CA. Voltage rating of transient voltage suppressor should be half the supply rating or less. (4) The minimum recommended value for R4 is 7.5k. Figure 52. Powerline Communication Line Coupling Copyright (c) 2011, Texas Instruments Incorporated 25 OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com PROGRAMMABLE POWER SUPPLY For more information on this circuit, see the Application Bulletin DC Motor Speed Controller: Control a DC Motor without Tachometer Feedback (SBOA043), available for download at the TI web site. Figure 53 shows the OPA333 used to control ISET in order to adjust the current limit of the OPA564-Q1. Figure 54 shows a basic motor speed driver but does not include any control over the motor speed. For applications where good control of the speed of the motor is desired, but the precision of a tachometer control is not required, the circuit in Figure 55 provides control by using feedback of the current consumption to adjust the motor drive. R1 Figure 56 shows two examples of generating the signal for VDIG. Figure 56a uses an 1N4732A zener to bias the VDIG to precisely 4.7V above V-. Figure 56b uses a high-voltage subregulator to derive the VDIG voltage. Figure 58 illustrates a detailed powerline communication circuit. RF V+ VOUT OPA564 VIN ISET +5V RLOAD IOUT VIN (1 + IOUT = RLOAD V- VSET 100mV ISET @ C1 100pF ILIM 20,000 ISET (0.4A to 1.5A) = 20mA to 75mA VSET RSET 5kW ILIM ILIM @ 20,000 ISET T1 2N2923 OPA333 + RF ) R1 and VSET (0.4A to 1.5A) = 100mV to 375mV ISET Figure 53. Programmable Current Limit Option Note (3) R1 5kW C1 0.1mF V+ C2 47mF (1) R2 20kW Z1 (2) S1 VIN G=- VDIG R2 R1 = -4 OPA564 (2) S2 10W (Noninductive) Motor 0.01mF C1 0.1mF C2 47mF V- (1) Z2 Note (3) (1) Z1, Z2 = zener diodes (IN5246 or equivalent). Select Z1 and Z2 diodes that are capable of the maximum anticipated surge current. (2) S1, S2 = Schottky diodes (STPS1L40 or equivalent). (3) C1 = high-frequency bypass capacitors; C2 = low-frequency bypass capacitors (minimum of 10F for every 1A peak current) Figure 54. Motor Drive Circuit 26 Copyright (c) 2011, Texas Instruments Incorporated OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com Note (4) +12V C2 47mF C1 0.1mF (2) Z1 R1 1kW R2 10kW VIN VDIG (3) S1 (1) OPA564 R3 5kW RM = 12W (3) RSET RM S2 C2 47mF C1 0.1mF dc Motor EMF (2) Z2 -12V Note (4) RS 1W (1) IFLAG and TFLAG connections are not shown. (2) Z1, Z2 = zener diodes (IN5246 or equivalent). Select Z1 and Z2 diodes that are capable of the maximum anticipated surge current. (3) S1, S2 = Schottky diodes (STPS1L40 or equivalent). (4) C1 = high-frequency bypass capacitors; C2 = low-frequency bypass capacitors (minimum of 10F for every 1A peak current). Figure 55. DC Motor Speed Controller (without Tachometer) IIN IOUT IN CI1 1000mF V+ 1 5 OUT CI2 100nF COUT 22mF REXT 5kW TLE4275-Q1 10kW VDIG IRO DELAY VIN ID,c 4.7V Zener 1N4732A ID,d 4 2 RESET VOUT 3 GND V- (a) VD CD 47nF IGND VRD (b) Figure 56. Circuits for Generating VDIG Copyright (c) 2011, Texas Instruments Incorporated 27 OPA564-Q1 SBOS567 - JUNE 2011 www.ti.com V+ VDIG +5V -IN VOUT OPA564 0.1mF +IN TSENSE V- 10kW (typ) 1 50W 2 50pF 3 V+ D+ 10kW (typ) 10kW (typ) 8 SCL TMP411 7 SDA D- 10kW (typ) SMBus Controller 6 ALERT/THERM2 4 Over-Temperature Fault THERM GND 5 Figure 57. Temperature Measurement Using TSENSE and TMP411 +3.3V R46 10k R47 10k +3.3V C2 5 30k C11 R49 10k R13 C6 C5 82pF R7 2.67k 4 R10 1 6.8k 100nF +3.3V 0.1uF GND U1 0.1uF GND 5 150pF C1 R6 15k R8 3 U2 R14 3.3k 4 C9 1 1.47k 3 1.0uF OPA 365 OPA 365 2 R11 C7 820pf 30k C8 10nF 2 R48 10k GND TP1 1 Test Point TEST POINT +3.3V 1 TEST POINT Gnd GND Test Point R45 0 ohm J3 1 2 3 4 5 6 7 8 9 10 11 12 TXRX 1 2 3 4 5 6 7 8 9 10 11 12 TXDRVEN_GPIO32 ADCIN LED GPIO20 LED GPIO21 LED GPIO22 GND 12 HEADER +15V TXDRVEN_GPIO32 R16 1 TEST POINT 2.49k 1 TEST POINT TP3 1 TEST POINT TP4 R19 Test Point 2700pF +3.3V C13 0.1uF 5 L1 1uH, 1.075A R20 LB3218T1ROM 0 ohm +3.3V C15 100nF 2 P2 1 Heat sink Pads 10 uF Pad 1 GND FREE PAD GND 1 C20 0.1uF +3.3V GND Pad FREE PAD C14 D5 B350A-13-F or equivalent C99 50pF 21 22 23 24 25 26 27 28 GND 1.0 ohms OPA 365 R23 10.0k P1 GND OPA564AIDWP 16.5k R21 1 3 228 ohm TXRX GND U5 4 R5 JP5 JUMPER 1SMB5930 or equivalent D4 B350A-13-F 20 19 18 17 16 15 14 13 12 11 R17 R18 12.0k 228 ohm C18 0.1uF VVV+ V+pwrSence TFLG V+pwr E/S V+pwr +IN Vout -IN Vout VDIG V-pwr IFLAG V-pwr ISET TSENSE VV- R25 10k Test Point +3.3V D3 LED R22 TP8 Test Point C12 228 ohm R3 LED 1 2 3 4 5 6 7 8 9 10 10.0k R4 C19 10uF U4 C17 0.1uF R24 10k 10.0k LED D2 10k +15V 12 HEADER D1 GND R50 GND 2 SPISOMIA_GPIO17 SPISIMOA_GPIO16 SPICLKA_GPIO18 SPISTEA_GPIO19 PWM2_GPIO02 PWM1_GPIO00 1 J2 +15V GND Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd GND C16 0.1uF Test Point TEST POINT TP2 35 Gnd 34 Gnd 33 Gnd 32 Gnd 31 Gnd 30 Gnd 29 Gnd Power Pad OPA564 GND GND L3 470uH D6 B350A-13-F C22 22nf GND GND C40 R27 150 ohm C21 L2 330uH 10uF 1 D7 B350A-13-F 33nf Test Point TEST POINT R26 150 ohm TP7 +3.3V C26 R34 3.83k 0.1uF C29 82pf GND +3.3V C30 82pf R35 4.4k C25 0.1uF 5 GND R31 R28 3.83k 15.4k 5 GND U6 4 1 3 R32 R29 4.4k 4.4k U7 4 1 3 OPA 365 OPA 365 2 2 C23 470pf GND C24 1500pf GND 1 Test Point TEST POINT TP6 TP5 1 Test Point TEST POINT +3.3V C36 GND U10 ADCIN 1 2 3 4 5 AVDD CH1 CH0/VCAL Vref Vout SPISIMOA_GPIO16 GND 0.1uF DVDD NOT CS DIO SCLK GND 10 9 8 7 6 C37 0.1uF +3.3V SPISTEA_GPIO19 0.0 ohm R41 SPISOMIA_GPIO17 SPICLKA_GPIO18 PGA112 Figure 58. Detailed Powerline Communication Circuit 28 Copyright (c) 2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 2-Jul-2011 PACKAGING INFORMATION Orderable Device OPA564AQDWPRQ1 Status (1) ACTIVE Package Type Package Drawing SO PowerPAD DWP Pins Package Qty 20 2000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF OPA564-Q1 : * Catalog: OPA564 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device OPA564AQDWPRQ1 Package Package Pins Type Drawing SO Power PAD DWP 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.3 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA564AQDWPRQ1 SO PowerPAD DWP 20 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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