© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 4 1Publication Order Number:
MC75172B/D
MC75172B, MC75174B
Quad EIA−485 Line Drivers
with Three−State Outputs
The ON Semiconductor MC75172B/174B Quad Line drivers are
differential high speed drivers designed to comply with the EIA−485
Standard. Features include three−state outputs, thermal shutdown, and
output current limiting in both directions. These devices also comply
with EIA−422−A, and CCITT Recommendations V.11 and X.27.
The MC75172B/174B are optimized for balanced multipoint bus
transmission at rates in excess of 10 MBPS. The outputs feature wide
common mode voltage range, making them suitable for party line
applications in noisy environments. The current limit and thermal
shutdown features protect the devices from line fault conditions.
These devices offer optimum performance when used with the
MC75173 and MC75175 line receivers.
Both devices are available in 16−pin plastic PDIP and 20−pin wide
body surface mount packages.
Features
•Meets EIA−485 Standard for Party Line Operation
•Meets EIA−422−A and CCITT Recommendations V.11 and X.27
•Operating Ambient Temperature: −40°C to +85°C
•High Impedance Outputs
•Common Mode Output Voltage Range: −7.0 to 12 V
•Positive and Negative Current Limiting
•Transmission Rates in Excess of 10 MBPS
•Thermal Shutdown at 150°C Junction Temperature, (±20°C)
•Single 5.0 V Supply
•Pin Compatible with TI SN75172/4 and NS mA96172/4
•Interchangeable with MC3487 and AM26LS31 for EIA−422−A
Applications
•Pb−Free Packages are Available*
MAXIMUM RATING
Rating Symbol Value Unit
Power Supply Voltage VCC −0.5, +7.0 Vdc
Input Voltage (Data, Enable) Vin +7.0 Vdc
Input Current (Data, Enable) Iin −24 mA
Applied Output Voltage, when in 3−State
Condition (VCC = 5.0 V) Vza −10, +14 Vdc
Applied Output Voltage, when VCC = 0 V Vzb ±14 Vdc
Output Current IOSelf−Limiting −
Storage Temperature Tstg −65, +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability .
1. Devices should not be operated at these limits. The “Recommended Operating
Conditions” table provides for actual device operation.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
PDIP−16
P SUFFIX
CASE 648
MARKING DIAGRAMS
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QUAD EIA−485 LINE DRIVERS
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
SOIC−20 WB
DW SUFFIX
CASE 751D
1
16
1
MC75174BP
AWLYYWWG
20
1
MC17517xBDW
AWLYYWWG
1
x = 2 or 4
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = W ork Week
G = Pb−Free Package
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RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Min Typ Max Unit
Power Supply V oltage VCC +4.75 +5.0 +5.25 Vdc
Input Voltage (All Inputs) Vin 0 − VCC Vdc
Output Voltage in 3−State Condition, or when VCC = 0 V Vcm −7.0 − +12 Vdc
Output Current (Normal data transmission) IO−65 − +65 mA
Operating Ambient Temperature (see text)
EIA−485
EIA−422
TA−40
0
− +85 °C
2. All limits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (−40°C p TA p 85°C, 4.75 V p VCC p 5.25 V, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Output Voltage
Single−Ended Voltage
IO = 0
High @ IO = −33 mA
Low @ IO = +33 mA
Differential Voltage
Open Circuit (IO = 0)
RL = 54 W (Figure 1)
VO
VOH
VOL
⎥VOD1⎜
⎥VOD2⎜
0
−
−
1.5
1.5
−
4.0
1.6
3.4
2.3
6.0
−
−
6.0
5.0
Vdc
Change in Differential*, RL = 54 W (Figure 1)
Differential Voltage, RL = 100 W (Figure 1)
Change in Differential*, RL = 100 W (Figure 1)
Differential Voltage, −7.0 V p Vcm p 12 V (Figure 2)
Change in Differential*, −7.0 V p Vcm p12 V (Figure 2)
Offset Voltage, RL = 54 W (Figure 1)
Change in Offset*, RL = 54 W (Figure 1)
⎥DVOD2⎜
⎥VOD2A⎜
⎥DVOD2A⎜
⎥VOD3⎜
⎥DVOD3⎜
VOS
⎥DVOS⎜
−
−
−
1.5
−
−
−
5.0
2.2
5.0
−
5.0
2.9
5.0
200
−
200
5.0
200
−
200
mVdc
Vdc
mVdc
Vdc
mVdc
Vdc
mVdc
Output Current (Each Output)
Power Off Leakage, VCC = 0, −7.0 V p VO p 12 V
Leakage in 3−State Mode, −7.0 V p VO p 12 V IO(off)
IOZ −50
−50 0
0+50
+50 mA
Short Circuit Current to Ground
Short Circuit Current, −7.0 V p VO p 12 V IOSR
IOS −150
−250 −
−+150
+250 mA
Inputs
Low Level Voltage (Pins 4 & 12, MC75174B only)
Low Level Voltage (All Other Pins)
High Level Voltage (All Inputs)
VIL(A)
VIL(B)
VIH
0
0
2.0
−
−
−
0.7
0.8
VCC
Vdc
Current @ Vin = 2.7 V (All Inputs)
Current @ Vin = 0.5 V (All Inputs) IIH
IIL −
−100 0.2
−15 20
−mA
Clamp Voltage (All Inputs, Iin = −18 mA) VIK −1.5 − − Vdc
Thermal Shutdown Junction Temperature Tjts − +150 − °C
Power Supply Current (Outputs Open, VCC = 5.25 V)
Outputs Enable
Outputs Disabled
ICC −
−60
30 70
40
mA
3. *Vin switched from 0.8 to 2.0 V. Typical values determined at 25°C ambient and 5.0 V supply.
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TIMING CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Characteristics Symbol Min Typ Max Unit
Propagation Delay − Input to Single−ended Output (Figure 3)
Output Low−to−High
Output High−to−Low tPLH
tPHL −
−23
18 30
30
ns
Propagation Delay − Input to Differential Output (Figure 4)
Input Low−to−High
Input High−to−Low tPLH(D)
tPHL(D) −
−15
17 25
25
ns
Differential Output Transition Time (Figure 4) tdr, tdf − 19 25 ns
Skew T iming
⎜tPLHD − tPHLD⎜ for Each Driver
Max − Min tPLHD Within a Package
Max − Min tPHLD Within a Package
tSK1
tSK2
tSK3
−
−
−
0.2
1.5
1.5
−
−
−
ns
Ena b l e Timing
Single−ended Outputs (Figure 5)
Enable to Active High Output
Enable to Active Low Output
Active High to Disable (using Enable)
Active Low to Disable (using Enable)
Enable to Active High Output (MC75172B only)
Enable to Active Low Output (MC75172B only)
Active High to Disable (using Enable, MC75172B only)
Active Low to Disable (using Enable, MC75172B only)
tPZH(E)
tPZL(E)
tPHZ(E)
tPLZ(E)
tPZH(E)
tPZL(E)
tPHZ(E)
tPLZ(E)
−
−
−
−
−
−
−
−
48
20
35
30
58
28
38
36
60
30
45
50
70
35
50
50
ns
Differential Outputs (Figure 6)
Enable to Active Output
Enable to Active Output (MC75172B only)
Enable to 3−State Output
Enable to 3−State Output (MC75172B only)
tPZD(E)
tPZD(E)
tPDZ(E)
tPDZ(E)
−
−
−
−
47
56
32
40
−
−
−
−
ns
PIN CONNECTIONS
MC75172B MC75174B
9
1
3A
3Y
3Z
En
12
4Z
4Y
4A
VCC
GND
2A
2Y
2Z
En
12
1Z
1A
1Y
P Package
2
3
4
5
6
7
8
16
15
14
13
12
11
DW Package
2A
8
7
6
5
4
4A
VCC
19
18
En
2Z
NC
10 11
9
1
3
En
17
4Y
GND
2Y
12
3A
14 3Z
4Z
15
16
1A
1Y 2
1Z NC
NC
NC
3Y
13
20
En
34 En
34
20
13
3Y
NC
NC
NC
1Z
2
1Y
1A
16
15
4Z
3Z14
12
2Y
GND
4Y
17
9
2A
8
7
6
5
4
4A
VCC
19
18
DW Package
2Z
NC
10 11
1
3
10
3A
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tdf
1.5 V
50%
tPHLD
3.0 V
tPLH
VOD
54 50 pF
Vin
VCC
VOD
VOD2,A
−1.5 V
50%
1.5 V
[4.6 V
tdr
S.G.
0 V
3.0 V
1.5 V
tPLHD
1.5 V
Vin
VCC
VOH
15 pF
Vin
Z
VCC
Vin
tPHL
(0.8 or 2.0 V)
VOS
(0.8 or 2.0 V)
RL/2
RL/2
VCC
Output Y
+
375
58
375
VOD3
VCM = 12 to −7.0 V
Y
Output
27 W
2.3 V
S.G.
Vin
3.0 V
3.0 V
tPLH
1.5 V
Output Z
Vin
VOL
0 V
3.0 V
1.5 V
tPHL
3.0 V
−1.5 V
NOTES: 1.S.G. set to: f p 1.0 MHz; duty cycle = 50%; tr, tf, p5.0 ns.
2.tSK1 = ⎥tPLHD − tPHLD⎥for each driver.
3.tSK2 computed by subtracting the shortest tPLHD from the longest tPLHD of the 4 drivers within a package.
4.tSK3 computed by subtracting the shortest tPHLD from the longest tPHLD of the 4 drivers within a package.
Figure 1. V DD Measurement Figure 2. Common Mode Test
Figure 3. Propagation Delay, Single−Ended Outputs
Figure 4. Propagation Delay, Differential Outputs
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tPZL(E)
1.5 V
Vout 2.3 V
1.5 V
VOL
0.5 V
tPLZ(E)
0 V
3.0 V
VCC
Vout
Vin
50 pF
110W
Vout
S.G.
Vin
Vout
110W
50 pF
VCC
VCC
0.5 V
VOH
0 V
tPHZ(E)
1.5 V
3.0 V
Vin 1.5 V
Vin
S.G.
2.3 V
0 or 3.0 V
3.0 V
3.0 V
0 or 3.0 V
tPZH(E)
tPDZ(E)
1.5 V
0
0 V
3.0 V
1.5 V
Active
tPZD(E)
S.G.
1.5 V
VOD
Disabled
VCC
Vin
0 or 3.0 V
3.0 V
VOD
50 pF
54
1.5 V
0
Vin
Disabled
NOTES: 1.S.G. set to: f p 1.0 MHz; duty cycle = 50%; tf, tf, p 5.0 ns.
2.Vin is inverted for Enable measurements.
Figure 5. Enable Timing, Single−Ended Outputs
Figure 6. Enable Timing, Differential Outputs
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Figure 7. Single−Ended Output Voltage
versus Output Sink Current Figure 8. Single−Ended Output Voltage
versus Temperature
Figure 9. Single−Ended Output Voltage
versus Output Source Current Figure 10. Single−Ended Output
Voltage versus Temperature
Figure 11. Output Differential Voltage
versus Load Current Figure 12. Output Differential Voltage
versus Temperature
IO, OUTPUT CURRENT (mA)
IO
VCC = 4.75 V
VOD
VCC = 5.0 V
VCC = 5.25 V
IOVOD
0.8 or
2.0 V
−40
1.0
VCC = 5.00 V
VCC = 5.25 V
IO = 20.0 mA
2.0
85
0
VCC = 4.75 V
3.0
TA, AMBIENT TEMPERATURE (°C)
1.0
4.0
20 40 60−20
VCC = 4.75 V
TA = 25°C
4.0
IOH, OUTPUT CURRENT (mA)
1.0
70
5.0
2.0
−100−30−20 −40 −50
60
−60
3.0
TA, AMBIENT TEMPERATURE (°C)
−70
IOH = −27.8 mA
VCC = 4.75 V
3.25
85
4.0
−40 0−20 6040
0.5
IOL, OUTPUT CURRENT (mA)
1.5
1.0
002010 30 40 50 60 70
2.0
4.75V pVCC p5.25 V
TA = 25°C
1.25
1.5
1.75
1.0
−40 0−20
2.0
0
85604020
4.75 V p VCC p 5.25 V
IOL = 27.8 mA
IOL = 20.0 mA
5030 40020
3.0
10
4.0
20
3.75
TA, AMBIENT TEMPERATURE (°C)
3.5
2.0
0
IO = 27.8 mA
, OUTPUT VOLTAGE (V)
VOL
, OUTPUT VOLTAGE (V)
VOL
, OUTPUT VOLTAGE (V)
VOH
, OUTPUT VOLTAGE (V)
VOH
, DIFFERENTIAL OUTPUT VOLTAGE (V)
VOD
IOH = −20.0 mA
0.8 or
2.0 V
TA = 25°C
, DIFFERENTIAL OUTPUT VOLTAGE (V)
VOD
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Figure 13. Output Leakage Current
versus Output Voltage Figure 14. Output Leakage Current
versus Temperature
Figure 15. Input Current
versus Input Voltage Figure 16. Short Circuit Current
versus Common Mode Voltage
9.00.5
−25
4.5
Vin, INPUT VOLTAGE (V)
−0.5 3.52.51.5 −150
Vz, APPLIED OUTPUT VOLTAGE (V)
−7.0 −3.05.5 5.0 121.0
Normally Low Output
Enable
Pins
Driver
Inputs
4.75 p VCC p 5.25 V
TA = 25°C
5.0
0
−5.0
−15
−10
−30
0
30
90
−20
150
Normally High Output
−9
0
Vout = +12 V
−20 85
20
10
−15
Vout = 7.0 V
−10
0−20
2.0
Vz, APPLIED OUTPUT VOLTAGE (V)
−1.0
0
1.0
−7.0
−2.0 1.0−3.0 5.0 9.0 12 −40
En = Low, En = High
or VCC = 0 V
5.0
15
0
TA = 25°C
En = Low, En = High
20
−5.0
60
TA = 25°C
4.75 p VCC p 5.25 V
TA, AMBIENT TEMPERATURE (°C)
40
IOZ, LEAKAGE CURRENT (μA)
IOZ, LEAKAGE CURRENT (μA)I ,
OX
Iin, INPUT CURRENT (
μA)
IOS, SHORT CIRCUIT CURRENT (mA)
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APPLICATIONS INFORMATION
Description
The MC75172B and MC75174B are differential line
drivers designed to comply with EIA−485 Standard (April
1983) for use in balanced digital multipoint systems
containing multiple drivers. The drivers also comply with
EIA−422−A and CCITT Recommendations V.11 and X.27.
The drivers meet the EIA−485 requirement for protection
from damage in the event that two or more drivers attempt
to transmit data simultaneously on the same cable. Data
rates in excess of 10 MBPS are possible, depending on the
cable length and cable characteristics. A single power
supply, 5.0 V, ±5%, is required at a nominal current of
60 mA, plus load currents.
Outputs
Each output (when active) will be a low or a high voltage,
which depends on the input state and the load current (see
Table 1, 2 and Figures 7 to 10). The graphs apply to each
driver, regardless of how many other drivers within the
package are supplying load current.
Table 1. MC75172B T ruth Table
Data Input
Enables Outputs
EN EN Y Z
H
L
H
L
X
H
H
X
X
L
X
X
L
L
H
H
L
H
L
Z
L
H
L
H
Z
Table 2. MC75174B T ruth Table
Data Input Enable
Outputs
Y Z
H
L
X
H
H
L
H
L
Z
L
H
Z
H = Logic high, L = Logic low, X = Irrelevant, Z = High impedance
The two outputs of a driver are always complementary.
A “high” output can only source current out, while a “low”
output can only sink current (except for short circuit current
− see Figure 16).
The outputs will be in the high impedance mode when:
the Enable inputs are set according to Table 1 or 2;a)
VCC is less than 1.5 V;
the junction temperature exceeds the trip point of
the thermal shutdown circuit (see below). When in
this condition, the output’s source and sink
capability are shut off, and only leakage currents
will flow (see Figures 13, 14). Disabled outputs may
be taken to any voltage between −7.0 V and 12 V
without damage.
b)
c)
The drivers are protected from short circuits by two
methods:
Current limiting is provided at each output, in both
the source and sink direction, for shorts to any
voltage within the range of 12V to −7.0V, with
respect to circuit ground (see Figure 16). The short
circuit current will flow until the fault is removed, or
until the thermal shutdown circuit activates (see
below). The current limiting circuit has a negative
temperature coefficient and requires no resetting
upon removal of the fault condition.
a)
A thermal shutdown circuit disables the outputs
when the junction temperature reaches 150°C,
±20°C. The thermal shutdown circuit has a
hysteresis of ≈ 12°C to prevent oscillations. When
this circuit activates, the output stage of each driver
is put into the high impedance mode, thereby
shutting off the ou t p u t c u r r e n t s . T h e r e m ainder of t h e
internal circuitry remains biased. The outputs will
become active once again as the IC cools down.
b)
Driver Inputs
The driver inputs determine the state of the outputs in
accordance with Tables 1 and 2. The driver inputs have a
nominal threshold of 1.2 V, and their voltage must be kept
within the range of 0 V to VCC for proper operation. If the
voltage is taken more than 0.5 V below ground, excessive
currents will flow, and proper operation of the drivers will
be affected. An open pin is equivalent to a logic high, but
good design practices dictate that inputs should never be
left open. The characteristics of the driver inputs are shown
in Figure 15. This graph is not affected by the state of the
Enable pins.
Enable Logic
Each driver’s outputs are active when the Enable inputs
(Pins 4 and 12) are true according to Tables 1 and 2.
The Enable inputs have a nominal threshold of 1.2 V and
their voltage must be kept within the range of 0 V to VCC
for proper operation. If the voltage is taken more than 0.5 V
below ground, excessive currents will flow, and proper
operation of the drivers will be affected. An open pin is
equivalent to a logic high, but good design practices dictate
that inputs should never be left open. The Enable input
characteristics are shown in Figure 15.
Operating Temperature Range
The minimum ambient operating temperature is listed as
−40°C to meet EIA−485 specifications, and 0°C to meet
EIA−422−A specifications. The higher VOD required by
EIA−422−A is the r eason f or the narrower temperature range.
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The maximum ambient operating temperature
(applicable to both EIA−485 and EIA−422−A) is listed as
85°C. However, a lower ambient may be required
depending on system use (i.e. specifically how many
drivers within a package are used) and at what current
levels they are operating. The maximum power which may
be dissipated within the package is determined by:
PDmax +
T
Jmax
–T
A
RqJA
RqJA = package thermal resistance (typical
70°C/W for the DIP package, 85°C/W for
SOIC package);
TJmax = max. operating junction
temperature, and
T
A
= ambient temperature.
w
here:
Since the thermal shutdown feature has a trip point of
150°C, ±20°C, TJmax is selected to be 130°C. The power
dissipated within the package is calculated from:
= {[(V
CC
− V
OH
)
•
I
OH
] + V
OL
•
I
OL
)} each
driver = + (VCC • ICC)
VCC = the supply voltage;
VOH, VOL are measured or estimated from
Figures 7 to 10;
ICC = the quiescent power supply current
(typical 60 mA).
PD
w
here:
As indicated in the equation, the first term (in brackets)
must be calculated and summed for each of the four drivers,
while the last term is common to the entire package.
Example 1: T
A = 25°C, IOL = IOH = 55 mA for each
driver, VCC = 5.0 V, DIP package. How many drivers per
package can be used?
Maximum allowable power dissipation is:
PDmax +130°C*25°C
70°CńW+1.5 W
Since the power supply current of 60 mA dissipates
300 mW, that leaves 1.2 W (1.5 W − 0.3 W) for the drivers.
From Figures 7 and 9, VOL [1.75 V, and VOH [3.85 V.
The power dissipated in each driver is:
{(5.0 − 3.85) • 0.055} + (1.75 • 0.055) = 160 mW.
Since each driver dissipates 160 mW, the four drivers per
package could be used in this application.
Example 2 : TA = 85°C, I OL = 27.8 mA, IOH = 20 mA for
each d river, V CC = 5.0 V, S OIC package. How m any d rivers
per packa ge can be use d?
Maximum allowable power dissipation is:
PDmax +130°C*85°C
85°CńW+0.53 W
Since the power supply current of 60 mA dissipates
300 mW, that leaves 230 mW (530 mW − 300 mW) for the
drivers. From Figures 8 and 10 (adjusted for VCC = 5.0 V),
VOL [1.38 V, and VOH [4.27 V. The power dissipated
in each driver is:
{(5.0 − 4.27) • 0.020} + (1.38 • 0.0278) = 53 mW
Since each driver dissipates 53 mW, the use of all four
drivers in a package would be marginal. Options include
reducing the load current, reducing the ambient
temperature, and/or providing a heat sink.
System Requirements
EIA−485 requires each driver to be capable of
transmitting data differentially to a t least 32 unit loads, plus
an equivalent DC termination resistance of 60W, over a
common mode voltage of −7.0 to 12 V. A unit load (U.L.),
as defined by EIA−485, is shown in Figure 17.
Figure 17. Unit Load Definition
1.0 mA
V
5.0 V
−3.0 V
−7.0 V
12 V
−0.8 mA
Reprinted from EIA−485, Electronic Industries Association,
Washington,DC.
I
A load current within the shaded regions represents an
impedance of less than one U.L., while a load current of a
magnitude outside the shaded area is greater than one U.L.
A system’s total load is the sum of the unit load equivalents
of each receiver’s input current, and each disabled driver’s
output leakage current. The 60W termination resistance
mentioned above allows for two 120W terminating
resistors.
Using the EIA−485 requirements (worst case limits), and
the graphs of Figures 7 and 9, it can be determined that the
maximum current an MC75172B or MC75174B driver will
source or sink is [65 mA.
System Example
An example of a typical EIA−485 system is shown in
Figure 18. In this example, it is assumed each receiver’s
input characteristics correspond to 1.0 U.L. as defined in
Figure 17. Each “off” driver, with a maximum leakage of
±50 mA over the common mode range, presents a load of
[0.06 U.L. The total load for the active driver is therefore
8.3 unit loads, plus the parallel combination of the two
terminating resistors (60W). It is up to the system software
to control the driver Enable pins to ensure that only one
driver is active at any time.
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Termination Resistors
Transmission line theory states that, in order to preserve
the shape and integrity of a waveform traveling along a
cable, the cable must be terminated in an impedance equal
to its characteristic impedance. In a system such as that
depicted in Figure 18, in which data can travel in both
directions, both physical ends of the cable must be
terminated. Stubs, leading to each receiver and driver,
should be as short as possible.
Leaving off the terminations will generally result in
reflections which can have amplitudes of several volts
above VCC or below ground. These overshoots and
undershoots can disrupt the driver and/or receiver
operation, create false data, and in some cases damage
components on the bus.
Figure 18. Typical EIA−485 System
NOTES: 1.Terminating resistors RT must be located at the physical ends of the cable.
2.Stubs should be as short as possible.
3.Circuit ground of all drivers and receivers must be connected via a dedicated wire within the cable.
Do not rely on chassis ground or power line ground.
#8
TTL
R
TTL
TTL
#3
TTL R
En
#2
TTL
TTL
En
TTL
R
TTL
#1
R
TTL RT
#1
En
D
#3
D
#5
D
TTL
En
#6
RTTL
R
En
#5
R
#6
D
#7
RT
TTL TTL
R
En
TTL
#4
D
5 “of f” drivers (@ 0.06 U.L. each),
+8 receivers (@ 1.0 U.L. each) = 8.3 Unit Loads
RT = 120 W at each end of the cable.
#4
D
#2
120 W
Twisted
Pair
MC75172B, MC75174B
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11
COMPARING SYSTEM REQUIREMENTS
Characteristic Symbol EIA−485 EIA−422−A V.11 and X.27
GENERATOR (Driver)
Output Impedance (Note 1) Zout Not Specified t100 W50 10 100 W
Open Circuit Voltage
Differential
Single−Ended VOCD
VOCS 1.5 to 6.0 V
t6.0 V p6.0 V
p6.0 V p6.0 V, w/3.9 kW, Load
p6.0 V, w/3.9 kW, Load
Loaded Differential Voltage VOD 1.5 to 5.0 V, w/54 W load q2.0 V or q 0.5 VOCD,
w/100 W load q2.0 V or q0.5 VOCD,
w/100 W load
Differential Voltage Balance DVOD t200 mV p400 mV t400 mV
Output Common Mode Range VCM −7.0 to +12 V Not Specified Not Specified
Of fset Voltage VOS −1.0 t VOS t 3.0 V p3.0 V p3.0 V
Offset Voltage Balance DVOS t200 mV p400 mV t400 mV
Short Circuit Current IOS p250 mA for −7.0 to 12 V p150 mA to ground p150 mA to ground
Leakage Current (VCC = 0) IOLK Not Specified p100 mA to −0.25 V thru
6.0 V p100 mA to ± 0.25 V
Output Rise/Fall Time (Note 2) tr, tfp0.3 TB, w/54 W/1150 pF
load p0.1 TB or p 20 ns, w/100
W load p0.1 TB or p 20 ns, w/100
W load
RECEIVER
Input Sensitivity Vth ± 200 mV ± 200 mV ±300 mV
Input Bias Voltage Vbias p3.0 V p3.0 V p3.0 V
Input Common Mode Range Vcm −7.0 to 12 V −7.0 to 7.0 V −7.0 to 7.0 V
Dynamic Input Impedance Rin Spec number of U.L. q4 kWq4 kW
NOTES: 1. Compliance with V.11 and X.27 (Blue book) output impedance requires external resistors in series with the outputs of the
MC75172B and MC75174B.
2. TB = Bit time. Additional Information
Copies of the EIA Recommendations (EIA−485 and EIA−422−A) can be obtained from the Electronics Industries
Association, Washington, D.C. (202−457−4966). Copies of the CCITT Recommendations (V.11 and X.27) can be obtained
from the United States Department of Commerce, Springfield, VA (703−487−4600).
ORDERING INFORMATION
Device Operating Temperature Range Package Shipping†
MC75172BDW
TA = −40° to +85°C
SOIC−20WB 38 Units / Rail
MC75172BDWG SOIC−20WB
(Pb−Free)
MC75172BDWR2 SOIC−20WB 1000 / Tape & Reel
MC75172BDWR2G SOIC−20WB
(Pb−Free)
MC75174BDW SOIC−20WB 38 Units / Rail
MC75174BDWG SOIC−20WB
(Pb−Free)
MC75174BDWR2 SOIC−20WB 1000 / Tape & Reel
MC75174BDWR2G SOIC−20WB
(Pb−Free)
MC75174BP PDIP−16 25 Units / Rail
MC75174BPG PDIP−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC75172B, MC75174B
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12
PACKAGE DIMENSIONS
SOIC−20 W B
DW SUFFIX
PLASTIC PACKAGE
CASE 751D−05
ISSUE G
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
q
hX 45_
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
eT
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
__
PDIP−16
P SUFFIX
PLASTIC PACKAGE
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
MC75172B, MC75174B
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13
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