© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 6
1Publication Order Number:
MC74VHC4051/D
MC74VHC4051,
MC74VHC4052,
MC74VHC4053
Analog Multiplexers /
Demultiplexers
High−Performance Silicon−Gate CMOS
The MC74VHC4051, MC74VHC4052 and MC74VHC4053 utilize
silicon−gate CMOS technology to achieve fast propagation delays,
low ON resistances, and low OFF leakage currents. These analog
multiplexers/demultiplexers control analog voltages that may vary
across the complete power supply range (from VCC to VEE).
The VHC4051, VHC4052 and VHC4053 are identical in pinout to
the high−speed HC4051A, HC4052A and HC4053A, and the
metal−gate MC14051B, MC14052B and MC14053B. The
Channel−Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to the
Common Output/Input. When the Enable pin is HIGH, all analog
switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal−gate CMOS analog
switches.
•Fast Switching and Propagation Speeds
•Low Crosstalk Between Switches
•Diode Protection on All Inputs/Outputs
•Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V
•Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V
•Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
•Low Noise
•Chip Complexity: VHC4051 — 184 FETs or 46 Equivalent Gates
VHC4052 — 168 FETs or 42 Equivalent Gates
VHC4053 — 156 FETs or 39 Equivalent Gates
•These Devices are Pb−Free and are RoHS Compliant
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MARKING
DIAGRAMS
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
ORDERING INFORMATION
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
18
9
16
18
16 9
VHC405xG
AWLYYWW
VHC405x = Specific Device Code
(x = 1, 2 or 3)
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G= Pb−Free Package
VHC
405x
ALYWG
G
SOIC EIAJ−16
M SUFFIX
CASE 966 1
16 9
8
VHC405x
ALYWG
(Note: Microdot may be in either location)
MC74VHC4051, MC74VHC4052, MC74VHC4053
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2
MC74VHC4051
Single−Pole, 8−Position Plus Common Off
X0 13
X1 14
X2 15
X3 12
X4 1
X5 5
X6 2
X7 4
A11
B10
C9
ENABLE 6
MULTIPLEXER/
DEMULTIPLEXER
X
3
ANALOG
INPUTS/
CHANNEL
INPUTS
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUT/
INPUT
OUTPUTS
SELECT
MC74VHC4052
Double−Pole, 4−Position Plus Common Off
X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
A10
B9
ENABLE 6
X SWITCH
Y SWITCH
X
13
ANALOG
INPUTS/OUTPUTS
CHANNEL‐SELECT
INPUTS PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
Y
3
MC74VHC4053
Triple Single−Pole, Double−Position Plus Common Off
X0 12
X1 13
A11
B10
C9
ENABLE 6
X SWITCH
Y SWITCH
X
14
ANALOG
INPUTS/OUTPUTS
CHANNEL‐SELECT
INPUTS
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
Y0 2
Y1 1Y
15
Z0 5
Z1 3Z
4
Z SWITCH
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls
the Y−Switch and Input C controls the Z−Switch
Figure 1. Logic Diagrams
MC74VHC4051, MC74VHC4052, MC74VHC4053
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3
1516 14 13 12 11 10
21 34567
VCC
9
8
X2 X1 X0 X3 A B C
X4 X6 X X7 X5 Enable VEE GND
Figure 2. Pinout: MC74VHC4051 (Top View)
Figure 3. Pinout: MC74VHC4052 (Top View)
1516 14 13 12 11 10
21 34567
VCC
9
8
X2 X1 X X0 X3 A B
Y0 Y2 Y Y3 Y1 Enable VEE GND
Figure 4. Pinout: MC74VHC4053 (Top View)
1516 14 13 12 11 10
21 34567
VCC
9
8
Y X X1 X0 A B C
Y1 Y0 Z1 Z Z0 Enable VEE GND
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
FUNCTION TABLE − MC74VHC4051
Control Inputs
ON Channels
Enable
Select
CBA
X0
X1
X2
X3
X4
X5
X6
X7
NONE
L
L
L
L
L
L
L
L
H
X = Don’t Care
L
L
H
H
X
L
H
L
H
X
FUNCTION TABLE − MC74VHC4052
Control Inputs
ON Channels
Enable
Select
BA
X0
X1
X2
X3
L
L
L
L
H
X = Don’t Care
Y0
Y1
Y2
Y3
NONE
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
FUNCTION TABLE − MC74VHC4053
Control Inputs
ON Channels
Enable
Select
CBA
L
L
L
L
L
L
L
L
H
X = Don’t Care
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
X0
X1
X0
X1
NONE
MC74VHC4051, MC74VHC4052, MC74VHC4053
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4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎ
ÎÎÎÎÎ
Value
ÎÎÎ
ÎÎÎ
Unit
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
– 0.5 to + 7.0
– 0.5 to + 14.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Negative DC Supply Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
– 7.0 to + 5.0
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Analog Input Voltage
ÎÎÎÎÎ
ÎÎÎÎÎ
VEE − 0.5 to
VCC + 0.5
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
Vin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Digital Input Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
– 0.5 to VCC + 0.5
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
I
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Current, Into or Out of Any Pin
ÎÎÎÎÎ
ÎÎÎÎÎ
±25
ÎÎÎ
ÎÎÎ
mA
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Power Dissipation in Still Air SOIC Package†
TSSOP Package†
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
500
450
ÎÎÎ
ÎÎÎ
ÎÎÎ
mW
ÎÎÎÎ
ÎÎÎÎ
Tstg
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Storage Temperature Range
ÎÎÎÎÎ
ÎÎÎÎÎ
– 65 to + 150
ÎÎÎ
ÎÎÎ
_C
ÎÎÎÎ
ÎÎÎÎ
TL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎ
ÎÎÎÎÎ
260
ÎÎÎ
ÎÎÎ
_C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎ
ÎÎÎ
Min
ÎÎÎ
ÎÎÎ
Max
Unit
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
2.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
6.0
12.0
V
ÎÎÎÎ
ÎÎÎÎ
VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Negative DC Supply Voltage, Output (Referenced to GND)
ÎÎÎ
ÎÎÎ
− 6.0
ÎÎÎ
ÎÎÎ
GND
V
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Analog Input Voltage
ÎÎÎ
ÎÎÎ
VEE
ÎÎÎ
ÎÎÎ
VCC
V
ÎÎÎÎ
ÎÎÎÎ
Vin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Digital Input Voltage (Referenced to GND)
ÎÎÎ
ÎÎÎ
GND
ÎÎÎ
ÎÎÎ
VCC
V
ÎÎÎÎ
ÎÎÎÎ
VIO*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Static or Dynamic Voltage Across Switch
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.2
V
ÎÎÎÎ
ÎÎÎÎ
TA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature Range, All Package Types
ÎÎÎ
ÎÎÎ
– 55
ÎÎÎ
ÎÎÎ
+ 125
_C
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Rise/Fall Time VCC = 2.0 V
(Channel Select or Enable Inputs) VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
ÎÎÎ
ÎÎÎ
ÎÎÎ
0
0
0
0
ÎÎÎ
ÎÎÎ
ÎÎÎ
1000
800
500
400
ns
*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74VHC4051, MC74VHC4052, MC74VHC4053
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5
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbol Parameter Condition
VCC
V
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
VIH Minimum High−Level Input
Voltage, Channel−Select or
Enable Inputs
Ron = Per Spec 2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL Maximum Low−Level Input
Voltage, Channel−Select or
Enable Inputs
Ron = Per Spec 2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
Iin Maximum Input Leakage Current,
Channel−Select or Enable Inputs
Vin = VCC or GND,
VEE = − 6.0 V
6.0 ±0.1 ±1.0 ±1.0 μA
ICC Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
VIS = VCC or GND; VEE = GND
VIO = 0 V VEE = − 6.0
6.0
6.0
1
4
10
40
40
80
μA
DC ELECTRICAL CHARACTERISTICS Analog Section
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Test Conditions
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VCC
V
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VEE
V
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Unit
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
– 55 to
25_C
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
v 85_C
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
v 125_C
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Ron
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Maximum “ON” Resistance
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Vin = VIL or VIH
VIS = VCC to VEE
IS v 2.0 mA
(Figures 5 through 11)
ÎÎÎ
ÎÎÎ
ÎÎÎ
3.0
4.5
4.5
6.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.0
0.0
– 4.5
– 6.0
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
200
160
120
100
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
240
200
150
125
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
320
280
170
140
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Ω
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Vin = VIL or VIH
VIS = VCC or VEE (Endpoints)
IS v 2.0 mA
(Figures 5 through11)
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
3.0
4.5
4.5
6.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.0
0.0
– 4.5
– 6.0
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
150
110
90
80
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
180
140
120
100
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
230
190
140
115
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ΔRon
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Vin = VIL or VIH
VIS = 1/2 (VCC − VEE)
IS v 2.0 mA
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
3.0
4.5
4.5
6.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.0
0.0
– 4.5
– 6.0
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
40
20
10
10
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
50
25
15
12
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
80
40
18
14
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Ω
Ioff Maximum Off−Channel Leakage
Current, Any One Channel
Vin = VIL or VIH;
VIO = VCC − VEE;
Switch Off (Figure 12)
6.0 − 6.0 0.1 0.5 1.0
μA
Maximum Off−ChannelVHC4051
Leakage Current, VHC4052
Common Channel VHC4053
Vin = VIL or VIH;
VIO = VCC − VEE;
Switch Off (Figure 13)
6.0
6.0
6.0
− 6.0
− 6.0
− 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
Ion Maximum On−Channel VHC4051
Leakage Current, VHC4052
Channel−to−Channel VHC4053
Vin = VIL or VIH;
Switch−to−Switch =
VCC − VEE; (Figure 14)
6.0
6.0
6.0
− 6.0
− 6.0
− 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
μA
MC74VHC4051, MC74VHC4052, MC74VHC4053
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6
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol Parameter
VCC
V
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
tPLH,
tPHL
Maximum Propagation Delay, Channel−Select to Analog Output
(Figures 18, 19)
2.0
3.0
4.5
6.0
270
90
59
45
320
110
79
65
350
125
85
75
ns
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figures 20, 21)
2.0
3.0
4.5
6.0
40
25
12
10
60
30
15
13
70
32
18
15
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog Output
(Figures 22, 23)
2.0
3.0
4.5
6.0
160
70
48
39
200
95
63
55
220
110
76
63
ns
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog Output
(Figures 22, 23)
2.0
3.0
4.5
6.0
245
115
49
39
315
145
69
58
345
155
83
67
ns
Cin Maximum Input Capacitance, Channel−Select or Enable Inputs 10 10 10 pF
CI/O Maximum Capacitance Analog I/O 35 35 35 pF
(All Switches Off) Common O/I: VHC4051
VHC4052
VHC4053
130
80
50
130
80
50
130
80
50
Feedthrough 1.0 1.0 1.0
CPD Power Dissipation Capacitance (Figure 25)* VHC4051
VHC4052
VHC4053
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
pF
45
80
45
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
MC74VHC4051, MC74VHC4052, MC74VHC4053
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7
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol Parameter Condition
VCC
V
VEE
V
Limit*
Unit
25°C
BW Maximum On−Channel Bandwidth
or Minimum Frequency Response
(Figure 15)
fin = 1MHz Sine Wave; Adjust fin Voltage to
Obtain 0dBm at VOS; Increase fin
Frequency Until dB Meter Reads −3dB;
RL = 50Ω, CL = 10pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
‘51 ‘52 ‘53 MHz
80
80
80
95
95
95
120
120
120
— Off−Channel Feedthrough Isolation
(Figure 16)
fin = Sine Wave; Adjust fin Voltage to
Obtain 0dBm at VIS
fin = 10kHz, RL = 600Ω, CL = 50pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−50
−50
−50
dB
fin = 1.0MHz, RL = 50Ω, CL = 10pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−40
−40
−40
—Feedthrough Noise.
Channel−Select Input to Common
I/O (Figure 17)
Vin ≤ 1MHz Square Wave (tr = tf = 6ns);
Adjust RL at Setup so that IS = 0A;
Enable = GND RL = 600Ω, CL = 50pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
25
105
135
mVPP
RL = 10kΩ, CL = 10pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
35
145
190
—Crosstalk Between Any Two
Switches (Figure 24)
(Test does not apply to VHC4051)
fin = Sine Wave; Adjust fin Voltage to
Obtain 0dBm at VIS
fin = 10kHz, RL = 600Ω, CL = 50pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−50
−50
−50
dB
fin = 1.0MHz, RL = 50Ω, CL = 10pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−60
−60
−60
THD Total Harmonic Distortion
(Figure 26)
fin = 1kHz, RL = 10kΩ, CL = 50pF
THD = THDmeasured − THDsource
VIS = 4.0VPP sine wave
VIS = 8.0VPP sine wave
VIS = 11.0VPP sine wave
2.25
4.50
6.00
−2.25
−4.50
−6.00
0.10
0.08
0.05
%
*Limits not tested. Determined by design and verified by qualification.
Figure 5. Typical On Resistance, VCC − VEE = 2.0 V Figure 6. Typical On Resistance, VCC − VEE = 3.0 V
250
200
150
100
50
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
100
80
60
40
20
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.25
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
25°C
-55°C
125°C
25°C
-55°C
125°C
2.0
0
300 180
160
140
120
02.5 2.75 3.0
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Figure 7. Typical On Resistance, VCC − VEE = 4.5 V Figure 8. Typical On Resistance, VCC − VEE = 6.0 V
120
100
80
60
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
75
60
45
30
15
0 1.0 2.0 3.0 4.0 5.0 6.03.5 4.5 5.5
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
20
0
25°C
-55°C
125°C
25°C
-55°C
125°C
90
105
00.5 1.5 2.5
Figure 9. Typical On Resistance, VCC − VEE = 9.0 V Figure 10. Typical On Resistance, VCC − VEE = 12.0 V
-4.5 -3.5
70
60
50
40
30
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
20
10
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5
25°C
-55°C
125°C
80
0-6.0 -5.0
60
50
40
30
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
20
10
-4.0 -3.0 -2.0 2.0 3.0 4.0 5.0 6.0
25°C
-55°C
125°C
0-1.0 1.00
Figure 11. On Resistance Test Set−Up
PLOTTER
MINI COMPUTER
PROGRAMMABLE
POWER
SUPPLY
DC ANALYZER
VCC
DEVICE
UNDER TEST
+-
VEE
ANALOG IN COMMON OUT
GND
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Figure 12. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
Figure 13. Maximum Off Channel Leakage Current,
Common Channel, Test Set−Up
Figure 14. Maximum On Channel Leakage Current,
Channel to Channel, Test Set−Up
Figure 15. Maximum On Channel Bandwidth,
Test Set−Up
Figure 16. Off Channel Feedthrough Isolation,
Test Set−Up
Figure 17. Feedthrough Noise, Channel Select to
Common Out, Test Set−Up
OFF
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIH
NC
A
VCC
VEE
VCC
OFF
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIH
ANALOG I/O
VCC
VEE
VCC
ON
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIL
VCC
VEE
VCC
N/C
A
ANALOG I/O
ON
6
7
8
16
VCC
VEE
0.1μF
CL*
fin
RL
dB
METER
*Includes all probe and jig capacitance
OFF
6
7
8
16
VCC
VEE
0.1μF
CL*
fin
RL
dB
METER
*Includes all probe and jig capacitance
VOS
VOS
RL
VIS
VIL or VIH
CHANNEL SELECT
ON/OFF
6
7
8
16
VCC
VEE
CL*
RL
*Includes all probe and jig capacitance
CHANNEL SELECT
TEST
POIN
T
COMMON O/I
11
VCC
OFF/ON
ANALOG I/O
RL
RL
VCC
GND
Vin ≤1 MHz
tr = tf = 6 ns
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Figure 18. Propagation Delays, Channel Select
to Analog Out
Figure 19. Propagation Delay, Test Set−Up Channel
Select to Analog Out
Figure 20. Propagation Delays, Analog In
to Analog Out
Figure 21. Propagation Delay, Test Set−Up
Analog In to Analog Out
Figure 22. Propagation Delays, Enable to
Analog Out
Figure 23. Propagation Delay, Test Set−Up
Enable to Analog Out
VCC
GND
CHANNEL
SELECT
ANALOG
OUT 50%
tPLH tPHL
50% ON/OFF
6
7
8
16
VCC
CL*
*Includes all probe and jig capacitance
CHANNEL SELECT
TEST
POINT
COMMON O/I
OFF/ON
ANALOG I/O
VCC
VCC
GND
ANALOG
IN
ANALOG
OUT 50%
tPLH tPHL
50%
ON
6
7
8
16
VCC
CL*
*Includes all probe and jig capacitance
TEST
POINT
COMMON O/I
ANALOG I/O
ON/OFF
6
7
8
ENABLE
VCC
ENABLE 90%
50%
10%
tftr
VCC
GND
ANALOG
OUT
tPZL
ANALOG
OUT
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
ANALOG I/O
CL*
TEST
POINT
16
VCC
1kΩ
1
2
1
2
POSITION 1 WHEN TESTING tPHZ AND tPZH
POSITION 2 WHEN TESTING tPLZ AND tPZL
MC74VHC4051, MC74VHC4052, MC74VHC4053
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11
RL
Figure 24. Crosstalk Between Any Two
Switches, Test Set−Up
Figure 25. Power Dissipation Capacitance,
Test Set−Up
Figure 26. Total Harmonic Distortion, Test Set−Up Figure 27. Plot, Harmonic Distortion
0
-10
-20
-30
-40
-50
- 100 1.0 2.0 3.125
FREQUENCY (kHz)
dB
-60
-70
-80
-90
FUNDAMENTAL FREQUENCY
DEVICE
SOURCE
ON
6
7
8
16
VEE CL*
*Includes all probe and jig capacitance
OFF
RL
RL
VIS
RLCL*
VOS
fin
0.1μF
ON/OFF
6
7
8
16
VCC
CHANNEL SELECT
NC
COMMON O/I
OFF/ON
ANALOG I/O
VCC
A
11
VCC
VEE
ON
6
7
8
16
VCC
VEE
0.1μF
CL*
fin
RL
TO
DISTORTION
METER
*Includes all probe and jig capacitance
VOS
VIS
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
VCC or GND logic levels. VCC being recognized as a logic
high and GND being recognized as a logic low. In this
example:
VCC = +5V = logic high
GND = 0V = logic low
The maximum analog voltage swings are determined by
the supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In this example,
the difference between VCC and VEE is ten volts. Therefore,
using the configuration of Figure 28, a maximum analog
signal of ten volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
VCC − GND = 2 to 6 volts
VEE − GND = 0 to −6 volts
VCC − VEE = 2 to 12 volts
and VEE ≤ GND
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in Figure
29. These diodes should be able to absorb the maximum
anticipated current surges during clipping.
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ANALOG
SIGNAL
Figure 28. Application Example Figure 29. External Germanium or
Schottky Clipping Diodes
a. Using Pull−Up Resistors b. Using HCT Interface
Figure 30. Interfacing LSTTL/NMOS to CMOS Inputs
ON
6
7
8
16
+5V
-5V
ANALOG
SIGNAL
+5V
-5V
+5V
-5V
11
10
9
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
ON/OFF
7
8
16
VCC
VEE
VEE
Dx
VCC
Dx
VEE
Dx
VCC
Dx
ANALOG
SIGNAL
ON/OFF
6
7
8
16
+5V
VEE
ANALOG
SIGNAL
+5V
VEE
+5V
VEE
11
10
9
R
*
R R
LSTTL/NMOS
CIRCUITRY
+5V
* 2K ≤ R ≤ 10K
ANALOG
SIGNAL
ON/OFF
6
7
8
16
+5V
VEE
ANALOG
SIGNAL
+5V
VEE
+5V
VEE
11
10
9
LSTTL/NMOS
CIRCUITRY
+5V
HCT
BUFFER
Figure 31. Function Diagram, VHC4051
13 X0
14 X1
15 X2
12 X3
1X4
5X5
2X6
4X7
3X
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
11
A
10
B
9
C
6
ENABLE
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Figure 32. Function Diagram, VHC4053
Figure 33. Function Diagram, VHC4052
13 X1
12 X0
1Y1
2Y0
3Z1
5Z0
14 X
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
11
A
10
B
9
C
6
ENABLE
12 X0
14 X1
15 X2
11 X3
1Y0
5Y1
2Y2
4Y3
3Y
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
10
A
9
B
6
ENABLE
13 X
15 Y
4Z
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ORDERING & SHIPPING INFORMATION
Device Package Shipping
MC74VHC4051DR2G SOIC−16 2500 Units / Tape & Reel
MC74VHC4051DTR2G TSSOP−16 2500 Units / Tape & Reel
MC74VHC4052DR2G SOIC−16 2500 Units / Tape & Reel
MC74VHC4052DTR2G TSSOP−16 2500 Units / Tape & Reel
MC74VHC4053DR2G SOIC−16 2500 Units / Tape & Reel
MC74VHC4053DTR2G TSSOP−16 2500 Units / Tape & Reel
MC74VHC4051MG SOEIAJ−16 50 Units / Rail
MC74VHC4052MG SOEIAJ−16 50 Units / Rail
MC74VHC4052MELG SOEIAJ−16 2000 Units / Reel
MC74VHC4053MG SOEIAJ−16 50 Units / Rail
MC74VHC4051, MC74VHC4052, MC74VHC4053
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15
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
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PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
MC74VHC4051, MC74VHC4052, MC74VHC4053
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17
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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