Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
Rev. C
12/11/06
IS41LV16100B ISSI®
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
—
Auto refresh Mode: 1,024 cycles /16 ms
—
RAS-Only, CAS-before-RAS (CBR), and Hidden
— Self refresh Mode: 1,024 cycles /128 ms
• JEDEC standard pinout
• Single power supply: 3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
• Industrial Temperature Range: -40oC to +85oC
• Lead-free available
DESCRIPTION
The ISSI IS41LV16100B is 1,048,576 x 16-bit high-perfor-
mance CMOS Dynamic Random Access Memories. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 1,024 random ac-
cesses within a single row with access cycle time as short
as 20 ns per 16-bit word.
These features make the IS41LV16100B ideally suited for
high-bandwidth graphics, digital signal processing, high-
performance computing systems, and peripheral
applications.
The IS41LV16100B is packaged in a 42-pin 400-mil SOJ
and 400-mil 50- (44-) pin TSOP (Type II).
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
KEY TIMING PARAMETERS
Parameter -50 -60 Unit
Max. RAS Access Time (tRAC) 5060ns
Max. CAS Access Time (tCAC) 1415ns
Max. Column Address Access Time (tAA)2530ns
Min. EDO Page Mode Cycle Time (tPC)3040ns
Min. Read/Write Cycle Time (tRC) 85 110 ns
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II) 42-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9 Address Inputs
I/O0-15 Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
VDD Power
GND Ground
NC No Connection
DECEMBER 2006
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
IS41LV16100B
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Rev. C
12/11/06
ISSI
®
FUNCTIONAL BLOCK DIAGRAM
O
E
WE
L
CAS
UCAS CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
1,048,576 x 16
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O15
RAS
RAS
A0-A9
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
IS41LV16100B
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ISSI
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TRUTH TABLE
Function RASRAS
RASRAS
RAS LCASLCAS
LCASLCAS
LCAS UCASUCAS
UCASUCAS
UCAS WEWE
WEWE
WE OEOE
OEOE
OE Address t
R
/t
C
I/O
Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL D
OUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, D
OUT
Upper Byte, High-Z
Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z
Upper Byte, D
OUT
Write: Word (Early Write) L L L L X ROW/COL D
IN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, D
IN
Upper Byte, High-Z
Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z
Upper Byte, D
IN
Read-Write
(1,2)
LLLH→LL→H ROW/COL D
OUT
, D
IN
EDO Page-Mode Read
(2)
1st Cycle: L H→LH→L H L ROW/COL D
OUT
2nd Cycle: L H→LH→L H L NA/COL D
OUT
Any Cycle: L L→HL→H H L NA/NA D
OUT
EDO Page-Mode Write
(1)
1st Cycle: L H→LH→L L X ROW/COL D
IN
2nd Cycle: L H→LH→L L X NA/COL D
IN
EDO Page-Mode
(1,2)
1st Cycle: L H→LH→LH→LL→H ROW/COL D
OUT
, D
IN
Read-Write 2nd Cycle: L H→LH→LH→LL→H NA/COL D
OUT
, D
IN
Hidden Refresh Read
(2)
L→H→L L L H L ROW/COL D
OUT
Write
(1,3)
L→H→L L L L X ROW/COL D
OUT
RAS-Only Refresh L H H X X ROW/NA High-Z
CBR Refresh
(4)
H→L L L X X X High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
IS41LV16100B
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®
Functional Description
The IS41LV16100B is a CMOS DRAM optimized for
high-
speed
bandwidth,
low power applications. During READ or
WRITE cycles, each bit is uniquely addressed through the
16 address bits. These are entered ten bits (A0-A9) at time.
The row address is latched by the Row Address Strobe
(RAS). The column address is latched by the Column
Address Strobe (CAS).
RAS is used to latch the first nine bits
and CAS is used to latch the latter nine bits.
The IS41LV16100B has two CAS controls, LCAS and UCAS.
The LCAS and UCAS inputs internally generates a CAS signal
functioning in an identical manner to the single CAS input on
the other 1M x 16 DRAMs.
The key difference is that each CAS
controls its corresponding I/O tristate logic (
in conjunction with
OE and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IS41LV16100B CAS function is determined by the first
CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41LV16100B both BYTE READ and BYTE WRITE cycle
capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by tAR.
Data Out becomes valid only when tRAC, tAA, tCAC and tOEA
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs first.
Auto Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0 through A9)
with RAS at least once every 128 ms. Any read, write, read-
modify-write or RAS-only cycle refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms. i.e.,
125 µs per row when using distributed CBR refreshes. The
feature also allows the user the choice of a fully static, low
power data retention mode. The optional Self Refresh feature
is initiated by performing a CBR Refresh cycle and holding
RAS LOW for the specified tRAS.
The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of tRP. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence, a
burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or burst
refresh sequence, all 1,024 rows must be refreshed within the
average internal refresh rate, prior to the resumption of
normal operation.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns within
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is equiva-
lent to that of the fast page mode in that case.
Power-On
After application of the VDD supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a RAS signal).
During power-on, it is recommended that RAS track with
VDD or be held at a valid VIH to avoid current surges.
IS41LV16100B
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Rev. C
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ISSI
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
VTVoltage on Any Pin Relative to GND 3.3V –0.5 to +4.6 V
VDD Supply Voltage 3.3V –0.5 to +4.6 V
IOUT Output Current 50 mA
PDPower Dissipation 1 W
TACommercial Operation Temperature 0 to +70 °C
Industrial Operation Temperature -40 to +85 °C
TSTG Storage Temperature –55 to +125 °C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Min. Typ. Max. Unit
VDD Supply Voltage 3.3V 3.0 3.3 3.6 V
VIH Input High Voltage 3.3V 2.0 — VDD + 0.3 V
VIL Input Low Voltage 3.3V –0.3 — 0.8 V
TACommercial Ambient Temperature 0 — 70 °C
Industrial Ambient Temperature –40 — 85 °C
CAPACITANCE(1,2)
Symbol Parameter Max. Unit
CIN1Input Capacitance: A0-A9 5 pF
CIN2Input Capacitance: RAS, UCAS, LCAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
IS41LV16100B
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ISSI
®
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
IIL Input Leakage Current Any input 0V ≤ VIN ≤ VDD –10 10 µA
Other inputs not under test = 0V
IIO Output Leakage Current Output is disabled (Hi-Z) –10 10 µA
0V ≤ VOUT ≤ VDD
VOH Output High Voltage Level IOH = –2.0 mA (3.3V) 2.4 — V
VOL Output Low Voltage Level IOL = 2.0 mA (3.3V) — 0.4 V
ICC1Standby Current: TTL RAS, LCAS, UCAS ≥ VIH Commercial 3.3V — 3 mA
Industrial 3.3V — 4 mA
ICC2Standby Current: CMOS RAS, LCAS, UCAS ≥ VDD – 0.2V 3.3V — 2 mA
ICC3Operating Current: RAS, LCAS, UCAS, -50 — 180 mA
Random Read/Write(2,3,4) Address Cycling, tRC = tRC (min.) -60 — 170
Average Power Supply Current
ICC4Operating Current: RAS = VIL, LCAS, UCAS, -50 — 180 mA
EDO Page Mode(2,3,4) Cycling tPC = tPC (min.) -60 — 170
Average Power Supply Current
ICC5Refresh Current: RAS Cycling, LCAS, UCAS ≥ VIH -50 — 180 mA
RAS-Only(2,3) tRC = tRC (min.) -60 — 170
Average Power Supply Current
ICC6Refresh Current: RAS, LCAS, UCAS Cycling -50 — 180 mA
CBR(2,3,5) tRC = tRC (min.) -60 — 170
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
IS41LV16100B
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AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tRC Random READ or WRITE Cycle Time 85 — 110 — ns
tRAC Access Time from RAS(6, 7) —50 —60 ns
tCAC Access Time from CAS(6, 8, 15) —14 —15 ns
tAA Access Time from Column-Address(6) —25 —30 ns
tRAS RAS Pulse Width 50 10K 60 10K ns
tRP RAS Precharge Time 30 — 40 — ns
tCAS CAS Pulse Width(26) 8 10K 10 10K ns
tCP CAS Precharge Time(9, 25) 9— 10— ns
tCSH CAS Hold Time (21) 50 — 60 — ns
tRCD RAS to CAS Delay Time(10, 20) 12 37 20 45 ns
tASR Row-Address Setup Time 0 — 0 — ns
tRAH Row-Address Hold Time 8 — 10 — ns
tASC Column-Address Setup Time(20) 0— 0— ns
tCAH Column-Address Hold Time(20) 8— 10— ns
tAR Column-Address Hold Time 30 — 40 — ns
(referenced to RAS)
tRAD RAS to Column-Address Delay Time(11) 14 25 15 30 ns
tRAL Column-Address to RAS Lead Time 25 — 30 — ns
tRPC RAS to CAS Precharge Time 5 — 5 — ns
tRSH RAS Hold Time(27) 14 — 15 — ns
tCLZ CAS to Output in Low-Z(15, 29) 0— 0— ns
tCRP CAS to RAS Precharge Time(21) 5— 5— ns
tOD Output Disable Time(19, 28, 29) 312 312 ns
tOE/tOEA Output Enable Time(15, 16) —14 —15 ns
tOEHC OE HIGH Hold Time from CAS HIGH 15 — 15 — ns
tOEP OE HIGH Pulse Width 10 — 10 — ns
tOES OE LOW to CAS HIGH Setup Time 5 — 5 — ns
tRCS Read Command Setup Time(17, 20) 0— 0— ns
tRRH Read Command Hold Time 0 — 0 — ns
(referenced to RAS)(12)
tRCH Read Command Hold Time 0 — 0 — ns
(referenced to CAS)(12, 17, 21)
tWCH Write Command Hold Time(17, 27) 8— 10— ns
tWCR Write Command Hold Time 40 — 50 — ns
(referenced to RAS)(17)
IS41LV16100B
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AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tWP Write Command Pulse Width(17) 8— 10— ns
tWPZ WE Pulse Widths to Disable Outputs 10 — 10 — ns
tRWL Write Command to RAS Lead Time(17) 13 — 15 — ns
tCWL Write Command to CAS Lead Time(17, 21) 8— 15— ns
tWCS Write Command Setup Time(14, 17, 20) 0— 0— ns
tDHR Data-in Hold Time (referenced to RAS)39—40—ns
tOEH OE Hold Time from WE during 14 — 15 — ns
READ-MODIFY-WRITE cycle(18)
tDS Data-In Setup Time(15, 22) 0— 0— ns
tDH Data-In Hold Time(15, 22) 8— 15— ns
tRWC READ-MODIFY-WRITE Cycle Time 110 — 155 — ns
tRWD RAS to WE Delay Time during 65 — 85 — ns
READ-MODIFY-WRITE Cycle(14)
tCWD CAS to WE Delay Time(14, 20) 26 — 40 — ns
tAWD Column-Address to WE Delay Time(14) 40 — 55 — ns
tPC EDO Page Mode READ or WRITE 30 — 40 — ns
Cycle Time(24)
tRASP RAS Pulse Width in EDO Page Mode 50 100K 60 100K ns
tCPA Access Time from CAS Precharge(15) —30 —35 ns
tPRWC EDO Page Mode READ-WRITE 56 — 56 — ns
Cycle Time(24)
tCOH Data Output Hold after CAS LOW 5— 5— ns
tOFF Output Buffer Turn-Off Delay from 3 12 3 15 ns
CAS or RAS(13,15,19, 29)
tWHZ Output Disable Delay from WE 310 315 ns
tCLCH Last CAS going LOW to First CAS 10 — 10 — ns
returning HIGH(23)
tCSR CAS Setup Time (CBR REFRESH)(30, 20) 5— 5— ns
tCHR CAS Hold Time (CBR REFRESH)(30, 21) 8— 10— ns
tORD OE Setup Time prior to RAS during 0 — 0 — ns
HIDDEN REFRESH Cycle
tREF Auto Refresh Period (1,024 Cycles) — 16 — 16 ms
tREF Self Refresh Period (1,024 Cycles) — 128 — 128 ms
tTTransition Time (Rise or Fall)(2, 3) 350 350 ns
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Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a
monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≤ tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data
output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is
greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is
greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≤ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≤ tRWD
(MIN), tAWD ≤ tAWD (MIN) and tCWD ≤ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and
OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
AC TEST CONDITIONS
Output load: One TTL Load and 50 pF (VDD = 3.3V ±10%)
Input timing reference levels: VIH = 2.0V, VIL = 0.8V (VDD = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V
IS41LV16100B
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ISSI
®
READ CYCLE
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
tRAS
tRC
tRP
tAR
tCAH
tASC
tRAD tRAL
OE
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
Open Open
Valid Data
tCSH
tCAS
tRSH
tCRP tCLCH
tRCD
tRAHtASR
tRRH
tRCHtRCS
tAA
tCAC tOFF(1)
tRAC
tCLC
tOES
tOE tOD
Don’t Care
Undefined
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ISSI
®
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
CWL
t
WCR
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
t
DHR
Valid Data
Don’t Care
IS41LV16100B
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ISSI
®
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRAS
tRWC
tRP
tAR
tCAH
tASC
tRAD tRAL
tACH
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
tCSH
tCAS
tRSH
tCRP tCLCH
tRCD
tRAHtASR
tRWD tCWL
tCWD tRWL
tAWD tWP
tRCS
tCAC
tCLZ tDS tDH
tOEHtOD
tOE
tRAC
tAA
I/O Open Open
Valid D
OUT
Valid D
IN
Don’t Care
Undefined
IS41LV16100B
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
13
Rev. C
12/11/06
ISSI
®
EDO-PAGE-MODE READ CYCLE
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
tRASP tRP
ADDRESS
UCAS/LCAS
RAS
Row Row
tCAS,
tCLCH
tCRP tRCD
tCSH
tCP tCAS,
tCLCH
tCAH
tCAS,
tCLCH
tRAL
tRSH
tCPtCP
tPC(1)
tASR
tRAH
tRAD
tAR
Column Column
tCAHtCAH
Column
tASCtASC
OE
I/O
WE
Open Ope
n
Valid Data
tAA tAA
tCPA
tCAC tCAC
tRAC
tCOHtCLZ
tOEP
tOE
tOES tOES tOD
tOEtOEHC
Valid Data
tRCH
tRRH
tAA
tCPA
tCAC
tOFFtCLZ
Valid Data
tOD
tASC
tRCS
Don’t Care
Undefined
IS41LV16100B
14
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
12/11/06
ISSI
®
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP tRP
ADDRESS
UCAS/LCAS
RAS
Row Row
tCAS,
tCLCH
tCRP tRCD
tCSH
tCP tCAS,
tCLCH
tCAH
tCAS,
tCLCH
tRAL
tRSH
tCPtCP
tPC
tASR
tRAH
tRAD
tAR tACH
Column Column
tACHtACH
tCAHtCAH
Column
tASCtASC
OE
I/O
WE
Valid Data
tASC
tWCS
tWCH
tCWL
tWP
tRHCP
tWCS
tWCH
tCWL
tWP
tDS
tDH
tDHR
tWCR
tWCS
tWCH
tCWL
tWP
Valid Data
tDS
tDH
Valid Data
tDS
tRWL
tDH
Don’t Care
IS41LV16100B
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
15
Rev. C
12/11/06
ISSI
®
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Don’t Care
Undefined
t
RASP
t
RP
ADDRESS
UCAS/LCAS
RAS
Row Row
t
CRP
t
RCD
t
CSH
t
CP
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
RAH
t
RAD
t
AR
t
ASR
Column Column
t
CAH
t
CAH
Column
t
ASC
t
ASC
t
CAS,
t
CLCH
t
CAS,
t
CLCH
OE
I/O
WE
t
ASC
t
RWD
t
RCS
t
CWL
t
WP
t
AWD
t
CWD
t
DH
t
DS
t
CAC
t
CLZ
t
AWD
t
CWD
t
CWL
t
WP
t
AWD
t
CWD
t
CWL
t
RWL
t
WP
Open Open
D
IN
D
OUT
t
OE
t
OE
t
OE
t
OD
t
OEH
t
OD
t
OD
t
DH
t
DS
t
CPA
t
AA
t
CAC
t
CLZ
D
IN
D
OUT
t
DH
t
DS
t
CAC
t
CLZ
D
IN
D
OUT
t
CPA
t
AA
t
RAC
t
AA
t
PC
/ t
PRWC
(1)
IS41LV16100B
16
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
12/11/06
ISSI
®
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY WRITE)
tRASP tRP
ADDRESS
UCAS/LCAS
RAS
Row Row
tCRP tRCD
tPC
tCSH
tCP
tCAH
tCAS
tRAL
tRSH
tCPtCP
tACH
tRAH
tRAD
tAR
tASR
Column (A) Column (N)
tCAHtCAH
Column (B)
tASCtASC
tCAS tCAS
OE
I/O
WE
tASC
tCAC
tRCH
tDH
Open Open
Valid Data (A)
tOE
tWCS
tCAC
tCOH
DIN
tCPA
tWCH
tRAC
tAA
tPC
Valid Data (B)
tWHZ
tDS
tRCS
tAA
Don’t Care
IS41LV16100B
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
17
Rev. C
12/11/06
ISSI
®
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RASRAS
RASRAS
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tAR
tCAH tASC
tASC
tRAD
OE
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column
Open Open
Valid Data
tCSH
tCAS
tCRP tRCD tCP
tRAHtASR
tRCH tRCStRCS
tAA
tCAC
tWHZ
tRAC
tCLZ
tCLZ
tOE tOD
Column
t
RAS
t
RC
t
RP
I/O
ADDRESS
UCAS/LCAS
RAS
Row Row
Open
t
CRP
t
RAH
t
ASR
t
RPC
Don’t Care
Undefined
Don’t Care
IS41LV16100B
18
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
12/11/06
ISSI
®
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
CBRCBR
CBRCBR
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
tRAS tRAStRP tRP
I/O
UCAS/LCAS
RAS
Open
tCP
tRPC
tCSR
tCHR tRPC
tCSR
tCHR
t
RAS
t
RAS
t
RP
UCAS/LCAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
AR
t
ASC
t
RAD
ADDRESS Row Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O Open Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Don’t Care
Undefined
IS41LV16100B
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1-800-379-4774
19
Rev. C
12/11/06
ISSI
®
ORDERING INFORMATION : 3.3V
Commercial Range: 0°°
°°
°C to +70°°
°°
°C
Speed (ns) Order Part No. Package
50 IS41LV16100B-50K 400-mil SOJ
IS41LV16100B-50KL 400-mil SOJ, Lead-free
IS41LV16100B-50T 400-mil TSOP (Type II)
IS41LV16100B-50TL 400-mil TSOP (Type II), Lead-free
60 IS41LV16100B-60K 400-mil SOJ
IS41LV16100B-60KL 400-mil SOJ, Lead-free
IS41LV16100B-60T 400-mil TSOP (Type II)
IS41LV16100B-60TL 400-mil TSOP (Type II), Lead-free
Industrial Range: -40°°
°°
°C to +85°°
°°
°C
Speed (ns) Order Part No. Package
50 IS41LV16100B-50KI 400-mil SOJ
IS41LV16100B-50KLI 400-mil SOJ, Lead-free
IS41LV16100B-50TI 400-mil TSOP (Type II)
IS41LV16100B-50TLI 400-mil TSOP (Type II), Lead-free
60 IS41LV16100B-60KI 400-mil SOJ
IS41LV16100B-60KLI 400-mil SOJ, Lead-free
IS41LV16100B-60TI 400-mil TSOP (Type II)
IS41LV16100B-60TLI 400-mil TSOP (Type II), Lead-free
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
10/29/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
400-mil Plastic SOJ
Package Code: K
Notes:
1. Controlling dimension:
millimeters.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
SEATING PLANE
1
N
E1
D
E2
E
B
eA1
A
C
A2
b
N/2+1
N/2
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
No. Leads (N) 28 32 36
A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148
A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 —
A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 —
B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020
b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032
C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013
D 18.29 18.54 0.720 0.730 20.82 21.08 0.820 0.830 23.37 23.62 0.920 0.930
E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445
E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC
e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC
PA CKA GING INFORMATION ISSI
®
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
10/29/03
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
No. Leads (N) 40 42 44
A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148
A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 —
A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 —
B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020
b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032
C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013
D 25.91 26.16 1.020 1.030 27.18 27.43 1.070 1.080 28.45 28.70 1.120 1.130
E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445
E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC
e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC
Integrated Silicon Solution, Inc.
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
Plastic TSOP (T - Type II) (MS 25)
Millimeters Inches
Symbol Min Max Min Max
Ref. Std.
N24/26
A 1.20 0.0472
A1 0.05 0.15 0.002 0.0059
b 0.30 0.51 0.012 0.0201
c 0.12 0.21 0.005 0.0083
D 17.01 17.27 0.670 0.6899
E17.49 7.75 0.295 0.3051
e1.27 BSC 0.050 BSC
E 9.02 9.42 0.462 0.4701
L 0.40 0.60 0.016 0.0236
α0°5°0°5°
PK13197T40 Rev. C 08/013/99
Plastic TSOP (T - Type II) (MS 24)
Millimeters Inches
Symbol Min Max Min Max
Ref. Std.
N40/44
A 1.20 0.0472
A1 0.05 0.15 0.002 0.0059
b 0.30 0.45 0.012 0.0157
c 0.12 0.21 0.005 0.0083
D 18.31 18.51 0.721 0.7287
E110.06 10.26 0.396 0.4040
e0.80 BSC 0.031 BSC
E 11.56 11.96 0.455 0.4709
L 0.40 0.60 0.016 0.0236
α0°8°0°8°
Plastic TSOP (T - Type II) (MS 24)
Millimeters Inches
Symbol Min Max Min Max
Ref. Std.
N44/50
A 1.20 0.0472
A1 0.05 0.15 0.002 0.0059
b 0.30 0.45 0.012 0.0157
c 0.12 0.21 0.005 0.0083
D 20.85 21.05 0.821 0.8287
E110.06 10.26 0.396 0.4040
e0.80 BSC 0.031 BSC
E 11.56 11.96 0.455 0.4709
L 0.40 0.60 0.016 0.0236
α0°8°0°8°
ISSI
®
Notes:
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protru-
sions and
should be measured from the bottom of the
package
.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
D
SEATING PLANE
b
ec
1N/2
N/2+1N
E1
A1
A
E
Lα
