HD64F3068F25V - RENESAS TECHNOLOGY

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April 1st, 2010

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H8/3068F-ZTATTM

Hardware Manual

User’s Manual

Rev.3.00 2005.09

Renesas 16-Bit Single-Chip

Microcomputer

H8 Family/H8/300H Series

H8/3068F HD64F3068F,

HD64F3068TE

The revision list can be viewed directly by

clicking the title page.

The revision list summarizes the locations of

revisions and additions. Details should always

be checked by referring to the relevant text.

Rev. 3.00 Sep 14, 2005 page ii of xxii

1. These materials are intended as a reference to assist our customers in the selection of the Renesas

Technology Corp. product best suited to the customer's application; they do not convey any license

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a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-

party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or

circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and

algorithms represents information on products at the time of publication of these materials, and are

subject to change by Renesas Technology Corp. without notice due to product improvements or

other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or

an authorized Renesas Technology Corp. product distributor for the latest product information

before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising

from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means,

including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,

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8. Please contact Renesas Technology Corp. for further details on these materials or the products

contained therein.

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and

more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate

measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or

(iii) prevention against any malfunction or mishap.

Keep safety first in your circuit designs!

Notes regarding these materials

Rev. 3.00 Sep 14, 2005 page iii of xxii

Preface

The H8/3068F is a group of high-performance single-chip microcontrollers that integrate system

supporting functions together with an H8/300H CPU core.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a

concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address

space.

The on-chip supporting functions include ROM, RAM, 16-bit timers, 8-bit timers, a

programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication

interface (SCI), an A/D converter, a D/A converter, I/O ports, a DMA controller (DMAC), and

other facilities. The three-channel SCI has been expanded to support the ISO/IEC7816-3 smart

card interface. Functions have also been added to reduce power consumption in battery-powered

applications: individual modules can be placed in standby, and the frequency of the system clock

supplied to the chip can be divided down under software control.

The address space is divided into eight areas. The data bus width and access cycle length can be

selected independently in each area, simplifying the connection of different types of memory.

Seven MCU operating modes (modes 1 to 7) are provided, offering a choice of data bus width and

address space size.

With these features, the H8/3068F offers easy implementation of compact, high-performance

systems.

The H8/3068F has an F-ZTAT™* version with on-chip flash memory that can be programmed

on-board. This version enables users to respond quickly and flexibly to changing application

specifications.

This manual describes the H8/3068F hardware. For details of the instruction set, refer to the

H8/300H Series Programming Manual.

Note: * F-ZTAT™ (Flexible ZTAT) is a registered trademark of Renesas Technology Corp.

Rev. 3.00 Sep 14, 2005 page iv of xxii

Rev. 3.00 Sep 14, 2005 page v of xxii

Main Revisions for this Edition

Item Page Revision (See Manual for Details)

All All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and

other Hitachi brand names changed to Renesas Technology Corp.

Designation for categories changed from “series” to “group”

19.2.1 Connecting

a Crystal Resonator

Table 19.1 (1)

Damping Resistance

Value

651 Note amended

Note: A crystal resonator between 2 MHz and 25 MHz can be

used. If the chip is to be operated at less than 2 MHz, the

on-chip frequency divider should be used. (A crystal

resonator of less than 2 MHz cannot be used.)

Section 21

Electrical

Characteristics

675 to

706 “Preliminary” deleted

21.1.2 DC

Characteristics

Table 21.2 DC

Characteristics (1)

677, 678 Table and note amended

Item Symbol Min Typ Max Unit Test

Conditions

Current

dissipation*

Normal

operation I

—32

(5.0 V) 47 mA f = 20 MHz

(5.0 V) 58 f = 25 MHz

Sleep mode —24

(5.0 V) 38 mA f = 20 MHz

(5.0 V) 47 f = 25 MHz

Module

standby mode —19

(5.0 V) 31 mA f = 20 MHz

(5.0 V) 37 f = 25 MHz

—1.0 10 µA T

50˚CStandby

mode*

— — 80 µA 50˚C T

Flash memory

programming/

erasing*

— 37 57 mA f = 20 MHz

42 68 f = 25 MHz

Notes: 3. The values are for VRAM ≤ VCC < 4.5 V, VIH min = VCC ×

0.9, and VIL max = 0.3 V.

4. ICC max. (normal operation)

= 3.0 (mA) + 0.40 (mA/(MHz × V)) × VCC × f

ICC max. (sleep mode)

= 3.0 (mA) + 0.32 (mA/(MHz × V)) × VCC × f

ICC max. (sleep mode + module standby mode)

= 3.0 (mA) + 0.25 (mA/(MHz × V)) × VCC × f

The Typ values for power consumption are reference

values.

5. Sum of current dissipation in normal operation and

current dissipation in program/erase operations.

Rev. 3.00 Sep 14, 2005 page vi of xxii

Item Page Revision (See Manual for Details)

21.1.6 Flash

Memory

Characteristics

Table 21.10 Flash

Memory

Characteristics

690, 691 Table amended and notes added

Item Symbol Min Typ Max Unit Notes

Programming time*

— 10 200 ms/

128 bytes

Erase time*

— 100 1200 ms/block

Reprogramming count N

WEC

100*

10,000*

— Times

Data retention period t

DRP

10*

— — Years

Notes: 6. Minimum number of times at which all characteristics are

guaranteed after reprogramming. (Reprogramming count

from 1 to minimum value is guaranteed.)

7. Reference characteristics at 25°C. (This is an indication

that reprogramming operations can normally be

performed up to this figure.)

8. Data retention characteristics when reprogramming is

performed correctly within the specification values,

including the minimum data retention period.

Rev. 3.00 Sep 14, 2005 page vii of xxii

Contents

Se ctio n 1 Ove r v iew............................................................................................................. 1

1.1 Overview........................................................................................................................... 1

1.2 Block Diagram.................................................................................................................. 6

1.3 Pin Description ................................................................................................................. 7

1.3.1 Pin Arrangement.................................................................................................. 7

1.3.2 Pin Functions ....................................................................................................... 8

1.3.3 Pin Assignments in Each Mode........................................................................... 13

Se ctio n 2 CPU...................................................................................................................... 19

2.1 Overview........................................................................................................................... 19

2.1.1 Features................................................................................................................ 19

2.1.2 Differences from H8/300 CPU ............................................................................ 20

2.2 CPU Operating Modes...................................................................................................... 21

2.3 Address Space................................................................................................................... 22

2.4 Register Configuration...................................................................................................... 23

2.4.1 Overview.............................................................................................................. 23

2.4.2 General Registers................................................................................................. 24

2.4.3 Control Registers................................................................................................. 25

2.4.4 Initial CPU Register Values................................................................................. 26

2.5 Data Formats..................................................................................................................... 27

2.5.1 General Register Data Formats............................................................................ 27

2.5.2 Memory Data Formats......................................................................................... 29

2.6 Instruction Set................................................................................................................... 30

2.6.1 Instruction Set Overview ..................................................................................... 30

2.6.2 Instructions and Addressing Modes..................................................................... 31

2.6.3 Tables of Instructions Classified by Function...................................................... 32

2.6.4 Basic Instruction Formats.................................................................................... 41

2.6.5 Notes on Use of Bit Manipulation Instructions ................................................... 42

2.7 Addressing Modes and Effective Address Calculation..................................................... 44

2.7.1 Addressing Modes ............................................................................................... 44

2.7.2 Effective Address Calculation ............................................................................. 46

2.8 Processing States............................................................................................................... 50

2.8.1 Overview.............................................................................................................. 50

2.8.2 Program Execution State ..................................................................................... 51

2.8.3 Exception-Handling State.................................................................................... 51

2.8.4 Exception-Handling Sequences ........................................................................... 53

2.8.5 Bus-Released State .............................................................................................. 54

Rev. 3.00 Sep 14, 2005 page viii of xxii

2.8.6 Reset State ........................................................................................................... 54

2.8.7 Power-Down State............................................................................................... 55

2.9 Basic Operational Timing................................................................................................. 56

2.9.1 Overview.............................................................................................................. 56

2.9.2 On-Chip Memory Access Timing........................................................................ 56

2.9.3 On-Chip Supporting Module Access Timing ...................................................... 57

2.9.4 Access to External Address Space....................................................................... 58

Se ctio n 3 MCU Ope r ating Mode s.................................................................................. 59

3.1 Overview........................................................................................................................... 59

3.1.1 Operating Mode Selection................................................................................... 59

3.1.2 Register Configuration......................................................................................... 60

3.2 Mode Control Register (MDCR)...................................................................................... 61

3.3 System Control Register (SYSCR)................................................................................... 62

3.4 Operating Mode Descriptions........................................................................................... 64

3.4.1 Mode 1................................................................................................................. 64

3.4.2 Mode 2................................................................................................................. 64

3.4.3 Mode 3................................................................................................................. 64

3.4.4 Mode 4................................................................................................................. 65

3.4.5 Mode 5................................................................................................................. 65

3.4.6 Mode 6................................................................................................................. 65

3.4.7 Mode 7................................................................................................................. 65

3.5 Pin Functions in Each Operating Mode............................................................................ 66

3.6 Memory Map in Each Operating Mode............................................................................ 67

3.6.1 Note on Reserved Areas ...................................................................................... 67

Section 4 Exception Handling......................................................................................... 73

4.1 Overview........................................................................................................................... 73

4.1.1 Exception Handling Types and Priority............................................................... 73

4.1.2 Exception Handling Operation ............................................................................ 73

4.1.3 Exception Vector Table....................................................................................... 74

4.2 Reset ................................................................................................................................. 76

4.2.1 Overview.............................................................................................................. 76

4.2.2 Reset Sequence.................................................................................................... 76

4.2.3 Interrupts after Reset............................................................................................ 79

4.3 Interrupts........................................................................................................................... 80

4.4 Trap Instruction ................................................................................................................ 81

4.5 Stack Status after Exception Handling.............................................................................. 82

4.6 Notes on Stack Usage....................................................................................................... 83

Rev. 3.00 Sep 14, 2005 page ix of xxii

Se ctio n 5 I nterrupt Control ler.......................................................................................... 85

5.1 Overview........................................................................................................................... 85

5.1.1 Features................................................................................................................ 85

5.1.2 Block Diagram..................................................................................................... 86

5.1.3 Pin Configuration................................................................................................. 87

5.1.4 Register Configuration......................................................................................... 87

5.2 Register Descriptions........................................................................................................88

5.2.1 System Control Register (SYSCR)...................................................................... 88

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 89

5.2.3 IRQ Status Register (ISR).................................................................................... 96

5.2.4 IRQ Enable Register (IER).................................................................................. 97

5.2.5 IRQ Sense Control Register (ISCR).................................................................... 98

5.3 Interrupt Sources............................................................................................................... 99

5.3.1 External Interrupts ............................................................................................... 99

5.3.2 Internal Interrupts ................................................................................................ 100

5.3.3 Interrupt Vector Table ......................................................................................... 100

5.4 Interrupt Operation ........................................................................................................... 104

5.4.1 Interrupt Handling Process .................................................................................. 104

5.4.2 Interrupt Sequence............................................................................................... 109

5.4.3 Interrupt Response Time...................................................................................... 110

5.5 Usage Notes...................................................................................................................... 111

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 111

5.5.2 Instructions that Inhibit Interrupts ....................................................................... 112

5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 112

Se ctio n 6 Bus Co ntr o ller................................................................................................... 113

6.1 Overview........................................................................................................................... 113

6.1.1 Features................................................................................................................ 113

6.1.2 Block Diagram..................................................................................................... 115

6.1.3 Pin Configuration................................................................................................. 116

6.1.4 Register Configuration......................................................................................... 117

6.2 Register Descriptions........................................................................................................ 118

6.2.1 Bus Width Control Register (ABWCR)............................................................... 118

6.2.2 Access State Control Register (ASTCR)............................................................. 119

6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 120

6.2.4 Bus Release Control Register (BRCR)................................................................ 124

6.2.5 Bus Control Register (BCR)................................................................................ 126

6.2.6 Chip Select Control Register (CSCR).................................................................. 129

6.2.7 DRAM Control Register A (DRCRA)................................................................. 130

6.2.8 DRAM Control Register B (DRCRB)................................................................. 132

Rev. 3.00 Sep 14, 2005 page x of xxii

6.2.9 Refresh Timer Control/Status Register (RTMCSR)............................................ 135

6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 136

6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 137

6.2.12 Address Control Register (ADRCR) ................................................................... 138

6.3 Operation.......................................................................................................................... 139

6.3.1 Area Division....................................................................................................... 139

6.3.2 Bus Specifications ............................................................................................... 141

6.3.3 Memory Interfaces............................................................................................... 142

6.3.4 Chip Select Signals.............................................................................................. 143

6.3.5 Address Output Method....................................................................................... 144

6.4 Basic Bus Interface........................................................................................................... 146

6.4.1 Overview.............................................................................................................. 146

6.4.2 Data Size and Data Alignment............................................................................. 146

6.4.3 Valid Strobes ...................................................................................................... 147

6.4.4 Memory Areas..................................................................................................... 148

6.4.5 Basic Bus Control Signal Timing........................................................................ 150

6.4.6 Wait Control........................................................................................................ 157

6.5 DRAM Interface............................................................................................................... 159

6.5.1 Overview.............................................................................................................. 159

6.5.2 DRAM Space and

RAS

Output Pin Settings....................................................... 159

6.5.3 A ddress Multipl exing.......................................................................................... 160

6.5.4 Data Bus .............................................................................................................. 161

6.5.5 Pins Used for DRAM Interface ........................................................................... 162

6.5.6 Basic Timing........................................................................................................ 162

6.5.7 Precharge State Control....................................................................................... 164

6.5.8 Wait Control........................................................................................................ 165

6.5.9 Byte Access Control and

CAS

Output Pin .......................................................... 166

6.5.10 Burst Operation.................................................................................................... 168

6.5.11 Refresh Control.................................................................................................... 174

6.5.12 Examples of Use.................................................................................................. 178

6.5.13 Usage Notes......................................................................................................... 183

6.6 Interval Timer................................................................................................................... 186

6.6.1 Operation............................................................................................................. 186

6.7 Interrupt Sources............................................................................................................... 192

6.8 Burst ROM Interface ........................................................................................................ 192

6.8.1 Overview.............................................................................................................. 192

6.8.2 Basic Timing........................................................................................................ 192

6.8.3 Wait Control........................................................................................................ 193

6.9 Idle Cycle.......................................................................................................................... 194

6.9.1 Operation............................................................................................................. 194

Rev. 3.00 Sep 14, 2005 page xi of xxii

6.9.2 Pin States in Idle Cycle........................................................................................ 197

6.10 Bus Arbiter........................................................................................................................ 198

6.10.1 Operation............................................................................................................. 198

6.11 Register and Pin Input Timing.......................................................................................... 201

6.11.1 Register Write Timing ......................................................................................... 201

6.11.2

BREQ

Pin Input Timing ...................................................................................... 202

Section 7 DMA Controller................................................................................................ 203

7.1 Overview........................................................................................................................... 203

7.1.1 Features................................................................................................................ 203

7.1.2 Block Diagram..................................................................................................... 204

7.1.3 Functional Overview............................................................................................ 205

7.1.4 Input/Outpu t Pins................................................................................................. 206

7.1.5 Register Configuration......................................................................................... 207

7.2 Register Descriptions (1) (Short Address Mode).............................................................. 208

7.2.1 Memory Address Registers (MAR)..................................................................... 208

7.2.2 I/O Address Registers (IOAR)............................................................................. 209

7.2.3 Execute Transfer Count Registers (ETCR).......................................................... 210

7.2.4 Data Transfer Control Registers (DTCR)............................................................ 211

7.3 Register Descriptions (2) (Full Address Mode)................................................................ 214

7.3.1 Memory Address Registers (MAR)..................................................................... 214

7.3.2 I/O Address Registers (IOAR)............................................................................. 214

7.3.3 Execute Transfer Count Registers (ETCR).......................................................... 215

7.3.4 Data Transfer Control Registers (DTCR)............................................................ 217

7.4 Operation .......................................................................................................................... 223

7.4.1 Overview.............................................................................................................. 223

7.4.2 I/O Mode.............................................................................................................. 225

7.4.3 Idle Mode............................................................................................................. 227

7.4.4 Repeat Mode........................................................................................................ 230

7.4.5 Normal Mode....................................................................................................... 234

7.4.6 Block Transfer Mode........................................................................................... 237

7.4.7 DMAC Act ivation................................................................................................ 242

7.4.8 DMAC Bus Cycle................................................................................................ 244

7.4.9 Multiple-Channel Operation................................................................................ 250

7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 251

7.4.11 N MI Interrup ts and DMA C ................................................................................. 252

7.4.12 Aborting a DMAC Transfer................................................................................. 253

7.4.13 Exiting Full Address Mode.................................................................................. 254

7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode ......................... 255

7.5 Interrupts........................................................................................................................... 256

Rev. 3.00 Sep 14, 2005 page xii of xxii

7.6 Usage Notes...................................................................................................................... 257

7.6.1 Note on Word Data Transfer ............................................................................... 257

7.6.2 DMAC Self-Access............................................................................................. 257

7.6.3 Longword Access to Memory Address Registers................................................ 257

7.6.4 Note on Full Address Mode Setup....................................................................... 257

7.6.5 Note on Activating DMAC by Internal Interrupts............................................... 258

7.6.6 NMI Interrupts and Block Transfer Mode........................................................... 259

7.6.7 Memory and I/O Address Register Values.......................................................... 259

7.6.8 Bus Cycle when Transfer is Aborted................................................................... 260

7.6.9 Transfer Requests by A/D Converter................................................................... 261

Section 8 I/O Ports.............................................................................................................. 263

8.1 Overview........................................................................................................................... 263

8.2 Port 1................................................................................................................................. 266

8.2.1 Overview.............................................................................................................. 266

8.2.2 Register Descriptions........................................................................................... 267

8.3 Port 2................................................................................................................................. 269

8.3.1 Overview.............................................................................................................. 269

8.3.2 Register Descriptions........................................................................................... 270

8.4 Port 3................................................................................................................................. 273

8.4.1 Overview.............................................................................................................. 273

8.4.2 Register Descriptions........................................................................................... 273

8.5 Port 4................................................................................................................................. 275

8.5.1 Overview.............................................................................................................. 275

8.5.2 Register Descriptions........................................................................................... 276

8.6 Port 5................................................................................................................................. 279

8.6.1 Overview.............................................................................................................. 279

8.6.2 Register Descriptions........................................................................................... 280

8.7 Port 6................................................................................................................................. 283

8.7.1 Overview.............................................................................................................. 283

8.7.2 Register Descriptions........................................................................................... 284

8.8 Port 7................................................................................................................................. 287

8.8.1 Overview.............................................................................................................. 287

8.8.2 Register Description ............................................................................................ 288

8.9 Port 8................................................................................................................................. 289

8.9.1 Overview.............................................................................................................. 289

8.9.2 Register Descriptions........................................................................................... 291

8.10 Port 9................................................................................................................................. 295

8.10.1 Overview.............................................................................................................. 295

8.10.2 Register Descriptions........................................................................................... 296

Rev. 3.00 Sep 14, 2005 page xiii of xxii

8.11 Port A................................................................................................................................ 300

8.11.1 Overview.............................................................................................................. 300

8.11.2 Register Descriptions........................................................................................... 302

8.12 Port B................................................................................................................................ 312

8.12.1 Overview.............................................................................................................. 312

8.12.2 Register Descriptions........................................................................................... 314

Se ctio n 9 16- Bit Tim e r ....................................................................................................... 321

9.1 Overview........................................................................................................................... 321

9.1.1 Features................................................................................................................ 321

9.1.2 Block Diagrams ................................................................................................... 323

9.1.3 Pin Configuration................................................................................................. 326

9.1.4 Register Configuration......................................................................................... 327

9.2 Register Descriptions........................................................................................................ 328

9.2.1 Timer Start Register (TSTR) ............................................................................... 328

9.2.2 Timer Synchro Register (TSNC)......................................................................... 329

9.2.3 Timer Mode Register (TMDR)............................................................................ 331

9.2.4 Timer Interrupt Status Register A (TISRA)......................................................... 333

9.2.5 Timer Interrupt Status Register B (TISRB)......................................................... 336

9.2.6 Timer Interrupt Status Register C (TISRC)......................................................... 339

9.2.7 Timer Counters (16TCNT).................................................................................. 341

9.2.8 General Registers (GRA, GRB)........................................................................... 342

9.2.9 Timer Control Registers (16TCR) ....................................................................... 343

9.2.10 Timer I/O Control Register (TIOR)..................................................................... 346

9.2.11 Timer Output Level Setting Register C (TOLR)................................................. 348

9.3 CPU Interface ................................................................................................................... 350

9.3.1 16-Bit Accessible Registers................................................................................. 350

9.3.2 8-Bit Accessible Registers................................................................................... 352

9.4 Operation .......................................................................................................................... 353

9.4.1 Overview.............................................................................................................. 353

9.4.2 Basic Functions.................................................................................................... 354

9.4.3 Synchronization................................................................................................... 361

9.4.4 PWM Mode ......................................................................................................... 363

9.4.5 Phase Counting Mode.......................................................................................... 367

9.4.6 16-Bit Timer Output Timing................................................................................ 369

9.5 Interrupts........................................................................................................................... 370

9.5.1 Setting of Status Flags ......................................................................................... 370

9.5.2 Timing of Clearing of Status Flags...................................................................... 372

9.5.3 Interrupt Sources.................................................................................................. 373

9.6 Usage Notes...................................................................................................................... 374

Rev. 3.00 Sep 14, 2005 page xiv of xxii

Section 10 8-Bit Timers..................................................................................................... 387

10.1 Overview........................................................................................................................... 387

10.1.1 Features................................................................................................................ 387

10.1.2 Block Diagram..................................................................................................... 389

10.1.3 Pin Configuration ................................................................................................ 390

10.1.4 Register Configuration......................................................................................... 391

10.2 Register Descriptions........................................................................................................ 392

10.2.1 Timer Counters (8TCNT).................................................................................... 392

10.2.2 Time Constant Registers A (TCORA)................................................................. 393

10.2.3 Time Constant Registers B (TCORB) ................................................................. 394

10.2.4 Timer Control Register (8TCR)........................................................................... 395

10.2.5 Timer Control/Status Registers (8TCSR) ............................................................ 398

10.3 CPU Interface................................................................................................................... 403

10.3.1 8-Bit Registers..................................................................................................... 403

10.4 Operation.......................................................................................................................... 405

10.4.1 8TCNT Count Timing ......................................................................................... 405

10.4.2 Compare Match Timing....................................................................................... 406

10.4.3 Input Capture Signal Timing ............................................................................... 407

10.4.4 Timing of Status Flag Setting.............................................................................. 408

10.4.5 Operation with Cascaded Connection.................................................................. 409

10.4.6 Input Capture Setting........................................................................................... 412

10.5 Interrupt ............................................................................................................................ 414

10.5.1 Interrupt Sources.................................................................................................. 414

10.5.2 A/D Converter Activation.................................................................................... 415

10.6 8-Bit Timer Application Example .................................................................................... 415

10.7 Usage Notes...................................................................................................................... 416

10.7.1 Contention between 8TCNT Write and Clear...................................................... 416

10.7.2 C ontention betw een 8 TCN T Write and Incremen t.............................................. 417

10.7.3 Contention between TCOR Write and Compare Match...................................... 418

10.7.4 C ontention betw een TCOR Read and Inpu t Capture........................................... 419

10.7.5 Contention between Counter Clearing by Input Capture and Counter

Increment............................................................................................................. 420

10.7.6 Contention between TCOR Write and Input Capture.......................................... 421

10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

(Cascaded Connection)........................................................................................ 422

10.7.8 Contention between Compare Matches A and B................................................. 423

10.7.9 8TCNT Operation and Internal Clock Source Switchover.................................. 423

Section 11 Programmable Timing Pattern Controller (TPC) ................................. 427

11.1 Overview........................................................................................................................... 427

Rev. 3.00 Sep 14, 2005 page xv of xxii

11.1.1 Features................................................................................................................ 427

11.1.2 Block Diagram..................................................................................................... 428

11.1.3 TPC Pin s.............................................................................................................. 429

11.1.4 Registers .............................................................................................................. 430

11.2 Register Descriptions........................................................................................................ 431

11.2.1 Port A Data Direction Register (PADDR)........................................................... 431

11.2.2 Port A Data Register (PADR).............................................................................. 431

11.2.3 Port B Data Direction Register (PBDDR)........................................................... 432

11.2.4 Port B Data Register (PBDR) .............................................................................. 432

11.2.5 Next Data Register A (NDRA)............................................................................ 433

11.2.6 Next Data Register B (NDRB) ............................................................................ 435

11.2.7 Next Data Enable Register A (NDERA).............................................................. 437

11.2.8 Next Data Enable Register B (NDERB)............................................................... 438

11.2.9 TPC Output Control Register (TPCR)................................................................. 439

11.2.10 TPC Output Mode Register (TPMR)................................................................... 442

11.3 Operation .......................................................................................................................... 444

11.3.1 Overview.............................................................................................................. 444

11.3.2 O utput Timing...................................................................................................... 445

11.3.3 N ormal TPC Output............................................................................................. 446

11.3.4 Non-Overlapping TPC Output............................................................................. 448

11.3.5 TPC Output Triggering by Input Capture............................................................ 450

11.4 Usage Notes...................................................................................................................... 451

11.4.1 Operation of TPC Output Pins............................................................................. 451

11.4.2 Note on Non-Overlapping Output ....................................................................... 451

Section 12 Watchdog Timer............................................................................................. 453

12.1 Overview........................................................................................................................... 453

12.1.1 Features................................................................................................................ 453

12.1.2 Block Diagram..................................................................................................... 454

12.1.3 Register Configuration......................................................................................... 454

12.2 Register Descriptions........................................................................................................ 455

12.2.1 Timer Counter (TCNT)........................................................................................ 455

12.2.2 Timer Control/Status Register (TCSR)................................................................ 456

12.2.3 Reset Control/Status Register (RSTCSR)............................................................ 458

12.2.4 Notes on Register Access .................................................................................... 459

12.3 Operation .......................................................................................................................... 461

12.3.1 Watchdog Timer Operation................................................................................. 461

12.3.2 Interval Timer Operation..................................................................................... 462

12.3.3 Timing of Setting of Overflow Flag (OVF)......................................................... 463

12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 464

Rev. 3.00 Sep 14, 2005 page xvi of xxii

12.4 Interrupts........................................................................................................................... 465

12.5 Usage Notes...................................................................................................................... 465

Section 13 Serial Communication Interface................................................................ 467

13.1 Overview........................................................................................................................... 467

13.1.1 Features................................................................................................................ 467

13.1.2 Block Diagram..................................................................................................... 469

13.1.3 Inpu t/Ou tput Pins................................................................................................. 470

13.1.4 Register Configuration......................................................................................... 471

13.2 Register Descriptions........................................................................................................ 472

13.2.1 Receive Shift Register (RSR) .............................................................................. 472

13.2.2 Receive Data Register (RDR).............................................................................. 472

13.2.3 Transmit Shift Register (TSR)............................................................................. 473

13.2.4 Transmit Data Register (TDR) ............................................................................ 473

13.2.5 Serial Mode Register (SMR) ............................................................................... 474

13.2.6 Serial Control Register (SCR) ............................................................................. 478

13.2.7 Serial Status Register (SSR) ................................................................................ 483

13.2.8 Bit Rate Register (BRR)...................................................................................... 488

13.3 Operation.......................................................................................................................... 497

13.3.1 Overview.............................................................................................................. 497

13.3.2 Operation in Asynchronous Mode....................................................................... 499

13.3.3 Multiprocessor Communication .......................................................................... 509

13.3.4 Synchronous Operation ....................................................................................... 516

13.4 SCI Interrupts.................................................................................................................... 525

13.5 Usage Notes...................................................................................................................... 526

13.5.1 Notes on Use of SCI ............................................................................................ 526

Section 14 Smart Card Interface..................................................................................... 533

14.1 Overview........................................................................................................................... 533

14.1.1 Features................................................................................................................ 533

14.1.2 Block Diagram..................................................................................................... 534

14.1.3 Pin Configuration ................................................................................................ 535

14.1.4 Register Configuration......................................................................................... 536

14.2 Register Descriptions........................................................................................................ 537

14.2.1 Smart Card Mode Register (SCMR).................................................................... 537

14.2.2 Serial Status Register (SSR) ................................................................................ 539

14.2.3 Serial Mode Register (SMR) ............................................................................... 540

14.2.4 Serial Control Register (SCR) ............................................................................. 541

14.3 Operation.......................................................................................................................... 542

14.3.1 Overview.............................................................................................................. 542

Rev. 3.00 Sep 14, 2005 page xvii of xxii

14.3.2 Pin Connections................................................................................................... 542

14.3.3 Data Format......................................................................................................... 544

14.3.4 Register Settings .................................................................................................. 545

14.3.5 Clock.................................................................................................................... 547

14.3.6 Transmitting and Receiving Data ........................................................................ 549

14.4 Usage Notes...................................................................................................................... 557

Section 15 A/D Converter................................................................................................. 561

15.1 Overview........................................................................................................................... 561

15.1.1 Features................................................................................................................ 561

15.1.2 Block Diagram..................................................................................................... 562

15.1.3 Inpu t Pins............................................................................................................. 563

15.1.4 Register Configuration......................................................................................... 564

15.2 Register Descriptions........................................................................................................ 565

15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 565

15.2.2 A/D Control/Status Register (ADCSR) ............................................................... 566

15.2.3 A/D Control Register (ADCR) ............................................................................ 569

15.3 CPU Interface ................................................................................................................... 570

15.4 Operation .......................................................................................................................... 572

15.4.1 Single Mode (SCAN = 0) .................................................................................... 572

15.4.2 Scan Mode (SCAN = 1)....................................................................................... 574

15.4.3 Input Sampling and A/D Conversion Time......................................................... 576

15.4.4 Exte rnal Trig g er Input Timing............................................................................. 578

15.5 Interrupts........................................................................................................................... 579

15.6 Usage Notes...................................................................................................................... 579

Section 16 D/A Converter................................................................................................. 585

16.1 Overview........................................................................................................................... 585

16.1.1 Features................................................................................................................ 585

16.1.2 Block Diagram..................................................................................................... 586

16.1.3 Inpu t/Ou tput Pins................................................................................................. 586

16.1.4 Register Configuration......................................................................................... 587

16.2 Register Descriptions........................................................................................................ 588

16.2.1 D/A Data Registers 0 and 1 (DADR0/1) ............................................................. 588

16.2.2 D/A Control Register (DACR) ............................................................................ 588

16.2.3 D/A Standby Control Register (DASTCR).......................................................... 590

16.3 Operation .......................................................................................................................... 591

16.4 D/A Output Control.......................................................................................................... 592

Rev. 3.00 Sep 14, 2005 page xviii of xxii

Se ctio n 1 7 RAM.................................................................................................................. 593

17.1 Overview........................................................................................................................... 593

17.1.1 Block Diagram..................................................................................................... 594

17.1.2 Register Configuration......................................................................................... 594

17.2 System Control Register (SYSCR)................................................................................... 595

17.3 Operation.......................................................................................................................... 596

Section 18 Flash Memory................................................................................................. 597

18.1 Overview........................................................................................................................... 597

18.2 Features............................................................................................................................. 598

18.2.1 Block Diagram..................................................................................................... 599

18.2.2 Pin Configuration ................................................................................................ 600

18.2.3 Register Configuration......................................................................................... 600

18.3 Register Descriptions........................................................................................................ 601

18.3.1 Flash Memory Control Register 1 (FLMCR1) .................................................... 601

18.3.2 Flash Memory Control Register 2 (FLMCR2) .................................................... 604

18.3.3 Erase Block Register 1 (EBR1)........................................................................... 605

18.3.4 Erase Block Register 2 (EBR2)........................................................................... 606

18.3.5 RAM Control Register (RAMCR)....................................................................... 607

18.4 Overview of Operation ..................................................................................................... 609

18.4.1 Mode Transi tion s................................................................................................. 609

18.4.2 O n-B oard Programming Modes........................................................................... 611

18.4.3 Flash Memory Emulation in RAM...................................................................... 613

18.4.4 Block Configuration ............................................................................................ 615

18.5 On-Board Prog ramming Mode ......................................................................................... 616

18.5.1 B oot Mode........................................................................................................... 617

18.5.2 U ser Program Mode............................................................................................. 622

18.6 Flash Memory Programming/Erasing............................................................................... 624

18.6.1 Program Mode..................................................................................................... 626

18.6.2 Program-Verify Mode ......................................................................................... 627

18.6.3 Erase Mode.......................................................................................................... 631

18.6.4 Erase-Verify Mode .............................................................................................. 631

18.7 Flash Memory Protection.................................................................................................. 633

18.7.1 H ardw are Protection............................................................................................ 633

18.7.2 Softw are Protection ............................................................................................. 634

18.7.3 Erro r Protecti on ................................................................................................... 635

18.8 Flash Memory Emulation in RAM ................................................................................... 637

18.9 NMI Input Disabling Conditions...................................................................................... 640

18.10 Fl ash Memory PROM Mod e ............................................................................................ 641

18.10.1 Socket Adapters and Memory Map ..................................................................... 641

Rev. 3.00 Sep 14, 2005 page xix of xxii

18.10.2 Notes on Use of PROM Mode............................................................................. 642

18.11 Flash Memory Programming and Erasing Precautions..................................................... 643

Section 19 Clock Pulse Generator.................................................................................. 649

19.1 Overview........................................................................................................................... 649

19.1.1 Block Diagram..................................................................................................... 650

19.2 Oscillator Circuit............................................................................................................... 651

19.2.1 Connecting a Crystal Resonator........................................................................... 651

19.2.2 External Clock Input............................................................................................ 653

19.3 Duty Adjustment Circuit................................................................................................... 655

19.4 Prescalers.......................................................................................................................... 655

19.5 Frequency Divider ............................................................................................................ 656

19.5.1 Register Configuration......................................................................................... 656

19.5.2 Division Control Register (DIVCR).................................................................... 656

19.5.3 Usage Notes......................................................................................................... 657

Section 20 Power-Down State......................................................................................... 659

20.1 Overview........................................................................................................................... 659

20.2 Register Configuration...................................................................................................... 661

20.2.1 System Control Register (SYSCR)...................................................................... 661

20.2.2 Module Standby Control Register H (MSTCRH)................................................ 663

20.2.3 Module Standby Control Register L (MSTCRL)................................................. 664

20.3 Sleep Mode....................................................................................................................... 667

20.3.1 Transition to Sleep Mode..................................................................................... 667

20.3.2 Exit from Sleep Mode.......................................................................................... 667

20.4 Software Standby Mode.................................................................................................... 668

20.4.1 Transition to Software Standby Mode................................................................. 668

20.4.2 Exit from Software Standby Mode...................................................................... 668

20.4.3 Selection of Waiting Time for Exit from Software Standby Mode ..................... 669

20.4.4 Sample Application of Software Standby Mode.................................................. 670

20.4.5 Note ..................................................................................................................... 670

20.5 Hardware Standby Mode .................................................................................................. 671

20.5.1 Transition to Hardware Standby Mode................................................................ 671

20.5.2 Exit from Hardware Standby Mode..................................................................... 671

20.5.3 Timing for Hardware Standby Mode................................................................... 671

20.6 Module Standby Function................................................................................................. 673

20.6.1 Module Standby Timing...................................................................................... 673

20.6.2 Read/Write in Module Standby ........................................................................... 673

20.6.3 Usage Notes......................................................................................................... 673

20.7 System Clock Output Disabling Function......................................................................... 674

Rev. 3.00 Sep 14, 2005 page xx of xxii

Section 21 Electrical Characteristics............................................................................. 675

21.1 Electrical Characteristics of H8/3068F-ZTAT.................................................................. 675

21.1.1 Absolute Maximum Ratings................................................................................ 675

21.1.2 DC Characteristics............................................................................................... 676

21.1.3 AC Characteristics............................................................................................... 681

21.1.4 A/D Conversion Characteristics .......................................................................... 687

21.1.5 D/A Conversion Characteristics.......................................................................... 689

21.1.6 Flash Memory Characteristics............................................................................. 690

21.2 Operational Timing........................................................................................................... 692

21.2.1 Clock Timing....................................................................................................... 692

21.2.2 Control Signal Timing ......................................................................................... 693

21.2.3 B us Timing .......................................................................................................... 694

21.2.4 DRAM Interface Bus Timing .............................................................................. 700

21.2.5 TPC and I/O Port Timing..................................................................................... 703

21.2.6 Tim er Input/Out put Timing ................................................................................. 704

21.2.7 SCI Input/Output Timing..................................................................................... 705

21.2.8 DMAC Timing..................................................................................................... 706

Appendix A Instruction Set.............................................................................................. 707

A.1 Instruction List.................................................................................................................. 707

A.2 Operation Code Maps....................................................................................................... 723

A.3 Number of States Required for Execution........................................................................ 726

Appendix B Internal I/O Registers................................................................................. 735

B.1 Addresses (EMC = 1) ......................................................................................................... 735

B.2 Addresses (EMC = 0) ......................................................................................................... 746

B.3 Functions .......................................................................................................................... 763

Appendix C I/O Port Block Diagrams.......................................................................... 854

C.1 Port 1 Block Diagram....................................................................................................... 854

C.2 Port 2 Block Diagram....................................................................................................... 855

C.3 Port 3 Block Diagram....................................................................................................... 856

C.4 Port 4 Block Diagram....................................................................................................... 857

C.5 Port 5 Block Diagram....................................................................................................... 858

C.6 Port 6 Block Diagrams...................................................................................................... 859

C.7 Port 7 Block Diagrams...................................................................................................... 866

C.8 Port 8 Block Diagrams...................................................................................................... 867

C.9 Port 9 Block Diagrams...................................................................................................... 872

C.10 Port A Block Diagrams..................................................................................................... 878

C.11 Port B Block Diagrams..................................................................................................... 881

Rev. 3.00 Sep 14, 2005 page xxi of xxii

Appendix D Pin States....................................................................................................... 889

D.1 Port States in Each Mode.................................................................................................. 889

D.2 Pin States at Reset............................................................................................................. 896

Appendix E Timing of Tran siti on to and Rec overy from Hardware Sta ndby

Mode............................................................................................................... 899

Appen di x F Product Code Lineup.................................................................................. 900

Appendix G Package Dimensions.................................................................................. 901

Appendix H Comparison of H8/ 300H Series Prod uct Sp eci ficat ions.................. 903

H.1 Differences between H8/3068F and H8/3067 Group and H8/3062 Group,

H8/3048 Group.................................................................................................................903

H.2 C ompari son of Pin Func tions of 100- Pin Packag e Produc ts (FP-100B, TF P-100B).......906

Rev. 3.00 Sep 14, 2005 page xxii of xxii

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 1 of 910

REJ09B0258-0300

Section 1 Overview

1.1 Overview

The H8/3068F is a series of microcontrollers (MCUs) that integrate system supporting functions

together with an H8/300H CPU core having an original Renesas Technology architecture.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a

concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address

space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,

enabling easy porting of software from the H8/300 Series.

The on-chip system supporting functions include ROM, RAM, a 16-bit timer, an 8-bit timer, a

programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication

interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller

(DMAC), and other facilities.

The H8/3068F has 384 kbytes of ROM and 16 kbytes of RAM.

Seven MCU operating modes offer a choice of bus width and address space size. The modes

(modes 1 to 7) include two single-chip modes and five expanded modes.

The H8/3068F includes an F-ZTAT™* version with on-chip flash memory that can be

programmed on-board. This version enables users to respond quickly and flexibly to changing

application specifications, growing production volumes, and other conditions.

Table 1.1 summarizes the features of the H8/3068F.

Note: * F-ZTAT™ (Flexible ZTAT) is a trademark of Renesas Technology Corp.

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 2 of 910

REJ09B0258-0300

Table 1.1 Features

Feature Description

CPU Upward-compatible with the H8/300 CPU at the object-code level

General-regi ster machine

• Sixteen 16-bit general registers

(also usable as sixteen 8-bit registers or eight 32-bit registers)

High-speed operation

• Maximum clock rate: 25 MHz

• Add/subtract: 80 ns

• Multiply/divide: 560 ns

16-Mbyte address space

Instruction features

• 8/16/32-bit data transfer, arithmetic, and logic instructions

• Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)

• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)

• Bit accumulator function

• Bit manipulation instructions with register-indirect specification of bit

positions

Memory H8/3068F

• ROM: 384 kbytes

• RAM: 16 kbytes

Interrupt

controller • Seven external interrupt pins: NMI,

IRQ

0 to

IRQ

• 36 internal interrupts

• Three selectable interrupt priority l evels

Bus controller • Address space can be partitioned into eight areas, with i ndependent bus

specifi cations in each area

• Chip select output available for areas 0 to 7

• 8-bit access or 16-bit access selectable for each area

• Two-state or three-state access selectable for each area

• Selecti on of two wait modes

• Number of program wait states selectable for each area

• Direct connection of burst ROM

• Direct connection of up to 8-Mbyte DRAM (or DRAM interface can be used

as interval timer)

• Bus arbitration function

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 3 of 910

REJ09B0258-0300

Feature Description

DMA controller

(DMAC) Short address mode

• Maximum four channels available

• Selecti on of I/O mode, idle mode, or repeat mode

• Can be activated by compare match/input capture A interrupts from 16-bit

timer channels 0 to 2, conversion-end interrupts from the A/D converter,

transmit-data-empty and receive-data-full interrupts from the SCI, or external

requests

Full address mode

• Maximum two channels available

• Selection of normal mode or block transfer mode

• Can be activated by compare match/input capture A interrupts from 16-bit

timer channels 0 to 2, conversion-end interrupts from the A/D converter,

external requests, or auto-request

16-bit ti mer,

3 channels • Three 16-bit timer channels, capabl e of processing up to six pulse outputs

or six pulse inputs

• 16-bit timer counter (channels 0 to 2)

• Two multiplexed output compare/input capture pins (channels 0 to 2)

• Operation can be synchronized (channels 0 to 2)

• PWM mode available (channels 0 to 2)

• Phase counting mode available (channel 2)

• DMAC can be activated by compare match/input capture A interrupts

(channels 0 to 2)

8-bit ti mer,

4 channels • 8-bit up-counter (external event count capability)

• Two time constant registers

• Two channels can be connected

Programmable

timing pattern

controller (TPC)

• Maximum 16-bit pulse output, using 16-bit timer as time base

• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit

groups)

• Non-overlap mode available

• Output data can be transferred by DMAC

Watchdog

timer (WDT),

1 channel

• Reset signal can be generated by overflow

• Reset signal can be output externally (not in the F-ZTAT version)

• Usable as an i nterval timer

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 4 of 910

REJ09B0258-0300

Feature Description

Serial

communication

interface (SCI),

3 channels

• Selecti on of asynchronous or synchronous mode

• Full duplex: can transmit and receive simultaneously

• On-chip baud-rate generator

• Smart card interface functions added

A/D converter • Resolution: 10 bits

• Eight channels, with selection of single or scan mode

• Variable analog conversion voltage range

• Sample-and-hold function

• A/D conversion can be started by an external trigger or 8-bit timer compare-

match

• DMAC can be activated by an A/D conversion end i nterrupt

D/A converter • Resolution: 8 bits

• Two channels

• D/A outputs can be sustained in software standby mode

I/O ports • 70 input/output pins

• 9 input-only pins

Operating modes • Seven MCU operating modes

Mode Address Space Address Pins Initial Bus Width Max. Bus Width

Mode 1 1 Mbyte A19 to A08 bits 16 bits

Mode 2 1 Mbyte A19 to A016 bits 16 bits

Mode 3 16 Mbytes A23 to A08 bits 16 bits

Mode 4 16 Mbytes A23 to A016 bits 16 bits

Mode 5 16 Mbytes A23 to A08 bits 16 bits

Mode 6 64 kbyte — — —

Mode 7 1 Mbyte — — —

• On-chip ROM is disabled in modes 1 to 4

Power-down

state • Sleep mode

• Software standby mode

• Hardware standby mode

• Module standby function

• Programmable system clock frequency division

Other features • On-chip clock pulse generator

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 5 of 910

REJ09B0258-0300

Feature Description

Product lineup P r oduct Type Product Code Package

H8/3068 F-ZTAT 5 V operation HD64F3068F 100-pin QFP (FP-100B)

HD64F3068TE 100-pin TQFP (TFP-100B)

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 6 of 910

REJ09B0258-0300

1.2 Block Diagram

Figure 1.1 shows an internal block diagram.

P3 /D

P4 /D

Port 3 Port 4

Port 5Port 9

P5 /A

P2 /A

P9 /SCK /IRQ

P9 /RxD

P9 /TxD

/AN

/P7

/AN

/P7

Port 7

/TIOCB

/TP

/PA

/TIOCA

/TP

/PA

/TIOCB

/TP

/PA

/TIOCA

/TP

/PA

TCLKD/TIOCB

/TP

/PA

TCLKC/TIOCA

/TP

/PA

TEND

/TCLKB/TP

/PA

TEND

/TCLKA/TP

/PA

Port A

RxD

/TP

/PB

TxD

/TP

/PB

SCK

/LCAS/TP

/PB

UCAS/TP

/PB

/DREQ

/TMIO

/TP

/PB

/TMO

/TP

/PB

/DREQ

/TMIO

/TP

/PB

/TMO

/TP

/PB

Port 8

/P8

ADTRG/CS

/IRQ

/P8

/IRQ

/P8

/IRQ

/P8

RFSH/IRQ

/P8

EXTAL

XTAL

STBY

RES

FWE

NMI

H8/300H CPU

Clock pulse

generator

Interrupt controller

ROM

(flash memory)

DMA controller

(DMAC)

Serial communication

interface

(SCI) 3 channels

Watchdog timer

(WDT)

Address bus

Data bus (upper)

Data bus (lower)

Port 2

P1 /A

Port 1

φ/P6

LWR/P6

HWR/P6

RD/P6

AS/P6

BACK/P6

BREQ/P6

WAIT/P6

RAM

16-bit timer unit

8-bit timer unit

A/D converter

D/A converter

Port 6

Bus controller

Programmable

timing pattern

controller (TPC)

Port B

REF

Figure 1.1 Block Diagram

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 7 of 910

REJ09B0258-0300

1.3 Pin Description

1.3.1 Pin Arrangement

The pin arrangement of the H8/3068F FP-100B and TFP-100B packages is shown in figure 1.2.

/TMO

/TP

/PB

/DREQ

/TMIO

/TP

/PB

/TMO

/TP

/PB

/DREQ

/TMIO

/TP

/PB

UCAS/TP

/PB

SCK

/LCAS/TP

/PB

TxD

/TP

/PB

RxD

/TP

/PB

FWE

TxD /P9

RxD /P9

IRQ /SCK /P9

D /P4

P6 /LWR

P6 /HWR

P6 /RD

P6 /AS

XTAL

EXTAL

NMI

RES

STBY

/φ

P6 /BACK

P6 /BREQ

P6 /WAIT

P5 /A

P2 /A

/P2

/P1

/P3

/P4

100

REF

/AN

/DA

/AN

/DA

/IRQ

/RFSH

/IRQ

/CS

/IRQ

/CS

/IRQ

/CS

/ADTRG

/CS

/TP

/TCLKA/TEND

/TP

/TCLKB/TEND

/TP

/TIOCA

/TCLKC

/TP

/TIOCB

/TCLKD

/TP

/TIOCA

/TP

/TIOCB

/TP

/TIOCA

/TP

/TIOCB

Top view

(FP-100B, TFP-100B)

Note: * Functions as V

pin. When functioning as V

pin, the connection of an external capacitor

is required.

0.1 µF

Figure 1.2 Pin Arrangement (FP-100B or TFP-100B, Top View)

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 8 of 910

REJ09B0258-0300

1.3.2 Pin Functions

Table 1.2 summarizes the pin functions.

Table 1.2 Pin Functions

Pin No.

Type Symbol FP-100B

TFP-100B I/O Name and Function

Power VCC 35, 68 Input Power: For connection to the power supply. Connect

all VCC pins to the system power supply.

VSS 11, 22, 44,

57, 65, 92 Input Ground: For connection to ground (0 V).

Connect all VSS pins to the 0-V system power supply.

Clock XTAL 67 Input For connection to a crystal resonator.

For examples of crystal resonator and external clock

input, see section 19, Clock Pulse Generator.

EXTAL 66 Input For connection to a crystal resonator or input of an

external clock signal. For examples of crystal

resonator and external clock input, see section 19,

Clock Pulse Generator.

φ61 Output System clock: Supplies the system clock to external

devices.

Internal

step-down

VCL 1 Output Connect an external capacitor between this pin and

GND (0 V). Do not connect to VCC.

0.1 µF

Operating

mode

control

MD2 to

MD0

75 to 73 Input Mode 2 to mode 0: For setting the operati ng mode,

as follows. Inputs at these pins must not be changed

during operation.

MD2MD1MD0Operating Mode

000—

0 0 1 Mode 1

0 1 0 Mode 2

0 1 1 Mode 3

1 0 0 Mode 4

1 0 1 Mode 5

1 1 0 Mode 6

1 1 1 Mode 7

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 9 of 910

REJ09B0258-0300

Pin No.

Type Symbol FP-100B

TFP-100B I/O Name and Function

System

control

RES

63 Input Reset input: When driven low, this pin resets the

chip

FWE 10 Input Write enable signal: Flash memory write control

signal

STBY

62 Input Standby: When driven low, this pin forces a

transition to hardware standby mode

BREQ

59 Input Bus request: Used by an external bus master to

request the bus right

BACK

60 Output Bus request acknowledge: Indicates that the bus

has been granted to an external bus master

Interrupts NMI 64 Input Nonmaskable interrupt: Requests a

nonmaskable interrupt

IRQ

5 to

IRQ

17, 16,

90 to 87 Input Interrupt request 5 to 0: Maskable i n terrupt request

pins

Address

bus A23 to A097 to 100,

56 to 45,

43 to 36

Output Address bus: Outputs address signals

Data bus D15 to D034 to 23,

21 to 18 Input/

output Data bus: Bidirecti onal data bus

Bus control

7 to

2 to 5,

88 to 91 Output Chip select: Select signals for areas 7 to 0

69 Output Address strobe: Goes low to indicate valid address

output on the address bus

70 Output Read: Goes low to indicate reading from the external

address space

HWR

71 Output High write: Goes low to indicate writing to the

external address space; indicates valid data on the

upper data bus (D15 to D8).

LWR

72 Output Low write: Goes low to indicate writing to the

external address space; indicates valid data on the

lower data bus (D7 to D0).

WAIT

58 Input Wait: Requests insertion of wait states in bus cycles

during access to the external address space

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 10 of 910

REJ09B0258-0300

Pin No.

Type Symbol FP-100B

TFP-100B I/O Name and Function

DRAM

interface

RFSH

87 Output Refresh: Indicates a refresh cycle

2 to

89, 88,

5, 4 Output Row address strobe

RAS

: Row address strobe

signal for DRAM

70 Output Write enable

: Write enable signal for DRAM

HWR

UCAS

6Output Upper column address strobe

UCAS

: Colu mn

address strobe signal for DRAM

LWR

LCAS

7Output Lower column address strobe

LCAS

: Colu mn

address strobe signal for DRAM

DREQ

5, 3 Input DMA request 1 and 0: DMAC activation

requests

DMA

controller

(DMAC)

TEND

94, 93 Output Transfer end 1 and 0: These signals indi cate that

the DMAC has ended a data transfer

16-bit timer TCLKD to

TCLKA 96 to 93 Input Clock input D to A: External clock i nputs

TIOCA2 to

TIOCA0

99, 97, 95 Input/

output Input capture/output compare A2 to A0: GRA2 to

GRA0 output compare or input capture, or PWM

output

TIOCB2 to

TIOCB0

100, 98,

96 Input/

output Input capture/output compare B2 to B0: GRB2 to

GRB0 output compare or input capture, or PWM

output

8-bit ti mer T MO0,

TMO2

2, 4 Output Compare match output: Compare match output

pins

TMIO1,

TMIO3

3, 5 Input/

output Input capture input/compare match output: Input

capture input or compare match output pins

TCLKD to

TCLKA 96 to 93 Input Counter external clock input: These pins input an

external clock to the counters.

Program-

mable

timing

pattern

controller

(TPC)

TP15 to

TP0

9 to 2,

100 to 93 Output TPC output 15 to 0: Pulse output

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 11 of 910

REJ09B0258-0300

Pin No.

Type Symbol FP-100B

TFP-100B I/O Name and Function

TxD2 to

TxD0

8, 13, 12 Output Transmit data (channels 0, 1, 2): SCI data outputSeria l com-

munication

interface

(SCI) RxD2 to

RxD0

9, 15, 14 Input Receive data (channels 0, 1, 2): SCI data input

SCK2 to

SCK0

7, 17, 16 Input/

output Serial clock (channels 0, 1, 2): SCI clock

input/output

A/D

converter AN7 to

AN0

85 to 78 Input Analog 7 to 0: Analog input pins

ADTRG

90 Input A/D conversion external trigger input: External

trigger i nput for starting A/D conversion

D/A

converter DA1, DA085, 84 Output Analog output: Analog output from the

D/A converter

A/D and

D/A

converters

AVCC 76 Input Power supply pin for the A/D and D/A converters.

Connect to the system power supply when not using

the A/D and D/A converters.

AVSS 86 Input Ground pin for the A/D and D/A converters. Connect

to system ground (0 V).

VREF 77 Input Reference voltage input pi n for the A/D and D/A

converters. Connect to the system power supply

when not using the A/D and D/A converters.

I/O ports P17 to P1043 to 36 Input/

output Port 1: Eight input/output pi ns. The direction of each

pin can be sel ected in the port 1 data direction

P27 to P2052 to 45 Input/

output Port 2: Eight input/output pi ns. The direction of each

pin can be sel ected in the port 2 data direction

P37 to P3034 to 27 Input/

output Port 3: Eight input/output pi ns. The direction of each

pin can be sel ected in the port 3 data direction

P47 to P4026 to 23,

21 to 18 Input/

output Port 4: Eight input/output pi ns. The direction of each

pin can be sel ected in the port 4 data direction

P53 to P5056 to 53 Input/

output Port 5: Four input/output pins. The direction of each

pin can be sel e cted in the port 5 data direction

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 12 of 910

REJ09B0258-0300

Pin No.

Type Symbol FP-100B

TFP-100B I/O Name and Function

I/O ports P67 to P6061,

72 to 69,

60 to 58

Input/

output Port 6: Eight input/output pi ns. The direction of each

pin can be sel ected in the port 6 data direction

P77 to P7085 to 78 Input Port 7: Eight input pins

P84 to P8091 to 87 Input/

output Port 8: Five input/output pins. The direction of each

pin can be sel e cted in the port 8 data direction

P95 to P9017 to 12 Input/

output Port 9: Six input/output pins. The direction of each

pin can be sel ected in the port 9 data direction

PA7 to PA0100 to 93 Input/

output Port A: Eight input/output pins. The direction of each

pin can be sel ected in the port A data directi o n

PB7 to PB09 to 2 Input/

output Port B: Eight input/output pins. The direction of each

pin can be sel ected in the port B data directi o n

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 13 of 910

REJ09B0258-0300

1.3.3 Pin Assignments in Each Mode

Table 1.3 lists the pin assignments in each mode.

Table 1.3 Pin Assignments in Each Mode (FP-100B or TFP-100B)

Pin No. Pin Name

FP-100B

TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

CL*1VCL*1VCL*1VCL*1VCL*1VCL*1VCL*1

2PB

0/TP8/

TMO0/

PB0/TP8/

TMO0/

PB0/TP8/

TMO0/

PB0/TP8/

TMO0/

PB0/TP8/

TMO0/

PB0/TP8/

TMO0

PB0/TP8/

TMO0

3PB

1/TP9/

TMIO1/

DREQ

PB1/TP9/

TMIO1/

DREQ

PB1/TP9/

TMIO1/

DREQ

PB1/TP9/

TMIO1/

DREQ

PB1/TP9/

TMIO1/

DREQ

PB1/TP9/

TMIO1/

DREQ

PB1/TP9/

TMIO1/

DREQ

4PB

2/TP10/

TMO2/

PB2/TP10/

TMO2/

PB2/TP10/

TMO2/

PB2/TP10/

TMO2/

PB2/TP10/

TMO2/

PB2/TP10/

TMO2

PB2/TP10/

TMO2

5PB

3/TP11/

TMIO3/

DREQ

PB3/TP11/

TMIO3/

DREQ

PB3/TP11/

TMIO3/

DREQ

PB3/TP11/

TMIO3/

DREQ

PB3/TP11/

TMIO3/

DREQ

PB3/TP11/

TMIO3/

DREQ

PB3/TP11/

TMIO3/

DREQ

6PB

4/TP12/

UCAS

PB4/TP12/

UCAS

PB4/TP12/

UCAS

PB4/TP12/

UCAS

PB4/TP12/

UCAS

PB4/TP12 PB4/TP12

7PB

5/TP13/

LCAS

SCK2

PB5/TP13/

LCAS

SCK2

PB5/TP13/

LCAS

SCK2

PB5/TP13/

LCAS

SCK2

PB5/TP13/

LCAS

SCK2

PB5/TP13/

SCK2

PB5/TP13/

SCK2

8PB

6/TP14/

TxD2

PB6/TP14/

TxD2

PB6/TP14/

TxD2

PB6/TP14/

TxD2

PB6/TP14/

TxD2

PB6/TP14/

TxD2

PB6/TP14/

TxD2

9PB

7/TP15/

RxD2

PB7/TP15/

RxD2

PB7/TP15/

RxD2

PB7/TP15/

RxD2

PB7/TP15/

RxD2

PB7/TP15/

RxD2

PB7/TP15/

RxD2

10 FWE FWE FWE FWE FWE FWE FWE

11 VSS VSS VSS VSS VSS VSS VSS

12 P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0

13 P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1

14 P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0

15 P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1

16 P94/

IRQ

SCK0

P94/

IRQ

SCK0

P94/

IRQ

SCK0

P94/

IRQ

SCK0

P94/

IRQ

SCK0

P94/

IRQ

SCK0

P94/

IRQ

SCK0

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 14 of 910

REJ09B0258-0300

Pin No. Pin Name

FP-100B

TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

17 P95/

IRQ

SCK1

P95/

IRQ

SCK1

P95/

IRQ

SCK1

P95/

IRQ

SCK1

P95/

IRQ

SCK1

P95/

IRQ

SCK1

P95/

IRQ

SCK1

18 P40/D0*2P40/D0*3P40/D0*2P40/D0*3P40/D0*2P40P40

19 P41/D1*2P41/D1*3P41/D1*2P41/D1*3P41/D1*2P41P41

20 P42/D2*2P42/D2*3P42/D2*2P42/D2*3P42/D2*2P42P42

21 P43/D3*2P43/D3*3P43/D3*2P43/D3*3P43/D3*2P43P43

22 VSS VSS VSS VSS VSS VSS VSS

23 P44/D4*2P44/D4*3P44/D4*2P44/D4*3P44/D4*2P44P44

24 P45/D5*2P45/D5*3P45/D5*2P45/D5*3P45/D5*2P45P45

25 P46/D6*2P46/D6*3P46/D6*2P46/D6*3P46/D6*2P46P46

26 P47/D7*2P47/D7*3P47/D7*2P47/D7*3P47/D7*2P47P47

27 D8D8D8D8D8P30P30

28 D9D9D9D9D9P31P31

29 D10 D10 D10 D10 D10 P32P32

30 D11 D11 D11 D11 D11 P33P33

31 D12 D12 D12 D12 D12 P34P34

32 D13 D13 D13 D13 D13 P35P35

33 D14 D14 D14 D14 D14 P36P36

34 D15 D15 D15 D15 D15 P37P37

35 VCC VCC VCC VCC VCC VCC VCC

36 A0A0A0A0P10/A0P10P10

37 A1A1A1A1P11/A1P11P11

38 A2A2A2A2P12/A2P12P12

39 A3A3A3A3P13/A3P13P13

40 A4A4A4A4P14/A4P14P14

41 A5A5A5A5P15/A5P15P15

42 A6A6A6A6P16/A6P16P16

43 A7A7A7A7P17/A7P17P17

44 VSS VSS VSS VSS VSS VSS VSS

45 A8A8A8A8P20/A8P20P20

46 A9A9A9A9P21/A9P21P21

47 A10 A10 A10 A10 P22/A10 P22P22

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 15 of 910

REJ09B0258-0300

Pin No. Pin Name

FP-100B

TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

48 A11 A11 A11 A11 P23/A11 P23P23

49 A12 A12 A12 A12 P24/A12 P24P24

50 A13 A13 A13 A13 P25/A13 P25P25

51 A14 A14 A14 A14 P26/A14 P26P26

52 A15 A15 A15 A15 P27/A15 P27P27

53 A16 A16 A16 A16 P50/A16 P50P50

54 A17 A17 A17 A17 P51/A17 P51P51

55 A18 A18 A18 A18 P52/A18 P52P52

56 A19 A19 A19 A19 P53/A19 P53P53

57 VSS VSS VSS VSS VSS VSS VSS

58 P60/

WAIT

P60/

WAIT

P60/

WAIT

P60/

WAIT

P60/

WAIT

P60P60

59 P61/

BREQ

P61/

BREQ

P61/

BREQ

P61/

BREQ

P61/

BREQ

P61P61

60 P62/

BACK

P62/

BACK

P62/

BACK

P62/

BACK

P62/

BACK

P62P62

61 φφφ φP67/φP67/φP67/φ

STBY STBY STBY STBY STBY STBY STBY

RES RES RES RES RES RES RES

64 NMI NMI NMI NMI NMI NMI NMI

65 VSS VSS VSS VSS VSS VSS VSS

66 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL

67 XTAL XTAL XTAL XTAL XTAL XTAL XTAL

68 VCC VCC VCC VCC VCC VCC VCC

AS AS AS AS AS

P63P63

RD RD RD RD RD

P64P64

HWR HWR HWR HWR HWR

P65P65

LWR LWR LWR LWR LWR

P66P66

73 MD0MD0MD0MD0MD0MD0MD0

74 MD1MD1MD1MD1MD1MD1MD1

75 MD2MD2MD2MD2MD2MD2MD2

76 AVCC AVCC AVCC AVCC AVCC AVCC AVCC

77 VREF VREF VREF VREF VREF VREF VREF

78 P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0

79 P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 16 of 910

REJ09B0258-0300

Pin No. Pin Name

FP-100B

TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

80 P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2

81 P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3

82 P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4

83 P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5

84 P76/AN6/

DA0

P76/AN6/

DA0

P76/AN6/

DA0

P76/AN6/

DA0

P76/AN6/

DA0

P76/AN6/

DA0

P76/AN6/

DA0

85 P77/AN7/

DA1

P77/AN7/

DA1

P77/AN7/

DA1

P77/AN7/

DA1

P77/AN7/

DA1

P77/AN7/

DA1

P77/AN7/

DA1

86 AVSS AVSS AVSS AVSS AVSS AVSS AVSS

87 P80/

IRQ

RFSH

P80/

IRQ

RFSH

P80/

IRQ

RFSH

P80/

IRQ

RFSH

P80/

IRQ

RFSH

P80/

IRQ

0P80/

IRQ

88 P81/

IRQ

P81/

IRQ

P81/

IRQ

P81/

IRQ

P81/

IRQ

P81/

IRQ

1P81/

IRQ

89 P82/

IRQ

P82/

IRQ

P82/

IRQ

P82/

IRQ

P82/

IRQ

P82/

IRQ

2P82/

IRQ

90 P83/

IRQ

ADTRG

P83/

IRQ

ADTRG

P83/

IRQ

ADTRG

P83/

IRQ

ADTRG

P83/

IRQ

ADTRG

P83/

IRQ

ADTRG

P83/

IRQ

ADTRG

91 P84/

0P84/

0P84P84

92 VSS VSS VSS VSS VSS VSS VSS

93 PA0/TP0/

TCLKA/

TEND

PA0/TP0/

TCLKA/

TEND

PA0/TP0/

TCLKA/

TEND

PA0/TP0/

TCLKA/

TEND

PA0/TP0/

TCLKA/

TEND

PA0/TP0/

TCLKA/

TEND

PA0/TP0/

TCLKA/

TEND

94 PA1/TP1/

TCLKB/

TEND

PA1/TP1/

TCLKB/

TEND

PA1/TP1

/TCLKB/

TEND

PA1/TP1/

TCLKB/

TEND

PA1/TP1/

TCLKB/

TEND

PA1/TP1/

TCLKB/

TEND

PA1/TP1/

TCLKB/

TEND

95 PA2/TP2/

TIOCA0/

TCLKC

PA2/TP2/

TIOCA0/

TCLKC

PA2/TP2/

TIOCA0/

TCLKC

PA2/TP2/

TIOCA0/

TCLKC

PA2/TP2/

TIOCA0/

TCLKC

PA2/TP2/

TIOCA0/

TCLKC

PA2/TP2/

TIOCA0/

TCLKC

96 PA3/TP3/

TIOCB0/

TCLKD

PA3/TP3/

TIOCB0/

TCLKD

PA3/TP3/

TIOCB0/

TCLKD

PA3/TP3/

TIOCB0/

TCLKD

PA3/TP3/

TIOCB0/

TCLKD

PA3/TP3/

TIOCB0/

TCLKD

PA3/TP3/

TIOCB0/

TCLKD

97 PA4/TP4/

TIOCA1

PA4/TP4/

TIOCA1

PA4/TP4/

TIOCA1/

A23

PA4/TP4/

TIOCA1/

A23

PA4/TP4/

TIOCA1/

A23

PA4/TP4/

TIOCA1

PA4/TP4/

TIOCA1

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 17 of 910

REJ09B0258-0300

Pin No. Pin Name

FP-100B

TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

98 PA5/TP5/

TIOCB1

PA5/TP5/

TIOCB1

PA5/TP5/

TIOCB1/

A22

PA5/TP5/

TIOCB1/

A22

PA5/TP5/

TIOCB1/

A22

PA5/TP5/

TIOCB1

PA5/TP5/

TIOCB1

99 PA6/TP6/

TIOCA2

PA6/TP6/

TIOCA2

PA6/TP6/

TIOCA2/

A21

PA6/TP6/

TIOCA2/

A21

PA6/TP6/

TIOCA2/

A21

PA6/TP6/

TIOCA2

PA6/TP6/

TIOCA2

100 PA7/TP7/

TIOCB2

PA7/TP7/

TIOCB2

A20 A20 PA7/TP7/

TIOCB2/

A20

PA7/TP7/

TIOCB2

PA7/TP7/

TIOCB2

Notes: 1. Functions as VCL pin.

2. In modes 1, 3, 5 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected after a

reset, but they can be changed by software.

3. In modes 2 and 4 the D0 to D7 functions of pins P40/D0 to P47/D7 are selected after a

reset, but they can be changed by software.

Section 1 Overview

Rev. 3.00 Sep 14, 2005 page 18 of 910

REJ09B0258-0300

Section 2 CPU

Rev. 3.00 Sep 14, 2005 page 19 of 910

REJ09B0258-0300

Section 2 CPU

2.1 Overview

The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that

is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general

registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

2.1.1 Features

The H8/300H CPU has the following features.

• Upward compatibility with H8/300 CPU

Can execute H8/300 Series object programs

• General-register architecture

Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)

• Sixty-two basic instructions

 8/16/32-bit arithmetic and logic instructions

 Multiply and divide instructions

 Powerful bit-manipulation instructions

• Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, or @aa:24]

 Immediate [#xx:8, #xx:16, or #xx:32]

 Program-counter relative [@(d:8, PC) or @(d:16, PC)]

 Memory indirect [@@aa:8]

• 16-Mbyte linear address space

Section 2 CPU

Rev. 3.00 Sep 14, 2005 page 20 of 910

REJ09B0258-0300

• High-speed operation

 All frequently-used instructions execute in two to four states

 Maximum clock frequency: 25 MHz

 8/16/32-bit register-register add/subtract: 80 ns

 8 × 8-bit register-register multiply: 560 ns

 16 ÷ 8-bit register-register divide: 560 ns

 16 × 16-bit register-register multiply: 880 ns

 32 ÷ 16-bit register-register divide: 880 ns

• Two CPU operating modes

 Normal mode

 Advanced mode

• Low-power mode

Transition to power-down state by SLEEP instruction

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8/300H has the following enhancements.

• More general registers

Eight 16-bit registers have been added.

• Expanded address space

 Advanced mode supports a maximum 16-Mbyte address space.

 Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

• Enhanced addressing

The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions

 Data transfer, arithmetic, and logic instructions can operate on 32-bit data.

 Signed multiply/divide instructions and other instructions have been added.

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2.2 CPU Ope rati ng Modes

The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a

maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes.

CPU operating modes

Normal mode

Advanced mode

Maximum 64 kbytes, program

and data areas combined

Maximum 16 Mbytes, program

and data areas combined

Figure 2.1 CPU Operating Modes

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2.3 Address Space

Figure 2.2 shows a simple memory map for the H8/3068F. The H8/300H CPU can address a

linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in

advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.

The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are

ignored.

H'00000

H'FFFFF

H'000000

H'FFFFFF

a. 1-Mbyte mode b. 16-Mbyte mode

H'0000

H'FFFF

Advanced modeNormal mode

Figure 2.2 Memory Map

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2.4 Register Configuration

2.4.1 Overview

The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers:

general registers and control registers.

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

0707015

(SP)

23 0

CCR 6543210

IUIHUNZVC

General Registers (ERn)

Control Registers (CR)

Legend

SP:

PC:

CCR:

UI:

Stack pointer

Program counter

Condition code register

Interrupt mask bit

User bit or interrupt mask bit

Half-carry flag

User bit

Negative flag

Zero flag

Overflow flag

Carry flag

Figure 2.3 CPU Registers

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2.4.2 General Registers

The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally

alike and can be used without distinction between data registers and address registers. When a

general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.

When the general registers are used as 32-bit registers or as address registers, they are designated

by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R

(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit

registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and

RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit

registers.

Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected

independently.

• Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

ER registers

ER0 to ER7

E registers

(extended registers)

E0 to E7

R registers

R0 to R7

RH registers

R0H to R7H

RL registers

R0L to R7L

Figure 2.4 Usage of General Registers

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General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the

stack.

Free area

Stack area

SP (ER7)

Figure 2.5 Stack

2.4.3 Control Registers

The control registers are the 24-bit program counter (PC) and the 8-bit condition code register

(CCR).

Program Counter (PC): This 24-bit counter indicates the address of the next instruction the

CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least

significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is

regarded as 0.

Condition Code Register (CCR): This 8-bit register contains internal CPU status information,

including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and

carry (C) flags.

Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted

regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.

Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the

LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask

bit. For details see section 5, Interrupt Controller.

Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B

instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0

otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is

set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,

SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or

borrow at bit 27, and cleared to 0 otherwise.

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Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC,

and XORC instructions.

Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the

sign bit.

Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at

other times.

Bit 0—Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and

cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,

STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional

branch (Bcc) instructions.

For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and

UI bits, see section 5, Interrupt Controller.

2.4.4 Initial CPU Register Values

In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit

in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular,

the initial value of the stack pointer (ER7) is also undefined. The stack pointer (ER7) must

therefore be initialized by an MOV.L instruction executed immediately after a reset.

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2.5 Data Formats

The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit

(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1,

2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as

two digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figures 2.6 and 2.7 show the data formats in general registers.

RnH

RnL

RnH

RnL

RnH

RnL

1-bit data

4-bit BCD data

Byte data

6543210

Don’t care

76543210

Don’t care

Lower digitUpper digit

743

Lower digitUpper digit

Don’t care 0

Don’t care

MSB LSB

Don’t care 70

MSB LSB

Data Type Data Format

General

RnH:

RnL: General register RH

General register RL

Legend

Figure 2.6 General Register Data Formats

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ERn

Word data

Longword data

15 0

MSB LSB

General

RegisterData Type Data Format

15 0

MSB LSB

31 16

MSB

15 0

Legend

ERn:

En:

Rn:

MSB:

LSB:

General register

General register E

General register R

Most significant bit

Least si

nificant bit

Figure 2.7 General Register Data Formats

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2.5.2 Memory Data Formats

Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and

longword data on memory, but word or longword data must begin at an even address. If an

attempt is made to access word or longword data at an odd address, no address error occurs but

the least significant bit of the address is regarded as 0, so the access starts at the preceding

address. This also applies to instruction fetches.

76543210Address L

Address L

LSB

MSB

LSB

MSB LSB

1-bit data

Byte data

Word data

Longword data

AddressData Type Data Format

Address 2M

Address 2M + 1

Address 2N

Address 2N + 1

Address 2N + 2

Address 2N + 3

Figure 2.8 Memory Data Formats

When ER7 (SP) is used as an address register to access the stack, the operand size should be word

size or longword size.

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2.6 I nstruction Set

2.6.1 Instruction Set Overview

The H8/300H CPU has 62 types of instructions, which are classified in table 2.1.

Table 2.1 Instruction Classification

Function Instruction Types

Data transfer MOV, PUSH*1, POP*1, MOVTPE*2, MOVFPE*23

Arithmetic operati ons ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS,

MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU 18

Logic operations AND, OR, XOR, NOT 4

Shift operations SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8

Bit manipu lation BSET, BCLR, BNOT, BTST, BAND, BI AND, BOR, BIOR, BXOR,

BIXOR, BLD, BILD, BST, BIST 14

Branch Bcc*3, JMP, BSR, JSR, RTS 5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9

Block d ata transfer EEPMOV 1

Total 62 types

Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.

PUSH.W Rn is identical to MOV.W Rn, @–SP.

POP.L ERn is identical to MOV.L @SP+, Rn.

PUSH.L ERn is identical to MOV.L Rn, @–SP.

2. Not available in the H8/3068F.

3. Bcc is a generic branching instruction.

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2.6.2 Instructions and Addressing Modes

Table 2.2 indicates the instructions available in the H8/300H CPU.

Table 2.2 Instructions and Addressing Modes

Addressing Modes

Function Instruction #xx Rn @ERn

(d:16,

ERn)

(d:24,

ERn) @ERn+/

@–ERn @

aa:8 @

aa:16 @

aa:24

(d:8,

PC)

(d:16,

PC) @@

aa:8 —

MOV BWL BWL BWL BWL BWL BWL B BWL BWL ————Data

transfer POP, PUSH —————— ——————WL

MOVFPE, —————— ———————

MOVTPE

ADD, CMP BWL BWL ———— ———————

Arithmetic

operations SUB WL BWL ———— ———————

ADDX, SUBX B B ———— ———————

ADDS, SUBS — L ———— ———————

INC, DEC —BWL ———— ———————

DAA, DAS — B ———— ———————

MULXU, —BW ———— ———————

MULXS,

DIVXU,

DIVXS

NEG —BWL ———— ———————

EXTU, EXTS —WL ———— ———————

AND, OR, XOR —BWL ———— ———————Logic

operations NOT —BWL ———— ———————

Shift instructions —BWL ———— ———————

Bit manipulation —BB——— B——————

Branch Bcc, BSR —————— ———————

JMP , JSR —— ——— ——— ——

RTS —————— —— —— —

TRAPA —————— ——————System

control RTE —————— ——————

SLEEP —————— ——————

LDC BBWWWW —WW———

STC —B WWWW —WW————

ANDC, ORC,

XORC B————— ———————

NOP —————— ——————

Block data transfer —————— ——————BW

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2.6.3 Tables of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation

used in these tables is defined next.

Operation Notation

Rd General regi ster (destination) *

Rs General regi ster (source)*

Rn General regi ster*

ERn General register (32-bit register or address register)

(EAd) Destination operand

(EAs) Source operand

CCR Conditi on code register

N N (negative) flag of CCR

Z Z (zero) flag of CCR

V V (overflow) flag of CCR

C C (carry) flag of CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

–Subtraction

×Multiplication

÷Division

∧AND logical

∨OR logical

⊕Exclusi ve OR logical

→Move

¬NOT (logical complement)

:3/:8/:16/:24 3-, 8-, 16-, or 24-bit l ength

Note: *General regi sters include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).

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Table 2.3 Data Transfer Instructions

Instruction Size*Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register and

memory, or moves immediate data to a general register.

MOVFPE B (EAs) → Rd

Cannot be used in this LSI.

MOVTPE B Rs → (EAs)

Cannot be used in this LSI.

POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to MOV.W

@SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W

Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @–SP.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

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Table 2.4 Arithmetic Operation Instructions

Instruction Size*Function

ADD,SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on

immediate data and data in a general register. (Immediate byte data cannot

be subtracted from data in a general register. Use the SUBX or ADD

instruction.)

ADDX,

SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on data in two general

registers, or on i mmediate data and data in a general register.

INC,

DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands can

be incremented or decremented by 1 only.)

ADDS,

SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bi t register.

DAA,

DAS B Rd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a general register by

referring to CCR to produce 4-bit BCD data.

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general registers:

either 8 bi ts × 8 bits → 16 bits or 16 bi ts × 16 bits → 32 bits.

MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general registers:

either 8 bi ts × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

DIVXU B/W Rd ÷ Rs → Rd

Performs unsi gned division on data in two general registers: either 16 bits ÷

8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit

quotient and 16-bi t remainder

DIVXS B/W Rd ÷ Rs → Rd

Performs si gned division on data in two general registers: either 16 bits ÷ 8

bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit

quotient and 16-bi t remainder

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register or

with immediate data, and sets CCR according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two’s complement (arithmetic complement) of data in a general

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Instruction Size*Function

EXTS W/L Rd (sign extension) → Rd

Extends byte data in the lower 8 bits of a 16-bit register to word data, or

extends word data i n the lower 16 bits of a 32-bit register to longword data,

by extending the sign bit.

EXTU W/L Rd (zero extension) → Rd

Extends byte data in the lower 8 bits of a 16-bit register to word data, or

extends word data i n the lower 16 bits of a 32-bit register to longword data,

by padding with zeros.

Note: * Size refers to the operand size.

B: Byte

W: Word

L: Longword

Table 2.5 Logic Operation Instructions

Instruction Size*Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another general

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #I MM → Rd

Performs a logical OR operati on on a general register and another general

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general regi ster and another

general regi ster or immediate data.

NOT B/W/L ¬ Rd → Rd

Takes the one's complement (logical complement) of general register

contents.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

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Table 2.6 Shift Instructions

Instruction Size*Function

SHAL,

SHAR B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.

SHLL,

SHLR B/W/L Rd (shift) → Rd

Performs a l ogical shift on general register contents.

ROTL,

ROTR B/W/L Rd (rotate) → Rd

Rotates general register contents.

ROTXL,

ROTXR B/W/L Rd (rotate) → Rd

Rotates general register contents, including the carry bit.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

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Table 2.7 Bit Manipulation Instructions

Instruction Size*Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit

number is specified by 3-bit i mmediate data or the lower 3 bits of a general

BCLR B 0 → (<bi t-No.> of <EAd>)

Clears a specified bit in a general regi ster or memory operand to 0. The bit

number is specified by 3-bit i mmediate data or the lower 3 bits of a general

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit

number is specified by 3-bit i mmediate data or the lower 3 bits of a general

BTST B ¬ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets or

clears the Z fl ag accordingly. The bit number is specified by 3-bit immediate

data or the lower 3 bits of a general register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general regi ster or memory

operand and stores the result in the carry flag.

BIAND B C ∧ [¬ (<bit-No.> of <EAd>)] → C

ANDs the carry flag with the inverse of a specified bit in a general register or

memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BOR B C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general register or memory

operand and stores the result in the carry flag.

BIOR B C ∨ [¬ (<bit-No.> of <EAd>)] → C

ORs the carry flag with the inverse of a speci fied bit in a general register or

memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag with a specified bit in a general register or

memory operand and stores the result in the carry flag.

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Instruction Size*Function

BIXOR B C ⊕ [¬ (<bit-No.> of <EAd>)] → C

Exclusive-ORs the carry flag with the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory operand to the carry

flag.

BILD B ¬ (<bit-No.> of <EAd>) → C

Transfers the inverse of a speci fied bit in a general register or memory

operand to the carry flag.

The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag val ue to a specified bit in a general register or

memory operand.

BIST B C → ¬ (<bit-No.> of <EAd>)

Transfers the inverse of the carry fl ag value to a specified bit in a general

The bit number is specified by 3-bit immediate data.

Note: *Size refers to the operand size.

B: Byte

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Table 2.8 Branching Instructions

Instruction Size Function

Bcc —Branches to a specified address if address specified condition is met. The

branching condi tions are listed below.

Mnemonic Description Condition

BRA (BT ) Always (true) Always

BRN (BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

Bcc (BHS) Carry clear (high or same) C = 0

BCS (BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z ∨ (N ⊕ V) = 0

BLE Less or equal Z ∨ (N ⊕ V) = 1

JMP — Branches unconditionally to a specified address

BSR —Branches to a subroutine at a specified address

JSR — Branches to a subroutine at a specified address

RTS —Returns from a subroutine

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Table 2.9 System Control Instructions

Instruction Size*Function

TRAPA —Starts trap-instruction exception handling

RTE —Returns from an exception-handling routine

SLEEP —Causes a transition to the power-down state

LDC B/W (EAs) → CCR

Moves the source operand contents to the condition code regi ster. The

conditi on code register size is one byte, but in transfer from memory, data is

read by word access.

STC B/W CCR → (EAd)

Transfers the CCR contents to a desti nation location. The condition code

access.

ANDC B CCR ∧ #IMM → CCR

Logical ly ANDs the condition code register with i mmediate data.

ORC B CCR ∨ #IMM → CCR

Logical ly ORs the condition code register with immediate data.

XORC B CCR ⊕ #IMM → CCR

Logical ly exclusive-ORs the condition code register with immediate data.

NOP — PC + 2 → PC

Only increments the program counter.

Note: *Size refers to the operand size.

B: Byte

W: Word

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Table 2.10 Block Transfer Instruction

Instruction Size Function

EEPMOV.B —if R4L

≠

0 then

repeat @ER5+ → @ER6+, R4L – 1 → R4L

until R4L = 0

else next;

EEPMOV.W —if R4

≠

0 then

repeat @ER5+ → @ER6+, R4 – 1 → R4

until R4 = 0

else next;

Block transfer instruction. This i nstruction transfers the number of data bytes

specifi ed by R4L or R4, starting from the address indicated by ER5, to the

location starting at the address indicated by ER6. At the end of the transfer,

the next instruction is executed.

2.6.4 Basic Instruction Formats

The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an

operation field (OP field), a register field (r field), an effective address extension (EA field), and a

condition field (cc).

Operation Field: Indicates the function of the instruction, the addressing mode, and the

operation to be carried out on the operand. The operation field always includes the first 4 bits of

the instruction. Some instructions have two operation fields.

registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register

field.

Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute

address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the

first 8 bits are 0 (H'00).

Condition Field: Specifies the branching condition of Bcc instructions.

Figure 2.9 shows examples of instruction formats.

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op NOP, RTS, etc.

op rn rm

EA (disp)

Operation field only

ADD.B Rn, Rm, etc.

Operation field and register fields

MOV.B @(d:16, Rn), Rm

Operation field, register fields, and effective address extension

BRA d:8

Operation field, effective address extension, and condition field

op cc EA (disp)

Figure 2.9 Instruction Formats

2.6.5 Notes on Use of Bit Manipulation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the

byte, then write the byte back. Care is required when these instructions are used to access

registers with write-only bits, or to access ports.

Step Description

1 Read Read one data byte at the specified address

2 Modify Modify one bit in the data byte

3 Write W rite the modified data byte back to the specified address

Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under

the following conditions.

P47, P46: Input pins

P45 – P40: Output pins

The intended purpose of this BCLR instruction is to switch P40 from output to input.

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Before Execution of BCLR Instruction

P47P46P45P44P43P42P41P40

Input/output Input Input Output Output Output Output Output Output

DDR 00111111

Execution of BCLR Instruction

BCLR #0, @P4DDR ;Clear bit 0 in data direction register

After Execution of BCLR Instruction

P47P46P45P44P43P42P41P40

Input/output Output Output Output Output Output Output Output Input

DDR 11111110

Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since

P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.

Next the CPU clears bit 0 of the read data, changing the value to H'FE.

Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.

As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR

are set to 1, making P47 and P46 output pins.

The BCLR instruction can be used to clear flags in the on-chip registers to 0. In an interrupt-

handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the

flag ahead of time.

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2.7 Addr essing Modes and Ef fec tive Address Calculati on

2.7.1 Addressing Modes

The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses

a subset of these addressing modes. Arithmetic and logic instructions can use the register direct

and immediate modes. Data transfer instructions can use all addressing modes except program-

counter relative and memory indirect. Bit manipulation instructions use register direct, register

indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,

BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit

number in the operand.

Table 2.11 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16, ERn)/@(d:24, ERn)

4 Register indirect with post-increment

@–ERn

5 Absolute address @aa:8/@aa:16/@aa:24

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8, PC)/@(d:16, PC)

8 Memory indirect @@aa:8

1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit

R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit

registers.

2 Register Indirect—@ERn: The register field of the instruction code specifies an address

3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit

displacement contained in the instruction code is added to the contents of an address register

(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify

the address of a memory operand. A 16-bit displacement is sign-extended when added.

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4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn) the lower 24 bits

of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is

added to the address register contents (32 bits) and the sum is stored in the address register.

The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or

longword access, the register value should be even.

• Register indirect with pre-decrement—@–ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instruction code, and the lower 24 bits of the result become the address of a memory

operand. The result is also stored in the address register. The value subtracted is 1 for byte

access, 2 for word access, or 4 for longword access. For word or longword access, the

resulting register value should be even.

5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute

address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long

(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all

assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A

24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible

address ranges.

Table 2.12 Absolute Address Access Ranges

Absolute

Address 1-Mbyte Modes 16-Mbyte Modes

8 bits (@aa:8) H'FFF00 to H'FFFFF

(1048320 to 1048575) H'FFFF00 to H'FFFFFF

(16776960 to 16777215)

16 bits (@aa:16) H'00000 to H'07FFF,

H'F8000 to H'FFFFF

(0 to 32767, 1015808 to 1048575)

H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

(0 to 32767, 16744448 to 16777215)

24 bits (@aa:24) H'00000 to H'FFFFF

(0 to 1048575) H'000000 to H'FFFFFF

(0 to 16777215)

6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit

(#xx:16), or 32-bit (#xx:32) immediate data as an operand.

The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data

implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate

data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data

specifying a vector address.

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7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and

BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-

extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The

PC value to which the displacement is added is the address of the first byte of the next instruction,

so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to

+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should

be an even number.

8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

instruction code contains an 8-bit absolute address specifying a memory operand. This memory

operand contains a branch address. The memory operand is accessed by longword access. The

first byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10.

The upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is

0 to 255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector

area. For further details see section 5, Interrupt Controller.

Specified by @aa:8 Reserved

Branch address

Figure 2.10 Memory-Indirect Branch Address Specification

When a word-size or longword-size memory operand is specified, or when a branch address is

specified, if the specified memory address is odd, the least significant bit is regarded as 0. The

accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,

Memory Data Formats.

2.7.2 Effective Address Calculation

Table 2.13 explains how an effective address is calculated in each addressing mode. In the

1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to

generate a 20-bit effective address.

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Table 2.13 Effective Address Calculation

Addressing Mode and

Instruction FormatNo. Effective Address Calculation Effective Address

1Operand is general

op rm rn

op r

General register contents

31 0 23 0

@(d:16, ERn)/@(d:24, ERn)

op r

General register contents

31 0

23 0

Sign extension disp

or pre-decrement

General register contents

31 0 23 0

1, 2, or 4

op r

General register contents

31 0

23 0

1, 2, or 4

op r

@ERn+

@–ERn

1 for a byte operand,

2 for a word operand,

4 for a longword operand

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Addressing Mode and

Instruction FormatNo. Effective Address Calculation Effective Address

Absolute address

@aa:8

Program-counter relative

@(d:8, PC) or @(d:16, PC)

23 0

abs

23 087

@aa:16

@aa:24

op abs

23 016 15

H'FFFF

Sign

extension

23 0

abs

Immediate

#xx:8, #xx:16, or #xx:32

6Operand is immediate data

op disp

23 0

PC contents

disp

op IMM

Sign

extension

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Addressing Mode and

Instruction FormatNo. Effective Address Calculation Effective Address

Legend

r, rm, rn:

op:

disp:

IMM:

abs:

Operation field

Displacement

Immediate data

Absolute address

Memory indirect @@aa:8

23 0

abs 23 087

H'0000

15 0

abs

16 15

Normal mode

23 0

abs 23 087

H'0000

abs

Advanced mode

H'00Memory contents

Memory contents

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2.8 Processing States

2.8.1 Overview

The H8/300H CPU has five processing states: the program execution state, exception-handling

state, power-down state, reset state, and bus-released state. The power-down state includes sleep

mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing

states. Figure 2.13 indicates the state transitions.

Processing states Program execution state

Bus-released state

Reset state

Power-down state

The CPU executes program instructions in sequence

A transient state in which the CPU executes a hardware sequence

(saving PC and CCR, fetching a vector, etc.) in response to a reset,

interrupt, or other exception

The external bus has been released in response to a bus request

signal from a bus master other than the CPU

The CPU and all on-chip supporting modules are initialized and halted

The CPU is halted to conserve power

Sleep mode

Software standby mode

Hardware standby mode

Exception-handling state

Figure 2.11 Processing States

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2.8.2 Program Execution State

In this state the CPU executes program instructions in normal sequence.

2.8.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address

from the exception vector table and branches to that address. In interrupt and trap exception

handling the CPU references the stack pointer (ER7) and saves the program counter and

condition code register.

Types of Exception Handling and Their Priority: Exception handling is performed for resets,

interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their

priority. Trap instruction exceptions are accepted at all times in the program execution state.

Table 2.14 Exception Handling Types and Priority

Priority Type of Exception Detection Timing Start of Exception Handling

High Reset Synchronized with clock Exception handling starts immediately

when RES changes from low to high

Interrupt End of instruction

execution or end of

exception handling*

When an interrupt is requested,

exception handling starts at the end of

the current instruction or current

exception-handling sequence

Low Trap instruction When TRAPA instruction

is executed Exception handling starts when a trap

(TRAPA) instruction is executed

Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,

or immediatel

after reset exception handlin

Figure 2.12 classifies the exception sources. For further details about exception sources, vector

numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt

Controller.

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Exception

sources

Reset

Interrupt

Trap instruction

External interrupts

Internal interrupts (from on-chip supporting modules)

Figure 2.12 Classification of Exception Sources

Bus-released state

Exception-handling state

Reset state

Program execution state

Sleep mode

Software standby mode

Hardware standby mode

Power-down state

Bus request

End of bus release

End of bus

release Bus

request

End of

exception

handling

Exception

handling source

Interrupt source

SLEEP

instruction

with SSBY = 0

SLEEP instruction

with SSBY = 1

NMI, IRQ , IRQ ,

or IRQ interrupt

STBY="High", RES ="Low"

RES = "High"

*1*2

Notes: 1.

From any state except hardware standby mode, a transition to the reset state occurs

whenever goes low.

From any state, a transition to hardware standby mode occurs when goes low.

RES

STBY

Figure 2.13 State Transitions

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2.8.4 Exception-Handling Sequences

Reset Exception Handling: Reset exception handling has the highest priority. The reset state is

entered when the

RES

signal goes low. Reset exception handling starts after that, when

RES

changes from low to high. When reset exception handling starts the CPU fetches a start address

from the exception vector table and starts program execution from that address. All interrupts,

including NMI, are disabled during the reset exception-handling sequence and immediately after

it ends.

Interrupt Exception Handling and Trap Instruction Exception Handling: When these

exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the

program counter and condition code register on the stack. Next, if the UE bit in the system

control register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If

the UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register

to 1. Then the CPU fetches a start address from the exception vector table and execution

branches to that address.

Figure 2.14 shows the stack after the exception-handling sequence.

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SP–4

SP–3

SP–2

SP–1

SP (ER7)

Before exception

handling starts

SP (ER7)

SP+1

SP+2

SP+3

SP+4

After exception

handling ends

Stack area

CCR

Even

addres

Pushed on stack

Legend

CCR:

SP: Condition code register

Stack pointer

Notes: 1.

PC is the address of the first instruction executed after the return from the

exception-handling routine.

Registers must be saved and restored by word access or longword access,

starting at an even address.

Figure 2.14 Stack Structure after Exception Handling

2.8.5 Bus-Released State

In this state the bus is released to a bus master other than the CPU, in response to a bus request.

The bus masters other than the CPU are the DMA controller, the DRAM interface, and an

external bus master. While the bus is released, the CPU halts except for internal operations.

Interrupt requests are not accepted. For details see section 6.10, Bus Arbiter.

2.8.6 Reset State

When the

RES

input goes low all current processing stops and the CPU enters the reset state. The

I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset

state. Reset exception handling starts when the

RES

signal changes from low to high.

The reset state can also be entered by a watchdog timer overflow. For details see section 12,

Watchdog Timer.

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2.8.7 Power-Down State

In the power-down state the CPU stops operating to conserve power. There are three modes:

sleep mode, software standby mode, and hardware standby mode.

Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the

SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop

immediately after execution of the SLEEP instruction, but the contents of CPU registers are

retained.

Software Standby Mode: A transition to software standby mode is made if the SLEEP

instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all

on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long

as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.

The I/O ports also remain in their existing states.

Hardware Standby Mode: A transition to hardware standby mode is made when the

STBY

input goes low. As in software standby mode, the CPU and all clocks halt and the on-chip

supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM

contents are retained.

For further information see section 20, Power-Down State.

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2.9 Basic Operational Timing

2.9.1 Overview

The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the

system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of

two or three states. The CPU uses different methods to access on-chip memory, the on-chip

supporting modules, and the external address space. Access to the external address space can be

controlled by the bus controller.

2.9.2 On-Chip Memory Access Timing

On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and

word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin

states.

T state

Bus cycle

Internal address bus

Internal read signal

Internal data bus

(read access)

Internal write signal

Internal data bus

(write access)

T state

Read data

Address

Write data

Figure 2.15 On-Chip Memory Access Cycle

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, , ,AS

Address bus

D to D

15 0

RD HWR LWR High

Address

High impedance

Figure 2.16 Pin States during On-Chip Memory Access

2.9.3 On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,

depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting

module access timing. Figure 2.18 indicates the pin states.

Address bus

Internal read signal

Internal data bus

Internal write signal

Address

Internal data bus

T state

Bus cycle

T state

Read

access

Write

access Write data

Read data

Figure 2.17 Access Cycle for On-Chip Supporting Modules

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, , ,AS

Address bus

D to D

15 0

RD HWR LWR High

High impedance

Address

Figure 2.18 Pin States during Access to On-Chip Supporting Modules

2.9.4 Access to External Address Space

The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings

determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in

two or three states. For details see section 6, Bus Controller.

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Sectio n 3 MCU Operating Mo des

3.1 Overview

3.1.1 Operating Mode Selection

The H8/3068F has seven operating modes (modes 1 to 7) that are selected by the mode pins (MD2

to MD0) as indicated in table 3.1. The input at these pins determines the size of the address space

and the initial bus mode.

Table 3.1 Operating Mode Selection

Description

Operating Mode Pins Initial Bus On-Chip On-Chip

Mode MD2MD1MD0Address Space Mode*1ROM RAM

—000— ———

Mode 1 0 0 1 Expanded mode 8 bits Disabl ed Enabled*2

Mode 2 0 1 0 Expanded mode 16 bits Disabled Enabled*2

Mode 3 0 1 1 Expanded mode 8 bits Disabl ed Enabled*2

Mode 4 1 0 0 Expanded mode 16 bits Disabled Enabled*2

Mode 5 1 0 1 Expanded mode 8 bits Enabled Enabled*2

Mode 6 1 1 0 Single-chip normal mode — Enabled Enabled

Mode 7 1 1 1 Single-chip advanced

mode — Enabled Enabled

Notes: 1. In modes 1 to 5, an 8-bit or 16-bit data bus can be selected on a per-area basis by

settings made in the area bus width control register (ABWCR). For detail s see

section 6, Bus Controller.

2. If the RAME bit in SYSCR is cleared to 0, these addresses become external

addresses.

For the address space size there are three choices: 64 kbytes, 1 Mbyte, or 16 Mbyte.The external

data bus is either 8 or 16 bits wide depending on ABWCR settings. If 8-bit access is selected for

all areas, 8-bit bus mode is used. For details see section 6, Bus Controller.

Modes 1 to 4 are externally expanded modes that enable access to external memory and

peripheral devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum

address space of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes.

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Mode 5 is an externally expanded mode that enables access to external memory and peripheral

devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space

of 16 Mbytes.

Modes 6 and 7 are single-chip modes that operate using the on-chip ROM, RAM, and registers,

and makes all I/O ports available. Mode 6 supports a maximum address space of 64 kbytes. Mode

7 supports a maximum address space of 1 Mbyte.

The H8/3068F can be used only in modes 1 to 7. The inputs at the mode pins must select one of

these seven modes. The inputs at the mode pins must not be changed during operation.

3.1.2 Register Configuration

The H8/3068F has a mode control register (MDCR) that indicates the inputs at the mode pins

(MD2 to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers.

Table 3.2 Registers

Address*Name Abbreviation R/W Initial Value

H'EE011 Mode control register MDCR R Undetermined

H'EE012 System control register SYSCR R/W H'09

Note: *Lower 20 bits of the address in advanced mode.

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3. 2 Mode Control Re gister (MDCR)

MDCR is an 8-bit read-only register that indicates the current operating mode of the

H8/3068F.

Bit

Initial value

Read/Write

—

MDS0

—*

MDS2

—*

MDS1

—*

Reserved bits Mode select 2 to 0

Bits indicating the current

operating mode

Reserved bits

Note: * Determined by pins MD2 to MD0.

Bits 7 and 6—Reserved: These bits can not be modified and are always read as 1.

Bits 5 to 3—Reserved: These bits can not be modified and are always read as 0.

Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins

MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to

MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched into these bits when

MDCR is read.

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3.3 System Contr ol Regi ster (SYSCR)

SYSCR is an 8-bit register that controls the operation of the H8/3068F.

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

SSOE

R/W

Software standby

Enables transition to software standby mode

User bit enable

Selects whether to use the UI bit in CCR

as a user bit or an interrupt mask bit

NMI edge select

Selects the valid edge

of the NMI input

RAM enable

Enables or

disables

on-chip RAM

Standby timer select 2 to 0

These bits select the waiting time at

recovery from software standby mode

Software standby output

port enable

Selects the output state

of the address bus

and bus control signals

in software standby mode

Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further

information about software standby mode see section 20, Power-Down State.)

When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear

this bit, write 0.

Bit 7

SSBY Description

0 SLEEP instruction caus es transition to sleep mode (Initi al value)

1 SLEEP instruction caus es transition to software standby mode

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Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time

the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when

software standby mode is exited by an external interrupt.

When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the

system clock rate.

For further information about waiting time selection, see section 20.4.3, Selection of Waiting

Time for Exit from Software Standby Mode.

Bit 6

STS2 Bit 5

STS1 Bit 4

STS0 Description

0 0 0 Waiting time = 8,192 states (Initi al value)

0 0 1 Waiting time = 16,384 states

0 1 0 Waiting time = 32,768 states

0 1 1 Waiting time = 65,536 states

1 0 0 Waiting time = 131,072 states

1 0 1 Waiting time = 262,144 states

1 1 0 Waiting time = 1,024 states

1 1 1 Illegal setting

Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as

a user bit or an interrupt mask bit.

Bit 3

UE Description

0 UI bit in CCR is used a s an interrupt mask bit

1 UI bit in CCR is used a s a user bit (Initial value)

Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.

Bit 2

NMIEG Description

0 An interrupt is requested at the fal ling edge of NMI (Initi al value)

1 An interrupt is requested at the rising edge of NMI

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Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and

bus control signals (

0 to

HWR

LWR

UCAS

LCAS

, and

RFSH

) are kept as

outputs or fixed high, or placed in the high-impedance state in software standby mode.

Bit 1

SSOE Description

0 In software standby mode, the address bus and bus control signals are all high-

impedance (Initi al value)

1 In software standby mode, the address bus retains its output state and bus control

signal s are fixed high

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized by the rising edge of the

RES

signal. It is not initialized in software standby mode.

Bit 0

RAME Description

0 On-chip RAM is disabled

1 On-chip RAM is enabled (Initi al value)

3.4 O pera ting Mode Descriptions

3.4.1 Mode 1

Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte

address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least

one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.

3.4.2 Mode 2

Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte

address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all

areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.

3.4.3 Mode 3

Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a

maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to

all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to

Section 3 MCU Operating Modes

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16 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register

(BRCR). (In this mode A20 is always used for address output.)

3.4.4 Mode 4

Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a

maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access

to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to

8 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20 is always

used for address output.)

3.4.5 Mode 5

Ports 1, 2, and 5 and part of port A can function as address pins A23 to A0, permitting access to a

maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2,

and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR,

and P5DDR) must be set to 1. For A23 to A20 output, write 0 in bits 7 to 4 of BRCR. The initial

bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for

16-bit access in ABWCR, the bus mode switches to 16 bits.

3.4.6 Mode 6

This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.

Mode 6 supports a maximum address space of 64 kbytes.

3.4.7 Mode 7

This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.

Mode 7 supports a 1-Mbyte address space.

Section 3 MCU Operating Modes

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3.5 P in Functions in E ach Operati ng Mode

The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3

indicates their functions in each operating mode.

Table 3.3 Pin Functions in Each Mode

Port Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

Port 1 A7 to A0A7 to A0A7 to A0A7 to A0P17 to P10*2P17 to P10P17 to P10

Port 2 A15 to A8A15 to A8A15 to A8A15 to A8P27 to P20*2P27 to P20P27 to P20

Port 3 D15 to D8D15 to D8D15 to D8D15 to D8D15 to D8P37 to P30P37 to P30

Port 4 P47 to P40*1D7 to D0*1P47 to P40*1D7 to D0*1P47 to P4 0*1P47 to P40P47 to P40

Port 5 A19 to A16 A19 to A16 A19 to A16 A19 to A16 P53 to P50*2P53 to P50P53 to P50

Port A PA7 to PA4PA7 to PA4PA6 to PA4,

A20*3PA6 to PA 4,

A20*3PA7 to PA 4*4PA7 to PA4PA7 to PA4

Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function

as P47 to P40 in 8-bit bus mode, and as D 7 to D0 in 16-bit bus mode.

2. Initial state. These pins become address output pins when the corresponding bits i n

the data dire ction registers (P1DDR, P2DDR, P5DDR) are set to 1 .

3. Initial state. A20 is always an address output pin. PA6 to PA4 are switched over to A23 to

A21 output by writing 0 in bits 7 to 5 of BRCR.

4. Initial state. PA7 to PA4 are switched over to A23 to A20 output by writing 0 in bits 7 to 4

of BRCR.

Section 3 MCU Operating Modes

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3.6 Memory Map in Each Operating Mode

Figure 3.1 to 3.2 show a memory maps of the H8/3068F. The address space is divided into eight

areas.

The EMC bit in BCR can be read and written to select either of the two memory maps. For

details, see section 6.2.5, Bus Control Register (BCR).

The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.

The address locations of the on-chip RAM and on-chip registers differ between the 64-kbyte

mode (mode 6), the 1-Mbyte modes (modes 1, 2, and 7), and the 16-Mbyte modes (modes 3, 4,

and 5). The address range specifiable by the CPU in the 8- and 16-bit absolute addressing modes

(@aa:8 and @aa:16) also differs.

3.6.1 Note on Reserved Areas

The H8/3068F memory map includes reserved areas to which read/write access is prohibited.

Note that normal operation is not guaranteed if the following reserved areas are accessed.

The reserved area in the internal I/O register space.

The H8/3068F internal I/O register space includes a reserved area to which access is prohibited.

For details see Appendix B, Internal I/O Registers.

Section 3 MCU Operating Modes

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H'00000

H'000FF

H'07FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

Modes 1 and 2

(1-Mbyte expanded modes with

on-chip ROM disabled)

H'1FFFF

H'20000

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

H'DFFFF

H'E0000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External address

space

External address

space

Vector area

On-chip RAM*

8-bit absolute addresses

16-bit absolute addresses

H'F8000

H'FBF1F

H'FBF20

H'FFF00

H'FFF1F

H'FFF20

H'FFFE9

H'FFFEA

H'FFFFF

Modes 3 and 4

(16-Mbyte expanded modes with

on-chip ROM disabled)

H'000000

H'0000FF

H'007FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

H'1FFFFF

H'200000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External

address

space

Vector area

External

address

space

8-bit absolute addresses

16-bit absolute addresses

H'FF8000

H'FFBF1F

H'FFBF20

H'FFFF1F

H'FFFF20

H'FFFF00

H'FFFFE9

H'FFFFEA

H'FFFFFF

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

H'FEE000

H'FEE0FF

Internal I/O

registers (1)

Internal I/O

registers (1)

Internal I/O

registers (2)

Internal I/O

registers (2)

External

address

space

H'EE000

H'EE0FF

External address

space

Note: * External addresses can be accessed by disabling on-chip RAM.

Figure 3.1(1) H8/3068F Memory Map in Each Operating Mode

Section 3 MCU Operating Modes

Rev. 3.00 Sep 14, 2005 page 69 of 910

REJ09B0258-0300

H'000000

H'0000FF

H'007FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

Mode 5

(16-Mbyte expanded mode with

on-chip ROM enabled)

Mode 6

(single-chip normal mode) Mode 7

(single-chip advanced mode)

H'05FFFF

H'060000

H'1FFFFF

H'200000

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External address

space

External address

space

Vector area

On-chip ROM

On-chip RAM*

External

address

space

Internal I/O

registers (1)

Internal I/O

registers (1)

Internal I/O

registers (2)

8-bit absolute addresses

16-bit absolute addresses

H'FEE000

H'FEE0FF

H'FF8000

H'FFBF1F

H'FFBF20

H'FFFF00

H'FFFF1F

H'FFFF20

H'FFFFE9

H'FFFFEA

H'FFFFFF

H'00000

H'000FF

Memory-indirect

branch addresses

16-bit absolute

addresses

Vector area

On-chip ROM

On-chip RAM

Internal I/O

registers(2)

8-bit absolute addresses

16-bit absolute addresses

H'EE000

H'EE0FF

H'FFF1F

H'FFF20

H'FBF20

H'FFFE9

H'FFFFF

H'FFF00

H'07FFF

H'5FFFF

H'F8000

H'0000

H'00FF

H'DFFF

H'E000

Memory-indirect

branch addresses

Vector area

Internal I/O

registers (2)

Internal I/O

registers (1)

8-bit absolute addresses

H'E720

H'E0FF

H'FF00

H'FF1F

H'FF20

H'FFFF

H'FFE9

On-chip RAM

On-chip ROM

Note: * External addresses can be accessed by disabling on-chip RAM.

Figure 3.1(2) H8/3068F Memory Map in Each Operating Mode (EMC = 1)

Section 3 MCU Operating Modes

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Vector area Vector area

External address

space

Internal I/O

registers (1)

Internal I/O

registers (2)

External address

space

On-chip RAM

(96 bytes)

Internal I/O

registers (3)

External address

space

On-chip RAM

(16 kbytes minus

96 bytes)

External address

space

Internal I/O

registers (1)

External address

space

On-chip RAM

(16 kbytes minus

96 bytes)

Internal I/O

registers (2)

External address

space

On-chip RAM

(96 bytes)

Internal I/O

registers (3)

H'00000

H'000FF

H'07FFF

H'1FFFF

H'20000

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

H'DFFFF

H'E0000

H'EE000

H'EE100

H'F8000

H'FBEE0

H'FFE80

H'FFF00

H'FFF80

H'FFFE0

H'FFFFF

H'000000

H'0000FF

H'007FFF

H'1FFFFF

H'200000

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

H'FEE000

H'FEE100

H'FF8000

H'FFBEE0

H'FFFE80

H'FFFF00

H'FFFF80

H'FFFFE0

H'FFFFFF

Modes 1 and 2

(1-Mbyte expanded modes with

on-chip ROM disabled)

Modes 3 and 4

(16-Mbyte expanded modes with

on-chip ROM disabled)

Memory-indirect

branch addresses

16-bit absolute

addresses

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

8-bit absolute

addresses

16-bit absolute addresses

Memory-indirect

branch addresses

16-bit absolute

addresses

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

8-bit absolute addresses

16-bit absolute addresses

Figure 3.2(1) H8/3068F Memory Map in Each Operating Mode (EMC = 0)

Section 3 MCU Operating Modes

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Vector area

On-chip ROM

(384 kbytes)

External address

space

Internal I/O

registers (1)

Internal I/O

registers (2)

External address

space

On-chip RAM

(96 bytes)

Internal I/O

registers (3)

On-chip RAM

(16 kbytes minus

96 bytes)

External address

space

Vector area

On-chip ROM

Internal I/O

registers (1)

On-chip RAM

(16 kbytes minus

96 bytes)

Internal I/O

registers (2)

On-chip RAM

(96 bytes)

Internal I/O

registers (3)

H'00000

H'000FF

H'07FFF

H'EE000

H'EE100

H'F8000

H'FBEE0

H'FFE80

H'FFF00

H'FFF80

H'FFFE0

H'FFFFF

H'000000

H'0000FF

H'007FFF

H'1FFFFF

H'200000

H'05FFFF

H'060000 H'5FFFF

H'60000

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

H'FEE000

H'FEE100

H'FF8000

H'FFBEE0

H'FFFE80

H'FFFF00

H'FFFF80

H'FFFFE0

H'FFFFFF

Mode 5

(16-Mbyte expanded mode with

on-chip ROM enabled)

Mode 7

(single-chip advanced mode)

Memory-indirect

branch addresses

16-bit absolute

addresses

8-bit absolute

addresses

16-bit absolute addresses

Memory-indirect

branch addresses

16-bit absolute

addresses

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

8-bit absolute addresses

16-bit absolute addresses

Figure 3.2(2) H8/3068F Memory Map in Each Operating Mode (EMC = 0)

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Section 4 Exception Handling

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Section 4 Exception Handling

4.1 Overview

4.1.1 Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.

Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur

simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are

accepted at all times in the program execution state.

Table 4.1 Exception Types and Priority

Priority Exception Type Start of Exception Handling

High Reset Starts immediately after a low-to-high transition at the RES pin

Interrupt Interrupt requests are handled when execution of the current

instruction or handling of the current exception is completed

Low Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA)

4.1.2 Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as

follows.

1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.

2. The CCR interrupt mask bit is set to 1.

3. A vector address corresponding to the exception source is generated, and program execution

starts from that address.

For a reset exception, steps 2 and 3 above are carried out.

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4.1.3 Exception Vector Table

The exception sources are classified as shown in figure 4.1. Different vectors are assigned to

different exception sources. Table 4.2 lists the exception sources and their vector addresses.

Exception

sources

• Reset

• Interrupts

• Trap instruction

External interrupts:

Internal interrupts:

NMI, IRQ to IRQ

36 interrupts from on-chip

supporting modules

0 5

Figure 4.1 Exception Sources

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Table 4.2 Exception Vector Table

Vector Address*1

Exception Source Vector Number Advanced Mode Normal Mode

Reset 0 H'0000 to H'0003 H'0000 to H'0001

Reserved for system use 1 H'0004 to H'0007 H'0002 to H'0003

2 H'0008 to H'000B H'0004 to H'0005

3 H'000C to H'000F H'0006 to H'0007

4 H'0010 to H'0013 H'0008 to H'0009

5 H'0014 to H'0017 H'000A to H'000B

6 H'0018 to H'001B H'000C to H'000D

External interrupt (NMI) 7 H'001C to H'001F H'000E to H'000F

Trap instructi on (4 sources) 8 H'0020 to H'0023 H'0010 to H'0011

9 H'0024 to H'0027 H'0012 to H'0013

10 H'0028 to H'002B H'0014 to H'0015

11 H'002C to H'002F H'0016 to H'0017

External interrupt IRQ012 H'0030 to H'0033 H'0018 to H'0019

External interrupt IRQ113 H'0034 to H'0037 H'001A to H'001B

External interrupt IRQ214 H'0038 to H'003B H'001C to H'001D

External interrupt IRQ315 H'003C to H'003F H'001E to H'001F

External interrupt IRQ416 H'0040 to H'0043 H'0020 to H'0021

External interrupt IRQ517 H'0044 to H'0047 H'0022 to H'0023

Reserved for system use 18 H'0048 to H'004B H'0024 to H'0025

19 H'004C to H'004F H'0026 to H'0027

Internal i nterrupts*220

H'0050 to H'0053

H'00F C to H'00F F

H'0028 to H'0029

H'007E to H'007F

Notes: 1. Lower 16 bits of the address.

2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table.

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4.2 Reset

4.2.1 Overview

A reset is the highest-priority exception. When the

RES

pin goes low, all processing halts and the

chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the

on-chip supporting modules. Reset exception handling begins when the

RES

pin changes from

low to high.

The chip can also be reset by overflow of the watchdog timer. For details see section 12,

Watchdog Timer.

4.2.2 Reset Sequence

The chip enters the reset state when the

RES

pin goes low.

To ensure that the chip is reset, hold the

RES

pin low for at least 20 ms at power-up. To reset the

chip during operation, hold the

RES

pin low for at least 10 system clock (φ) cycles. When the

flash memory and flash memory R versions are used, the

RES

pin must be held low for at least 20

system clock cycles. See appendix D.2, Pin States at Reset, for the states of the pins in the reset

state.

When the

RES

pin goes high after being held low for the necessary time, the chip starts reset

exception handling as follows.

• The internal state of the CPU and the registers of the on-chip supporting modules are

initialized, and the I bit is set to 1 in CCR.

• The contents of the reset vector address (H'0000 to H'0003 in advanced mode, H'0000 to

H'0001 in normal mode) are read, and program execution starts from the address indicated in

the vector address.

Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in

modes 2 and 4. Figure 4.4 shows the reset sequence in mode 6.

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Address

bus

RES

HWR

D to D

15 8

Vector fetch Internal

processing Prefetch of

first program

instruction

(1), (3), (5), (7)

(2), (4), (6), (8)

(9)

(10)

Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.

Address of reset vector: (1) = H'000000, (3) = H'000001, (5) = H'000002, (7) = H'000003

Start address (contents of reset exception handling vector address)

Start address

First instruction of program

High

(1) (3) (5) (7) (9)

(2) (4) (6) (8) (10)

LWR,

Figure 4.2 Reset Sequence (Modes 1 and 3)

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Address bus

RES

HWR

D to D

15 0

Vector fetch Internal

processing Prefetch of first

program instruction

(1), (3)

(2), (4)

(5)

(6)

Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.

High

LWR,

Address of reset vector: (1) = H'000000, (3) = H'000002

Start address (contents of reset exception handling vector address)

Start address

First instruction of program

(2) (4)

(3)(1) (5)

(6)

Figure 4.3 Reset Sequence (Modes 2 and 4)

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Vector fetch Internal

processing

Prefetch of

first program

instruction

Internal

address bus

RES

Internal

read signal

Internal

write signal

Internal

data bus

(16 bits wide)

(1) (2)

(2) (3)

(1) Address of reset vector (H'0000)

(2) Start address (contents of reset exception handling vector address)

(3) First instruction of program

Figure 4.4 Reset Sequence (Mode 6)

4.2.3 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR

will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,

including NMI, are disabled immediately after a reset. The first instruction of the program is

always executed immediately after the reset state ends. This instruction should initialize the stack

pointer (example: MOV.L #xx:32, SP).

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4.3 Interrupts

Interrupt exception handling can be requested by seven external sources (NMI, IRQ0 to IRQ5),

and 36 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt

sources and indicates the number of interrupts of each type.

The on-chip supporting modules that can request interrupts are the watchdog timer (WDT),

DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication

interface (SCI), and A/D converter. Each interrupt source has a separate vector address.

NMI is the highest-priority interrupt and is always accepted*. Interrupts are controlled by the

interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority

levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt

priority registers A and B (IPRA and IPRB) in the interrupt controller.

Note: * In the flash memory and flash memory R versions, NMI input is sometimes disabled. For

details see section18.9, NMI Input Disable Conditions.

For details on interrupts see section 5, Interrupt Controller.

Interrupts

External interrupts

Internal interrupts

NMI (1)

IRQ to IRQ (6)

WDT

(1)

DRAM interface

(1)

16-bit timer (9)

8-bit timer (8)

DMAC (4)

SCI (12)

A/D converter (1)

0 5

Notes: Numbers in parentheses are the number of interrupt sources.

1. When the watchdog timer is used as an interval timer, it generates an interrupt request

at every counter overflow.

2. When the DRAM interface is used as an interval timer, it generates an interrupt request

at compare match.

Figure 4.5 Interrupt Sources and Number of Interrupts

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4.4 Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is

set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1

in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a

start address from a vector table entry corresponding to a vector number from 0 to 3, which is

specified in the instruction code.

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4.5 Stack Status after Exception Handling

Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt

exception handling.

SP–4

SP–3

SP–2

SP–1

SP (ER7) →

SP (ER7)

SP+1

SP+2

SP+3

SP+4

→

SP–4

SP–3

SP–2

SP–1

SP (ER7) →

SP (ER7)

SP+1

SP+2

SP+3

SP+4

→

Before exception handling

After exception handling

Stack area

CCR

CCR*

CCR

After exception handling

Even addres

Pushed on stack

a. Normal mode

b. Advanced mode

Legend

PCE:

PCH:

PCL:

CCR:

SP:

Notes: PC indicates the address of the first instruction that will be executed after return.

Registers must be saved in word or longword size at even addresses.

Ignored at return.

Bits 23 to 16 of program counter (PC)

Bits 15 to 8 of program counter (PC)

Bits 7 to 0 of program counter (PC)

Condition code register

Stack pointer

Figure 4.6 Stack after Completion of Exception Handling

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4.6 Notes on Stack Usage

When accessing word data or longword data, the H8/3068F regards the lowest address bit as 0.

The stack should always be accessed by word access or longword access, and the value of the

stack pointer (SP, ER7) should always be kept even.

Use the following instructions to save registers:

PUSH.W Rn (or MOV.W Rn, @–SP)

PUSH.L ERn (or MOV.L ERn, @–SP)

Use the following instructions to restore registers:

POP.W Rn (or MOV.W @SP+, Rn)

POP.L ERn (or MOV.L @SP+, ERn)

Setting SP to an odd value may lead to a malfunction. Figure 4.7 shows an example of what

happens when the SP value is odd.

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TRAPA instruction executed

CCR

Legend

CCR:

PC:

R1L:

SP:

R1L

MOV. B R1L, @-ER7

SP set to H'FFFEFF Data saved above SP CCR contents lost

Condition code register

Program counter

General register R1L

Stack pointer

Note: The diagram illustrates modes 3 and 4.

H'FFFEFA

H'FFFEFB

H'FFFEFC

H'FFFEFD

H'FFFEFF

Figure 4.7 Operation when SP Value is Odd

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Section 5 Interrupt Contro ller

5.1 Overview

5.1.1 Features

The interrupt controller has the following features:

• Interrupt priority registers (IPRs) for setting interrupt priorities

• Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis

in interrupt priority registers A and B (IPRA and IPRB).

• Three-level masking by the I and UI bits in the CPU condition code register (CCR)

• Seven external interrupt pins

NMI has the highest priority and is always accepted*; either the rising or falling edge can be

selected. For each of IRQ0 to IRQ5, sensing of the falling edge or level sensing can be selected

independently.

Note: * In the flash memory and flash memory R versions, NMI input is sometimes disabled. For

details see section18.9, NMI Input Disable Conditions.

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5.1.2 Block Diagram

Figure 5.1 shows a block diagram of the interrupt controller.

ISCR IER IPRA, IPRB

OVF

TME

TEI

TEIE

CPU

CCR

SYSCR

ISCR:

IER:

ISR:

IPRA:

IPRB:

SYSCR:

NMI

input

IRQ input IRQ input

section ISR

Interrupt controller

Priority

decision logic

Interrupt

request

Vector

number

IRQ sense control register

IRQ enable register

IRQ status register

Interrupt priority register A

Interrupt priority register B

System control re

ister

Legend

Figure 5.1 Interrupt Controller Block Diagram

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5.1.3 Pin Configuration

Table 5.1 lists the interrupt pins.

Table 5.1 Interrupt Pins

Name Abbreviation I/O Function

Nonmaskable interrupt NMI Input Nonmaskable interrupt*, rising edge or

fall ing edge selectable

External interrupt request 5 to 0

IRQ

5 to

IRQ

0Input Maskable in terrupts, falling edge or level

sensing selectable

Note: *NMI input is sometimes disabled. For details see 18.9, NMI Input Disabling Conditions.

5.1.4 Register Configuration

Table 5.2 lists the registers of the interrupt controller.

Table 5.2 Interrupt Controller Registers

Address*1Name Abbreviation R/W Initial Value

H'EE012 System control register SYSCR R/W H'09

H'EE014 IRQ sense control register ISCR R/W H'00

H'EE015 IRQ enable register IER R/W H'00

H'EE016 IRQ status register ISR R/(W)*2H'00

H'EE018 Interrupt priority register A IPRA R/W H'00

H'EE019 Interrupt priority register B IPRB R/W H'00

Notes: 1. Lower 20 bits of the address in advanced mode.

2. Only 0 can be written, to cl ear flags.

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5.2 Register Descriptions

5.2.1 System Control Register (SYSCR)

SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the

action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.

Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register

(SYSCR).

SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

SSOE

R/W

Software standby

Standby timer

select 2 to 0

User bit enable

Selects whether to use the UI bit in

CCR as a user bit or interrupt mask bit

NMI edge select

Selects the NMI input edge

Software standby

output port enable

RAM enable

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Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an

interrupt mask bit.

Bit 3

UE Description

0 UI bit in CCR is used a s interrupt mask bit

1 UI bit in CCR is used as user bi t (Init ial value)

Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.

Bit 2

NMIEG Description

0 Interrupt is requested at falling edge of NMI input (Initi al value)

1 Interrupt is requested at rising edge of NMI input

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)

IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.

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Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which

interrupt priority levels can be set.

Bit

Initial value

Read/Write

IPRA7

R/W

IPRA6

R/W

IPRA5

R/W

IPRA4

R/W

IPRA3

R/W

IPRA0

R/W

IPRA2

R/W

IPRA1

R/W

Priority level A7

Selects the priority level of IRQ interrupt requests

Priority level A3

Selects the priority level of WDT,

DRAM interface, and A/D converter

interrupt requests

Priority level A2

Selects the priority level of

16-bit timer channel 0 interrupt

requests

Priority level A1

Selects the priority level

of 16-bit timer channel 1

interrupt requests

Priority

level A0

Selects the

priority level

of 16-bit timer

channel 2

interrupt

requests

Selects the priority level of IRQ interrupt requests

Priority level A6

Selects the priority level of IRQ and IRQ interrupt requests

Priority level A5

Selects the priority level of IRQ and IRQ

interrupt requests

Priority level A4

IPRA is initialized to H'00 by a reset and in hardware standby mode.

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Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests.

Bit 7

IPRA7 Description

0IRQ

0 interrupt requests have priority level 0 (low priority) (Initial val ue)

1IRQ

0 interrupt requests have priority level 1 (high pri ority)

Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests.

Bit 6

IPRA6 Description

0IRQ

1 interrupt requests have priority level 0 (low priority) (Initial val ue)

1IRQ

1 interrupt requests have priority level 1 (high pri ority)

Bit 5—Priority Level A5 (IPRA5): Selects the priority level of IRQ2 and IRQ3 interrupt

requests.

Bit 5

IPRA5 Description

0IRQ

2 and IRQ3 interrupt requests have priority level 0 (low priority) (Initial value)

1IRQ

2 and IRQ3 interrupt requests have priority level 1 (high priority)

Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ5 interrupt

requests.

Bit 4

IPRA4 Description

0IRQ

4 and IRQ5 interrupt requests have priority level 0 (low priority) (Initial value)

1IRQ

4 and IRQ5 interrupt requests have priority level 1 (high priority)

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Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and

A/D converter interrupt requests.

Bit 3

IPRA3 Description

0 WDT, DRAM interface, and A/D converter interrupt requests have priority level 0

(low priority) (Initial value)

1 WDT, DRAM interface, and A/D converter interrupt requests have priority level 1

(high priority)

Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt

requests.

Bit 2

IPRA2 Description

0 16-bit timer channel 0 interrupt requests have pri ority level 0 (low priority)(Initial value)

1 16-bit timer channel 0 interrupt requests have pri ority level 1 (high priority)

Bit 1—Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt

requests.

Bit 1

IPRA1 Description

0 16-bit timer channel 1 interrupt requests have pri ority level 0 (low priority)(Initial value)

1 16-bit timer channel 1 interrupt requests have pri ority level 1 (high priority)

Bit 0—Priority Level A0 (IPRA0): Selects the priority level of 16-bit timer channel 2 interrupt

requests.

Bit 0

IPRA0 Description

0 16-bit timer channel 2 interrupt requests have pri ority level 0 (low priority)(Initial value)

1 16-bit timer channel 2 interrupt requests have pri ority level 1 (high priority)

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Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which

interrupt priority levels can be set.

Bit

Initial value

Read/Write

IPRB7

R/W

IPRB6

R/W

IPRB5

R/W



R/W

IPRB3

R/W



R/W

IPRB2

R/W

IPRB1

R/W

Priority level B7

Selects the priority level of 8-bit timer channel 0, 1 interrupt requests

Priority level B3

Selects the priority level of SCI

channel 0 interrupt requests

Priority level B2

Selects the priority level of

SCI channel 1 interrupt requests

Priority level B1

Selects the priority level

of SCI channel 2 interrupt

requests

Reserved bit

Selects the priority level of 8-bit timer channel 2, 3 interrupt requests

Priority level B6

Selects the priority level of DMAC

interrupt requests (channels 0 and 1)

Priority level B5

Reserved bit

IPRB is initialized to H'00 by a reset and in hardware standby mode.

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Bit 7—Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt

requests.

Bit 7

IPRB7 Description

0 8-bit timer channel 0, 1 interrupt requests have pri ority level 0 (low priority)(Initial value)

1 8-bit timer channel 0, 1 interrupt requests have pri ority level 1 (high priority)

Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt

requests.

Bit 6

IPRB6 Description

0 8-bit timer channel 2, 3 interrupt requests have pri ority level 0 (low priority)(Initial value)

1 8-bit timer channel 2, 3 interrupt requests have pri ority level 1 (high priority)

Bit 5—Priority Level B5 (IPRB5): Selects the priority level of DMAC interrupt requests

(channels 0 and 1).

Bit 5

IPRB5 Description

0 DMAC interrupt requests (channels 0 and 1) have priority level 0 (Initial value)

(low priority)

1 DMAC interrupt requests (channels 0 and 1) have priority l evel 1 (high priority)

Bit 4—Reserved: This bit can be written and read, but it does not affect interrupt priority.

Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests.

Bit 3

IPRB3 Description

0 SCI0 interrupt requests have priority level 0 (low priority) (Initial value)

1 SCI0 interrupt requests have priority level 1 (hi gh priority)

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Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests.

Bit 2

IPRB2 Description

0 SCI1 interrupt requests have priority level 0 (low priority) (Initial value)

1 SCI1 interrupt requests have priority level 1 (hi gh priority)

Bit 1—Priority Level B1 (IPRB1): Selects the priority level of SCI channel 2 interrupt requests.

Bit 1

IPRB1 Description

0 SCI channel 2 interrupt requests have priority level 0 (low priority) (Initial value)

1 SCI channel 2 interrupt requests have priority level 1 (high priority)

Bit 0—Reserved: This bit can be written and read, but it does not affect interrupt priority.

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5.2.3 IRQ Status Register (ISR)

ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt

requests.

Bit

Initial value

Read/Write

—

These bits indicate IRQ to IRQ

interrupt request status

Note: * Onl

0 can be written, to clear fla

—

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

IRQ0F

R/(W)*

IRQ to IRQ flags

Reserved bits

ISR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 and 6—Reserved: These bits can not be modified and are always read as 0.

Bits 5 to 0—IRQ5 to IRQ0 Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to

IRQ0 interrupt requests.

Bits 5 to 0

IRQ5F to IRQ0F Description

0 [Clearing conditions] (Initial val ue)

0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.

IRQnSC = 0,

IRQn

input i s high, and interrupt exception handling is carried out.

IRQnSC = 1 and IRQn interrupt exception handli ng is carried out.

1 [Setting conditions]

IRQnSC = 0 and

IRQn

input is low.

IRQnSC = 1 and

IRQn

input changes from high to low.

Note: n = 5 to 0

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5.2.4 IRQ Enable Register (IER)

IER is an 8-bit readable/writable register that enables or disables IRQ5 to IRQ0 interrupt requests.

Bit

Initial value

Read/Write



R/W

These bits enable or disable IRQ to IRQ interrupt



R/W

IRQ5E

R/W

IRQ4E

R/W

IRQ3E

R/W

IRQ2E

R/W

IRQ1E

R/W

IRQ0E

R/W

IRQ to IRQ enable

Reserved bits

IER is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable

interrupts.

Bits 5 to 0—IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits enable or disable

IRQ5 to IRQ0 interrupts.

Bits 5 to 0

IRQ5E to IRQ0E Description

0IRQ

5 to IRQ0 interrupts are disabl ed (Initi al value)

1IRQ

5 to IRQ0 interrupts are enabled

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5.2.5 IRQ Sense Control Register (ISCR)

ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the

inputs at pins

IRQ

5 to

IRQ

Bit

Initial value

Read/Write



R/W

These bits select level sensing or falling-edge

sensing for IRQ to IRQ interrupts



R/W

IRQ5SC

R/W

IRQ4SC

R/W

IRQ3SC

R/W

IRQ2SC

R/W

IRQ1SC

R/W

IRQ0SC

R/W

IRQ to IRQ sense control

Reserved bits

ISCR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 and 6—Reserved: These bits can be written and read, but they do not select level or

falling-edge sensing.

Bits 5 to 0—IRQ5 to IRQ0 Sense Control (IRQ5SC to IRQ0SC): These bits select whether

interrupts IRQ5 to IRQ0 are requested by level sensing of pins

IRQ

5 to

IRQ

0, or by falling-edge

sensing.

Bits 5 to 0

IRQ5SC to IRQ0SC Description

0 Interrupts are requested when

IRQ

5 to

IRQ

0 inputs are low (Initial value)

1 Interrupts are requested by falling-edge input at

IRQ

5 to

IRQ

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5.3 Interrupt Sources

The interrupt sources include external interrupts (NMI, IRQ0 to IRQ5) and 36 internal interrupts.

5.3.1 External Interrupts

There are seven external interrupts: NMI, and IRQ0 to IRQ5. Of these, NMI, IRQ0, IRQ1, and

IRQ2 can be used to exit software standby mode.

NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I

and UI bits in CCR*. The NMIEG bit in SYSCR selects whether an interrupt is requested by the

rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector

number 7.

Note: * NMI input is sometimes disabled. For details see section18.9, NMI Input Disabling

Conditions.

IRQ0 to IRQ5 Interrupts: These interrupts are requested by input signals at pins

IRQ

0 to

IRQ

The IRQ0 to IRQ5 interrupts have the following features.

• ISCR settings can select whether an interrupt is requested by the low level of the input at pins

IRQ

0 to

IRQ

5, or by the falling edge.

• IER settings can enable or disable the IRQ0 to IRQ5 interrupts. Interrupt priority levels can be

assigned by four bits in IPRA (IPRA7 to IPRA4).

• The status of IRQ0 to IRQ5 interrupt requests is indicated in ISR. The ISR flags can be cleared

to 0 by software.

Figure 5.2 shows a block diagram of interrupts IRQ0 to IRQ5.

input

Edge/level

sense circuit

IRQnSC

IRQnF

IRQnE

IRQn interrupt

request

Clear signal

IRQn

Note: n = 5 to 0

Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5

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Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).

IRQn

IRQnF

Note: n = 5 to 0

input pin

Figure 5.3 Timing of Setting of IRQnF

Interrupts IRQ0 to IRQ5 have vector numbers 12 to 17. These interrupts are detected regardless of

whether the corresponding pin is set for input or output. When using a pin for external interrupt

input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, SCI

input/output, or A/D external trigger input.

5.3.2 Internal Interrupts

Thirty-Six internal interrupts are requested from the on-chip supporting modules.

• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits

for enabling or disabling interrupts.

• Interrupt priority levels can be assigned in IPRA and IPRB.

• 16-bit timer, SCI, and A/D converter interrupt requests can activate the DMAC, in which case

no interrupt request is sent to the interrupt controller, and the I and UI bits are disregarded.

5.3.3 Interrupt Vector Table

Table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. In the

default priority order, smaller vector numbers have higher priority. The priority of interrupts other

than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order

shown in table 5.3.

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Table 5.3 Interrupt Sources, Vector Addresses, and Priority

Vector Vector Address*

Interrupt Source Origin Number Advanced Mode Normal Mode IPR Priority

NMI External 7 H'001C to H'001F H'000E to H'000F — High

IRQ

pins 12 H'0030 to H'0033 H'0018 to H'0019 IPRA7

IRQ

13 H'0034 to H0037 H'001A to H'001B IPRA6

IRQ

15 H'0038 to H'003B

H'003C to H'003F H'001C to H'001D

H'001E to H'001F IPRA5

IRQ

17 H'0040 to H'0043

H'0044 to H'0047 H'0020 to H'0021

H'0022 to H'0023 IPRA4

Reserved — 18

19 H'0048 to H'004B

H'004C to H'004F H'0024 to H'0025

H'0026 to H'0027

WOVI

(interval timer) Watchdog

timer 20 H'0050 to H'0053 H'0028 to H'0029 IPRA3

CMI

(compare match) DRAM

interface 21 H'0054 to H'0057 H'002A to H'002B

Reserved — 22 H'0058 to H'005B H'002C to H'002D

ADI (A/D end) A/D 23 H'005C to H'005F H'002E to H'002F

IMIA0

(compare match/

input capture A0)

IMIB0

(compare match/

input capture B0)

OVI0 (overflow 0)

16-bit timer

channel 0 24

H'0060 to H'0063

H'0064 to H'0067

H'0068 to H'006B

H'0030 to H'0031

H'0032 to H'0033

H'0034 to H'0035

IPRA2

Reserved — 27 H'006C to H'006F H'0036 to H'0037

IMIA1

(compare match/

inputcapture A1)

IMIB1

(compare match/

input capture B1)

OVI1 (overflow 1)

16-bit timer

channel 1 28

H'0070 to H'0073

H'0074 to H'0077

H'0078 to H'007B

H'0038 to H'0039

H'003A to H'003B

H'003C to H'003D

IPRA1

Reserved — 31 H'007C to H'007F H'003E to H'003F Low

Note: * Lower 16 bits of the address.

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Vector Vector Address*

Interrupt Source Origin Number Advanced Mode Normal Mode IPR Priority

IMIA2

(compare match/

input capture A2)

IMIB2

(compare match/

input capture B2)

OVI2 (overflow 2)

16-bit timer

channel 2 32

H'0080 to H'0083

H'0084 to H'0087

H'0088 to H'008B

H'0040 to H'0041

H'0042 to H'0043

H'0044 to H'0045

IPRA0 High

Reserved — 35 H'008C to H'008F H'0046 to H'0047

CMIA0

(compare match

A0)

CMIB0

(compare match

B0)

CMIA1/CMIB1

(compare match

A1/B1)

TOVI0/TOVI1

(overflow 0/1)

8-bit timer

channel 0/1 36

H'0090 to H'0093

H'0094 to H'0097

H'0098 to H'009B

H'009C to H'009F

H'0048 to H'0049

H'004A to H'004B

H'004C to H'004D

H'004E to H'004F

IPRB7

CMIA2

(compare match

A2)

CMIB2

(compare match

B2)

CMIA3/CMIB3

(compare match

A3/B3)

TOVI2/TOVI3

(overflow 2/3)

8-bit timer

channel 2/3 40

H'00A0 to H'00A3

H'00A4 to H'00A7

H'00A8 to H'00AB

H'00AC to H'00AF

H'0050 to H'0051

H'0052 to H'0053

H'0054 to H'0055

H'0056 to H'0057

IPRB6

DEND0A

DEND0B

DEND1A

DEND1B

DMAC 44

H'00B0 to H'00B3

H'00B4 to H'00B7

H'00B8 to H'00BB

H'00BC to H'00BF

H'0058 to H'0059

H'005A to H'005B

H'005C to H'005D

H'005E to H'005F

IPRB5

Reserved — 48

H'00C0 to H'00C3

H'00C4 to H'00C7

H'00C8 to H'00CB

H'00CC to H'00CF

H'0060 to H'0061

H'0062 to H'0063

H'0064 to H'0065

H'0066 to H'0067

—

Low

Note: * Lower 16 bits of the address.

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Vector Vector Address*

Interrupt Source Origin Number Advanced Mode Normal Mode IPR Priority

ERI0

(receive error 0)

RXI0 (receive

data full 0)

TXI0 (transmit

data empty 0)

TEI0

(transmit end 0)

SCI

channel 0 52

H'00D0 to H'00D3

H'00D4 to H'00D7

H'00D8 to H'00DB

H'00DC to H'00DF

H'0068 to H'0069

H'006A to H'006B

H'006C to H'006D

H'006E to H'006F

IPRB3 High

ERI1

(receive error 1)

RXI1 (receive

data full 1)

TXI1 (transmit

data empty 1)

TEI1 (transmit

end 1)

SCI

channel 1 56

H'00E0 to H'00E3

H'00E4 to H'00E7

H'00E8 to H'00EB

H'00EC to H'00EF

H'0070 to H'0071

H'0072 to H'0073

H'0074 to H'0075

H'0076 to H'0077

IPRB2

ERI2

(receive error 2)

RXI2 (receive

data full 2)

TXI2 (transmit

data empty 2)

TEI2 (transmit

end 2)

SCI

channel 2 60

H'00F0 to H'00F3

H'00F4 to H'00F7

H'00F8 to H'00FB

H'00FC to H'00FF

H'0078 to H'0079

H'007A to H'007B

H'007C to H'007D

H'007E to H'007F

IPRB1

Low

Note: * Lower 16 bits of the address.

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5.4 Interrupt Operation

5.4.1 Interrupt Handling Process

The H8/3068F handles interrupts differently depending on the setting of the UE bit. When UE =

1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI

bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I, and

UI bits.

NMI interrupts are always accepted except in the reset and hardware standby states*. IRQ

interrupts and interrupts from the on-chip supporting modules have their own enable bits.

Interrupt requests are ignored when the enable bits are cleared to 0.

Note: * NMI input is sometimes disabled. For details see section 18.9, NMI Input Disabling

Conditions.

Table 5.4 UE, I, and UI Bit Settings and Interrupt Handling

SYSCR CCR

UE I UI Description

10—All interrupts are accepted. Interrupts with priority level 1 have higher

priority.

1 — No interrupts are accepted except NMI.

00—All interrupts are accepted. Interrupts with priority level 1 have higher

priority.

1 0 NMI and interrupts with priority l evel 1 are accepted.

1 No interrupts are accepted except NMI.

UE = 1: Interrupts IRQ0 to IRQ5 and interrupts from the on-chip supporting modules can all be

masked by the I bit in the CPU’s CCR. Interrupts are masked when the I bit is set to 1, and

unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority.

Figure 5.4 is a flowchart showing how interrupts are accepted when UE = 1.

Section 5 Interrupt Controll er

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Program execution state

Interrupt requested?

NMI

Yes

Priority level 1?

IRQ

Yes No

IRQ

Yes TEI2

Yes

IRQ

Yes No

IRQ

Yes TEI2

Yes

I = 0

Yes

Save PC and CCR

I 1

Branch to interrupt

service routine

←

Pending

Yes

Read vector address

Figure 5.4 Process Up to Interrupt Acceptance when UE = 1

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• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

• When the interrupt controller receives one or more interrupt requests, it selects the highest-

priority request, following the IPR interrupt priority settings, and holds other requests

pending. If two or more interrupts with the same IPR setting are requested simultaneously, the

interrupt controller follows the priority order shown in table 5.3.

• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt

request is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are

held pending.

• When an interrupt request is accepted, interrupt exception handling starts after execution of

the current instruction has been completed.

• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is

saved indicates the address of the first instruction that will be executed after the return from

the interrupt service routine.

• Next the I bit is set to 1 in CCR, masking all interrupts except NMI.

• The vector address of the accepted interrupt is generated, and the interrupt service routine

starts executing from the address indicated by the contents of the vector address.

UE = 0: The I and UI bits in the CPU’s CCR and the IPR bits enable three-level masking of

IRQ0 to IRQ5 interrupts and interrupts from the on-chip supporting modules.

• Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked

when the I bit is cleared to 0.

• Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and

are unmasked when either the I bit or the UI bit is cleared to 0.

For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to

H'20, and IPRB is set to H'00 (giving IRQ2 and IRQ3 interrupt requests priority over other

interrupts), interrupts are masked as follows:

a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ2 > IRQ3 >IRQ0 …).

b. If I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 are unmasked.

c. If I = 1 and UI = 1, all interrupts are masked except NMI.

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Figure 5.5 shows the transitions among the above states.

All interrupts are

unmasked Only NMI, IRQ , and

IRQ are unmasked

Exception handling,

or I 1, UI 1

a. b.

All interrupts are

masked except NMI

UI 0I 0 Exception handling,

or UI 1

I 0

I 1, UI 0

←← ←←

←

←←

Figure 5.5 Interrupt Masking State Transitions (Example)

Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.

• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

• When the interrupt controller receives one or more interrupt requests, it selects the highest-

priority request, following the IPR interrupt priority settings, and holds other requests

pending. If two or more interrupts with the same IPR setting are requested simultaneously, the

interrupt controller follows the priority order shown in table 5.3.

• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt

request is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set

to 1 and the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted;

interrupt requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1,

only NMI is accepted; all other interrupt requests are held pending.

• When an interrupt request is accepted, interrupt exception handling starts after execution of

the current instruction has been completed.

• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is

saved indicates the address of the first instruction that will be executed after the return from

the interrupt service routine.

• The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.

• The vector address of the accepted interrupt is generated, and the interrupt service routine

starts executing from the address indicated by the contents of the vector address.

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Program execution state

Interrupt requested?

NMI

Yes

Priority level 1?

IRQ

Yes No

IRQ

Yes TEI2

Yes

IRQ

Yes No

IRQ

Yes TEI2

Yes

I = 0

Yes

I = 0

Yes

UI = 0

Yes

Save PC and CCR

I 1, UI 1

←

Pending

Branch to interrupt

service routine

Yes

←

Read vector address

Figure 5.6 Process Up to Interrupt Acceptance when UE = 0

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5.4.2 Interrupt Sequence

Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an

external memory area accessed in two states via a 16-bit bus.

Address

bus

Interrupt

request

signal

HWR

D to D

15 0

(1)

(2), (4)

(3)

(5)

(7)

Note: Mode 2, with program code and stack in external memory area accessed in two states via 16-bit bus.

LWR,

Interrupt level

decision and wait

for end of instruction

Interrupt accepted

Instruction

prefetch Internal

processing Stack Vector fetch Internal

processing

Prefetch of

interrupt

service routine

instruction

High

Instruction prefetch address (not executed;

return address, same as PC contents)

Instruction code (not executed)

Instruction prefetch address (not executed)

SP – 2

SP – 4

(6), (8)

(9), (11)

(10), (12)

(13)

(14)

PC and CCR saved to stack

Vector address

Starting address of interrupt service routine (contents of

vector address)

Starting address of interrupt service routine; (13) = (10), (12)

First instruction of interrupt service routine

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

Figure 5.7 Interrupt Sequence

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5.4.3 Interrupt Response Time

Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until

the first instruction of the interrupt service routine is executed.

Table 5.5 Interrupt Response Time

External Memory

On-Chip 8-Bit Bus 16-Bit Bus

No. Item Memory 2 States 3 States 2 States 3 States

1 Interrupt priority

decision 2*12*12*12*12*1

2 Maximum number

of states until end of

current in struction

1 to 23*51 to 27*51 to 41*4,*61 to 23*51 to 25*4,*5

3 Saving PC and CCR

to stack 48 12*446*4

4 Vector fetch 4 8 12*446*4

5 Instruction prefetch*248 12*446*4

6 Internal processing*344 4 4 4

Total 19 to 41 31 to 57 43 to 83 19 to 41 25 to 49

Notes: 1. 1 state for internal interrupts.

2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the

interrupt servi ce routine.

3. Internal processing after the interrupt is accepted and internal processing after vector

fetch.

4. The number of states increases if wait states are inserted in external memory access.

5. Example for DIVXS.W Rs,ERd and MULXS.W Rs,ERd

6. Example for MOV.L @(d:24,ERs),ERd and MOV.L ERs,@(d:24,ERd)

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5.5 Usage Notes

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction

When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not

disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR,

MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant

when execution of the instruction ends the interrupt is still enabled, so its interrupt exception

handling is carried out. If a higher-priority interrupt is also requested, however, interrupt

exception handling for the higher-priority interrupt is carried out, and the lower-priority interrupt

is ignored. This also applies to the clearing of an interrupt flag to 0.

Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in the 16-bit timer's TISRA

IMIA exception handlingTISRA write cycle by CPU

TISRA address

Internal

address bus

Internal

write signal

IMIEA

IMIA

IMFA interrupt

signal

Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction

This type of contention will not occur if the interrupt is masked when the interrupt enable bit or

flag is cleared to 0.

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5.5.2 Instructions that Inhibit Interrupts

The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs,

after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the

CPU is currently executing one of these interrupt-inhibiting instructions, however, when the

instruction is completed the CPU always continues by executing the next instruction.

5.5.3 Interrupts during EEPMOV Instruction Execution

The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.

When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the

transfer is completed, not even NMI.

When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are

not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts

at a transfer cycle boundary. The PC value saved on the stack is the address of the next

instruction. Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W

execution:

L1: EEPMOV.W

MOV.W R4,R4

BNE L1

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Section 6 Bus Controller

6.1 Overview

The H8/3068F has an on-chip bus controller (BSC) that manages the external address space

divided into eight areas. The bus specifications, such as bus width and number of access states,

can be set independently for each area, enabling multiple memories to be connected easily.

The bus controller also has a bus arbitration function that controls the operation of the internal

bus masters-the CPU, DMA controller (DMAC), and DRAM interface and can release the bus to

an external device.

6.1.1 Features

The features of the bus controller are listed below.

• Manages external address space in area units

 Manages the external space as eight areas (0 to 7) of 128 kbytes in 1M-byte modes, or 2

Mbytes in 16-Mbyte modes

 Bus specifications can be set independently for each area

 DRAM/burst ROM interfaces can be set

• Basic bus interface

 Chip select (

0 to

7) can be output for areas 0 to 7

 8-bit access or 16-bit access can be selected for each area

 Two-state access or three-state access can be selected for each area

 Program wait states can be inserted for each area

 Pin wait insertion capability is provided

• DRAM interface

 DRAM interface can be set for areas 2 to 5

 Row address/column address multiplexed output (8/9/10 bits)

 2-CAS byte access mode

 Burst operation (fast page mode)

 TP cycle insertion to secure RAS precharging time

 Choice of CAS-before-RAS refreshing or self-refreshing

• Burst ROM interface

 Burst ROM interface can be set for area 0

 Selection of two- or three-state burst access

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• Idle cycle insertion

 An idle cycle can be inserted in case of an external read cycle between different areas

 An idle cycle can be inserted when an external read cycle is immediately followed by an

external write cycle

• Bus arbitration function

 A built-in bus arbiter grants the bus right to the CPU, DMAC, DRAM interface, or an

external bus master

• Other features

 Refresh counter (refresh timer) can be used as interval timer

 Choice of two address update modes

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6.1.2 Block Diagram

Figure 6.1 shows a block diagram of the bus controller.

Internal address bus

ABWCR

ASTCR

BCR

CSCR

ADRCR

Area

decoder

Chip select

control signals

to CS

Bus control

circuit

WCRH

WCRL

BRCR

DRAM control

Legend

DRAM interface

Wait state

controller

WAIT

BACK

BREQ

Internal data bus

CPU bus request signal

DMAC bus request signal

DRAM interface bus request signal

CPU bus acknowledge signal

DMAC bus acknowledge signal

DRAM interface bus acknowledge signal

Bus arbiter

Bus mode control signal

Internal signals

Bus size control signal

Access state control signal

Wait request signal

: Bus width control register

: Access state control register

: DRAM control register A

: DRAM control register B

: Wait control register H

: Wait control register L

: Bus release control register

: Chip select control register

: Refresh timer control/status register

: Refresh timer counter

: Refresh time constant register

ASTCR

DRCRA

DRCRB

WCRH

WCRL

BRCR

CSCR

RTMCSR

RTCNT

RTCOR

ADRCR : Address control register

ABWCR

DRCRA

DRCRB

RTMCSR

RTCNT

RTCOR

BCR : Bus control register

Figure 6.1 Block Diagram of Bus Controller

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6.1.3 Pin Configuration

Table 6.1 summarizes the input/output pins of the bus controller.

Table 6.1 Bus Controller Pins

Name Abbreviation I/O Function

Chip select 0 to 7

0 to

7Output Strobe signals selecting areas 0 to 7

Address strobe

Output Strobe signal indicating val id address output

on the address bus

Read

Output Strobe si gnal indicating reading from the

external address space

High write

HWR

Output Strobe signal i ndicating writi ng to the

external address space, with valid data on

the upper data bus (D15 to D8)

Low write

LWR

Output Strobe signal i ndicating writi ng to the

external address space, with valid data on

the lower data bus (D7 to D0)

Wait

WAIT

Input Wait request signal for access to external

three-state access areas

Bus request

BREQ

Input Request signal for releasing the bus to an

external device

Bus acknowledge

BACK

Output Acknowledge signal indicating release of the

bus to an external device

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6.1.4 Register Configuration

Table 6.2 summarizes the bus controller's registers.

Table 6.2 Bus Controller Registers

Address*1Name Abbreviation R/W Initial Value

H'EE020 Bus width control register ABWCR R/W H'FF*2

H'EE021 Access state control register ASTCR R/W H'FF

H'EE022 Wait control register H WCRH R/W H'FF

H'EE023 Wait control register L WCRL R/W H'FF

H'EE013 Bus release control register BRCR R/W H'FE*3

H'EE01F Chip select control register CSCR R/W H'0F

H'EE01E Address control reg ister ADRCR R/W H'FF

H'EE024 Bus control register BCR R/W H'C6

H'EE026 DRAM contro l re gister A DRCRA R/W H'10

H'EE027 DRAM contro l re gister B DRCRB R/W H'08

H'EE028 Refresh timer control/status register RTMCSR R(W)*4H'07

H'EE029 Refresh timer counter RTCNT R/W H'00

H'EE02A Refresh time constant register RTCOR R/W H'FF

Notes: 1. Lower 20 bits of the address in advanced mode.

2. In modes 2 and 4, the initial value is H'00.

3. In modes 3 and 4, the initial value is H'EE.

4. For Bit 7, only 0 can be written to clear the flag.

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6.2 Register Descriptions

6.2.1 Bus Width Control Register (ABWCR)

ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.

ABW7

R/W

ABW6

R/W

ABW5

R/W

ABW4

R/W

ABW3

R/W

ABW2

R/W

ABW1

R/W

ABW0

R/W

Bit

Modes

1, 3, 5, 6,

and 7 Initial value

Read/Write

Initial value

Read/Write

Modes

2 and 4

When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus

mode: the upper data bus (D15 to D8) is valid, and port 4 is an input/output port. When at least

one bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus

(D15 to D0). In modes 1, 3, 5, 6, and 7, ABWCR is initialized to H'FF by a reset and in hardware

standby mode. In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware

standby mode. It is not initialized in software standby mode.

Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access

or 16-bit access for the corresponding areas.

Bits 7 to 0

ABW7 to ABW0 Description

0 Areas 7 to 0 are 16-bit access areas

1 Areas 7 to 0 are 8-bit access areas

ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip

memory and registers is fixed, and does not depend on ABWCR settings. These settings are

therefore meaningless in the single-chip modes (modes 6 and 7).

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6.2.2 Access State Control Register (ASTCR)

ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two

states or three states.

AST3 AST2 AST1 AST0

1Initial value 1111111

Read/Write R/W R/W R/W R/WR/W R/W R/W R/W

76543210

Bits selectin

number of states for access to each area

AST7 AST6 AST5 AST4

Bit

ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the

corresponding area is accessed in two or three states.

Bits 7 to 0

AST7 to AST0 Description

0 Areas 7 to 0 are accessed in two states

1 Areas 7 to 0 are accessed in three states (Initial value)

ASTCR specifies the number of states in which external areas are accessed. On-chip memory and

registers are accessed in a fixed number of states that does not depend on ASTCR settings. These

settings are therefore meaningless in the single-chip modes (modes 6 and 7).

When the corresponding area is designated as DRAM space by bits DRAS2 to DRAS0 in DRAM

control register A (DRCRA), the number of access states does not depend on the AST bit setting.

When an AST bit is cleared to 0, programmable wait insertion is not performed.

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6.2.3 Wait Control Registers H and L (WCRH, WCRL)

WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait

states for each area.

On-chip memory and registers are accessed in a fixed number of states that does not depend on

WCRH/WCRL settings.

WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are

not initialized in software standby mode.

WCRH

W51 W50 W41 W40

1Initial value 1111111

Read/Write R/W R/W R/W R/WR/W R/W R/W R/W

76543210

W71 W70 W61 W60

Bit

Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of

program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set

to 1.

Bit 7

W71 Bit 6

W70 Description

0 0 Program wait not inserted when external space area 7 is accessed

1 1 program wait state inserted when external space area 7 is accessed

1 0 2 program wait states inserted when external space area 7 is accessed

1 3 program wait states inserted when external space area 7 is accessed

(Initi al value)

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Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of

program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set

to 1.

Bit 5

W61 Bit 4

W60 Description

0 0 Program wait not inserted when external space area 6 is accessed

1 1 program wait state inserted when external space area 6 is accessed

1 0 2 program wait states inserted when external space area 6 is accessed

1 3 program wait states inserted when external space area 6 is accessed

(Initi al value)

Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of

program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set

to 1.

Bit 3

W51 Bit 2

W50 Description

0 0 Program wait not inserted when external space area 5 is accessed

1 1 program wait state inserted when external space area 5 is accessed

1 0 2 program wait states inserted when external space area 5 is accessed

1 3 program wait states inserted when external space area 5 is accessed

(Initi al value)

Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of

program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set

to 1.

Bit 1

W41 Bit 0

W40 Description

0 0 Program wait not inserted when external space area 4 is accessed

1 1 program wait state inserted when external space area 4 is accessed

1 0 2 program wait states inserted when external space area 4 is accessed

1 3 program wait states inserted when external space area 4 is accessed

(Initi al value)

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WCRL

W11 W10 W01 W00

1Initial value 1 1 1 1111

Read/Write R/W R/W R/W R/WR/W R/W R/W R/W

76543210

W31 W30 W21 W20

Bit

Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of

program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set

to 1.

Bit 7

W31 Bit 6

W30 Description

0 0 Program wait not inserted when external space area 3 is accessed

1 1 program wait state inserted when external space area 3 is accessed

1 0 2 program wait states inserted when external space area 3 is accessed

1 3 program wait states inserted when external space area 3 is accessed

(Initi al value)

Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of

program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set

to 1.

Bit 5

W21 Bit 4

W20 Description

0 0 Program wait not inserted when external space area 2 is accessed

1 1 program wait state inserted when external space area 2 is accessed

1 0 2 program wait states inserted when external space area 2 is accessed

1 3 program wait states inserted when external space area 2 is accessed

(Initi al value)

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Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of

program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set

to 1.

Bit 3

W11 Bit 2

W10 Description

0 0 Program wait not inserted when external space area 1 is accessed

1 1 program wait state inserted when external space area 1 is accessed

1 0 2 program wait states inserted when external space area 1 is accessed

1 3 program wait states inserted when external space area 1 is accessed

(Initi al value)

Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of

program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set

to 1.

Bit 1

W01 Bit 0

W00 Description

0 0 Program wait not inserted when external space area 0 is accessed

1 1 program wait state inserted when external space area 0 is accessed

1 0 2 program wait states inserted when external space area 0 is accessed

1 3 program wait states inserted when external space area 0 is accessed

(Initi al value)

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6.2.4 Bus Release Control Register (BRCR)

BRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A20

and enables or disables release of the bus to an external device.

A23E

—

R/W

Address 23 to 20 enable

These bits enable PA

to PA

to be

used for A

to A

address output

A22E

—

R/W

A21E

—

R/W

A20E

—

R/W

—

BRLE

R/W

Bit

Modes

1, 2, 6,

and 7 Initial value

Read/Write

Initial value

Read/Write

Initial value

Read/Write

Modes

3 and 4

Mode 5

Reserved bits

Bus release enable

Enables or disables

release of the bus

to an external device

BRCR is initialized to H'FE in modes 1, 2, 5, 6, and 7, and to H'EE in modes 3 and 4, by a reset

and in hardware standby mode. It is not initialized in software standby mode.

Bit 7—Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin.

Writing 0 in this bit enables A23 output from PA4. In modes other than 3, 4, and 5, this bit cannot

be modified and PA4 has its ordinary port functions.

Bit 7

A23E Description

0PA

4 is the A23 address output pin

1PA

4 is an input/output pin (Initial value)

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Bit 6—Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin.

Writing 0 in this bit enables A22 output from PA5. In modes other than 3, 4, and 5, this bit cannot

be modified and PA5 has its ordinary port functions.

Bit 6

A22E Description

0PA

5 is the A22 address output pin

1PA

5 is an input/output pin (Initial value)

Bit 5—Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin.

Writing 0 in this bit enables A21 output from PA6. In modes other than 3, 4, and 5, this bit cannot

be modified and PA6 has its ordinary port functions.

Bit 5

A21E Description

0PA

6 is the A21 address output pin

1PA

6 is an input/output pin (Initial value)

Bit 4—Address 20 Enable (A20E): Enables PA7 to be used as the A20 address output pin.

Writing 0 in this bit enables A20 output from PA7. This bit can only be modified in mode 5.

Bit 4

A20E Description

0PA

7 is the A20 address output pin (Initial value when in mode 3 or 4)

1PA

7 is an input/output pin (Initial val ue when in mode 1, 2, 5, 6, or 7)

Bits 3 to 1—Reserved: These bits cannot be modified and are always read as 1.

Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external

device.

Bit 0

BRLE Description

0 The bus cannot be released to an external device

BREQ

and

BACK

can be used as input/output pi ns (Initial value)

1 The bus can be released to an external device

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6.2.5 Bus Control Register (BCR)

BRSTS0 EMC RDEA WAITE

1Initial value 1 0 0 0 1 1 0

Read/Write R/W R/W R/W R/WR/W R/W R/W R/W

76543210

ICIS1 ICIS0 BROME BRSTS1

Bit

BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the

address map, selects the area division unit, and enables or disables

WAIT

pin input.

BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted

between bus cycles in case of consecutive external read cycles for different areas.

Bit 7

ICIS1 Description

0 No idle cycle inserted in case of consecutive external read cycles for different

areas

1 Idl e cycle inserted in case of consecutive external read cycles for different

areas (Initi al value)

Bit 6—Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted

between bus cycles in case of consecutive external read and write cycles.

Bit 6

ICIS0 Description

0 No idle cycle inserted in case of consecutive external read and write cycles

1 Idl e cycle inserted in case of consecutive external read and write cycles

(Initi al value)

Bit 5—Burst ROM Enable (BROME): Selects whether area 0 is a burst ROM interface area.

Bit 5

BROME Description

0 Area 0 is a basic bus interface area (Initi al value)

1 Area 0 is a burst ROM interface area

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Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycle states for the burst

ROM interface.

Bit 4

BRSTS1 Description

0 Burst access cycl e comprises 2 states (Initial value)

1 Burst access cycl e comprises 3 states

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a

burst ROM interface burst access.

Bit 3

BRSTS0 Description

0 Max. 4 words in burst access (burst access on match of address bits above

A3) (Initial value)

1 Max. 8 words in burst access (burst access on match of address bits above

A4)

Bit 2—Expansion Memory Map Control (EMC): Selects either of the two memory maps.

Bit 2

EMC Description

0 Selects the memory map shown i n figure 3.2: see section 3.6, Memory Map in

Each Operating Mode

1 Selects the memory map shown i n figure 3.1: see section 3.6, Memory Map in

Each Operating Mode (Initi al value)

When EMC is cleared to 0, addresses of some internal I/O registers are moved. For details, refer

to appendix B.2, Address List (when EMC = 0).

This bit is invalid in mode 6. In mode 6 and when the RDEA bit is 0, EMC must not be cleared to

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Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units. This bit

is valid in modes 3, 4, and 5, and is invalid in modes 1, 2, 6, and 7.

When the EMC bit is 0, RDEA must not be cleared to 0.

Bit 1

RDEA Description

0 Area divisions are as follows: Area 0: 2 Mbytes Area 4: 1.93 Mbytes

Area 1: 2 Mbytes Area 5: 4 kbytes

Area 2: 8 Mbytes Area 6: 23.75 kbytes

Area 3: 2 Mbytes Area 7: 22 bytes

1 Areas 0 to 7 are the same size (2 Mbytes) (Initial value)

Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the

WAIT

pin.

Bit 0

WAITE Description

WAIT

pin wait input is disabled, and the

WAIT

pin can be used as an

input/output port (Initial value)

WAIT

pin wait input is enabled

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6.2.6 Chip Select Control Register (CSCR)

CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals

(

7 to

4).

If output of a chip select signal is enabled by a setting in this register, the corresponding pin

functions as a chip select signal (

7 to

4) output regardless of any other settings. CSCR

cannot be modified in single-chip mode.

————

0Initial value 0001111

Read/Write ————R/W R/W R/W R/W

76543210

Reserved bits

CS7E CS6E CS5E CS4E

Chip select 7 to 4 enable

These bits enable or disable

chip select signal output

Bit

CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 4—Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of

the corresponding chip select signal.

Bit n

CSnE Description

0 Output of chip select signal

CSn

is disabled (Initi al value)

1 Output of chip select signal

CSn

is enabled

Note: n = 7 to 4

Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 1.

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6.2.7 DRAM Control Register A (DRCRA)

BE RDM SRFMD RFSHE

0Initial value 0010000

Read/Write R/W R/W R/W R/WR/W R/W R/W —

76543210

DRAS2 DRAS1 DRAS0 —

Bit

DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface

function, and the access mode, and enables or disables self-refreshing and refresh pin output.

DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 5—DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5

are to function as DRAM interface areas (DRAM space) in expanded mode, and at the same time

select the

RAS

output pin corresponding to each DRAM space.

Description

Bit 7

DRAS2 Bit 6

DRAS1 Bit 5

DRAS0 Area 5 Area 4 Area 3 Area 2

000Normal Normal Normal Normal

1 Normal Normal Normal DRAM space

(

1 0 Normal Normal DRAM space

(

3)DRAM space

(

1 Normal Normal DRAM space

(

2)*DRAM space

(

2)*

100Normal DRAM space

(

4)DRAM space

(

3)DRAM space

(

1 DRAM space

(

5)DRAM space

(

4)DRAM space

(

3)DRAM space

(

1 0 DRAM space

(

4)*DRAM space

(

4)*DRAM space

(

2)*DRAM space

(

2)*

1 DRAM space

(

2)*DRAM space

(

2)*DRAM space

(

2)*DRAM space

(

2)*

Note: *A single

CSn

pin serves as a common

RAS

output pin for a number of areas. Unused

CSn

pins can be used as input/output ports.

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When any of bits DRAS2 to DRAS0 is set to 1 in expanded mode, it is not possible to write to

DRCRB, RTMCSR, RTCNT, or RTCOR. However, 0 can be written to the CMF flag in

RTMCSR to clear the flag.

When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than

000 must not be performed.

Bit 4—Reserved: This bit cannot be modified and is always read as 1.

Bit 3—Burst Access Enable (BE): Enables or disables burst access to DRAM space. DRAM

space burst access is performed in fast page mode.

Bit 3

BE Description

0 Burst disabled (always full access) (Initial val ue)

1 DRAM space access performed in fast page mode

Bit 2—RAS Down Mode (RDM): Selects whether to wait for the next DRAM access with the

RAS

signal held low (RAS down mode), or to drive the RAS signal high again (RAS up mode),

when burst access is enabled for DRAM space (BE = 1), and access to DRAM is interrupted.

Caution is required when the

HWR

and

LWR

are used as the

UCAS

and

LCAS

output pins. For

details, see RAS Down Mode and RAS Up Mode in section 6.5.10, Burst Operation.

Bit 2

RDM Description

0 DRAM interface: RAS up mode selected (Initial value)

1 DRAM interface: RAS down mode selected

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Bit 1—Self-Refresh Mode (SRFMD): Specifies DRAM self-refreshing in software standby

mode.

When any of areas 2 to 5 is designated as DRAM space, DRAM self-refreshing is possible when a

transition is made to software standby mode after the SRFMD bit has been set to 1.

The normal access state is restored when software standby mode is exited, regardless of the

SRFMD setting.

Bit 1

SRFMD Description

0 DRAM self-refreshing disabled in software standby mode (Initial value)

1 DRAM self-refreshing enabled in software standby mode

Bit 0—Refresh Pin Enable (RFSHE): Enables or disables

RFSH

pin refresh signal output. If

areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1.

Bit 0

RFSHE Description

RFSH

pin refresh si gnal output disabled (Initial value)

(

RFSH

pin can be used as i nput/output port)

RFSH

pin refresh si gnal output enabled

6.2.8 DRAM Control Register B (DRCRB)

— TPC RCW RLW

0Initial value 0001000

Read/Write — R/W R/W R/WR/W R/W R/W R/W

76543210

MXC1 MXC0 CSEL RCYCE

Bit

DRCRB is an 8-bit readable/writable register that selects the number of address multiplex column

address bits for the DRAM interface, the column address strobe output pin, enabling or disabling

of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state

insertion between

RAS

and

CAS

, and enabling or disabling of wait state insertion in refresh

cycles.

DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

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The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0.

Bits 7 and 6—Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row

address/column address multiplexing method used on the DRAM interface. In burst operation,

the row address used for comparison is determined by the setting of these bits and the bus width

of the relevant area set in ABWCR.

Bit 7

MXC1 Bit 6

MXC0 Description

0 0 Column address: 8 bits

Compared address:

Modes 1, 2 8-bit access space A19 to A8

16-bit access space A19 to A9

Modes 3, 4, 5 8-bit access space A23 to A8

16-bit access space A23 to A9

1 Column address: 9 bits

Compared address:

Modes 1, 2 8-bit access space A19 to A9

16-bit access space A19 to A10

Modes 3, 4, 5 8-bit access space A23 to A9

16-bit access space A23 to A10

1 0 Column address: 10 bits

Compared address:

Modes 1, 2 8-bit access space A19 to A10

16-bit access space A19 to A11

Modes 3, 4, 5 8-bit access space A23 to A10

16-bit access space A23 to A11

1 Il legal setting

Bit 5—

CAS

Output Pin Select (CSEL): Selects the

UCAS

and

LCAS

output pins when areas 2

to 5 are designated as DRAM space.

Bit 5

CSEL Description

0 PB4 and PB5 selected as

UCAS

and

LCAS

output pins (Initial value)

HWR

and

LWR

selected as

UCAS

and

LCAS

output pins

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Bit 4—Refresh Cycle Enable (RCYCE): Enables or disables CAS-before-RAS refresh cycle

insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not

inserted regardless of the setting of this bit.

Bit 4

RCYCE Description

0 Refresh cycles disabled (Initial value)

1 DRAM refresh cycles enabled

Bit 3—Reserved: This bit cannot be modified and is always read as 1.

Bit 2—TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (TP) is

to be used for DRAM read/write cycles and CAS-before-RAS refresh cycles.

The setting of this bit does not affect the self-refresh function.

Bit 2

TPC Description

0 1-state precharge cycle inser ted (Initial value)

1 2-state precharge cycle inserted

Bit 1—

RAS

CAS

Wait (RCW): Controls wait state (Trw) insertion between Tr and Tc1 in

DRAM read/write cycles. The setting of this bit does not affect refresh cycles.

Bit 1

RCW Description

0 Wait state (Trw) insertion disabled (Initi al value)

1 One wait state (Trw) inserted

Bit 0—Refresh Cycle Wait Control (RLW): Controls wait state (TRW) insertion for CAS-

before-RAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles.

Bit 0

RLW Description

0 Wait state (TRW) insertion disabled (Initi al value)

1 One wait state (TRW) inserted

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6.2.9 Refresh Timer Control/Status Register (RTMCSR)

CKS0 ———

0Initial value 0000111

Read/Write R/W ———R(W)*R/W R/W R/W

76543210

CMF CMIE CKS2 CKS1

Bit

RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When

the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests.

Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes. Bits 5 to 3 are

initialized to 0 by a reset and in hardware standby mode; they are not initialized in software

standby mode.

Note: * Only 0 can be written to clear the flag.

Bit 7—Compare Match Flag (CMF): Status flag that indicates a match between the values of

RTCNT and RTCOR.

Bit 7

CMF Description

0 Clearing conditions

When the chip is reset and in standby mode

Read CMF when CMF = 1, then write 0 in CMF (Initi al value)

1 Setting condition

When RTCNT = RTCOR

Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt

requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when

any of areas 2 to 5 is designated as DRAM space.

Bit 6

CMIE Description

0 The CMI interrupt requested by CMF is disabled (Initial value)

1 The CMI interrupt requested by CMF is enabled

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Bits 5 to 3—Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be

input to RTCNT from among 7 clocks obtained by dividing the system clock (φ). When the input

clock is selected with bits CKS2 to CKS0, RTCNT begins counting up.

Bit 5

CKS2 Bit 4

CKS1 Bit 3

CKS0 Description

0 0 0 Count operation halted (Initial value)

1φ/2 used as counter clock

10φ/8 used as counter clock

1φ/32 used as counter clock

100φ/128 used as counter clock

1φ/512 used as counter clock

10φ/2048 used as counter clock

1φ/4096 used as counter clock

Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 1.

6.2.10 Refresh Timer Counter (RTCNT)

0Initial value 0000000

Read/Write R/W R/W R/W R/WR/W R/W R/W R/W

76543210

Bit

RTCNT is an 8-bit readable/writable up-counter.

RTCNT is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When

RTCNT matches RTCOR (compare match), the CMF flag in RTMCSR is set to 1 and RTCNT is

cleared to H'00. If the RCYCE bit in DRCRB is set to 1 at this time, a refresh cycle is started.

Also, if the CMIE bit in RTMCSR is set to 1, a compare match interrupt (CMI) is generated.

RTCNT is initialized to H'00 by a reset and in standby mode.

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6.2.11 Refresh Time Constant Register (RTCOR)

1Initial value 1111111

Read/Write R/W R/W R/W R/WR/W R/W R/W R/W

76543210

Bit

RTCOR is an 8-bit readable/writable register that determines the interval at which RTCNT is

cleared.

RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1

in RTMCSR, and RTCNT is simultaneously cleared to H'00.

RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Note: Only byte access can be used on this register.

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6.2.12 Address Control Register (ADRCR)

ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address

update mode 2 as the address output method.

—

ADRCTL

R/W

Bit

Initial value

R/W

Reserved bits Address control

Selects address update

mode 1 or address

update mode 2

ADRCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.

Bit 1—Reserved: This bit is always read as 1. Do not write 0 to this bit.

Bit 0—Address Control (ADRCTL): Selects the address output method.

Bit 0

ADRCTL Description

0 Address update mode 2 is selected

1 Address update mode 1 is selected (Initi al value)

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6.3 Operation

6.3.1 Area Division

The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the

1-Mbyte modes, or 2-Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the

memory map.

H' 00000

H' 1FFFF

H' 20000

H' 3FFFF

H' 40000

H' 5FFFF

H' 60000

H' 7FFFF

H' 80000

H' 9FFFF

H' A0000

H' BFFFF

H' C0000

H' DFFFF

H' E0000

H' FFFFF

Area 0 (128 kbytes)

Area 1 (128 kbytes)

Area 2 (128 kbytes)

Area 3 (128 kbytes)

Area 4 (128 kbytes)

Area 5 (128 kbytes)

Area 6 (128 kbytes)

Area 7 (128 kbytes)

H' 000000

H' 1FFFFF

H' 200000

H' 3FFFFF

H' 400000

H' 5FFFFF

H' 600000

H' 7FFFFF

H' 800000

H' 9FFFFF

H' A00000

H' BFFFFF

H' C00000

H' DFFFFF

H' E00000

H' FFFFFF

Area 0 (2 Mbytes)

Area 1 (2 Mbytes)

Area 2 (2 Mbytes)

Area 3 (2 Mbytes)

Area 4 (2 Mbytes)

Area 5 (2 Mbytes)

Area 6 (2 Mbytes)

Area 7 (2 Mbytes)

(a) 1-Mbyte modes (modes 1, and 2) (b) 16-Mbyte modes (modes 3, 4, and 5)

Figure 6.2 Access Area Map for Each Operating Mode

Chip select signals (

0 to

7) can be output for areas 0 to 7. The bus specifications for each

area are selected in ABWCR, ASTCR, WCRH, and WCRL.

In 16-Mbyte mode, the area division units can be selected with the RDEA bit in BCR.

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H'000000

H'1FFFFF

H'200000

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

H'FEE000

H'FEE0FF

H'FEE100

H'FF7FFF

H'FF8000

H'FF8FFF

H'FF9000

H'FFEF1F

H'FFEF20

H'FFFEFF

H'FFFF00

H'FFFF1F

H'FFFF20

H'FFFFE9

H'FFFFEA

H'FFFFFF

Area 0

2 Mbytes

Area 1

2 Mbytes

Area 2

2 Mbytes

Area 3

2 Mbytes

Area 4

2 Mbytes

Area 5

2 Mbytes

Area 6

2 Mbytes

Area 7

1.93 Mbytes

On-chip registers (1)

Area 7

67.5 kbytes

On-chip RAM

4 kbytes

On-chip registers (2)

Area 7

22 bytes

Area 0

2 Mbytes

Area 1

2 Mbytes

Area 2

8 Mbytes

Area 3

2 Mbytes

Area 4

1.93 Mbytes

Area 5

4 kbytes

On-chip RAM

4 kbytes*

On-chip registers (2)

Area 7

22 bytes

Area 6

23.75 kbytes

On-chip registers (1)

2 Mbytes2 Mbytes2 Mbytes2 Mbytes2 Mbytes 2 Mbytes2 Mbytes2 Mbytes

Absolute

address 16 bits

Absolute

address 8 bits

(A) Memory map when RDEA = 1 (b) Memory map when RDEA = 0

Reserved 39.75 kbytes

Note: * Area 6 when the RAME bit is cleared.

Figure 6.3 Memory Map in 16-Mbyte Mode

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6.3.2 Bus Specifications

The external space bus specifications consist of three elements: (1) bus width, (2) number of

access states, and (3) number of program wait states.

The bus width and number of access states for on-chip memory and registers are fixed, and are

not affected by the bus controller.

Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-

bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is

selected functions as a16-bit access space.

If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-

bit access, 16-bit bus mode is set.

Number of Access States: Two or three access states can be selected with ASTCR. An area for

which two-state access is selected functions as a two-state access space, and an area for which

three-state access is selected functions as a three-state access space.

DRAM space is accessed in four states regardless of the ASTCR settings.

When two-state access space is designated, wait insertion is disabled.

Number of Program Wait States: When three-state access space is designated in ASTCR, the

number of program wait states to be inserted automatically is selected with WCRH and WCRL.

From 0 to 3 program wait states can be selected.

When ASTCR is cleared to 0 for DRAM space, a program wait (Tc1-Tc2 wait) is not inserted.

Also, no program wait is inserted in burst ROM space burst cycles.

Table 6.3 shows the bus specifications for each basic bus interface area.

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Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)

ABWCR ASTCR WCRH/WCRL Bus Specifications (Basic Bus Interface)

ABWn ASTn Wn1 Wn0 Bus Width Access St ates Program Wait States

00——16 2 0

100 3 0

10 2

10——82 0

100 3 0

10 2

Note: n = 7 to 0

6.3.3 Memory Interfaces

The H8/3068F memory interfaces comprise a basic bus interface that allows direct connection of

ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst

ROM interface that allows direct connection of burst ROM. The interface can be selected

independently for each area.

An area for which the basic bus interface is designated functions as normal space, an area for

which the DRAM interface is designated functions as DRAM space, and area 0 for which the

burst ROM interface is designated functions as burst ROM space.

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6.3.4 Chip Select Signals

For each of areas 0 to 7, the H8/3068F can output a chip select signal (

0 to

7) that goes low

when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing of

n signal.

Output of

0 to

3: Output of

0 to

3 is enabled or disabled in the data direction register

(DDR) of the corresponding port.

In the expanded modes with on-chip ROM disabled, a reset leaves pin

0 in the output state and

pins

1 to

3 in the input state. To output chip select signals

1 to

3, the corresponding

DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins

0 to

3 in the input state. To output chip select signals

0 to

3, the corresponding DDR

bits must be set to 1. For details, see section 8, I/O Ports.

Output of

4 to

7: Output of

4 to

7 is enabled or disabled in the chip select control

4 to

7 in the input state. To output chip select signals

4 to

7, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports.

Address External address in area n

Figure 6.4

n Signal Output Timing (n = 0 to 7)

When the on-chip ROM, on-chip RAM, and on-chip registers are accessed,

0 to

7 remain

high. The

n signals are decoded from the address signals. They can be used as chip select

signals for SRAM and other devices.

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6.3.5 Address Output Method

The H8/3068F provides a choice of two address update methods: either the same method as in the

previous H8/300H Series (address update mode 1), or a method in which address update is

restricted to external space accesses or self-refresh cycles (address update mode 2).

Figure 6.5 shows examples of address output in these two update modes.

On-chip

memory cycle On-chip

memory cycle

External

read cycle On-chip

memory cycle External

read cycle

Address update

mode 1

Address update

mode 2

Figure 6.5 Sample Address Output in Each Address Update Mode

(Basic Bus Interface, 3-State Space)

Address Update Mode 1: Address update mode 1 is compatible with the previous H8/300H

Series. Addresses are always updated between bus cycles.

Address Update Mode 2: In address update mode 2, address updating is performed only in

external space accesses or self-refresh cycles. In this mode, the address can be retained between

an external space read cycle and an instruction fetch cycle (on-chip memory) by placing the

program in on-chip memory. Address update mode 2 is therefore useful when connecting a

device that requires address hold time with respect to the rise of the

strobe.

Switching between address update modes 1 and 2 is performed by means of the ADRCTL bit in

ADRCR. The initial value of ADRCR is the address update mode 1 setting, providing

compatibility with the previous H8/300H Series.

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Cautions: When using address update modes, the following points should be noted.

• When address update mode 2 is selected, the address in an internal space (on-chip memory or

internal I/O) access cycle is not output externally.

• In order to secure address holding with respect to the rise of

, when address update mode 2

is used an external space read access must be completed within a single access cycle. For

example, in a word access to 8-bit access space, the bus cycle is split into two as shown in

figure 6.6., and so there is not a single access cycle. In this case, address holding is not

guaranteed at the rise of

between the first (even address) and second (odd address) access

cycles (area inside the ellipse in the figure).

On-chip

memory cycle On-chip

memory cycle

External read cycle

(8-bit space word access)

Address update

mode 2

Even address Odd address

Figure 6.6 Example of Consecutive External Space Accesses in Address Update Mode 2

• When address update mode 2 is selected, in a DRAM space CAS-before-RAS (CBR) refresh

cycle the previous address is retained (the area 2 start address is not output).

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6.4 Basic Bus Interface

6.4.1 Overview

The basic bus interface enables direct connection of ROM, SRAM, and so on.

The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL

(see table 6.3).

6.4.2 Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus

controller has a data alignment function, and when accessing external space, controls whether the

upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications

for the area being accessed (8-bit access area or 16-bit access area) and the data size.

8-Bit Access Areas: Figure 6.7 illustrates data alignment control for 8-bit access space. With 8-

bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data

that can be accessed at one time is one byte: a word access is performed as two byte accesses, and

a longword access, as four byte accesses.

D15 D8D7D0

Upper data bus Lower data bus

1st bus cycle

2nd bus cycle

1st bus cycle

2nd bus cycle

3rd bus cycle

4th bus cycle

Byte size

Word size

Longword size

Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Area)

16-Bit Access Areas: Figure 6.8 illustrates data alignment control for 16-bit access areas. With

16-bit access areas, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for

accesses. The amount of data that can be accessed at one time is one byte or one word, and a

longword access is executed as two word accesses.

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In byte access, whether the upper or lower data bus is used is determined by whether the address

is even or odd. The upper data bus is used for an even address, and the lower data bus for an

odd address.

Upper data bus Lower data bus

1st bus cycle

2nd bus cycle

Byte size

Longword size

· Even address

· Odd address

Word size

Byte size

Figure 6.8 Access Sizes and Data Alignment Control (16-Bit Access Area)

6.4.3 Valid Strobes

Table 6.4 shows the data buses used, and the valid strobes, for the access spaces.

In a read, the

signal is valid for both the upper and the lower half of the data bus.

In a write, the

HWR

signal is valid for the upper half of the data bus, and the

LWR

signal for the

lower half.

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Table 6.4 Data Buses Used and Valid Strobes

Area Access

Size Read/Write Address Valid Strobe Upper Data Bus

(D15 to D8)Lower Data Bus

(D7 to D0)

8-bit Byte Read —

Valid Invalid

access

area Write —

HWR

Undetermined

data

16-bit Byte Read Even

Valid Invalid

access Odd Invalid Valid

area Write Even

HWR

Valid Undetermined

data

Odd

LWR

Undetermined

data Valid

Word Read —

Valid Valid

Write —

HWR

LWR

Valid Valid

Notes: 1. Undetermined data means that unpredictable data is output.

2. Invalid means that the bus is in the input state and the input is ignored.

6.4.4 Memory Areas

The initial state of each area is basic bus interface, three-state access space. The initial bus width

is selected according to the operating mode. The bus specifications described here cover basic

items only, and the following sections should be referred to for further details: 6.4, Basic Bus

Interface, 6.5, DRAM Interface, 6.8, Burst ROM Interface.

Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is

external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external

space.

When area 0 external space is accessed, the

0 signal can be output.

Either basic bus interface or burst ROM interface can be selected for area 0.

The size of area 0 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5.

Areas 1 and 6: In external expansion mode, areas 1 and 6 are entirely external space.

When area 1 and 6 external space is accessed, the

1 and

6 pin signals respectively can be

output.

Only the basic bus interface can be used for areas 1 and 6.

The size of areas 1 and 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5.

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Areas 2 to 5: In external expansion mode, areas 2 to 5 are entirely external space.

When area 2 to 5 external space is accessed, signals

2 to

5 can be output.

Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM

interface, signals

2 to

5 are used as

RAS

signals.

The size of areas 2 to 5 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5.

Area 7: Area 7 includes the on-chip RAM and registers. In external expansion mode, the space

excluding the on-chip RAM and registers is external space. The on-chip RAM is enabled when

the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to

0, the on-chip RAM is disabled and the corresponding space becomes external space .

When area 7 external space is accessed, the

7 signal can be output.

Only the basic bus interface can be used for the area 7 memory interface.

The size of area 7 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5.

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6.4.5 Basic Bus Control Signal Timing

8-Bit, Three-State-Access Areas

Figure 6.9 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper

data bus (D15 to D8) is used in accesses to these areas. The

LWR

pin is always high. Wait states

can be inserted.

Bus cycle

External address in area n

Valid

Invalid

Valid

Undetermined data

High

Address bus

to D

HWR

LWR

to D

Read access

Write access

Note: n = 7 to 0

Figure 6.9 Bus Control Signal Timing for 8-Bit, Three-State-Access Area

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8-Bit, Two-State-Access Areas

Figure 6.10 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper

data bus (D15 to D8) is used in accesses to these areas. The

LWR

pin is always high. Wait states

cannot be inserted.

Bus cycle

External address in area n

Valid

Invalid

Valid

Undetermined data

High

Address bus

CSn

D15 to D8

D7 to D0

HWR

LWR

D15 to D8

D7 to D0

Read access

Write access

Note: n = 7 to 0

T1T2

Figure 6.10 Bus Control Signal Timing for 8-Bit, Two-State-Access Area

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16-Bit, Three-State-Access Areas

Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area.

In these areas, the upper data bus (D15 to D8) is used in accesses to even addresses and the lower

data bus (D7 to D0) in accesses to odd addresses. Wait states can be inserted.

Bus cycle

Even external address in area n

Valid

Invalid

Valid

High

Address bus

CSn

to D

HWR

LWR

to D

Read access

Write access

Note: n = 7 to 0

Undetermined data

Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)

(Byte Access to Even Address)

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Bus cycle

Odd external address in area n

Valid

Invalid

Valid

Address bus

to D

HWR

LWR

to D

Read access

Write access

Note: n = 7 to 0

High

Undetermined data

Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)

(Byte Access to Odd Address)

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Bus cycle

External address in area n

Valid

Address bus

to D

HWR

LWR

to D

Read access

Write access

Note: n = 7 to 0

Valid

Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)

(Word Access)

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16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for

a 16-bit, two-state-access area. In these areas, the upper data bus (D15 to D8) is used in accesses

to even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait states

cannot be inserted.

Bus cycle

Even external address in area n

Valid

Invalid

Valid

High

Address bus

to D

HWR

LWR

to D

Read access

Write access

Note: n = 7 to 0

Undetermined data

Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)

(Byte Access to Even Address)

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Bus cycle

Odd external address in area n

Valid

Invalid

Valid

High

Address bus

to D

HWR

LWR

to D

Read access

Write access

Note: n = 7 to 0

Undetermined data

Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)

(Byte Access to Odd Address)

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Bus cycle

External address in area n

Valid

Address bus

to D

HWR

LWR

to D

Read access

Write access

Note: n = 7 to 0

Valid

Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)

(Word Access)

6.4.6 Wait Control

When accessing external space, the H8/3068F can extend the bus cycle by inserting one or more

wait states (Tw). There are two ways of inserting wait states: (1) program wait insertion and (2)

pin wait insertion using the

WAIT

pin.

Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2

state and T3 state on an individual area basis in three-state access space, according to the settings

of WCRH and WCRL.

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Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the

WAIT

pin. When external space is accessed in this state, a program wait is first inserted. If the

WAIT

pin is low at the falling edge of φ in the last T2 or TW state, another TW state is inserted. If

the

WAIT

pin is held low, TW states are inserted until it goes high.

This is useful when inserting four or more TW states, or when changing the number of TW states

for different external devices.

The WAITE bit setting applies to all areas. Pin waits cannot be inserted in DRAM space.

Figure 6.17 shows an example of the timing for insertion of one program wait state in 3-state

space.

WAIT

Address bus

Data bus

Read access

Write access Data bus

HWR, LWR

Note: indicates the timing of WAIT pin sampling.

Inserted

by program wait Inserted by WAIT pin

Read data

Write data

Figure 6.17 Example of Wait State Insertion Timing

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6.5 DRAM Interface

6.5.1 Overview

The H8/3068F is provided with a DRAM interface with functions for DRAM control signal

(

RAS

UCAS

LCAS

) output, address multiplexing, and refreshing, that direct connection of

DRAM. In the expanded modes, external address space areas 2 to 5 can be designated as DRAM

space accessed via the DRAM interface. A data bus width of 8 or 16 bits can be selected for

DRAM space by means of a setting in ABWCR. When a 16-bit data bus width is selected, CAS is

used for byte access control. In the case of × 16-bit organization DRAM, therefore, the 2-CAS

type can be connected. A fast page mode is supported in addition to the normal read and write

access modes.

6.5.2 DRAM Space and

RAS

Output Pin Settings

Designation of areas 2 to 5 as DRAM space, and selection of the

RAS

output pin for each area

designated as DRAM space, is performed by setting bits in DRCRA. Table 6.5 shows the

correspondence between the settings of bits DRAS2 to DRAS0 and the selected DRAM space and

RAS

output pin.

When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than

000 must not be performed.

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Table 6.5 Settings of Bits DRAS2 to DRAS0 and Corresponding DRAM Space (

RAS

Output Pin)

DRAS2 DRAS1 DRAS0 Area 5 Area 4 Area 3 Area 2

000Normal spaceNormal spaceNormal spaceNormal space

1 Normal space Normal space Normal space DRAM space

(

1 0 Normal space Norma l space DRAM space

(

3)DRAM space

(

1 Normal space Normal space DRAM space

(

2)*DRAM space

(

2)*

100Normal spaceDRAM space

(

4)DRAM space

(

3)DRAM space

(

1 DRAM space

(

5)DRAM space

(

4)DRAM space

(

3)DRAM space

(

1 0 DRAM space

(

4)*DRAM space

(

4)*DRAM space

(

2)*DRAM space

(

2)*

1 DRAM space

(

2)*DRAM space

(

2)*DRAM space

(

2)*DRAM space

(

2)*

Note: *A single

n pin serves as a common

RAS

output pin for a number of areas. Unused

pins can be used as input/output ports.

6.5.3 Address Multiplexing

When DRAM space is accessed, the row address and column address are multiplexed. The

address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the

number of bits in the DRAM column address. Table 6.6 shows the correspondence between the

settings of MXC1 and MXC0 and the address multiplexing method.

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Table 6.6 Settings of Bits MXC1 and MXC0 and Address Multiplexing Method

DRCRB Column

Address Address Pins

MXC1 MXC0 Bits A23 to A13 A12 A11 A10 A9A8A7A6A5A4A3A2A1A0

Row

address 008 bitsA

23 to A13 A20*A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9A8

1 9 bits A23 to A13 A12 A20*A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9

1 0 10 bits A23 to A13 A12 A11 A20*A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

1 Illegal

setting — —————————————

Column

address ——— A23 to A13 A12 A11 A10 A9A8A7A6A5A4A3A2A1A0

Note: *Row address bit A20 is not multipl exed in 1-Mbyte mode.

6.5.4 Data Bus

If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is

designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM

space. In 16-bit DRAM space, × 16-bit organization DRAM can be connected directly.

In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM

space both the upper and lower halves of the data bus, D15 to D0, are enabled.

Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2,

Data Size and Data Alignment.

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6.5.5 Pins Used for DRAM Interface

Table 6.7 shows the pins used for DRAM interfacing and their functions.

Table 6.7 DRAM Interface Pins

Pin With DRAM

Designated Name I/O Function

PB4

UCAS

Upper column

address strobe Output Upper column address strobe for DRAM

space access (when CSEL = 0 in DRCRB)

PB5

LCAS

Lower column

address strobe Output Lower column address strobe for DRAM

space access (when CSEL = 0 in DRCRB)

HWR UCAS

Upper column

address strobe Output Upper column address strobe for DRAM

space access (when CSEL = 1 in DRCRB)

LWR LCAS

Lower column

address strobe Output Lower column address strobe for DRAM

space access (when CSEL = 1 in DRCRB)

RAS

2Row address

strobe 2 Output Row address strobe for DRAM space

access

RAS

3Row address

strobe 3 Output Row address strobe for DRAM space

access

RAS

4Row address

strobe 4 Output Row address strobe for DRAM space

access

RAS

5Row address

strobe 5 Output Row address strobe for DRAM space

access

RD WE

Write enable Output Write enable for DRAM space write

access*

P80

RFSH

Refresh Output Goes low in refresh cycle

A12 to A0A12 to A0Address Output Row address/column address multiplexed

output

D15 to D0D15 to D0Data I/O Data input/output pins

Note: *Fixed high in a read access.

6.5.6 Basic Timing

Figure 6.18 shows the basic access timing for DRAM space. The basic DRAM access timing is

four states: one precharge cycle (Tp) state, one row address output cycle (Tr) state, and two

column address output cycle (Tc1, Tc2) states. Unlike the basic bus interface, the corresponding

bits in ASTCR control only enabling or disabling of wait insertion between Tc1 and Tc2, and do

not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0,

wait states cannot be inserted between Tc1 and Tc2 in the DRAM access cycle.

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If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM

space when

HWR

and

LWR

are selected as the

UCAS

and

LCAS

output pins, an idle cycle (Ti) is

inserted unconditionally immediately after the DRAM access cycle. See section 6.9, Idle Cycle,

for details.

to A

CSn (RAS)

Tr T

(UCAS / LCAS)

/PB

RD(WE)

to D

RD(WE)

to D

(UCAS / LCAS)

/PB

Row Column

Read access

Write access

Note: n = 2 to 5

High level

Figure 6.18 Basic Access Timing (CSEL = 0 in DRCRB)

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6.5.7 Precharge State Control

In the H8/3068F, provision is made for the DRAM RAS precharge time by always inserting one

RAS precharge state (Tp) when DRAM space is accessed. This can be changed to two Tp states

by setting the TPC bit to 1 in DRCRB. The optimum number of Tp cycles should be set

according to the DRAM connected and the operating frequency of the H8/3068F chip. Figure

6.19 shows the timing when two Tp states are inserted.

When the TCP bit is set to 1, two Tp states are also used for CAS-before-RAS refresh cycles.

A23 to A0

CSn (RAS)

Tp1 Tr Tc1

(UCAS /LCAS)

PB4 /PB5

RD(WE)

D15 to D0

RD(WE)

D15 to D0

(UCAS /LCAS)

PB4 /PB5

Tc2

Tp2

Note: n = 2 to 5

Row

High level

Column

Read access

Write access

Figure 6.19 Timing with Two Precharge States (CSEL = 0 in DRCRB)

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6.5.8 Wait Control

In a DRAM access cycle, wait states can be inserted (1) between the Tr state and Tc1 state, and (2)

between the Tc1 state and Tc2 state.

Insertion of Trw Wait State between Tr and Tc1: One Trw state can be inserted between Tr and

Tc1 by setting the RCW bit to 1 in DRCRB.

Insertion of Tw Wait State(s) between Tc1 and Tc2: When the bit in ASTCR corresponding to an

area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted between the Tc1

state and Tc2 state by means of settings in WCRH and WCRL.

Figure 6.20 shows an example of the timing for wait state insertion.

The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh

cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the

WAIT

pin.

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Tr T

(UCAS /LCAS)

/PB

RD(WE)

CSn(RAS)

to D

RD(WE)

to D

(UCAS /LCAS)

/PB

to A

Trw Tw Tw

Write access

Read access

Read data

Write data

Note: n = 2 to 5

Row Column

High level

Figure 6.20 Example of Wait State Insertion Timing (CSEL = 0)

6.5.9 Byte Access Control and

CAS

Output Pin

When an access is made to DRAM space designated as a 16-bit-access area in ABWCR, column

address strobes (

UCAS

and

LCAS

) corresponding to the upper and lower halves of the external

data bus are output. In the case of × 16-bit organization DRAM, the 2-CAS type can be

connected.

Either PB4 and PB5, or

HWR

and

LWR

, can be used as the

UCAS

and

LCAS

output pins, the

selection being made with the CSEL bit in DRCRB. Table 6.8 shows the CSEL bit settings and

corresponding output pin selections.

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When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only

UCAS

is output. When the entire DRAM space is designated as 8-bit-access space and CSEL =

0, PB5 can be used as an input/output port.

Note that

RAS

down mode cannot be used when a device other than DRAM is connected to

external space and

HWR

and

LWR

are used as write strobes. In this case, also, an idle cycle (Ti)

is always inserted when an external access to other than DRAM space occurs after a DRAM

space access. For details, see section 6.9, Idle Cycle.

Table 6.8 CSEL Settings and

UCAS

and

LCAS

Output Pins

CSEL

UCAS LCAS

0PB

4PB5

HWR LWR

Figure 6.21 shows the control timing.

A23 to A0

CSn (RAS)

TpTr Tc1 Tc2

PB4(UCAS)

PB5(LCAS)

RD(WE)

Note: n = 2 to 5

Byte control

Row Column

Figure 6.21 Control Timing (Upper-Byte Write Access When CSEL = 0)

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6.5.10 Burst Operation

With DRAM, in addition to full access (normal access) in which data is accessed by outputting a

row address for each access, a fast page mode is also provided which can be used when making a

number of consecutive accesses to the same row address. This mode enables fast (burst) access

of data by simply changing the column address after the row address has been output. Burst

access can be selected by setting the BE bit to 1 in DRCRA.

Burst Access (Fast Page Mode) Operation Timing: Figure 6.22 shows the operation timing for

burst access. When there are consecutive access cycles for DRAM space, the column address and

CAS

signal output cycles (two states) continue as long as the row address is the same for

consecutive access cycles. In burst access, too, the bus cycle can be extended by inserting wait

states between Tc1 and Tc2. The wait state insertion method and timing are the same as for full

access: see section 6.5.8, Wait Control, for details.

The row address used for the comparison is determined by the bus width of the relevant area set

in bits MXC1 and MXC0 in BRCRB, and in ABWCR. Table 6.9 shows the compared row

addresses corresponding to the various settings of bits MXC1 and MXC0, and ABWCR.

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to A

CSn(RAS)

Tr T

(UCAS /LCAS)

/PB

RD(WE)

to D

(UCAS/LCAS)

/PB

to D

RD(WE)

Note: n = 2 to 5

Read access

Write access

Row Column 1 Column 2

High level

Figure 6.22 Operation Timing in Fast Page Mode

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Table 6.9 Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and

Row Address Compared in Burst Access

DRCRB ABWCR

Operating Mode MXC1 MXC0 ABWn Bus Width Compared Row Address

0 0 0 16 bits A19 to A9Modes 1 and 2

(1-Mbyte) 1 8 bits A19 to A8

1 0 16 bits A19 to A10

1 8 bits A19 to A9

1 0 0 16 bits A19 to A11

1 8 bits A19 to A10

1—— Illegal setti ng

0 0 0 16 bits A23 to A9Modes 3, 4, and 5

(16-Mbyte) 1 8 bits A23 to A8

1 0 16 bits A23 to A10

1 8 bits A23 to A9

1 0 0 16 bits A23 to A11

1 8 bits A23 to A10

1—— Illegal setti ng

Note: n = 2 to 5

RAS Down Mode and RAS Up Mode: With DRAM provided with fast page mode, as long as

accesses are to the same row address, burst operation can be continued without interruption even

if accesses are not consecutive by holding the

RAS

signal low.

• RAS Down Mode

To select RAS down mode, set the BE and RDM bits to 1 in DRCRA. If access to DRAM

space is interrupted and another space is accessed, the

RAS

signal is held low during the

access to the other space, and burst access is performed if the row address of the next DRAM

space access is the same as the row address of the previous DRAM space access. Figure 6.23

shows an example of the timing in RAS down mode.

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to A

CSn (RAS)

Tr T

(UCAS/LCAS)

/PB

to D

Note: n = 2 to 5

DRAM access DRAM access

External space

access

Figure 6.23 Example of Operation Timing in RAS Down Mode (CSEL = 0)

When RAS down mode is selected, the conditions for an asserted

RAS

n signal to return to the

high level are as shown below. The timing in these cases is shown in figure 6.24.

 When DRAM space with a different row address is accessed

 Immediately before a CAS-before-RAS refresh cycle

 When the BE bit or RDM bit is cleared to 0 in DRCRA

 Immediately before release of the external bus

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ASn

Note: n = 2 to 5

DRAM access cycle

CBR refresh cycle

DRCRA write cycle

External bus released

High-impedance

(a) Access to DRAM space with a different row address

(b) CAS-before-RAS refresh cycle

(d) External bus released

Figure 6.24

RAS

n Negation Timing when RAS Down Mode is Selected

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When RAS down mode is selected, the CAS-before-RAS refresh function provided with this

DRAM interface must always be used as the DRAM refreshing method. When a refresh

operation is performed, the

RAS

signal goes high immediately beforehand. The refresh

interval setting must be made so that the maximum DRAM

RAS

pulse width specification is

observed.

When the self-refresh function is used, the RDM bit must be cleared to 0, and RAS up mode

selected, before executing a SLEEP instruction in order to enter software standby mode.

Select RAS down mode again after exiting software standby mode.

Note that RAS down mode cannot be used when

HWR

and

LWR

are selected for

UCAS

and

LCAS

, a device other than DRAM is connected to external space, and

HWR

and

LWR

are

used as write strobes.

• RAS Up Mode

To select RAS up mode, clear the RDM bit to 0 in DRCRA. Each time access to DRAM

space is interrupted and another space is accessed, the

RAS

signal returns to the high level.

Burst operation is only performed if DRAM space is continuous. Figure 6.25 shows an

example of the timing in RAS up mode.

to A

CSn(RAS)

Tr T

to D

/PB

(UCAS/LCAS)

Note: n = 2 to 5

DRAM access DRAM access External space

access

Figure 6.25 Example of Operation Timing in RAS Up Mode

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6.5.11 Refresh Control

The H8/3068F is provided with a CAS-before-RAS (CBR) function and self-refresh function as

DRAM refresh control functions.

CAS-Before-RAS (CBR) Refreshing: To select CBR refreshing, set the RCYCE bit to 1 in

DRCRB.

With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in

RTMCSR, and a refresh request is generated when the count matches the value set in RTCOR

(compare match). At the same time, RTCNT is reset and starts counting up again from H'00.

Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. A

refresh cycle is executed after this refresh request has been accepted and the DRAM interface has

acquired the bus. Set a value in bits CKS2 to CKS0 in RTCOR that will meet the refresh interval

specification for the DRAM used. When RAS down mode is used, set the refresh interval so that

the maximum

RAS

pulse width specification is met.

RTCNT starts counting up when bits CKS2 to CKS0 are set. RTCNT and RTCOR settings

should therefore be completed before setting bits CKS2 to CKS0.

Also note that a repeat refresh request generated during a bus request, or a refresh request during

refresh cycle execution, will be ignored.

RTCNT operation is shown in figure 6.26, compare match timing in figure 6.27, and CBR refresh

timing in figures 6.28 and 6.29.

RTCNT

RTCOR

H'00

Refresh request

Figure 6.26 RTCNT Operation

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H'00

RTCNT

RTCOR

Refresh request signal

and CMF bit setting signal

Figure 6.27 Compare Match Timing

(RAS)

(UCAS/LCAS)

/PB

RD(WE)

RFSH

Address bus*Area 2 start address

High

High level

Note: * In address update mode 1, the area 2 start address is output.

In address update mode 2, the address in the preceding bus cycle is retained.

Figure 6.28 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0)

The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (TRP) state,

and two RAS output cycle (TR1, TR2) states. Either one or two states can be selected for the RAS

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precharge cycle. When the TPC bit is set to 1 in DRCRB,

RAS

signal output is delayed by one

cycle. This does not affect the timing of

UCAS

and

LCAS

output.

Use the RLW bit in DRCRB to adjust the

RAS

signal width. A single refresh wait state (TRW) can

be inserted between the TR1 state and TR2 state by setting the RLW bit to 1.

The RLW bit setting is valid only for CBR refresh cycles, and does not affect DRAM read/write

cycles. The number of states in the CBR refresh cycle is not affected by the settings in ASTCR,

WCRH, or WCRL, or by the state of the

WAIT

pin.

Figure 6.29 shows the timing when the TPC bit and RLW bit are both set to 1.

TRp1 TRP2 TR1 TRW

RD(WE)

CSn(RAS)

(UCAS/LCAS)

PB4/PB5

TR2

RFSH

Address bus*Area 2 start address

High

High level

Note: * In address update mode 1, the area 2 start address is output.

In address update mode 2, the address in the preceding bus cycle is retained.

Figure 6.29 CBR Refresh Timing (CSEL = 0, TPC = 1, RLW = 1)

DRAM must be refreshed immediately after powering on in order to stabilize its internal state.

When using the H8/3068F CAS-before-RAS refresh function, therefore, a DRAM stabilization

period should be provided by means of interrupts by another timer module, or by counting the

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number of times bit 7 (CMF) of RTMCSR is set, for instance, immediately after bits DRAS2 to

DRAS0 have been set in DRCRA.

Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of

standby mode. In this mode, refresh timing and refresh addresses are generated within the

DRAM. The H8/3068F has a function that places the DRAM in self-refresh mode when the chip

enters software standby mode.

To use the self-refresh function, set the SRFMD bit to 1 in DRCRA. When a SLEEP instruction

is subsequently executed in order to enter software standby mode, the

CAS

and

RAS

signals are

output and the DRAM enters self-refresh mode, as shown in figure 6.30.

When the chip exits software standby mode,

CAS

and

RAS

outputs go high.

The following conditions must be observed when the self-refresh function is used:

• When burst access is selected, RAS up mode must be selected before executing a SLEEP

instruction in order to enter software standby mode. Therefore, if RAS down mode has been

selected, the RDM bit in DRCRA must be cleared to 0 and RAS up mode selected before

executing the SLEEP instruction. Select RAS down mode again after exiting software standby

mode.

• The instruction immediately following a SLEEP instruction must not be located in an area

designated as DRAM space.

The self-refresh function will not work properly unless the above conditions are observed.

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(RAS)

Address bus

(UCAS)

(LCAS)

RD(WE)

RFSH

Software standby

mode Oscillation stabilization

time

High-impedance

Figure 6.30 Self-Refresh Timing (CSEL = 0)

Refresh Signal (

RFSH

): A refresh signal (

RFSH

) that transmits a refresh cycle off-chip can be

output by setting the RFSHE bit to 1 in DRCRA.

RFSH

output timing is shown in figures 6.28,

6.29, and 6.30.

6.5.12 Examples of Use

Examples of DRAM connection and program setup procedures are shown below. When the

DRAM interface is used, check the DRAM device characteristics and choose the most

appropriate method of use for that device.

Connection Examples

• Figure 6.31 shows typical interconnections when using two 2-CAS type 16-Mbit DRAMs

using a × 16-bit organization, and the corresponding address map. The DRAMs used in this

example are of the 10-bit row address × 10-bit column address type. Up to four DRAMs can

be connected by designating areas 2 to 5 as DRAM space.

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(RAS

)

(RAS

)

RD (WE)

-A

-D

-A

-D

(UCAS)

(LCAS)

RAS

UCAS

LCAS

-A

-D

RAS

UCAS

LCAS

No.1

No.2

DRAM (No.1)

H'400000

H'5FFFFE

H'600000

H'7FFFFE

H'800000

H'9FFFFE

H'A00000

H'BFFFFE

DRAM (No.2)

Normal

(RAS

)

(RAS

)

(UCAS) PB

(LCAS)

15 078

H8/3067 Group chip

2-CAS 16-Mbit DRAM

10-bit row address x 10-bit column address

x16-bit organization

(a) Interconnections (example)

(b) Address map

Area 2

Area 3

Area 4

Area 5

Figure 6.31 Interconnections and Address Map for 2-CAS 16-Mbit DRAMs with ×

××

16-Bit Organization

• Figure 6.32 shows typical interconnections when using two 16-Mbit DRAMs using a × 8-bit

organization, and the corresponding address map. The DRAMs used in this example are of the

11-bit row address × 10-bit column address type. The

2 pin is used as the common

RAS

output pin for areas 2 and 3. When the

DRAM

address space spans a number of contiguous

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areas, as in this example, the appropriate setting of bits DRAS2 to DRAS0 enables a single

pin to be used as the common

RAS

output pin for a number of areas, and makes it possible to

directly connect large-capacity DRAM with address space that spans a maximum of four

areas. Any unused

pins (in this example, the

3 pin) can be used as input/output ports.

(RAS

)

RD (WE)

, A

-A

-D

-A

-D

(UCAS)

(LCAS)

RAS

CAS

-A

-D

RAS

CAS

No.1

No.2

DRAM

(No.1)

H'400000

H'5FFFFE

H'600000

H'7FFFFE

H'800000

H'9FFFFE

H'A00000

H'BFFFFE

DRAM

(No.2)

(RAS

)

(UCAS) PB

(LCAS)

15 078

H8/3067 Group chip

2-CAS 16-Mbit DRAM

11-bit row address x 10-bit column address

x8-bit organization

(a) Interconnections (example)

(

)

Address map

16-Mbyte mode

Area 2

Area 3

Area 4

Area 5

Normal

Figure 6.32 Interconnections and Address Map for 16-Mbit DRAMs with ×

××

8-Bit

Organization

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• Figure 6.33 shows typical interconnections when using two 4-Mbit DRAMs, and the

corresponding address map. The DRAMs used in this example are of the 9-bit row address ×

10-bit column address type. In this example, upper address decoding allows multiple DRAMs

to be connected to a single area. The

RFSH

pin is used in this case, since both DRAMs must

be refreshed simultaneously. However, note that RAS down mode cannot be used in this

interconnection example.

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(RAS

)

RD (WE)

-A

-D

-A

-D

(UCAS)

(LCAS)

RAS

UCAS

LCAS

-A

-D

RAS

UCAS

LCAS

No.1

No.2

DRAM (No.1)

H'400000

H'47FFFE

H'480000

H'4FFFFE

H'500000

H'5FFFFE

DRAM (No.2)

Not used

(a) Interconnections (example)

(RAS

)

(UCAS) PB

(LCAS)

15 078

Area 2

16-Mbyte mode

(b) Address map

H8/3067 Group chip

2-CAS 4-Mbit DRAM

9-bit row address x 9-bit column addres

x16-bit organization

RFSH

Figure 6.33 Interconnections and Address Map for 2-CAS 4-Mbit DRAMs with ×

××

16-Bit

Organization

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Example of Program Setup Procedure: Figure 6.34 shows an example of the program setup

procedure.

Set ABWCR

Set RTCOR

Set bits CKS2 to CKS0 in RTMCSR

Set DRCRB

Set DRCRA

Wait for DRAM stabilization time

DRAM can be accessed

Figure 6.34 Example of Setup Procedure when Using DRAM Interface

6.5.13 Usage Notes

Note the following points when using the DRAM refresh function.

• Refresh cycles will not be executed when the external bus released state, software standby

mode, or a bus cycle is extended by means of wait state insertion. Refreshing must therefore

be performed by other means in these cases.

• If a refresh request is generated internally while the external bus is released, the first request is

retained and a single refresh cycle will be executed after the bus-released state is cleared.

Figure 6.35 shows the bus cycle in this case.

• When a bus cycle is extended by means of wait state insertion, the first request is retained in

the same way as when the external bus has been released.

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• In the event of contention with a bus request from an external bus master when a transition is

made to software standby mode, the

BACK

and strobe states may be indeterminate after the

transition to software standby mode (see figure 6.36).

When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before

executing the SLEEP instruction.

Similar contention in a transition to self-refresh mode may prevent dependable strobe

waveform output. This can also be avoided by clearing the BRLW bit to 0 in BRCR.

• Immediately after self-refreshing is cleared, external bus release is possible during a given

period until the start of a CPU cycle. Attention must be paid to the

RAS

state to ensure that

the specification for the

RAS

precharge time immediately after self-refreshing is met.

RFSH

Refresh

request

BACK

External bus released Refresh cycle CPU cycle Refresh cycle

Figure 6.35 Bus-Released State and Refresh Cycles

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BREQ

BACK

Software standby mode

Address bus

Strobe

Figure 6.36 Bus-Released State and Software Standby Mode

@SP

RAS

CAS

Oscillation stabilization

time on exit from software

standby mode

CPU internal cycle

(period in which external

bus can be released)

CPU cycle

Address

Figure 6.37 Self-Refresh Clearing

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6.6 Interval Timer

6.6.1 Operation

When DRAM is not connected to the H8/3068F chip, the refresh timer can be used as an interval

timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR, selection a clock

source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1.

Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag

in RTMCSR is set to 1 by a compare match output when the RTCOR and RTCNT values match.

The compare match signal is generated in the last state in which the values match (when RTCNT

is updated from the matching value to a new value). Accordingly, when RTCNT and RTCOR

match, the compare match signal is not generated until the next counter clock pulse. Figure 6.38

shows the timing.

H'00

RTCNT

CMF flag

RTCOR

Compare match

signal

Figure 6.38 Timing of CMF Flag Setting

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Operation in Power-Down State: The interval timer operates in sleep mode. It does not operate

in hardware standby mode. In software standby mode, RTCNT and RTMCSR bits 7 and 6 are

initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to

software standby mode.

Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the

T3 state of an RTCNT write cycle, clearing of the counter takes priority and the write is not

performed. See Figure 6.39.

H'00

RTCNT

Address bus

Internal write signal

Counter clear signal

RTCNT address

Figure 6.39 Contention between RTCNT Write and Clear

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Contention between RTCNT Write and Increment: If an increment pulse occurs in the T3

state of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See Figure

6.40.

RTCNT

Address bus RTCNT address

Internal write signal

RTCNT input clock

Counter write data

Figure 6.40 Contention between RTCNT Write and Increment

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Contention between RTCOR Write and Compare Match: If a compare match occurs in the T3

state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited.

See Figure 6.41.

RTCOR

Compare match signal

T1T2T3

N+1N

RTCNT

Internal write signal

Address bus RTCOR address

RTCOR write data

Inhibited

Figure 6.41 Contention between RTCOR Write and Compare Match

RTCNT Operation at Internal Clock Source Switchover: Switching internal clock sources

may cause RTCNT to increment, depending on the switchover timing. Table 6.10 shows the

relation between the time of the switchover (by writing to bits CKS2 to CKS0) and the operation

of RTCNT.

The RTCNT input clock is generated from the internal clock source by detecting the falling edge

of the internal clock. If a switchover is made from a high clock source to a low clock source, as

in case No. 3 in table 6.10, the switchover will be regarded as a falling edge, an RTCNT clock

pulse will be generated, and RTCNT will be incremented.

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Table 6.10 Internal Clock Switchover and RTCNT Operation

N N+1

No.

N N+1

N+2

CKS2 to CKS0

Write Timing RTCNT Operation

Low Low

switchover

Low High

switchover

Old clock source

New clock source

RTCNT clock

RTCNT

Old clock source

New clock source

RTCNT clock

RTCNT

CKS bits rewritten

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NN+1

No.

NN+1

RTCNT

N+2

1. Including switchovers from a low clock source to the halted state, and from the halted state to a low clock source.

2. Including switchover from the halted state to a high clock source.

3. Including switchover from a high clock source to the halted state.

4. The switchover is regarded as a falling edge, causing RTCNT to increment.

Notes:

CKS2 to CKS0

Write Timing RTCNT Operation

High Low

switchover

High High

switchover

Old clock source

New clock source

RTCNT clock

RTCNT

Old clock source

New clock source

RTCNT clock

CKS bits rewritten

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6.7 Interrupt Sources

Compare match interrupts (CMI) can be generated when the refresh timer is used as an interval

timer. Compare match interrupt requests are masked/unmasked with the CMIE bit in RTMCSR.

6.8 Burst ROM Interface

6.8.1 Overview

With the H8/3068F, external space area 0 can be designated as burst ROM space, and burst ROM

space interfacing can be performed. The burst ROM space interface enables 16-bit organization

ROM with burst access capability to be accessed at high speed. Area 0 is designated as burst

ROM space by means of the BROME bit in BCR.

Continuous burst access of a maximum or four or eight words can be performed on external space

area 0. Two or three states can be selected for burst access.

6.8.2 Basic Timing

The number of states in the initial cycle (full access) and a burst cycle of the burst ROM interface

is determined by the setting of the AST0 bit in ASTCR. When the AST0 bit is set to 1, wait states

can also be inserted in the initial cycle. Wait states cannot be inserted in a burst cycle.

Burst access of up to four words is performed when the BRSTS0 bit is cleared to 0 in BCR, and

burst access of up to eight words when the BRSTS0 bit is set to 1. The number of burst access

states is two when the BRSTS1 bit is cleared to 0, and three when the BRSTS1 bit is set to 1.

The basic access timing for burst ROM space is shown in figure 6.42.

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Full access Burst access

Address bus Only lower address changes

Read data Read data Read dataData bus

Figure 6.42 Example of Burst ROM Access Timing

6.8.3 Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion using the

WAIT

pin can be used in the initial cycle (full access) of the burst ROM interface.

Wait states cannot be inserted in a burst cycle.

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6.9 Idle Cycle

6.9.1 Operation

When the H8/3068F chip accesses external space, it can insert a 1-state idle cycle (TI) between

bus cycles in the following cases: (1) when read accesses between different areas occur

consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) immediately

after a DRAM space access. By inserting an idle cycle it is possible, for example, to avoid data

collisions between ROM, which has a long output floating time, and high-speed memory, I/O

interfaces, and so on.

The ICIS1 and ICIS0 bits in BCR both have an initial value of 1, so that an idle cycle is inserted

in the initial state. If there are no data collisions, the ICIS bits can be cleared.

Consecutive Reads between Different Areas: If consecutive reads between different areas

occur while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second

read cycle.

Figure 6.43 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,

each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs

in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is

inserted, and a data collision is prevented.

φT

Address bus

Data bus

Address bus

Data bus

Bus cycle A Bus cycle B Bus cycle A Bus cycle B

Data

collision

Long buffer-off

time

(a) Idle cycle not inserted (b) Idle cycle inserted

Figure 6.43 Example of Idle Cycle Operation (1) (ICIS1 = 1)

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Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to

1 in BCR, an idle cycle is inserted at the start of the write cycle.

Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.

In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from

ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.

φT

Address bus

Data bus

HWR

Address bus

Data bus

HWR

Bus cycle A Bus cycle B Bus cycle A Bus cycle B

Long buffer-off

time Data

collision

(a) Idle cycle not inserted (b) Idle cycle inserted

Figure 6.44 Example of Idle Cycle Operation (2) (ICIS0 = 1)

External Address Space Access Immediately after DRAM Space Access: If a DRAM space

access is followed by a non-DRAM external access when

HWR

and

LWR

have been selected as

the

UCAS

and

LCAS

output pins by means of the CSEL bit in DRCRB, a Ti cycle is inserted

regardless of the settings of bits ICIS0 and ICIS1 in BCR. Figure 6.45 shows an example of the

operation.

This is done to prevent simultaneous changing of the

HWR

and

LWR

signals used as

UCAS

and

LCAS

in DRAM space and

n for the space in the next cycle, and so avoid an erroneous write

to the external device in the next cycle.

A Ti cycle is not inserted when PB4 and PB5 have been selected as the

UCAS

and

LCAS

output

pins.

In the case of consecutive DRAM space access precharge cycles (Tp), the ICIS0 and ICIS1 bit

settings are invalid. In the case of consecutive reads between different areas, for example, if the

second access is a DRAM access, only a Tp cycle is inserted, and a Ti cycle is not. The timing in

this case is shown in figure 6.46.

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Address bus

Simultaneous change of

HWR/LWR and CSn

Tp Tr Tc1 Tc2

Bus cycle A

(DRAM access cycle)

HWR/LWR

(UCAS/LCAS)

T1 T2

Bus cycle B

CSn

Tp Tr Tc1 Tc2 T1Ti T2

Address bus

HWR/LWR

(UCAS/LCAS)

CSn

Bus cycle A

(DRAM access cycle) Bus cycle B

(

)

Idle c

cle not inserted

(

)

Idle c

cle inserted

Figure 6.45 Example of Idle Cycle Operation (3) (

HWR

LWR

Used as

UCAS

LCAS

)

Address bus

T1 T2 T3

Address bus

UCAS/LCAS

Tp Tc1Tr Tc2

External read DRAM space read

Figure 6.46 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles)

Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of

and the fall

(assertion) of

CSn

may occur simultaneously. An example of the operation is shown in figure

6.47.

If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in

BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0

bit is cleared to 0, the

negation in the first read cycle and the

CSn

assertion in the following

bus cycle will occur simultaneously. Therefore, depending on the output delay time of each

signal, it is possible that the low-level output of

in the preceding read cycle and the low-level

output of

CSn

in the following bus cycle will overlap.

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A setting whereby idle cycle insertion is not performed can be made only when

and

CSn

not change simultaneously, or when it does not matter if they do.

Address bus

T1 T2 T3

Bus cycle A

T1 T2

(a) Idle cycle not inserted

T1 T2 T3 Ti T2

(b) Idle cycle inserted

Simultaneous change of RD and CSn

Possibility of mutual overlap

CSn

Address bus

CSn

Bus cycle B Bus cycle A Bus cycle B

Figure 6.47 Example of Idle Cycle Operation (5)

6.9.2 Pin States in Idle Cycle

Table 6.11 shows the pin states in an idle cycle.

Table 6.11 Pin States in Idle Cycle

Pins Pin State

A23 to A0Next cycle address value

D15 to D0High impedance

nHigh*

UCAS

LCAS

High

HWR

High

LWR

High

Note: *Remains low in DRAM space RAS down mode.

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6.10 Bus Arbiter

The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There

are four bus masters: the CPU, DMA controller (DMAC), DRAM interface, and an external bus

master. When a bus master has the bus right it can carry out read, write, or refresh access. Each

bus master uses a bus request signal to request the bus right. At fixed times the bus arbiter

determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can

the operate using the bus.

The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and

returns an acknowledge signal to the bus master. When two or more bus masters request the bus,

the highest-priority bus master receives an acknowledge signal. The bus master that receives an

acknowledge signal can continue to use the bus until the acknowledge signal is deactivated.

The bus master priority order is:

(High) External bus master > DRAM interface > DMAC > CPU (Low)

The bus arbiter samples the bus request signals and determines priority at all times, but it does not

always grant the bus immediately, even when it receives a bus request from a bus master with

higher priority than the current bus master. Each bus master has certain times at which it can

release the bus to a higher-priority bus master.

6.10.1 Operation

CPU: The CPU is the lowest-priority bus master. If the DMAC, DRAM interface, or an external

bus master requests the bus while the CPU has the bus right, the bus arbiter transfers the bus right

to the bus master that requested it. The bus right is transferred at the following times:

• The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two

consecutive byte accesses, however, the bus right is not transferred between the two byte

accesses.

• If another bus master requests the bus while the CPU is performing internal operations, such

as executing a multiply or divide instruction, the bus right is transferred immediately. The

CPU continues its internal operations.

• If another bus master requests the bus while the CPU is in sleep mode, the bus right is

transferred immediately.

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DMAC: When the DMAC receives an activation request, it requests the bus right from the bus

arbiter. If the DMAC is bus master and the DRAM interface or an external bus master requests

the bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested

the bus. The bus right is transferred at the following times.

The bus right is transferred when the DMAC finishes transferring one byte or one word. A

DMAC transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred

between the read cycle and the write cycle.

There is a priority order among the DMAC channels. For details see section 7.4.9, Multiple-

Channel Operation.

DRAM Interface: The DRAM interface requests the bus right from the bus arbiter when a

refresh cycle request is issued, and releases the bus at the end of the refresh cycle. For details see

section 6.5, DRAM Interface.

External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an

external bus master. The external bus master has highest priority, and requests the bus right from

the bus arbiter y driving the

BREQ

signal low. Once the external bus master acquires the bus, it

keeps the bus until the

BREQ

signal goes high. While the bus is released to an external bus

master, the H8/3068F chip holds the address bus, data bus, bus control signals (

HWR

and

LWR

), and chip select signals (

n: n = 7 to 0) in the high-impedance state, and holds the

BACK

pin in the low output state.

The bus arbiter samples the

BREQ

pin at the rise of the system clock (φ). If

BREQ

is low, the

bus is released to the external bus master at the appropriate opportunity. The

BREQ

signal

should be held low until the

BACK

signal goes low.

When the

BREQ

pin is high in two consecutive samples, the

BACK

pin is driven high to end the

bus-release cycle.

Figure 6.48 shows the timing when the bus right is requested by an external bus master during a

read cycle in a two-state access area. There is a minimum interval of three states from when the

BREQ

signal goes low until the bus is released.

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BACK

(1) (2) (3) (4) (5) (6)

BREQ

HWR, LWR

Data bus

Address bus

CPU cycles CPU cyclesExternal bus released

High

Address

Minimum 3 cycles

High-impedance

Figure 6.48 Example of External Bus Master Operation

In the event of contention with a bus request from an external bus master when a transition is

made to software standby mode, the

BACK

and strobe states may be indeterminate after the

transition to software standby mode (see figure 6.36).

When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before

executing the SLEEP instruction.

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6.11 Regi ster and Pin Input Timing

6.11.1 Register Write Timing

ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR,

WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.49 shows the timing

when an instruction fetched from area 0 changes area 0 from three-state access to two-state

access.

φT

Address bus

3-state access to area 0 2-state access to area 0

ASTCR address

Figure 6.49 ASTCR Write Timing

DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the

n pin to switch between

n output and generic input takes effect starting from the T3 state of

the DDR write cycle. Figure 6.50 shows the timing when the

1 pin is changed from generic

input to

1 output.

φT1T2T3

CS1

Address bus

h-impedance

P8DDR address

Figure 6.50 DDR Write Timing

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BRCR Write Timing: Data written to BRCR to switch between A23, A22, A21, or A20 output and

generic input or output takes effect starting from the T3 state of the BRCR write cycle. Figure

6.51 shows the timing when a pin is changed from generic input to A23, A22, A21, or A20 output.

φT

to PA

to A

)

Address bus BRCR address

High-impedance

Figure 6.51 BRCR Write Timing

6.11.2

BREQ

Pin Input Timing

After driving the

BREQ

pin low, hold it low until

BACK

goes low. If

BREQ

returns to the high

level before

BACK

goes lows, the bus arbiter may operate incorrectly.

To terminate the external-bus-released state, hold the

BREQ

signal high for at least three states.

BREQ

is high for too short an interval, the bus arbiter may operate incorrectly.

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Section 7 DM A Controller

7.1 Overview

The H8/3068F has an on-chip DMA controller (DMAC) that can transfer data on up to four

channels.

When the DMA controller is not used, it can be independently halted to conserve power. For

details see section 20.6, Module Standby Function.

7.1.1 Features

DMAC features are listed below.

• Selection of short address mode or full address mode

Short address mode

 8-bit source address and 24-bit destination address, or vice versa

 Maximum four channels available

 Selection of I/O mode, idle mode, or repeat mode

Full address mode

 24-bit source and destination addresses

 Maximum two channels available

 Selection of normal mode or block transfer mode

• Directly addressable 16-Mbyte address space

• Selection of byte or word transfer

• Activation by internal interrupts, external requests, or auto-request (depending on transfer

mode)

 16-bit timer compare match/input capture interrupts (×3)

 Serial communication interface (SCI channel 0) transmit-data-empty/receive-data-full

interrupts

 External requests

 Auto-request

 A/D converter conversion-end interrupt

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7.1.2 Block Diagram

Figure 7.1 shows a DMAC block diagram.

IMIA0

IMIA1

IMIA2

ADI

TXI0

RXI0

DREQ

TEND

DEND0A

DEND0B

DEND1A

DEND1B

DTCR0A

DTCR0B

DTCR1A

DTCR1B

Control logic

Data buffer

Address buffer

Arithmetic-logic unit

MAR0A

MAR0B

MAR1A

MAR1B

IOAR0A

IOAR0B

IOAR1A

IOAR1B

ETCR0A

ETCR0B

ETCR1A

ETCR1B

Internal address bus

Internal

interrupts

Interrupt

signals

Internal data bus

Module data bus

Legend

DTCR:

MAR:

IOAR:

ETCR:

Data transfer control register

Memory address register

I/O address register

Execute transfer count register

Channel

Figure 7.1 Block Diagram of DMAC

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7.1.3 Functional Overview

Table 7.1 gives an overview of the DMAC functions.

Table 7.1 DMAC Functional Overview

Address

Reg. Le ngth

Transfer Mode Ac tiva tion Source Destina-

tion

Short

address

mode

I/O mode

• Transfers one byte or one word

per request

• Increments or decrements the memory

address by 1 or 2

• Executes 1 to 65,536 transfers

• Compare match/input

capture A interrupts from 16-

bit timer channels

0 to 2

• Transmit-data-empty

interrupt from SCI channel 0

24 8

Idle mode

• Transfers one byte or one word per

request

• Holds the memory address fixed

• Conversion-end interrupt

from A/D converter

• Receive-data-full interrupt

from SCI channel 0

824

• Executes 1 to 65,536 transfers

Repeat mode

• Transfers one byte or one word per

request

• Increments or decrements the memory

address by 1 or 2

• Executes a specified number (1 to 255)

of transfers, then returns to the initial

state and continues

• External request 24 8

Full

address

mode

Normal mode

• Auto-request

 Retains the transfer request

internally

 Executes a specified number(1 to

65,536) of transfers continuously

 Selection of burst mode or cycle-

steal mode

• External request

 Transfers one byte or one word per

request

 Executes 1 to 65,536 transfers

• Auto-request

• External request 24 24

Block transfer

• Transfers one block of a specified size

per request

• Executes 1 to 65,536 transfers

• Allows either the source or destination

to be a fixed block area

• Block size can be 1 to 255 bytes or

words

• Compare match/ input

capture A interrupts from 16-

bit timer channels 0 to 2

• External request

• Conversion-end interrupt

from A/D converter

24 24

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7.1.4 Input/Output Pins

Table 7.2 lists the DMAC pins.

Table 7.2 DMAC Pins

Channel Name Abbrevia-

tion Input/

Output Function

0 DMA request 0

DREQ

0Input External request for DMAC channel 0

Transfer end 0

TEND

0Output Transfer end on DMAC channel 0

1 DMA request 1

DREQ

1Input External request for DMAC channel 1

Transfer end 1

TEND

1Output Transfer end on DMAC channel 1

Note: External requests cannot be made to channel A in short address mode.

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7.1.5 Register Configuration

Table 7.3 lists the DMAC registers.

Table 7.3 DMAC Registers

Channel Address*Name Abbreviation R/W Initial Value

0 H'FFF20 Memory address register 0AR MAR0AR R/W Undetermined

H'FFF21 Memory address register 0AE MAR0AE R/W Undetermined

H'FFF22 Memory address register 0AH MAR0AH R/W Undetermined

H'FFF23 Memory address register 0AL MAR0AL R/W Undetermined

H'FFF26 I/O address register 0A IOAR0A R/W Undetermined

H'FFF24 Execute transfer count register 0AH ETCR0AH R/W Undetermined

H'FFF25 Execute transfer count register 0AL ETCR0AL R/W Undetermined

H'FFF27 Data transfer control register 0A DTCR0A R/W H'00

H'FFF28 Memory address register 0BR MAR0BR R/W Undetermined

H'FFF29 Memory address register 0BE MAR0BE R/W Undetermined

H'FFF2A Memory address register 0BH MAR0BH R/W Undetermined

H'FFF2B Memory address register 0BL MAR0BL R/W Undetermined

H'FFF2E I/O address register 0B IOAR0B R/W Undetermined

H'FFF2C Execute transfer count register 0BH ETCR0BH R/W Undetermined

H'FFF2D Execute transfer count register 0BL ETCR0BL R/W Undetermined

H'FFF2F Data transfer control register 0B DTCR0B R/W H'00

1 H'FFF30 Memory address register 1AR MAR1AR R/W Undetermined

H'FFF31 Memory address register 1AE MAR1AE R/W Undetermined

H'FFF32 Memory address register 1AH MAR1AH R/W Undetermined

H'FFF33 Memory address register 1AL MAR1AL R/W Undetermined

H'FFF36 I/O address register 1A IOAR1A R/W Undetermined

H'FFF34 Execute transfer count register 1AH ETCR1AH R/W Undetermined

H'FFF35 Execute transfer count register 1AL ETCR1AL R/W Undetermined

H'FFF37 Data transfer control register 1A DTCR1A R/W H'00

H'FFF38 Memory address register 1BR MAR1BR R/W Undetermined

H'FFF39 Memory address register 1BE MAR1BE R/W Undetermined

H'FFF3A Memory address register 1BH MAR1BH R/W Undetermined

H'FFF3B Memory address register 1BL MAR1BL R/W Undetermined

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Channel Address*Name Abbreviation R/W Initial Value

1 H'FFF3E I/O address register 1B IOAR1B R/W Undetermined

H'FFF3C Execute transfer count register 1BH ETCR1BH R/W Undetermined

H'FFF3D Execute transfer count register 1BL ETCR1BL R/W Undetermined

H'FFF3F Data transfer control register 1B DTCR1B R/W H'00

Note: *The lower 20 bits of the address are indicated.

7.2 Register Descriptions (1) (Short Address Mode)

In short address mode, transfers can be carried out independently on channels A and B. Short

address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA)

as indicated in table 7.4.

Table 7.4 Selection of Short and Full Address Modes

Channel Bit 2

DTS2A Bit 1

DTS1A Description

0 1 1 DMAC channel 0 operates as one channel in full address mode

Other than above DMAC channels 0A and 0B operate as two independent channels

in short address mode

1 1 1 DMAC channel 1 operates as one channel in full address mode

Other than above DMAC channels 1A and 1B operate as two independent channels

in short address mode

7.2.1 Memory Address Registers (MAR)

A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or

destination address. The transfer direction is determined automatically from the activation source.

An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits

of MARR are reserved; they cannot be modified and are always read as 1.

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Bit

Initial value

Read/Write

—

Source or destination address

—

R/W

Undetermined

R/W

MARR MARE MARH MARL

An MAR functions as a source or destination address register depending on how the DMAC is

activated: as a destination address register if activation is by a receive-data-full interrupt from

serial communication interface (SCI) channel 0 or by an A/D converter conversion-end interrupt,

and as a source address register otherwise.

The MAR value is incremented or decremented each time one byte or word is transferred,

automatically updating the source or destination memory address. For details, see section 7.3.4,

Data Transfer Control Registers (DTCR).

The MARs are not initialized by a reset or in standby mode.

7.2.2 I/O Address Registers (IOAR)

An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or

destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits

are all 1 (H'FFFF).

Bit

Initial value

Read/Write

R/W

Source or destination address

Undetermined

An IOAR functions as a source or destination address register depending on how the DMAC is

activated: as a destination address register if activation is by a receive-data-full interrupt from

serial communication interface (SCI) channel 0 or by an A/D converter conversion-end interrupt,

and as a source address register otherwise.

The IOAR value is held fixed. It is not incremented or decremented when a transfer is executed.

The IOARs are not initialized by a reset or in standby mode.

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7.2.3 Execute Transfer Count Registers (ETCR)

An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the

number of transfers to be executed. These registers function in one way in I/O mode and idle

mode, and another way in repeat mode.

• I/O mode and idle mode

Bit

Initial value

Read/Write

R/W

Transfer counter

Undetermined

R/W

In I/O mode and idle mode, ETCR functions as a 16-bit counter. The count is decremented by

1 each time one transfer is executed. The transfer ends when the count reaches H'0000.

• Repeat mode

Bit

Initial value

Read/Write

R/W

Undetermined

Transfer counter

ETCRH

Bit

Initial value

Read/Write

R/W

Undetermined

Initial count

ETCRL

In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial

transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH

reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated.

The ETCRs are not initialized by a reset or in standby mode.

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7.2.4 Data Transfer Control Registers (DTCR)

A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the

operation of one DMAC channel.

Bit

Initial value

Read/Write

DTE

R/W

DTSZ

R/W

DTID

R/W

RPE

R/W

DTIE

R/W

DTS0

R/W

DTS2

R/W

DTS1

R/W

Data transfer enable

Enables or disables

data transfer

Data transfer interrupt enable

Enables or disables the CPU interrupt

at the end of the transfer

Data transfer select

These bits select the data

transfer activation source

Data transfer size

Selects byte or

word size

Data transfer

increment/decrement

Selects whether to

increment or decrement

the memory address

Repeat enable

Selects repeat

mode

The DTCRs are initialized to H'00 by a reset and in standby mode.

Bit 7—Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the

DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer

when activated as specified by bits DTS2 to DTS0. When DTE is 0, the channel is disabled and

does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then

writing 1.

Bit 7

DTE Description

0 Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0 (Initial value)

when the specified number of transfers have been completed

1 Data transfer is enabled

If DTIE is set to 1, a CPU interrupt is requested when DTIE is cleared to 0.

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Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.

Bit 6

DTSZ Description

0 Byte-size transfer (Initial value)

1 Word-size transfer

Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or

decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode.

Bit 5

DTID Description

0 MAR is incremented after each data transfer (Initial val ue)

• If DTSZ = 0, MAR is incremented by 1 after each transfer

• If DTSZ = 1, MAR is incremented by 2 after each transfer

1 MAR is decremented after each data transfer

• If DTSZ = 0, MAR is decremented by 1 after each transfer

• If DTSZ = 1, MAR is decremented by 2 after each transfer

MAR is not incremented or decremented in idle mode.

Bit 4—Repeat Enable (RPE): Selects whether to transfer data in I/O mode, idle mode, or repeat

mode.

Bit 4

RPE Bit 3

DTIE Description

0 0 I/O mode (Initi al value)

1 0 Repeat mode

1 Idle mode

Operations in these modes are described in sections 7.4.2, I/O Mode, 7.4.3, Idle Mode, and 7.4.4,

Repeat Mode.

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Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt

(DEND) requested when the DTE bit is cleared to 0.

Bit 3

DTIE Description

0 The DEND interrupt requested by DTE is disabled (Initial value)

1 The DEND interrupt requested by DTE is enabled

Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer

activation source. Some of the selectable sources differ between channels A and B.

Bit 2

DTS2 Bit 1

DTS1 Bit 0

DTS0 Description

0 0 0 Compare match/input capture A interrupt from 16-bit timer channel 0

(Initi al value)

1 Compare match/input capture A interrupt from 16-bit timer channel 1

1 0 Compare match/input capture A interrupt from 16-bit timer channel 2

1 Conversi on-end interrupt from A/D converter

1 0 0 Transmit-data-empty interrupt from SCI channel 0

1 Recei ve-data-full interrupt from SCI channel 0

1 0 Fall ing edge of

DREQ

input (channel B)

Transfer in ful l address mode (channel A)

1 Low level of

DREQ

input (channel B)

Transfer in ful l address mode (channel A)

Note: See section 7.3.4, Data Transfer Control Registers (DTCR).

The same internal interrupt can be selected as an activation source for two or more channels at

once. In that case the channels are activated in a priority order, highest-priority channel first. For

the priority order, see section 7.4.9, Multiple-Channel Operation.

When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a

CPU interrupt.

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7.3 Register Descriptions (2) (Full Address Mode)

In full address mode the A and B channels operate together. Full address mode is selected as

indicated in table 7.4.

7.3.1 Memory Address Registers (MAR)

A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the

source address register of the transfer, and MARB as the destination address register.

An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits

of MARR are reserved; they cannot be modified and are always read as 1. (Write is invalid.)

Bit

Initial value

Read/Write

—

Source or destination address

—

R/W

MARR MARE MARH MARL

Undetermined

The MAR value is incremented or decremented each time one byte or word is transferred,

automatically updating the source or destination memory address. For details, see section 7.3.4,

Data Transfer Control Registers (DTCR).

The MARs are not initialized by a reset or in standby mode.

7.3.2 I/O Address Registers (IOAR)

The I/O address registers (IOARs) are not used in full address mode.

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7.3.3 Execute Transfer Count Registers (ETCR)

An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the

number of transfers to be executed. The functions of these registers differ between normal mode

and block transfer mode.

• Normal mode

ETCRA

Bit

Initial value

Read/Write

R/W

Transfer counter

Undetermined

R/W

ETCRB: Is not used in normal mode.

In normal mode ETCRA functions as a 16-bit transfer counter. The count is decremented by 1

each time one transfer is executed. The transfer ends when the count reaches H'0000. ETCRB is

not used.

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• Block transfer mode

ETCRA

Bit

Initial value

Read/Write

R/W

Undetermined

Block size counter

ETCRAH

Bit

Initial value

Read/Write

R/W

Undetermined

Initial block size

ETCRAL

ETCRB

Bit

Initial value

Read/Write

R/W

Block transfer counter

Undetermined

R/W

In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the

initial block size. ETCRAH is decremented by 1 each time one byte or word is transferred. When

the count reaches H'00, ETCRAH is reloaded from ETCRAL. Blocks consisting of an arbitrary

number of bytes or words can be transferred repeatedly by setting the same initial block size value

in ETCRAH and ETCRAL.

In block transfer mode ETCRB functions as a 16-bit block transfer counter. ETCRB is

decremented by 1 each time one block is transferred. The transfer ends when the count reaches

H'0000.

The ETCRs are not initialized by a reset or in standby mode.

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7.3.4 Data Transfer Control Registers (DTCR)

The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the

operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and

DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address

mode.

DTCRA

Bit

Initial value

Read/Write

DTE

R/W

DTSZ

R/W

SAID

R/W

SAIDE

R/W

DTIE

R/W

DTS0A

R/W

DTS2A

R/W

DTS1A

R/W

Data transfer enable

Enables or disables

data transfer

Enables or disables the

CPU interrupt at the end

of the transfer

Data transfer size

Selects byte or

word size

Source address

increment/decrement Data transfer select

2A and 1A

These bits must both be

set to 1

Data transfer

interrupt enable

Source address increment/

decrement enable

These bits select whether

the source address register

(MARA) is incremented,

decremented, or held fixed

durin

the data transfer

Selects block

transfer mode

Data transfer

select 0A

DTCRA is initialized to H'00 by a reset and in standby mode.

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Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables

or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the

channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the

channel waits for transfers to be requested. When the specified number of transfers have been

completed, the DTE bit is automatically cleared to 0. When DTE is 0, the channel is disabled and

does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then

writing 1.

Bit 7

DTE Description

0 Data transfer is disabl ed (DTE is cleared to 0 when the specified number (Initial value)

of transfers have been completed)

1 Data transfer is enabled

If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.

Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.

Bit 6

DTSZ Description

0 Byte-size transfer (Initial value)

1 Word-size transfer

Bit 5—Source Address Increment/Decrement (SAID) and,

Bit 4—Source Address Increment/Decrement Enable (SAIDE): These bits select whether the

source address register (MARA) is incremented, decremented, or held fixed during the data

transfer.

Bit 5

SAID Bit 4

SAIDE Description

0 0 MARA is held fixed (Initial value)

1 MARA is incremented after each data transfer

• If DTSZ = 0, MARA is incremented by 1 after each transfer

• If DTSZ = 1, MARA is incremented by 2 after each transfer

1 0 MARA is held fixed

1 MARA is decremented after each data transfer

• If DTSZ = 0, MARA is decremented by 1 after each transfer

• If DTSZ = 1, MARA is decremented by 2 after each transfer

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Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt

(DEND) requested when the DTE bit is cleared to 0.

Bit 3

DTIE Description

0 The DEND interrupt requested by DTE is disabled (Initial value)

1 The DEND interrupt requested by DTE is enabled

Bits 2 and 1—Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full

address mode when DTS2A and DTS1A are both set to 1.

Bit 0—Data Transfer Select 0A (DTS0A): Selects normal mode or block transfer mode.

Bit 0

DTS0A Description

0 Normal mode (Initi al value)

1 Block transfer mode

Operations in these modes are described in sections 7.4.5, Normal Mode, and 7.4.6, Block

Transfer Mode.

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DTCRB

Bit

Initial value

Read/Write

DTME

R/W



R/W

DAID

R/W

DAIDE

R/W

TMS

R/W

DTS0B

R/W

DTS2B

R/W

DTS1B

R/W

Data transfer master enable

Enables or disables data

transfer, together with

the DTE bit, and is cleared

to 0 by an interrupt

Reserved bit

Destination address

increment/decrement Data transfer select

2B to 0B

These bits select the data

transfer activation source

Transfer mode select

Destination address

increment/decrement enable

These bits select whether

the destination address

decremented, or held fixed

durin

the data transfer

Selects whether the

block area is the source

or destination in block

transfer mode

DTCRB is initialized to H'00 by a reset and in standby mode.

Bit 7—Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit

enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is

enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the

CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further

information on operation in block transfer mode, see section 7.6.6, NMI Interrupts and Block

Transfer Mode.

DTME is set to 1 by reading the register while DTME = 0, then writing 1.

Bit 7

DTME Description

0 Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt (Ini tial value)

occurs)

1 Data transfer is enabled

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Bit 6—Reserved: Although reserved, this bit can be written and read.

Bit 5—Destination Address Increment/Decrement (DAID) and,

Bit 4—Destination Address Increment/Decrement Enable (DAIDE): These bits select

whether the destination address register (MARB) is incremented, decremented, or held fixed

during the data transfer.

Bit 5

DAID Bit 4

DAIDE Description

0 0 MARB is held fixed (Initial value)

1 MARB is incremented after each data transfer

• If DTSZ = 0, MARB is incremented by 1 after each data transfer

• If DTSZ = 1, MARB is incremented by 2 after each data transfer

1 0 MARB is held fixed

1 MARB is decremented after each data transfer

• If DTSZ = 0, MARB is decremented by 1 after each data transfer

• If DTSZ = 1, MARB is decremented by 2 after each data transfer

Bit 3—Transfer Mode Select (TMS): Selects whether the source or destination is the block area

in block transfer mode.

Bit 3

TMS Description

0 Destination is the block area i n block transfer mode (Initi al value)

1 Source is the block area in block transfer mode

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Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the

data transfer activation source. The selectable activation sources differ between normal mode and

block transfer mode.

Normal mode

Bit 2

DTS2B Bit 1

DTS1B Bit 0

DTS0B Description

000Auto-request (burst mode) (Initi al value)

1 Cannot be used

1 0 Auto-request (cycle-steal mode)

1 Cannot be used

100Cannot be used

1 Cannot be used

1 0 Falling edge of

DREQ

1 Low level input at

DREQ

Block transfer mode

Bit 2

DTS2B Bit 1

DTS1B Bit 0

DTS0B Description

000Compare match/input capture A interrupt from 16-bit timer channel 0

(Initi al value)

1 Compare match/input capture A interrupt from 16-bit timer channel 1

1 0 Compare match/input capture A interrupt from 16-bit timer channel 2

1 Conversion-end interrupt from A/D converter

100Cannot be used

1 Cannot be used

1 0 Falling edge of

DREQ

1 Cannot be used

The same internal interrupt can be selected to activate two or more channels. The channels are

activated in a priority order, highest priority first. For the priority order, see section 7.4.9,

Multiple-Channel Operation.

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7.4 Operation

7.4.1 Overview

Table 7.5 summarizes the DMAC modes.

Table 7.5 DMAC Modes

Transfer Mode Activation Notes

Short address

mode I/O mode

Idle mode

Repeat mode

Compare match/input

capture A interrupt from

16-bit ti mer channels 0 to 2

• Up to four channels

can operate

independently

Transmit-data-empty

and receive-data-full

interrupts from SCI

channel 0

• Only the B channels

support external requests

Conversion-end interrupt

from A/D converter

External request

Full address

mode Normal mode Auto-request

External request

• A and B channels are

paired; up to two

channels are avai lable

Block transfer mode Compare match/input

capture A interrupt from

16-bit ti mer channels 0 to 2

Conversion-end interrupt

from A/D converter

• Burst mode transfer or

cycle-steal mode transfer

can be selected for auto-

requests

External request

A summary of operations in these modes follows.

I/O Mode: One byte or word is transferred per request. A designated number of these transfers

are executed. A CPU interrupt can be requested at completion of the designated number of

transfers. One 24-bit address and one 8-bit address are specified. The transfer direction is

determined automatically from the activation source.

Idle Mode: One byte or word is transferred per request. A designated number of these transfers

are executed. A CPU interrupt can be requested at completion of the designated number of

transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed.

The transfer direction is determined automatically from the activation source.

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Repeat Mode: One byte or word is transferred per request. A designated number of these

transfers are executed. When the designated number of transfers are completed, the initial address

and counter value are restored and operation continues. No CPU interrupt is requested. One 24-

bit address and one 8-bit address are specified. The transfer direction is determined automatically

from the activation source.

Normal Mode

• Auto-request

The DMAC is activated by register setup alone, and continues executing transfers until the

designated number of transfers have been completed. A CPU interrupt can be requested at

completion of the transfers. Both addresses are 24-bit addresses.

 Cycle-steal mode

The bus is released to another bus master after each byte or word is transferred.

 Burst mode

Unless requested by a higher-priority bus master, the bus is not released until the

designated number of transfers have been completed.

• External request

One byte or word is transferred per request. A designated number of these transfers are

executed. A CPU interrupt can be requested at completion of the designated number of

transfers. Both addresses are 24-bit addresses.

Block Transfer Mode: One block of a specified size is transferred per request. A designated

number of block transfers are executed. At the end of each block transfer, one address is restored

to its initial value. When the designated number of blocks have been transferred, a CPU interrupt

can be requested. Both addresses are 24-bit addresses.

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7.4.2 I/O Mode

I/O mode can be selected independently for each channel.

One byte or word is transferred at each transfer request in I/O mode. A designated number of

these transfers are executed. One address is specified in the memory address register (MAR), the

other in the I/O address register (IOAR). The direction of transfer is determined automatically

from the activation source. The transfer is from the address specified in IOAR to the address

specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the

address specified in MAR to the address specified in IOAR otherwise.

Table 7.6 indicates the register functions in I/O mode.

Table 7.6 Register Functions in I/O Mode

Function

Activated by

SCI 0 Receive-

Data-Full

Interrupt Other

Activation Initial Setting Operation

23 0

MAR

Destination

address

Source

address

Destination or

source start

address

Incremented or

decremented

once per

transfer

All 1s IOAR

23 07

Source

address

Destination

address

Source or

destination

address

Held fixed

15 0

ETCR

Transfer counter Number of

transfers Decremented

once per

transfer until

H'0000 is

reached and

transfer ends

Legend

MAR: Memory address register

IOAR: I/O address register

ETCR: Execute transfer count register

MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or

destination address, which is incremented or decremented as each byte or word is transferred.

IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not

incremented or decremented.

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Figure 7.2 illustrates how I/O mode operates.

Address T

Address B

Transfer

Legend

L = initial setting of MAR

N = initial setting of ETCR

Address T = L

Address B = L + (–1) • (2 • N – 1)

DTID

IOAR

1 byte or word is

transferred per request

DTSZ

Figure 7.2 Operation in I/O Mode

The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1

at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer

ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer

count is 65,536, obtained by setting ETCR to H'0000.

Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit

timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0,

conversion-end interrupts from the A/D converter, and external request signals.

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For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR).

Figure 7.3 shows a sample setup procedure for I/O mode.

Set source and

destination addresses

Set transfer count

Read DTCR

Set DTCR

I/O mode

I/O mode setup

Set the source and destination addresses

in MAR and IOAR. The transfer direction is

determined automatically from the activation

source.

Set the transfer count in ETCR.

Read DTCR while the DTE bit is cleared to 0.

Set the DTCR bits as follows.

Select the DMAC activation source with bits

DTS2 to DTS0.

Set or clear the DTIE bit to enable or disable

the CPU interrupt at the end of the transfer.

Clear the RPE bit to 0 to select I/O mode.

Select MAR increment or decrement with the

DTID bit.

Select byte size or word size with the DTSZ bit.

Set the DTE bit to 1 to enable the transfer.

•

Figure 7.3 I/O Mode Setup Procedure (Example)

7.4.3 Idle Mode

Idle mode can be selected independently for each channel.

One byte or word is transferred at each transfer request in idle mode. A designated number of

these transfers are executed. One address is specified in the memory address register (MAR), the

other in the I/O address register (IOAR). The direction of transfer is determined automatically

from the activation source. The transfer is from the address specified in IOAR to the address

specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the

address specified in MAR to the address specified in IOAR otherwise.

Table 7.7 indicates the register functions in idle mode.

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Table 7.7 Register Functions in Idle Mode

Function

Activated by

SCI 0 Receive-

Data-Full

Interrupt Other

Activation Initial Setting Operation

23 0

MAR

Destination

address

Source

address

Destination or

source address Held fixed

All 1s IOAR

23 07

Source

address

Destination

address

Source or

destination

address

Held fixed

15 0

ETCR

Transfer counter Number of

transfers Decremented

once per

transfer until

H'0000 is

reached and

transfer ends

Legend

MAR: Memory address register

IOAR: I/O address register

ETCR: Execute transfer count register

MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or

destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all

1s. MAR and IOAR are not incremented or decremented.

Figure 7.4 illustrates how idle mode operates.

Transfer

1 byte or word is

transferred per request

IOARMAR

Figure 7.4 Operation in Idle Mode

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The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1

at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends,

and a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting

ETCR to H'0000.

Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit

timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0,

conversion-end interrupts from the A/D converter, and external request signals.

For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).

Figure 7.5 shows a sample setup procedure for idle mode.

Set source and

destination addresses

Set transfer count

Read DTCR

Set DTCR

Idle mode

Idle mode setup

Set the source and destination addresses

in MAR and IOAR. The transfer direction is deter-

mined automatically from the activation source.

Set the transfer count in ETCR.

Read DTCR while the DTE bit is cleared to 0.

Set the DTCR bits as follows.

Select the DMAC activation source with bits

DTS2 to DTS0.

Set the DTIE and RPE bits to 1 to select idle mode.

Select byte size or word size with the DTSZ bit.

Set the DTE bit to 1 to enable the transfer.

•

Figure 7.5 Idle Mode Setup Procedure (Example)

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7.4.4 Repeat Mode

Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable

timing pattern controller (TPC) in synchronization, for example, with 16-bit timer compare

match. Repeat mode can be selected for each channel independently.

One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number

of these transfers are executed. One address is specified in the memory address register (MAR),

the other in the I/O address register (IOAR). At the end of the designated number of transfers,

MAR and ETCRH are restored to their original values and operation continues. The direction of

transfer is determined automatically from the activation source. The transfer is from the address

specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data-

full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.

Table 7.8 indicates the register functions in repeat mode.

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Table 7.8 Register Functions in Repeat Mode

Function

Activated by

SCI 0 Receive-

Data-Full

Interrupt Other

Activation Initial Setting Operation

Destination

address

Source

address

Destination or

source start

address

Incremented or

decremented at

each transfer until

ETCRH reaches

H'0000, then restored

to initial value

Source

address

Destination

address

Source or

destination

address

Held fixed

Transfer counter Number of

transfers Decremented once

per transfer until

H'0000 is reached,

then reloaded from

ETCRL

Initial transfer count Number of

transfers Held fixed

Legend

MAR: Memory address register

IOAR: I/O address register

ETCR: Execute transfer count register

23 0

MAR

All 1s IOAR

23 0

ETCRH

ETCRL

In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer

count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from

ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID

bits in DTCR. Specifically, MAR is restored as follows:

MAR ← MAR – (–1)DTID · 2DTSZ · ETCRL

ETCRH and ETCRL should be initially set to the same value.

In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to

0, if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No

CPU interrupt is requested.

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As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a

24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The

upper 16 bits are all 1s. IOAR is not incremented or decremented.

Figure 7.6 illustrates how repeat mode operates.

Address T

Address B

Transfer

1 byte or word is

transferred per request

Legend

L = initial setting of MAR

N = initial setting of ETCRH and ETCRL

Address T = L

Address B = L + (–1) • (2 • N – 1)

DTID DTSZ

IOAR

Figure 7.6 Operation in Repeat Mode

The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer

count is 255, obtained by setting both ETCRH and ETCRL to H'FF.

Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit

timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0,

conversion-end interrupts from the A/D converter, and external request signals.

For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR).

Figure 7.7 shows a sample setup procedure for repeat mode.

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Set source and

destination addresses

Set transfer count

Read DTCR

Set DTCR

Repeat mode

Set the source and destination addresses in MAR

and IOAR. The transfer direction is determined

automatically from the activation source.

Set the transfer count in both ETCRH and ETCRL.

Read DTCR while the DTE bit is cleared to 0.

Select byte size or word size with the DTSZ bit.

Set the DTE bit to 1 to enable the transfer.

•

Select the DMAC activation source with bits

DTS2 to DTS0.

Clear the DTIE bit to 0 and set the RPE bit to 1

to select repeat mode.

Select MAR increment or decrement with the DTID bit.

Set the DTCR bits as follows.

Figure 7.7 Repeat Mode Setup Procedure (Example)

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7.4.5 Normal Mode

In normal mode the A and B channels are combined. One byte or word is transferred per request.

A designated number of these transfers are executed. Addresses are specified in MARA and

MARB. Table 7.9 indicates the register functions in I/O mode.

Table 7.9 Register Functions in Normal Mode

23 0

MARA

Source address

address Incremented or

decremented once per

transfer, or held fi xed

23 0

MARB

Destination

address register Destination start

address Incremented or

decremented once per

transfer, or held fi xed

15 0

ETCRA

Transfer counter Number of

transfers Decremented once per

transfer

Legend

MARA: Memory address register A

MARB: Memory address register B

ETCRA: Execute transfer count register A

The source and destination addresses are both 24-bit addresses. MARA specifies the source

address. MARB specifies the destination address. MARA and MARB can be independently

incremented, decremented, or held fixed as data is transferred.

The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by

1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the

transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum

transfer count is 65,536, obtained by setting ETCRA to H'0000.

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Figure 7.8 illustrates how normal mode operates.

Address T

Address B

Transfer

Legend

SAID

DAID

Address T

Address B

= initial setting of MARA

= initial setting of MARB

= initial setting of ETCRA

= L

= L + SAIDE • (–1) • (2 • N – 1)

= L

= L + DAIDE • (–1) • (2 • N – 1)

DTSZ

Figure 7.8 Operation in Normal Mode

Transfers can be requested (activated) by an external request or auto-request. An auto-requested

transfer is activated by the register settings alone. The designated number of transfers are

executed automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode the

DMAC releases the bus temporarily after each transfer. In burst mode the DMAC keeps the bus

until the transfers are completed, unless there is a bus request from a higher-priority bus master.

For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).

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Figure 7.9 shows a sample setup procedure for normal mode.

Set the initial source address in MARA.

Set the initial destination address in MARB.

Set the transfer count in ETCRA.

Set the DTCRB bits as follows.

Set the DTCRA bits as follows.

Read DTCRB with DTME cleared to 0.

Normal mode

Set initial source address

Set initial destination address

Set transfer count

Set DTCRB (1)

Set DTCRA (1)

Read DTCRB

Set DTCRB (2)

Read DTCRA

Set DTCRA (2)

•

Clear the DTME bit to 0.

Set the DAID and DAIDE bits to select whether

MARB is incremented, decremented, or held fixed.

Select the DMAC activation source with bits

DTS2B to DTS0B.

Clear the DTE bit to 0.

Select byte or word size with the DTSZ bit.

Set the SAID and SAIDE bits to select whether

MARA is incremented, decremented, or held fixed.

Set or clear the DTIE bit to enable or disable the

CPU interrupt at the end of the transfer.

Clear the DTS0A bit to 0 and set the DTS2A

and DTS1A bits to 1 to select normal mode.

Set the DTME bit to 1 in DTCRB.

Read DTCRA with DTE cleared to 0.

Set the DTE bit to 1 in DTCRA to enable the transfer.

Note: Carry out settings 1 to 9 with the DEND interrupt masked in the CPU.

If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in

which case the transfer will not start.

Figure 7.9 Normal Mode Setup Procedure (Example)

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7.4.6 Block Transfer Mode

In block transfer mode the A and B channels are combined. One block of a specified size is

transferred per request. A designated number of block transfers are executed. Addresses are

specified in MARA and MARB. The block area address can be either held fixed or cycled.

Table 7.10 indicates the register functions in block transfer mode.

Table 7.10 Register Functions in Block Transfer Mode

Source address

address Incremented or

decremented once per

transfer, or held fixed

Destination

address register Destination start

address Incremented or

decremented once per

transfer, or held fixed

Block size counter Block size Decremented once per

transfer until H'00 is

reached, then reloaded

from ETCRL

Initial block size Block size Held fixed

Block transfer

counter Number of block

transfers Decremented once per

block transfer until H'0000

is reached and the

transfer ends

Legend

MARA: Memory address register A

MARB: Memory address register B

ETCRA: Execute transfer count register A

ETCRB: Execute transfer count re

ister B

23 0

MARA

ETCRAH

ETCRAL

23 0

MARB

15 0

ETCRB

The source and destination addresses are both 24-bit addresses. MARA specifies the source

address. MARB specifies the destination address. MARA and MARB can be independently

incremented, decremented, or held fixed as data is transferred. One of these registers operates as

a block area register: even if it is incremented or decremented, it is restored to its initial value at

the end of each block transfer. The TMS bit in DTCRB selects whether the block area is the

source or destination.

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If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the

number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and

ETCRB should initially be set to N.

Figure 7.10 illustrates how block transfer mode operates. In this figure, bit TMS is cleared to 0,

meaning the block area is the destination.

Transfer

Legend

Address T

M bytes or words are

transferred per request

Address B

Block 1

Block N

Block area

Block 2

= initial setting of MARA

= initial setting of MARB

= initial setting of ETCRAH and ETCRAL

= initial setting of ETCRB

= L

= L + SAIDE • (–1) • (2 • M – 1)

= L

= L + DAIDE • (–1) • (2 • M – 1)

SAID

DAID

DTSZ

Figure 7.10 Operation in Block Transfer Mode

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When activated by a transfer request, the DMAC executes a burst transfer. During the transfer

MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented.

When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The

memory address register of the block area is also restored to its initial value, and ETCRB is

decremented. If ETCRB is not H'0000, the DMAC then waits for the next transfer request.

ETCRAH and ETCRAL should be initially set to the same value.

The above operation is repeated until ETCRB reaches H'0000, at which point the DTE bit is

cleared to 0 and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this

time.

Figure 7.11 shows examples of a block transfer with byte data size when the block area is the

destination. In (a) the block area address is cycled. In (b) the block area address is held fixed.

Transfers can be requested (activated) by compare match/input capture A interrupts from ITU

channels 0 to 2, by an A/D converter conversion-end interrupt, and by external request signals.

For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).

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Start

(DTE = DTME = 1)

Transfer requested?

Get bus

MARA = MARA + 1

Read from MARA address

Write to MARB address

MARB = MARB + 1

ETCRAH = ETCRAH – 1

ETCRAH = H'00

Release bus

Clear DTE to 0 and end transfer

ETCRAH = ETCRAL

MARB = MARB – ETCRAL

ETCRB = ETCRB – 1

ETCRB = H'0000

Start

(DTE = DTME = 1)

Transfer requested?

Get bus

MARA = MARA + 1

Read from MARA address

Write to MARB address

ETCRAH = ETCRAH – 1

ETCRAH = H'00

Release bus

Clear DTE to 0 and end transfer

ETCRB = ETCRB – 1

ETCRB = H'0000

ETCRAH = ETCRAL

Yes

a. DTSZ = TMS = 0

SAID = DAID = 0

SAIDE = DAIDE = 1

b. DTSZ = TMS = 0

SAID = 0

SAIDE = 1

DAIDE = 0

Figure 7.11 Block Transfer Mode Flowcharts (Examples)

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Figure 7.12 shows a sample setup procedure for block transfer mode.

10.

Block transfer mode

Set source address

Set destination address

Set block transfer count

Set block size

Set DTCRB (1)

Set DTCRA (1)

Read DTCRB

Set DTCRB (2)

Read DTCRA

Set DTCRA (2)

Block transfer mode

Set the source address in MARA.

Set the destination address in MARB.

Set the block transfer count in ETCRB.

Set the block size (number of bytes or words)

in both ETCRAH and ETCRAL.

Set the DTCRB bits as follows.

Set the DTCRA bits as follows.

•

Clear the DTME bit to 0.

Set the DAID and DAIDE bits to select whether

MARB is incremented, decremented, or held fixed.

Set or clear the TMS bit to make the block area

the source or destination.

Select the DMAC activation source with bits

DTS2B to DTS0B.

Clear the DTE to 0.

Select byte size or word size with the DTSZ bit.

Set the SAID and SAIDE bits to select whether

MARA is incremented, decremented, or held fixed.

Set or clear the DTIE bit to enable or disable the

CPU interrupt at the end of the transfer.

Set bits DTS2A to DTS0A all to 1 to select

block transfer mode.

Read DTCRB with DTME cleared to 0.

Set the DTME bit to 1 in DTCRB.

Read DTCRA with DTE cleared to 0.

Set the DTE bit to 1 in DTCRA to enable

the transfer.

Note: Carry out settings 1 to 10 with the DEND interrupt masked in the CPU.

If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in

which case the transfer will not start.

Figure 7.12 Block Transfer Mode Setup Procedure (Example)

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7.4.7 DMAC Activation

The DMAC can be activated by an internal interrupt, external request, or auto-request. The

available activation sources differ depending on the transfer mode and channel as indicated in

table 7.11.

Table 7.11 DMAC Activation Sources

Short Address Mode

Channels Channels Full Address Mode

Activation Source 0A and 1A 0B and 1B Normal Block

Internal IMIA0 ×

interrupts IMIA1 ×

IMIA2 ×

ADI ×

TXI0 ××

RXI0 ××

External

requests Falling edge

DREQ

Low input at

DREQ

× ×

Auto-request ×× ×

Activation by Internal Interrupts: When an interrupt request is selected as a DMAC activation

source and the DTE bit is set to 1, that interrupt request is not sent to the CPU. It is not possible

for an interrupt request to activate the DMAC and simultaneously generate a CPU interrupt.

When the DMAC is activated by an interrupt request, the interrupt request flag is cleared

automatically. If the same interrupt is selected to activate two or more channels, the interrupt

request flag is cleared when the highest-priority channel is activated, but the transfer request is

held pending on the other channels in the DMAC, which are activated in their priority order.

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Activation by External Request: If an external request (

DREQ

pin) is selected as an activation

source, the

DREQ

pin becomes an input pin and the corresponding

TEND

pin becomes an output

pin, regardless of the port data direction register (DDR) settings. The

DREQ

input can be level-

sensitive or edge-sensitive.

In short address mode and normal mode, an external request operates as follows. If edge sensing

is selected, one byte or word is transferred each time a high-to-low transition of the

DREQ

input

is detected. If the next edge is input before the transfer is completed, the next transfer may not be

executed. If level sensing is selected, the transfer continues while

DREQ

is low, until the transfer

is completed. The bus is released temporarily after each byte or word has been transferred,

however. If the

DREQ

input goes high during a transfer, the transfer is suspended after the

current byte or word has been transferred. When

DREQ

goes low, the request is held internally

until one byte or word has been transferred. The

TEND

signal goes low during the last write

cycle.

In block transfer mode, an external request operates as follows. Only edge-sensitive transfer

requests are possible in block transfer mode. Each time a high-to-low transition of the

DREQ

input is detected, a block of the specified size is transferred. The

TEND

signal goes low during

the last write cycle in each block.

Activation by Auto-Request: The transfer starts as soon as enabled by register setup, and

continues until completed. Cycle-steal mode or burst mode can be selected.

In cycle-steal mode the DMAC releases the bus temporarily after transferring each byte or word.

Normally, DMAC cycles alternate with CPU cycles.

In burst mode the DMAC keeps the bus until the transfer is completed, unless there is a higher-

priority bus request. If there is a higher-priority bus request, the bus is released after the current

byte or word has been transferred.

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7.4.8 DMAC Bus Cycle

Figure 7.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a

word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When

the DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address

and writes to the destination address. During these read and write operations the bus is not

released even if there is another bus request. DMAC cycles comply with bus controller settings in

the same way as CPU cycles.

HWR

LWR

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

3 T

1 T

2 T

3 T

1 T

2 T

1 T

CPU cycle DMAC cycle (1 word transfer) CPU cycle

Source

address Destination address

Address

bus

Figure 7.13 DMA Transfer Bus Timing (Example)

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Figure 7.14 shows the timing when the DMAC is activated by low input at a

DREQ

pin. This

example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-

state access area. The DMAC continues the transfer while the

DREQ

pin is held low.

DREQ

HWR

TEND

LWR,

CPU cycle DMAC cycle CPU cycle DMAC cycle

(last transfer cycle) CPU cycle

Source

address

Destination

address

Source

address

Destination

address

Address

bus

Figure 7.14 Bus Timing of DMA Transfer Requested by Low

DREQ

Input

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Figure 7.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three

words from a 16-bit two-state access area to another 16-bit two-state access area.

CPU cycle DMAC cycle

Source

address

Destination

address

CPU cycle

Address

bus

HWR

LWR

Figure 7.15 Burst DMA Bus Timing

When the DMAC is activated from a

DREQ

pin there is a minimum interval of four states from

when the transfer is requested until the DMAC starts operating. The

DREQ

pin is not sampled

during the time between the transfer request and the start of the transfer. In short address mode

and normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the

pin is next sampled at the end of one block transfer.

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Figure 7.16 shows the timing when the DMAC is activated by the falling edge of

DREQ

in normal

mode.

DREQ

HWR

LWR,

CPU cycle DMAC cycle CPU

cycle DMAC cycle

Minimum 4 states Next sampling point

Address

bus

Figure 7.16 Timing of DMAC Activation by Falling Edge of

DREQ

in Normal Mode

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Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low

DREQ

input in

normal mode.

DREQ

HWR

LWR,

2 T

1 T

2 T

1 T

2 T

d T

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

CPU cycle DMAC cycle CPU cycle

Minimum 4 states Next samplin

point

Address

bus

Figure 7.17 Timing of DMAC Activation by Low

DREQ

Level in Normal Mode

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Figure 7.18 shows the timing when the DMAC is activated by the falling edge of

DREQ

in block

transfer mode.

DREQ

HWR

TEND

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

d T

1 T

DMAC cycle DMAC cycleCPU cycle

Next sampling

Minimum 4 states

End of 1 block transfer

LWR

Address

bus

Figure 7.18 Timing of DMAC Activation by Falling Edge of

DREQ

in Block Transfer

Mode

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7.4.9 Multiple-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B.

Table 7.12 shows the complete priority order.

Table 7.12 Channel Priority Order

Short Address Mode Full Address Mode Priority

Channel 0A Channel 0 High

Channel 0B

Channel 1A Channel 1

Channel 1B Low

If transfers are requested on two or more channels simultaneously, or if a transfer on one channel

is requested during a transfer on another channel, the DMAC operates as follows.

• When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it

starts a transfer on the highest-priority channel at that time.

• Once a transfer starts on one channel, requests to other channels are held pending until that

channel releases the bus.

• After each transfer in short address mode, and each externally-requested or cycle-steal

transfer in normal mode, the DMAC releases the bus and returns to step 1. After releasing the

bus, if there is a transfer request for another channel, the DMAC requests the bus again.

• After completion of a burst-mode transfer, or after transfer of one block in block transfer

mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a

higher-priority channel or a bus request from a higher-priority bus master, however, the

DMAC releases the bus after completing the transfer of the current byte or word. After

releasing the bus, if there is a transfer request for another channel, the DMAC requests the

bus again.

Figure 7.19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst

mode, and a transfer request for channel 0A is received while channel 1 is active.

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DMAC cycle

(channel 1) CPU

cycle DMAC cycle

(channel 0A) CPU

cycle DMAC cycle

(channel 1)

Address

bus

HWR

LWR

Figure 7.19 Timing of Multiple-Channel Operations

7.4.10 External Bus Requests, DRAM Interface, and DMAC

During a DMAC transfer, if the bus right is requested by an external bus request signal (

BREQ

)

or by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the

transfer of the current byte or word. If there is a transfer request at this point, the DMAC requests

the bus right again. Figure 7.20 shows an example of the timing of insertion of a refresh cycle

during a burst transfer on channel 0.

HWR LWR,

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

d T

1 T

2 T

1 T

2 T

1 T

DMAC cycle (channel 0) DMAC cycle (channel 0)

Refresh

cycle

Address

bus

Figure 7.20 Bus Timing of DRAM Interface, and DMAC

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7.4.11 NMI Interrupts and DMAC

NMI interrupts do not affect DMAC operations in short address mode.

If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends

operations. In full address mode, a channel is enabled when its DTE and DTME bits are both set

to 1. NMI input clears the DTME bit to 0. After transferring the current byte or word, the DMAC

releases the bus to the CPU. In normal mode, the suspended transfer resumes when the CPU sets

the DTME bit to 1 again. Check that the DTE bit is set to 1 and the DTME bit is cleared to 0

before setting the DTME bit to 1.

Figure 7.21 shows the procedure for resuming a DMAC transfer in normal mode on channel 0

after the transfer was halted by NMI input.

Resuming DMAC transfer

in normal mode

DTE = 1

DTME = 0

Set DTME to 1

DMA transfer continues End

2. Check that DTE = 1 and DTME = 0.

Read DTCRB while DTME = 0,

then write 1 in the DTME bit.

Yes

Figure 7.21 Procedure for Resuming a DMAC Transfer Halted by NMI (Example)

For information about NMI interrupts in block transfer mode, see section 7.6.6, NMI Interrupts

and Block Transfer Mode.

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7.4.12 Aborting a DMAC Transfer

When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the

current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode,

the DTME bit can be used for the same purpose. Figure 7.22 shows the procedure for aborting a

DMAC transfer by software.

DMAC transfer abort

Set DTCR

DMAC transfer aborted

1. Clear the DTE bit to 0 in DTCR.

To avoid generating an interrupt when

aborting a DMA transfer, clear the DTIE

bit to 0 simultaneously.

Figure 7.22 Procedure for Aborting a DMAC Transfer

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7.4.13 Exiting Full Address Mode

Figure 7.23 shows the procedure for exiting full address mode and initializing the pair of

channels. To set the channels up in another mode after exiting full address mode, follow the setup

procedure for the relevant mode.

Exiting full address mode

Halt the channel

Initialize DTCRB

Initialize DTCRA

Initialized and halted

Clear the DTE bit to 0 in DTCRA, or wai

for the transfer to end and the DTE bit

to be cleared to 0.

Clear all DTCRB bits to 0.

Clear all DTCRA bits to 0.

Figure 7.23 Procedure for Exiting Full Address Mode (Example)

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7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode

When the chip is reset or enters software standby mode, the DMAC is initialized and halts.

DMAC operations continue in sleep mode. Figure 7.24 shows the timing of a cycle-steal transfer

in sleep mode.

Address bus

HWR LWR,

2 T

T T

2 1 T

T d T

T 2 T

T 2

CPU cycle DMAC cycle DMAC cycle

Sleep mode

Figure 7.24 Timing of Cycle-Steal Transfer in Sleep Mode

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7.5 Interrupts

The DMAC generates only DMA-end interrupts. Table 7.13 lists the interrupts and their priority.

Table 7.13 DMAC Interrupts

Description

Interrupt Short Address Mode Full Address Mode Interrupt Priority

DEND0A End of transfer on channel 0A End of transfer on channel 0 High

DEND0B End of transfer on channel 0B —

DEND1A End of transfer on channel 1A End of transfer on channel 1

DEND1B End of transfer on channel 1B — Low

Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control

The interrupt priority order among channels is channel 0 > channel 1 and channel A > channel B.

Figure 7.25 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and

DTIE = 1.

DTE

DTIE

DMA-end interrupt

Figure 7.25 DMA-End Interrupt Logic

The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The

DTME bit does not affect interrupt operations.

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7.6 Usage Notes

7.6.1 Note on Word Data Transfer

Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set

even values in the memory and I/O address registers (MAR and IOAR).

7.6.2 DMAC Self-Access

The DMAC itself cannot be accessed during a DMAC cycle. DMAC registers cannot be specified

as source or destination addresses.

7.6.3 Longword Access to Memory Address Registers

A memory address register can be accessed as longword data at the MARR address.

Example

MOV.L #LBL, ER0

MOV.L ER0, @MARR

Four byte accesses are performed. Note that the CPU may release the bus between the second

byte (MARE) and third byte (MARH).

Memory address registers should be written and read only when the DMAC is halted.

7.6.4 Note on Full Address Mode Setup

Full address mode is controlled by two registers: DTCRA and DTCRB. Care must be taken to

prevent the B channel from operating in short address mode during the register setup. The enable

bits (DTE and DTME) should not be set to 1 until the end of the setup procedure.

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7.6.5 Note on Activating DMAC by Internal Interrupts

When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as

the activating source does not occur during the interval after it has been selected but before the

DMAC has been enabled. The on-chip supporting module that will generate the interrupt should

not be activated until the DMAC has been enabled. If the DMAC must be enabled while the on-

chip supporting module is active, follow the procedure in figure 7.26.

Enabling of DMAC

Selected interrupt

requested?

Interrupt hand-

ling by CPU

Clear selected interrupt's

enable bit to 0

Enable DMAC

Set selected interrupt's

enable bit to 1

While the DTE bit is cleared to 0,

interrupt requests are sent to the

CPU.

Clear the interrupt enable bit to 0

in the interrupt-generating on-chip

supporting module.

Enable the DMAC.

Enable the DMAC-activating

interrupt.

DMAC operates

Yes

Figure 7.26 Procedure for Enabling DMAC while On-Chip Supporting

Module is Operating (Example)

If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected

activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt,

for example, the selected activating source cannot generate CPU interrupts. To terminate DMAC

operations in this state, clear the DTE bit to 0 to allow CPU interrupts to be requested. To

continue DMAC operations, carry out steps 2 and 4 in figure 7.26 before and after setting the

DTME bit to 1.

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When 16-bit timer interrupt activates the DMAC, make sure the next interrupt does not occur

before the DMA transfer ends. If one 16-bit timer interrupt activates two or more channels, make

sure the next interrupt does not occur before the DMA transfers end on all the activated channels.

If the next interrupt occurs before a transfer ends, the channel or channels for which that interrupt

was selected may fail to accept further activation requests.

7.6.6 NMI Interrupts and Block Transfer Mode

If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows.

• When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word,

then clears the DTME bit to 0 and halts. The halt may occur in the middle of a block.

It is possible to find whether a transfer was halted in the middle of a block by checking the

block size counter. If the block size counter does not have its initial value, the transfer was

halted in the middle of a block.

• If the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0.

The activation request is not held pending.

• While the DTE bit is set to 1 and the DTME bit is cleared to 0, the DMAC is halted and does

not accept activating interrupt requests. If an activating interrupt occurs in this state, the

DMAC does not operate and does not hold the transfer request pending internally. Neither is a

CPU interrupt requested.

For this reason, before setting the DTME bit to 1, first clear the enable bit of the activating

interrupt to 0. Then, after setting the DTME bit to 1, set the interrupt enable bit to 1 again. See

section 7.6.5, Note on Activating DMAC by Internal Interrupts.

• When the DTME bit is set to 1, the DMAC waits for the next transfer request. If it was halted

in the middle of a block transfer, the rest of the block is transferred when the next transfer

request occurs. Otherwise, the next block is transferred when the next transfer request occurs.

7.6.7 Memory and I/O Address Register Values

Table 7.14 indicates the address ranges that can be specified in the memory and I/O address

registers (MAR and IOAR).

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Table 7.14 Address Ranges Specifiable in MAR and IOAR

1-Mbyte Mode 16-Mbyte Mode

MAR H'00000 to H'FFFFF

(0 to 1048575) H'000000 to H'FFFFFF

(0 to 16777215)

IOAR H'FFF00 to H'FFFFF

(1048320 to 1048575) H'FFFF00 to H'FFFFFF

(16776960 to 16777215)

MAR bits 23 to 20 are ignored in 1-Mbyte mode.

7.6.8 Bus Cycle when Transfer is Aborted

When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the

DTME bit, if this halts a channel for which the DMAC has a transfer request pending internally, a

dead cycle may occur. This dead cycle does not update the halted channel’s address register or

counter value. Figure 7.27 shows an example in which an auto-requested transfer in cycle-steal

mode on channel 0 is aborted by clearing the DTE bit in channel 0.

Address bus

HWR,LWR

CPU cycle DMAC cycle CPU cycle DMAC

cycle CPU cycle

DTE bit is

cleared

Figure 7.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode

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7.6.9 Transfer Requests by A/D Converter

When the A/D converter is set to scan mode and conversion is performed on more than one

channel, the A/D converter generates a transfer request when all conversions are completed. The

converted data is stored in the appropriate ADDR registers. Block transfer mode and full address

mode should therefore be used to transfer all the conversion results at one time.

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Section 8 I/O Ports

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Section 8 I/O Ports

8.1 Overview

The H8/3068F has 11 input/output ports (ports 1, 2, 3, 4, 5, 6, 7, 8, 9, A, and B). Table 8.1

summarizes the port functions. The pins in each port are multiplexed as shown in table 8.1.

Each port has a data direction register (DDR) for selecting input or output, and a data register

(DR) for storing output data. In addition to these registers, ports 2, 4, and 5 have an input pull-up

control register (PCR) for switching input pull-up transistors on and off.

Ports 1 to 6 and port 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can

drive one TTL load and a 30-pF capacitive load. Ports 1 to 6 and 8 to B can drive a darlington

pair. Ports 1, 2, and 5 can drive LEDs (with 10-mA current sink). Pins P82 to P80, PA7 to PA0

have Schmitt-trigger input circuits.

For block diagrams of the ports see appendix C, I/O Port Block Diagrams.

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Table 8.1 Port Functions

Expanded Modes Single-Chip Modes

Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

Port 1 •8-bit I/O po rt

•Can drive LEDs

P17 to P10/

A7 to A0

Address output pins (A7 to A0) Addre ss output (A7 to

A0) and generic input

DDR = 0:

generic input

DDR = 1:

address output

Generic input/output

Port 2 •8-bit I/O po rt

•Built-in input pull-

up transistors

•Can drive LEDs

P27 to P20/

A15 to A8

Address output pins (A15 to A8) Address output (A15 to

A8) and generic input

DDR = 0:

generic input

DDR = 1:

address output

Generic input/output

Port 3 •8-bit I/O port P37 to P30/

D15 to D8

Data input/output (D15 to D8) Generic input/output

Port 4 •8-bit I/O po rt

•Built-in input pull-

up transistors

P47 to P40/

D7 to D0

Data input/output (D7 to D0) and 8-bit generic input/output

8-bit bus mode: generic input/output

16-bit bus mode: data input/output

Generic input/output

Port 5 •4-bit I/O po rt

•Built-in input pull-

up transistors

•Can drive LEDs

P53 to P50/

A19 to A16

Address output (A19 to A16) Address output (A19 to

A16) and 4-bit

generic input

DDR = 0: generic input

DDR = 1: address output

Generic input/output

Port 6 •8-bit I/O port P67/φClock output (φ) and generic input

P66/

LWR

P65/

HWR

P64/

P63/

Bus control signal output (

LWR

HWR

) Gene ric input/output

P62/

BACK

P61/

BREQ

P60/

WAIT

Bus control signal input/output (

BACK

BREQ

WAIT

) and

3-bit gene ric input/output

Port 7 •8-bit I/O port P77/AN7/DA1

P76/AN6/DA0

Analog input (AN7, AN6) to A/D converter, analog output (DA1, DA0)

from D/A conv erter, and generic input

P75 to P70/

AN5 to AN0

Analog input (AN5 to AN0) to A/D converter, and generic input

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Expanded Modes Single-Chip Modes

Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

Port 8 •5-bit I/O po rt

•P82 to P80 have

Schmitt inputs

P84/

0DDR = 0: generic input

DDR = 1 (reset value):

0 output DDR = 0 (reset value):

generic input

DDR = 1:

0 o u tp u t

Generic input/output

P83/

IRQ

ADTRG IRQ

3 input,

1 output, external trigger input (

ADTRG

) to A/D con verter, and

generic input

DDR = 0 (after re set): generic input

DDR = 1:

1 output

IRQ

3 input, external

trigger input (

ADTRG

) to

A/D converter, and

generic input/output

P82/

IRQ

P81/

IRQ

2 and

IRQ

1 input,

2 and

3 output, and generic input*

DDR = 0 (reset value): ge neric input

DDR = 1:

2 and

3 output

IRQ

2 and

IRQ

1 input and

generic input/output

P80/

IRQ

RFSH IRQ

0 input,

RFSH

output, a nd generic input/output

IRQ

0 input and generic

input/output

Port 9 •6-bit I/O port P95/

IRQ

/SCK1

P94/

IRQ

/SCK0

P93/RxD1

P92/RxD0

P91/TxD1

P90/TxD0

Input and output (SCK1, SCK0, RxD1, RxD0, TxD1, TxD0) for serial commu nica t io n interfaces 1 and 0

(SCI1/0),

IRQ

5 and

IRQ

4 input, and 6-bit generic input/output

Port A •8-bit I/O port

•Schmitt inputs

PA7/TP7/

TIOCB2/A20

Output (TP7) from pro-

gramma ble timing pattern

cont roller (TPC),

input or o utput (TIOCB2)

for 16-bit timer and

generic input/output

Address output

(A20)Address output (A20),

TPC output (TP7), inp ut

or output (TIOCB2) for

16-bit timer, and generic

input/output

TPC output (TP7), 16-bit

timer input or output

(TIOCB2), and generic

input/output

PA6/TP6/

TIOCA2/A21

PA5/TP5/

TIOCB1/A22

PA4/TP4/

TIOCA1/A23

TPC output (TP6 to TP4),

16-bit timer input and

outp u t (TIOCA2, TIOCB1,

TIOCA1) , and generic

input/output

TPC output (TP6 to TP4),16-bit timer input and

outp u t (TIOCA2, TIOCB1, TIOCA1), address output

(A23 to A21), a nd generic input/output

TPC output (TP6 to

TP4), 16-bit timer input

and output (TIOCA2,

TIOCB1, TIOCA1) a nd

generic input/output

PA3/TP3/

TIOCB0/

TCLKD

PA2/TP2/

TIOCA0/

TCLKC

PA1/TP1/

TCLKB

TEND

PA0/TP0/

TCLKA

TEND

TPC output (TP3 to TP0), 16-bit timer input and o utput (TIOCB0, TIOCA0, TCLKD, TCLKC , TCLKB,

TCLKA), 8-bit timer input (TCLKD, TCLKC, TCLKB, TCLKA), output (

TEND

0) from DMA

controller (DMAC), and generic input/output

Port B •8-bit I/O port PB7/TP15/

RXD2

PB6/TP14/

TXD2

PB5/TP13/

SCK2/

LCAS

PB4/TP12/

UCAS

TPC output (TP15 to TP12), SCI2 input and output (SCK2 , RxD2, TxD2), DRAM

interface output (

LCAS

UCAS

), and ge neric input/output TPC output (TP15 to

TP12), SCI2 input and

outp u t (SCK2, RxD2,

TxD2), and ge neric

input/output

PB3/TP11/

TMIO3/

DREQ

PB2/TP10/

TMO2/

PB1/TP9/

TMIO1/

DREQ

PB0/TP8/

TMO0/

TPC output (TP11 to TP8), 8-bit timer input and output (TMIO3, TMO2, TMIO1,

TMO0), DMAC input (

DREQ

0),

7 to

4 output, and generic

input/output

TPC ou tp u t (TP11 to TP8),

8-bit time r inp ut and

outp u t (TMIO3, TMO2,

TMIO1, TMO0), DMAC

input (

DREQ

0),

and generic input/output

Note: *P81 can be used as an output p o rt by making a setting in DRCRA.

Section 8 I/O Ports

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8.2 Port 1

8.2.1 Overview

Port 1 is an 8-bit input/output port also used for address output, with the pin configuration shown

in figure 8.1. The pin functions differ between the expanded modes with on-chip ROM disabled,

expanded modes with on-chip ROM enabled, and single-chip mode. In modes 1 to 4 (expanded

modes with on-chip ROM disabled), they are address bus output pins (A7 to A0).

In modes 5 (expanded modes with on-chip ROM enabled), settings in the port 1 data direction

and 7 (single-chip mode), port 1 is a generic input/output port.

When DRAM is connected to area 2, 3, 4, 5, A7 to A0 output row and column addresses in read

and write cycles. For details see section 6.5, DRAM Interface.

Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or

a darlington transistor pair.

Port 1

P1 /A

P1 (input/output)

A (output)

Port 1 pins Mode 6 and 7Modes 1 to 4

P1 (input)/A (output)

Modes 5

Figure 8.1 Port 1 Pin Configuration

Section 8 I/O Ports

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8.2.2 Register Descriptions

Table 8.2 summarizes the registers of port 1.

Table 8.2 Port 1 Registers

Initial Value

Address*Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7

H'EE000 Port 1 data direction register P1DDR W H'FF H'00

H'FFFD0 Port 1 data register P1DR R/W H'00 H'00

Note: * Lower 20 bits of the address in advanced mode.

Port 1 Data Direction Register (P1DDR): P1DDR is an 8-bit write-only register that can select

input or output for each pin in port 1.

Bit

Modes

1 to 4 Initial value

Read/Write

Initial value

Read/Write

Modes

5 to 7

P1 DDR



P1 DDR



P1 DDR



P1 DDR



P1 DDR



P1 DDR



P1 DDR



P1 DDR



Port 1 data direction 7 to 0

These bits select input or

output for port 1 pins

Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P1DDR values are fixed at 1.

Port 1 functions as an address bus.

Modes 5 (Expanded Modes with On-Chip ROM Enabled): After a reset, port 1 functions as

an input port.A pin in port 1 becomes an address output pin if the corresponding P1DDR bit is set

to 1, and a generic input pin if this bit is cleared to 0.

Mode 6 and 7 (Single-Chip Mode): Port 1 functions as an input/output port. A pin in port 1

becomes an output port if the corresponding P1DDR bit is set to 1, and an input port if this bit is

cleared to 0.

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In modes 1 to 4, P1DDR bits are always read as 1, and cannot be modified.

In modes 5 to 7, P1DDR is a write-only register. Its value cannot be read. All bits return 1 when

read.

P1DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 to 7, by a reset and in

hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a

transition is made to software standby mode while port 1 is functioning as an input/output port

and a P1DDR bit is set to 1, the corresponding pin maintains its output state.

Port 1 Data Register (P1DR): P1DR is an 8-bit readable/writable register that stores port 1

output data. When port 1 functions as an output port, the value of this register is output. When

this register is read, the pin logic level is read for bits for which the P1DDR setting is 0, and the

P1DR value is read for bits for which the P1DDR setting is 1.

Bit

Initial value

Read/Write

R/W

Port 1 data 7 to 0

These bits store data for port 1 pins

R/W

P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Section 8 I/O Ports

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8.3 Port 2

8.3.1 Overview

Port 2 is an 8-bit input/output port with the pin configuration shown in figure 8.2. The pin

functions differ according to the operating mode.

In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus

output pins (A15 to A8). In modes 5 (expanded modes with on-chip ROM enabled), settings in the

port 2 data direction register (P2DDR) can designate pins for address bus output (A15 to A8) or

generic input. In mode 6 and 7 (single-chip mode), port 2 is a generic input/output port.

When DRAM is connected to areas 2 to 5, A12 to A8 output row and column addresses in read and

write cycles. For details see section 6.5, DRAM Interface.

Port 2 has software-programmable built-in pull-up transistors.

Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED

or a darlington transistor pair.

Port 2

P2 /A

P2 (input/output)

A (output)

Port 2 pins Mode 6 and 7Modes 1 to 4

P2 (input)/A (output)

Modes 5

Figure 8.2 Port 2 Pin Configuration

Section 8 I/O Ports

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8.3.2 Register Descriptions

Table 8.3 summarizes the registers of port 2.

Table 8.3 Port 2 Registers

Initial Value

Address*Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7

H'EE001 Port 2 data direction register P2DDR W H'FF H'00

H'FFFD1 Port 2 data register P2DR R/W H'00 H'00

H'EE03C Port 2 input pull-up MOS control

Note: * Lower 20 bits of the address in advanced mode.

Port 2 Data Direction Register (P2DDR): P2DDR is an 8-bit write-only register that can select

input or output for each pin in port 2.

Bit

Modes

1 to 4 Initial value

Read/Write

Initial value

Read/Write

Modes

5 to 7

P2 DDR



P2 DDR



P2 DDR



P2 DDR



P2 DDR



P2 DDR



P2 DDR



P2 DDR



Port 2 data direction 7 to 0

These bits select input or

output for port 2 pins

Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P2DDR values are fixed at 1.

Port 2 functions as an address bus.

Modes 5 (Expanded Modes with On-Chip ROM Enabled): Following a reset, port 2 is an

input port. A pin in port 2 becomes an address output pin if the corresponding P2DDR bit is set to

1, and a generic input port if this bit is cleared to 0.

Mode 6 and 7 (Single-Chip Mode): Port 2 functions as an input/output port. A pin in port 2

becomes an output port if the corresponding P2DDR bit is set to 1, and an input port if this bit is

cleared to 0.

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In modes 1 to 4, P2DDR bits are always read as 1, and cannot be modified.

In modes 5 to 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when

read.

P2DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 to 7, by a reset and in

hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a

transition is made to software standby mode while port 2 is functioning as an input/output port

and a P2DDR bit is set to 1, the corresponding pin maintains its output state.

Port 2 Data Register (P2DR): P2DR is an 8-bit readable/writable register that stores output data

for Port 2. When port 2 functions as an output port, the value of this register is output. When a bit

in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is returned. When

a bit in P2DDR is cleared to 0, if port 2 is read the corresponding pin logic level is read.

Bit

Initial value

Read/Write

R/W

Port 2 data 7 to 0

These bits store data for port 2 pins

R/W

P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Port 2 Input Pull-Up MOS Control Register (P2PCR): P2PCR is an 8-bit readable/writable

Bit

Initial value

Read/Write

P2 PCR

R/W

Port 2 input pull-up MOS control 7 to 0

These bits control input pull-up

transistors built into port 2

P2 PCR

R/W

P2 PCR

R/W

P2 PCR

R/W

P2 PCR

R/W

P2 PCR

R/W

P2 PCR

R/W

P2 PCR

R/W

In modes 5 to 7, when a P2DDR bit is cleared to 0 (selecting generic input), if the corresponding

bit in P2PCR is set to 1, the input pull-up transistor is turned on.

Section 8 I/O Ports

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P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting.

Table 8.4 Input Pull-Up Transistor States (Port 2)

Mode Reset Hardware

Standby Mode Software

Standby Mode Other Modes

Off Off Off Off

Off Off On/off On/off

Legend

Off: The input pull-up transistor is always off.

On/off: The input pull-up transistor i s on if P2PCR = 1 and P2DDR = 0. Otherwise, it is off.

Section 8 I/O Ports

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8.4 Port 3

8.4.1 Overview

Port 3 is an 8-bit input/output port with the pin configuration shown in figure 8.3. Port 3 is a data

bus in modes 1 to 5 (expanded modes) and a generic input/output port in mode 6, 7 (single-chip

mode).

Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a

darlington transistor pair.

Port 3

P3 /D

P3 (input/output)

D (input/output)

Port 3 pins Mode 6 and 7Modes 1 to 5

Figure 8.3 Port 3 Pin Configuration

8.4.2 Register Descriptions

Table 8.5 summarizes the registers of port 3.

Table 8.5 Port 3 Registers

Address*Name Abbreviation R/W Initial Value

H'EE002 Port 3 data direction register P3DDR W H'00

H'FFFD2 Port 3 data register P3DR R/W H'00

Note: * Lower 20 bits of the address in advanced mode.

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Port 3 Data Direction Register (P3DDR): P3DDR is an 8-bit write-only register that can select

input or output for each pin in port 3.

Bit

Initial value

Read/Write

P3 DDR

Port 3 data direction 7 to 0

These bits select input or output for port 3 pins

P3 DDR

Modes 1 to 5 (Expanded Modes): Port 3 functions as a data bus, regardless of the P3DDR

settings.

Mode 6 and 7 (Single-Chip Mode): Port 3 functions as an input/output port. A pin in port 3

becomes an output port if the corresponding P3DDR bit is set to 1, and an input port if this bit is

cleared to 0.

P3DDR is a write-only register. Its value cannot be read. All bits return 1 when read.

P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting. Therefore, if a transition is made to software standby mode while

port 3 is functioning as an input/output port and a P3DDR bit is set to 1, the corresponding pin

maintains its output state.

Port 3 Data Register (P3DR): P3DR is an 8-bit readable/writable register that stores output data

for port 3. When port 3 functions as an output port, the value of this register is output. When a bit

in P3DDR is set to 1, if port 3 is read the value of the corresponding P3DR bit is returned. When

a bit in P3DDR is cleared to 0, if port 3 is read the corresponding pin logic level is read.

Bit

Initial value

Read/Write

R/W

Port 3 data 7 to 0

These bits store data for port 3 pins

R/W

P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Section 8 I/O Ports

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8.5 Port 4

8.5.1 Overview

Port 4 is an 8-bit input/output port with the pin configuration shown in figure 8.4. The pin

functions differ depending on the operating mode.

In modes 1 to 5 (expanded modes), when the bus width control register (ABWCR) designates

areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic

input/output port. When at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip

operates in 16-bit bus mode and port 4 becomes part of the data bus. In mode 6, 7 (single-chip

mode), port 4 is a generic input/output port.

Port 4 has software-programmable built-in pull-up transistors.

Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a

darlington transistor pair.

Port 4

P4 /D

P4 (input/output)/D7 (input/output)

P4 (input/output)/D6 (input/output)

P4 (input/output)/D5 (input/output)

P4 (input/output)/D4 (input/output)

P4 (input/output)/D3 (input/output)

P4 (input/output)/D2 (input/output)

P4 (input/output)/D1 (input/output)

P4 (input/output)/D0 (input/output)

Port 4 pins Modes 1 to 5

P4 (input/output)

Mode 6 and 7

Figure 8.4 Port 4 Pin Configuration

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8.5.2 Register Descriptions

Table 8.6 summarizes the registers of port 4.

Table 8.6 Port 4 Registers

Address*Name Abbreviation R/W Initial Value

H'EE003 Port 4 data direction register P4DDR W H'00

H'FFFD3 Port 4 data register P4DR R/W H'00

H'EE03E Port 4 input pull-up control register P4PCR R/W H'00

Note: * Lower 20 bits of the address in advanced mode.

Port 4 Data Direction Register (P4DDR): P4DDR is an 8-bit write-only register that can select

input or output for each pin in port 4.

Bit

Initial value

Read/Write

P4 DDR

Port 4 data direction 7 to 0

These bits select input or output for port 4 pins

P4 DDR

Modes 1 to 5 (Expanded Modes): When all areas are designated as 8-bit-access areas by the bus

controller’s bus width control register (ABWCR), selecting 8-bit bus mode, port 4 functions as an

input/output port. In this case, a pin in port 4 becomes an output port if the corresponding P4DDR

bit is set to 1, and an input port if this bit is cleared to 0.

When at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4

functions as part of the data bus, regardless of the P4DDR settings.

Mode 6 and 7 (Single-Chip Mode): Port 4 functions as an input/output port. A pin in port 4

becomes an output port if the corresponding P4DDR bit is set to 1, and an input port if this bit is

cleared to 0.

P4DDR is a write-only register. Its value cannot be read. All bits return 1 when read.

P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting.

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ABWCR and P4DDR are not initialized in software standby mode. Therefore, if a transition is

made to software standby mode while port 4 is functioning as an input/output port and a P4DDR

bit is set to 1, the corresponding pin maintains its output state.

Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data

for port 4. When port 4 functions as an output port, the value of this register is output. When a bit

in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned. When

a bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin logic level is read.

Bit

Initial value

Read/Write

R/W

Port 4 data 7 to 0

These bits store data for port 4 pins

R/W

P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Port 4 Input Pull-Up MOS Control Register (P4PCR): P4PCR is an 8-bit readable/writable

Bit

Initial value

Read/Write

P4 PCR

R/W

Port 4 input pull-up control 7 to 0

These bits control input pull-up transistors built into port 4

P4 PCR

R/W

P4 PCR

R/W

P4 PCR

R/W

P4 PCR

R/W

P4 PCR

R/W

P4 PCR

R/W

P4 PCR

R/W

In mode 6 and 7 (single-chip mode), and in 8-bit bus mode in modes 1 to 5 (expanded modes),

when a P4DDR bit is cleared to 0 (selecting generic input), if the corresponding P4PCR bit is set

to 1, the input pull-up transistor is turned on.

P4PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting.

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Table 8.7 summarizes the states of the input pull-ups in each operating mode.

Table 8.7 Input Pull-Up Transistor States (Port 4)

Mode Reset Hardware

Standby Mode Software

Standby Mode Other Modes

1 to 5 8-bit bus mode Off Off On/off On/off

16-bit bus mode Off Off

6 and 7 On/off On/off

Legend

Off: The input pull- up transistor is always off.

On/off: The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off.

Section 8 I/O Ports

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8.6 Port 5

8.6.1 Overview

Port 5 is a 4-bit input/output port with the pin configuration shown in figure 8.5. The pin

functions differ depending on the operating mode.

In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 5 consists of address output

pins (A19 to A16). In modes 5 (expanded modes with on-chip ROM enabled), settings in the port 5

data direction register (P5DDR) designate pins for address bus output (A19 to A16) or generic

input. In mode 6, 7 (single-chip mode), port 5 is a generic input/output port.

Port 5 has software-programmable built-in pull-up transistors.

Pins in port 5 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or

a darlington transistor pair.

Port 5

P5 /A

A (output)

P5 (input)/A (output)

Port 5

pins Modes 1 to 4 Mode 5

P5 (input/output)

Mode 6 and 7

Figure 8.5 Port 5 Pin Configuration

Section 8 I/O Ports

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8.6.2 Register Descriptions

Table 8.8 summarizes the registers of port 5.

Table 8.8 Port 5 Registers

Initial Value

Address*Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7

H'EE004 Port 5 data direction register P5DDR W H'FF H'F0

H'FFFD4 Port 5 data register P5DR R/W H'F0 H'F0

H'EE03F Port 5 input pull-up control regi ster P5PCR R/W H'F0 H'F0

Note: * Lower 20 bits of the address in advanced mode.

Port 5 Data Direction Register (P5DDR): P5DDR is an 8-bit write-only register that can select

input or output for each pin in port 5.

Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified.

Bit

Modes

1 to 4 Initial value

Read/Write

Initial value

Read/Write

Modes

5 to 7

—

P5 DDR

—

P5 DDR

—

P5 DDR

—

P5 DDR

—

Reserved bits Port 5 data direction 3 to 0

These bits select input or

output for port 5 pins

Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P5DDR values are fixed at 1.

Port 5 functions as an address bus.

Modes 5 (Expanded Modes with On-Chip ROM Enabled): Following a reset, port 5 is an

input port. A pin in port 5 becomes an address output pin if the corresponding P5DDR bit is set to

1, and an input port if this bit is cleared to 0.

Mode 6 and 7 (Single-Chip Mode): Port 5 functions as an input/output port. A pin in port 5

becomes an output port if the corresponding P5DDR bit is set to 1, and an input port if this bit is

cleared to 0.

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In modes 1 to 4, P5DDR bits are always read as 1, and cannot be modified.

In modes 5 to 7, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when

read.

P5DDR is initialized to H'FF in modes 1 to 4, and to H'F0 in modes 5 to 7, by a reset and in

hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a

transition is made to software standby mode while port 5 is functioning as an input/output port

and a P5DDR bit is set to 1, the corresponding pin maintains its output state.

Port 5 Data Register (P5DR): P5DR is an 8-bit readable/writable register that stores output data

for port 5. When port 5 functions as an output port, the value of this register is output. When a bit

in P5DDR is set to 1, if port 5 is read the value of the corresponding P5DR bit is returned. When

a bit in P5DDR is cleared to 0, if port 5 is read the corresponding pin logic level is read.

Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified.

Bit

Initial value

Read/Write

—

R/W

Reserved bits These bits store data

for port 5 pins

Port 5 data 3 to 0

P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

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Port 5 Input Pull-Up MOS Control Register (P5PCR): P5PCR is an 8-bit readable/writable

Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified.

Bit

Initial value

Read/Write



P5 PCR

R/W

P5 PCR

R/W

P5 PCR

R/W

P5 PCR

R/W

Reserved bits These bits control input pull-up

transistors built into port 5

Port 5 input pull-up control 3 to 0

In modes 5 to 7, when a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding

bit in P5PCR is set to 1, the input pull-up transistor is turned on.

P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting.

Table 8.9 summarizes the states of the input pull-ups in each mode.

Table 8.9 Input Pull-Up Transistor States (Port 5)

Mode Reset Hardware Standby Mode Software Standby Mode Other Modes

Off Off Off Off

Off Off On/off On/off

Legend

Off: The input pull- up transistor is always off.

On/off: The input pull-up transistor is on if P5PCR = 1 and P5DDR = 0. Otherwise, it is off.

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8.7 Port 6

8.7.1 Overview

Port 6 is an 8-bit input/output port that is also used for input and output of bus control signals

(

LWR

HWR

BACK

BREQ

WAIT

) and for clock (φ) output.

In modes 1 to 5 (expanded modes), the pin functions are P67 (generic input)/φ,

LWR

HWR

, P62/

BACK

, P61/

BREQ

, and P60/

WAIT

). See table 8.11 for the selection of the pin functions.

In modes 6 and 7 (single-chip modes), P67 functions as a generic input port or ø output, and P66

to P60 function as generic input/output ports.

When DRAM is connected to areas 2 to 5,

LWR

HWR

, and

also function as

LCAS

UCAS

and

, respectively. For details see section 6.5, DRAM Interface.

Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a

darlington transistor pair.

Port 6

P6 /

LWR

HWR

BACK

BREQ

WAIT

Port 6 pins

LWR

HWR

BACK

BREQ

WAIT

Modes 1 to 5

(expanded modes)

(output)

(input)

Mode 6 and 7

(single-chip mode)

(input) / φ(output)

(input/output)

(input)/

(input/output)/

Figure 8.6 Port 6 Pin Configuration

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8.7.2 Register Descriptions

Table 8.10 summarizes the registers of port 6.

Table 8.10 Port 6 Registers

Address*Name Abbreviation R/W Initial Value

H'EE005 Port 6 data direction register P6DDR W H'80

H'FFFD5 Port 6 data register P6DR R/W H'80

Note: *Lower 20 bits of the address in advanced mode.

Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select

input or output for each pin in port 6.

Bit 7 is reserved. It is fixed at 1, and cannot be modified.

Bit

Initial value

Read/Write

—

P6 DDR

Port 6 data direction 6 to 0

These bits select input or output for port 6 pins

Reserved bit

Modes 1 to 5 (Expanded Modes): P67 functions as the clock output pin (φ) or an input port. P67

is the clock output pin (ø) if the PSTOP bit in MSTRCH is cleared to 0 (initial value), and an

input port if this bit is set to 1.

P66 to P63 function as bus control output pins (

LWR

HWR

, and

), regardless of the

settings of bits P66DDR to P63DDR.

P62 to P60 function as bus control input/output pins (

BACK

BREQ

, and

WAIT

) or input/output

ports. For the method of selecting the pin functions, see table 8.11.

When P62 to P60 function as input/output ports, the pin becomes an output port if the

corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.

Mode 6 and 7 (Single-Chip Mode): P67 functions as the clock output pin (φ) or an input port.

P66 to P60 function as generic input/output ports. P67 is the clock output pin (φ) if the PSTOP bit

in MSTCRH is cleared to 0 (initial value), and an input port if this bit is set to 1. A pin in port 6

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becomes an output port if the corresponding bit of P66DDR to P60DDR is set to 1, and an input

port if this pin is cleared to 0.

P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read.

P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting. Therefore, if a transition is made to software standby mode while

port 6 is functioning as an input/output port and a P6DDR bit is set to 1, the corresponding pin

maintains its output state.

Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data

for port 6. When port 6 functions as an output port, the value of this register is output. For bit 7, a

value of 1 is returned if the bit is read while the PSTOP bit in MSTCRH is cleared to 0, and the

P67 pin logic level is returned if the bit is read while the PSTOP bit is set to 1. Bit 7 cannot be

modified. For bits 6 to 0, the pin logic level is returned if the bit is read while the corresponding

bit in P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the

corresponding bit in P6DDR is set to 1.

Bit

Initial value

Read/Write

R/W

Port 6 data 7 to 0

These bits store data for port 6 pins

P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

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Table 8.11 Port 6 Pin Functions in Modes 1 to 5

Pin Pin Functions and Selection Method

P67/φBit PSTOP in MSTCRH selects the pin function.

PSTOP 0 1

Pin function φ output P67 input

LWR

Functions as

LWR

regardless of the setting of bit P66DDR

P66DDR 0 1

Pin function

LWR

output*

Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1 and bit CSEL in DRCRB i s 1 ,

LWR

output functions as

LCAS

HWR

Functions as

HWR

regardless of the setting of bit P65DDR

P65DDR 0 1

Pin function

HWR

output*

Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1 and bit CSEL in DRCRB i s 1 ,

HWR

output functions as

UCAS

Functions as

regardless of the setting of bit P64DDR

P64DDR 0 1

Pin function

output*

Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1,

output functions as

Functions as

regardless of the setting of bit P63DDR

P63DDR 0 1

Pin function

output

P62/

BACK

Bit BRLE in BRCR and bit P62DDR select th e pin function as follo ws

BRLE 0 1

P62DDR 0 1 —

Pin function P62 input P62 output

BACK

output

P61/

BREQ

Bit BRLE in BRCR and bit P61DDR select th e pin function as follo ws

BRLE 0 1

P61DDR 0 1 —

Pin function P61 input P61 output

BREQ

input

P60/

WAIT

Bit WAITE in BCR and bit P60DDR selec t the pin function a s follows.

WAITE 0 1

P60DDR 0 1 0*

Pin function P60 input P60 output

WAIT

input

Note: * Do not set bit P60DDR to 1.

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8.8 Port 7

8.8.1 Overview

Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog

output from the D/A converter. The pin functions are the same in all operating modes. Figure 8.7

shows the pin configuration of port 7.

See section 15, A/D Converter, for details of the A/D converter analog input pins, and section 16,

D/A Converter, for details of the D/A converter analog output pins.

Port 7

P7 (input)/AN (input)/DA (output)

P7 (input)/AN (input)

Port 7 pins

Figure 8.7 Port 7 Pin Configuration

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8.8.2 Register Description

Table 8.12 summarizes the port 7 register. Port 7 is an input port, and port 7 has no data direction

Table 8.12 Port 7 Data Register

Address*Name Abbreviation R/W Initial Value

H'FFFD6 Port 7 data register P7DR R Undetermined

Note: * Lower 20 bits of the address in advanced mode.

Port 7 Data Register (P7DR)

Bit

Initial value

Read/Write

—*

Note: * Determined by pins P7

to P7

—*

When port 7 is read, the pin logic levels are always read. P7DR cannot be modified.

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8.9 Port 8

8.9.1 Overview

Port 8 is a 5-bit input/output port that is also used for

3 to

0 output,

RFSH

output,

IRQ

3 to

IRQ

0 input, and A/D converter

ADTRG

input. Figure 8.8 shows the pin configuration of port 8.

In modes 1 to 5 (expanded modes), port 8 can provide

3 to

0 output,

RFSH

output,

IRQ

3 to

IRQ

0 input, and

ADTRG

input. See table 8.14 for the selection of pin functions in expanded

modes.

In modes 6 and 7 (single-chip modes), port 8 can provide

IRQ

3 to

IRQ

0 input and

ADTRG

input.

See table 8.15 for the selection of pin functions in single-chip mode.

See section 15, A/D Converter, for a description of the A/D converter's

ADTRG

input pin.

The

IRQ

3 to

IRQ

0 functions are selected by IER settings, regardless of whether the pin is used for

input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts.

When DRAM is connected to areas 2 to 5, the

3 and

2 output pins function as

RAS

output

pins for each area. For details see section 6.5, DRAM Interface.

Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a

darlington transistor pair.

Pins P82 to P80 have Schmitt-trigger inputs.

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Port 8

P8 /

P8 / /

Port 8 pins

RFSH

IRQ / ADTRG

IRQ

P8 (input)/ (output)

P8 (input)/ (output)/ (input) / ADTRG (input)

P8 (input)/ (output)/ (input)

P8 (input/output)/ CS

(output)/IRQ

(input)

P8 (input/output)/ (output)/ (input)

Pin functions in modes 1 to 5

(expanded modes)

RFSH

IRQ

P8 /(input/output)

P8 /(input/output)/ (input) /

P8 /(input/output)/ (input)

Pin functions in mode 6 and 7

(single-chip mode)

IRQ

ADTRG (input)

Figure 8.8 Port 8 Pin Configuration

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8.9.2 Register Descriptions

Table 8.13 summarizes the registers of port 8.

Table 8.13 Port 8 Registers

Initial Value

Address*Name Abbreviation R/W Mode 1 to 4 Mode 5 to 7

H'EE007 Port 8 data direction

H'FFFD7 Port 8 data register P8DR R/W H'E0 H'E0

Note: * Lower 20 bits of the address in advanced mode.

Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select

input or output for each pin in port 8.

Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.



P8 DDR

Reserved bits Port 8 data direction 4 to 0

These bits select input or

output for port 8 pins

Bit

Modes

1 to 4 Initial value

Read/Write

Initial value

Read/Write

Modes

5 to 7

Modes 1 to 5 (Expanded Modes): When bits in P8DDR bit are set to 1, P84 to P81 become

3 output pins. When bits in P8DDR are cleared to 0, the corresponding pins become input

ports. However, P81 can also be used as an output port, depending on the setting of bits DRAS2 to

DRAS0 in DRAM control register A (DRCRA). For details see section 6.5.2, DRAM Space and

RAS

Output Pin Settings.

In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset P84 functions as

the

0 output, while

1 to

3 are input ports. In mode 5 (expanded mode with on-chip ROM

enabled), following a reset

0 to

3 are all input ports.

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When the refresh enable bit (RFSHE) in DRCRA is set to 1, P80 is used for

RFSH

output. When

RFSHE is cleared to 0, P80 becomes an input/output port according to the P8DDR setting. For

details see table 8.14.

Mode 6 and 7 (Single-Chip Mode): Port 8 is a generic input/output port. A pin in port 8

becomes an output port if the corresponding P8DDR bit is set to 1, and an input port if this bit is

cleared to 0.

P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.

P8DDR is initialized to H'F0 in modes 1 to 4, and to H'E0 in modes 5 to 7, by a reset and in

hardware standby mode. In software standby mode P8DDR retains its previous setting.

Therefore, if a transition is made to software standby mode while port 8 is functioning as an

input/output port and a P8DDR bit is set to 1, the corresponding pin maintains its output state.

Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data

for port 8. When port 8 functions as an output port, the value of this register is output. When a bit

in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is returned. When

a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin logic level is read.

Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.

Bit

Initial value

Read/Write



R/W

Reserved bits Port 8 data 4 to 0

These bits store data

for port 8 pins

P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

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Table 8.14 Port 8 Pin Functions in Modes 1 to 5

Pin Pin Functions and Selection Method

P84/

0Bit P84DDR selects th e pin function as follo ws

P84DDR 0 1

Pin function P84 input

0 output

P83/

IRQ

ADTRG

Bit P83DDR selects th e pin function as follo ws

P83DDR 0 1

Pin function P83 input

1 output

IRQ

3 input

ADTRG

input

P82/

IRQ

2The DRAM in t erface settings by bi ts DRAS2 to DRAS0 i n DRCRA, and bit P82DDR, select

the pin function as follow s.

DRAM interf ace

settings (1) in table below |(2) in table below

P82DDR 0 1 —

Pin function P82 input

2 output

2 output*

IRQ

3 input

Note: *

2 is output as

RAS

DRAM interf ace

setting (1) (2)

DRAS2 0 1

DRAS1 0101

DRAS0 01010101

P81/

IRQ

1The DRAM in t erface settings by bi ts DRAS2 to DRAS0 i n DRCRA, and bit P81DDR, select

the pin function as follow s.

DRAM interf ace

settings (1) in table below (2) in table below (3) in table below

P81DDR 0101 —

Pin function P81 input

output pin P81 input

pin P81 output

3 output pin*

IRQ

1 input pin

Note: *

3 is output as

RAS

DRAM interf ace

setting (1) (3) (2) (3) (2)

DRAS2 0 1

DRAS1 0101

DRAS0 01010101

P80/

RFSH

IRQ

0Bit RFSHE in DRCRA and bit P80DDR select the p in function as follows.

RFSHE 0 1*

P80DDR 0 1 —

Pin function P80 input P80 output

RFSH

output

IRQ

0 input

Note: * If areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1.

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Table 8.15 Port 8 Pin Functions in Mode 6 and 7

Pin Pin Functions and Selection Method

P84Bit P84DDR selects the pin function as follows

P84DDR 0 1

Pin function P84 input P84 output

P83/

IRQ

ADTRG

Bit P83DDR selects the pin function as follows

P83DDR 0 1

Pin function P83 input P83 output

IRQ

3 input

ADTRG

input

P82/

IRQ

2Bit P82DDR selects the pin function as follows

P82DDR 0 1

Pin function P82 input P82 output

IRQ

2 input

P81/

IRQ

1Bit P81DDR selects the pin function as follows

P81DDR 0 1

Pin function P81 input P81 output

IRQ

1 input

P80/

IRQ

0Bit P80DDR select the pin function as follows

P80DDR 0 1

Pin function P80 input P80 output

IRQ

0 input

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8.10 Port 9

8.10.1 Overview

Port 9 is a 6-bit input/output port that is also used for input and output (TxD0, TxD1, RxD0, RxD1,

SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for

IRQ

and

IRQ

4 input. See table 8.17 for the selection of pin functions.

The

IRQ

5 and

IRQ

4 functions are selected by IER settings, regardless of whether the pin is used

for input or output. Caution is therefore required. For details see section 5.3.1, External

Interrupts.

Port 9 has the same set of pin functions in all operating modes. Figure 8.9 shows the pin

configuration of port 9.

Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a

darlington transistor pair.

Port 9

P9 (input/output)/SCK

P9 (input/output)/RxD (input)

P9 (input/output)/TxD (output)

Port 9 pins

(input/output)/IRQ (input)

Figure 8.9 Port 9 Pin Configuration

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8.10.2 Register Descriptions

Table 8.16 summarizes the registers of port 9.

Table 8.16 Port 9 Registers

Address*Name Abbreviation R/W Initial Value

H'EE008 Port 9 data direction register P9DDR W H'C0

H'FFFD8 Port 9 data register P9DR R/W H'C0

Note: * Lower 20 bits of the address in advanced mode.

Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select

input or output for each pin in port 9.

Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified.

Bit

Initial value

Read/Write



P9 DDR

Reserved bits Port 9 data direction 5 to 0

These bits select input or

output for port 9 pins

When port 9 functions as an input/output port, a pin in port 9 becomes an output port if the

corresponding P9DDR bit is set to 1, and an input port if this bit is cleared to 0. For the method of

selecting the pin functions, see table 8.17.

P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read.

P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting. Therefore, if a transition is made to software standby mode while

port 9 is functioning as an input/output port and a P9DDR bit is set to 1, the corresponding pin

maintains its output state.

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Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data

for port 9. When port 9 functions as an output port, the value of this register is output. When a bit

in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When

a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin logic level is read.

Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified.

Bit

Initial value

Read/Write



R/W

Reserved bits Port 9 data 5 to 0

These bits store data

for port 9 pins

P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

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Table 8.17 Port 9 Pin Functions

Pin Pin Functions and Selection Method

P95/SCK1/

IRQ

5Bit C/

in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P95DDR select the pin function

as follows

CKE1 0 1

01—

CKE0 0 1 ——

P95DDR 0 1 ———

Pin function P95

input P95

output SCK1 output SCK1 output SCK1 input

IRQ

5 input

P94/SCK0/

IRQ

4Bit C/

in SMR of SCI0, bits CKE0 and CKE1 in SCR, and bit P94DDR select the pin function

as follows

CKE1 0 1

01—

CKE0 0 1 ——

P94DDR 0 1 ———

Pin function P94

input P94

output SCK0 output SCK0 output SCK0 input

IRQ

4 input

P93/RxD1Bit RE in SCR of SCI1, bit SMIF in SCMR, and bit P93DDR select the pin function as follows.

SMIF 0 1

RE 0 1 —

P93DDR 0 ——

Pin function P93 input P93 output RxD1 input RxD1 input

P92/RxD0Bit RE in SCR of SCI0, bit SMIF in SCMR, and bit P92DDR select the pin function as follows

SMIF 0 1

RE 0 1 —

P92DDR 0 1 ——

Pin function P92 input P92 output RxD0 input RxD0 input

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Pin Pin Functions and Selection Method

P91/TxD1Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P91DDR select the pin function a s follows.

SMIF 0 1

TE 0 1 —

P91 DDR 0 1 ——

Pin function P91 input P91 output TxD1 output TxD1 output*

Note: * Functions as the TxD1 output pin, but there are two states: one in which the pin is

driven, and another in which the pin is at high-impedance.

P90/TxD0Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P90DDR select the pin function a s follows.

SMIF 0 1

TE 0 1 —

P90DDR 0 1 ——

Pin function P90 input P90 output TxD0 output TxD0 output*

Note: * Functions as the TxD0 output pin, but there are two states: one in which the pin is

driven, and another in which the pin is at highimpedance.

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8.11 Port A

8.11.1 Overview

Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the

programmable timing pattern controller (TPC), input and output, (TIOCB2, TIOCA2, TIOCB1,

TIOCA1, TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit timer, input

(TCLKD, TCLKC, TCLKB, TCLKA) to the 8-bit timer, output (

TEND

0) from the DMA

controller (DMAC), and address output (A23 to A20). A reset or hardware standby transition

leaves port A as an input port, except that in modes 3 and 4, one pin is always used for A20 output.

See table 8.19 to 8.21 for the selection of pin functions.

Usage of pins for TPC, 16-bit timer, 8-bit timer, and DMAC input and output is described in the

sections on those modules. For output of address bits A23 to A20 in modes 3, 4, and 5, see section

6.2.4, Bus Release Control Register (BRCR). Pins not assigned to any of these functions are

available for generic input/output. Figure 8.10 shows the pin configuration of port A.

Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a

darlington transistor pair. Port A has Schmitt-trigger inputs.

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Port A

PA /TP /TIOCB /A

PA /TP /TIOCA /A21

PA /TP /TIOCB /A22

PA /TP /TIOCA /A23

PA /TP /TIOCB /TCLKD

PA /TP /TIOCA /TCLKC

PA /TP /TEND /TCLKB

PA /TP /TEND /TCLKA

Port A pins

PA (input/output)/TP (output)/TIOCB (input/output)

PA (input/output)/TP (output)/TIOCA (input/output)

PA (input/output)/TP (output)/TIOCB (input/output)

PA (input/output)/TP (output)/TIOCA (input/output)

Pin functions in modes 1, 2, 6, and 7

PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)

PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)

PA (input/output)/TP (output)/TEND (output)/TCLKB (input)

PA (input/output)/TP (output)/TEND (output)/TCLKA (input)

Pin functions in mode 5

A (output)

PA (input/output)/TP (output)/TIOCA (input/output)/A (output)

PA (input/output)/TP (output)/TIOCB (input/output)/A (output)

PA (input/output)/TP (output)/TIOCA (input/output)/A (output)

Pin functions in modes 3, 4

PA (input/output)/TP (output)/TEND (output)/TCLKA (input)

PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)

PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)

PA (input/output)/TP (output)/TEND (output)/TCLKB (input)

PA7 (input/output)/TP7 (output)/TIOCB2 (input/output)/A (output)

PA6 (input/output)/TP6 (output)/TIOCA2 (input/output)/A (output)

PA5 (input/output)/TP5 (output)/TIOCB1 (input/output)/A (output)

PA4 (input/output)/TP4 (output)/TIOCA1 (input/output)/A (output)

PA3 (input/output)/TP3 (output)/TIOCB0 (input/output)/TCLKD (input)

PA2 (input/output)/TP2 (output)/TIOCA0 (input/output)/TCLKC (input)

PA1 (input/output)/TP1 (output)/TEND1 (output)/TCLKB (input)

PA0 (input/output)/TP0 (output)/TEND0 (output)/TCLKA (input)

Figure 8.10 Port A Pin Configuration

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8.11.2 Register Descriptions

Table 8.18 summarizes the registers of port A.

Table 8.18 Port A Registers

Initial Value

Address*Name R/W Modes 1, 2, 5, 6, and 7 Modes 3, 4

H'EE009 Port A data direction

H'FFFD9 Port A data register PADR R/W H'00 H'00

Note: * Lower 20 bits of the address in advanced mode.

Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can

select input or output for each pin in port A. When pins are used for TPC output, the

corresponding PADDR bits must also be set.

PA DDR

—

Port A data direction 7 to 0

These bits select input or output for port A pins

PA DDR

Bit

Modes

3, 4 Initial value

Read/Write

Initial value

Read/Write

Modes

1, 2, 5,

6 and 7

The pin functions that can be selected for pins PA7 to PA4 differ between modes 1, 2, 6, and 7,

and modes 3 to 5. For the method of selecting the pin functions, see tables 8.19 and 8.20.

The pin functions that can be selected for pins PA3 to PA0 are the same in modes 1 to 7. For the

method of selecting the pin functions, see table 8.21.

When port A functions as an input/output port, a pin in port A becomes an output port if the

corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and

4, PA7DDR is fixed at 1 and PA7 functions as the A20 address output pin.

PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.

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PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, 6, and 7.

It is initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software

standby mode it retains its previous setting. Therefore, if a transition is made to software standby

mode while port A is functioning as an input/output port and a PADDR bit is set to 1, the

corresponding pin maintains its output state.

Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output

data for port A. When port A functions as an output port, the value of this register is output.

When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is

returned. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level

is read.

Bit

Initial value

Read/Write

R/W

Port A data 7 to 0

These bits store data for port A pins

PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

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Table 8.19 Port A Pin Functions (Modes 1, 2, 6, 7)

Pin Pin Functions and Selection Method

PA7/TP7/

TIOCB2

Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit PA7DDR select the pin

function as follow s.

16-bit timer channel 2

settings (1) in table below (2) in table below

PA7DDR —011

NDER7 ——01

Pin function TIOCB2 output PA7 input PA7 output TP7 output

TIOCB2 input*

Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0.

16-bit timer channel 2

settings (2) (1) (2)

IOB2 0 1

IOB1 0 0 1 —

IOB0 0 1 ——

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Pin Pin Functions and Selection Method

PA6/TP6/

TIOCA2

Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, and bit PA6DDR sele ct the pin

function as follow s.

16-bit timer channel 2

settings (1) in table below (2) in table below

PA6DDR —011

NDER6 ——01

Pin function TIOCA2 output PA6 input PA6 output TP6 output

TIOCA2 input*

Note: * TIOC A2 input when IOA2 = 1.

16-bit timer channel 2

settings (2) (1) (2) (1)

PWM2 0 1

IOA2 0 1 —

IOA1 001 ——

IOA0 0 1 —— —

PA5/TP5/

TIOCB1

Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, and bit PA5DDR sele ct the pin

function as follow s.

16-bit timer channel 1

settings (1) in table below (2) in table below

PA5DDR —011

NDER5 ——01

Pin function TIOCB1 output PA5 input PA5 output TP5 output

TIOCB1 input*

Note: * TIOC B1 input when IOB2 = 1 and PWM1 = 0.

16-bit timer channel 1

settings (2) (1) (2)

IOB2 0 1

IOB1 0 0 1 —

IOB0 0 1 ——

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Pin Pin Functions and Selection Method

PA4/TP4/

TIOCA1

Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, and bit PA4DDR select the pin

function as follow s.

16-bit timer channel 1

settings (1) in table below (2) in table below

PA4DDR —011

NDER4 ——01

Pin function TIOCA1 output PA4 input PA4 output TP4 output

TIOCA1 input*

Note: * TIOCA1 input when IOA2 = 1.

16-bit timer channel 1

settings (2) (1) (2) (1)

PWM1 0 1

IOA2 0 1 —

IOA1 001——

IOA0 0 1 —— —

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Table 8.20 Port A Pin Functions (Modes 3, 4, 5)

Pin Pin Functions and Selection Method

PA7/TP7/ Modes 3 and 4: Always used as A20 output.

TIOCB2/ A20 Pin function A20 output

Mode 5:

Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, bit A20E in BRCR, and bit PA7DDR

select the pin function as follows.

A20E 1 0

16-bit timer channel 2

settings (1) in table below (2) in table below —

PA7DDR —011—

NDER7 ——01—

Pin function TIOCB2 output PA7 input PA7 output TP7 output A20 output

TIOCB2 input*

Note: * TIOC B2 input when IOB2 = 1 and PWM2 = 0.

16-bit timer channel 2 settings (2) (1) (2)

IOB2 0 1

IOB1 0 0 1 —

IOB0 0 1 ——

PA6/TP6/

TIOCA2/A21

Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in BRCR, and bit PA6DDR

select the pin function as follows.

A21E 1 0

16-bit timer channel 2

settings (1) in table below (2) in table below —

PA6DDR —011—

NDER6 ——01—

Pin function TIOCA2 output PA6 input PA6 output TP6 output A21 output

TIOCA2 input*

Note: * TIOC A2 input when IOA2 = 1.

16-bit timer channel 2 settings (2) (1) (2) (1)

PWM2 0 1

IOA2 0 1 —

IOA1 0 0 1 ——

IOA0 0 1 ———

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Pin Pin Functions and Selection Method

PA5/TP5/

TIOCB1/A22

Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, bit A22E in BRCR, and bit PA5DDR

select the pin function as follows.

A22E 1 0

16-bit timer channel 1

settings (1) in table below (2) in table below —

PA5DDR —011—

NDER5 ——01—

Pin function TIOCB1 output PA5 input PA5 output TP5 output A22 output

TIOCB1 input*

Note: * TIOC B1 input when IOB2 = 1 and PWM1 = 0.

16-bit timer channel 1

settings (2) (1) (2)

IOB2 0 1

IOB1 0 0 1 —

IOB0 0 1 ——

PA4/TP4/

TIOCA1/A23

Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, bit A23E in BRCR, and bit PA4DDR

select the pin function as follows.

A23E 1 0

16-bit timer channel 1

settings (1) in table below (2) in table below —

PA4DDR —011—

NDER4 ——01—

Pin function TIOCA1 output PA4 input PA4 output TP4 output A23 output

TIOCA1 input*

Note: * TIOC A1 input when IOA2 = 1.

16-bit timer channel 1

settings (2) (1) (2) (1)

PWM1 0 1

IOA2 0 1 —

IOA1 001——

IOA0 0 1 —— —

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Table 8.21 Port A Pin Functions (Modes 1 to 7)

Pin Pin Functions and Selection Method

PA3/TP3/

TIOCB0/

TCLKD

Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit

timer, bits CKS2 to CKS0 in 8TCR2 of the 8-bit time r, bit NDER3 in NDERA, and bit PA3DDR select the pin

function as follow s.

16-bit timer channel 0

settings (1) in table below (2) in table below

PA3DDR —011

NDER3 ——01

Pin function TIOCB0

output PA3

input PA3

output TP3

output

TIOCB0 input*1

TCLKD input*2

Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0.

2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2

to CKS0 in 8TCR2 are as shown in (3) in the table below.

16-bit timer channel 0

settings (2) (1) (2)

IOB2 0 1

IOB1 0 0 1 —

IOB0 0 1 ——

8-bit timer channel 2

settings (4) (3)

CKS2 0 1

CKS1 —01

CKS0 —01 —

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Pin Pin Functions and Selection Method

PA2/TP2/

TIOCA0/

TCLKC

Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit

timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit time r, bit NDER2 in NDERA, and bit PA2DDR select the pin

function as follow s.

16-bit timer channel 0

settings (1) in table below (2) in table below

PA2DDR —011

NDER2 ——01

Pin function TIOCA0 output PA2

input PA2 output TP2 output

TIOCA0 input*1

TCLKC input*2

Notes: 1. TIOCA0 input when IOA2 = 1.

2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits

CKS2 to CKS0 in 8TCR0 are as shown in (3) in the table below.

16-bit timer channel 0

settings (2) (1) (2) (1)

PWM0 0 1

IOA2 0 1 —

IOA1 001——

IOA0 0 1 —— —

8-bit timer channel 0

settings (4) (3)

CKS2 0 1

CKS1 —01

CKS0 —01 —

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Pin Pin Functions and Selection Method

PA1/TP1/

TCLKB/

TEND

Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in

8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit PA1DDR select the pin function as follows.

PA1DDR 0 1 1

NDER1 —01

Pin function PA1 input PA1 output TP1 output

TCLKB output*1

TEND

1 output*2

Notes: 1. TCLKB input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of

16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR3 are as shown in (1) in the table below.

2. W hen an external request is specified as a DMAC activation source,

TEND

1 output regardless

of bits PA1DDR and NDER1.

8-bit timer channel 3

settings (2) (1)

CKS2 0 1

CKS1 —01

CKS0 —01 —

PA0/TP0/

TCLKA/

TEND

Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in

8TCR1 of the 8-bit timer, bit NDER0 in NDERA, and bit PA0DDR select the pin function as follows.

PA0DDR 0 1

NDER0 —01

Pin function PA0 input PA0 output TP0 output

TCLKA output*1

TEND

0 output*2

Notes: 1. TCLKA input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0 and TPSC0 = 0 in any of

16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in (1) in the table below.

2. W hen an external request is specified as a DMAC activation source,

TEND

0 output regardless

of bits PA0DDR and NDER0.

8-bit timer channel 1

settings (2) (1)

CKS2 0 1

CKS1 —01

CKS0 —01 —

Section 8 I/O Ports

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8.12 Port B

8.12.1 Overview

Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the

programmable timing pattern controller (TPC), input/output (TMIO3, TMO2, TMIO1, TMO0) by

the 8-bit timer,

7 to

4 output, input (

DREQ

0) to the DMA controller (DMAC), input

and output (TxD2, RxD2, SCK2) by serial communication interface channel 2 (SCI2), and output

(

UCAS

LCAS

) by the DRAM interface. See table 8.23 to 8.24 for the selection of pin functions.

A reset or hardware standby transition leaves port B as an input port.

For output of

7 to

4 in modes 1 to 5, see section 6.3.4, Chip Select Signals. When DRAM is

connected to areas 2, 3, 4, and 5, the

4 and

5 output pins become

RAS

output pins for these

areas. For details see section 6.5, DRAM Interface. Pins not assigned to any of these functions

are available for generic input/output. Figure 8.11 shows the pin configuration of port B.

When DRAM is connected to areas 2, 3, 4, and 5, the

4 and

5 output pins become

RAS

output pins for these areas. For details see 6.5, DRAM Interface.

Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive darlington

transistor pair.

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Port B

PB7/TP /RxD

PB6/TP /TxD

PB5/TP /SCK

/LCAS

PB4/TP /UCAS

PB3/TP /TMIO

/DREQ

/CS

PB2/TP /TMO

/CS

PB1/TP /TMIO

/DREQ

/CS

PB0/TP /TMO

/CS

Port B pins

PB7 (input/output)/TP15 (output) /RxD

(input)

PB6 (input/output)/TP14 (output) /TxD

(output)

PB5 (input/output)/TP13 (output) /SCK

(input/output) /LCAS (output)

PB4 (input/output)/TP12 (output) /UCAS (output)

PB3 (input/output)/TP11 (output) /TMIO

(input/output) /DREQ

(input) CS

(output)

PB2 (input/output)/TP10 (output) /TMO

(output) /CS

(output)

PB1 (input/output)/TP9 (output) /TMIO

(input/output) /DREQ

(input) /CS

(output)

PB0 (input/output)/TP8 (output) /TMO

(output) /CS

(output)

Pin functions in modes 1 to 5

PB7 (input/output)/TP15 (output) /RxD

(input)

PB6 (input/output)/TP14 (output) /TxD

(output)

PB5 (input/output)/TP13 (output) /SCK

(input/output)

PB4 (input/output)/TP12 (output)

PB3 (input/output)/TP11 (output) /TMIO

(input/output) /DREQ

(input)

PB2 (input/output)/TP10 (output) /TMO

(output)

PB1 (input/output)/TP9 (output) /TMIO

(input/output) /DREQ

(input)

PB0 (input/output)/TP8 (output) /TMO

(output)

Pin functions in mode 6 and 7

Figure 8.11 Port B Pin Configuration

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8.12.2 Register Descriptions

Table 8.22 summarizes the registers of port B.

Table 8.22 Port B Registers

Address*Name Abbreviation R/W Initial Value

H'EE00A Port B data direction register PBDDR W H'00

H'FFFDA Port B data register PBDR R/W H'00

Note: * Lower 20 bits of the address in advanced mode.

Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can

select input or output for each pin in port B. When pins are used for TPC output, the

corresponding PBDDR bits must also be set.

Bit

Initial value

Read/Write

PB DDR

Port B data direction 7 to 0

These bits select input or output for port B pins

PB DDR

The pin functions that can be selected for port B differ between modes 1 to 5, and modes 6 and 7.

For the method of selecting the pin functions, see tables 8.23 and 8.24.

When port B functions as an input/output port, a pin in port B becomes an output port if the

corresponding PBDDR bit is set to 1, and an input port if this bit is cleared to 0.

PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.

PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting. Therefore, if a transition is made to software standby mode while

port B is functioning as an input/output port and a PBDDR bit is set to 1, the corresponding pin

maintains its output state.

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Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output

data for pins port B. When port B functions as an output port, the value of this register is output.

When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is

returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin logic level

is read.

Bit

Initial value

Read/Write

R/W

Port B data 7 to 0

These bits store data for port B pins

PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

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Table 8.23 Port B Pin Functions (Modes 1 to 5)

Pin Pin Functions and Selection Method

PB7/TP15/

RxD2

Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB7DDR select the p in function as

follows.

SMIF 0 1

RE 0 1 —

PB7DDR 0 1 1 ——

NDER15 —01——

Pin function PB7 input PB7 output TP15 output RxD2 input RxD2 input

PB6/TP14/

TxD2

Bit TE in SCR of SCI2, bit SMIF in SCMR, bit NDER14 in NDERB, and bit PB6DDR select the pin functio n as

follows.

SMIF 0 1

TE 0 1 —

PB6DDR 0 1 1 ——

NDER14 —01——

Pin function PB6 input PB6 output TP14 output TxD2 output TxD2 output*

Note: *Functions as the TxD2 output pin, but there are two states: one in which the pin is driven, and

another in which the pin is at high-impedance.

PB5/TP13/

SCK2/

LCAS

Bit C/

in SMR of SCI2, bits CKE0 and CKE1 in SCR, bit NDER13 in NDERB, and bit PB5DDR select the pin

function as follow s.

CKE1 0 1

01—

CKE0 0 1 ——

PB5DDR 011———

NDER13 —01———

Pin function PB5 input PB5 output TP13 output SCK2 output SCK2 output SCK2 input

LCAS

output*

Note: *

LCAS

output depending on bits DRAS2 to DRAS0 in DRCRA and bit CSEL in DRCRB, and

regardless of bits C/

, CKE0, and CKE1, NDER13, and PB5DDR. For det ails, see section 6, Bus

Controller.

PB4/TP12/ Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows.

UCAS

PB4DDR 0 1 1

NDER12 —01

Pin function PB4 input PB4 output TP12 output

UCAS

output*

Note: *

UCAS

output depending on bits DRAS2 to DRAS0 in DRCRA and bit CSEL in DRCRB, and

regardless of bits NDER12 and PB4DDR. For details, see section 6, Bus Controller.

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Pin Pin Functions and Selection Method

PB3/TP11/

TMIO3/

DREQ

The DRAM interface settin gs by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR3, bits

CCLR1 and CCLR0 in 8TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB3DDR select the p in

function as follow s.

DRAM interface

settings (1) in table below (2) in table

below

OIS3/2 and OS1/0 All 0 Not all 0 —

CS4E 0 1 ——

PB3DDR 0 1 1 ———

NDER11 —01———

Pin function PB3

input PB3

output TP11

output

output TMIO3

output

output*3

TMIO3 input*1

DREQ

1 input*2

Notes: 1. TMIO3 input w hen CCLR1 = CCLR0 = 1.

2. W hen an external request is specified as a DMAC activation source,

DREQ

1 input regardless

of bits OIS3 and OIS2, OS1 and OS0, CCLR1 and CCLR0, CS4E, NDER11, and PB3DDR.

4 is output as

RAS

DRAM interface

settings (1) (2) (1)

DRAS2 0 1

DRAS1 0101

DRAS0 01010101

PB2/TP10/

TMO2/

The DRAM interface settin gs by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR2, bit

CS5E in CSCR, bit NDER10 in NDERB, and bit PB2DDR select the pin function as follows.

DRAM interface

settings (1) in table below (2) in table

below

OIS3/2 and OS1/0 All 0 Not all 0 —

CS5E 0 1 ——

PB2DDR 0 1 1 ———

NDER10 —01———

Pin function PB2

input PB2

output TP10

output

output TMIO2

output

output*

Note: *

5 is output as

RAS

DRAM interface

settings (1) (2) (1)

DRAS2 0 1

DRAS1 0 1 0 1

DRAS0 01010101

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Pin Pin Functions and Selection Method

PB1/TP9/

TMIO1/

DREQ

Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCL R1 and CCLR0 in TCR1, bit CS6E in CSCR, bit NDER9 in

NDERB, and bit PB1DDR select the pin function as follow s.

OIS3/2 and OS1/0 All 0 Not all 0

CS6E 0 1 —

PB1DDR 0 1 1 ——

NDER9 —01——

Pin function PB1

input PB1

output TP9

output

output TMIO1 output

TMIO1 input*1

DREQ

0 input*2

Notes: 1. TMIO1 input when CCLR1 = CCLR0 = 1.

2. W hen an external request is specified as a DMAC activation source,

DREQ

0 input regardless

of bits OIS3/2 and OS1/0, bits CCLR1/0, bit CS6E, bit NDER9, and bit PB1DDR.

PB0/TP8/

TMO0/

Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit NDER8 in NDERB, and bit PB0DDR select the pin

function as follow s.

OIS3/2 and OS1/0 All 0 Not all 0

CS7E 0 1 —

PB0DDR 0 1 1 ——

NDER8 —01——

Pin function PB0 input PB0 output TP8 output

7 output TMO0 output

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Table 8.24 Port B Pin Functions (Modes 6 and 7)

Pin Pin Functions and Selection Method

PB7/TP15/

RxD2

Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB7DDR select the p in function as

follows.

SMIF 0 1

RE 0 1 —

PB7DDR 0 1 1 ——

NDER15 —01——

Pin function PB7 input PB7 output TP15 output RxD2 input RxD2 input

PB6/TP14/

TxD2

Bit TE in SCR of SCI2, bit SMIF in SCMR, bit NDER14 in NDERB, and bit PB6DDR select the pin function as

follows.

SMIF 0 1

TE 0 1 —

PB6DDR 0 1 1 ——

NDER14 —01——

Pin function PB6 input PB6 output TP14 output TxD2 output TxD2 output*

Note: *Functions as the TxD2 output pin, but there are two states: one in which the pin is driven, and

another in which the pin is at high-impedance.

PB5/TP13/

SCK2

Bit C/

in SMR of SCI2, bits CKE0 and CKE1 in SCR, bit NDER13 in NDERB, and bit PB5DDR select the pin

function as follow s.

CKE1 0 1

01—

CKE0 0 1 ——

PB5DDR 0 1 1 ———

NDER13 —01———

Pin function PB5 input PB5 output TP13 output SCK2 output SCK2 output SCK2 input

PB4/TP12 Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows.

PB4DDR 0 1 1

NDER12 —01

Pin function PB4 input PB4 output TP12 output

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Pin Pin Functions and Selection Method

PB3/TP11/

TMIO3/Bits OIS3/2 and OS1/0 in TCSR3, bits CCLR1 and CCLR0 in TCR3, bit NDER11 in NDERB, and bit PB3DDR

select the pin function as follows.

DREQ

1OIS3/2 and OS1/0 All 0 Not all 0

PB3DDR 0 1 1 —

NDER11 —01—

Pin function PB3 input PB3 output TP11 output TMIO3 output

TMIO3 input*1

DREQ

1 input*2

Notes: 1. TMIO3 input when CCLR1 = CCLR0 = 1.

2. W hen an external request is specified as a DMAC activation source,

DREQ

1 input regardless

of bits OIS3/2 and OS1/0, bit NDER11, and bit PB3DDR.

PB2/TP10/

TMO2

Bits OIS3/2 and OS1/0 in TCSR2, bit NDER10 in NDERB, and bit PB2DDR select the pin f unction as follows.

OIS3/2 and OS1/0 All 0 Not all 0

PB2DDR 0 1 1 —

NDER10 —01—

Pin function PB2 input PB2 output TP10 output TMO2 output

PB1/TP9/

TMIO1/Bits OIS3/2 and OS1/0 in TCSR1, bits CCLR1 and CCLR0 in TCR1, bit NDER9 in NDERB, and bit PB1DDR

select the pin function as follows.

DREQ

0OIS3/2 and OS1/0 All 0 Not all 0

PB1DDR 0 1 1 —

NDER9 —01—

Pin function PB1

input PB1

output TP9

output TMIO1

output

TMIO1 input*1

DREQ

0 input*2

Notes: 1. TMIO1 input when CCLR1 = CCLR0 = 1.

2. W hen an external request is specified as a DMAC activation source,

DREQ

0 input regardless

of bits OIS3/2 and OS1/0, bit NDER9, and bit PB1DDR.

PB0/TP8/ Bits OIS3/2 and OS1/0 in TCSR0, bit NDER8 in NDERB, and bit PB0DDR select the pin function as follows.

TMO0OIS3/2 and OS1/0 All 0 Not all 0

PB0DDR 0 1 1 —

NDER8 —01—

Pin function PB0

input PB0

output TP8

output TMO0

output

Section 9 16-Bit Timer

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Section 9 16-Bit Timer

9.1 Overview

The H8/3068F has built-in 16-bit timer module with three 16-bit counter channels.

9.1.1 Features

16-bit timer features are listed below.

• Capability to process up to 6 pulse outputs or 6 pulse inputs

• Six general registers (GRs, two per channel) with independently-assignable output compare or

input capture functions

• Selection of eight counter clock sources for each channel:

Internal clocks: φ, φ/2, φ/4, φ/8

External clocks: TCLKA, TCLKB, TCLKC, TCLKD

• Five operating modes selectable in all channels:

 Waveform output by compare match

Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)

 Input capture function

Rising edge, falling edge, or both edges (selectable)

 Counter clearing function

Counters can be cleared by compare match or input capture

 Synchronization

Two or more timer counters (16TCNTs) can be preset simultaneously, or cleared

simultaneously by compare match or input capture. Counter synchronization enables

synchronous register input and output.

 PWM mode

PWM output can be provided with an arbitrary duty cycle. With synchronization, up to

three-phase PWM output is possible

• Phase counting mode selectable in channel 2

Two-phase encoder output can be counted automatically.

• High-speed access via internal 16-bit bus

The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus.

• Any initial timer output value can be set

Section 9 16-Bit Timer

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• Nine interrupt sources

Each channel has two compare match/input capture interrupts and an overflow interrupt. All

interrupts can be requested independently.

• Output triggering of programmable timing pattern controller (TPC)

Compare match/input capture signals from channels 0 to 2 can be used as TPC output

triggers.

Table 9.1 summarizes the 16-bit timer functions.

Table 9.1 16-bit timer Functions

Item Channel 0 Channel 1 Channel 2

Clock sources Inte rnal clocks: φ, φ/2, φ/4, φ/8

Externa l clocks: TCLKA, TCLKB, TCLKC, TCLKD, select able independently

General registers (output

compare/input

capture registers)

GRA0, GRB0 GRA1, GRB1 GRA2, GRB2

Input/output pins TIOCA0, TIOCB0TIOCA1, TIOCB1TIOCA2, TIOCB2

Counter clearing function GRA0/GRB0 compare

match or input capture GRA1/GRB1 compare

match or input capture GRA2/GRB2 compare

match or input capture

Initial output value setting function Available Available Available

0Available Available Available

Compare match

output 1Available Available Available

Toggle Available Available Not available

Input capture function Available Available Available

Synchronization Available Available Available

PWM mode Available Available Available

Phase counting mode Not available Not available Available

Interrupt sources Three sources

•Compare match/input

capture A0

•Compare match/input

capture B0

•Overflow

Three sources

•Compare match/input

capture A1

•Compare match/input

capture B1

•Overflow

Three sources

•Compare match/input

capture A2

•Compare match/input

capture B2

•Overflow

Section 9 16-Bit Timer

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9.1.2 Block Diagrams

16-bit timer Block Diagram (Overall): Figure 9.1 is a block diagram of the 16-bit timer.

16-bit timer channel 2

16-bit timer channel 1

16-bit timer channel 0

Module data bus

Bus interface

Internal data bus

IMIA0 to IMIA2

IMIB0 to IMIB2

OVI0 to OVI2

TCLKA to TCLKD

φ, φ/2, φ/4, φ/8 Clock selector

Control logic

TIOCA0 to TIOCA2

TIOCB0 to TIOCB2

TSTR

TSNR

TMDR

TOLR

TISRA

TISRB

TISRC

Legend:

TSTR: Timer start register (8 bits)

TSNR: Timer synchro register (8 bits)

TMDR: Timer mode register (8 bits)

TOLR: Timer output level setting register (8 bits)

TISRA: Timer interrupt status register A (8 bits)

TISRB: Timer interrupt status register B (8 bits)

TISRC: Timer interrupt status register C (8 bits)

Figure 9.1 16-bit timer Block Diagram (Overall)

Section 9 16-Bit Timer

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Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical.

Both have the structure shown in figure 9.2.

Clock selector

Comparator

Control logic

TCLKA to TCLKD

φ, φ/2, φ/4, φ/8

TIOCA

TIOCB

IMIA0

IMIB0

OVI0

16TCNT

GRA

GRB

16TCR

TIOR

Module data bus

Legend:

16TCNT:

GRA, GRB:

TCR:

TIOR:

Timer counter (16 bits)

General registers A and B (input capture/output compare registers) (16 bits 2)

Timer control register (8 bits)

Timer I/O control register (8 bits)

Figure 9.2 Block Diagram of Channels 0 and 1

Section 9 16-Bit Timer

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Block Diagram of Channel 2: Figure 9.3 is a block diagram of channel 2

Clock selector

Comparator

Control logic

TCLKA to TCLKD

φ, φ/2, φ/4, φ/8

TIOCA

TIOCB

IMIA2

IMIB2

OVI2

16TCNT2

GRA2

GRB2

16TCR2

TIOR2

Module data bus

Legend:

16TCNT2:

GRA2, GRB2:

TCR2:

TIOR2:

Timer counter 2 (16 bits)

General registers A2 and B2 (input capture/output compare registers)

(16 bits × 2)

Timer control register 2 (8 bits)

Timer I/O control register 2 (8 bits)

Figure 9.3 Block Diagram of Channel 2

Section 9 16-Bit Timer

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9.1.3 Pin Configuration

Table 9.2 summarizes the 16-bit timer pins.

Table 9.2 16-bit timer Pins

Channel Name Abbre-

viation Input/

Output Function

Common Clock input A TCLKA Input External clock A i nput pin

(phase-A input pin in phase counting

mode)

Clock input B TCLKB Input External clock B input pi n

(phase-B input pin in phase counting

mode)

Clock input C TCLKC Input External clock C input pin

Clock input D TCLKD Input External clock D input pin

0 Input capture/output

compare A0 TIOCA0Input/

output GRA0 output compare or input capture pin

PWM output pin in PWM mode

Input capture/output

compare B0 TIOCB0Input/

output GRB0 output compare or input capture pin

1 Input capture/output

compare A1 TIOCA1Input/

output GRA1 output compare or input capture pin

PWM output pin in PWM mode

Input capture/output

compare B1 TIOCB1Input/

output GRB1 output compare or input capture pin

2 Input capture/output

compare A2 TIOCA2Input/

output GRA2 output compare or input capture pin

PWM output pin in PWM mode

Input capture/output

compare B2 TIOCB2Input/

output GRB2 output compare or input capture pin

Section 9 16-Bit Timer

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9.1.4 Register Configuration

Table 9.3 summarizes the 16-bit timer registers.

Table 9.3 16-bit timer Registers

Channel Address*1Name Abbre-

viation R/W Initial

Value

Common H'FFF60 Timer start register TSTR R/W H'F8

H'FFF61 Timer synchro register TSNC R/W H'F8

H'FFF62 Timer mode register TMDR R/W H'98

H'FFF63 Timer output level setting register TOLR W H'C0

H'FFF64 Timer interrupt status register A TISRA R/(W)*2H'88

H'FFF65 Timer interrupt status register B TISRB R/(W)*2H'88

H'FFF66 Timer interrupt status register C TISRC R/(W)*2H'88

0 H'FFF68 Timer control register 0 16TCR0 R/W H'80

H'FFF69 Timer I/O control register 0 TIOR0 R/W H'88

H'FFF6A Timer counter 0H 16TCNT0H R/W H'00

H'FFF6B Timer counter 0L 16TCNT0L R/W H'00

H'FFF6C General register A0H GRA0H R/W H'FF

H'FFF6D General register A0L GRA0L R/W H'FF

H'FFF6E General register B0H GRB0H R/W H'FF

H'FFF6F General register B0L GRB0L R/W H'FF

1 H'FFF70 Timer control register 1 16TCR1 R/W H'80

H'FFF71 Timer I/O control register 1 TIOR1 R/W H'88

H'FFF72 Timer counter 1H 16TCNT1H R/W H'00

H'FFF73 Timer counter 1L 16TCNT1L R/W H'00

H'FFF74 General register A1H GRA1H R/W H'FF

H'FFF75 General register A1L GRA1L R/W H'FF

H'FFF76 General register B1H GRB1H R/W H'FF

H'FFF77 General register B1L GRB1L R/W H'FF

Section 9 16-Bit Timer

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Channel Address*1Name Abbre-

viation R/W Initial

Value

2 H'FFF78 Timer control register 2 16TCR2 R/W H'80

H'FFF79 Timer I/O control register 2 TIOR2 R/W H'88

H'FFF7A Timer counter 2H 16TCNT2H R/W H'00

H'FFF7B Timer counter 2L 16TCNT2L R/W H'00

H'FFF7C General register A2H GRA2H R/W H'FF

H'FFF7D General register A2L GRA2L R/W H'FF

H'FFF7E General register B2H GRB2H R/W H'FF

H'FFF7F General register B2L GRB2L R/W H'FF

Notes: 1. The lower 20 bits of the address in advanced mode are indicated.

2. Only 0 can be written i n bits 3 to 0, to clear the flags.

9.2 Register Descriptions

9.2.1 Timer Start Register (TSTR)

TSTR is an 8-bit readable/writable register that starts and stops the timer counter (16TCNT) in

channels 0 to 2.

Bit

Initial value

Read/Write

—

STR2

R/W

STR1

R/W

STR0

R/W

Reserved bits Counter start 2 to 0

These bits start and

stop 16TCNT2 to 16TCNT

TSTR is initialized to H'F8 by a reset and in standby mode.

Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.

Section 9 16-Bit Timer

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Bit 2—Counter Start 2 (STR2): Starts and stops timer counter 2 (16TCNT2).

Bit 2

STR2 Description

0 16TCNT2 is halted (Initial value)

1 16TCNT2 is counting

Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (16TCNT1).

Bit 1

STR1 Description

0 16TCNT1 is halted (Initial value)

1 16TCNT1 is counting

Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (16TCNT0).

Bit 0

STR0 Description

0 16TCNT0 is halted (Initial value)

1 16TCNT0 is counting

9.2.2 Timer Synchro Register (TSNC)

TSNC is an 8-bit readable/writable register that selects whether channels 0 to 2 operate

independently or synchronously. Channels are synchronized by setting the corresponding bits to

Bit

Initial value

Read/Write

—

SYNC2

R/W

SYNC1

R/W

SYNC0

R/W

Reserved bits Timer sync 2 to 0

These bits synchronize

channels 2 to 0

TSNC is initialized to H'F8 by a reset and in standby mode.

Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.

Section 9 16-Bit Timer

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Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or

synchronously.

Bit 2

SYNC2 Description

0 Channel 2’s timer counter (16TCNT2) operates independently (Initial value)

16TCNT2 is preset and cleared independently of other channels

1 Channel 2 operates synchronously

16TCNT2 can be synchronously preset and cleared

Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or

synchronously.

Bit 1

SYNC1 Description

0 Channel 1’s timer counter (16TCNT1) operates independently (Initial value)

16TCNT1 is preset and cleared independently of other channels

1 Channel 1 operates synchronously

16TCNT1 can be synchronously preset and cleared

Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or

synchronously.

Bit 0

SYNC0 Description

0 Channel 0’s timer counter (16TCNT0) operates independently (Initial value)

16TCNT0 is preset and cleared independently of other channels

1 Channel 0 operates synchronously

16TCNT0 can be synchronously preset and cleared

Section 9 16-Bit Timer

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9.2.3 Timer Mode Register (TMDR)

TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also

selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.

Bit

Initial value

Read/Write

—

MDF

R/W

FDIR

R/W

—

PWM0

R/W

PWM2

R/W

PWM1

R/W

Reserved bit

Reserved bit PWM mode 2 to 0

These bits select PWM

mode for channels 2 to 0

Phase counting mode flag

Selects phase counting mode for channel 2

Flag direction

Selects the setting condition for the overflow

flag (OVF) in TISRC

TMDR is initialized to H'98 by a reset and in standby mode.

Bit 7—Reserved: This bit cannot be modified and is always read as 1.

Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in

phase counting mode.

Bit 6

MDF Description

0 Channel 2 operates normally (Initial value)

1 Channel 2 operates in phase counting mode

When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter

and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and

falling edges of TCLKA and TCLKB, and counts up or down as follows.

Section 9 16-Bit Timer

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Counting

Direction Down-Counting Up-Counting

TCLKA pin ↑High ↓Low Low ↑High ↓

TCLKB pin Low ↑High ↓↑High ↓Low

In phase counting mode, external clock edge selection by bits CKEG1 and CKEG0 in 16TCR2

and counter clock selection by bits TPSC2 to TPSC0 are invalid, and the above phase counting

mode operations take precedence.

The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the

compare match/input capture settings and interrupt functions of TIOR2, TISRA, TISRB, TISRC

remain effective in phase counting mode.

Bit 5—Flag Direction (FDIR): Designates the setting condition for the OVF flag in TISRC. The

FDIR designation is valid in all modes in channel 2.

Bit 5

FDIR Description

0 OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows (Initial val ue)

1 OVF is set to 1 in TISRC when 16TCNT2 overflows

Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.

Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.

Bit 2

PWM2 Description

0 Channel 2 operates normally (Initial value)

1 Channel 2 operates in PWM mode

When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The

output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2.

Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.

Bit 1

PWM1 Description

0 Channel 1 operates normally (Initial value)

1 Channel 1 operates in PWM mode

Section 9 16-Bit Timer

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When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The

output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1.

Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.

Bit 0

PWM0 Description

0 Channel 0 operates normally (Initial value)

1 Channel 0 operates in PWM mode

When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The

output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0.

9.2.4 Timer Interrupt Status Register A (TISRA)

TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture

and enables or disables GRA compare match and input capture interrupt requests.

—

Bit

Initial value

Read/Write

IMIEA2

R/W

IMIEA1

R/W

IMIEA0

R/W

—

IMFA2

R/(W)*

IMFA1

R/(W)*

IMFA0

R/(W)*

Reserved bit

Input capture/compare match interrupt enable A2 to A0

These bits enable or disable interrupts by the IMFA flags

Input capture/compare match

flags A2 to A0

Status flags indicating GRA

compare match or input capture

Note: * Onl

0 can be written, to clear the fla

TISRA is initialized to H'88 by a reset and in standby mode.

Bit 7—Reserved: This bit cannot be modified and is always read as 1.

Section 9 16-Bit Timer

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Bit 6—Input Capture/Compare Match Interrupt Enable A2 (IMIEA2): Enables or disables

the interrupt requested by the IMFA2 when IMFA2 flag is set to 1.

Bit 6

IMIEA2 Description

0 IMIA2 interrupt requested by IMFA2 flag is disabled (Initial value)

1 IMIA2 interrupt requested by IMFA2 flag is enabled

Bit 5—Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables

the interrupt requested by the IMFA1 flag when IMFA1 is set to 1.

Bit 5

IMIEA1 Description

0 IMIA1 interrupt requested by IMFA1 flag is disabled (Initial value)

1 IMIA1 interrupt requested by IMFA1 flag is enabled

Bit 4—Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables

the interrupt requested by the IMFA0 flag when IMFA0 is set to 1.

Bit 4

IMIEA0 Description

0 IMIA0 interrupt requested by IMFA0 flag is disabled (Initi al value)

1 IMIA0 interrupt requested by IMFA0 flag is enabled

Bit 3—Reserved: This bit cannot be modified and is always read as 1.

Bit 2—Input Capture/Compare Match Flag A2 (IMFA2): This status flag indicates GRA2

compare match or input capture events.

Bit 2

IMFA2 Description

0 [Clearing condition] (Initial value)

Read IMFA2 flag when IMFA2 =1, then write 0 in IMFA2 flag

1 [Setting conditi ons]

• 16TCNT2 = GRA2 when GRA2 functions as an output compare register

• 16TCNT2 value is transferred to GRA2 by an input capture signal when GRA2

functions as an input capture register

Section 9 16-Bit Timer

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Bit 1—Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1

compare match or input capture events.

Bit 1

IMFA1 Description

0 [Clearing condition] (Initial value)

Read IMFA1 flag when IMFA1 =1, then write 0 in IMFA1 flag

1 [Setting conditi ons]

• 16TCNT1 = GRA1 when GRA1 functions as an output compare register

• 16TCNT1 value is transferred to GRA1 by an input capture signal when GRA1

functions as an input capture register

Bit 0—Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0

compare match or input capture events.

Bit 0

IMFA0 Description

0 [Clearing condition] (Initi al value)

Read IMFA0 flag when IMFA0 =1, then write 0 in IMFA0 flag

1 [Setting conditi ons]

• 16TCNT0 = GRA0 when GRA0 functions as an output compare register

• 16TCNT0 value is transferred to GRA0 by an input capture signal when GRA0

functions as an input capture register

Section 9 16-Bit Timer

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9.2.5 Timer Interrupt Status Register B (TISRB)

TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture

and enables or disables GRB compare match and input capture interrupt requests.

—

Bit

Initial value

Read/Write

IMIEB2

R/W

IMIEB1

R/W

IMIEB0

R/W

—

IMFB2

R/(W)*

IMFB1

R/(W)*

IMFB0

R/(W)*

Reserved bit

Input capture/compare match interrupt enable B2 to B0

These bits enable or disable interrupts by the IMFB flags

Input capture/compare match

flags B2 to B0

Status flags indicating GRB

compare match or input capture

Note: * Onl

0 can be written, to clear the fla

TISRB is initialized to H'88 by a reset and in standby mode.

Bit 7—Reserved: This bit cannot be modified and is always read as 1.

Bit 6—Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables

the interrupt requested by the IMFB2 when IMFB2 flag is set to 1.

Bit 6

IMIEB2 Description

0 IMIB2 interrupt requested by IMFB2 flag is disabled (Initial value)

1 IMIB2 interrupt requested by IMFB2 flag is enabled

Section 9 16-Bit Timer

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Bit 5—Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables

the interrupt requested by the IMFB1 when IMFB1 flag is set to 1.

Bit 5

IMIEB1 Description

0 IMIB1 interrupt requested by IMFB1 flag is disabled (Initial value)

1 IMIB1 interrupt requested by IMFB1 flag is enabled

Bit 4—Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables

the interrupt requested by the IMFB0 when IMFB0 flag is set to 1.

Bit 4

IMIEB0 Description

0 IMIB0 interrupt requested by IMFB0 flag is disabled (Initi al value)

1 IMIB0 interrupt requested by IMFB0 flag is enabled

Bit 3—Reserved: This bit cannot be modified and is always read as 1.

Bit 2—Input Capture/Compare Match Flag B2 (IMFB2): This status flag indicates GRB2

compare match or input capture events.

Bit 2

IMFB2 Description

0 [Clearing condition] (Initi al value)

Read IMFB2 flag when IMFB2 =1, then write 0 in IMFB2 flag

1 [Setting conditi ons]

• 16TCNT2 = GRB2 when GRB2 functions as an output compare register

• 16TCNT2 value is transferred to GRB2 by an input capture signal when GRB2

functions as an input capture register

Section 9 16-Bit Timer

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Bit 1—Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1

compare match or input capture events.

Bit 1

IMFB1 Description

0 [Clearing condition] (Initi al value)

Read IMFB1 flag when IMFB1 =1, then write 0 in IMFB1 flag

1 [Setting conditi ons]

• 16TCNT1 = GRB1 when GRB1 functions as an output compare register

• 16TCNT1 value is transferred to GRB1 by an input capture signal when GRB1

functions as an input capture register

Bit 0—Input Capture/Compare Match Flag B0 (IMFB0): This status flag indicates GRB0

compare match or input capture events.

Bit 0

IMFB0 Description

0 [Clearing condition] (Initi al value)

Read IMFB0 flag when IMFB0 =1, then write 0 in IMFB0 flag

1 [Setting conditi ons]

• 16TCNT0 = GRB0 when GRB0 functions as an output compare register

• 16TCNT0 value is transferred to GRB0 by an input capture signal when GRB0

functions as an input capture register

Section 9 16-Bit Timer

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9.2.6 Timer Interrupt Status Register C (TISRC)

TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and

enables or disables overflow interrupt requests.

—

Bit

Initial value

Read/Write

OVIE2

R/W

OVIE1

R/W

OVIE0

R/W

—

OVF2

R/(W)*

OVF1

R/(W)*

OVF0

R/(W)*

Reserved bit

Overflow interrupt enable 2 to 0

These bits enable or disable interrupts by the OVF flags

Overflow flags 2 to 0

Status flags indicating

interrupts by OVF flags

Note: * Only 0 can be written, to clear the flag.

TISRC is initialized to H'88 by a reset and in standby mode.

Bit 7—Reserved: This bit cannot be modified and is always read as 1.

Bit 6—Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by

the OVF2 when OVF2 flag is set to 1.

Bit 6

OVIE2 Description

0 OVI2 i nterrupt requested by OVF2 flag is disabled (Initial value)

1 OVI2 interrupt requested by OVF2 flag is enabl ed

Bit 5—Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by

the OVF1 when OVF1 flag is set to 1.

Bit 5

OVIE1 Description

0 OVI1 i nterrupt requested by OVF1 flag is disabled (Initial value)

1 OVI1 interrupt requested by OVF1 flag is enabl ed

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Bit 4—Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by

the OVF0 when OVF0 flag is set to 1.

Bit 4

OVIE0 Description

0 OVI0 i nterrupt requested by OVF0 flag is disabled (Initial value)

1 OVI0 interrupt requested by OVF0 flag is enabl ed

Bit 3—Reserved: This bit cannot be modified and is always read as 1.

Bit 2—Overflow Flag 2 (OVF2): This status flag indicates 16TCNT2 overflow.

Bit 2

OVF2 Description

0 [Clearing condition] (Initi al value)

Read OVF2 flag when OVF2 =1, then write 0 in OVF2 flag

1 [Setting conditi on]

16TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF

Note: 16TCNT underflow occurs when 16TCNT operates as an up/down-counter. Underflow

occurs only when channel 2 operates in phase counting mode (MDF = 1 in TMDR).

Bit 1—Overflow Flag 1 (OVF1): This status flag indicates 16TCNT1 overflow.

Bit 1

OVF1 Description

0 [Clearing condition] (Initi al value)

Read OVF1 flag when OVF1 =1, then write 0 in OVF1 flag

1 [Setting conditi on]

16TCNT1 overflowed from H'FFFF to H'0000

Bit 0—Overflow Flag 0 (OVF0): This status flag indicates 16TCNT0 overflow.

Bit 0

OVF0 Description

0 [Clearing condition] (Initial value)

Read OVF0 flag when OVF0 =1, then write 0 in OVF0 flag

1 [Setting conditi on]

16TCNT0 overflowed from H'FFFF to H'0000

Section 9 16-Bit Timer

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9.2.7 Timer Counters (16TCNT)

16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel.

Channel Abbreviation Function

0 16TCNT0 Up-counter

1 16TCNT1

2 16TCNT2 Phase counting mode: up/down-counter

Other modes: up-counter

Bit

Initial value

Read/Write

R/W

Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source.

The clock source is selected by bits TPSC2 to TPSC0 in 16TCR.

16TCNT0 and 16TCNT1 are up-counters. 16TCNT2 is an up/down-counter in phase counting

mode and an up-counter in other modes.

16TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to

GRA or GRB (counter clearing function).

When 16TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TISRC of

the corresponding channel.

When 16TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TISRC

of the corresponding channel.

The 16TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either

word access or byte access.

Each 16TCNT is initialized to H'0000 by a reset and in standby mode.

Section 9 16-Bit Timer

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9.2.8 General Registers (GRA, GRB)

The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each

channel.

Channel Abbreviation Function

0 GRA0, GRB0 Output compare/input capture register

1 GRA1, GRB1

2 GRA2, GRB2

Bit

Initial value

Read/Write

R/W

A general register is a 16-bit readable/writable register that can function as either an output

compare register or an input capture register. The function is selected by settings in TIOR.

When a general register is used as an output compare register, its value is constantly compared

with the 16TCNT value. When the two values match (compare match), the IMFA or IMFB flag is

set to 1 in TISRA/TISRB. Compare match output can be selected in TIOR.

When a general register is used as an input capture register, an external input capture signal are

detected and the current 16TCNT value is stored in the general register. The corresponding IMFA

or IMFB flag in TISRA/TISRB is set to 1 at the same time. The edges of the input capture signal

are selected in TIOR.

TIOR settings are ignored in PWM mode.

General registers are linked to the CPU by an internal 16-bit bus and can be written or read by

either word access or byte access.

General registers are set as output compare registers (with no pin output) and initialized to

H'FFFF by a reset and in standby mode.

Section 9 16-Bit Timer

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9.2.9 Timer Control Registers (16TCR)

16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel.

Channel Abbreviation Function

16TCR0

16TCR1

16TCR2

16TCR controls the timer counter. The 16TCRs in all

channels are functi onally identical. When phase counting

mode is selected in channel 2, the settings of bits CKEG1

and CKEG0 and TPSC2 to TPSC0 in 16TCR2 are ignored.

Bit

Initial value

Read/Write

—

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Timer prescaler 2 to 0

These bits select the timer

counter clock

Reserved bit

Clock edge 1/0

These bits select external clock edges

Counter clear 1/0

These bits select the counter clear source

Each 16TCR is an 8-bit readable/writable register that selects the timer counter clock source,

selects the edge or edges of external clock sources, and selects how the counter is cleared.

16TCR is initialized to H'80 by a reset and in standby mode.

Bit 7—Reserved: This bit cannot be modified and is always read as 1.

Section 9 16-Bit Timer

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Bits 6 and 5—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is

cleared.

Bit 6

CCLR1 Bit 5

CCLR0 Description

0 0 16TCNT is not cleared (Initi al value)

1 16TCNT is cleared by GRA compare match or input capture*1

1 0 16TCNT is cleared by GRB compare match or input capture*1

1 Synchronous clear: 16TCNT is cleared in synchronization with other

synchronized timers*2

Notes: 1. 16TCNT is cleared by compare match when the general register functions as an output

compare register, and by input capture when the general register functions as an input

capture register.

2. Selected in TSNC.

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input

edges when an external clock source is used.

Bit 4

CKEG1 Bit 3

CKEG0 Description

0 0 Count ri sing edges (Initi al value)

1 Count falling edges

1 — Count both edges

When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in 16TCR2 are ignored.

Phase counting takes precedence.

Section 9 16-Bit Timer

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Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock

source.

Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Function

000Internal clock: φ(Initial value)

1 Internal clock: φ/2

1 0 Internal clock: φ/4

1 Internal clock: φ/8

100External clock A: TCLKA input

1 External clock B: TCLKB input

1 0 External clock C: TCLKC input

1 External clock D: TCLKD input

When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only

falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer

counts the edges selected by bits CKEG1 and CKEG0.

When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2

to TPSC0 in 16TCR2 are ignored. Phase counting takes precedence.

Section 9 16-Bit Timer

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9.2.10 Timer I/O Control Register (TIOR)

TIOR is an 8-bit register. The 16-bit timer has three TIORs, one in each channel.

Channel Abbreviation Function

0 TIOR0 TIOR controls the general registers. Some functions differ in PWM

1 TIOR1 mode.

2 TIOR2

Bit

Initial value

Read/Write

—

IOB2

R/W

IOB1

R/W

IOB0

R/W

—

IOA0

R/W

IOA2

R/W

IOA1

R/W

I/O control A2 to A0

These bits select GRA

functions

Reserved bit

I/O control B2 to B0

These bits select GRB functions

Reserved bit

Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture

function for GRA and GRB, and specifies the functions of the TIORA and TIORB pins. If the

output compare function is selected, TIOR also selects the type of output. If input capture is

selected, TIOR also selects the edges of the input capture signal.

TIOR is initialized to H'88 by a reset and in standby mode.

Bit 7—Reserved: This bit cannot be modified and is always read as 1.

Section 9 16-Bit Timer

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Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.

Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Function

000GRB is an outputNo output at compare match(Initial value)

1compare register 0 output at GRB compare match*1

1 0 1 output at GRB compare match*1

1 Output toggles at GRB compare match

(1 output in channel 2)*1 *2

100GRB is an input GRB captures rising edge of input

1compare register GRB captures falling edge of input

1 0 GRB captures both edges of input

Notes: 1. After a reset, the output conforms to the TOLR setti ng until the first compare match.

2. Channel 2 output cannot be toggled by compare match. When this setting is made, 1

output is sele cted automatically.

Bit 3—Reserved: This bit cannot be modified and is always read as 1.

Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.

Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Function

000GRA is an outputNo output at compare match(Initial value)

1compare register 0 output at GRA compare match*1

1 0 1 output at GRA compare match*1

1 Output toggles at GRA compare match

(1 output in channel 2)*1 *2

100GRA is an input GRA captures rising edge of input

1compare register GRA captures falling edge of input

1 0 GRA captures both edges of input

Notes: 1. After a reset, the output conforms to the TOLR setti ng until the first compare match.

2. Channel 2 output cannot be toggled by compare match. When this setting is made, 1

output is sele cted automatically.

Section 9 16-Bit Timer

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9.2.11 Timer Output Level Setting Register C (TOLR)

TOLR is an 8-bit write-only register that selects the timer output level for channels 0 to 2.

—

Bit

Initial value

Read/Write

—

TOB2

TOA2

TOB1

TOA1

TOB0

TOA0

Reserved bits

Output level setting A2 to A0, B2 to B0

These bits set the levels of the timer outputs

(TIOCA

to TIOCA

, and TIOCB

to TIOCB

)

A TOLR setting can only be made when the corresponding bit in TSTR is 0.

TOLR is a write-only register, and cannot be read. If it is read, all bits will return a value of 1.

TOLR is initialized to H'C0 by a reset and in standby mode.

Bits 7 and 6—Reserved: These bits cannot be modified.

Bit 5—Output Level Setting B2 (TOB2): Sets the value of timer output TIOCB2.

Bit 5

TOB2 Description

0 TIOCB2 is 0 (Initial value)

1 TIOCB2 is 1

Bit 4—Output Level Setting A2 (TOA2): Sets the value of timer output TIOCA2.

Bit 4

TOA2 Description

0 TIOCA2 is 0 (Initi al value)

1 TIOCA2 is 1

Section 9 16-Bit Timer

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Bit 3—Output Level Setting B1 (TOB1): Sets the value of timer output TIOCB1.

Bit 3

TOB1 Description

0 TIOCB1 is 0 (Initial value)

1 TIOCB1 is 1

Bit 2—Output Level Setting A1 (TOA1): Sets the value of timer output TIOCA1.

Bit 2

TOA1 Description

0 TIOCA1 is 0 (Initi al value)

1 TIOCA1 is 1

Bit 1—Output Level Setting B0 (TOB0): Sets the value of timer output TIOCB0.

Bit 0

TOB0 Description

0 TIOCB0 is 0 (Initi al value)

1 TIOCB0 is 1

Bit 0—Output Level Setting A0 (TOA0): Sets the value of timer output TIOCA0.

Bit 0

TOA0 Description

0 TIOCA0 is 0 (Initi al value)

1 TIOCA0 is 1

Section 9 16-Bit Timer

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9.3 CPU Interface

9.3.1 16-Bit Accessible Registers

The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers,

and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a

word at a time, or a byte at a time.

Figures 9.4 and 9.5 show examples of word read/write access to a timer counter (16TCNT).

Figures 9.6 to 9.9 show examples of byte read/write access to 16TCNTH and 16TCNTL.

On-chip data bus

CPU

L Bus interface

LModule

data bus

16TCNTH 16TCNTL

Figure 9.4 16TCNT Access Operation [CPU →

→→

→ 16TCNT (Word)]

On-chip data bus

CPU

L Bus interface

LModule

data bus

16TCNTH 16TCNTL

Figure 9.5 Access to Timer Counter (CPU Reads 16TCNT, Word)

Section 9 16-Bit Timer

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On-chip data bus

CPU

L Bus interface

LModule

data bus

16TCNTH 16TCNTL

Figure 9.6 Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte)

On-chip data bus

CPU

L Bus interface

LModule

data bus

16TCNTH 16TCNTL

Figure 9.7 Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte)

On-chip data bus

CPU

L Bus interface

LModule

data bus

16TCNTH 16TCNTL

Figure 9.8 Access to Timer Counter H (CPU Reads 16TCNTH, Upper Byte)

Section 9 16-Bit Timer

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On-chip data bus

CPU

L Bus interface

LModule

data bus

16TCNTH 16TCNTL

Figure 9.9 Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte)

9.3.2 8-Bit Accessible Registers

The registers other than the timer counters and general registers are 8-bit registers. These

registers are linked to the CPU by an internal 8-bit data bus.

Figures 9.10 and 9.11 show examples of byte read and write access to a 16TCR.

If a word-size data transfer instruction is executed, two byte transfers are performed.

On-chip data bus

CPU

L Bus interface

LModule

data bus

16TCR

Figure 9.10 16TCR Access (CPU Writes to 16TCR)

Section 9 16-Bit Timer

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On-chip data bus

CPU

L Bus interface

LModule

data bus

16TCR

Figure 9.11 16TCR Access (CPU Reads 16TCR)

9.4 Operation

9.4.1 Overview

A summary of operations in the various modes is given below.

Normal Operation: Each channel has a timer counter and general registers. The timer counter

counts up, and can operate as a free-running counter, periodic counter, or external event counter.

GRA and GRB can be used for input capture or output compare.

Synchronous Operation: The timer counters in designated channels are preset synchronously.

Data written to the timer counter in any one of these channels is simultaneously written to the

timer counters in the other channels as well. The timer counters can also be cleared

synchronously if so designated by the CCLR1 and CCLR0 bits in the TCRs.

PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare

match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending

on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB

automatically become output compare registers.

Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and

TCLKB is detected and 16TCNT2 counts up or down accordingly. When phase counting mode is

selected TCLKA and TCLKB become clock input pins and 16TCNT2 operates as an up/down-

counter.

Section 9 16-Bit Timer

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9.4.2 Basic Functions

Counter Operation: When one of bits STR0 to STR2 is set to 1 in the timer start register

(TSTR), the timer counter (16TCNT) in the corresponding channel starts counting. The counting

can be free-running or periodic.

• Sample setup procedure for counter

Figure 9.12 shows a sample procedure for setting up a counter.

Counter setup

Select counter clock

Count operation

Periodic counting

Select counter clear source

Select output compare

Set period

Start counter

Free-running counting

Start counter

Periodic counter Free-runnin

counter

Yes

Figure 9.12 Counter Setup Procedure (Example)

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1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock

source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the

external clock signal.

2. For periodic counting, set CCLR1 and CCLR0 in 16TCR to have 16TCNT cleared at GRA

compare match or GRB compare match.

3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in

step 2.

4. Write the count period in GRA or GRB, whichever was selected in step 2.

5. Set the STR bit to 1 in TSTR to start the timer counter.

• Free-running and periodic counter operation

A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running

counters. A free-running counter starts counting up when the corresponding bit in TSTR is set

to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC.

After the overflow, the counter continues counting up from H'0000. Figure 9.13 illustrates

free-running counting.

16TCNT value

H'FFFF

H'0000

STR0 to

STR2 bit

OVF

Time

Figure 9.13 Free-Running Counter Operation

When a channel is set to have its counter cleared by compare match, in that channel 16TCNT

operates as a periodic counter. Select the output compare function of GRA or GRB, set bit

CCLR1 or CCLR0 in 16TCR to have the counter cleared by compare match, and set the count

period in GRA or GRB. After these settings, the counter starts counting up as a periodic

counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or

GRB, the IMFA or IMFB flag is set to 1 in TISRA/TISRB and the counter is cleared to

H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TISRA/TISRB, a CPU

interrupt is requested at this time. After the compare match, 16TCNT continues counting up

from H'0000. Figure 9.14 illustrates periodic counting.

Section 9 16-Bit Timer

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16TCNT value

H'0000

STR bit

IMF

Time

Counter cleared by general

Figure 9.14 Periodic Counter Operation

• 16TCNT count timing

 Internal clock source

Bits TPSC2 to TPSC0 in 16TCR select the system clock (φ) or one of three internal clock

sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).

Figure 9.15 shows the timing.

Internal

clock

16TCNT input

clock

16TCNT N – 1 N N + 1

Figure 9.15 Count Timing for Internal Clock Sources

 External clock source

The external clock pin (TCLKA to TCLKD) can be selected by bits TPSC2 to TPSC0 in

16TCR, and the detected edge by bits CKEG1 and CKEG0. The rising edge, falling edge,

or both edges can be selected.

The pulse width of the external clock signal must be at least 1.5 system clocks when a

single edge is selected, and at least 2.5 system clocks when both edges are selected.

Shorter pulses will not be counted correctly.

Figure 9.16 shows the timing when both edges are detected.

Section 9 16-Bit Timer

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External

clock input

16TCNT input

clock

16TCNT N – 1 N N + 1

Figure 9.16 Count Timing for External Clock Sources (when Both Edges are Detected)

Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B

can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the

output can only go to 0 or go to 1.

• Sample setup procedure for waveform output by compare match

Figure 9.17 shows an example of the setup procedure for waveform output by compare match.

Output setup

Select waveform

output mode

Set output timing

Start counter

Waveform output

Select the compare match output mode (0, 1, or

toggle) in TIOR. When a waveform output mode

is selected, the pin switches from its generic input/

output function to the output compare function

(TIOCA or TIOCB). An output compare pin outputs

the value set in TOLR until the first compare match

occurs.

Set a value in GRA or GRB to designate the

compare match timing.

Set the STR bit to 1 in TSTR to start the timer

counter.

Figure 9.17 Setup Procedure for Waveform Output by Compare Match (Example)

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• Examples of waveform output

Figure 9.18 shows examples of 0 and 1 output. 16TCNT operates as a free-running counter, 0

output is selected for compare match A, and 1 output is selected for compare match B. When

the pin is already at the selected output level, the pin level does not change.

Time

H'FFFF

GRB

TIOCB

TIOCA

GRA

No change

1 output

0 output

16TCNT value

H'0000

Figure 9.18 0 and 1 Output (TOA = 1, TOB = 0)

Figure 9.19 shows examples of toggle output. 16TCNT operates as a periodic counter, cleared

by compare match B. Toggle output is selected for both compare match A and B.

GRB

TIOCB

TIOCA

GRA

16TCNT value

Time

Counter cleared by compare match with GRB

Toggle

output

Toggle

output

H'0000

Figure 9.19 Toggle Output (TOA = 1, TOB = 0)

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• Output compare output timing

The compare match signal is generated in the last state in which 16TCNT and the general

compare match signal is generated, the output value selected in TIOR is output at the output

compare pin (TIOCA or TIOCB). When 16TCNT matches a general register, the compare

match signal is not generated until the next counter clock pulse.

Figure 9.20 shows the output compare timing.

N + 1N

16TCNT input

clock

16TCNT

Compare

match signal

TIOCA,

TIOCB

Figure 9.20 Output Compare Output Timing

Input Capture Function: The 16TCNT value can be transferred to a general register when an

input edge is detected at an input capture input/output compare pin (TIOCA or TIOCB). Rising-

edge, falling-edge, or both-edge detection can be selected. The input capture function can be used

to measure pulse width or period.

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• Sample setup procedure for input capture

Figure 9.21 shows a sample procedure for setting up input capture.

Input selection

Select input-capture input

Start counter

Input capture

Set TIOR to select the input capture function of a

general register and the rising edge, falling edge,

or both edges of the input capture signal. Clear the

DDR bit to 0 before making these TIOR settings.

Set the STR bit to 1 in TSTR to start the timer

counter.

Figure 9.21 Setup Procedure for Input Capture (Example)

• Examples of input capture

Figure 9.22 illustrates input capture when the falling edge of TIOCB and both edges of

TIOCA are selected as capture edges. 16TCNT is cleared by input capture into GRB.

H'0005

H'0180

H'0160

H'0005

H'0000

TIOCB

TIOCA

GRA

GRB

16TCNT value

H'0160

Figure 9.22 Input Capture (Example)

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• Input capture signal timing

Input capture on the rising edge, falling edge, or both edges can be selected by settings in

TIOR. Figure 9.23 shows the timing when the rising edge is selected. The pulse width of the

input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system

clocks for capture of both edges.

Input-capture input

Input capture signal

16TCNT

GRA, GRB

Figure 9.23 Input Capture Signal Timing

9.4.3 Synchronization

The synchronization function enables two or more timer counters to be synchronized by writing

the same data to them simultaneously (synchronous preset). With appropriate 16TCR settings,

two or more timer counters can also be cleared simultaneously (synchronous clear).

Synchronization enables additional general registers to be associated with a single time base.

Synchronization can be selected for all channels (0 to 2).

Sample Setup Procedure for Synchronization: Figure 9.24 shows a sample procedure for

setting up synchronization.

Section 9 16-Bit Timer

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Setup for synchronization

Synchronous preset

Set the SYNC bits to 1 in TSNC for the channels to be synchronized.

When a value is written in 16TCNT in one of the synchronized channels, the same value is

simultaneously written in 16TCNT in the other channels.

Set the CCLR1 or CCLR0 bit in 16TCR to have the counter cleared by compare match or input capture.

Set the CCLR1 and CCLR0 bits in 16TCR to have the counter cleared synchronously.

Set the STR bits in TSTR to 1 to start the s

nchronized counters.

Select synchronization

Synchronous preset

Write to 16TCNT

Synchronous clear

Clearing

synchronized to this

channel?

Select counter clear source

Start counter

Counter clear Synchronous clear

Start counter

Select counter clear source

Yes

Figure 9.24 Setup Procedure for Synchronization (Example)

Example of Synchronization: Figure 9.25 shows an example of synchronization. Channels 0, 1,

and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter

clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter

clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are

synchronously cleared by compare match with GRB0. A three-phase PWM waveform is output

from pins TIOCA0, TIOCA1, and TIOCA2. For further information on PWM mode, see section

9.4.4, PWM Mode.

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TIOCA

GRA2

GRA1

GRB2

GRA0

GRB1

GRB0

Value of 16TCNT0

to 16TCNT2 Cleared by compare match with GRB0

H'0000

Figure 9.25 Synchronization (Example)

9.4.4 PWM Mode

In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.

GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which

the PWM output changes to 0. If either GRA or GRB compare match is selected as the counter

clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin.

PWM mode can be selected in all channels (0 to 2).

Table 9.4 summarizes the PWM output pins and corresponding registers. If the same value is set

in GRA and GRB, the output does not change when compare match occurs.

Section 9 16-Bit Timer

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Table 9.4 PWM Output Pins and Registers

Channel Output Pin 1 Output 0 Output

0 TIOCA0GRA0 GRB0

1 TIOCA1GRA1 GRB1

2 TIOCA2GRA2 GRB2

Sample Setup Procedure for PWM Mode: Figure 9.26 shows a sample procedure for setting up

PWM mode.

PWM mode 1.

Set bits TPSC2 to TPSC0 in 16TCR to

select the counter clock source. If an

external clock source is selected, set

bits CKEG1 and CKEG0 in 16TCR to

select the desired edge(s) of the

external clock signal.

Set bits CCLR1 and CCLR0 in 16TCR

to select the counter clear source.

Set the time at which the PWM

waveform should go to 1 in GRA.

Set the time at which the PWM

waveform should go to 0 in GRB.

Set the PWM bit in TMDR to select

PWM mode. When PWM mode is

selected, regardless of the TIOR

contents, GRA and GRB become

output compare registers specifying

the times at which the PWM output

goes to 1 and 0. The TIOCA pin

automatically becomes the PWM

output pin. The TIOCB pin conforms

to the settings of bits IOB1 and IOB0

in TIOR. If TIOCB output is not

desired, clear both IOB1 and IOB0 to 0.

Set the STR bit to 1 in TSTR to start

the timer counter.

PWM mode

Select counter clock 1

Select counter clear source 2

Set GRA 3

Set GRB 4

Select PWM mode 5

Start counter 6

Figure 9.26 Setup Procedure for PWM Mode (Example)

Section 9 16-Bit Timer

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Examples of PWM Mode: Figure 9.27 shows examples of operation in PWM mode. In PWM

mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0

at compare match with GRB.

In the examples shown, 16TCNT is cleared by compare match with GRA or GRB. Synchronized

operation and free-running counting are also possible.

16TCNT value Counter cleared by compare match A

Time

GRA

GRB

TIOCA

a. Counter cleared by GRA (TOA = 1)

16TCNT value Counter cleared by compare match B

Time

GRB

GRA

TIOCA

b. Counter cleared by GRB (TOA = 0)

H'0000

Figure 9.27 PWM Mode (Example 1)

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Figure 9.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%.

If the counter is cleared by compare match with GRB, and GRA is set to a higher value than

GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set

to a higher value than GRA, the duty cycle is 100%.

16TCNT value Counter cleared by compare match B

Time

GRB

GRA

TIOCA

a. 0% duty cycle (TOA=0)

16TCNT value Counter cleared by compare match A

Time

GRA

GRB

TIOCA

b. 100% duty cycle (TOA=1)

Write to GRA Write to GRA

Write to GRB Write to GRB

H'0000

Figure 9.28 PWM Mode (Example 2)

Section 9 16-Bit Timer

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9.4.5 Phase Counting Mode

In phase counting mode the phase difference between two external clock inputs (at the TCLKA

and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly.

In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock

input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2

to TPSC0, CKEG1, and CKEG0 in 16TCR2. Settings of bits CCLR1, CCLR0 in 16TCR2, and

settings in TIOR2, TISRA, TISRB, TISRC, setting of STR2 bit in TSTR, GRA2, and GRB2 are

valid. The input capture and output compare functions can be used, and interrupts can be

generated.

Phase counting is available only in channel 2.

Sample Setup Procedure for Phase Counting Mode: Figure 9.29 shows a sample procedure for

setting up phase counting mode.

Phase counting mode

Select phase counting mode

Select flag setting condition

Start counter

Phase counting mode

Set the MDF bit in TMDR to 1 to select

phase counting mode.

Select the flag setting condition with

the FDIR bit in TMDR.

Set the STR2 bit to 1 in TSTR to start

the timer counter.

Figure 9.29 Setup Procedure for Phase Counting Mode (Example)

Section 9 16-Bit Timer

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Example of Phase Counting Mode: Figure 9.30 shows an example of operations in phase

counting mode. Table 9.5 lists the up-counting and down-counting conditions for 16TCNT2.

In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted.

The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap

must also be at least 1.5 states, and the pulse width must be at least 2.5 states.

16TCNT2 value

Counting up Counting down

TCLKB

TCLKA

Figure 9.30 Operation in Phase Counting Mode (Example)

Table 9.5 Up/Down Counting Conditions

Counting

Direction Up-Counting Down-Counting

TCLKB pin ↑High ↓Low HIgh ↓Low ↑

TCLKA pin Low ↑High ↓↓Low ↑HIgh

TCLKA

TCLKB

Phase

difference Phase

difference Pulse width Pulse width

Overlap Overlap

Phase difference and overlap:

Pulse width: at least 1.5 state

at least 2.5 state

Figure 9.31 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

Section 9 16-Bit Timer

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9.4.6 16-Bit Timer Output Timing

The initial value of 16-bit timer output when a timer count operation begins can be specified

arbitrarily by making a setting in TOLR.

Figure 9.32 shows the timing for setting the initial value with TOLR.

Only write to TOLR when the corresponding bit in TSTR is cleared to 0.

TOLR address

T2T3

Address bus

TOLR

16-bit timer output pin

Figure 9.32 Timing for Setting 16-Bit Timer Output Level by Writing to TOLR

Section 9 16-Bit Timer

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9.5 Interrupts

The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and

overflow interrupts.

9.5.1 Setting of Status Flags

Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a

compare match signal generated when 16TCNT matches a general register (GR). The compare

match signal is generated in the last state in which the values match (when 16TCNT is updated

from the matching count to the next count). Therefore, when 16TCNT matches a general register,

the compare match signal is not generated until the next 16TCNT clock input. Figure 9.33 shows

the timing of the setting of IMFA and IMFB.

16TCNT

IMF

IMI

16TCNT input

clock

Compare

match signal

N N + 1

Figure 9.33 Timing of Setting of IMFA and IMFB by Compare Match

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Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an

input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding

general register. Figure 9.34 shows the timing.

Input capture

signal

IMF

16TCNT

IMI

Figure 9.34 Timing of Setting of IMFA and IMFB by Input Capture

Section 9 16-Bit Timer

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Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from

H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 9.35 shows the timing.

Overflow

signal

16TCNT

OVF

OVI

Figure 9.35 Timing of Setting of OVF

9.5.2 Timing of Clearing of Status Flags

If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is

cleared. Figure 9.36 shows the timing.

Address

IMF, OVF

TISR write cycle

TISR address

Figure 9.36 Timing of Clearing of Status Flags

Section 9 16-Bit Timer

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9.5.3 Interrupt Sources

Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare

match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt

sources of three kinds, all independently vectored. An interrupt is requested when the interrupt

request flag are set to 1.

The priority order of the channels can be modified in interrupt priority registers A (IPRA). For

details see section 5, Interrupt Controller.

Table 9.6 lists the interrupt sources.

Table 9.6 16-bit timer Interrupt Sources

Channel Interrupt

Source Description Priority*

0 IMIA0

IMIB0

OVI0

Compare match/input capture A0

Compare match/input capture B0

Overflow 0

High

1 IMIA1

IMIB1

OVI1

Compare match/input capture A1

Compare match/input capture B1

Overflow 1

2 IMIA2

IMIB2

OVI2

Compare match/input capture A2

Compare match/input capture B2

Overflow 2 Low

Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed

by settings in IPRA.

Section 9 16-Bit Timer

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9.6 Usage Notes

This section describes contention and other matters requiring special attention during 16-bit timer

operations.

Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T3 state

of a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed.

See

figure 9.37.

Address bus

Internal write signal

Counter clear signal

16TCNT

16TCNT write cycle

16TCNT address

N H'0000

Figure 9.37 Contention between 16TCNT Write and Clear

Section 9 16-Bit Timer

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Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the

T3 state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented.

Figure 9.38 shows the timing in this case.

Address bus

Internal write signal

16TCNT input clock

16TCNT N

16TCNT address

16TCNT write data

16TCNT word write cycle

T1T2T3

Figure 9.38 Contention between 16TCNT Word Write and Increment

Section 9 16-Bit Timer

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Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the

T2 or T3 state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not

incremented. The byte data for which a write was not performed is not incremented, and retains

its pre-write value. See figure 9.39, which shows an increment pulse occurring in the T2 state of a

byte write to 16TCNTH.

Address bus

Internal write signal

16TCNT input clock

16TCNTH

16TCNTL

16TCNTH byte write cycle

16TCNTH address

16TCNT write data

XXX + 1

Figure 9.39 Contention between 16TCNT Byte Write and Increment

Section 9 16-Bit Timer

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Contention between General Register Write and Compare Match: If a compare match occurs

in the T3 state of a general register write cycle, writing takes priority and the compare match

signal is inhibited. See figure 9.40.

Address bus

Internal write signal

16TCNT

Compare match signal

General register write cycle

GR address

N N + 1

General register write data

Inhibited

Figure 9.40 Contention between General Register Write and Compare Match

Section 9 16-Bit Timer

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Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the

T3 state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF

is set to 1.The same holds for underflow. See figure 9.41.

Address bus

Internal write signal

16TCNT input clock

Overflow signal

16TCNT

OVF

H'FFFF

16TCNT address

16TCNT write data

16TCNT write cycle

Figure 9.41 Contention between 16TCNT Write and Overflow

Section 9 16-Bit Timer

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Contention between General Register Read and Input Capture: If an input capture signal

occurs during the T3 state of a general register read cycle, the value before input capture is read.

See figure 9.42.

Address bus

Internal read signal

Input capture signal

Internal data bus

GR address

General register read cycle

Figure 9.42 Contention between General Register Read and Input Capture

Section 9 16-Bit Timer

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Contention between Counter Clearing by Input Capture and Counter Increment: If an input

capture signal and counter increment signal occur simultaneously, the counter is cleared

according to the input capture signal. The counter is not incremented by the increment signal.

The value before the counter is cleared is transferred to the general register. See figure 9.43.

Input capture signal

Counter clear signal

16TCNT input clock

16TCNT

GR N

N H'0000

Figure 9.43 Contention between Counter Clearing by Input Capture and Counter

Increment

Section 9 16-Bit Timer

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Contention between General Register Write and Input Capture: If an input capture signal

occurs in the T3 state of a general register write cycle, input capture takes priority and the write to

the general register is not performed. See figure 9.44.

Address bus

Internal write signal

Input capture signal

16TCNT

GR M

GR address

General register write cycle

Figure 9.44 Contention between General Register Write and Input Capture

Section 9 16-Bit Timer

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Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is

cleared in the last state at which the 16TCNT value matches the general register value, at the time

when this value would normally be updated to the next count. The actual counter frequency is

therefore given by the following formula:

f = φ

(N+1)

(f: counter frequency. φ: system clock frequency. N: value set in general register.)

Note on Writes in Synchronized Operation: When channels are synchronized, if a 16TCNT

value is modified by byte write access, all 16 bits of all synchronized counters assume the same

value as the counter that was addressed.

(Example) When channels 1 and 2 are synchronized

• Byte write to channel 1 or byte write to channel 2

16TCNT1

16TCNT2

16TCNT1

16TCNT2

16TCNT1

16TCNT2

16TCNT1

16TCNT2

16TCNT1

16TCNT2

• Word write to channel 1 or word write to channel 2

Upper byte Lower byte

Upper b

te Lower b

Upper byte Lower byte

Upper b

te Lower b

Upper byte Lower byte

Write A to upper byte

of channel 1

Write A to lower byte

of channel 2

Write AB word to

channel 1 or 2

Section 9 16-Bit Timer

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16-bit timer Operating Modes

Table 9.7 (a) 16-bit timer Operating Modes (Channel 0)

TSNC TMDR TIOR0 16TCR0

Synchro- Clear Clock

Operating Mode nization MDF FDIR PWM IOA IOB Select Select

Synchronous preset SYNC0 = 1 ——

PWM mode ——PWM0 = 1 — *

Output compare A ——PWM0 = 0 IOA2 = 0

Other bits

unrestricted

Output compare B — —IOB2 = 0

Other bits

unrestricted

Input capture A ——PWM0 = 0 IOA2 = 1

Other bits

unrestricted

Input capture B ——PWM0 = 0 IOB2 = 1

Other bits

unrestricted

Counter By compare —— CCLR1 = 0

clearing match/input CCLR0 = 1

capture A

By compare —— CCLR1 = 1

match/input CCLR0 = 0

capture B

Syn- SYNC0 = 1 —— CCLR1 = 1

chronous CCLR0 = 1

clear

Legend: Setting available (valid). — Setting does not affect this mode.

Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur

simultaneously, the compare match signal is inhibited.

Section 9 16-Bit Timer

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Table 9.7 (b) 16-bit timer Operating Modes (Channel 1)

TSNC TMDR TIOR1 16TCR1

Synchro- Clear Clock

Operating Mode nization MDF FDIR PWM IOA IOB Select Select

Synchronous preset SYNC1 = 1 ——

PWM mode ——PWM1 = 1 —

Output compare A ——PWM1 = 0 IOA2 = 0

Other bits

unrestricted

Output compare B —— IOB2 = 0

Other bits

unrestricted

Input capture A ——PWM1 = 0 IOA2 = 1

Other bits

unrestricted

Input capture B ——PWM1 = 0 IOB2 = 1

Other bits

unrestricted

Counter By compare —— CCLR1 = 0

clearing match/input CCLR0 = 1

capture A

By compare —— CCLR1 = 1

match/input CCLR0 = 0

capture B

Syn- SYNC1 = 1 —— CCLR1 = 1

chronous CCLR0 = 1

clear

Legend: Setting available (valid). — Setting does not affect this mode.

Note: *The input capture function cannot be used in PWM mode. If compare match A and compare match B

occur simultaneousl

, the compare match si

nal is inhibited.

Section 9 16-Bit Timer

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Table 9.7 (c) 16-bit timer Operating Modes (Channel 2)

TSNC TMDR TIOR2 16TCR2

Synchro- Clear Clock

Operating Mode nization MDF FDIR PWM IOA IOB Select Select

Synchronous preset SYNC2 = 1 —

PWM mode —PWM2 = 1 —*

Output compare A —PWM2 = 0 IOA2 = 0

Other bits

unrestricted

Output compare B —IOB2 = 0

Other bits

unrestricted

Input capture A —PWM2 = 0 IOA2 = 1

Other bits

unrestricted

Input capture B —PWM2 = 0 IOB2 = 1

Other bits

unrestricted

Counter By compare —CCLR1 = 0

clearing match/input CCLR0 = 1

capture A

By compare —CCLR1 = 1

match/input CCLR0 = 0

capture B

Syn- SYNC2 = 1 —CCLR1 = 1

chronous CCLR0 = 1

clear

Phase counting MDF = 1 —

mode

Legend: Setting available (valid). — Setting does not affect this mode.

Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur

simultaneousl

, the compare match si

nal is inhibited.

Section 9 16-Bit Timer

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Section 10 8-Bit Timers

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Section 10 8-Bit Timers

10.1 Overview

The H8/3068F has a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2, and

TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two 8-bit

time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT

value to detect compare match events. The timers can be used as multifunctional timers in a

variety of applications, including the generation of a rectangular-wave output with an arbitrary

duty cycle.

10.1.1 Features

The features of the 8-bit timer module are listed below.

• Selection of four clock sources

The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an

external clock input (enabling use as an external event counter).

• Selection of three ways to clear the counters

The counters can be cleared on compare match A or B, or input capture B.

• Timer output controlled by two compare match signals

The timer output signal in each channel is controlled by two independent compare match

signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM

output.

• A/D converter can be activated by a compare match

• Two channels can be cascaded

 Channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit

count mode).

 Channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit

count mode).

 Channel 1 can count channel 0 compare match events (compare match count mode).

 Channel 3 can count channel 2 compare match events (compare match count mode).

• Input capture function can be set

8-bit or 16-bit input capture operation is available.

Section 10 8-Bit Timers

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• Twelve interrupt sources

There are twelve interrupt sources: four compare match sources, four compare match/input

capture sources, four overflow sources.

Two of the compare match sources and two of the combined compare match/input capture

sources each have an independent interrupt vector. The remaining compare match interrupts,

combined compare match/input capture interrupts, and overflow interrupts have one interrupt

vector for two sources.

Section 10 8-Bit Timers

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10.1.2 Block Diagram

The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0

and 1, and group 1 comprising channels 2 and 3. Figure 10.1 shows a block diagram of 8-bit

timer group 0.

φ/8

φ/64

φ/8192

CMIA0

CMIB0

CMIA1/CMIB1

OVI0/OVI1

Interrupt signals

TMO

TMIO

TCORA0

TCORB0

8TCSR0

8TCR0

TCORA1

8TCNT1

TCORB1

8TCSR1

8TCR1

TCLKA

TCLKC

8TCNT0

Legend:

TCORA: Time constant register A

TCORB: Time constant register B

8TCNT: Timer counter

8TCSR: Timer control/status register

8TCR: Timer control register

External clock

sources Internal clock

sources

Clock select

Control logic

Clock 1

Clock 0

Compare match A1

Compare match A0

Overflow 1

Overflow 0

Compare match B1

Compare match B0

Input capture B1

Comparator A0 Comparator A1

Comparator B0 Comparator B1

Internal bus

Figure 10.1 Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0)

Section 10 8-Bit Timers

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10.1.3 Pin Configuration

Table 10.1 summarizes the input/output pins of the 8-bit timer module.

Table 10.1 8-Bit Timer Pins

Group Channel Name Abbreviation I/O Function

0 0 Timer output TMO0Output Compare match output

Timer clock input TCLKC Input Counter external clock i nput

1 Timer input/output TMIO1I/O Compare match output/input

capture input

Timer clock input TCLKA Input Counter external clock input

1 2 Timer output TMO2Output Compare match output

Timer clock input TCLKD Input Counter external clock i nput

3 Timer input/output TMIO3I/O Compare match output/input

capture input

Timer clock input TCLKB Input Counter external clock input

Section 10 8-Bit Timers

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10.1.4 Register Configuration

Table 10.2 summarizes the registers of the 8-bit timer module.

Table 10.2 8-Bit Timer Registers

Channel Address*1Name Abbreviation R/W Initial value

0 H'FFF80 Timer control register 0 8TCR0 R/W H'00

H'FFF82 Timer control/status register 0 8TCSR0 R/(W)*2H'00

H'FFF84 Time constant register A0 TCORA0 R/W H'FF

H'FFF86 Time constant register B0 TCORB0 R/W H'FF

H'FFF88 Timer counter 0 8TCNT0 R/W H'00

1 H'FFF81 Timer control register 1 8TCR1 R/W H'00

H'FFF83 Timer control/status register 1 8TCSR1 R/(W)*2H'00

H'FFF85 Time constant register A1 TCORA1 R/W H'FF

H'FFF87 Time constant register B1 TCORB1 R/W H'FF

H'FFF89 Timer counter 1 8TCNT1 R/W H'00

2 H'FFF90 Timer control register 2 8TCR2 R/W H'00

H'FFF92 Timer control/status register 2 8TCSR2 R/(W)*2H'10

H'FFF94 Time constant register A2 TCORA2 R/W H'FF

H'FFF96 Time constant register B2 TCORB2 R/W H'FF

H'FFF98 Timer counter 2 8TCNT2 R/W H'00

3 H'FFF91 Timer control register 3 8TCR3 R/W H'00

H'FFF93 Timer control/status register 3 8TCSR3 R/(W)*2H'00

H'FFF95 Time constant register A3 TCORA3 R/W H'FF

H'FFF97 Time constant register B3 TCORB3 R/W H'FF

H'FFF99 Timer counter 3 8TCNT3 R/W H'00

Notes: 1. Indicates the lower 20 bits of the address in advanced mode.

2. Only 0 can be written to bi ts 7 to 5, to clear these flags.

Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the channel 0

together by word access.

Similarly, each pair of registers for channel 2 and channel 3 comprises a 16-bit register with the

channel 2 register as the upper 8 bits and the channel 3 register as the lower 8 bits, so they can be

accessed together by word access.

Section 10 8-Bit Timers

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10.2 Register Descriptions

10.2.1 Timer Counters (8TCNT)

R/W

Bit

Initial value

Read/Write

R/W

Bit

Initial value

Read/Write

R/W

8TCNT0 8TCNT1

R/W

8TCNT2 8TCNT3

The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses

generated from an internal or external clock source. The clock source is selected by clock select

bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR). The CPU can always read or

write to the timer counters.

The 8TCNT0 and 8TCNT1 pair, and the 8TCNT2 and 8TCNT3 pair, can each be accessed as a

16-bit register by word access.

8TCNT can be cleared by an input capture signal or compare match signal. Counter clear bits 1

and 0 (CCLR1 and CCLR0) in 8TCR select the method of clearing.

When 8TCNT overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status

Each 8TCNT is initialized to H'00 by a reset and in standby mode.

Section 10 8-Bit Timers

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10.2.2 Time Constant Registers A (TCORA)

TCORA0 to TCORA3 are 8-bit readable/writable registers.

R/W

TCORA0 TCORA1

R/W

TCORA2 TCORA3

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a

16-bit register by word access.

The TCORA value is constantly compared with the 8TCNT value. When a match is detected, the

corresponding compare match flag A (CMFA) is set to 1 in 8TCSR.

The timer output can be freely controlled by these compare match signals and the settings of

output select bits 1 and 0 (OS1, OS0) in 8TCSR.

Each TCORA register is initialized to H'FF by a reset and in standby mode.

Section 10 8-Bit Timers

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10.2.3 Time Constant Registers B (TCORB)

R/W

TCORB0 TCORB1

R/W

TCORB2 TCORB3

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and

the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access.

The TCORB value is constantly compared with the 8TCNT value. When a match is detected, the

corresponding compare match flag B (CMFB) is set to 1 in 8TCSR*.

The timer output can be freely controlled by these compare match signals and the settings of

output/input capture edge select bits 3 and 2 (OIS3, OIS2) in 8TCSR.

When TCORB is used for input capture, it stores the 8TCNT value on detection of an external

input capture signal. At this time, the CMFB flag is set to 1 in the corresponding 8TCSR register.

The detected edge of the input capture signal is set in 8TCSR.

Each TCORB register is initialized to H'FF by a reset and in standby mode.

Note: * When channel 1 and channel 3 are designated for TCORB input capture, the CMFB flag

is not set by a channel 0 or channel 2 compare match B.

Section 10 8-Bit Timers

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10.2.4 Timer Control Register (8TCR)

CMIEB

R/W

CMIEA

R/W

OVIE

R/W

CCLR1

R/W

CCLR0

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT

clearing specification, and enables interrupt requests.

8TCR is initialized to H'00 by a reset and in standby mode.

For the timing, see section 10.4, Operation.

Bit 7—Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt

request when the CMFB flag is set to 1 in 8TCSR.

Bit 7

CMIEB Description

0 CMIB interrupt requested by CMFB is disabled (Initial value)

1 CMIB interrupt requested by CMFB is enabled

Bit 6—Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA

interrupt request when the CMFA flag is set to 1 in 8TCSR.

Bit 6

CMIEA Description

0 CMIA interrupt requested by CMFA is disabled (Initial value)

1 CMIA interrupt requested by CMFA is enabled

Bit 5—Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt

request when the OVF flag is set to 1 in 8TCSR.

Bit 5

OVIE Description

0 OVI interrupt requested by OVF is disabled (Initial val ue)

1 OVI interrupt requested by OVF is enabl ed

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Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits specify the 8TCNT

clearing source. Compare match A or B, or input capture B, can be selected as the clearing

source.

Bit 4

CCLR1 Bit 3

CCLR0 Description

0 0 Clearing is di sabled (Initi al value)

1 Cleared by compare match A

1 0 Cleared by compare match B/input capture B

1 Cleared by input capture B

Note: When input capture B is set as the 8TCNT1 and 8TCNT3 counter clear source, 8TCNT0

and 8TCNT2 are not cleared by compare match B.

Bits 2 to 0—Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to

8TCNT is an internal or external clock.

Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and

φ/8192. The rising edge of the selected internal clock triggers the count.

When use of an external clock is selected, three types of count can be selected: at the rising edge,

the falling edge, and both rising and falling edges.

When CKS2, CKS1, CKS0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded.

The incrementing clock source is different when 8TCR0 and 8TCR2 are set, and when 8TCR1

and 8TCR3 are set.

Section 10 8-Bit Timers

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Bit 2

CSK2 Bit 1

CSK1 Bit 0

CSK0 Description

0 0 0 Clock i nput disabled (Initial value)

1 Internal clock, counted on falling edge of φ/8

1 0 Internal clock, counted on falling edge of φ/64

1 Internal clock, counted on falling edge of φ/8192

1 0 0 Channel 0 (16-bit count mode): Count on 8TCNT1 overflow

signal*1

Channel 1 (compare match count mode): Count on 8TCNT0

compare match A*1

Channel 2 (16-bit count mode): Count on 8TCNT3 overflow

signal*2

Channel 3 (compare match count mode): Count on 8TCNT2

compare match A*2

1 External clock, counted on rising edge

1 0 External clock, counted on falling edge

1 External clock, counted on both rising and falling edges

Notes: 1. If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is

the 8TCNT0 compare match signal, no incrementing clock is generated. Do not use

this setti ng.

2. If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is

the 8TCNT2 compare match signal, no incrementing clock is generated. Do not use

this setti ng.

Section 10 8-Bit Timers

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10.2.5 Timer Control/Status Registers (8TCSR)

CMFB

R/(W)*

CMFA

R/(W)*

OVF

R/(W)*

—

OIS3

R/W

OS0

R/W

OIS2

R/W

OS1

R/W

8TCSR2

CMFB

R/(W)*

CMFA

R/(W)*

OVF

R/(W)*

R/W

OIS3

R/W

OS0

R/W

OIS2

R/W

OS1

R/W

8TCSR0

ADTE

Bit

Initial value

Read/Write

Bit

Initial value

Read/Write

CMFB

R/(W)*

CMFA

R/(W)*

OVF

R/(W)*

ICE

R/W

OIS3

R/W

OS0

R/W

OIS2

R/W

OS1

R/W

8TCSR1, 8TCSR3

Note: * Only 0 can be written to bits 7 to 5, to clear these flags.

Bit

Initial value

Read/Write

The timer control/status registers 8TCSR are 8-bit registers that indicate compare match/input

capture and overflow statuses, and control compare match output/input capture edge selection.

8TCSR2 is initialized to H'10, and 8TCSR0, 8TCSR1, and 8TCSR3 to H'00, by a reset and in

standby mode.

Section 10 8-Bit Timers

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Bit 7—Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the

occurrence of a TCORB compare match or input capture.

Bit 7

CMFB Description

0 [Clearing condition] (Initial value)

Read CMFB when CMFB = 1, then write 0 in CMFB

1 [Setting conditions]

• 8TCNT = TCORB*

• The 8TCNT value is transferred to TCORB by an input capture signal

when TCORB functions as an input capture register

Note: *When bit ICE is set to 1 in 8TCSR1 and 8TCSR3, the CMFB flag is not set when 8TCNT0

= TCORB0 or 8TCNT2 = TCORB2.

Bit 6—Compare Match Flag A (CMFA): Status flag that indicates the occurrence of a TCORA

compare match.

Bit 6

CMFA Description

0 [Clearing condition] (Initial value)

Read CMFA when CMFA = 1, then write 0 in CMFA

1 [Setting condition]

8TCNT = TCORA

Bit 5—Timer Overflow Flag (OVF): Status flag that indicates that the 8TCNT has overflowed

from H'FF to H'00.

Bit 5

OVF Description

0 [Clearing condition] (Initial value)

Read OVF when OVF = 1, then write 0 in OVF

1 [Setting condition]

8TCNT overflows from H'FF to H'00

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Bit 4—A/D Trigger Enable (ADTE) (In 8TCSR0): In combination with TRGE in the A/D

control register (ADCR), enables or disables A/D converter start requests by compare match A or

an external trigger.

TRGE*Bit 4

ADTE Description

0 0 A/D converter start requests by compare match A or external trigger pin

(

ADTRG

) input are di sabled (Initi al value)

1 A/D converter start requests by compare match A or external trigger pin

(

ADTRG

) input are di sabled

1 0 A/D converter start requests by external trigger pin (

ADTRG

) input are

enabled, and A/D converter start requests by compare match A are disabled

1 A/D converter start requests by compare match A are enabled, and A/D

converter start requests by external trigger pin (

ADTRG

) input are di sabled

Note: *TRGE is bit 7 of the A/D control reg ister (ADCR).

Bit 4—Reserved (In 8TCSR1): This bit is a reserved bit, but can be read and written.

Bit 4—Input Capture Enable (ICE) (In 8TCSR1 and 8TCSR3): Selects the function of

TCORB1 and TCORB3.

Bit 4

ICE Description

0 TCORB1 and TCORB3 are compare match registers (Initial value)

1 TCORB1 and TCORB3 are input capture registers

When bit ICE is set to 1 in 8TCSR1 or 8TCSR3, the operation of the TCORA and TCORB

registers in channels 0 to 3 is as shown in the tables below.

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Table 10.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register

Function Status Flag Change Timer Output

Capture Input Interrupt Request

TCORA0 Compare match

operation CMFA changed from 0

to 1 in 8TCSR0 by

compare match

TMO0 output

controllable CMIA0 interrupt request

generated by compare

match

TCORB0 Compare match

operation CMFB not changed

from 0 to 1 in 8TCSR0

by compare match

No output from

TMO0

CMIB0 interrupt request

not generated by compare

match

TCORA1 Compare match

operation CMFA changed from 0

to 1 in 8TCSR1 by

compare match

TMIO1 is

dedicated i nput

capture pin

CMIA1 interrupt request

generated by compare

match

TCORB1 Input capture

operation CMFB changed from 0

to 1 in 8TCSR1 by

input capture

TMIO1 is

dedicated i nput

capture pin

CMIB1 interrupt request

generated by input

capture

Table 10.4 Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register

Function Status Flag Change Timer Output

Capture Input Interrupt Request

TCORA2 Compare match

operation CMFA changed from 0

to 1 in 8TCSR2 by

compare match

TMO2 output

controllable CMIA2 interrupt request

generated by compare

match

TCORB2 Compare match

operation CMFB not changed

from 0 to 1 in 8TCSR2

by compare match

No output from

TMO2

CMIB2 interrupt request

not generated by compare

match

TCORA3 Compare match

operation CMFA changed from 0

to 1 in 8TCSR3 by

compare match

TMIO3 is

dedicated i nput

capture pin

CMIA3 interrupt request

generated by compare

match

TCORB3 Input capture

operation CMFB changed from 0

to 1 in 8TCSR3 by

input capture

TMIO3 is

dedicated i nput

capture pin

CMIB3 interrupt request

generated by input

capture

Section 10 8-Bit Timers

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Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination

with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the

input capture input detected edge.

The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3).

ICE Bit in

8TCSR1

(8TCSR3) Bit 3

OIS3 Bit 2

OIS2 Description

0 0 0 No change when compare match B occurs (Initial value)

1 0 is output when compare match B occurs

1 0 1 is output when compare match B occurs

1 Output is inverted when compare match B occurs (toggle output)

1 0 0 TCORB input capture on rising edge

1 TCORB input capture on falling edge

1 0 TCORB input capture on both rising and falling edges

• When the compare match register function is used, the timer output priority order is: toggle

output > 1 output > 0 output.

• If compare match A and B occur simultaneously, the output changes in accordance with the

higher-priority compare match.

• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.

Bits 1 and 0—Output Select A1 and A0 (OS1, OS0): These bits select the compare match A

output level.

Bit 1

OS1 Bit 0

OS0 Description

0 0 No change when compare match A occurs (Initial value)

1 0 i s output when compare match A occurs

1 0 1 is output when compare match A occurs

1 Output is inverted when compare match A occurs (toggle output)

• When the compare match register function is used, the timer output priority order is: toggle

output > 1 output > 0 output.

• If compare match A and B occur simultaneously, the output changes in accordance with the

higher-priority compare match.

• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.

Section 10 8-Bit Timers

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10.3 CPU Interface

10.3.1 8-Bit Registers

8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected

to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at

a time.

Figures 10.2 and 10.3 show the operation in word read and write accesses to 8TCNT.

Figures 10.4 to 10.7 show the operation in byte read and write accesses to 8TCNT0 and 8TCNT1.

8TCNT0 8TCNT1

Internal data bus

Bus

interface Module data bus

Figure 10.2 8TCNT Access Operation (CPU Writes to 8TCNT, Word)

8TCNT0 8TCNT1

Internal data bus

Bus

interface Module data bus

Figure 10.3 8TCNT Access Operation (CPU Reads 8TCNT, Word)

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8TCNTH0 8TCNTL1

Internal data bus

Bus

interface Module data bus

Figure 10.4 8TCNT0 Access Operation (CPU Writes to 8TCNT0, Upper Byte)

8TCNTH0 8TCNTL1

Internal data bus

Bus

interface Module data bus

Figure 10.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte)

8TCNT0 8TCNT1

Internal data bus

Bus

interface Module data bus

Figure 10.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte)

8TCNT0 8TCNT1

Internal data bus

Bus

interface Module data bus

Figure 10.7 8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte)

Section 10 8-Bit Timers

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10.4 Operation

10.4.1 8TCNT Count Timing

8TCNT is incremented by input clock pulses (either internal or external).

Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the

system clock (φ) can be selected, by setting bits CKS2 to CKS0 in 8TCR. Figure 10.8 shows the

count timing.

8TCNT N–1 N N+1

Internal clock

8TCNT input clock

Note: Even if the same internal clock is selected for the 16-bit timer and the 8-bit timer, the same operation

will not be performed since the incrementing edge is different in each case.

Figure 10.8 Count Timing for Internal Clock Input

External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in

8TCR: on the rising edge, the falling edge, and both rising and falling edges.

The pulse width of the external clock signal must be at least 1.5 system clocks when a single

edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will

not be counted correctly.

Figure 10.9 shows the timing for incrementation on both edges of the external clock signal.

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8TCNT N–1NN+1

External clock input

8TCNT input clock

Figure 10.9 Count Timing for External Clock Input (Both-Edge Detection)

10.4.2 Compare Match Timing

Timer Output Timing: When compare match A or B occurs, the timer output is as specified by

the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output).

Figure 10.10 shows the timing when the output is set to toggle on compare match A.

Compare match A

signal

Timer output

Figure 10.10 Timing of Timer Output

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Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,

8TCNT can be cleared when compare match A or B occurs, Figure 10.11 shows the timing of

this operation.

N H'008TCNT

Compare match signal

Figure 10.11 Timing of Clear by Compare Match

Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,

8TCNT can be cleared when input capture B occurs. Figure 10.12 shows the timing of this

operation.

Input capture signal

Input capture input

8TCNT NH

'00

Figure 10.12 Timing of Clear by Input Capture

10.4.3 Input Capture Signal Timing

Input capture on the rising edge, falling edge, or both edges can be selected by settings in 8TCSR.

Figure 10.13 shows the timing when the rising edge is selected.

The pulse width of the input capture input signal must be at least 1.5 system clocks when a single

edge is selected, and at least 2.5 system clocks when both edges are selected.

Section 10 8-Bit Timers

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Input capture signal

Input capture input

8TCNT N

TCORB N

Figure 10.13 Timing of Input Capture Input Signal

10.4.4 Timing of Status Flag Setting

Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: The CMFA and CMFB

flags in 8TCSR are set to 1 by the compare match signal output when the TCORA or TCORB and

8TCNT values match. The compare match signal is generated in the last state of the match (when

the matched 8TCNT count value is updated). Therefore, after the 8TCNT and TCORA or

TCORB values match, the compare match signal is not generated until an incrementing clock

pulse signal is generated. Figure 10.14 shows the timing in this case.

CMF

Compare match signal

8TCNT N N+1

TCOR

Figure 10.14 CMF Flag Setting Timing when Compare Match Occurs

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Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture

signal, the CMFB flag is set to 1 and at the same time the 8TCNT value is transferred to TCORB.

Figure 10.15 shows the timing in this case.

CMFB

Input capture signal

8TCNT

TCORB

Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs

Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow

signal generated when 8TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in

this case.

OVF

Overflow signal

8TCNT H'FF H'00

Figure 10.16 Timing of OVF Setting

10.4.5 Operation with Cascaded Connection

If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0

and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer

(16-bit timer mode), or channel 0 8-bit timer compare matches can be counted in channel 1

(compare match count mode). Similarly, if bits CKS2 to CKS0 are set to (100) in either 8TCR2

Section 10 8-Bit Timers

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or 8TCR3, the 8-bit timers of channels 2 and 3 are cascaded. With this configuration, the two

timers can be used as a single 16-bit timer (16-bit timer mode),or channel 2 8-bit timer compare

matches can be counted in channel 3 (compare match count mode). In this case, the timer

operates as below.

16-Bit Count Mode

• Channels 0 and 1:

When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit

timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.

 Setting when Compare Match Occurs

• The CMFA or CMFB flag is set to 1 in 8TCSR0 when a 16-bit compare match occurs.

• The CMFA or CMFB flag is set to 1 in 8TCSR1 when a lower 8-bit compare match

occurs.

• TMO0 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in accordance

with the 16-bit compare match conditions.

• TMIO1 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in

accordance with the lower 8-bit compare match conditions.

 Setting when Input Capture Occurs

• The CMFB flag is set to 1 in 8TCSR0 and 8TCSR1 when the ICE bit is 1 in TCSR1 and

input capture occurs.

• TMIO1 pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in

8TCSR0.

 Counter Clear Specification

• If counter clear on compare match or input capture has been selected by the CCLR1 and

CCLR0 bits in 8TCR0, the 16-bit counter (both 8TCNT0 and 8TCNT1) is cleared.

• The settings of the CCLR1 and CCLR0 bits in 8TCR1 are ignored. The lower 8 bits

cannot be cleared independently.

 OVF Flag Operation

• The OVF flag is set to 1 in 8TCSR0 when the 16-bit counter (8TCNT0 and 8TCNT1)

overflows (from H'FFFF to H'0000).

• The OVF flag is set to 1 in 8TCSR1 when the 8-bit counter (8TCNT1) overflows (from

H'FF to H'00).

Section 10 8-Bit Timers

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• Channels 2 and 3:

When bits CKS2 to CKS0 are set to (100) in 8TCR2, the timer functions as a single 16-bit

timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits.

 Setting when Compare Match Occurs

• The CMFA or CMFB flag is set to 1 in 8TCSR2 when a 16-bit compare match occurs.

• The CMFA or CMFB flag is set to 1 in 8TCSR3 when a lower 8-bit compare match

occurs.

• TMO2 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR2 is in accordance

with the 16-bit compare match conditions.

• TMIO3 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR3 is in

accordance with the lower 8-bit compare match conditions.

 Setting when Input Capture Occurs

• The CMFB flag is set to 1 in 8TCSR2 and 8TCSR3 when the ICE bit is 1 in TCSR3 and

input capture occurs.

• TMIO3 pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in

8TCSR2.

 Counter Clear Specification

• If counter clear on compare match has been selected by the CCLR1 and CCLR0 bits in

8TCR2, the 16-bit counter (both 8TCNT2 and 8TCNT3) is cleared.

• The settings of the CCLR1 and CCLR0 bits in 8TCR3 are ignored. The lower 8 bits

cannot be cleared independently.

 OVF Flag Operation

• The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3)

overflows (from H'FFFF to H'0000).

• The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from

H'FF to H'00).

Compare Match Count Mode

• Channels 0 and 1:

When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare

match A events.

CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in

accordance with the settings for each channel.

Note: When bit ICE = 1 in 8TCSR1, the compare match register function of TCORB0 in

channel 0 cannot be used.

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• Channels 2 and 3:

When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare

match A events.

CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in

accordance with the settings for each channel.

Note: When bit ICE = 1 in 8TCSR3, the compare match register function of TCORB2 in

channel 2 cannot be used.

Caution

Do not set 16-bit counter mode and compare match count mode simultaneously within the same

group, as the 8TCNT input clock will not be generated and the counters will not operate.

10.4.6 Input Capture Setting

The 8TCNT value can be transferred to TCORB on detection of an input edge on the input

capture/output compare pin (TMIO1 or TMIO3). Rising edge, falling edge, or both edge detection

can be selected. In 16-bit count mode, 16-bit input capture can be used.

Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation)

• Channel 1:

 Set TCORB1 as an 8-bit input capture register with the ICE bit in 8TCSR1.

 Select rising edge, falling edge, or both edges as the input edge(s) for the input capture

signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR1.

 Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count.

• Channel 3:

 Set TCORB3 as an 8-bit input capture register with the ICE bit in 8TCSR3.

 Select rising edge, falling edge, or both edges as the input edge(s) for the input capture

signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR3.

 Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count.

Note: When TCORB1 in channel 1 is used for input capture, TCORB0 in channel 0 cannot be

used as a compare match register.

Similarly, when TCORB3 in channel 3 is used for input capture, TCORB2 in channel 2

cannot be used as a compare match register.

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Setting Input Capture Operation in 16-Bit Count Mode

• Channels 0 and 1:

 In 16-bit count mode, TCORB0 and TCORB1 function as a 16-bit input capture register

when the ICE bit is set to 1 in 8TCSR1.

 Select rising edge, falling edge, or both edges as the input edge(s) for the input capture

signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR0. (In 16-bit count mode, the settings

of bits OIS3 and OIS2 in 8TCSR1 are ignored.)

 Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count.

• Channels 2 and 3:

 In 16-bit count mode, TCORB2 and TCORB3 function as a 16-bit input capture register

when the ICE bit is set to 1 in 8TCSR3.

 Select rising edge, falling edge, or both edges as the input edge(s) for the input capture

signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR2. (In 16-bit count mode, the settings

of bits OIS3 and OIS2 in 8TCSR3 are ignored.)

 Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count.

Section 10 8-Bit Timers

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10.5 Interrupt

10.5.1 Interrupt Sources

The 8-bit timer unit can generate three types of interrupt: compare match A and B (CMIA and

CMIB) and overflow (TOVI). Table 10.5 shows the interrupt sources and their priority order.

Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8TCR. A

separate interrupt request signal is sent to the interrupt controller by each interrupt source.

Table 10.5 Types of 8-Bit Timer Interrupt Sources and Priority Order

PriorityInterrupt Source Description

HighCMIA Interrupt by CMFA

CMIB Interrupt by CMFB

TOVI Interrupt by OVF Low

For compare match interrupts CMIA1/CMIB1 and CMIA3/CMIB3 and the overflow interrupts

(TOVI0/TOVI1 and TOVI2/TOVI3), one vector is shared by two interrupts.

Table 10.6 lists the interrupt sources.

Table 10.6 8-Bit Timer Interrupt Sources

Channel Interrupt Source Description

0 CMIA0 TCORA0 compare match

CMIB0 TCORB0 compare match/input capture

1 CMIA1/CMIB1 TCORA1 compare match, or TCORB1 compare match/input

capture

0, 1 TOVI0/TOVI1 Counter 0 or counter 1 overflow

2 CMIA2 TCORA2 compare match

CMIB2 TCORB2 compare match/input capture

3 CMIA3/CMIB3 TCORA3 compare match, or TCORB3 compare match/input

capture

2, 3 TOVI2/TOVI3 Counter 2 or counter 3 overflow

Section 10 8-Bit Timers

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10.5.2 A/D Converter Activation

The A/D converter can only be activated by channel 0 compare match A.

If the ADTE bit setting is 1 when the CMFA flag in 8TCSR0 is set to 1 by generation of channel

0 compare match A, an A/D conversion start request will be issued to the A/D converter. If the

TRGE bit in ADCR is 1 at this time, the A/D converter will be started. If the ADTE bit in

8TCSR0 is 1, A/D converter external trigger pin (

ADTRG

) input is disabled.

10.6 8-Bit Timer Application Example

Figure 10.17 shows how the 8-bit timer module can be used to output pulses with any desired

duty cycle. The settings for this example are as follows:

• Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1 in 8TCR so that 8TCNT is cleared by a

TCORA compare match.

• Set bits OIS3, OIS2, OS1, and OS0 to (0110) in 8TCSR so that 1 is output on a TCORA

compare match and 0 is output on a TCORB compare match.

The above settings enable a waveform with the cycle determined by TCORA and the pulse width

detected by TCORB to be output without software intervention.

8TCNT

H'FF Counter clear

TCORA

TCORB

H'00

TMO

Figure 10.17 Example of Pulse Output

Section 10 8-Bit Timers

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10.7 Usage Notes

Note that the following kinds of contention can occur in 8-bit timer operation.

10.7.1 Contention between 8TCNT Write and Clear

If a timer counter clear signal occurs in the T3 state of a 8TCNT write cycle, clearing of the

counter takes priority and the write is not performed. Figure 10.18 shows the timing in this case.

Address bus 8TCNT address

Internal write signal

Counter clear signal

8TCNT N H'00

8TCNT write cycle

Figure 10.18 Contention between 8TCNT Write and Clear

Section 10 8-Bit Timers

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10.7.2 Contention between 8TCNT Write and Increment

If an increment pulse occurs in the T3 state of a 8TCNT write cycle, writing takes priority and

8TCNT is not incremented. Figure 10.19 shows the timing in this case.

Address bus 8 TCNT address

Internal write signal

8TCNT input clock

8TCNT NM

8TCNT write cycle

8TCNT write data

Figure 10.19 Contention between 8TCNT Write and Increment

Section 10 8-Bit Timers

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10.7.3 Contention between TCOR Write and Compare Match

If a compare match occurs in the T3 state of a TCOR write cycle, writing takes priority and the

compare match signal is inhibited. Figure 10.20 shows the timing in this case.

Address bus TCOR address

Internal write signal

8TCNT

TCOR NM

TCOR write cycle

TCOR write data

N N+1

Compare match signal Inhibited

Figure 10.20 Contention between TCOR Write and Compare Match

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10.7.4 Contention between TCOR Read and Input Capture

If an input capture signal occurs in the T3 state of a TCOR read cycle, the value before input

capture is read. Figure 10.21 shows the timing in this case.

Address bus TCORB address

Internal read signal

Input capture signal

TCORB NM

TCORB read cycle

Internal data bus N

Figure 10.21 Contention between TCOR Read and Input Capture

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10.7.5 Contention between Counter Clearing by Input Capture and Counter Increment

If an input capture signal and counter increment signal occur simultaneously, counter clearing by

the input capture signal takes priority and the counter is not incremented. The value before the

counter is cleared is transferred to TCORB. Figure 10.22 shows the timing in this case.

Counter clear signal

8TCNT internal clock

8TCNT N

H'00

Input capture signal

TCORB N

Figure 10.22 Contention between Counter Clearing by Input Capture and Counter

Increment

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10.7.6 Contention between TCOR Write and Input Capture

If an input capture signal occurs in the T3 state of a TCOR write cycle, input capture takes

priority and the write to TCOR is not performed. Figure 10.23 shows the timing in this case.

Address bus TCOR address

Internal write signal

Input capture signal

8TCNT M

TCOR write cycle

TCOR MX

Figure 10.23 Contention between TCOR Write and Input Capture

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10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

(Cascaded Connection)

If an increment pulse occurs in the T3 state of an 8TCNT byte write cycle in 16-bit count mode,

the counter write takes priority and the byte data for which the write was performed is not

incremented. The byte data for which a write was not performed is incremented. Figure 10.24

shows the timing when an increment pulse occurs in the T2 state of a byte write to 8TCNT (upper

byte). If an increment pulse occurs in the T2 state, on the other hand, the increment takes priority.

Address bus 8TCNTH address

Internal write signal

8TCNT input clock

8TCNT (upper byte) N N+1 8TCNT write dat

8TCNT (upper byte) byte write cycle

8TCNT (lower byte) X+1X

Figure 10.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

Section 10 8-Bit Timers

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10.7.8 Contention between Compare Matches A and B

If compare matches A and B occur at the same time, the 8-bit timer operates according to the

relative priority of the output states set for compare match A and compare match B, as shown in

Table 10.7.

Table 10.7 Timer Output Priority Order

PriorityOutput Setting

HighToggle output

1 output

0 output

No change Low

10.7.9 8TCNT Operation and Internal Clock Source Switchover

Switching internal clock sources may cause 8TCNT to increment, depending on the switchover

timing. Table 10.8 shows the relation between the time of the switchover (by writing to bits

CKS1 and CKS0) and the operation of 8TCNT.

The 8TCNT input clock is generated from the internal clock source by detecting the rising edge of

the internal clock. If a switchover is made from a low clock source to a high clock source, as in

case No. 3 in Table 10.8, the switchover will be regarded as a falling edge, a 8TCNT clock pulse

will be generated, and 8TCNT will be incremented.

8TCNT may also be incremented when switching between internal and external clocks.

Section 10 8-Bit Timers

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Table 10.8 Internal Clock Switchover and 8TCNT Operation

No. CKS1 and CKS0 Write

Timing 8TCNT Operation

1 High → hi gh switchover*1

Old clock

source

New clock

source

8TCNT clock

8TCNT

CKS bits rewritten

N N+1

2 High → l o w switchover*2

Old clock

source

New clock

source

8TCNT clock

8TCNT

CKS bits rewritten

N N+1 N+2

3 Low → high switchover*3

Old clock

source

New clock

source

8TCNT clock

8TCNT

CKS bits rewritten

N N+1 N+2

Section 10 8-Bit Timers

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No. CKS1 and CKS0 Write

Timing 8TCNT Operation

4 Low → low swi tchover*4

Old clock

source

New clock

source

8TCNT clock

8TCNT

CKS bits rewritten

N N+1 N+2

Notes: 1. Including switchovers from the high level to the halted state, and from the halted state

to the high l e vel.

2. Including switchover from the halted state to the low level.

3. Including switchover from the low level to the halted state.

4. The switchover is regarded as a rising edge, causing 8TCNT to increment.

Section 10 8-Bit Timers

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Section 11 Programmable Timing Pattern Controller (TPC)

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Section 11 Programmable Timing Pattern Controller (TPC )

11.1 Overview

The H8/3068F has a built-in programmable timing pattern controller (TPC) that provides pulse

outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided into 4-bit

groups (group 3 to group 0) that can operate simultaneously and independently.

11.1.1 Features

TPC features are listed below.

• 16-bit output data

Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis.

• Four output groups

Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit

outputs.

• Selectable output trigger signals

Output trigger signals can be selected for each group from the compare match signals of three

16-bit timer channels.

• Non-overlap mode

A non-overlap margin can be provided between pulse outputs.

• Can operate together with the DMA controller (DMAC)

The compare-match signals selected as trigger signals can activate the DMAC for sequential

output of data without CPU intervention.

Section 11 Programmable Timing Pattern Controller (TPC)

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11.1.2 Block Diagram

Figure 11.1 shows a block diagram of the TPC.

PADDR

NDERA

TPMR

PBDDR

NDERB

TPCR

Internal

data bu

Control logic

16-bit timer compare match signals

Pulse output

pins, group 3

PBDR

PADR

Legend

TPMR:

TPCR:

NDERB:

NDERA:

PBDDR:

PADDR:

NDRB:

NDRA:

PBDR:

PADR:

Pulse output

pins, group 2

Pulse output

pins, group 1

Pulse output

pins, group 0

TPC output mode register

TPC output control register

Next data enable register B

Next data enable register A

Port B data direction register

Port A data direction register

Next data register B

Next data register A

Port B data register

Port A data re

ister

NDRB

NDRA

Figure 11.1 TPC Block Diagram

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11.1.3 TPC Pins

Table 11.1 summarizes the TPC output pins.

Table 11.1 TPC Pins

Name Symbol I/O Function

TPC output 0 TP0Output Group 0 pulse output

TPC output 1 TP1Output

TPC output 2 TP2Output

TPC output 3 TP3Output

TPC output 4 TP4Output Group 1 pulse output

TPC output 5 TP5Output

TPC output 6 TP6Output

TPC output 7 TP7Output

TPC output 8 TP8Output Group 2 pulse output

TPC output 9 TP9Output

TPC output 10 TP10 Output

TPC output 11 TP11 Output

TPC output 12 TP12 Output Group 3 pulse output

TPC output 13 TP13 Output

TPC output 14 TP14 Output

TPC output 15 TP15 Output

Section 11 Programmable Timing Pattern Controller (TPC)

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11.1.4 Registers

Table 11.2 summarizes the TPC registers.

Table 11.2 TPC Registers

Address*1Name Abbreviation R/W Function

H'EE009 Port A data direction register PADDR W H'00

H'FFFD9 Port A data register PADR R/(W)*2H'00

H'EE00A Port B data direction register PBDDR W H'00

H'FFFDA Port B data register PBDR R/(W)*2H'00

H'FFFA0 TPC output mode register TPMR R/W H'F0

H'FFFA1 TPC output control register TPCR R/W H'FF

H'FFFA2 Next data enable register B NDERB R/W H'00

H'FFFA3 Next data enable register A NDERA R/W H'00

H'FFFA5/

H'FFFA7*3Next data register A NDRA R/W H'00

H'FFFA4/

H'FFFA6*3Next data register B NDRB R/W H'00

Notes: 1. Lower 20 bits of the address in advanced mode.

2. Bits used for TPC output cannot be written.

3. The NDRA address i s H'FFFA5 when the same output trigger is selected for TPC

output groups 0 and 1 by settings i n TPCR. When the output triggers are different, the

NDRA address is H'FFFA7 for group 0 and H'FFFA5 for group 1. Similarly, the address

of NDRB is H'FFFA4 when the same output trigger is selected for TPC output groups 2

and 3 by settings in TPCR. When the output triggers are di fferent, the NDRB address

is H'FFFA6 for group 2 and H'FFFA4 for group 3.

Section 11 Programmable Timing Pattern Controller (TPC)

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11.2 Register Descriptions

11.2.1 Port A Data Direction Register (PADDR)

PADDR is an 8-bit write-only register that selects input or output for each pin in port A.

Bit

Initial value

Read/Write

PA DDR

Port A data direction 7 to 0

These bits select input or

output for port A pins

PA DDR

Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must

be set to 1. For further information about PADDR, see section 8.11, Port A.

11.2.2 Port A Data Register (PADR)

PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when

these TPC output groups are used.

Bit

Initial value

Read/Write

R/(W)*

Port A data 7 to 0

These bits store output data

for TPC output groups 0 and 1

Note: * Bits selected for TPC output b

NDERA settin

s become read-onl

bits.

For further information about PADR, see section 8.11, Port A.

Section 11 Programmable Timing Pattern Controller (TPC)

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11.2.3 Port B Data Direction Register (PBDDR)

PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.

Bit

Initial value

Read/Write

DDR

Port B direction 7 to 0

These bits select input or

output for port B pins

Port B is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must

be set to 1. For further information about PBDDR, see section 8.12, Port B.

11.2.4 Port B Data Register (PBDR)

PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when

these TPC output groups are used.

Bit

Initial value

Read/Write

Note: * Bits selected for TPC output b

NDERB settin

s become read-onl

bits.

PB0

R/(W)*

PB1

R/(W)*

PB2

R/(W)*

PB3

R/(W)*

PB4

R/(W)*

PB5

R/(W)*

PB6

R/(W)*

PB7

R/(W)*

Port B data 7 to 0

These bits store output data

for TPC output groups 2 and 3

For further information about PBDR, see section 8.12, Port B.

Section 11 Programmable Timing Pattern Controller (TPC)

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11.2.5 Next Data Register A (NDRA)

NDRA is an 8-bit readable/writable register that stores the next output data for TPC output

groups 1 and 0 (pins TP7 to TP0). During TPC output, when an 16-bit timer compare match event

specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR.

The address of NDRA differs depending on whether TPC output groups 0 and 1 have the same

output trigger or different output triggers.

NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by

the same compare match event, the NDRA address is H'FFFA5. The upper 4 bits belong to group

1 and the lower 4 bits to group 0. Address H'FFFA7 consists entirely of reserved bits that cannot

be modified and always read 1.

Address H'FFFA5

Bit

Initial value

Read/Write

NDR0

R/W

NDR1

R/W

NDR2

R/W

NDR3

R/W

NDR4

R/W

NDR5

R/W

NDR6

R/W

NDR7

R/W

Next data 7 to 4

These bits store the next output

data for TPC output group 1

Next data 3 to 0

These bits store the next output

data for TPC output group 0

Address H'FFFA7

Bit

Initial value

Read/Write

—

Reserved bits

Section 11 Programmable Timing Pattern Controller (TPC)

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Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are

triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1)

is H'FFFA5 and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address

H'FFFA5 and bits 7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always

Address H'FFFA5

Bit

Initial value

Read/Write

—

NDR4

R/W

NDR5

R/W

NDR6

R/W

NDR7

R/W

Next data 7 to 4

These bits store the next output

data for TPC output group 1

Reserved bits

Address H'FFFA7

Bit

Initial value

Read/Write

NDR0

R/W

NDR1

R/W

NDR2

R/W

NDR3

R/W

—

Next data 3 to 0

These bits store the next output

data for TPC output group 0

Reserved bits

Section 11 Programmable Timing Pattern Controller (TPC)

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11.2.6 Next Data Register B (NDRB)

NDRB is an 8-bit readable/writable register that stores the next output data for TPC output

groups 3 and 2 (pins TP15 to TP8). During TPC output, when an 16-bit timer compare match event

specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR.

The address of NDRB differs depending on whether TPC output groups 2 and 3 have the same

output trigger or different output triggers.

NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by

the same compare match event, the NDRB address is H'FFFA4. The upper 4 bits belong to group

3 and the lower 4 bits to group 2. Address H'FFFA6 consists entirely of reserved bits that cannot

be modified and always read 1.

Address H'FFFA4

Bit

Initial value

Read/Write

NDR8

R/W

NDR9

R/W

NDR10

R/W

NDR11

R/W

NDR12

R/W

NDR13

R/W

NDR14

R/W

NDR15

R/W

Next data 15 to 12

These bits store the next output

data for TPC output group 3

Next data 11 to 8

These bits store the next output

data for TPC output group 2

Address H'FFFA6

Bit

Initial value

Read/Write

—

Reserved bits

Section 11 Programmable Timing Pattern Controller (TPC)

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Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are

triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is

H'FFFA4 and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address

H'FFFA4 and bits 7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always

Address H'FFFA4

Bit

Initial value

Read/Write

—

NDR12

R/W

NDR13

R/W

NDR14

R/W

NDR15

R/W

Next data 15 to 12

These bits store the next output

data for TPC output group 3

Reserved bits

Address H'FFFA6

Bit

Initial value

Read/Write

NDR8

R/W

NDR9

R/W

NDR10

R/W

NDR11

R/W

—

Next data 11 to 8

These bits store the next output

data for TPC output group 2

Reserved bits

Section 11 Programmable Timing Pattern Controller (TPC)

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11.2.7 Next Data Enable Register A (NDERA)

NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0

(TP7 to TP0) on a bit-by-bit basis.

Bit

Initial value

Read/Write

NDER0

R/W

NDER1

R/W

NDER2

R/W

NDER3

R/W

NDER4

R/W

NDER5

R/W

NDER6

R/W

NDER7

R/W

Next data enable 7 to 0

These bits enable or disable

TPC output groups 1 and 0

If a bit is enabled for TPC output by NDERA, then when the 16-bit timer compare match event

selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically

transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled,

the bit value is not transferred from NDRA to PADR and the output value does not change.

NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC

output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis.

Bits 7 to 0

NDER7 to NDER0 Description

0 TPC outputs TP7 to TP0 are disabled

(NDR7 to NDR0 are not tran sferred to PA7 to PA0)(Initial value)

1 TPC outputs TP7 to TP0 are enabled

(NDR7 to NDR0 are transferred to PA7 to PA0)

Section 11 Programmable Timing Pattern Controller (TPC)

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11.2.8 Next Data Enable Register B (NDERB)

NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2

(TP15 to TP8) on a bit-by-bit basis.

Bit

Initial value

Read/Write

NDER8

R/W

NDER9

R/W

NDER10

R/W

NDER11

R/W

NDER12

R/W

NDER13

R/W

NDER14

R/W

NDER15

R/W

Next data enable 15 to 8

These bits enable or disable

TPC output groups 3 and 2

If a bit is enabled for TPC output by NDERB, then when the 16-bit timer compare match event

selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically

transferred to the corresponding PBDR bit, updating the output value. If TPC output is disabled,

the bit value is not transferred from NDRB to PBDR and the output value does not change.

NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC

output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis.

Bits 7 to 0

NDER15 to NDER8 Description

0 TPC outputs TP15 to TP8 are disabl ed

(NDR15 to NDR8 a re not transferred to PB7 to PB0)(Initial value)

1 TPC outputs TP15 to TP8 are enabled

(NDR15 to NDR8 a re transferred to PB7 to PB0)

Section 11 Programmable Timing Pattern Controller (TPC)

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11.2.9 TPC Output Control Register (TPCR)

TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a

group-by-group basis.

Bit

Initial value

Read/Write

G0CMS0

R/W

G0CMS1

R/W

G1CMS0

R/W

G1CMS1

R/W

G2CMS0

R/W

G2CMS1

R/W

G3CMS0

R/W

G3CMS1

R/W

Group 3 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 3

(TP

to TP

)

Group 2 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 2

(TP

to TP

)

Group 1 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 1

(TP

to TP

)

Group 0 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 0

(TP

to TP

)

TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

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Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits

select the compare match event that triggers TPC output group 3 (TP15 to TP12).

Bit 7

G3CMS1 Bit 6

G3CMS0 Description

0 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-

bit ti mer channel 0

1 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-

bit ti mer channel 1

1 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-

bit ti mer channel 2

1 TPC output group 3 (TP15 to TP12) is triggered by

compare match in 16-bit timer channel 2 (Initial value)

Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits

select the compare match event that triggers TPC output group 2 (TP11 to TP8).

Bit 5

G2CMS1 Bit 4

G2CMS0 Description

0 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit

timer channel 0

1 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit

timer channel 1

1 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit

timer channel 2

1 TPC output group 2 (TP11 to TP8) is triggered by

compare match in 16-bit timer channel 2 (Initial value)

Section 11 Programmable Timing Pattern Controller (TPC)

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Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits

select the compare match event that triggers TPC output group 1 (TP7 to TP4).

Bit 3

G1CMS1 Bit 2

G1CMS0 Description

0 0 TPC output group 1 (TP7 to TP4) is triggered by compare match i n 16-bit

timer channel 0

1 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit

timer channel 1

1 0 TPC output group 1 (TP7 to TP4) is triggered by compare match i n 16-bit

timer channel 2

1 TPC output group 1 (TP7 to TP4) is triggered by

compare match in 16-bit timer channel 2 (Initial value)

Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits

select the compare match event that triggers TPC output group 0 (TP3 to TP0).

Bit 1

G0CMS1 Bit 0

G0CMS0 Description

0 0 TPC output group 0 (TP3 to TP0) is triggered by compare match i n 16-bit

timer channel 0

1 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit

timer channel 1

1 0 TPC output group 0 (TP3 to TP0) is triggered by compare match i n 16-bit

timer channel 2

1 TPC output group 0 (TP3 to TP0) is triggered by

compare match in 16-bit timer channel 2 (Initial value)

Section 11 Programmable Timing Pattern Controller (TPC)

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11.2.10 TPC Output Mode Register (TPMR)

TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output

for each group.

Bit

Initial value

Read/Write

—

G3NOV

R/W

G0NOV

R/W

G2NOV

R/W

G1NOV

R/W

Group 3 non-overlap

Selects non-overlapping TPC

output for group 3 (TP to TP )

Reserved bits

Group 2 non-overlap

Selects non-overlapping TPC

output for group 2 (TP to TP )

Group 1 non-overlap

Selects non-overlapping TPC

output for group 1 (TP to TP )

Group 0 non-overlap

Selects non-overlapping TPC

output for group 0 (TP to TP )

15 12

11 8

The output trigger period of a non-overlapping TPC output waveform is set in general register B

(GRB) in the 16-bit timer channel selected for output triggering. The non-overlap margin is set in

general register A (GRA). The output values change at compare match A and B. For details see

section 11.3.4, Non-Overlapping TPC Output.

TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.

Section 11 Programmable Timing Pattern Controller (TPC)

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Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for

group 3 (TP15 to TP12).

Bit 3

G3NOV Description

0 Normal TPC output in group 3 (output values change at

compare match A in the selected 16-bit timer channel) (Initial value)

1 Non-overlapping TPC output in group 3 (independent 1 and 0 output at

compare match A and B in the sel e cted 16-bit timer channel)

Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for

group 2 (TP11 to TP8).

Bit 2

G2NOV Description

0 Normal TPC output in group 2 (output values change at

compare match A in the selected 16-bit timer channel) (Initial value)

1 Non-overlapping TPC output in group 2 (independent 1 and 0 output at

compare match A and B in the sel e cted 16-bit timer channel)

Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for

group 1 (TP7 to TP4).

Bit 1

G1NOV Description

0 Normal TPC output in group 1 (output values change at

compare match A in the selected 16-bit timer channel) (Initial value)

1 Non-overlapping TPC output in group 1 (independent 1 and 0 output at

compare match A and B in the sel e cted 16-bit timer channel)

Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for

group 0 (TP3 to TP0).

Bit 0

G0NOV Description

0 Normal TPC output in group 0 (output values change at

compare match A in the selected 16-bit timer channel) (Initial value)

1 Non-overlapping TPC output in group 0 (independent 1 and 0 output at

compare match A and B in the sel e cted 16-bit timer channel)

Section 11 Programmable Timing Pattern Controller (TPC)

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11.3 Operation

11.3.1 Overview

When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output

is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.

When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit

contents are transferred to PADR or PBDR to update the output values.

Figure 11.2 illustrates the TPC output operation. Table 11.3 summarizes the TPC operating

conditions.

DDR NDER

TPC output pin

DR NDR

QD QDInternal

data bus

Output trigger signal

Figure 11.2 TPC Output Operation

Table 11.3 TPC Operating Conditions

NDER DDR Pin Function

0 0 Generic input port

1 Generic output port

1 0 Generic input port (but the DR bit is a read-onl y bit, and when compare

match occurs, the NDR bit value is tr a nsferred to the DR bit)

1 TPC pulse output

Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and

NDRB before the next compare match. For information on non-overlapping operation, see

section 11.3.4, Non-Overlapping TPC Output.

Section 11 Programmable Timing Pattern Controller (TPC)

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11.3.2 Output Timing

If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output

when the selected compare match event occurs. Figure 11.3 shows the timing of these operations

for the case of normal output in groups 2 and 3, triggered by compare match A.

TCNT

GRA

Compare

match A signal

NDRB

PBDR

TP to TP

815

N + 1

Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example)

Section 11 Programmable Timing Pattern Controller (TPC)

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11.3.3 Normal TPC Output

Sample Setup Procedure for Normal TPC Output: Figure 11.4 shows a sample procedure for

setting up normal TPC output.

Normal TPC output

Set next TPC output data

Compare match? No

Yes

Set next TPC output data

16-bit timer

setup

16-bit timer

setup

Port and

TPC setup

10.

11.

Set TIOR to make GRA an output compare

Set the TPC output trigger period.

Select the counter clock source with bits

TPSC2 to TPSC0 in TCR. Select the counter

clear source with bits CCLR1 and CCLR0.

Enable the IMFA interrupt in TIER.

The DMAC can also be set up to transfer

data to the next data register.

Set the initial output values in the DR bits

of the input/output port pins to be used for

TPC output.

Set the DDR bits of the input/output port

pins to be used for TPC output to 1.

Set the NDER bits of the pins to be used for

TPC output to 1.

Select the 16-bit timer compare match event

to be used as the TPC output trigger in TPCR.

Set the next TPC output values in the NDR bits.

Set the STR bit to 1 in TSTR to start the

timer counter.

At each IMFA interrupt, set the next output

values in the NDR bits.

Select GR functions

Set GRA value

Select counting operation

Select interrupt request

Start counter

Set initial output data

Select port output

Enable TPC output

Select TPC output trigger

Figure 11.4 Setup Procedure for Normal TPC Output (Example)

Section 11 Programmable Timing Pattern Controller (TPC)

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Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows

an example in which the TPC is used for cyclic five-phase pulse output.

GRA

H'0000

NDRB

PBDR

TP15

TP14

TP13

TP12

TP11

•

Time

TCNT

TCNT value

C0 40 60 20 30 10 18 08 88 80 C0

Compare match

The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output

compare register and the counter will be cleared by compare match A. The trigger period is set in GRA.

The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt.

H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in

TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger.

Output data H'80 is written in NDRB.

The timer counter in this 16-bit timer channel is started. When compare match A occurs, the NDRB

contents are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt

service routine writes the next output data (H'C0) in NDRB.

Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing

H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts. If the DMAC is set for

activation by this interrupt, pulse output can be obtained without loading the CPU.

80 C0 40 60 20 30 10 18 08 88 80 C0 40

Figure 11.5 Normal TPC Output Example (Five-Phase Pulse Output)

Section 11 Programmable Timing Pattern Controller (TPC)

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11.3.4 Non-Overlapping TPC Output

Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11.6 shows a sample

procedure for setting up non-overlapping TPC output.

Non-overlapping

TPC output

Set next TPC output data

Compare match A? No

Yes

Set next TPC output data

Start counter

16-bit timer

setup

16-bit timer

setup

Port and

TPC setup

Set initial output data

Set up TPC output

Enable TPC transfer

Select TPC transfer trigger

Select non-overlapping groups

10.

11.

12.

Set TIOR to make GRA and GRB output

compare registers (with output inhibited).

Set the TPC output trigger period in GRB

and the non-overlap margin in GRA.

Select the counter clock source with bits

TPSC2 to TPSC0 in TCR. Select the counter

clear source with bits CCLR1 and CCLR0.

Enable the IMFA interrupt in TISRA.

The DMAC can also be set up to transfer

data to the next data register.

Set the initial output values in the DR bits

of the input/output port pins to be used for

TPC output.

Set the DDR bits of the input/output port pins

to be used for TPC output to 1.

Set the NDER bits of the pins to be used for

TPC output to 1.

In TPCR, select the 16-bit timer compare match

event to be used as the TPC output trigger.

In TPMR, select the groups that will operate

in non-overlap mode.

Set the next TPC output values in the NDR

bits.

Set the STR bit to 1 in TSTR to start the timer

counter.

At each IMFA interrupt, write the next output

value in the NDR bits.

Select GR functions

Set GR values

Select counting operation

Select interrupt requests

Figure 11.6 Setup Procedure for Non-Overlapping TPC Output (Example)

Section 11 Programmable Timing Pattern Controller (TPC)

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Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-

Overlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase

complementary non-overlapping pulse output.

GRB

H'0000

NDRB

PBDR

TP15

TP14

TP13

TP12

TP11

TP10

TP9

TP8

Time

59 56 95 65

05 65 41 59 50 56 14 95 05 65

TCNT

period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TISRA to enable

IMFA interrupts.

H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in

TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Bits

G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in

NDRB.

TCNT value

Non-overlap margin

The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are

output compare registers and the counter will be cleared by compare match B. The TPC output trigger

•

The timer counter in this 16-bit timer channel is started. When compare match B occurs, outputs change

from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed

by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.

Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…

at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be

obtained without loading the CPU.

GRA

Figure 11.7 Non-Overlapping TPC Output Example (Four-Phase Complementary

Non-Overlapping Pulse Output)

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11.3.5 TPC Output Triggering by Input Capture

TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA

functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output

will be triggered by the input capture signal. Figure 11.8 shows the timing.

TIOC pin

Input capture

signal

NDR

DR N

Figure 11.8 TPC Output Triggering by Input Capture (Example)

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11.4 Usage Notes

11.4.1 Operation of TPC Output Pins

TP0 to TP15 are multiplexed with 16-bit timer, DMAC, address bus, and other pin functions.

When 16-bit timer, DMAC, or address output is enabled, the corresponding pins cannot be used

for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of

the usage of the pin.

Pin functions should be changed only under conditions in which the output trigger event will not

occur.

11.4.2 Note on Non-Overlapping Output

During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as

follows.

1. NDR bits are always transferred to DR bits at compare match A.

2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred

if their value is 1.

Figure 11.9 illustrates the non-overlapping TPC output operation.

DDR NDER

TPC output pin

DR NDR

QD QD

Compare match A

Compare match B

Figure 11.9 Non-Overlapping TPC Output

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Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before

compare match A. NDR contents should not be altered during the interval from compare match B

to compare match A (the non-overlap margin).

This can be accomplished by having the IMFA interrupt service routine write the next data in

NDR, or by having the IMFA interrupt activate the DMAC. The next data must be written before

the next compare match B occurs.

Figure 11.10 shows the timing relationships.

Compare

match A

Compare

match B

NDR write

NDR

NDR write

0/1 output 0/1 output0 output 0 output

Do not write

to NDR in this

interval

Do not write

to NDR in this

interval

Write to NDR

in this interval

Write to NDR

in this interval

Figure 11.10 Non-Overlapping Operation and NDR Write Timing

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Section 12 Watchdog Timer

12.1 Overview

The H8/3068F has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it

can operate as a watchdog timer to supervise system operation, or it can operate as an interval

timer. As a watchdog timer, it generates a reset signal for the H8/3068F chip if a system crash

allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation,

an interval timer interrupt is requested at each TCNT overflow.

12.1.1 Features

WDT features are listed below.

• Selection of eight counter clock sources

φ/2, φ /32, φ /64, φ /128, φ /256, φ /512, φ /2048, or φ /4096

• Interval timer option

• Timer counter overflow generates a reset signal or interrupt.

The reset signal is generated in watchdog timer operation. An interval timer interrupt is

generated in interval timer operation.

• Watchdog timer reset signal resets the entire H8/3068F internally.

The reset signal generated by timer counter overflow during watchdog timer operation resets

the entire H8/3068F internally.

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12.1.2 Block Diagram

Figure 12.1 shows a block diagram of the WDT.

φ/2

φ/32

φ/64

φ/128

φ/256

φ/512

φ/2048

φ/4096

TCNT

TCSR

RSTCSR

Reset control

Interrupt signal

Reset

(internal, external)

(interval timer) Interrupt

control

Overflow

Clock Clock

selector

Read/

write

control

Internal

data bus

Internal clock sources

Legend

TCNT:

TCSR:

RSTCSR:

Timer counter

Timer control/status register

Reset control/status register

Figure 12.1 WDT Block Diagram

12.1.3 Register Configuration

Table 12.1 summarizes the WDT registers.

Table 12.1 WDT Registers

Address*1

Write*2Read Name Abbreviation R/W Initial Value

H'FFF8C H'FFF8C Timer control /status register TCSR R/(W)*3H'18

H'FFF8D Timer counter TCNT R/W H'00

H'FFF8E H'FFF8F Reset control/status register RSTCSR R/(W)*3H'3F

Notes: 1. Lower 20 bits of the address in advanced mode.

2. Write word data starting at this address.

3. Only 0 can be written in bit 7, to clear the flag.

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12.2 Register Descriptions

12.2.1 Timer Counter (TCNT)

TCNT is an 8-bit readable and writable up-counter.

Bit

Initial value

Read/Write

Note: TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register

Access.

R/W

When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal

clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from

H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when

the TME bit is cleared to 0.

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12.2.2 Timer Control/Status Register (TCSR)

TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode

and clock source.

Bit

Initial value

Read/Write

Notes: TCSR is write-protected by a password. For details see section 12.2.4, Notes on Register

Access.

* Onl

0 can be written, to clear the fla

OVF

R/(W)*

WT/IT

R/W

TME

R/W

—

CKS0

R/W

CKS2

R/W

CKS1

R/W

Overflow flag

Status flag indicating overflow

Clock select

These bits select the

TCNT clock source

Timer mode select

Selects the mode

Timer enable

Selects whether TCNT runs or halts

Reserved bits

Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a

reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.

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Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed

from H'FF to H'00.

Bit 7

OVF Description

0 [Clearing condition]

Cleared by reading OVF when OVF = 1, then writing 0 in OVF (Initial value)

1 [Setting condition]

Set when TCNT changes from H'FF to H'00

Bit 6—Timer Mode Select (WT/

): Selects whether to use the WDT as a watchdog timer or

interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request

when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when

TCNT overflows.

Bit 6

WT/

Description

0 Interval timer: requests interval timer interrupts (Initial val ue)

1 Watchdog timer: generates a reset signal

Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted. When WT/

= 1, clear

the software standby bit (SSBY) to 0 in SYSCR before setting TME. When setting SSBY to 1,

TME should be cleared to 0.

Bit 5

TME Description

0 TCNT is initialized to H'00 and halted (Initial val ue)

1 TCNT is counting

Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.

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Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock

sources, obtained by prescaling the system clock (φ), for input to TCNT.

Bit 2

CKS2 Bit 1

CKS1 Bit 0

CKS0 Description

000φ/2 (Initi al value)

1φ /32

10φ /64

1φ /128

100φ /256

1φ /512

10φ /2048

1φ /4096

12.2.3 Reset Control/Status Register (RSTCSR)

RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been

generated by watchdog timer overflow, and controls external output of the reset signal.

Bit

Initial value

Read/Write

Notes: RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on

* Onl

0 can be written in bit 7, to clear the fla

WRST

R/(W)*

—

R/W

—

Watchdog timer reset

Indicates that a reset signal has been generated

Reserved bits

Bits 7 and 6 are initialized by input of a reset signal at the

RES

pin. They are not initialized by

reset signals generated by watchdog timer overflow.

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Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates

that TCNT has overflowed and generated a reset signal. This reset signal resets the entire

H8/3068F chip internally.

Bit 7

WRST Description

0 [Clearing condition]

Reset signal at

RES

pin.

Read WRST when WRST =1, then write 0 in WRST. (Initial value)

1 [Setting condition]

Set when TCNT overflow generates a reset signal during watchdog timer operation

Bit 6—Reserved

Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.

12.2.4 Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being

more difficult to write. The procedures for writing and reading these registers are given below.

Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.

They cannot be written by byte instructions. Figure 12.2 shows the format of data written to

TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be

contained in the lower byte of the written word. The upper byte must contain H'5A (password for

TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT

or TCSR.

15 8 7 0

H'5A Write dataAddress H'FFF8C*

15 8 7 0

H'A5 Write dataAddress H'FFF8C*

TCNT write

TCSR write

Note: * Lower 20 bits of the address in advanced mode.

Figure 12.2 Format of Data Written to TCNT and TCSR

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Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be

written by byte transfer instructions. Figure 12.3 shows the format of data written to RSTCSR. To

write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower

byte. The data (H'00) in the lower byte is written to RSTCSR, clearing the WRST bit to 0. To

write to the RSTOE bit, the upper byte must contain H'5A and the lower byte must contain the

write data. Writing this word transfers a write data value into the RSTOE bit.

15 8 7 0

H'A5 H'00Address H'FFF8E*

15 8 7 0

H'5A Write dataAddress H'FFF8E*

Writing 0 in WRST bit

Writing to RSTOE bit

Note: * Lower 20 bits of the address in advanced mode.

Figure 12.3 Format of Data Written to RSTCSR

Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Reading

TCNT, TCSR, and RSTCSR: These registers are read like other registers. Byte transfer

instructions can be used. The read addresses are H'FFF8C for TCSR, H'FFF8D for TCNT, and

H'FFF8F for RSTCSR, as listed in table 12.2.

Table 12.2 Read Addresses of TCNT, TCSR, and RSTCSR

Address*Register

H'FFF8C TCSR

H'FFF8D TCNT

H'FFF8F RSTCSR

Note: *Lower 20 bits of the address in advanced mode.

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12.3 Operation

Operations when the WDT is used as a watchdog timer and as an interval timer are described

below.

12.3.1 Watchdog Timer Operation

Figure 12.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the

WT/

and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the

TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and

overflows due to a system crash etc., the H8/3068F is internally reset for a duration of 518 states.

A watchdog reset has the same vector as a reset generated by input at the

RES

pin. Software can

distinguish a

RES

reset from a watchdog reset by checking the WRST bit in RSTCSR.

If a

RES

reset and a watchdog reset occur simultaneously, the

RES

reset takes priority.

H'FF

H'00

WDT overflow

Start H'00 written

in TCNT Reset

TME set to 1

H'00 written

in TCNT

Internal

reset signal

518 states

TCNT count

value

OVF = 1

Figure 12.4 Operation in Watchdog Timer Mode

Section 12 Watchdog Timer

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12.3.2 Interval Timer Operation

Figure 12.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit

WT/

to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each

TCNT overflow. This function can be used to generate interval timer interrupts at regular

intervals.

TCNT

count value

Time t

Interval

timer

interrupt

Interval

timer

interrupt

Interval

timer

interrupt

Interval

timer

interrupt

WT/ = 0

TME = 1

H'FF

H'00

Figure 12.5 Interval Timer Operation

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12.3.3 Timing of Setting of Overflow Flag (OVF)

Figure 12.6 shows the timing of setting of the OVF flag. The OVF flag is set to 1 when TCNT

overflows. At the same time, a reset signal is generated in watchdog timer operation, or an

interval timer interrupt is generated in interval timer operation.

TCNT

Overflow signal

OVF

H'FF H'00

Figure 12.6 Timing of Setting of OVF

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12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)

The WRST bit in RSTCSR is valid when bits WT/

and TME are both set to 1 in TCSR.

Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is

set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is

generated for the entire H8/3068F chip. This internal reset signal clears OVF to 0, but the WRST

bit remains set to 1. The reset routine must therefore clear the WRST bit.

TCNT

Overflow signal

OVF

WRST

H'FF H'00

WDT internal

reset

Figure 12.7 Timing of Setting of WRST Bit and Internal Reset

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12.4 Interrupts

During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The

interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.

12.5 Usage Notes

Contention between TCNT Write and Increment: If a timer counter clock pulse is generated

during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not

incremented. See figure 12.8.

TCNT

TCNT NM

Counter write dat

CPU: TCNT write cycle

Internal write

signal

TCNT input

clock

Figure 12.8 Contention between TCNT Write and Count up

Changing CKS2 to CKS0 Bit: Halt TCNT by clearing the TME bit to 0 in TCSR before

changing the values of bits CKS2 to CKS0.

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Section 13 Serial Communication Interface

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Section 13 Serial Communication Interface

13.1 Overview

The H8/3068F has a serial communication interface (SCI) with three independent channels. All

three channels have identical functions. The SCI can communicate in both asynchronous and

synchronous mode. It also has a multiprocessor communication function for serial

communication among two or more processors.

When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted

independently. For details, see section 20.6, Module Standby Function.

The SCI also has a smart card interface function conforming to the ISO/IEC 7816-3

(Identification Card) standard. This function supports serial communication with a smart card.

Switching between the normal serial communication interface and the smart card interface is

carried out by means of a register setting.

13.1.1 Features

SCI features are listed below.

• Selection of synchronous or asynchronous mode for serial communication

Asynchronous mode

Serial data communication is synchronized one channel at a time. The SCI can communicate

with a universal asynchronous receiver/transmitter (UART), asynchronous communication

interface adapter (ACIA), or other chip that employs standard asynchronous communication.

It can also communicate with two or more other processors using the multiprocessor

communication function. There are twelve selectable serial data transfer formats.

 Data length: 7 or 8 bits

 Stop bit length: 1 or 2 bits

 Parity: even/odd/none

 Multiprocessor bit: 1 or 0

 Receive error detection: parity, overrun, and framing errors

 Break detection: by reading the RxD level directly when a framing error occurs

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Synchronous mode

Serial data communication is synchronized with a clock signal. The SCI can communicate

with other chips having a synchronous communication function.

There is a single serial data communication format.

 Data length: 8 bits

 Receive error detection: overrun errors

• Full-duplex communication

The transmitting and receiving sections are independent, so the SCI can transmit and receive

simultaneously. The transmitting and receiving sections are both double-buffered, so serial

data can be transmitted and received continuously.

• The following settings can be made for the serial data to be transferred:

 LSB-first or MSB-first transfer

 Inversion of data logic level

• Built-in baud rate generator with selectable bit rates

• Selectable transmit/receive clock sources: internal clock from baud rate generator, or external

clock from the SCK pin

• Four types of interrupts

Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are

requested independently. The transmit-data-empty and receive-data-full interrupts from SCI0

can activate the DMA controller (DMAC) to transfer data.

Features of the smart card interface are listed below.

• Asynchronous communication

 Data length: 8 bits

 Parity bits generated and checked

 Error signal output in receive mode (parity error)

 Error signal detect and automatic data retransmit in transmit mode

 Supports both direct convention and inverse convention

• Built-in baud rate generator with selectable bit rates

• Three types of interrupts

Transmit-data-empty, receive-data-full, and transmit/receive-error interrupts are requested

independently. The transmit-data-empty and receive-data-full interrupts can activate the

DMA controller (DMAC) to transfer data.

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13.1.2 Block Diagram

Figure 13.1 shows a block diagram of the SCI.

RDR

RSR

TDR

TSR

SSR

SCR

SMR

SCMR

BRR

φ/ 4

φ/16

φ/64

RxD

TxD

SCK TEI

TXI

RXI

ERI

Legend

RSR : Receive shift register

RDR : Receive data register

TSR : Transmit shift register

TDR : Transmit data register

SMR : Serial mode register

SCR : Serial control register

SSR : Serial status register

BRR : Bit rate register

SCMR : Smart card mode re

ister

Module data bus

Bus interface

Internal data bu

Parity generate

Parity check

Transmit/receive

control

Baud rate

generator

Clock

External clock

Figure 13.1 SCI Block Diagram

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13.1.3 Input/Output Pins

The SCI has serial pins for each channel as listed in table 13.1.

Table 13.1 SCI Pins

Channel Name Abbreviation I/O Function

0 Serial clock pin SCK0Input/output SCI0 clock input/output

Receive data pin RxD0Input SCI0 receive data input

Transmit data pin TxD0Output SCI0 transmit data output

1 Serial clock pin SCK1Input/output SCI1 clock input/output

Receive data pin RxD1Input SCI1 receive data input

Transmit data pin TxD1Output SCI1 transmit data output

2 Serial clock pin SCK2Input/output SCI2 clock input/output

Receive data pin RxD2Input SCI2 receive data input

Transmit data pin TxD2Output SCI2 transmit data output

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13.1.4 Register Configuration

The SCI has internal registers as listed in table 13.2. These registers select asynchronous or

synchronous mode, specify the data format and bit rate, control the transmitter and receiver

sections, and specify switching between the serial communication interface and smart card

interface.

Table 13.2 SCI Registers

Channel Address*1Name Abbreviation R/W Initial Value

0 H’FFFB0 Serial mode register SMR R/W H'00

H’FFFB1 Bit rate register BRR R/W H'FF

H’FFFB2 Serial control register SCR R/W H'00

H’FFFB3 Transmi t data register TDR R/W H'FF

H’FFFB4 Serial status register SSR R/(W)*2H'84

H’FFFB5 Receive data register RDR R H'00

H’FFFB6 Smart card mode register SCMR R/W H'F2

1 H’FFFB8 Serial mode register SMR R/W H'00

H’FFFB9 Bit rate register BRR R/W H'FF

H’FFFBA Serial control register SCR R/W H'00

H’FFFBB Transmit data register TDR R/W H'FF

H’FFFBC Serial status register SSR R/(W)*2H'84

H’FFFBD Receive data register RDR R H'00

H’FFFBE Smart card mode register SCMR R/W H'F2

2 H’FFFC0 Serial mode register SMR R/W H'00

H’FFFC1 Bit rate register BRR R/W H'FF

H’FFFC2 Serial control register SCR R/W H'00

H’FFFC3 Transmit data register TDR R/W H'FF

H’FFFC4 Serial status register SSR R/(W)*2H'84

H’FFFC5 Receive data regi ster RDR R H'00

H’FFFC6 Smart card mode register SCMR R/W H'F2

Notes: 1. Indicates the lower 20 bits of the address in advanced mode.

2. Only 0 can be written, to cl ear flags.

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13.2 Register Descriptions

13.2.1 Receive Shift Register (RSR)

RSR is the register that receives serial data.

Bit

76543210

Read/Write

The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first,

thereby converting the data to parallel data. When one byte of data has been received, it is

automatically transferred to RDR. The CPU cannot read or write RSR directly.

13.2.2 Receive Data Register (RDR)

RDR is the register that stores received serial data.

Bit 76543210

Initial value

Read/Write R

00000

000

RRRR

When the SCI has received one byte of serial data, it transfers the received data from RSR into

RDR for storage, completing the receive operation. RSR is then ready to receive the next data.

This double-buffering allows data to be received continuously.

RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to

H'00 by a reset and in standby mode.

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13.2.3 Transmit Shift Register (TSR)

TSR is the register that transmits serial data.

Bit 7 6543210

Read/Write

The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin,

LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit

data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR, however,

the SCI does not load the TDR contents into TSR. The CPU cannot read or write RSR directly.

13.2.4 Transmit Data Register (TDR)

TDR is an 8-bit register that stores data for serial transmission.

Bit 76543210

Initial value

Read/Write R/W

11111111

R/WR/WR/WR/WR/WR/W

R/W

When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into

TSR and starts serial transmission. Continuous serial transmission is possible by writing the next

transmit data in TDR during serial transmission from TSR.

The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby

mode.

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13.2.5 Serial Mode Register (SMR)

SMR is an 8-bit register that specifies the SCI's serial communication format and selects the

clock source for the baud rate generator.

C/ACHR PE O/ESTOP MP CKS1 CKS0

R/W

00000000

R/WR/WR/WR/WR/WR/WR/W

Initial value

Read/Write

Bit 76543210

Clock select 1/0

These bits select the

baud rate generator's

clock source

Communication mode

Selects asynchronous or synchronous mode

Character length

Selects character length in asynchronous mode

Parity enable

Enables or disables the addition of a parity bit

Parity mode

Selects even or odd parity

Stop bit length

Selects the stop bit length

Multiprocessor mode

Selects the multiprocessor

function

The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby

mode.

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Bit 7—Communication Mode (C/

)/GSM Mode (GM): The function of this bit differs for the

normal serial communication interface and for the smart card interface. Its function is switched

with the SMIF bit in SCMR.

For serial communication interface (SMIF bit in SCMR cleared to 0): Selects whether the

SCI operates in asynchronous or synchronous mode.

Bit 7

Description

0 Asynchronous mode (Initial value)

1 Synchronous mode

For smart card interface (SMIF bit in SCMR set to 1): Selects GSM mode for the smart card

interface.

Bit 7

GM Description

0 The TEND flag is set 12.5 etu after the start bit (Initial value)

1 The TEND flag is set 11.0 etu after the start bit

Note: etu (Elementary time unit: the time for transfer of one bit)

Bit 6—Character Length (CHR): Selects 7-bit or 8-bits data length in asynchronous mode. In

synchronous mode, the data length is 8 bits regardless of the CHR setting,

Bit 6

CHR Description

0 8-bit data (Initial value)

1 7-bi t data*

Note: *When 7-bit data is sel ected, the MSB (bit 7) of TDR is not transmitted.

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Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a

parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous

mode, the parity bit is neither added nor checked, regardless of the PE bit setting.

Bit 5

PE Description

0 Parity bit not added or checked (Initial value)

1 Parity bit added and checked*

Note: * When PE bit i s set to 1, an even or odd parity bit is added to transmit data according to the

even or odd parity mode selection by the O/

bit, and the pari ty bit in receive data is

checked to see that it matches the even or odd mode selected by the O/

bit.

Bit 4—Parity Mode (O/

): Selects even or odd parity. The O/

bit setting is only valid when

the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/

bit setting is ignored in synchronous mode, or when parity addition and checking is disabled in

asynchronous mode.

Bit 4

Description

0 Even parity*1(Initial value)

1 Odd parity*2

Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even

number of 1s in the transmitted character and parity bit combined. Receive data must

have an even number of 1s in the received character and parity bit combined.

2. When odd parity is selected, the parity bit added to transmit data makes an odd

number of 1s in the transmitted character and parity bit combined. Receive data must

have an odd number of 1s in the received character and parity bit combined.

Bit 3—Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This

setting is used only in asynchronous mode. In synchronous mod no stop bit is added, so the

STOP bit setting is ignored.

Bit 3

STOP Description

0 1 stop bit*1(Initial value)

1 2 stop bits*2

Notes: 1. One stop bit (with value 1) is added to the end of each transmitted character.

2. Two stop bits (with value 1) are added to the end of each transmitted character.

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In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second

stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the

next incoming character.

Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor

format is selected, parity settings made by the PE and O/

bits are ignored. The MP bit setting is

valid only in asynchronous mode. It is ignored in synchronous mode.

For further information on the multiprocessor communication function, see section 13.3.3,

Multiprocessor Communication.

Bit 2

MP Description

0 Multi processor function disabled (Initial value)

1 Multi processor format selected

Bits 1 and 0—Clock Select 1 and 0 (CKS1/0): These bits select the clock source for the on-chip

baud rate generator. Four clock sources are available: φ, φ/4, φ/16, and φ/64.

For the relationship between the clock source, bit rate register setting, and baud rate, see section

13.2.8, Bit Rate Register (BRR).

Bit 1

CKS1 Bit 0

CKS0 Description

00φ(Initial value)

01φ/4

10φ/16

11φ/64

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13.2.6 Serial Control Register (SCR)

SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock

output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive

clock source.

Bit 7 6 5 43210

TIE RIE TE RE MPIE TEIE CKE1 CKE0

Initial value

Read/Write R/W

00000000

R/W

R/WR/WR/WR/W

Transmit-end interrupt enable

Enables or disables transmit-end

interrupts (TEI)

Multiprocessor interrupt enable

Enables or disables multiprocessor

interrupts

Receive enable

Enables or disables the receiver

Transmit enable

Enables or disables the transmitter

Receive interrupt enable

Enables or disables receive-data-full interrupts (RXI) and

receive-error interrupts (ERI)

Transmit interrupt enable

Enables or disables transmit-data-empty interrupts (TXI)

Clock enable 1/0

hese bits select the

SCI clock source

The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby

mode.

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Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt

(TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from

TDR to TSR.

Bit 7

TIE Description

0 Transmit-data-empty interrupt request (TXI) is disabled*(Initial val ue)

1 Transmit-data-empty interrupt request (TXI) is enabled

Note: *TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then

cleari ng it to 0; or by clearing the TIE bit to 0.

Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt

(RXI) requested when the RDRF flag in SSR is set to 1 due to transfer of serial receive data from

RSR to RDR; also enables or disables the receive-error interrupt (ERI).

Bit 6

RIE Description

0 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are

disabled*(Initial value)

1 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled

Note: *RXI and ERI interrupt requests can be cleared by reading the val ue 1 from the RDRF, FER,

PER, or ORER flag, then cleari ng the flag to 0; or by clearing the RIE bit to 0.

Bit 5—Transmit Enable (TE): Enables or disables the start of SCI serial transmitting

operations.

Bit 5

TE Description

0 Transmitting di sabled*1(Initial value)

1 Transmitting enabled*2

Notes: 1. The TDRE flag is fixed at 1 in SSR.

2. In the enabled state, serial transmission starts when the TDRE flag in SSR is cleared

to 0 after writing of transmit data i nto TDR. Select the transmit format in SMR before

setting the TE bit to 1.

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Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.

Bit 4

RE Description

0 Receiving disabled*1(Initial value)

1 Receiving enabled*2

Notes: 1. Clearing the RE bit to 0 does not affect the RDRF , FER, PER, and ORER flags. These

flags retai n their previous values.

2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous

mode, or serial clock input is detected in synchronous mode. Select the receive format

in SMR before setting the RE bit to 1.

Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor

interrupts. The MPIE bit setting is valid only in asynchronous mode, and only if the MP bit is set

to 1 in SMR. The MPIE bit setting is ignored in synchronous mode or when the MP bit is cleared

to 0.

Bit 3

MPIE Description

0 Multiprocessor interrupts are disabled (normal receive operation)(Initial value)

Clearing conditions

(1) The MPIE bit is cleared to 0

(2) MPB = 1 in received data

1 Multiprocessor interrupts are enabled*

Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of

the RDRF, FER, and ORER status flags in SSR are disabled until data with the

mu ltiprocessor bit set to 1 is received.

Note: *The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,

and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which

MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0,

enables RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows the

FER and ORER flags to be set.

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Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt

(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.

Bit 2

TEIE Description

0 Transmit-end interrupt requests (TEI) are disabled*(Initial value)

1 Transmit-end interrupt requests (TEI) are enabled*

Note: *TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,

then cleari ng the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing

the TEIE bit to 0.

Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): The function of these bits differs for the normal

serial communication interface and for the smart card interface. Their function is switched with

the SMIF bit in SCMR.

For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the

SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings

of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or

serial clock input.

The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally

clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external

clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the

CKE1 and CKE0 bits . For further details on selection of the SCI clock source, see table 13.9 in

section 13.3, Operation.

Bit 1

CKE1 Bit 0

CKE0 Description

0 0 Asynchronous mode Internal clock, SCK pin available for generic i nput/output *1

Synchronous mode Internal clock, SCK pin used for serial clock output*1

0 1 Asynchronous mode Internal clock, SCK pin used for clock output*2

Synchronous mode Internal clock, SCK pin used for serial clock output

1 0 Asynchronous mode External clock, SCK pin used for clock input*3

Synchronous mode External clock, SCK pin used for serial clock input

1 1 Asynchronous mode External clock, SCK pin used for clock input*3

Synchronous mode External clock, SCK pin used for serial clock input

Notes: 1. Initial value

2. The output clock frequency is the same as the bit rate.

3. The input clock frequency is 16 times the bit rate.

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For smart card interface (SMIF bit in SCMR set to 1): These bits, together with the GM bit in

SMR, determine whether the SCK pin is used for generic input/output or as the serial clock output

pin.

SMR

GM Bit 1

CKE1 Bit 0

CKE0 Description

0 0 0 SCK pin available for generic input/output (Initial value)

0 0 1 SCK pin used for clock output

1 0 0 SCK pin output fixed low

1 0 1 SCK pin used for clock output

1 1 0 SCK pin output fixed high

1 1 1 SCK pin used for clock output

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13.2.7 Serial Status Register (SSR)

SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the

operating status of the SCI.

Initial value

Read/Write RR/W

01000100

Bit 76543210

Multiprocessor bit

transfer

Value of multiprocessor

bit to be transmitted

R/(W)

TDRE RDRF ORER FER/ERS PER TEND MPB MPBT

Multiprocessor bit

Stores the received

multiprocessor bit value

Transmit end

Status flag indicating end of

transmission

Parity error

Status flag indicating detection

of a receive parity error

Framing error (FER)/Error signal status (ERS)

Status flag indicating detection of a receive framing

error, or flag indicating detection of an error signal

Overrun error

Status flag indicating detection

of a receive overrun error

Receive data register full

Status flag indicating that data has been received

and stored in RDR

Transmit data register empty

Status flag indicating that transmit data has been transferred from

TDR into TSR and new data can be written in TDR

Notes: 1. Only 0 can be written, to clear the flag.

2. Function differs between the normal serial communication interface and the smart card interface.

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The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,

and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1.

The TEND and MPB flags are read-only bits that cannot be written.

SSR is initialized to H'84 by a reset and in standby mode.

Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data

from TDR into TSR and the next serial data can be written in TDR.

Bit 7

TDRE Description

0 TDR contains valid transmit data

Clearing conditions

Read TDRE when TDRE = 1, then write 0 in TDRE

The DMAC wr ites data in TDR

1 TDR does not contain valid transmit data (Initial value)

Setting conditions

The chip is reset or enters standby mode

The TE bit in SCR is cleared to 0

TDR contents are loaded into TSR, so new data can be wri tten in TDR

Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.

Bit 6

RDRF Description

0 RDR does not contain new receive data (Initial value)

Clearing conditions

The chip is reset or enters standby mode

Read RDRF when RDRF = 1, then write 0 in RDRF

The DMAC reads data from RDR

1 RDR con t ains new receive data

Setting condition

Serial data is received normally and transferred from RSR to RDR

Note: The RDR contents and the RDRF flag are not affected by detection of receive er rors or by

clearing of th e RE bit to 0 in SCR. The y retain their p revious values. If the RDRF flag is

still set to 1 when reception of the next data ends, an overrun error will occur and the

receive data will be lost.

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Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an

overrun error.

Bit 5

ORER Description

0 Receiving is in progress or has ended normally*1(Initial value)

Clearing conditions

The chip is reset or enters standby mode

Read ORER when ORER = 1, then write 0 in ORER

1 A receive overrun error occurred*2

Setting condition

Reception of the next serial data ends when RDRF = 1

Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, wh ich retains its

previous val ue.

2. RDR continues to hold the receive data prior to the overrun error, so subsequent

receive data is lost. Serial receiving cannot continue while the ORER flag is set to 1.

In synchronous mode, serial transmitting is also disabled.

Bit 4—Framing Error (FER)/Error Signal Status (ERS): The function of this bit differs for

the normal serial communication interface and for the smart card interface. Its function is

switched with the SMIF bit in SCMR.

For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that data

reception ended abnormally due to a framing error in asynchronous mode.

Bit 4

FER Description

0 Receiving is in progress or has ended normally*1(Initial value)

Clearing conditions

The chip is reset or enters standby mode

Read FER when FER = 1, then write 0 in FER

1 A receive framing error occurred*2

Setting condition

The stop bit at the end of the recei ve data is checked and found to be 0

Notes: 1. Cleari ng the RE bit to 0 in SCR does not affect the FER flag, which retains its previous

value.

2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is

not checked. When a framing error occurs the SCI transfers the receive data into RDR

but does not set the RDRF flag. Serial receiving cannot continue while the FER flag is

set to 1. In synchronous mode, serial transmitting is also di sabled.

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For smart card interface (SMIF bit in SCMR set to 1): Indicates the status of the error signal

sent back from the receiving side during transmission. Framing errors are not detected in smart

card interface mode.

Bit 4

ERS Description

0 Normal reception, no error signal *(Initial value)

Clearing conditions

The chip is reset or enters standby mode

Read ERS when ERS = 1, then write 0 in ERS

1 An error signal has been sent from the receiving side indicating detecti on of a

parity error

Setting condition

The error signal is low when sampled

Note: *Clearing the TE bi t to 0 in SCR does not affect the ERS flag, which retains its previous

value.

Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error

in asynchronous mode.

Bit 3

PER Description

0 Receiving is in progress or has ended normally*1(Initial value)

Clearing conditions

The chip is reset or enters standby mode

Read PER when PER = 1, then write 0 in PER

1 A receive parity error occurred*2

Setting condition

The number of 1s in receive data, including the parity bit, does not match the

even or odd parity setti ng of O/

in SMR

Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous

value.

2. When a parity error occurs the SCI transfers the recei ve data into RDR but does not

set the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In

synchronous mode, serial transmitting is also disabled.

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Bit 2—Transmit End (TEND): The function of this bit differs for the normal serial

communication interface and for the smart card interface. Its function is switched with the SMIF

bit in SCMR.

For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that when

the last bit of a serial character was transmitted TDR did not contain valid transmit data, so

transmission has ended. The TEND flag is a read-only bit and cannot be written.

Bit 2

TEND Description

0 Transmission i s in progress

Clearing conditions

Read TDRE when TDRE = 1, then write 0 in TDRE

The DMAC wr ites data in TDR

1 End of transmissi on (Initial value)

Setting conditions

The chip is reset or enters standby mode

The TE bit in SCR is cleared to 0

TDRE is 1 when the last bit of a 1-byte serial transmit character is transmitted

For smart card interface (SMIF bit in SCMR set to 1): Indicates that when the last bit of a

serial character was transmitted TDR did not contain valid transmit data, so transmission has

ended. The TEND flag is a read-only bit and cannot be written.

Bit 2

TEND Description

0 Transmission i s in progress

Clearing conditions

Read TDRE when TDRE = 1, then write 0 in TDRE

The DMAC wr ites data in TDR

1 End of transmissi on (Initial value)

Setting conditions

The chip is reset or enters standby mode

The TE bit is cl eared to 0 in SCR and the FER/ERS bit is also cleared to 0

TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu (when GM = 0) or

1.0 etu (when GM = 1) after a 1-byte serial character is transmitted

Note: etu (Elementary time unit: the time for transfer of one bit)

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Bit 1—Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data

when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot

be written.

Bit 1

MPB Description

0 Multi processor bit value in receive data is 0*(Initial value)

1 Multi processor bit value in receive data is 1

Note: *If the RE bit in SCR is cleared to 0 when a multiprocessor format is selected, MPB retains

its previous value.

Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added

to transmit data when a multiprocessor format in selected for transmitting in asynchronous mode.

The MPBT bit setting is ignored in synchronous mode, when a multiprocessor format is not

selected, or when the SCI cannot transmit.

Bit 1

MPBT Description

0 Multi processor bit value in transmit data is 0 (Initial value)

1 Multi processor bit value in transmit data is 1

13.2.8 Bit Rate Register (BRR)

BRR is an 8-bit register that., together with the CKS1 and CKS0 bits in SMR that select the baud

rate generator clock source, determines the serial communication bit rate.

Bit

Initial value

Read/Write

R/W R/W R/W R/W R/W R/W R/W R/W

11111111

543210

The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby

mode. Each SCI channel has independent baud rate generator control, so different values can be

set in the three channels.

Table 13.3 shows examples of BRR settings in asynchronous mode. Table 13.4 shows examples

of BRR settings in synchronous mode.

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Table 13.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode

φφ

φ (MHz)

Bit Rate 2 2.097152 2.4576 3

(bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03

150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16

300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16

600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16

1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16

2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16

4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34

9600 0 6 –6.99 0 6 –2.48 0 7 0.00 0 9 –2.34

19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 –2.34

31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00

38400 0 1 –18.62 0 1 –14.67 0 1 0.00 ———

φφ

φ (MHz)

Bit Rate 3.6864 4 4.9152 5

(bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25

150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16

300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16

600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16

1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16

2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16

4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36

9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73

19200 0 5 0.00 0 6 –6.99 070.00 071.73

31250 ——— 0 3 0.00 0 4 –1.70 0 4 0.00

38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73

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φφ

φ (MHz)

Bit Rate 6 6.144 7.3728 8

(bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03

150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16

300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16

600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16

1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16

2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16

4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16

9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16

19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16

31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00

38400 0 4 –2.34 0 4 0.00 0 5 0.00 0 6 –6.99

φφ

φ (MHz)

Bit Rate 9.8304 10 12 12.288

(bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08

150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00

300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00

600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00

1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00

2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00

4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00

9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00

19200 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00

31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40

38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00

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φφ

φ (MHz)

Bit 13 14 14.7456 16 18 20

Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 230 –0.08 2 248 –0.17 3 64 0.70 3 70 0.03 3 79 –0.12 3 88 –0.25

150 2 168 0.16 2 181 0.16 2 191 0.00 2 207 0.16 2 233 0.16 3 64 0.16

300 2 84 –0.43 2 90 0.16 2 95 0.00 2 103 0.16 2 116 0.16 2 129 0.16

600 1 168 0.16 1 181 0.16 1 191 0.00 1 207 0.16 1 233 0.16 2 64 0.16

1200 1 84 –0.43 1 90 0.16 1 95 0.00 1 103 0.16 1 116 0.16 1 129 0.16

2400 0 168 0.16 0 181 0.16 0 191 0.00 0 207 0.16 0 233 0.16 1 64 0.16

4800 0 84 –0.43 0 90 0.16 0 95 0.00 0 103 0.16 0 116 0.16 0 129 0.16

9600 0 41 0.76 0 45 –0.93 0 47 0.00 0 51 0.16 0 58 –0.69 0 64 0.16

19200 0 20 0.76 0 22 –0.93 0 23 0.00 0 25 0.16 0 28 1.02 0 32 –1.36

31250 0 12 0.00 0 13 0.00 0 14 –1.70 0 15 0.00 0 17 0.00 0 19 0.00

38400 0 10 –3.82 0 10 3.57 0 11 0.00 0 12 0.16 0 14 –2.34 0 15 1.73

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Table 13.4 Examples of Bit Rates and BRR Settings in Synchronous Mode

Bit φ

φφ

φ (MHz)

Rate 2 4 8 1013161820

(bit/s) nN n N n N n N nN nN nN n N

110 3 70 — — — — — — —— —— —— — —

250 2 124 2 249 3 124 —— 3 202 3 249 —— — —

500 1 249 2 124 2 249 —— 3 101 3 124 3 140 3 155

1k 1 124 1 249 2 124 —— 2 202 2 249 3 69 3 77

2.5k 0 199 1 99 1 199 1 249 2 80 2 99 2 112 2 124

5k 0 99 0 199 1 99 1 124 1 162 1 199 1 224 1 249

10k 0 49 0 99 0 199 0 249 1 80 1 99 1 112 1 124

25k 0 19 0 39 0 79 0 99 0 129 0 159 0 179 0 199

50k 0 9 0 19 0 39 0 49 0 64 0 79 0 89 0 99

100k 0 4 0 9 0 19 0 24 —— 0390440 49

250k 0 1 0 3 0 7 0 9 0 12 0 15 0 17 0 19

500k 0 0*01 03 04 —— 07 08 0 9

1M 0 0*01 —— —— 03 04 0 4

2M 0 0*—— —— 01 —— — —

2.5M —— 00*—— —— —— — —

4M 0 0*—— — —

Note: Settings with an error of 1% or less are recommended.

Legend

Blank : No setting available

— : Setting possible, but error occurs

* : Continuous transmission/reception not possi ble

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The BRR setting is calculated as follows:

Asynchronous mode:

N = 64 × 2

2n–1

× B× 10

– 1

Synchronous mode:

N = 8 × 2

2n–1

× B× 10

– 1

B: Bit rate (bit/s)

N: BRR setting for baud rate generator (0

≤

255)

φ: System clock frequency (MHz)

n: Baud rate generator clock source (n = 0, 1, 2, 3)

(For the clock sources and values of n, see the following table.)

SMR Settings

n Clock Source CKS1 CKS0

0φ00

1φ/4 0 1

2φ/16 1 0

3φ/64 1 1

The bit rate error in asynchronous mode is calculated as follows:

Error (%) = (N + 1) × B × 64 × 22n–1

– 1 × 100

φ × 106

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Table 13.5 shows the maximum bit rates in asynchronous mode for various system clock

frequencies. Table 13.6 and 13.7 shows the maximum bit rates with external clock input.

Table 13.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode)

Settings

φφ

φ (MHz) Maximum Bit Rate (bit/s) n N

2 62500 0 0

2.097152 65536 0 0

2.4576 76800 0 0

3 93750 0 0

3.6864 115200 0 0

4 125000 0 0

4.9152 153600 0 0

5 156250 0 0

6 187500 0 0

6.144 192000 0 0

7.3728 230400 0 0

8 250000 0 0

9.8304 307200 0 0

10 312500 0 0

12 375000 0 0

12.288 384000 0 0

14 437500 0 0

14.7456 460800 0 0

16 500000 0 0

17.2032 537600 0 0

18 562500 0 0

20 625000 0 0

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Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)

φφ

φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)

2 0.5000 31250

2.097152 0.5243 32768

2.4576 0.6144 38400

3 0.7500 46875

3.6864 0.9216 57600

4 1.0000 62500

4.9152 1.2288 76800

5 1.2500 78125

6 1.5000 93750

6.144 1.5360 96000

7.3728 1.8432 115200

8 2.0000 125000

9.8304 2.4576 153600

10 2.5000 156250

12 3.0000 187500

12.288 3.0720 192000

14 3.5000 218750

14.7456 3.6864 230400

16 4.0000 250000

17.2032 4.3008 268800

18 4.5000 281250

20 5.0000 312500

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Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)

φφ

φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)

2 0.3333 333333.3

4 0.6667 666666.7

6 1.0000 1000000.0

8 1.3333 1333333.3

10 1.6667 1666666.7

12 2.0000 2000000.0

14 2.3333 2333333.3

16 2.6667 2666666.7

18 3.0000 3000000.0

20 3.3333 3333333.3

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13.3 Operation

13.3.1 Overview

The SCI can carry out serial communication in two modes: asynchronous mode in which

synchronization is achieved character by character, and synchronous mode in which

synchronization is achieved with clock pulses. A smart card interface is also supported as a serial

communication function for an IC card interface.

Selection of asynchronous or synchronous mode and the transmission format for the normal serial

communication interface is made in SMR, as shown in table 13.8. The SCI clock source is

selected by the C/

bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13.9.

For details of the procedures for switching between LSB-first and MSB-first mode and inverting

the data logic level, see section 14.2.1, Smart Card Mode Register (SCMR).

For selection of the smart card interface format, see section 14.3.3, Data Format.

Asynchronous Mode

• Data length is selectable: 7 or 8 bits

• Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These

selections determine the communication format and character length.

• In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break

state.

• An internal or external clock can be selected as the SCI clock source.

 When an internal clock is selected, the SCI operates using the on-chip baud rate generator,

and can output a serial clock signal with a frequency matching the bit rate.

 When an external clock is selected, the external clock input must have a frequency 16

times the bit rate. (The on-chip baud rate generator is not used.)

Synchronous Mode

• The communication format has a fixed 8-bit data length.

• In receiving, it is possible to detect overrun errors.

• An internal or external clock can be selected as the SCI clock source.

 When an internal clock is selected, the SCI operates using the on-chip baud rate generator,

and can output a serial clock signal to external devices.

 When an external clock is selected, the SCI operates on the input serial clock. The on-chip

baud rate generator is not used.

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Smart Card Interface

• One frame consists of 8-bit data and a parity bit.

• In transmitting, a guard time of at least two elementary time units (2 etu) is provided between

the end of the parity bit and the start of he next frame. (An elementary time unit is the time

required to transmit one bit.)

• In receiving, if a parity error is detected, a low error signal level is output for 1 etu, beginning

10.5 etu after the start bit..

• In transmitting, if an error signal is received, the same data is automatically transmitted again

after at least 2 etu.

• Only asynchronous communication is supported. There is no synchronous communication

function.

For details of smart card interface operation, see section 14, Smart Card Interface.

Table 13.8 SMR Settings and Serial Communication Formats

SMR Settings SCI Co mmunication Format

Bit 7

Bit 6

CHR Bit 2

MP Bit 5

PE Bit 3

STOP Mode Data

Length

Multi-

pro-

cessor

Bit Parity

Bit Stop Bit

Length

0 0 0 0 0 8-bit data Absent Absent 1 bit

1 2 bits

Asyn-

Chronous

mode Present 1 bit

1 2 bits

1 0 0 7-bit data Absent 1 bit

1 2 bits

1 0 Present 1 bit

1 2 bits

01—0 8-bit data Present Absent 1 bit

—1 2 bits

1 — 0 7-bit data 1 bit

— 1

Asyn-

chronous

mode (multi-

processor

format) 2 bits

1———— Syn-

chronous

mode

8-bit data Absent None

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Table 13.9 SMR and SCR Settings and SCI Clock Source Selection

SMR SCR Setting SCI Transmit/Receive clock

Bit 7

Bit 1

CKE1 Bit 0

CKE0 Mode Clo ck Source SCK Pin Function

0 0 0 Internal SCI does not use the SCK pin

Asynchronous

mode Outputs clock with frequency matching the

bit rate

1 0 External Inputs clock with frequency 16 times the bit

1rate

1 0 0 Internal Outputs the serial clock

Synchronous

mode

1 0 External Inputs the serial clock

13.3.2 Operation in Asynchronous Mode

In asynchronous mode, each transmitted or received character begins with a start bit and ends

with one or two stop bits. Serial communication is synchronized one character at a time.

The transmitting and receiving sections of the SCI are independent, so full-duplex communication

is possible. The transmitter and the receiver are both double-buffered, so data can be written and

read while transmitting and receiving are in progress, enabling continuous transmitting and

receiving.

Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous

serial communication the communication line is normally held in the mark (high) state. The SCI

monitors the line and starts serial communication when the line goes to the space (low) state,

indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit

(high or low), and one or two stop bits (high), in that order.

When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit.

The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit

rate. Receive data is latched at the center of each bit.

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1D0 D1 D2 D3 D4 D5 D6 D7 0/1 1

Idle (mark) stat

(MSB)(LSB)

Serial

data Start

bit

1 bit

Transmit or receive data

7 or 8 bits

One unit of data (character or frame)

1 bit,

none

Parity

bit

1 or 2 bits

Stop bit(s)

Figure 13.2 Data Format in Asynchronous Communication

(Example: 8-Bit Data with Parity and 2 Stop Bits)

Communication Formats: Table 13.10 shows the 12 communication formats that can be

selected in asynchronous mode. The format is selected by settings in SMR.

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Table 13.10 Serial Communication Formats (Asynchronous Mode)

7-bit data

STOP STOP

MPB

STOPMPB

STOP

STOP STOP

SMR Settings

CHR PE MP STOP

00 0 0

00 0 1

01 0 0

01 0 1

10 0 0

10 0 1

11 0 0

11 0 1

0—10

0 — 11

1 — 10

1 — 11

Serial Communication Format and Frame Length

123456789101112

STOP

8-bit data

STOP

8-bit data

STOP

7-bit data

8-bit data

STOP STOP

MPB

8-bit data

7-bit data

STOPSTOP

STOP

STOPMPB

Legend

S: St art bit

STOP: Sto p bit

P: Parity bit

MPB: Multiprocessor bit

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Clock: An internal clock generated by the on-chip baud rate generator or an external clock input

from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected

by the C/

bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source

selection, see table 13.9.

When an external clock is input at the SCK pin, it must have a frequency 16 times the desired bit

rate.

When the SCI is operated on an internal clock, it can output a clock signal at the SCK pin. The

frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure

13.3 so that the rising edge of the clock occurs at the center of each transmit data bit.

D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1

1frame

Figure 13.3 Phase Relationship between Output Clock and Serial Data

(Asynchronous Mode)

Transmitting and Receiving Data:

• SCI Initialization (Asynchronous Mode): Before transmitting or receiving data, clear the TE

and RE bits to 0 in SCR, then initialize the SCI as follows.

When changing the communication mode or format, always clear the TE and RE bits to 0

before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and

initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and

ORER flags, or RDR, which retain their previous contents.

When an external clock is used the clock should not be stopped during initialization or

subsequent operation, since operation will be unreliable in this case.

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Figure 13.4 shows a sample flowchart for initializing the SCI.

Start of initialization

Set value in BRR

Select communication format

in SMR

1-bit interval elapsed?

Wait

(4)

(3)

(2)

(1)

Yes

Note: In simultaneous transmitting and receiving, the TE and RE bits should be cleared to

0 or set to 1 simultaneously.

Set TE or RE bit to 1 in SCR

Set the RIE, TIE, TEIE, and

MPIE bits

Set CKE1 and CKE0 bits in SCR

(leaving TE and RE bits

cleared to 0)

Clear TE and RE bits

to 0 in SCR

(1)

(2)

(3)

(4)

Set the clock source in SCR. Clear the

RIE, TIE, TEIE, MPIE, TE, and RE bits to

0. If clock output is selected in

asynchronous mode, clock output starts

immediately after the setting is made in

SCR.

Select the communication format in SMR.

Write the value corresponding to the bit

rate in BRR.

This step is not necessary when an

external clock is used.

Wait for at least the interval required to

transmit or receive one bit, then set the

TE or RE bit to 1 in SCR. Set the RIE,

TIE, TEIE, and MPIE bits as necessary.

Setting the TE or RE bit enables the SCI

to use the TxD or RxD pin.

Figure 13.4 Sample Flowchart for SCI Initialization

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• Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for

transmitting serial data and indicates the procedure to follow.

Yes

<End>

Clear TE bit to 0 in SCR

Clear DR bit to 0 and set

DDR bit to 1

TEND = 1 No

Output break signal? No

Read TEND flag in SSR

All data transmitted? No

TDRE = 1

Yes

Read TDRE flag in SSR

(3)

Initialize

(4)

Write transmit data in TDR

and clear TDRE flag to 0 in SSR

(1)

(2)

(3)

(4)

Start transmitting

(1)

(2)

Yes

SCI initialization:

the transmit data output function of the TxD pin is

selected automatically.

SCI status check and transmit data write:

read SSR and check that the TDRE flag is set to 1,

then write transmit data in TDR and clear the TDRE

flag to 0.

To continue transmitting serial data:

after checking that the TDRE flag is 1, indicating that

data can be written, write data in TDR, then clear the

TDRE flag to 0. When the DMAC is activated by a

transmit-data-empty interrupt request (TXI) to write

data in TDR, the TDRE flag is checked and cleared

automatically.

To output a break signal at the end of serial

transmission:

set the DDR bit to 1 and clear the DR bit to 0, then

clear the TE bit to 0 in SCR.

Figure 13.5 Sample Flowchart for Transmitting Serial Data

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 505 of 910

REJ09B0258-0300

In transmitting serial data, the SCI operates as follows:

• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI

recognizes that TDR contains new data, and loads this data from TDR into TSR.

• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty

interrupt (TXI) at this time.

Serial transmit data is transmitted in the following order from the TxD pin:

 Start bit: One 0 bit is output.

 Transmit data: 7 or 8 bits are output, LSB first.

 Parity bit or multiprocessor bit: One parity bit (even or odd parity),or one multiprocessor

bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can

also be selected.

 Stop bit(s): One or two 1 bits (stop bits) are output.

 Mark state: Output of 1 bits continues until the start bit of the next transmit data.

• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI

loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the

next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop

bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a

transmit-end interrupt (TEI) is requested at this time

Figure 13.6 shows an example of SCI transmit operation in asynchronous mode.

0/1D0 D1 D7 0/1 1

Start bit

0D0D1 D7 1

Data Parity

bit Stop

bit Start

bit Data Parity

bit Stop

bit

TDRE

TEND

Idle state

(mark state)

TEI interrupt

request

TXI interrupt

request

TXI interrupt handler

writes data in TDR and

clears TDRE flag to 0

TXI interrupt

request

1 frame

Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode

(8-Bit Data with Parity and One Stop Bit)

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 506 of 910

REJ09B0258-0300

• Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for

receiving serial data and indicates the procedure to follow.

Yes

<End>

All data received?

(2)

(1)

Initialize

(4)

(5)

(1)

(2)(3)

(4)

(5)

Start receiving

Error handling

Read ORER, PER, and FER

flags in SSR

PER⁄FER⁄OPER = 1

RDRF = 1

Read RDRF flag in SSR

(continued on next page)

Read receive data from RDR, and

clear RDRF flag to 0 in SSR

Yes

(3)

SCI initialization:

the receive data input function of the RxD

pin is selected automatically.

Receive error handling and break detection:

if a receive error occurs, read the ORER,

PER, and FER flags in SSR to identify the

error. After executing the necessary error

handling, clear the ORER, PER, and FER

flags all to 0. Receiving cannot resume if

any of these flags remains set to 1. When a

framing error occurs, the RxD pin can be

read to detect the break state.

SCI status check and receive data read:

read SSR, check that the RDRF flag is set

to 1, then read receive data from RDR and

clear the RDRF flag to 0. Notification that

the RDRF flag has changed from 0 to 1 can

also be given by the RXI interrupt.

To continue receiving serial data:

check the RDRF flag, read RDR, and clear

the RDRF flag to 0 before the stop bit of the

current frame is received. When the DMAC

is activated by a receive-data-full interrupt

request (RXI) to read RDR, the RDRF flag

is cleared automatically.

Clear RE bit to 0 in SCR

Figure 13.7 Sample Flowchart for Receiving Serial Data (1)

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 507 of 910

REJ09B0258-0300

Yes

<End>

Error handling

Yes

ORER = 1

Overrun error handling

FER = 1

Break?

Framing error handling Clear RE bit to 0 in SCR

PER = 1

Parity error handling

Clear ORER, PER, and FER flags

to 0 in SSR

(3)

Figure 13.7 Sample Flowchart for Receiving Serial Data (2)

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 508 of 910

REJ09B0258-0300

In receiving, the SCI operates as follows:

• The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI

synchronizes internally and starts receiving.

• Receive data is stored in RSR in order from LSB to MSB.

• The parity bit and stop bit are received.

After receiving these bits, the SCI carries out the following checks:

 Parity check: The number of 1s in the receive data must match the even or odd parity

setting of in the O/

bit in SMR.

 Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first is

checked.

 Status check: The RDRF flag must be 0, indicating that the receive data can be transferred

from RSR into RDR.

If these all checks pass, the RDRF flag is set to 1 and the received data is stored in RDR. If

one of the checks fails (receive error*), the SCI operates as shown in table 13.11.

Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag is

not set to 1. Be sure to clear the error flags to 0.

• When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt

(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also

set to 1, a receive-error interrupt (ERI) is requested.

Table 13.11 Receive Error Conditions

Receive Erro r Abbreviation Condition Data Transfer

Overrun error ORER Receiving of next data ends whi le

RDRF flag is still set to 1 in SSR Receive data is not transferred

from RSR to RDR

Framing error FER Stop bi t is 0 Receive data is transferred from

RSR to RDR

Parity error PER Parity of received data differs from

even/odd parity setti ng in SMR Receive data is transferred from

RSR to RDR

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 509 of 910

REJ09B0258-0300

Figure 13.8 shows an example of SCI receive operation in asynchronous mode.

0/1D0 D1 D7 0/1 1

Start

bit

0D0D1 D7 1

Data Data

Parity

bit Parity

bit

Stop

bit Stop

bit

Start

bit

RDRF

FER

Idle (mark) state

Framing error,

ERI request

RXI request RXI interrupt handler

reads data in RDR and

clears RDRF flag to 0

1 frame

Figure 13.8 Example of SCI Receive Operation

(8-Bit Data with Parity and One Stop Bit)

13.3.3 Multiprocessor Communication

The multiprocessor communication function enables several processors to share a single serial

communication line. The processors communicate in asynchronous mode using a format with an

additional multiprocessor bit (multiprocessor format).

In multiprocessor communication, each receiving processor is addressed by an ID. A serial

communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a

data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending

cycles.

The transmitting processor stars by sending the ID of the receiving processor with which it wants

to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor

sends transmit data with the multiprocessor bit cleared to 0.

Receiving processors skip incoming data until they receive data with the multiprocessor bit set to

1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the

data with their IDs. Processors with IDs not matching the received data skip further incoming

data until they again receive data with the multiprocessor bit set to 1. Multiple processors can

send and receive data in this way.

Figure 13.9 shows an example of communication among different processors using a

multiprocessor format.

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 510 of 910

REJ09B0258-0300

Communication Formats: Four formats are available. Parity bit settings are ignored when a

multiprocessor format is selected. For details see table 13.10.

Clock: See the description of asynchronous mode.

(ID=04)(ID=01) (ID=02) (ID=03)

Transmitting

processor

Receiving

processor B

Receiving

processor A Receiving

processor C Receiving

processor D

H'01 (MPB=1)

Serial data H'AA (MPB=0)

Serial communication line

ID-sending cycle:

receiving processor address Data-sending cycle:

data sent to receiving processor

specified by ID

Legend

MPB : Multiprocessor bit

Figure 13.9 Example of Communication among Processors using Multiprocessor Format

(Sending Data H'AA to Receiving Processor A)

Transmitting and Receiving Data:

• Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for

transmitting multiprocessor serial data and indicates the procedure to follow.

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 511 of 910

REJ09B0258-0300

TEND = 1 No

Read TEND flag in SSR

Yes

<End>

Clear TE bit to 0 in SCR

Clear DR bit to 0 and set DDR to 1

(2)

(1)

Initialize

(3)

(4)

(1)

(2)

(3)

(4)

TDRE = 1

All data transmitted?

Read TDRE flag in SSR

Start transmitting

Write transmit data in TDR

and set MPBT bit in SSR

Clear TDRE flag to 0

Output break signal?

SCI initialization:

the transmit data output function of the TxD pin

is selected automatically.

SCI status check and transmit data write:

read SSR, check that the TDRE flag is 1, then

write transmit data in TDR. Also set the MPBT

flag to 0 or 1 in SSR. Finally, clear the TDRE

flag to 0.

To continue transmitting serial data:

after checking that the TDRE flag is 1,

indicating that data can be written, write data

in TDR, then clear the TDRE flag to 0. When

the DMAC is activated by a transmit-data-

empty interrupt request (TXI) to write data in

TDR, the TDRE flag is checked and cleared

automatically.

To output a break signal at the end of serial

transmission:

set the DDR bit to 1 and clear the DR bit to 0,

then clear the TE bit to 0 in SCR.

Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 512 of 910

REJ09B0258-0300

In transmitting serial data, the SCI operates as follows:

• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI

recognizes that TDR contains new data, and loads this data from TDR into TSR.

• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty

interrupt (TXI) at this time.

Serial transmit data is transmitted in the following order from the TxD pin:

 Start bit: One 0 bit is output.

 Transmit data: 7 or 8 bits are output, LSB first.

 Multiprocessor bit: One multiprocessor bit (MPBT value) is output.

 Stop bit(s): One or two 1 bits (stop bits) are output.

 Mark state: Output of 1 bits continues until the start bit of the next transmit data.

• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI

loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the

next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop

bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a

transmit-end interrupt (TEI) is requested at this time

Figure 13.11 shows an example of SCI transmit operation using a multiprocessor format.

D0 D1 D7 0/1 1

Start

bit

0D0 D1 D7 0/1 1

Data Multi-

processor

bit Stop

bit Start

bit Data Multi-

processor

bit Stop

bit

TDRE

TEND

Idle (mark)

state

TEI interrupt

request

TXI interrupt

request

TXI interrupt handler

writes data in TDR and

clears TDRE flag to 0

TXI interrupt

request

1 frame

Figure 13.11 Example of SCI Transmit Operation

(8-Bit Data with Multiprocessor Bit and One Stop Bit)

• Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving

multiprocessor serial data and indicates the procedure to follow.

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 513 of 910

REJ09B0258-0300

Read RDRF flag in SSR

Yes

Read ORER and FER flags

in SSR

(3)

(1)

(2)

(4)

(1)

(2)

(3)

(4)

(5)

RDRF = 1

FER⁄ORER = 1

Start receiving

Own ID?

<End>

RDRF = 1

Read RDRF flag in SSR

Finished receiving?

Read receive data from RDR

Yes

Clear RE bit to 0 in SCR

(5)

Error handling

(continued on next page)

SCI initialization:

the receive data input function of the

RxD pin is selected automatically.

ID receive cycle:

set the MPIE bit to 1 in SCR.

SCI status check and ID check:

read SSR, check that the RDRF flag

is set to 1, then read data from RDR

and compare it with the processor's

own ID. If the ID does not match, set

the MPIE bit to 1 again and clear the

RDRF flag to 0. If the ID matches,

clear the RDRF flag to 0.

SCI status check and data receiving:

read SSR, check that the RDRF flag

is set to 1, then read data from RDR.

Receive error handling and break

detection:

if a receive error occurs, read the

ORER and FER flags in SSR to

identify the error. After executing the

necessary error handling, clear the

ORER and FER flags both to 0.

Receiving cannot resume while either

the ORER or FER flag remains set to

1. When a framing error occurs, the

RxD pin can be read to detect the

break state.

Set MPIE bit to 1 in SCR

Read ORER and FER flags

in SSR

Read RDRF flag in SSR

Initialize

Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1)

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 514 of 910

REJ09B0258-0300

Yes

<End>

Clear ORER, PER, and FER

flags to 0 in SSR

Clear RE bit to 0 in SCR

(5)

Error handling

ORER = 1

FER = 1

Break?

Overrun error handling

Framing error handling

Yes

Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2)

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 515 of 910

REJ09B0258-0300

Figure 13.13 shows an example of SCI receive operation using a multiprocessor format.

ID2 Data2

Idle (mark)

state

Not own ID, so MPIE

bit is set to 1 again

a. Own ID does not match data

b. Own ID matches data

D0 D1 D7 1

Start

bit Start

bit

Stop

bit Stop

bit

0D0 D1 D7 011

Data (ID1) Data (data1)

Start

bit

Stop

bit Stop

bit

Data (data1)

MPIE

Idle (mark)

state

MPB

RDRF

RDR value

RXI interrupt

request

(multiprocessor

interrupt)

MPB detection

MPIE = 0 RXI interrupt handler reads

RDR data and clears

RDRF flag to 0

No RXI interrupt

request, RDR not

updated

ID1

MPB

D0 D1 D7 1

Start

bit

0D0 D1 D7 011

Data (ID2)

MPIE

MPB

RDRF

RXI interrupt

request

(multiprocessor

interrupt)

RXI interrupt handler

reads RDR data and

clears RDRF flag to 0

Own ID, so receiving

continues, with data

received by RXI

interrupt handler

MPB

ID1

MPIE bit is set to

1 again

MPB detection

MPIE = 0

Figure 13.13 Example of SCI Receive Operation

(8-Bit Data with Multiprocessor Bit and One Stop Bit)

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 516 of 910

REJ09B0258-0300

13.3.4 Synchronous Operation

In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses.

This mode is suitable for high-speed serial communication.

The SCI transmitter and receiver share the same clock but are otherwise independent, so full-

duplex communication is possible. The transmitter and the receiver are also double-buffered, so

continuous transmitting or receiving is possible by reading or writing data while transmitting or

receiving is in progress.

Figure 13.14 shows the general format in synchronous serial communication.

Don't care

One unit (character or frame) of transfer data

MSB

Bit 0 Bit 1 Bit 3 Bit 2 Bit 4 Bit 5 Bit 6 Bit 7

LSB

Don't care

Serial clock

Serial data

Note: * Hi

h except in continuous transmittin

or receivin

Figure 13.14 Data Format in Synchronous Communication

In synchronous serial communication, each data bit is placed on the communication line from one

falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.

In each character, the serial data bits are transferred in order from LSB (first) to MSB (last).

After output of the MSB, the communication line remains in the state of the MSB. In

synchronous mode the SCI receives data by synchronizing with the rise of the serial clock.

Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit

can be added.

Clock: An internal clock generated by the on-chip baud rate generator or an external clock input

from the SCK pin can be selected by means of the C/

bit in SMR and the CKE1 and CKE0 bits

in SCR. See table 13.6 for details of SCI clock source selection.

When the SCI operates on an internal clock, it outputs the clock source at the SCK pin. Eight

clock pulses are output per transmitted or received character. When the SCI is not transmitting or

receiving, the clock signal remains in the high state. If receiving in single-character units is

required, an external clock should be selected.

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 517 of 910

REJ09B0258-0300

Transmitting and Receiving Data:

• SCI Initialization (Synchronous Mode): Before transmitting or receiving data, clear the TE

and RE bits to 0 in SCR, then initialize the SCI as follows.

When changing the communication mode or format, always clear the TE and RE bits to 0

before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and

initializes TSR. Note that clearing RE to 0, however, does not initialize the RDRF, PER, and

ORE flags, or RDR, which retain their previous contents.

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 518 of 910

REJ09B0258-0300

Figure 13.15 shows a sample flowchart for initializing the SCI.

(4)

(3)

(2)

(1)

Start of initialization

Yes

Wait

1-bit interval elapsed?

Set value in BRR

Clear TE and RE bits to 0 in SCR

Select communication format

in SMR

Set RIE, TIE, TEIE, MPIE, CKE1,

and CKE0 bits in SCR (leaving

TE and RE bits cleared to 0)

Set TE or RE bit to 1 in SCR

Set RIE, TIE, TEIE, and MPIE

bits as necessary

(1)

(2)

(3)

(4)

Note: *

Set the clock source in SCR. Clear the RIE,

TIE, TEIE, MPIE, TE, and RE bits to 0.*

Select the communication format in SMR.

Write the value corresponding to the bit rate in

BRR.

This step is not necessary when an external

clock is used.

Wait for at least the interval required to transmit

or receive one bit, then set the TE or RE bit to

1 in SCR.* Set the RIE, TIE, TEIE, and MPIE

bits as necessary. Setting the TE or RE bit

enables the SCI to use the TxD or RxD pin.

In simultaneous transmitting and receiving,

the TE and RE bits should be cleared to 0 or

set to 1 simultaneously.

Figure 13.15 Sample Flowchart for SCI Initialization

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 519 of 910

REJ09B0258-0300

• Transmitting Serial Data (Synchronous Mode): Figure 13.16 shows a sample flowchart for

transmitting serial data and indicates the procedure to follow.

<End>

Yes

Clear TE bit to 0 in SCR

Yes

(2)

(1)

Initialize

(3)

(1)

(2)

(3)

Start transmitting

TDRE = 1

All data transmitted?

Read TEND flag in SSR

Read TDRE flag in SSR

Write transmit data in TDR

and clear TDRE flag to 0 in SSR

TEND = 1

SCI initialization: the transmit data output

function of the TxD pin is selected

automatically.

SCI status check and transmit data write:

read SSR, check that the TDRE flag is 1, then

write transmit data in TDR and clear the

TDRE flag to 0.

To continue transmitting serial data: after

checking that the TDRE flag is 1, indicating

that data can be written, write data in TDR,

then clear the TDRE flag to 0. When the

DMAC is activated by a transmit-data-empty

interrupt request (TXI) to write data in TDR,

the TDRE flag is checked and cleared

automatically.

Figure 13.16 Sample Flowchart for Serial Transmitting

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 520 of 910

REJ09B0258-0300

In transmitting serial data, the SCI operates as follows.

• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI

recognizes that TDR contains new data, and loads this data from TDR into TSR.

• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty

interrupt (TXI) at this time.

If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock

source is selected, the SCI outputs data in synchronization with the input clock. Data is

output from the TxD pin n order from LSB (bit 0) to MSB (bit 7).

• The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the

SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the

TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB (bit

7), holds the TxD pin in the MSB state. If the TEIE bit is set to 1 in SCR, a transmit-end

interrupt (TEI) is requested at this time

• After the end of serial transmission, the SCK pin is held in a constant state.

Figure 13.17 shows an example of SCI transmit operation.

Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

Serial clock

Serial data

1 frame

TXI interrupt

request TXI interrupt handler

writes data in TDR

and clears TDRE

flag to 0

TXI interrupt

request TEI interrupt

request

Transmit direction

TEND

TDRE

Figure 13.17 Example of SCI Transmit Operation

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 521 of 910

REJ09B0258-0300

• Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for

receiving serial data and indicates the procedure to follow. When switching from

asynchronous to synchronous mode. make sure that the ORER, PER, and FER flags are

cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both

transmitting and receiving will be disabled.

Yes

<End>

Clear RE bit to 0 in SCR

Finished receiving?

(2)

(1)

Initialize

(4)

(3)

(5)

(1)

(2)(3)

(4)

(5)

Start receiving

Error handling

ORER = 1

RDRF = 1

Read RDRF flag in SSR

Read ORER flag in SSR

(continued on next page)

Read receive data from

RDR, and clear RDRF

flag to 0 in SSR

Yes

SCI initialization: the receive data

input function of the RxD pin is

selected automatically.

Receive error handling: if a receive

error occurs, read the ORER flag in

SSR, then after executing the

necessary error handling, clear the

ORER flag to 0. Neither transmitting

nor receiving can resume while the

ORER flag remains set to 1.

SCI status check and receive data

read: read SSR, check that the RDRF

flag is set to 1, then read receive data

from RDR and clear the RDRF flag to

0. Notification that the RDRF flag

has changed from 0 to 1 can also be

given by the RXI interrupt.

To continue receiving serial data:

check the RDRF flag, read RDR, and

clear the RDRF flag to 0 before the

MSB (bit 7) of the current frame is

received. When the DMAC is

activated by a receive-data-full

interrupt request (RXI) to read RDR,

the RDRF flag is cleared

automatically.

Figure 13.18 Sample Flowchart for Serial Receiving (1)

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 522 of 910

REJ09B0258-0300

<End>

(3)

Error handling

Overrun error handling

Clear ORER flag to 0 in SSR

Figure 13.18 Sample Flowchart for Serial Receiving (2)

In receiving, the SCI operates as follows:

• The SCI synchronizes with serial clock input or output and synchronizes internally.

• Receive data is stored in RSR in order from LSB to MSB.

After receiving the data, the SCI checks that the RDRF flag is 0, so that receive data can be

transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received

data is stored in RDR. If the checks fails (receive error), the SCI operates as shown in table

13.11.

When a receive error has been identified in the error check, subsequent transmit and receive

operations are disabled.

• When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt

(RXI) is requested. If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1, a

receive-error interrupt (ERI) is requested.

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 523 of 910

REJ09B0258-0300

Figure 13.19 shows an example of SCI receive operation.

Serial clock

Serial data

RXI interrupt handler

reads data in RDR and

clears RDRF flag to 0

RXI interrupt

request

RXI interrupt

request Overrun error,

ERI interrupt

request

ORER

RDRF

Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

1 frame

Figure 13.19 Example of SCI Receive Operation

Section 13 Serial Communication Interface

Rev. 3.00 Sep 14, 2005 page 524 of 910

REJ09B0258-0300

• Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 13.20 shows a

sample flowchart for transmitting and receiving serial data simultaneously and indicates the

procedure to follow.

Yes

<End>

Read receive data from RDR, and

clear RDRF flag to 0 in SSR

Yes

(2)

(1)

Initialize

(3)

(5)

(4)

(1)

(2)

(3)

(4)

(5)

Start of transmitting and receiving

Error handling

TDRE = 1

ORER = 1

Read ORER flag in SSR

Read RDRF flag in SSR

Read TDRE flag in SSR

Write transmit data in TDR and

clear TDRE flag to 0 in SSR

Yes

End of transmitting

and receiving?

Clear TE and RE bits to 0 in SCR

RDRF = 1

Yes

SCI initialization: the transmit data output function of the

TxD pin and the read data input function of the RxD pin

are selected, enabling simultaneous transmitting and

receiving.

SCI status check and transmit data write: read SSR, check

that the TDRE flag is 1, then write transmit data in TDR

and clear the TDRE flag to 0.

Notification that the TDRE flag has changed from 0 to 1

can also be given by the TXI interrupt.

Receive error handling: if a receive error occurs, read the

ORER flag in SSR, then after executing the necessary

error handling, clear the ORER flag to 0.

Neither transmitting nor receiving can resume while the

ORER flag remains set to 1.

SCI status check and receive data read: read SSR, check

that the RDRF flag is 1, then read receive data from RDR

and clear the RDRF flag to 0. Notification that the RDRF

flag has changed from 0 to 1 can also be given by the RXI

interrupt.

To continue transmitting and receiving serial data: check

the RDRF flag, read RDR, and clear the RDRF flag to 0

before the MSB (bit 7) of the current frame is received.

Also check that the TDRE flag is set to 1, indicating that

data can be written, write data in TDR, then clear the

TDRE flag to 0 before the MSB (bit 7) of the current frame

is transmitted. When the DMAC is activated by a transmit-

data-empty interrupt request (TXI) to write data in TDR,

the TDRE flag is checked and cleared automatically.

When the DMAC is activated by a receive-data-full

interrupt request (RXI) to read RDR, the RDRF flag is

cleared automatically.

Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, clear both the TE bit

and the RE bit to 0, then set both bits to 1 simultaneously.

Figure 13.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving

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13.4 SCI Interrupts

The SCI has four interrupt request sources: the transmit-end interrupt (TEI), receive-error

interrupt (ERI), receive-data-full interrupt (RXI), and transmit-data-empty interrupt (TXI). Table

13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled or

disabled by the TIE, RIE, and TEIE bits in SCR. Each interrupt request is sent separately to the

interrupt controller.

A TXI interrupt is requested when the TDRE flag is set to 1 in SSR. A TEI interrupt is requested

when the TEND flag is set to 1 in SSR. A TXI interrupt request can activate the DMAC to

transfer data. Data transfer by the DMAC automatically clears the TDRE flag to 0. A TEI

interrupt request cannot activate the DMAC.

An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is

requested when the ORER, PER, or FER flag is set to 1 in SSR. An RXI interrupt can activate the

DMAC to transfer data. Data transfer by the DMAC automatically clears the RDRF flag to 0. An

ERI interrupt request cannot activate the DMAC.

The DMAC can be activated by interrupts from SCI channel 0.

Table 13.12 SCI Interrupt Sources

Interrupt Source Description Priority

ERI Receive error (ORER, FER, or PER) High

RXI Rece ive dat a register full (RDRF)

TXI Transmit data register empty (TDRE)

TEI Transmit end (TEND) Low

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13.5 Usage Notes

13.5.1 Notes on Use of SCI

Note the following points when using the SCI.

TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of

transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from

TDR to TSR.

Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in

TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not

yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the

TDRE flag is set to 1.

Simultaneous Multiple Receive Errors: Table 13.13 shows the state of the SSR status flags

when multiple receive errors occur simultaneously. When an overrun error occurs the RSR

contents are not transferred to RDR, so receive data is lost.

Table 13.13 SSR Status Flags and Transfer of Receive Data

SSR Status Flags Receive Data

Transfer

RDRF ORER FER PER RSR →

→→

→ RDR Receive Errors

11 0 0 × Overrun error

00 1 0 Framing error

00 0 1 Parity error

11 1 0 × Overrun error +

framing error

11 0 1 × Overrun error +

parity error

00 1 1 Framing error +

parity error

11 1 1 × Overrun error +

framing error +

parity error

Notes: : Receive da t a is transferred from RSR to RDR.

× :Receive data is no t transferred from RSR to RDR.

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Break Detection and Processing: Break signals can be detected by reading the RxD pin directly

when a framing error (FER) is detected. In the break state the input from the RxD pin consists of

all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the

SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.

Sending a Break Signal: The input/output condition and level of the TxD pin are determined by

DR and DDR bits. This feature can be used to send a break signal.

After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE

bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR

bits should therefore be set to 1 beforehand.

To send a break signal during serial transmission, clear the DR bit to 0 , then clear the TE bit to 0.

When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the

TxD pin becomes an input/output outputting the value 0.

Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive

error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE

flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note

that clearing the RE bit to 0 does not clear the receive error flags to 0.

Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In

asynchronous mode the SCI operates on a base clock with 16 times the bit rate frequency. In

receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the

base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See figure

13.21.

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15 0

Internal base clock

8 clocks

Receive data

(RxD)

Synchronization

sampling timing

Data sampling

timing

15 0

D0D1

Start bit

16 clocks

Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode

The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).

M = (0.5 – 1

2N D – 0.5

) – (L – 0.5) F – (1 + F) × 100%

. . . . . . . . (1)

M: Receive margin (%)

N: Ratio of clock frequency to bit rate (N = 16)

D: Clock duty cycle (L = 0 to 1.0)

L: Frame length (L = 9 to 12)

F: Absolute deviation of clock frequency

From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).

M = 2 × 16 ) × 100%(0.5 –1

D = 0.5, F = 0

= 46.875% . . . . . . . . (2)

This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.

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Restrictions on Use of DMAC:

• When an external clock source is used for the serial clock, after the DMAC updates TDR,

allow an inversion of at least five system clock (φ) cycles before input of the serial clock to

start transmitting. If the serial clock is input within four states of the TDR update, a

malfunction may occur. (See figure 13.22)

• To have the DMAC read RDR, be sure to select the corresponding SCI receive-data-full

interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.

SCK

D0 D1 D2 D3 D4 D5 D6 D7

TDRE

Note: In operation with an external clock source, be sure that t >4 states.

Figure 13.22 Example of Synchronous Transmission Using DMAC

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Switching from SCK Pin Function to Port Pin Function:

• Problem in Operation: When switching the SCK pin function to the output port function (high-

level output) by making the following settings while DDR = 1, DR = 1, C/

= 1, CKE1 = 0,

CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.

1. End of serial data transmission

2. TE bit = 0

3. C/

bit = 0 ... switchover to port output

4. Occurrence of low-level output (see figure 13.23)

SCK/port

Data

C/A

CKE1

CKE0

Bit 7Bit 6

1. End of transmission 4. Low-level output

3. C/A = 0

2. TE= 0

Half-cycle low-level output

Figure 13.23 Operation when Switching from SCK Pin Function to Port Pin Function

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• Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily

places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with

an external circuit.

With DDR = 1, DR = 1, C/

= 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following

settings in the order shown.

1. End of serial data transmission

2. TE bit = 0

3. CKE1 bit = 1

4. C/

bit = 0 ... switchover to port output

5. CKE1 bit = 0

SCK/port

Data

C/A

CKE1

CKE0

Bit 7Bit 6

1. End of transmission

3. CKE1= 1 5. CKE1= 0

4. C/A = 0

2. TE= 0

High-level output TE

Figure 13.24 Operation when Switching from SCK Pin Function to Port Pin Function

(Example of Preventing Low-Level Output)

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Section 14 Smart Card Interface

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Section 14 Smart Card Interface

14.1 Overview

An IC card (smart card) interface conforming to the ISO/IEC 7816-3 (Identification Card)

standard is supported as an extension of the serial communication interface (SCI) functions.

Switchover between the normal serial communication interface and the smart card interface is

controlled by a register setting.

14.1.1 Features

Features of the smart card interface supported by the H8/3068F are listed below.

• Asynchronous communication

 Data length: 8 bits

 Parity bit generation and checking

 Transmission of error signal (parity error) in receive mode

 Error signal detection and automatic data retransmission in transmit mode

 Direct convention and inverse convention both supported

• Built-in baud rate generator allows any bit rate to be selected

• Three interrupt sources

 There are three interrupt sources—transmit-data-empty, receive-data-full, and

transmit/receive error—that can issue requests independently.

 The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA

controller (DMAC) to execute data transfer.

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14.1.2 Block Diagram

Figure 14.1 shows a block diagram of the smart card interface.

Bus interface

TDR

RSR

RDR

Module data bus

TSR

SCMR

SSR

SCR

Transmission/

reception

control

BRR

Baud rate

generator

Internal

data bus

RxD

TxD

SCK

Parity generation

Parity check

Clock

External clock

φ/4

φ/16

φ/64

TXI

RXI

ERI

SMR

Legend

SCMR: Smart card mode register

RSR: Receive shift register

RDR: Receive data register

TSR: Transmit shift register

TDR: Transmit data register

SMR: Serial mode register

SCR: Serial control register

SSR: Serial status register

BRR: Bit rate re

ister

Figure 14.1 Block Diagram of Smart Card Interface

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14.1.3 Pin Configuration

Table 14.1 shows the smart card interface pins.

Table 14.1 Smart Card Interface Pins

Pin Name Abbreviation I/O Function

Serial clock pin SCK I/O Clock input/output

Receive data pin RxD Input Receive data input

Transmit data pin TxD Output Transmit data output

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14.1.4 Register Configuration

The smart card interface has the internal registers listed in table 14.2. The BRR, TDR, and RDR

registers have their normal serial communication interface functions, as described in section 13,

Serial Communication Interface.

Table 14.2 Smart Card Interface Registers

Channel Address*1Name Abbreviation R/W Initial Value

0 H'FFFB0 Serial mode register SMR R/W H'00

H'FFFB1 Bit rate register BRR R/W H'FF

H'FFFB2 Serial control register SCR R/W H'00

H'FFFB3 Transmit data register TDR R/W H'FF

H'FFFB4 Serial status register SSR R/(W)*2H'84

H'FFFB5 Receive data register RDR R H'00

H'FFFB6 Smart card mode register SCMR R/W H'F2

1 H'FFFB8 Serial mode register SMR R/W H'00

H'FFFB9 Bit rate register BRR R/W H'FF

H'FFFBA Serial control register SCR R/W H'00

H'FFFBB T ransmit data register TDR R/W H'FF

H'FFFBC Serial status register SSR R/(W)*2H'84

H'FFFBD Receive data register RDR R H'00

H'FFFBE Smart card mode register SCMR R/W H'F2

2 H'FFFC0 Serial mode register SMR R/W H'00

H'FFFC1 Bit rate register BRR R/W H'FF

H'FFFC2 Serial control register SCR R/W H'00

H'FFFC3 Transmit data register TDR R/W H'FF

H'FFFC4 Serial status register SSR R/(W)*2H'84

H'FFFC5 Receive data register RDR R H'00

H'FFFC6 Smart card mode register SCMR R/W H'F2

Notes: 1. Lower 20 bits of the address in advanced mode.

2. Only 0 can be written i n bits 7 to 3, to clear the flags.

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14.2 Register Descriptions

This section describes the new or modified registers and bit functions in the smart card interface.

14.2.1 Smart Card Mode Register (SCMR)

SCMR is an 8-bit readable/writable register that selects smart card interface functions.

—

SDIR

R/W

SMIF

R/W

SINV

R/W

—

Bit

Initial value

Read/Write

Reserved bits Reserved bit

Smart card interface

mode select

Enables or disables

the smart card interface

function

Smart card data invert

Inverts data logic levels

Smart card data transfer direction

Selects the serial/parallel conversion format

SCMR is initialized to H'F2 by a reset and in standby mode.

Bits 7 to 4—Reserved: Read-only bits, always read as 1.

Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion

format.*1

Bit 3

SDIR Description

0 TDR contents are transmitted LSB-first (Initial value)

Receive data is stored LSB-first in RDR

1 TDR contents are transmitted MSB-first

Receive data is stored MSB-first in RDR

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Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This

function is used in combination with the SDIR bit to communicate with inverse-convention

cards.*2 The SINV bit does not affect the logic level of the parity bit. For parity settings, see

section 14.3.4, Register Settings.

Bit 2

SINV Description

0 Unmodified TDR contents are transmitted (Initial value)

Receive data is stored unmodified in RDR

1 Inverted TDR contents are transmitted

Receive data is inverted before storage in RDR

Bit 1—Reserved: Read-only bit, always read as 1.

Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.

Bit 0

SMIF Description

0 Smart card interface function is disabled (Initi al value)

1 Smart card interface function is enabled

Notes: 1. The function for switching between LSB-first and MSB-first mode can also be used

with the normal serial communication interface. Note that when the communication

format data length is set to 7 bits and MSB-first mode is selected for the serial data to

be transferred, bit 0 of TDR is not transmitted, and only bits 7 to 1 of the received data

are valid.

2. The data logic level inversion function can also be used with the normal serial

communication interface. Note that, when inverting the serial data to be transferred,

parity transmission and parity checking is based on the number of high-level periods at

the serial data I/O pin, and not on the register value.

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14.2.2 Serial Status Register (SSR)

The function of SSR bit 4 is modified in smart card interface mode. This change also causes a

modification to the setting conditions for bit 2 (TEND).

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

ERS

R/(W)*

PER

R/(W)*

MPBT

R/W

TEND

MPB

Bit

Initial value

Read/Write

Transmit end

Status flag indicating end

of transmission

Error signal status (ERS)

Status flag indicating that an error

signal has been received

Note: * Onl

0 can be written, to clear the fla

Bits 7 to 5: These bits operate as in normal serial communication. For details see section 13.2.7,

Serial Status Register (SSR).

Bit 4—Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of

the error signal sent from the receiving device to the transmitting device. The smart card interface

does not detection framing errors.

Bit 4

ERS Description

0 Indicates normal transmission, with no error signal returned (Initial val ue)

[Clearing conditions]

The chip is reset, or enters standby mode or module stop mode

Software reads ERS while it is set to 1, then writes 0.

1 Indicates that the receiving device sent an error signal reporting a parity error

[Setting condition]

A low error signal was sampled.

Note: Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous

value.

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Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13.2.7,

Serial Status Register (SSR). The setting conditions for transmit end (TEND), however, are

modified as follows.

Bit 2

TEND Description

0 Transmission is in progress

[Clearing conditions]

Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.

The DMAC or DTC writes data in TDR.

1 End of transmission

[Setting conditions] (Initial value)

The chip is reset or enters standby mode.

The TE bit and FER/ERS bit are both cleared to 0 in SCR.

TDRE is 1 and FER/ERS is 0 at a time 2.5 etu after the last bit of a 1-byte serial

character is transmitted (normal transmission).

Note: etu (Elementary time unit: the time for transfer of one bit)

14.2.3 Serial Mode Register (SMR)

The function of SMR bit 7 is modified in smart card interface mode. This change also causes a

modification to the function of bits 1 and 0 in the serial control register (SCR).

R/W

CHR

R/W

O/E

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Bit

Initial value

Read/Write

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Bit 7—GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting

this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the

TEND flag that indicates completion of transmission, and the type of clock output used. The

details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in

the serial control register (SCR).

Bit 7

GM Description

0 Normal smart card interface mode operati on

The TEND flag is set 12.5 etu after the beginning of the start bit.

Clock output on/off control only. (Initial val ue)

1 GSM mode smart card interface mode operation

The TEND flag is set 11.0 etu after the beginning of the start bit.

Clock output on/off and fixed-high/fixed-low control.

Note: etu (Elementary time unit: the time for transfer of one bit)

Bits 6 to 0: These bits operate as in normal serial communication. For details see section 13.2.5,

Serial Mode Register (SMR).

14.2.4 Serial Control Register (SCR)

The function of SCR bits 1 and 0 is modified in smart card interface mode

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

Read/Write

Bits 7 to 2: These bits operate as in normal serial communication. For details see section 13.2.6,

Serial Control Register (SCR).

Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source

and enable or disable clock output from the SCK pin. In smart card interface mode, it is possible

to specify a fixed high level or fixed low level for the clock output, in addition to the usual

switching between enabling and disabling of the clock output.

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Bit 7

GM Bit 1

CKE1 Bit 0

CKE0 Description

0 0 0 Internal clock/SCK pin is I/O port (Initial value)

1 Internal clock/SCK pin is clock output

1 0 Internal clock/SCK pin is fixed at low output

1 Internal clock/SCK pin is clock output

1 0 Internal clock/SCK pin is fixed at high output

1 Internal clock/SCK pin is clock output

14.3 Operation

14.3.1 Overview

The main features of the smart card interface are as follows.

• One frame consists of 8-bit data plus a parity bit.

• In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of

one bit) is provided between the end of the parity bit and the start of the next frame.

• If a parity error is detected during reception, a low error signal level is output for a1 etu period

10.5 etu after the start bit.

• If an error signal is detected during transmission, the same data is transmitted automatically

after the elapse of 2 etu or longer.

• Only asynchronous communication is supported; there is no synchronous communication

function.

14.3.2 Pin Connections

Figure 14.2 shows a pin connection diagram for the smart card interface.

In communication with a smart card, since both transmission and reception are carried out on a

single data transmission line, the TxD pin and RxD pin should both be connected to this line. The

data transmission line should be pulled up to VCC with a resistor.

When the smart card uses the clock generated on the smart card interface, the SCK pin output is

input to the CLK pin of the smart card. If the smart card uses an internal clock, this connection is

unnecessary.

The reset signal should be output from one of the H8/3068F’s generic ports.

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In addition to these pin connections, power and ground connections will normally also be

necessary.

TxD

RxD

SCK

Px (port)

H8/3068F

chip

VCC

I/O

Data line

Clock line

Reset line

CLK

RST

Card-processing device

Smart card

Figure 14.2 Smart Card Interface Connection Diagram

Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a

smart card.

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14.3.3 Data Format

Figure 14.3 shows the smart card interface data format. In reception in this mode, a parity check

is carried out on each frame, and if an error is detected an error signal is sent back to the

transmitting device to request retransmission of the data. In transmission, the error signal is

sampled and the same data is retransmitted if the error signal is low.

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

No parity error

Output from transmitting device

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

Parity error

Output from transmitting device

Output from

receiving

device

Legend

Ds: Start bit

D0 to D7: Data bits

Dp: Parity bit

DE: Error signal

Figure 14.3 Smart Card Interface Data Format

The operating sequence is as follows.

1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-

up resistor.

2. The transmitting device starts transfer of one frame of data. The data frame starts with a start

bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).

3. With the smart card interface, the data line then returns to the high-impedance state. The data

line is pulled high with a pull-up resistor.

4. The receiving device carries out a parity check. If there is no parity error and the data is

received normally, the receiving device waits for reception of the next data. If a parity error

occurs, however, the receiving device outputs an error signal (DE, low-level) to request

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retransmission of the data. After outputting the error signal for the prescribed length of time,

the receiving device places the signal line in the high-impedance state again. The signal line is

pulled high again by a pull-up resistor.

5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data

frame. If it receives an error signal, however, it returns to step 2 and transmits the same data

again.

14.3.4 Register Settings

Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or

1 must be set to the value shown. The setting of other bits is described in this section.

Table 14.3 Smart Card Interface Register Settings

Bit

SMR H'FFFB0 GM 0 1 O/

1 0 CKS1 CKS0

BRR H'FFFB1 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0

SCR H'FFFB2 TIE RIE TE RE 0 0 CKE1*2CKE0

TDR H'FFFB3 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0

SSR H'FFFB4 TDRE RDRF ORER ERS PER TEND 0 0

RDR H'FFFB5 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0

SCMR H'FFFB6 ————SDIR SINV —SMIF

Notes: — Unused bit.

1. Lower 20 bits of the address in advanced mode.

2. When GM is cleared to 0 in SMR, the CKE1 bit must also be cleared to 0.

Serial Mode Register (SMR) Settings: Clear the GM bit to 0 when using the normal smart card

interface mode, or set to 1 when using GSM mode. Clear the O/

bit to 0 if the smart card is of

the direct convention type, or set to 1 if of the inverse convention type.

Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator. See section

14.3.5, Clock.

Bit Rate Register (BRR) Settings: BRR is used to set the bit rate. See section 14.3.5, Clock, for

the method of calculating the value to be set.

Serial Control Register (SCR) Settings: The TIE, RIE, TE, and RE bits have their normal serial

communication functions. See section 13, Serial Communication Interface, for details. The CKE1

and CKE0 bits specify clock output. To disable clock output, clear these bits to 00; to enable

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clock output, set these bits to 01. Clock output is not performed when the GM bit is set to 1 in

SMR. Clock output can also be fixed low or high.

Smart Card Mode Register (SCMR) Settings: Clear both the SDIR bit and SINV bit cleared to

0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention

type. To use the smart card interface, set the SMIF bit to 1.

The register settings and examples of starting character waveforms are shown below for two

smart cards, one following the direct convention and one the inverse convention.

1. Direct Convention (SDIR = SINV = O/

= 0)

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

AZZAZZZAAZ(Z) (Z) State

With the direct convention type, the logic 0 level corresponds to state Z and the logic 1 level

to state A, and transfer is performed in LSB-first order. In the example above, the first

character data is H'3B. The parity bit is 1, following the even parity rule designated for smart

cards.

2. Indirect Convention (SDIR = SINV = O/

= 1)

Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp

AZZAAAAAAZ(Z) (Z) State

With the indirect convention type, the logic 1 level corresponds to state Z and the logic 0 level

to state A, and transfer is performed in MSB-first order. In the example above, the first

character data is H'3F. The parity bit is 0, corresponding to state Z, following the even parity

rule designated for smart cards.

In the H8/3068F, inversion specified by the SINV bit applies only to the data bits, D7 to D0.

For parity bit inversion, the O/

bit in SMR must be set to odd parity mode. This applies to

both transmission and reception.

Section 14 Smart Card Interface

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14.3.5 Clock

Only an internal clock generated by the on-chip baud rate generator can be used as the

transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register

(BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for

calculating the bit rate is shown below. Table 14.5 shows some sample bit rates.

If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is

output from the SCK pin.

B = 1488 × 22n–1 × (N + 1) × 10

where, N: BRR setting (0

≤

255)

B: Bit rate (bit/s)

φ: Operating frequency (MHz)

n: See table 14.4

Table 14.4 n-Values of CKS1 and CKS0 Settings

n CKS1 CKS0

00 0

21 0

Note: *If the gear function is used to divide the clock frequency, use the divided frequency to

calculate the bit rate. The equation above applies directly to 1/1 frequency divisi on.

Table 14.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0)

φφ

φ (MHz)

N 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00

0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5

1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8

2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5

Note: Bit rates are rounded off to one decimal place.

Section 14 Smart Card Interface

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The following equation calculates the bit rate register (BRR) setting from the operating frequency

and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.

N = 1488 × 22n–1 × B× 106 – 1

Table 14.6 BRR Settings for Typical Bit Rates (bits/s) (When n = 0)

φφ

φ (MHz)

7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00

bit/s N Error N Error N Error N Error N Error N Error N Error

9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99

Table 14.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface Mode)

φφ

φ (MHz) Maximum Bit Rate (bits/s) N n

7.1424 9600 0 0

10.00 13441 0 0

10.7136 14400 0 0

13.00 17473 0 0

14.2848 19200 0 0

16.00 21505 0 0

18.00 24194 0 0

The bit rate error is given by the following equation:

Error (%) = 1488 × 2

2n-1

× B × (N + 1) × 10

– 1 × 100

Section 14 Smart Card Interface

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14.3.6 Transmitting and Receiving Data

Initialization: Before transmitting or receiving data, the smart card interface must be initialized

as described below. Initialization is also necessary when switching from transmit mode to receive

mode, or vice versa.

1. Clear the TE and RE bits to 0 in the serial control register (SCR).

2. Clear error flags FER/ERS, PER, and ORER to 0 in the serial status register (SSR).

3. Set the parity bit (O/

) and baud rate generator select bits (CKS1 and CKS0) in the serial

mode register (SMR). Clear the C/

, CHR, and MP bits to 0, and set the STOP and PE bits to

4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCMR).

When the SMIF bit is set to 1, the TxD pin and RxD pin are both switched from port to SCI pin

functions and go to the high-impedance state.

5. Set a value corresponding to the desired bit rate in the bit rate register (BRR).

6. Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE, and CKE1 bits to 0. If

the CKE0 bit is set to 1, the clock is output from the SCK pin.

7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the

TE bit and RE bit at the same time, except for self-diagnosis.

Transmitting Serial Data: As data transmission in smart card mode involves error signal

sampling and retransmission processing, the processing procedure is different from that for the

normal SCI. Figure 14.5 shows a sample transmission processing flowchart.

1. Perform smart card interface mode initialization as described in Initialization above.

2. Check that the FER/ERS error flag is cleared to 0 in SSR.

3. Repeat steps 2 and 3 until it can be confirmed that the TEND flag is set to 1 in SSR.

4. Write the transmit data in TDR, clear the TDRE flag to 0, and perform the transmit operation.

The TEND flag is cleared to 0.

5. To continue transmitting data, go back to step 2.

6. To end transmission, clear the TE bit to 0.

The above processing may include interrupt handling DMA transfer.

If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt

requests are enabled, a transmit-data-empty interrupt (TXI) will be requested. If an error occurs in

transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are

enabled, a transmit/receive-error interrupt (ERI) will be requested.

The timing of TEND flag setting depends on the GM bit in SMR (see figure 14.4).

Section 14 Smart Card Interface

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If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be

transmitted automatically, including automatic retransmission.

For details, see Interrupt Operations and Data Transfer by DMAC in this section.

Serial data

Note: etu (Elementary time unit: the time for transfer of one bit)

(1) GM = 0

TEND

(2) GM = 1

TEND

Ds Dp DE

Guard time

11.0 etu

12.5 etu

Figure 14.4 Timing of TEND Flag Setting

Section 14 Smart Card Interface

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Initialization

Yes

Clear TE bit to 0

Start transmitting

Start

Yes

End

Write transmit data in TDR,

and clear TDRE flag

to 0 in SSR

Error handling

TEND = 1?

All data transmitted?

TEND = 1?

FER/ERS = 0?

Figure 14.5 Sample Transmission Processing Flowchart

Section 14 Smart Card Interface

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1. Data write

TDR TSR

(shift register)

Data 1

2. Transfer from TDR to TSR Data 1 Data 1 Data remains in TDR

Data 1

3. Serial data output

Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first

transmission, D0 in MSB-first transmission) of the retransmit data to be transmitted next has

been completed.

In case of normal transmission: TEND flag is set

In case of transmit error: ERS flag is set

Steps 2 and 3 above are repeated until the

TEND flag is set.

I/O signal

output

Data 1

Figure 14.6 Relation Between Transmit Operation and Internal Registers

I/O data

When GM = 0

Guard time

DEDs Da Db Dc Dd De Df Dg Dh Dp

12.5 etu

11.0 etu When GM = 1

TXI (TEND

interrupt)

Note: etu (Elementary time unit: the time for transfer of one bit)

Figure 14.7 Timing of TEND Flag Setting

Receiving Serial Data: Data reception in smart card mode uses the same processing procedure

as for the normal SCI. Figure 14.8 shows a sample reception processing flowchart.

1. Perform smart card interface mode initialization as described in Initialization above.

2. Check that the ORER flag and PER flag are cleared to 0 in SSR. If either is set, perform the

appropriate receive error handling, then clear both the ORER and the PER flag to 0.

3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1.

4. Read the receive data from RDR.

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5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2.

6. To end reception, clear the RE bit to 0.

Initialization

Read RDR and clear

RDRF flag to 0 in SSR

Clear RE bit to 0

Start receiving

Start

Error handling

Yes

ORER = 0

and PER = 0?

RDRF = 1?

All data received?

Yes

Figure 14.8 Sample Reception Processing Flowchart

The above procedure may include interrupt handling and DMA transfer.

If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests

are enabled, a receive-data-full interrupt (RXI) will be requested. If an error occurs in reception

and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) will

be requested.

If the RXI interrupt activates the DMAC, the number of bytes designated in the DMAC will be

transferred, skipping receive data in which an error occurred.

Section 14 Smart Card Interface

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For details, see Interrupt Operations and Data Transfer by DMAC in this section.

If a parity error occurs during reception and the PER flag is set to 1, the received data is

transferred to RDR, so the erroneous data can be read.

Switching Modes: When switching from receive mode to transmit mode, first confirm that the

receive operation has been completed, then start from initialization, clearing RE to 0 and setting

TE to 1. The RDRF, PER, or ORER flag can be used to check that the receive operation has been

completed.

When switching from transmit mode to receive mode, first confirm that the transmit operation has

been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND

flag can be used to check that the transmit operation has been completed.

Fixing Clock Output: When the GM bit is set to 1 in SMR, clock output can be fixed by means

of the CKE1 and CKE0 bits in SCR. The minimum clock pulse width can be set to the specified

width in this case.

Figure 14.9 shows the timing for fixing clock output. In this example, GM = 1, CKE1 = 0, and the

CKE0 bit is controlled.

Specified pulse

width

CKE1 value

SCK

Specified pulse

width

SCR write

(CKE0 = 1)

SCR write

(CKE0 = 0)

Figure 14.9 Timing for Fixing Cock Output

Interrupt Operations: The smart card interface has three interrupt sources: transmit-data-empty

(TXI), transmit/receive-error (ERI), and receive-data-full (RXI). The transmit-end interrupt

request (TEI) is not available in smart card mode.

A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is

requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER,

PER, or ERS flag is set to 1 in SSR. These relationships are shown in table 14.8.

Section 14 Smart Card Interface

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Table 14.8 Smart Card Interface Mode Operating States and Interrupt Sources

Operating State Flag Enable Bit Interrupt

Source DMAC

Activation

Transmit Mode Normal

operation TEND TIE TXI Available

Error ERS RIE ERI Not available

Receive Mode Normal

operation RDRF RIE RXI Available

Error PER, ORER RIE ERI Not available

Data Transfer by DMAC: The DMAC can be used to transmit and receive data in smart card

mode, as in normal SCI operations. In transmit mode, when the TEND flag is set to 1 in SSR, the

TDRE flag is set simultaneously, generating a TXI interrupt. If the TXI request is designated

beforehand as a DMAC activation source, the DMAC will be activated by the TXI request and

will transfer the next transmit data. This data transfer by the DMAC automatically clears the

TDRE and TEND flags to 0. In the event of an error, the SCI automatically retransmits the same

data, keeping the TEND flag cleared to 0 so that the DMAC is not activated. The SCI and DMAC

will therefore automatically transmit the designated number of bytes, including retransmission

when an error occurs. When an error occurs, the ERS flag is not cleared automatically, so the RIE

bit should be set to 1 to enable the error to generate an ERI request, and the ERI interrupt handler

should clear ERS.

When using the DMAC to transmit or receive, first set up and enable the DMAC, then make SCI

settings. DMAC settings are described in section 7, DMA controller.

In receive operations, an RXI interrupt is requested when the RDRF flag is set to 1 in SSR. If the

RXI request is designated beforehand as a DMAC activation source, the DMAC will be activated

by the RXI request and will transfer the received data. This data transfer by the DMAC

automatically clears the RDRF flag to 0. When an error occurs, the RDRF flag is not set and an

error flag is set instead. The DMAC is not activated. The ERI interrupt request is directed to the

CPU. The ERI interrupt handler should clear the error flags.

Section 14 Smart Card Interface

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Examples of Operation in GSM Mode: When switching between smart card interface mode

and software standby mode, use the following procedures to maintain the clock duty cycle.

• Switching from smart card interface mode to software standby mode

1. Set the P94 data register (DR) and data direction register (DDR) to the values for the fixed

output state in software standby mode.

2. Write 0 in the TE and RE bits in the serial control register (SCR) to stop transmit/receive

operations. At the same time, set the CKE1 bit to the value for the fixed output state in

software standby mode.

3. Write 0 in the CKE0 bit in SCR to stop the clock.

4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock

output is fixed at the specified level.

5. Write H'00 in the serial mode register (SMR) and smart card mode register (SCMR).

6. Make the transition to the software standby state.

• Returning from software standby mode to smart card interface mode

1. Clear the software standby state.

2. Set the CKE1 bit in SCR to the value for the fixed output state at the start of software standby

(the current P94 pin state).

3. Set smart card interface mode and output the clock. Clock signal generation is started with the

normal duty cycle.

Software

standby Normal operation

Normal operation

(1) (2) (3) (4) (5) (6) (1) (2) (3)

Figure 14.10 Procedure for Stopping and Restarting the Clock

Use the following procedure to secure the clock duty cycle after powering on.

1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the

potential.

2. Fix at the output specified by the CKE1 bit in SCR.

3. Set SMR and SCMR, and switch to smart card interface mode operation.

4. Set the CKE0 bit to 1 in SCR to start clock output.

Section 14 Smart Card Interface

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14.4 Usage Notes

The following points should be noted when using the SCI as a smart card interface.

Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In

smart card interface mode, the SCI operates on a base clock with a frequency of 372 times the

transfer rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it

samples on the base clock. Receive data is latched at the rising edge of the 186th base clock pulse.

The timing is shown in figure 14.11.

Internal base

clock

372 clocks

186 clocks

Receive data

(RxD)

Synchronization

sampling timing

D0 D1

Data sampling

timing

185 371 0

371

185 0

Start bit

Figure 14.11 Receive Data Sampling Timing in Smart Card Interface Mode

Section 14 Smart Card Interface

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The receive margin can therefore be expressed as follows.

Receive margin in smart card interface mode:

M = (0.5 – 1

2N D – 0.5

) – (L – 0.5) F – (1 + F) × 100

M: Receive margin (%)

N: Ratio of clock frequency to bit rate (N = 372)

D: Clock duty cycle (L = 0 to 1.0)

L: Frame length (L =10)

F: Absolute deviation of clock frequency

From the above equation, if F = 0 and D = 0.5, the receive margin is as follows.

When D = 0.5 and F = 0:

M= (0.5 – 1/2 × 372) × 100%

= 49.866%

Retransmission: Retransmission is performed by the SCI in receive mode and transmit mode as

described below.

• Retransmission when SCI is in Receive Mode

Figure 14.12 illustrates retransmission when the SCI is in receive mode.

1. If an error is found when the received parity bit is checked, the PER bit is automatically set to

1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER bit

should be cleared to 0 in SSR before the next parity bit sampling timing.

2. The RDRF bit in SSR is not set for the frame in which the error has occurred.

3. If no error is found when the received parity bit is checked, the PER bit is not set to 1 in SSR.

4. If no error is found when the received parity bit is checked, the receive operation is assumed

to have been completed normally, and the RDRF bit is automatically set to 1 in SSR. If the

RIE bit in SCR is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a

DMA transfer activation source, the RDR contents can be read automatically. When the

DMAC reads the RDR data, the RDRF flag is automatically cleared to 0.

5. When a normal frame is received, the data pin is held in the high-impedance state at the error

signal transmission timing.

Section 14 Smart Card Interface

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D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp(DE) Ds D0 D1 D2 D3 D4Ds

Frame n+1

Retransmitted frameFrame n

RDRF

[1]

PER [2]

[3]

[4]

Figure 14.12 Retransmission in SCI Receive Mode

• Retransmission when SCI is in Transmit Mode

Figure 14.13 illustrates retransmission when the SCI is in transmit mode.

6. If an error signal is sent back from the receiving device after transmission of one frame is

completed, the FER/ERS bit is set to 1 in SSR. If the RIE bit in SCR is set to the enable state,

an ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity

bit sampling timing.

7. The TEND bit in SSR is not set for the frame for which the error signal was received.

8. If an error signal is not sent back from the receiving device, the ERS flag is not set in SSR.

9. If an error signal is not sent back from the receiving device, transmission of one frame,

including retransmission, is assumed to have been completed, and the TEND bit is set to 1 in

SSR. If the TIE bit in SCR is set to the enable state, a TXI interrupt is requested. If TXI is

enabled as a DMA transfer activation source, the next data can be written in TDR

automatically. When the DMAC writes data in TDR, the TDRE bit is automatically cleared to

D0D1D2D3D4D5D6D7Dp DE Ds D0D1D2D3D4D5D6D7Dp (DE) Ds D0D1D2D3D4Ds

Frame n+1

Retransmitted frameFrame n

TDRE

TEND

[6]

ERS

Transfer from TDR to TSR Transfer from TDR to TSR Transfer from TDR to TSR

[7] [9]

[8]

Figure 14.13 Retransmission in SCI Transmit Mode

Section 14 Smart Card Interface

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Section 15 A/D Converter

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Section 15 A/D Converter

15.1 Overview

The H8/3068F includes a 10-bit successive-approximations A/D converter with a selection of up

to eight analog input channels.

When the A/D converter is not used, it can be halted independently to conserve power. For details

see section 20.6, Module Standby Function.

15.1.1 Features

A/D converter features are listed below.

• 10-bit resolution

• Eight input channels

• Selectable analog conversion voltage range

The analog voltage conversion range can be programmed by input of an analog reference

voltage at the VREF pin.

• High-speed conversion

Conversion time: maximum 3.5 µs per channel (with 20 MHz system clock)

• Two conversion modes

Single mode: A/D conversion of one channel

Scan mode: continuous conversion on one to four channels

• Four 16-bit data registers

A/D conversion results are transferred for storage into data registers corresponding to the

channels.

• Sample-and-hold function

• Three conversion start sources

The A/D converter can be activated by software, an external trigger, or an 8-bit timer compare

match.

• A/D interrupt requested at end of conversion

At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.

• DMA controller (DMAC) activation

The DMAC can be activated at the end of A/D conversion.

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15.1.2 Block Diagram

Figure 15.1 shows a block diagram of the A/D converter.

Module data bus

Bus interface

Internal

data bus

ADDRA

ADDRB

ADDRC

ADDRD

ADCSR

ADCR

Successive-

approximations register

10-bit D/A

Analog

multi-

plexer Sample-and-

hold circuit

Comparator

–

Control circuit

ø/4

ø/8

ADI

interrupt signal

REF

Legend

ADCR:

ADCSR:

ADDRA:

ADDRB:

ADDRC:

ADDRD:

A/D control register

A/D control/status register

A/D data register A

A/D data register B

A/D data register C

A/D data re

ister D

ADTRG

ADTE

Compare match A0

TCSR0

8-bit timer

Figure 15.1 A/D Converter Block Diagram

Section 15 A/D Converter

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15.1.3 Input Pins

Table 15.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided

into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power

supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference voltage.

Table 15.1 A/D Converter Pins

Pin Name Abbrevi-

ation I/O Function

Analog power supply pin AVCC Input Analog power supply

Analog ground pin AVSS Input Analog ground and reference voltage

Reference voltage pin VREF Input Analog reference voltage

Analog input pin 0 AN0Input Group 0 analog inputs

Analog input pin 1 AN1Input

Analog input pin 2 AN2Input

Analog input pin 3 AN3Input

Analog input pin 4 AN4Input Group 1 analog inputs

Analog input pin 5 AN5Input

Analog input pin 6 AN6Input

Analog input pin 7 AN7Input

A/D external trigger input pin

ADTRG

Input External trigger input for starting A/D conversion

Section 15 A/D Converter

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15.1.4 Register Configuration

Table 15.2 summarizes the A/D converter’s registers.

Table 15.2 A/D Converter Registers

Address*1Name Abbreviation R/W Initial Value

H'FFFE0 A/D data register A H ADDRAH R H'00

H'FFFE1 A/D data register A L ADDRAL R H'00

H'FFFE2 A/D data register B H ADDRBH R H'00

H'FFFE3 A/D data register B L ADDRBL R H'00

H'FFFE4 A/D data register C H ADDRCH R H'00

H'FFFE5 A/D data register C L ADDRCL R H'00

H'FFFE6 A/D data register D H ADDRDH R H'00

H'FFFE7 A/D data register D L ADDRDL R H'00

H'FFFE8 A/D control/status register ADCSR R/(W)*2H'00

H'FFFE9 A/D control register ADCR R/W H'7E

Notes: 1. Lower 20 bits of the address in advanced mode.

2. Only 0 can be written in bit 7, to clear the flag.

Section 15 A/D Converter

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15.2 Register Descriptions

15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)

Bit

ADDRn

Initial value

AD8

AD6

AD4

AD2

AD0

—

AD9

AD7

AD5

AD3

AD1

—

A/D conversion data

10-bit data giving an

A/D conversion result

Reserved bits

Read/Write

(n = A to D)

The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the

results of A/D conversion.

An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data

upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an

A/D data register are reserved bits that are always read as 0. Table 15.3 indicates the pairings of

analog input channels and A/D data registers.

The CPU can always read and write the A/D data registers. The upper byte can be read directly,

but the lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU

Interface.

The A/D data registers are initialized to H'0000 by a reset and in standby mode.

Table 15.3 Analog Input Channels and A/D Data Registers

Analog Input Channel

Group 0 Group 1 A/D Data Register

AN0AN4ADDRA

AN1AN5ADDRB

AN2AN6ADDRC

AN3AN7ADDRD

Section 15 A/D Converter

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15.2.2 A/D Control/Status Register (ADCSR)

Bit

Initial value

Read/Write

ADF

R/(W)*

ADIE

R/W

ADST

R/W

SCAN

R/W

CKS

R/W

CH0

R/W

CH2

R/W

CH1

R/W

Note: * Onl

0 can be written, to clear the fla

A/D end flag

Indicates end of A/D conversion

A/D interrupt enable

Enables and disables A/D end interrupts

A/D start

Starts or stops A/D conversion

Scan mode

Selects single mode or scan mode

Clock select

Selects the A/D conversion time

Channel select 2 to 0

These bits select analog

input channels

ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D

converter. ADCSR is initialized to H'00 by a reset and in standby mode.

Section 15 A/D Converter

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Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.

Bit 7

ADF Description

0 [Clearing condition]

Read ADF when ADF =1, then write 0 in ADF.

DMAC activated by ADI interrupt.

(Initi al value)

1 [Setting conditions]

Single mode: A/D conversion ends

Scan mode: A/D conversion ends i n all selected channels

Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the

end of A/D conversion.

Bit 6

ADIE Description

0 A/D end interrupt request (ADI) is disabled (Initial value)

1 A/D end interrupt request (ADI) is enabled

Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during

A/D conversion. It can also be set to 1 by external trigger input at the

ADTRG

pin, or by an 8-bit

timer compare match.

Bit 5

ADST Description

0 A/D conversion is stopped (Initial value)

1 Single mode: A/D conversion starts; ADST is automatically cleared to 0 when

conversion ends.

Scan mode: A/D conversion starts and continues, cycling among the selected

channels, until ADST is cleared to 0 by software, by a reset, or by a transition to

standby mode.

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Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on

operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching

the conversion mode.

Bit 4

SCAN Description

0 Single mode (Initi al value)

1 Scan mode

Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before

switching the conversion time.

Bit 3

CKS Description

0 Conversion ti me = 134 states (maximum) (Initial value)

1 Conversion ti me = 70 states (maximum)

Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the

analog input channels. Clear the ADST bit to 0 before changing the channel selection.

Group

Selection Channel Selection Description

CH2 CH1 CH0 Single Mode Scan Mode

000 AN

0 (Initial value) AN0

1AN

1AN0, AN1

10 AN

2AN0 to AN2

1AN

3AN0 to AN3

100 AN

4AN4

1AN

5AN4, AN5

10 AN

6AN4 to AN6

1AN

7AN4 to AN7

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15.2.3 A/D Control Register (ADCR)

Bit

Initial value

Read/Write

TRGE

R/W

—

R/W

—

Trigger enable

Enables or disables starting of A/D conversion

by an external trigger or 8-bit timer compare match

Reserved bits

ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by

external trigger input or an 8-bit timer compare match signal. ADCR is initialized to H'7F by a

reset and in standby mode.

Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external

trigger or 8-bit timer compare match.

Bit 7

TRGE Description

0 Starting of A/D conversion by an external trigger or 8-bit timer

compare match is disabled (Initi al value)

1 A/D conversion is started at the fal ling edge of the external trigger

signal (

ADTRG

) or by an 8-bit ti mer compare match

External trigger pin and 8-bit timer selection are performed by the 8-bit timer. For details, see

section 10, 8-Bit Timers.

Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 1.

Bit 0—Reserved: This bit can be read or written, but must not be set to 1.

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15.3 CPU Interface

ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.

Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read

through an 8-bit temporary register (TEMP).

An A/D data register is read as follows. When the upper byte is read, the upper-byte value is

transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when

the lower byte is read, the TEMP contents are transferred to the CPU.

When reading an A/D data register, always read the upper byte before the lower byte. It is

possible to read only the upper byte, but if only the lower byte is read, incorrect data may be

obtained.

Figure 15.2 shows the data flow for access to an A/D data register.

Section 15 A/D Converter

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Upper-byte read

Bus interface Module data bus

CPU

(H'AA)

ADDRnH

(H'AA) ADDRnL

(H'40)

Lower-byte read

Bus interface Module data bus

CPU

(H'40)

ADDRnH

(H'AA) ADDRnL

(H'40)

TEMP

(H'40)

TEMP

(H'40)

(n = A to D)

Figure 15.2 A/D Data Register Access Operation (Reading H'AA40)

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15.4 Operation

The A/D converter operates by successive approximations with 10-bit resolution. It has two

operating modes: single mode and scan mode.

15.4.1 Single Mode (SCAN = 0)

Single mode should be selected when only one A/D conversion on one channel is required. A/D

conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The

ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when

conversion ends.

When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is

requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.

When the mode or analog input channel must be switched during analog conversion, to prevent

incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making

the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be

set at the same time as the mode or channel is changed.

Typical operations when channel 1 (AN1) is selected in single mode are described next.

Figure 15.3 shows a timing diagram for this example.

1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0,

CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started

(ADST = 1).

2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time

the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.

3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.

4. The A/D interrupt handling routine starts.

5. The routine reads ADCSR, then writes 0 in the ADF flag.

6. The routine reads and processes the conversion result (ADDRB).

7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,

A/D conversion starts again and steps 2 to 7 are repeated.

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ADIE

ADST

ADF

State of channel 0

(AN )

Set*

Set*Set*

Clear*Clear*

Idle

A/D conversion (1)

A/D conversion (2)

Idle

Read conversion result

A/D conversion result (1) Read conversion result

A/D conversion result (2)

Note: * Vertical arrows

(

)

indicate instructions executed b

software.

A/D conversion

starts

ADDRA

ADDRB

ADDRC

ADDRD

State of channel 1

(AN )

State of channel 2

(AN )

State of channel 3

(AN )

Idle

Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)

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15.4.2 Scan Mode (SCAN = 1)

Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the

ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first

channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are

selected, after conversion of the first channel ends, conversion of the second channel (AN1 or

AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the

ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data

registers corresponding to the channels.

When the mode or analog input channel selection must be changed during analog conversion, to

prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After

making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the

first channel in the group. The ADST bit can be set at the same time as the mode or channel

selection is changed.

Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are

described next. Figure 15.4 shows a timing diagram for this example.

1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels

AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).

2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into

ADDRA. Next, conversion of the second channel (AN1) starts automatically.

3. Conversion proceeds in the same way through the third channel (AN2).

4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1

and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI

interrupt is requested at this time.

5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is

cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion

starts again from the first channel (AN0).

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ADST

ADF

State of channel 0

(AN )

Continuous A/D conversion

Set

Clear

Idle

A/D conversion (1)

Idle

A/D conversion (4) Idle

A/D conversion (2)

Idle

A/D conversion (5)

Idle

A/D conversion (3)

Idle

Transfer A/D conversion result (1) A/D conversion result (4)

A/D conversion result (2)

A/D conversion result (3)

A/D conversion time

Notes:

ADDRA

ADDRB

ADDRC

ADDRD

State of channel 1

(AN )

State of channel 2

(AN )

State of channel 3

(AN )

Vertical arrows ( ) indicate instructions executed by software.

Data currently being converted is ignored.

Figure 15.4 Example of A/D Converter Operation (Scan Mode,

Channels AN0 to AN2 Selected)

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15.4.3 Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D

conversion timing. Table 15.4 indicates the A/D conversion time.

As indicated in figure 15.5, the A/D conversion time includes tD and the input sampling time. The

length of tD varies depending on the timing of the write access to ADCSR. The total conversion

time therefore varies within the ranges indicated in table 15.4.

In scan mode, the values given in table 15.4 apply to the first conversion. In the second and

subsequent conversions the conversion time is fixed at 128 states when CKS = 0 or 66 states

when CKS = 1.

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Address bus

Write signal

Input sampling

timing

ADF

(1)

(2)

tDtSPL

tCONV

Legend

(1):

(2):

t :

SPL

CONV

ADCSR write cycle

ADCSR address

Synchronization delay

Input sampling time

A/D conversion time

Figure 15.5 A/D Conversion Timing

Table 15.4 A/D Conversion Time (Single Mode)

CKS = 0 CKS = 1

Symbol Min Typ Max Min Typ Max

Synchronization del ay tD6 — 94 — 5

Input samp ling time tSPL —31 —— 15 —

A/D conversion time tCONV 131 —134 69 —70

Note: Values in the table are numbers of states.

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15.4.4 External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR and the 8-bit

timer's ADTE bit is cleared to 0, external trigger input is enabled at the

ADTRG

pin. A high-to-

low transition at the

ADTRG

pin sets the ADST bit to 1 in ADCSR, starting A/D conversion.

Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1

by software. Figure 15.6 shows the timing.

ADTRG

Internal trigger

signal

ADST

A/D conversion

Figure 15.6 External Trigger Input Timing

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15.5 Interrupts

The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt

request can be enabled or disabled by the ADIE bit in ADCSR. The ADI interrupt request can be

designated as a DMAC activation source. In this case, an interrupt request is not sent to the CPU.

15.6 Usage Notes

When using the A/D converter, note the following points:

1. Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input

pins should be in the range AVSS

≤

ANn

≤

VREF.

2. Relationships of AVCC and AVSS to VCC and VSS: AVCC, AVSS, VCC, and VSS should be related

as follows: AVSS = VSS. AVCC and AVSS must not be left open, even if the A/D converter is

not used.

3. VREF Programming Range: The reference voltage input at the VREF pin should be in the range

VREF

≤

AVCC.

4. Note on Board Design: In board layout, separate the digital circuits from the analog circuits as

much as possible. Particularly avoid layouts in which the signal lines of digital circuits cross

or closely approach the signal lines of analog circuits. Induction and other effects may cause

the analog circuits to operate incorrectly, or may adversely affect the accuracy of A/D

conversion.

The analog input signals (AN0 to AN7), analog reference voltage (VREF), and analog supply

voltage (AVCC) must be separated from digital circuits by the analog ground (AVSS). The

analog ground (AVSS) should be connected to a stable digital ground (VSS) at one point on the

board.

5. Note on Noise: To prevent damage from surges and other abnormal voltages at the analog

input pins (AN0 to AN7) and analog reference voltage pin (VREF), connect a protection circuit

like the one in figure 15.7 between AVCC and AVSS. The bypass capacitors connected to AVCC

and VREF and the filter capacitors connected to AN0 to AN7 must be connected to AVSS. If

filter capacitors like the ones in figure 15.7 are connected, the voltage values input to the

analog input pins (AN0 to AN7) will be smoothed, which may give rise to error. Error can also

occur if A/D conversion is frequently performed in scan mode so that the current that charges

and discharges the capacitor in the sample-and-hold circuit of the A/D converter becomes

greater than that input to the analog input pins via input impedance Rin. The circuit constants

should therefore be selected carefully.

Section 15 A/D Converter

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*1*1

REF

to AN

Notes: 1.

2. Rin: input impedance

Rin

100 Ω

0.1 µF

0.01 µF10 µF

Figure 15.7 Example of Analog Input Protection Circuit

Table 15.5 Analog Input Pin Ratings

Item min max Unit

Analog input capacitance —20 pF

Allowable signal-source impedance —10*k

Ω

Note: *When conversion time = 134 states, VCC = 4.0 V to 5.5 V, and ø

≤

13 Mhz. For details see

section 21, Electrical Characteristics.

20 pF

To A/D converterAN0 to AN7

10 kΩ

Figure 15.8 Analog Input Pin Equivalent Circuit

Note: Numeric values are approximate, except in table 15.5

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6. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/3068F is defined

as follows:

• Resolution: Digital output code length of A/D converter

• Offset error: Deviation from ideal A/D conversion characteristic of analog input

voltage required to raise digital output from minimum voltage value

0000000000 to 0000000001 (figure 15.10)

• Full-scale error: Deviation from ideal A/D conversion characteristic of analog input

voltage required to raise digital output from 1111111110 to 1111111111

(figure 15.10)

• Quantization error: Intrinsic error of the A/D converter; 1/2 LSB (figure 15.9)

• Nonlinearity error: Deviation from ideal A/D conversion characteristic in range from zero

volts to full scale, exclusive of offset error, full-scale error, and

quantization error.

• Absolute accuracy: Deviation of digital value from analog input value, including offset error,

full-scale error, quantization error, and nonlinearity error.

111

110

101

100

011

010

001

000 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS

Quantization error

Analog inpu

volta

Digital

output

Ideal A/D conversion

characteristic

Figure 15.9 A/D Converter Accuracy Definitions (1)

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Offset error

Nonlinearity

error

Actual A/D conversion

characteristic

Analog input

voltage

Digital

output

Ideal A/D

conversion

characteristic

Full-scale

error

Figure 15.10 A/D Converter Accuracy Definitions (2)

7. Allowable Signal-Source Impedance: The analog inputs of the H8/3068F are designed to

assure accurate conversion of input signals with a signal-source impedance not exceeding 10

Ω

. The reason for this rating is that it enables the input capacitor in the sample-and-hold

circuit in the A/D converter to charge within the sampling time. If the sensor output

impedance exceeds 10 k

Ω

, charging may be inadequate and the accuracy of A/D conversion

cannot be guaranteed.

If a large external capacitor is provided in single mode, then the internal 10-k

Ω

input

resistance becomes the only significant load on the input. In this case the impedance of the

signal source is not a problem.

A large external capacitor, however, acts as a low-pass filter. This may make it impossible to

track analog signals with high dv/dt (e.g. a variation of 5 mV/µs) (figure 15.11). To convert

high-speed analog signals or to use scan mode, insert a low-impedance buffer.

8. Effect on Absolute Accuracy: Attaching an external capacitor creates a coupling with ground,

so if there is noise on the ground line, it may degrade absolute accuracy. The capacitor must

be connected to an electrically stable ground, such as AVSS.

Section 15 A/D Converter

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If a filter circuit is used, be careful of interference with digital signals on the same board, and

make sure the circuit does not act as an antenna.

Equivalent circuit of

A/D converter

H8/3067 Group

20 pF

Cin =

15 pF

10 kΩ

Up to 10 kΩ

Low-pass

filter

C Up to 0.1µF

Sensor output impedance

Sensor

input

Figure 15.11 Analog Input Circuit (Example)

Section 15 A/D Converter

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Section 16 D/A Converter

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Section 16 D/A Converter

16.1 Overview

The H8/3068F includes a D/A converter with two channels.

16.1.1 Features

D/A converter features are listed below.

• Eight-bit resolution

• Two output channels

• Conversion time: maximum 10 µs (with 20-pF capacitive load)

• Output voltage: 0 V to VREF

• D/A outputs can be sustained in software standby mode

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16.1.2 Block Diagram

Figure 16.1 shows a block diagram of the D/A converter.

DADR0

DADR1

DACR

DASTCR

REF

Legend

DACR:

DADR0:

DADR1:

DASTCR:

8-bit D/A

Module data bus

Bus interface

Internal

data bus

Control circuit

D/A control register

D/A data register 0

D/A data register 1

D/A standby control register

Figure 16.1 D/A Converter Block Diagram

16.1.3 Input/Output Pins

Table 16.1 summarizes the D/A converter's input and output pins.

Table 16.1 D/A Converter Pins

Pin Name Abbreviation I/O Function

Analog power supply pin AVCC Input Analog power supply and reference vol tage

Analog ground pin AVSS Input Analog ground and reference voltage

Analog output pin 0 DA0Output Analog output, channel 0

Analog output pin 1 DA1Output Analog output, channel 1

Reference voltage input pin VREF Input Analog reference voltage

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16.1.4 Register Configuration

Table 16.2 summarizes the D/A converter's registers.

Table 16.2 D/A Converter Registers

Address*Name Abbreviation R/W Initial Value

H'FFF9C D/A data register 0 DADR0 R/W H'00

H'FFF9D D/A data register 1 DADR1 R/W H'00

H'FFF9E D/A control register DACR R/W H'1F

H'EE01A D/A standby control register DASTCR R/W H'FE

Note: *Lower 20 bits of the address in advanced mode.

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16.2 Register Descriptions

16.2.1 D/A Data Registers 0 and 1 (DADR0/1)

Bit

Initial value

Read/Write

R/W

The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the

data to be converted. When analog output is enabled, the D/A data register values are constantly

converted and output at the analog output pins.

The D/A data registers are initialized to H'00 by a reset and in standby mode.

When the DASTE bit is set to 1 in the D/A standby control register (DASTCR), the D/A registers

are not initialized in software standby mode.

16.2.2 D/A Control Register (DACR)

Bit

Initial value

Read/Write

DAOE1

R/W

DAOE0

R/W

DAE

R/W

—

D/A output enable 1

D/A output enable 0

D/A enable

Controls D/A conversion and analog output

Controls D/A conversion

DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.

DACR is initialized to H'1F by a reset and in standby mode.

When the DASTE bit is set to 1 in DASTCR, the DACR is not initialized in software standby

mode.

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Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.

Bit 7

DAOE1 Description

0DA

1 analog output is disabled

1 Channel-1 D/A conversion and DA1 analog output are enabled

Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.

Bit 6

DAOE0 Description

0DA

0 analog output is disabled

1 Channel-0 D/A conversion and DA0 analog output are enabled

Bit 5—D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1.

When the DAE bit is cleared to 0, analog conversion is controlled independently in channels 0

and 1. When the DAE bit is set to 1, analog conversion is controlled together in channels 0 and 1.

Output of the conversion results is always controlled independently by DAOE0 and DAOE1.

Bit 7

DAOE1 Bit 6

DAOE0 Bit 5

DAE Description

0 0 — D/A conversion is disabled in channel s 0 and 1

1 0 D/A conversion is enabled in channel 0

D/A conversion is disabled in channel 1

1 D/A conversion is enabled in channels 0 and 1

1 0 0 D/A conversion i s disabled in channel 0

D/A conversion is enabled in channel 1

1 D/A conversion is enabled in channels 0 and 1

1 — D/A conversion is enabled in channels 0 and 1

When the DAE bit is set to 1, even if bits DAOE0 and DAOE1 in DACR and the ADST bit in

ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D

and D/A conversion.

Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.

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16.2.3 D/A Standby Control Register (DASTCR)

DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software

standby mode.

Bit

Initial value

Read/Write

—

DASTE

R/W

—

Reserved bits D/A standby enable

Enables or disables D/A output

in software standby mode

DASTCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 1—Reserved: These bits cannot be modified and are always read as 1.

Bit 0—D/A Standby Enable (DASTE): Enables or disables D/A output in software standby

mode.

Bit 0

DASTE Description

0 D/A output is disabled in software standby mode (Initial value)

1 D/A output is enabled in software standby mode

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16.3 Operation

The D/A converter has two built-in D/A conversion circuits that can perform conversion

independently.

D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value

is modified, conversion of the new data begins immediately. The conversion results are output

when bits DAOE0 and DAOE1 are set to 1.

An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 16.2.

1. Data to be converted is written in DADR0.

2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The

converted result is output after the conversion time.

× V

REF

The output value is DADR contents

256

Output of this conversion result continues until the value in DADR0 is modified or the

DAOE0 bit is cleared to 0.

3. If the DADR0 value is modified, conversion starts immediately, and the result is output after

the conversion time.

4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.

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DADR0

write cycle DACR

write cycle DADR0

write cycle DACR

write cycle

Address

DADR0

DAOE0

Conversion data 1 Conversion data 2

High-impedance state Conversion

result 1

Conversion

result 2

tDCONV tDCONV

Legend

t : D/A conversion time

DCONV

Figure 16.2 Example of D/A Converter Operation

16 .4 D/A Output Contr ol

In the H8/3068F, D/A converter output can be enabled or disabled in software standby mode.

When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby

mode. The D/A converter registers retain the values they held prior to the transition to software

standby mode.

When D/A output is enabled in software standby mode, the reference supply current is the same

as during normal operation.

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Section 17 RAM

17.1 Overview

The H8/3068F has 16 kbytes RAM. The RAM is connected to the CPU by a 16-bit data bus. The

CPU accesses both byte data and word data in two states, making the RAM useful for rapid data

transfer.

The on-chip RAM of the H8/3068F is assigned to addresses H'FBF20 to H'FFF1F in modes 1, 2,

and 7, and to addresses H'FFBF20 to H'FFFF1F in modes 3, 4, and 5,and to addresses H'E720 to

H'FF1F in mode 6. The RAM enable bit (RAME) in the system control register (SYSCR) can

enable or disable the on-chip RAM.

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17.1.1 Block Diagram

Figure 17.1 shows a block diagram of the on-chip RAM.

H'FBF20*

H'FBF22*

H'FFF1E*

H'FBF21*

H'FBF23*

H'FFF1F*

On-chip data bus (upper 8 bits)

On-chip data bus (lower 8 bits)

Bus interface SYSCR

On-chip RAM

Even addresses Odd addresses

Legend

SYSCR: System control register

Note: * Lower 20 bits of the address in mode 7.

Figure 17.1 RAM Block Diagram

17.1.2 Register Configuration

The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of

SYSCR.

Table 17.1 System Control Register

Address*Name Abbreviation R/W Initial Value

H'EE012 System control register SYSCR R/W H'09

Note: *Lower 20 bits of the address in advanced mode.

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17 .2 Syste m Control Re gister (SYSCR)

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

NMIEG

R/W

SSOE

R/W

RAME

R/W

Software standby

Standby timer select 2 to 0

User bit enable

NMI edge select

Software standby

output port enable

RAM enable bit

Enables or disable

on-chip RAM

One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is

enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,

System Control Register (SYSCR).

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized at the rising edge of the input at the

RES

pin. It is not initialized in software standby

mode.

Bit 0

RAME Description

0 On-chip RAM is disabled

1 On-chip RAM is enabled (Initi al value)

Section 17 RAM

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17.3 Operation

When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FBF20 to

H'FFF1F in modes 1, 2, and 7, and to addresses H'FFBF20 to H'FFFF1F in the H8/3068F in

modes 3, 4, and 5, and to addresses H'7F20 to H'FF1F in mode 6, are directed to the on-chip

RAM. In modes 1 to 5 (expanded modes), when the RAME bit is cleared to 0, the off-chip

address space is accessed. In mode 6, 7 (single-chip mode), when the RAME bit is cleared to 0,

the on-chip RAM is not accessed: read access always results in H'FF data, and write access is

ignored.

Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written

and read by word access. It can also be written and read by byte access. Byte data is accessed in

two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed

in two states using all 16 bits of the data bus.

Section 18 Flash Memory

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Section 18 Flash Memory

18.1 Overview

The H8/3068F-ZTAT has 384 kbytes of on-chip flash memory. The flash memory is connected to

the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states,

enabling rapid data transfer.

The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0) as shown in

table 18.1.

The on-chip flash memory product (H8/3068F-ZTAT) can be erased and programmed on-board,

as well as with a special-purpose PROM programmer.

Table 18.1 Operating Modes and ROM

Mode Pins

Mode MD2 MD1 MD0 On-Chip ROM

Mode 1 (expanded 1-Mbyte mode with on-chip ROM

disabled) 0 0 1 Disabled (external

address area)

Mode 2 (expanded 1-Mbyte mode with on-chip ROM

disabled) 010

Mode 3 (expanded 16-Mbyte mode with on-chip ROM

disabled) 011

Mode 4 (expanded 16-Mbyte mode with on-chip ROM

disabled) 100

Mode 5 (expanded 16-Mbyte mode with on-chip ROM

enabled) 1 0 1 Enabled

Mode 6 (single-chip normal mode) 1 1 0

Mode 7 (single-chip advanced mode) 1 1 1

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18.2 Features

The H8/3068F-ZTAT has 384 kbytes of on-chip flash memory.

The features of the flash memory are summarized below.

• Four flash memory operating modes

 Program mode

 Erase mode

 Program-verify mode

 Erase-verify mode

• Programming/erase methods

The flash memory is programmed 128 bytes at a time. Erasing is performed in block units. To

erase the entire flash memory, each block must be erased in turn. In block erasing, 4-kbyte,

32-kbyte, and 64-kbyte blocks can be set arbitrarily.

• Programming/erase times

The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming,

equivalent approximately to 80 µs (typ.) per byte, and the erase time is 100 ms (typ.) per

block.

• Reprogramming capability

The flash memory can be reprogrammed up to 100 times.

• On-board programming modes

There are two modes in which flash memory can be programmed/erased/verified on-board:

 Boot mode

 User program mode

• Automatic bit rate adjustment

For data transfer in boot mode, the H8/3068F-ZTAT chip’s bit rate can be automatically

adjusted to match the transfer bit rate of the host.

• Flash memory emulation in RAM

Flash memory programming can be emulated in real time by overlapping a part of RAM onto

flash memory.

• Protect modes

There are three protect modes—hardware, software, and error—which allow protected status

to be designated for flash memory program/erase/verify operations

• PROM mode

Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as

well as in on-board programming mode.

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18.2.1 Block Diagram

Module bus

Bus interface/controller

Flash memory

(384 kbytes)

Operating

mode

Internal address bus

Internal data bus (16 bits)

FWE pin

Mode pins

FLMCR2

Legend

FLMCR1: Flash memory control register 1

FLMCR2: Flash memory control register 2

EBR1: Erase block register 1

EBR2: Erase block register 2

RAMCR: RAM control register

EBR1

EBR2

RAMCR

FLMCR1

Figure 18.1 Block Diagram of Flash Memory

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18.2.2 Pin Configuration

The flash memory is controlled by means of the pins shown in table 18.2.

Table 18.2 Flash Memory Pins

Pin Name Abbreviation I/O Function

Reset

RES

Input Reset

Flash write enable FWE Input Flash program/erase protection by hardware

Mode 2 MD2Input Sets H8/3068F-ZTAT operating mode

Mode 1 MD1Input Sets H8/3068F-ZTAT operating mode

Mode 0 MD0Input Sets H8/3068F-ZTAT operating mode

Transmit data T xD1Output Serial transmit data output

Receive data RxD1Input Seri al receive data input

18.2.3 Register Configuration

The registers used to control the on-chip flash memory when enabled are shown in table 18.3.

Table 18.3 Flash Memory Registers

Flash memory control register 1 FLMCR1 R/W H'00*2H'EE030

Flash memory control regi ster 2 FLMCR2 R H'00 H'EE031

Erase block register 1 EBR1 R/W H'00 H'EE032

Erase block register 2 EBR2 R/W H'00 H'EE033

RAM control register RAMCR R/W H'F0 H'EE077

Notes: FLMCR1, FLMCR2, EBR1, EBR2, and RAMCR are 8-bit registers, and should be

accessed by byte access.

1. Lower 20 bits of address in advanced mode.

2. When a high level is input to the FWE pin, the initial val ue is H'80.

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18.3 Register Descriptions

18.3.1 Flash Memory Control Register 1 (FLMCR1)

Bit 76543210

FWE SWE ESU PSU EV PV E P

Initial value —*0000000

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Note: * Determined by the state of the FWE pin.

FLMCR1 is an 8-bit register used for flash memory operating mode control.

Program-verify mode or erase-verify mode for addresses H'00000 to H'5FFFF is entered by

setting the SWE bit when FWE = 1, then setting the PV or EV bit. Program mode for addresses

H'00000 to H'5FFFF is entered by setting the SWE bit when FWE = 1, then setting the PSU bit,

and finally setting the P bit. Erase mode for addresses H'00000 to H'5FFFF is entered by setting

the SWE bit when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is

initialized by a reset, and in hardware standby mode and software standby mode. Its initial value

is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. In mode 6

the FWE pin must be fixed low since flash memory on-board programming modes are not

supported. When the on-chip flash memory is disabled, a read access to this register will return

H'00, and writes are invalid.

When setting bits 6 to 0 in this register, one bit must be set one at a time. Writes to the SWE bit in

FLMCR1 are enabled only when FWE = 1; writes to bits ESU, PSU, EV, and PV only when FWE

= 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to

the P bit only when FWE = 1, SWE = 1, and PSU = 1.

Notes: 1. The programming and erase flowcharts must be followed when setting the bits in this

2. Transitions are made to program mode, erase mode, program-verify mode, and erase-

verify mode according to the settings in this register. When reading flash memory as

normal on-chip ROM, bits 6 to 0 in this register must be cleared.

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Bit 7—Flash Write Enable (FWE): Sets hardware protection against flash memory

programming/erasing.

Bit 7

FWE Description

0 When a low level is input to the FWE pin (hardware-protected state)

1 When a high level is i nput to the FWE pin

Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming and

erasing. (This bit should be set when setting bits 5 to 0, EBR1 bits 7 to 0, and EBR2 bits 3 to 0.)

Bit 6

SWE Description

0 Programming/erasing di sabled (Initial value)

1 Programming/erasing enabled

[Setting condition]

When FWE = 1

Note : Do not execute a SLEEP instruction while the SWE bit is set t o 1.

Bit 5—Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before

setting the E bit to 1 in FLMCR1 (do not set the SWE, PSU, EV, PV, E, or P bit at the same

time).

Bit 5

ESU Description

0 Erase setup cleared (Initi al value)

1 Erase setup

[Setting condition]

When FWE = 1 and SWE = 1

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Bit 4—Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before

setting the P bit to 1 in FLMCR1 (do not set the SWE, ESU, EV, PV, E, or P bit at the same

time).

Bit 4

PSU Description

0 Program setup cleared (Initi al value)

1 Program setup

[Setting condition]

When FWE = 1 and SWE = 1

Bit 3—Erase-Verify Mode (EV): Selects erase-verify mode transition or clearing. (Do not set

the SWE, ESU, PSU, PV, E, or P bit at the same time.)

Bit 3

EV Description

0 Erase-verify mode cleared (Initial value)

1 Transition to erase-verify mode

[Setting condition]

When FWE = 1 and SWE = 1

Bit 2—Program-Verify Mode (PV): Selects program-verify mode transition or clearing. (Do

not set the SWE, ESU, PSU, EV, E, or P bit at the same time.)

Bit 2

PV Description

0 Program-verify mode cleared (Initial value)

1 Transition to program-verify mode

[Setting condition]

When FWE = 1 and SWE = 1

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Bit 1—Erase Mode (E): Selects erase mode transition or clearing. (Do not set the SWE, ESU,

PSU, EV, PV, or P bit at the same time.)

Bit 1

E Description

0 Erase mode cleared (Initial value)

1 Transition to erase mode

[Setting condition]

When FWE = 1, SWE = 1, and ESU = 1

Note: Do not access the fl ash memory whil e the E bit is set.

Bit 0—Program (P): Selects program mode transition or clearing. (Do not set the SWE, ESU,

PSU, EV, PV, or E bit at the same time.)

Bit 0

P Description

0 Program mode cleared (Initial value)

1 Transition to program mode

[Setting condition]

When FWE = 1, SWE = 1, and PSU = 1

Note: Do not access the fl ash memory whil e the P bit is set.

18.3.2 Flash Memory Control Register 2 (FLMCR2)

Bit 76543210

FLER———————

Initial value00000000

Read/Write RRRRRRRR

FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is

initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When

the on-chip flash memory is disabled, a read will return H'00.

Note: FLMCR2 is a read-only register, and should not be written to.

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Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation

on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the

error-protection state.

Bit 7

FLER Description

0 Flash memory is operating normally

Flash memory program/erase protection (error protection) is disabled

[Clearing condition]

Reset (

RES

pin or WDT reset) or hardware standby mode (Initial val ue)

1 An error occurred during flash memory programming/erasi ng

Flash memory program/erase protection (error protection) is enabled

[Setting conditions]

• When flash memory is read during programming/erasing (including a vector read

or instruction fetch, but excluding a read of the RAM area overlapping flash

me mory space)

• Immediately after the start of exception handl ing during programmi ng/erasing

(excluding reset, illegal instruction, trap instruction, and division-by-zero

exception handling)

• When a SLEEP instru ction (including softwar e standby) is executed during

programming/erasing

• When the bus is released during programming/erasing

Bits 6 to 0—Reserved: These bits are always read as 0.

18.3.3 Erase Block Register 1 (EBR1)

Bit 76543210

EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

Initial value00000000

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is

initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low

level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in

FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other

blocks are erase-protected. Only one bit can be set in EBR1 and EBR2 together; do not set two or

Section 18 Flash Memory

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more bits at the same time. When the on-chip flash memory is disabled, a read access to this

The flash memory block configuration is shown in table 18.4. To erase the entire flash memory,

each block must be erased in turn.

As the H8/3068F-ZTAT does not support on-board programming modes in mode 6, EBR1

18.3.4 Erase Block Register 2 (EBR2)

Bit 76543210

— — EB13 EB12 EB11 EB10 EB9 EB8

Initial value00000000

Read/Write R R R/W R/W R/W R/W R/W R/W

EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is

initialized to H'00 by a reset, in hardware standby mode and software standby mode, and when a

low level is input to the FWE pin. When a high level is input to the FWE pin and the SWE bit in

FLMCR1 is not set, it is initialized to bit 0. When a bit in EBR2 is set to 1, the corresponding

block can be erased. Other blocks are erase-protected. Only one bit can be set in EBR1 and EBR2

together; do not set two or more bits at the same time. When the on-chip flash memory is

disabled, a read will return H'00, and erasing is disabled.

The flash memory block configuration is shown in table 18.4. To erase the entire flash memory,

each block must be erased in turn.

As the H8/3068F-ZTAT does not support on-board programming modes in mode 6, EBR2

Note: Bits 7 and 4 in this register are read-only. These bits must not be set to 1. If bits 7 and 4

are set when an EBR1/EBR2 bit is set, EBR1/EBR2 will be initialized to H'00.

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Table 18.4 Flash Memory Erase Blocks

Block (Size) Addresses

EB0 (4 kbytes) H'000000 to H'000FFF

EB1 (4 kbytes) H'001000 to H'001FFF

EB2 (4 kbytes) H'002000 to H'002FFF

EB3 (4 kbytes) H'003000 to H'003FFF

EB4 (4 kbytes) H'004000 to H'004FFF

EB5 (4 kbytes) H'005000 to H'005FFF

EB6 (4 kbytes) H'006000 to H'006FFF

EB7 (4 kbytes) H'007000 to H'007FFF

EB8 (32 kbytes) H'008000 to H'00FFFF

EB9 (64 kbytes) H'010000 to H'01FFFF

EB10 (64 kbytes) H'020000 to H'02FFFF

EB11 (64 kbytes) H'030000 to H'03FFFF

EB12 (64 kbytes) H'040000 to H'04FFFF

EB13 (64 kbytes) H'050000 to H'05FFFF

18.3.5 RAM Control Register (RAMCR)

Bit 76543210

————RAMSRAM2RAM1RAM0

Initial value11110000

Read/Write RRRRR/WR/WR/WR/W

RAMCR specifies the area of flash memory to be overlapped with part of RAM when emulating

realtime flash memory programming. RAMCR is initialized to H'00 by a reset and in hardware

standby mode. RAMCR settings should be made in user mode or user program mode.

Flash memory area divisions are shown in table 18.5. To ensure correct operation of the

emulation function, the ROM for which RAM emulation is performed should not be accessed

immediately after this register has been modified. Normal execution of an access immediately

after register modification is not guaranteed.

Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.

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Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in

RAM. When RAMS = 1, all flash memory blocks are program/erase-protected.

Bit 3

RAMS Description

0 Emulation not selected

Program/er a se-protection of all flash me mory blocks is disabled (Initial value)

1 Emulation selected

Program/erase-protection of all flash memory blocks is enabled

Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together

with bit 3 to select the flash memory area to be overlapped with RAM. (See table 18.5.)

Table 18.5 Flash Memory Area Divisions

RAM Area Block Name RAMS RAM2 RAM1 RAM0

H'FFE000 to H'FFEFFF 4-kbyte RAM area 0 ***

H'000000 to H'000FFF EB0 (4 kbytes) 1 0 0 0

H'001000 to H'001FFF EB1 (4 kbytes) 1 0 0 1

H'002000 to H'002FFF EB2 (4 kbytes) 1 0 1 0

H'003000 to H'003FFF EB3 (4 kbytes) 1 0 1 1

H'004000 to H'004FFF EB4 (4 kbytes) 1 1 0 0

H'005000 to H'005FFF EB5 (4 kbytes) 1 1 0 1

H'006000 to H'006FFF EB6 (4 kbytes) 1 1 1 0

H'007000 to H'007FFF EB7 (4 kbytes) 1 1 1 1

*: Don’t care

Note: Flash memory emulation by RAM is not supported in mode 6 (single-chip normal mode);

therefore, although these bi ts can be written, they should not be set to 1.

When performing flash memory emulation by RAM, the RAME bit in SYSCR must be set to

Section 18 Flash Memory

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18.4 Overview of Operation

18.4.1 Mode Transitions

When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the

H8/3068F-ZTAT enters one of the operating modes shown in figure 18.2. In user mode, flash

memory can be read but not programmed or erased.

Flash memory can be programmed and erased in boot mode, user program mode, and PROM

mode.

Boot mode and user program mode cannot be used in the H8/3068F-ZTAT’s mode 6 (normal

mode with on-chip ROM enabled).

Section 18 Flash Memory

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Boot mode

On-board programming mode

User program

mode

User mode

with on-chip ROM

enabled

Reset state

PROM mode

RES = 0

FWE = 0 RES = 0

RES = 0

Notes: Only make a transition between user mode and user program mode when the CPU is not

accessing the flash memory.

1. RAM emulation possible

2. The H8/3068F-ZTAT is placed in PROM mode by means of a dedicated PROM writer.

3. MD

, MD

= (1, 0, 1) (1, 1, 0) (1, 1, 1)

FWE = 0

4. MD

, MD

= (1, 0, 1) (1, 1, 1)

FWE = 1

5. MD

, MD

(0, 0, 1) (0, 1, 1)

FWE = 1

Figure 18.2 Flash Memory Related State Transitions

State transitions between the normal and user modes and on-board programming mode are

performed by changing the FWE pin level from high to low or from low to high. To prevent

misoperation (erroneous programming or erasing) in these cases, the bits in the flash memory

control register (FLMCR1) should be cleared to 0 before making such a transition. After the bits

are cleared, a wait time is necessary. Normal operation is not guaranteed if this wait time is

insufficient.

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18.4.2 On-Board Programming Modes

Example of Boot Mode Operation

Flash memory

H8/3068F-ZTAT

RAM

Host

Programming control

program

SCI

Application

program

(old version)

New application

program

Flash memory

H8/3068F-ZTAT

RAM

Host

SCI

Application

program

(old version)

Boot program area

New application

program

Flash memory

H8/3068F-ZTAT

RAM

Host

SCI

Flash memory

prewrite-erase

Boot program

New application

program

Flash memory

H8/3068F-ZTAT

Program execution state

RAM

Host

SCI

New application

program

Boot program

Programming control

program

Boot program area

1. Initial state

The old program version or data remains

written in the flash memory. The user should

prepare the programming control program and

new application program beforehand in the

host.

2. Programming control program transfer

When boot mode is entered, the boot program

in the H8/3068F-ZTAT (originally incorporated

in the chip) is started and the programming

control program in the host is transferred to

RAM via SCI communication. The boot

program required for flash memory erasing is

automatically transferred to the RAM boot

program area.

3. Flash memory initialization

The erase program in the boot program area

(in RAM) is executed, and the flash memory is

initialized (to H'FF). In boot mode, total flash

memory erasure is performed, without regard

to blocks.

4. Writing new application program

The programming control program transferred

from the host to RAM is executed, and the new

application program in the host is written into

the flash memory.

Boot programBoot program

Programming control

program

Boot program area

Programming control

program

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Example of User Program Mode Operation

Flash memory

H8/3068F-ZTAT

RAM

Host

Programming/erase

control program

SCI

Boot program

New application

program

Flash memory

H8/3068F-ZTAT

RAM

Host

SCI

New application

program

Flash memory

H8/3068F-ZTAT

RAM

Host

SCI

Flash memory

erase

Boot program

New application

program

Flash memory

H8/3068F-ZTAT

Program execution state

RAM

Host

SCI

Boot program

Programming/erase

control program

Boot program

FWE assessment program

Transfer program

Application program

(old version) Application program

(old version)

FWE assessment program

Transfer program

New application

program

FWE assessment program

Transfer program

1. Initial state

The FWE assessment program that confirms

that user program mode has been entered, and

the program that will transfer the programming/

erase control program from flash memory to

on-chip RAM should be written into the flash

memory by the user beforehand. The

programming/erase control program should be

prepared in the host or in the flash memory.

3. Flash memory initialization

The programming/erase program in RAM is

executed, and the flash memory is initialized (to

H'FF). Erasing can be performed in block units,

but not in byte units.

4. Writing new application program

Next, the new application program in the host is

written into the erased flash memory blocks.

Do not write to unerased blocks.

2. Programming/erase control program transfer

When user program mode is entered, user

software recognizes this fact, executes the

transfer program in the flash memory, and

transfers the programming/erase control

program to RAM.

FWE assessment program

Transfer program

Programming/erase

control program

Programming/erase

control program

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18.4.3 Flash Memory Emulation in RAM

In the H8/3068F-ZTAT, flash memory programming can be emulated in real time by overlapping

the flash memory with part of RAM (“overlap RAM”). When the emulation block set in RAMCR

is accessed while the emulation function is being executed, data written in the overlap RAM is

read.

Emulation should be performed in user mode or user program mode.

Application program

Execution state

Flash memory

Emulation block

RAM

SCI

Overlap RAM

(Emulation is performed on data written

in RAM)

Figure 18.3 Reading Overlap RAM Data in User Mode/User Program Mode

When overlap RAM data is confirmed, clear the RAMS bit to cancel RAM overlap, and actually

perform writes to the flash memory in user program mode.

When the programming control program is transferred to RAM in on-board programming mode,

ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in

the overlap RAM to be rewritten.

Section 18 Flash Memory

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Application program

Flash memory RAM

SCI

Programming control program

Execution state

Overlap RAM

(program data)

Program data

Figure 18.4 Writing Overlap RAM Data in User Program Mode

Section 18 Flash Memory

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18.4.4 Block Configuration

The flash memory in the H8/3068F-ZTAT is divided into three 64-kbyte blocks, one 32-kbyte

block, and eight 4-kbyte blocks. Erasing can be carried out in block units.

Address H'5FFFF

Address H'00000

64 kbytes

32 kbytes

64 kbytes

384 kbytes

4 kbytes × 8

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18.5 On-Board Programming Mode

When pins are set to on-board programming mode and a reset-start is executed, the chip enters

the on-board programming state in which on-chip flash memory programming, erasing, and

verifying can be carried out. There are two operating modes in this mode—boot mode and user

program mode. The pin settings for entering each mode are shown in table 18.6. For a diagram of

the transitions to the various flash memory modes, see figure 18.2.

Boot mode and user program mode cannot be used in the H8/3068F-ZTAT’s mode 6 (on-chip

ROM enabled).

Table 18.6 On-Board Programming Mode Settings

Mode FWE MD2MD1MD0

Boot mode Mode 5 1*10*201

Mode 7 0*211

User program mode Mode 5 1 0 1

Mode 7 1 1 1

Notes: 1. For the High l evel input timing, see items 6 and 7 of Notes on Using the Boot Mode.

2. In boot mode, the MD2 setting should be the inverse of the input.

In the boot mode in the H8/3068F-ZTAT, the levels of the mode pins (MD2 to MD0) are

reflected i n mode select bits 2 to 0 (MDS2 to MDS0) in the mode control register

(MDCR).

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18.5.1 Boot Mode

When boot mode is used, a flash memory programming control program must be prepared

beforehand in the host, and SCI channel 1, which is to be used, must be set to asynchronous

mode.

When a reset-start is executed after setting the H8/3068F-ZTAT’ pins to boot mode, the boot

program already incorporated in the MCU is activated, and the programming control program

prepared beforehand in the host is transmitted sequentially to the H8/3068F-ZTAT, using the SCI.

In the H8/3068F-ZTAT, the programming control program received via the SCI is written into the

programming control program area in on-chip RAM. After the transfer is completed, control

branches to the start address (H'FFC720) of the programming control program area and the

programming control program execution state is entered (flash memory programming/erasing can

be performed).

Figure 18.5 shows a system configuration diagram when using boot mode, and figure 18.6 shows

the boot program mode execution procedure.

RxD1

TxD1SCI1

H8/3068F-ZTAT

Flash memory

Reception of programming data

Transmission of verify data

Host

On-chip RAM

Figure 18.5 System Configuration When Using Boot Mode

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n = N?

Yes

Set pins to boot program mode and execute reset-start

n = 1

n + 1 → n

Host transfers data (H'00) continuously at prescribed

bit rate

H8/3068F-ZTAT measures low period of H'00 data

transmitted by host

After bit rate adjustment, H8/3068F-ZTAT transmits one

H'00 data byte to host to indicate end of adjustment

Host confirms normal reception of bit rate adjustment

end indication (H'00), and transmits one H'55 data byte

After receiving H'55, H8/3068F-ZTAT transmits one

H'AA byte to host

Host transmits number of programming control program

bytes (N), upper byte followed by lower byte

H8/3068F-ZTAT transmits received number of bytes to

host as verify data (echo-back)

Host transmits programming control program

sequentially in byte units

H8/3068F-ZTAT transmits received programming

control program to host as verify data (echo-back)

Transfer received programming control program to

on-chip RAM

End of transmission

Check flash memory data, and if data has already been

written, erase all blocks

After confirming that all flash memory data has been

erased, H8/3068F-ZTAT transmits one H'AA byte to

host

Execute programming control program transferred to

on-chip RAM

Start

H8/3068F-ZTAT calculates bit rate and sets value in bit

rate register

Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error

indication, and the erase operation and subsequent operations are halted.

Figure 18.6 Boot Mode Execution Procedure

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Automatic SCI Bit Rate Adjustment:

Start

bit Stop

bit

D0 D1 D2 D3 D4 D5 D6 D7

Low period (9 bits) measured (H'00 data) High period

(1 or more bits)

When boot mode is initiated, the H8/3068F-ZTAT measures the low period of the asynchronous

SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive

format should be set as 8-bit data, 1 stop bit, no parity. The H8/3068F-ZTAT calculates the bit

rate of the transmission from the host from the measured low period, and transmits one H'00 byte

to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment

end indication (H'00) has been received normally, and transmit one H'55 byte to the H8/3068F-

ZTAT. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the

above operations. Depending on the host’s transmission bit rate and the H8/3068F-ZTAT’s

system clock frequency, there will be a discrepancy between the bit rates of the host and the

H8/3068F-ZTAT. To ensure correct SCI operation, the host’s transfer bit rate should be set to

4800, 9600, or 19,200 bps*.

Table 18.7 shows typical host transfer bit rates and system clock frequencies for which automatic

adjustment of the H8/3068F-ZTAT bit rate is possible. The boot program should be executed

within this system clock range.

Table 18.7 System Clock Frequencies for which Automatic Adjustment of H8/3068F-

ZTAT Bit Rate is Possible

Host Bit Rate (b ps) System Clock Frequency for which Automatic

Adjustment of H8/3068F-ZTAT Bit Rate is Possible (MHz)

19,200 16 to 25

9,600 8 to 25

4,800 4 to 25

Note: * Only use a setting of 4800, 9600, or 19200 bps for the host’s bit rate. No other settings

can be used.

Although the H8/3068F-ZTAT may also perform automatic bit rate adjustment with bit

rate and system clock combinations other than those shown in table 18.7, a degree of

error will arise between the bit rates of the host and the H8/3068F-ZTAT, and subsequent

transfer will not be performed normally. Therefore, only a combination of bit rate and

Section 18 Flash Memory

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system clock frequency within one of the ranges shown in table 18.7 can be used for boot

mode execution.

On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an

area used by the boot program and an area to which the user program is transferred via the SCI, as

shown in figure 18.7. The boot program area becomes available when a transition is made to the

execution state for the user program transferred to RAM.

H'FFBF20

H'FFC71F

H'FFC720

User program

transfer area

Boot program

area

H'FFFF1F

Note: The boot program area cannot be used until a transition is made to the execution state

for the user program transferred to RAM. Note also that the boot program remains in

this area in RAM even after control branches to the user program.

Figure 18.7 RAM Areas in Boot Mode

Notes on Use of Boot Mode:

1. When the H8/3068F-ZTAT chip comes out of reset in boot mode, it measures the low period

of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends,

it takes about 100 states for the chip to get ready to measure the low period of the RxD1 input.

2. In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all

flash memory blocks are erased. Boot mode is for use when user program mode is

unavailable, such as the first time on-board programming is performed, or if the program

activated in user program mode is accidentally erased.

3. Interrupts cannot be used while the flash memory is being programmed or erased.

4. The RxD1 and TxD1 lines should be pulled up on the board.

5. Before branching to the user program the H8/3068F-ZTAT terminates transmit and receive

operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits to 0 in the serial

Section 18 Flash Memory

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control register (SCR)), but the adjusted bit rate value remains set in the bit rate register

(BRR). The transmit data output pin, TxD1, goes to the high-level output state (P91DDR = 1 in

P9DDR, P91DR = 1 in P9DR).

The contents of the CPU’s internal general registers are undefined at this time, so these

registers must be initialized immediately after branching to the user program. In particular,

since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be

specified for use by the user program.

The initial values of other on-chip registers are not changed.

6. Boot mode can be entered by setting pins MD0 to MD2 and FWE in accordance with the mode

setting conditions shown in table 18.6, and then executing a reset-start.

a. When switching from boot mode to normal mode, the boot mode state within the chip

must first be cleared by reset input via the

RES

pin*1. The

RES

pin must be held low for at

least 20 system clock cycles.*3

b. Do not change the input levels of the mode pins (MD2 to MD0) or the FWE pin in boot

mode. To change the mode, the

RES

pin must first be driven low to set the reset state.

Also, if a watchdog timer reset occurs in the boot mode state, the MCU’s internal state will

not be cleared, and the on-chip boot program will be restarted regardless of the mode pin

states.

c. The FWE pin must not be driven low while the boot program is running or flash memory is

being programmed or erased*2.

7. If the mode pin input levels are changed (for example, from low to high) during a reset, the

state of ports with multiplexed address functions and bus control output signals (

CSn

LWR

HWR

) may also change according to the change in the MCU’s operating mode.

Therefore, care must be taken to make pin settings to prevent these pins from being used

directly as output signal pins during a reset, or to prevent collision with signals outside the

MCU.

Section 18 Flash Memory

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H8/3068F-ZTAT

MD2

MD1

MD0

FWE

RES

CSn

System

control

unit

External

memory,

etc.

Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS)

with respect to the reset release timing.

2. For further information on FWE application and disconnection, see section 18.11,

Flash Memory Programming and Erasing Precautions.

3. See section 4.2.2, Reset Sequence, and section 18.11, Flash Memory Programming

and Erasing Precautions. The H8/3068F-ZTAT requires a minimum of 20 system

clock cycles for a reset during operation.

18.5.2 User Program Mode

When set to user program mode, the H8/3068F-ZTAT can program and erase its flash memory by

executing a user program/erase control program. Therefore, on-board reprogramming of the on-

chip flash memory can be carried out by providing on-board means of FWE control and supply of

programming data, and storing a program/erase control program in part of the program area as

necessary.

To select user program mode, select a mode that enables the on-chip ROM (mode 5 or 7), and

apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash

memory operate as they normally would in modes 5 and 7.

Flash memory programming/erasing should not be carried out in mode 6. When mode 6 is set, the

FWE pin must be driven low.

The flash memory itself cannot be read while being programmed or erased, so the program that

performs programming should be placed in external memory or transferred to RAM and executed

there.

Section 18 Flash Memory

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Figure 18.8 shows the execution procedure when user program mode is entered during program

execution in RAM. It is also possible to start from user program mode in a reset-start.

MD2–MD0 = 101 or 111

Reset-start

Transfer programming/erase control

program to RAM

Branch to programming/erase control

program in RAM area

FWE = high

(user program mode)

Execute programming/erase control

program in RAM

(flash memory rewriting)

Clear SWE bit, then release FWE

(user program mode clearing)

Branch to application program

in flash memory

Write FWE assessment program and transfer

program (and programming/erase control

program if necessary) beforehand

Notes: 1. Do not apply a constant high level to the FWE pin. A high level should be applied to the

FWE pin only when programming or erasing flash memory (including execution of flash

memory emulation by RAM). Also, while a high level is applied to the FWE pin, the

watchdog timer should be activated to prevent overprogramming or overerasing due to

program runaway, etc.

2. For further information on FWE application and disconnection, see section 18.11, Flash

Memory Programming and Erasing Precautions.

3. In order to execute a normal read of flash memory in user program mode, the

programming/erase program must not be executing. It is thus necessary to ensure that

bits 6 to 0 in FLMCR1 are cleared to 0.

Figure 18.8 Example of User Program Mode Execution Procedure

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18.6 Flash Memory Programming/Erasing

A software method, using the CPU, is employed to program and erase flash memory in the on-

board programming modes. There are four flash memory operating modes: program mode, erase

mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses

H'000000 to H'03FFFF are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.

The flash memory cannot be read while being programmed or erased. Therefore, the program

(user program) that controls flash memory programming/erasing should be located and executed

in on-chip RAM or external memory.

See section 18.11, Flash Memory Programming and Erasing Precautions, for points to be noted

when programming or erasing the flash memory. In the following operation descriptions, wait

times after setting or clearing individual bits in FLMCR1 are given as parameters; for details of

the wait times, see section 21.1.6, Flash Memory Characteristics.

Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and

P bits in FLMCR1 is executed by a program in flash memory.

2. When programming or erasing, set FWE to 1 (programming/erasing will not be

executed if FWE = 0).

3. Programming must be executed in the erased state. Do not perform additional

programming on addresses that have already been programmed.

Section 18 Flash Memory

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Normal mode

On-board

programming mode

Software programming

disable state

Erase setup

state Erase mode

Program mode

Erase-verify

mode

Program

setup state

Program-verify

mode

SWE = 1

SWE = 0

FWE = 1 FWE = 0

E = 1

E = 0

P = 1

P = 0

Software

programming

enable

state

Notes: In order to perform a normal read of flash memory, SWE must be cleared to 0. Also note that verify-reads

can be performed during the programming/erasing process.

1. : Normal mode : On-board programming mode

2. Do not make a state transition by setting or clearing multiple bits simultaneously.

3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing

through the software programming enable state.

4. After a transition from program mode to the program setup state, do not enter program mode without

passing through the software programming enable state.

ESU = 0

ESU = 1

PSU = 1

PSU = 0

PV = 1

PV = 0

EV = 0

EV = 1

Figure 18.9 FLMCR1 Bit Settings and State Transitions

Section 18 Flash Memory

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18.6.1 Program Mode

When writing data or programs to flash memory, the program/program-verify flowchart shown in

figure 18.10 should be followed. Performing programming operations according to this flowchart

will enable data or programs to be written to flash memory without subjecting the device to

voltage stress or sacrificing program data reliability. Programming should be carried out 128

bytes at a time.

The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and

the maximum number of programming operations (N) are shown in table 21.10 in section 21.1.6,

Flash Memory Characteristics.

Following the elapse of (tsswe) µs or more after the SWE bit is set to 1 in FLMCR1, 128-byte data

is written consecutively to the write addresses. The lower 8 bits of the first address written to

must be H'00 and H'80, 128 consecutive byte data transfers are performed. The program address

and program data are latched in the flash memory. A 128-byte data transfer must be performed

even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra

addresses.

Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.

Set a value greater than (tspsu + tsp + tcp + tcpsu) µs as the WDT overflow period. Preparation for

entering program mode (program setup) is performed next by setting the PSU bit in FLMCR1.

The operating mode is then switched to program mode by setting the P bit in FLMCR1 after the

elapse of at least (tspsu) µs. The time during which the P bit is set is the flash memory

programming time. Make a program setting so that the time for one programming operation is

within the range of (tsp) µs.

The wait time after P bit setting must be changed according to the degree of progress through the

programming operation. For details see “Notes on Program/Program-Verify Mode.”

Section 18 Flash Memory

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18.6.2 Program-Verify Mode

In program-verify mode, the data written in program mode is read to check whether it has been

correctly written in the flash memory.

After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least

(tcp) µs before clearing the PSU bit to exit program mode. After exiting program mode, the

watchdog timer setting is also cleared. The operating mode is then switched to program-verify

mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write

of H'FF data should be made to the addresses to be read. The dummy write should be executed

after the elapse of (tspv) µs or more. When the flash memory is read in this state (verify data is

read in 16-bit units), the data at the latched address is read. Wait at least (tspvr) µs after the dummy

write before performing this read operation. Next, the originally written data is compared with the

verify data, and reprogram data is computed (see figure 18.10) and transferred to RAM. After

verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least

(tcpv) µs, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode

again, and repeat the program/program-verify sequence as before. The maximum number of

repetitions of the program/program-verify sequence is indicated by the maximum programming

count (N). Leave a wait time of at least (tcswe) µs after clearing SWE.

Notes on Program/Program-Verify Procedure

1. The program/program-verify procedure for the H8/3068F-ZTAT uses a 128-byte-unit

programming algorithm.

In order to perform 128-byte-unit programming, the lower 8 bits of the write start address

must be H'00 or H'80.

2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer

should be used.

128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write

H'FF data to the extra addresses.

3. Verify data is read in word units.

4. The write pulse is applied and a flash memory write executed while the P bit in FLMCR1 is

set. In the H8/3068F-ZTAT, write pulses should be applied as follows in the

program/program-verify procedure to prevent voltage stress on the device and loss of write

data reliability.

a. After write pulse application, perform a verify-read in program-verify mode and apply a

write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write

bits in the 128-byte write data are read as 0 in the verify-read operation, the

program/program-verify procedure is completed. In the H8/3068F-ZTAT, the number of

Section 18 Flash Memory

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loops in reprogramming processing is guaranteed not to exceed the maximum value of the

maximum programming count (N).

b. After write pulse application, a verify-read is performed in program-verify mode, and

programming is judged to have been completed for bits read as 0. The following

processing is necessary for programmed bits.

When programming is completed at an early stage in the program/program-verify

procedure:

If programming is completed in the 1st to 6th reprogramming processing loop, additional

programming should be performed on the relevant bits. Additional programming should

only be performed on bits which first return 0 in a verify-read in certain reprogramming

processing.

When programming is completed at a late stage in the program/program-verify procedure:

If programming is completed in the 7th or later reprogramming processing loop, additional

programming is not necessary for the relevant bits.

c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing

should be executed. If a bit for which programming has been judged to be completed is

read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit.

5. The period for which the P bit in FLMCR1 is set (the write pulse width) should be changed

according to the degree of progress through the program/program-verify procedure. For

detailed wait time specifications, see section 21.1.6, Flash Memory Characteristics.

Item Symbol Item Symbol

tsp When reprogramming loop count (n) is 1 to 6 tsp30Wait time after P

bit setting When reprogramming loop count (n) is 7 or more tsp200

In case of additi onal programming processing*tsp10

Note: *Additional programming processing is necessary only when the reprogramming loop count

(n) is 1 to 6.

6. The program/program-verify flowchart for the H8/3068F-ZTAT is shown in figure 18.10.

To cover the points noted above, bits on which reprogramming processing is to be executed,

and bits on which additional programming is to be executed, must be determined as shown

below.

Since reprogram data and additional-programming data vary according to the progress of the

programming procedure, it is recommended that the following data storage areas (128 bytes

each) be provided in RAM.

Section 18 Flash Memory

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Reprogram Data Computation Table

(D)

Result of Verify-Read

after Write Pulse

Application (V) (X)

Result of Operation Comments

0 0 1 Programming completed: reprogramming

processing not to be executed

0 1 0 Programming incomplete: reprogramming

processing to be executed

10 1 

1 1 1 Still in erased state: no action

Legend

(D): Source data of bits on which programming is executed

(X): Source data of bits on which reprogramming i s executed

Additional-Programming Data Computation Table

(X')

Result of Verify-Read

after Write Pulse

Application (V) (Y)

Result of Operation Comments

0 0 0 Programming by write pul se application

judged to be completed: additional

programming processing to be executed

0 1 1 Programming by write pul se application

incomplete: additional programming

processing not to be executed

1 0 1 Programming already completed: additional

programming processing not to be executed

1 1 1 Still in erased state: no action

Legend

(Y): Data of bits on which additional programming is executed

(X'): Data of bits on which reprogramming is executed in a certain reprogramming loop

7. It is necessary to execute additional programming processing during the course of the

H8/3068F-ZTAT program/program-verify procedure. However, once 128-byte-unit

programming is finished, additional programming should not be carried out on the same

address area. When executing reprogramming, an erase must be executed first. Note that

normal operation of reads, etc., is not guaranteed if additional programming is performed on

addresses for which a program/program-verify operation has finished.

Section 18 Flash Memory

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START

End of programming

Set SWE bit in FLMCR1

Start of programming

Write pulse application subroutine

Wait (t

sswe

) µs

Sub-Routine Write Pulse

End Sub

Set PSU bit in FLMCR1

WDT enable

Disable WDT

Number of Writes (n)

998

999

1000

Note: 6. Write Pulse Width

Write Time (tsp) µsec

200

Wait (t

spsu

) µs

Set P bit in FLMCR1

Wait (t

) µs

Clear P bit in FLMCR1

Wait (t

) µs

Clear PSU bit in FLMCR1

Wait (t

cpsu

) µs

n= 1

m= 0

NG NG

Wait (t

spv

) µs

Wait (t

spvr

) µs

Start of programming

Programming halted

*5*7

Wait (t

cpv

) µs

Write pulse

Sub-Routine-Call

Set PV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Write data =

verify data?

Transfer reprogram data to reprogram data area

Reprogram data computation

Transfer additional-programming data to

additional-programming data area

Additional-programming data computation

Clear PV bit in FLMCR1

Clear SWE bit in FLMCR1

m = 1

Reprogram

See Note *6 for pulse width

m= 0 ?

Increment address

Programming failure

Clear SWE bit in FLMCR1

Wait (t

cswe

) µs

≥

n ?

Wait (t

cswe

) µs

n ≥ N?

n ← n + 1

Original Data

(D)

Verify Data

(V)

Reprogram Data

(X)

Comments

Programming completed

Still in erased state; no action

Programming incomplete;

reprogram

Note: Use a 10 µs write pulse for additional programming.

Consecutively write 128-byte data in reprogram

data area in RAM to flash memory

RAM

Program data storage

area (128 bytes)

Reprogram data storage

area (128 bytes)

Additional-programming

data storage area

(128 bytes)

Store 128-byte program data in program

data area and reprogram data area

Write Pulse (Additional programming)

Sub-Routine-Call

128-byte

data verification completed?

Consecutively write 128-byte data in additional-

programming data area in RAM to flash memory

Reprogram Data Computation Table

Reprogram Data

(X')

Verify Data

(V)

Additional-

Programming Data

(Y)

000

Comments

Additional programming

to be executed

Additional programming

not to be executed

Additional programming

not to be executed

Additional programming

not to be executed

100

Additional-Programming Data Computation Table

Perform programming in the erased state.

Do not perform additional programming

on previously programmed addresses.

Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.

A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.

2. Verify data is read in 16-bit (word) units.

3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for

which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to

programming once again if the result of the subsequent verify operation is NG.

4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional-programming data must be provided in

RAM. The contents of the reprogram data area and additional-programming data area are modified as programming proceeds.

5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of

additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.

7. The wait times and value of N are shown in section 21.1.6, Flash Memory Characteristics.

Figure 18.10 Program/Program-Verify Flowchart (128-Byte Programming)

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 631 of 910

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18.6.3 Erase Mode

When erasing flash memory, the single-block erase flowchart shown in figure 18.11 should be

followed.

The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and

the maximum number of erase operations (N) are shown in table 21.10 in section 21.1.6, Flash

Memory Characteristics.

To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in

erase block register 1 and 2 (EBR1, EBR2) at least (tsswe) µs after setting the SWE bit to 1 in

FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program

runaway, etc. Set a value greater than (tse) ms + (tsesu + tce + tcesu) µs as the WDT overflow period.

Preparation for entering erase mode (erase setup) is performed next by setting the ESU bit in

FLMCR1. The operating mode is then switched to erase mode by setting the E bit in FLMCR1

after the elapse of at least (tsesu) µs. The time during which the E bit is set is the flash memory

erase time. Ensure that the erase time does not exceed (tse) ms.

Note: With flash memory erasing, preprogramming (setting all memory data in the memory to

be erased to all 0) is not necessary before starting the erase procedure.

18.6.4 Erase-Verify Mode

In erase-verify mode, data is read after memory has been erased to check whether it has been

correctly erased.

After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (tce) µs

before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer

setting is also cleared. The operating mode is then switched to erase-verify mode by setting the

EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be

made to the addresses to be read. The dummy write should be executed after the elapse of (tsev) µs

or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data

at the latched address is read. Wait at least (tsevr) µs after the dummy write before performing this

read operation. If the read data has been erased (all 1), a dummy write is performed to the next

address, and erase-verify is performed. If the read data is unerased, set erase mode again, and

repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the

erase/erase-verify sequence is indicated by the maximum erase count (N). When verification is

completed, exit erase-verify mode, and wait for at least (tcev) µs. If erasure has been completed on

all the erase blocks, clear the SWE bit in FLMCR1, and leave a wait time of at least (tcswe) µs.

If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and

repeat the erase/erase-verify sequence as before.

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 632 of 910

REJ09B0258-0300

End of erasing

Start

Set SWE bit in FLMCR1

Set ESU bit in FLMCR1

Set E bit in FLMCR1

Wait (tsswe) µs

Wait (tsesu) µs

n = 1

Set EBR1 or EBR2

Enable WDT

*3 *4

*5*5

Wait (tse) ms

Wait (tce) µs

Wait (tcesu) µs

Wait (tsev) µs

Set block start address as verify address

Wait (tsevr) µs

Wait (tcev) µs

Start of erase

Clear E bit in FLMCR1

Clear ESU bit in FLMCR1

Set EV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Clear EV bit in FLMCR1

Wait (tcev) µs

Clear EV bit in FLMCR1

Re-erase

Clear SWE bit in FLMCR1

Disable WDT

End of erase

Verify data = all 1s?

Last address of block?

Erase failure

Clear SWE bit in FLMCR1

n ≥ N?

Yes

n ← n + 1

Increment

address

Wait (tcswe) µsWait (tcswe) µs

Notes: 1. Prewriting (setting erase block data to all 0s) is not necessary.

2. Verify data is read in 16-bit (word) units.

3. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously.

4. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.

5. The wait times and the value of N are shown in section 21.1.6, Flash Memory Characteristics.

Perform erasing in block units.

Figure 18.11 Erase/Erase-Verify Flowchart (Single-Block Erasing)

Section 18 Flash Memory

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18.7 Flash Memory Protection

There are three kinds of flash memory program/erase protection: hardware, software, and error

protection.

18.7.1 Hardware Protection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted. In this state, the settings in flash memory control register 1 (FLMCR1) and

erase block registers 1 and 2 (EBR1, EBR2) are reset. In the error protection state, the FLMCR1,

EBR1, and EBR2 settings are retained; the P bit and E bit can be set, but a transition is not made

to program mode or erase mode. (See table 18.8.)

Table 18.8 Hardware Protection

Function

Item Description Program Erase Verify

FWE pin

protection • When a low level is input to the FWE pi n,

FLMCR1, EBR1, and EBR2 are initialized, and

the program/erase-protected state is entered.

Not

possible*1Not

possible*3Not

possible

Reset/

standby

protection

• In a reset (including a WDT overflow reset)

and in standby mode, FLMCR1, FLMCR2,

EBR1, and EBR2 are initialized, and the

program/erase-protected state is entered.

• In a reset via the

RES

pin, the reset state is

not entered unless the

RES

pin i s held low

until oscillation stabilizes after powering on. In

the case of a reset during operati on, hold the

RES

pin l ow for the

RES

pulse width specified

in the AC Characteristics section.*4

Not

possible Not

possible*3Not

possible

Error

protection • When a microcomputer operation error (error

generation (FLER = 1)) was detected while

flash memory was being programmed/erased,

error protection i s enabled. At this time, the

FLMCR1, EBR1, and EBR2 settings are held,

but programming/erasing is aborted at the time

the error was generated. Error protection is

released only by a reset via the

RES

pin or a

WDT reset, or i n the hardware standby mode.

Not

possible Not

possible*3Possible*2

Notes: 1. The RAM area that overlapped flash memory is deleted.

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 634 of 910

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2. It is possible to perform a program-verify operation on the 128 bytes being

programmed, or an erase-verify operation on the block being erased.

3. All blocks are unerasable and block-by-block specification is not possible.

4. See section 4.2.2, Reset Sequence, and section 18.11, Flash Memory Programming

and Erasing Precautions. The H8/3068F -ZTAT requires a minimum of 20 system clock

cycles for a reset duri ng operation.

18.7.2 Software Protection

Software protection can be implemented by setting the erase block register 1 (EBR1), erase block

protection, setting the P or E bit in the flash memory control register 1 (FLMCR1) does not cause

a transition to program mode or erase mode. (See table 18.9.)

Table 18.9 Software Protection

Functions

Item Description Program Erase Verify

Block

protection • Erase protection can be set for individual

blocks by settings in erase block register 1

(EBR1) and erase block register 2

(EBR2)*2. However, programming

protection i s disabled.

• Setting EBR1 and EBR2 to H'00 places all

blocks in the erase-protected state.

—Not

possible Possible

Emulation

protection • Setting the RAMS bit 1 in RAMCR places

all blocks i n the program/erase-protected

state.

Not

possible*1Not

possible*3Possible

Notes: 1. The RAM area overlapping flash memory can be written to.

2. When not erasing, set EBR1 and EBR2 to H'00.

3. All blocks are unerasable and block-by-block specification is not possible.

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 635 of 910

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18.7.3 Error Protection

In error protection, an error is detected when MCU runaway occurs during flash memory

programming/erasing*1, or operation is not performed in accordance with the program/erase

algorithm, and the program/erase operation is aborted. Aborting the program/erase operation

prevents damage to the flash memory due to overprogramming or overerasing.

If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in

the flash memory status register (FLMSR2) and the error protection state is entered. FLMCR1,

FLMCR2, EBR1, and EBR2 settings*3 are retained, but program mode or erase mode is aborted

at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-

setting the P or E bit in FLMCR. However, PV and EV bit setting is enabled, and a transition can

be made to verify mode*2.

FLER bit setting conditions are as follows:

1. When flash memory is read during programming/erasing (including a vector read or

instruction fetch)

2. Immediately after the start of exception handling during programming/erasing (excluding

reset, illegal instruction, trap instruction, and division-by-zero exception handling)

3. When a SLEEP instruction (including software standby) is executed during

programming/erasing

4. When the bus is released during programming/erasing

Error protection is released only by a

RES

pin or WDT reset, or in hardware standby mode.

Notes: 1. State in which the P bit or E bit in FLMCR1 is set to 1. Note that NMI input is

disabled in this state.

2. It is possible to perform a program-verify operation on the 128 bytes being

programmed, or an erase-verify on the block being erased.

3. FLMCR1, EBR1, and EBR2 can be written to. However, the registers are initialized if

a transition is made to software standby mode while in the error protection state.

Figure 18.12 shows the flash memory state transition diagram.

Section 18 Flash Memory

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RD VF PR ER FLER = 0

Error

occurrence

RES = 0 or STBY = 0

RES = 0 or

STBY = 0

RD VF PR ER INIT FLER = 0

Program mode

Erase mode Reset or standby

(hardware protection)

RD VF PR ER FLER = 1 RD VF PR ER INIT FLER = 1

Error protection mode Error protection mode

(software standby)

Software

standby mode

FLMCR1, EBR1, EBR2

initialization state

FLMCR1, FLMCR2,

EBR1, EBR2

initialization state

Software standby

mode release

RD: Memory read possible

VF: Verify-read possible

PR: Programming possible

ER: Erasing possible

RD: Memory read not possible

VF: Verify-read not possible

PR: Programming not possible

ER: Erasing not possible

INIT: Register initialization state

RES = 0 or

STBY = 0

Error occurrence

(software standby)

Figure 18.12 Flash Memory State Transitions

(When High Level is Applied to FWE Pin in Mode 5 or 7 (On-Chip ROM Enabled))

The error protection function is invalid for abnormal operations other than the FLER bit setting

conditions. Also, if a certain time has elapsed before this protection state is entered, damage may

already have been caused to the flash memory. Consequently, this function cannot provide

complete protection against damage to flash memory.

To prevent such abnormal operations, therefore, it is necessary to ensure correct operation in

accordance with the program/erase algorithm, with the flash write enable (FWE) voltage applied,

and to conduct constant monitoring for MCU errors, internally and externally, using the watchdog

timer or other means. There may also be cases where the flash memory is in an erroneous

programming or erroneous erasing state at the point of transition to this protection mode, or

where programming or erasing is not properly carried out because of an abort. In cases such as

these, a forced recovery (program rewrite) must be executed using boot mode. However, it may

also happen that boot mode cannot be normally initiated because of overprogramming or

overerasing.

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 637 of 910

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18.8 Flash Memory Emulation in RAM

Making a setting in the RAM control register (RAMCR) enables part of RAM to be overlapped

onto the flash memory area so that data to be written to flash memory can be emulated in RAM in

real time. After the RAMCR setting has been made, accesses can be made from the flash memory

area or the RAM area overlapping flash memory. Emulation can be performed in user mode and

user program mode. Figure 18.13 shows an example of emulation of realtime flash memory

programming.

Yes

Set RAMCR

Write tuning data to overlap RAM

Execute application program

Tuning OK?

Clear RAMCR

Write to flash memory emulation block

Start of emulation program

End of emulation program

Figure 18.13 Flowchart of Flash Memory Emulation in RAM

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 638 of 910

REJ09B0258-0300

H'00000

H'01000

H'02000

H'03000

H'04000

H'05000

H'06000

H'07000

H'08000

H'5FFFF

Flash memory

EB8 to EB13

This area can be accessed

from both the RAM area

and flash memory area

EB0

EB1

EB2

EB3

EB4

EB5

EB6

EB7

H'FFE000

H'FFEFFF

H'FFFF1F

On-chip RAM

Figure 18.14 Example of RAM Overlap Operation

Example of Flash Memory Block Area EB0 Overlapping

1. Set bits RAMS and RAM2 to RAM0 in RAMCR to 1,0, 0, 0, to overlap part of RAM onto the

area (EB0) for which realtime programming is required.

2. Realtime programming is performed using the overlapping RAM.

3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.

4. The data written in the overlapping RAM is written into the flash memory space (EB0).

Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks

regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting

the P or E bit in FLMCR1 will not cause a transition to program mode or erase mode.

When actually programming or erasing a flash memory area, the RAMS bit should be

cleared to 0.

2. A RAM area cannot be erased by execution of software in accordance with the erase

algorithm while flash memory emulation in RAM is being used.

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 639 of 910

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3. Block area EB0 contains the vector table. When performing RAM emulation, the

vector table is needed in the overlap RAM.

4. As in on-board programming mode, care is required when applying and releasing FWE

to prevent erroneous programming or erasing. To prevent erroneous programming and

erasing due to program runaway during FWE application, in particular, the watchdog

timer should be set when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while

the emulation function is being used.

5. When the emulation function is used, NMI input is prohibited when the P bit or E bit

is set to 1 in FLMCR1, in the same way as with normal programming and erasing.

The P and E bits are cleared by a reset (including a watchdog timer reset), in standby

mode, when a high level is not being input to the FWE pin, or when the SWE bit in

FLMCR1 is 0 while a high level is being input to the FWE pin.

Section 18 Flash Memory

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18 .9 NMI Input Disabl ing Conditions

All interrupts, including NMI input, should be disabled while flash memory is being programmed

or erased (while the P bit or E bit is set in FLMCR1), and while the boot program is executing in

boot mode*1, to give priority to the program or erase operation. There are three reasons for this:

1. NMI input during programming or erasing might cause a violation of the programming or

erasing algorithm, with the result that normal operation could not be assured.

2. In the NMI exception handling sequence during programming or erasing, the vector would not

be read correctly*2, possibly resulting in MCU runaway.

3. If NMI input occurred during boot program execution, it would not be possible to execute the

normal boot mode sequence.

For these reasons, in on-board programming mode alone there are conditions for disabling NMI

input, as an exception to the general rule. However, this provision does not guarantee normal

erasing and programming or MCU operation. All interrupt requests (exception handling and bus

release), including NMI, must therefore be restricted inside and outside the MCU during FWE

application. NMI input is also disabled in the error protection state and while the P or E bit

remains set in FLMCR1 during flash memory emulation in RAM.

Notes: 1. This is the interval until a branch is made to the boot program area in the on-chip

RAM (This branch takes place immediately after transfer of the user program is

completed). Consequently, after the branch to the RAM area, NMI input is enabled

except during programming and erasing. Interrupt requests must therefore be disabled

inside and outside the MCU until the user program has completed initial programming

(including the vector table and the NMI interrupt handling routine).

2. The vector may not be read correctly in this case for the following two reasons:

•If flash memory is read while being programmed or erased (while the P bit or E bit

is set in FLMCR1), correct read data will not be obtained (undetermined values will

be returned).

•If the entry in the interrupt vector table has not been programmed yet, interrupt

exception handling will not be executed correctly.

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 641 of 910

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18.10 Flash Memory PROM Mode

The H8/3068F-ZTAT has a PROM mode as well as the on-board programming modes for

programming and erasing flash memory. In PROM mode, the on-chip ROM can be freely

programmed using a general-purpose PROM writer that supports the Renesas Technology

microcomputer device type with 256-kbyte on-chip flash memory.

18.10.1 Socket Adapters and Memory Map

In PROM mode using a PROM writer, memory reading (verification) and writing and flash

memory initialization (total erasure) can be performed. For these operations, a special socket

adapter is mounted in the PROM writer. The socket adapter product codes are given in table

18.10. In the H8/3068F-ZTAT PROM mode, only the socket adapters shown in this table should

be used.

Table 18.10 H8/3068F-ZTAT Socket Adapter Product Codes

Product Code Package Socket Adapter

Product Code Manufacturer

HD64F3068F 100-pin QFP (FP-100B) ME3064ESHF1H

HD64F3068TE 100-pin TQFP (TFP-100B) ME3064ESNF1H

MINATO

ELECTRONICS INC.

HD64F3068F 100-pin QFP (FP-100B) HF306BQ100D4001 DATA I/O JAPAN CO.

HD64F3068TE 100-pin TQFP (TFP-100B) HF306BT100D4001

Figure 18.15 shows the memory map in PROM mode.

H8/3068F-ZTAT

H'000000

H'05FFFF

H'00000

H'5FFFF

MCU mode PROM mode

On-chip ROM

Figure 18.15 Memory Map in PROM Mode

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 642 of 910

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18.10.2 Notes on Use of PROM Mode

1. A write to a 128-byte programming unit in PROM mode should be performed once only.

Erasing must be carried out before reprogramming an address that has already been

programmed.

2. When using a PROM writer to reprogram a device on which on-board programming/erasing

has been performed, it is recommended that erasing be carried out before executing

programming.

3. The memory is initially in the erased state when the device is shipped by Renesas Technology.

For samples for which the erasure history is unknown, it is recommended that erasing be

executed to check and correct the initialization (erase) level.

4. The H8/3068F-ZTAT does not support a product identification mode as used with general-

purpose EPROMs, and therefore the device name cannot be set automatically in the PROM

writer.

5. Refer to the instruction manual provided with the socket adapter, or other relevant

documentation, for information on PROM writers and associated program versions that are

compatible with the PROM mode of the H8/3068F-ZTAT.

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 643 of 910

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18.11 Flash Memory Programming and Erasing Precautions

Precautions concerning the use of on-board programming mode, the RAM emulation function,

and PROM mode are summarized below.

1. Use the specified voltages and timing for programming and erasing.

Applied voltages in excess of the rating can permanently damage the device. Use a PROM

programmer that supports the Renesas Technology microcomputer device type “F-ZTAT512”

with 512-kbyte on-chip flash memory.

2. Powering on and off (see figures 18.16 to 18.18)

Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin

low before turning off VCC.

When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory

in the hardware protection state.

The power-on and power-off timing requirements should also be satisfied in the event of a

power failure and subsequent recovery. Failure to do so may result in overprogramming or

overerasing due to MCU runaway, and loss of normal memory cell operation.

3. FWE application/disconnection

FWE application should be carried out when MCU operation is in a stable condition. If MCU

operation is not stable, fix the FWE pin low and set the protection state.

The following points must be observed concerning FWE application and disconnection to

prevent unintentional programming or erasing of flash memory:

•Apply FWE when the VCC voltage has stabilized within its rated voltage range.

If FWE is applied when the MCU’s VCC power supply is not within its rated voltage range,

MCU operation will be unstable and flash memory may be erroneously programmed or

erased.

•Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling

time).

When VCC power is turned on, hold the

RES

pin low for the duration of the oscillation

settling time before applying FWE. Do not apply FWE when oscillation has stopped or is

unstable.

•In boot mode, apply and disconnect FWE during a reset.

In a transition to boot mode, FWE = 1 input and MD2–MD0 setting should be performed

while the

RES

input is low. FWE and MD2–MD0 pin input must satisfy the mode

programming setup time (tMDS) with respect to the reset release timing. When making a

transition from boot mode to another mode, also, a mode programming setup time is

necessary with respect to the reset release timing.

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 644 of 910

REJ09B0258-0300

In a reset during operation, the

RES

pin must be held low for a minimum of 20 system

clock cycles.

•In user program mode, FWE can be switched between high and low level regardless of

RES

input.

FWE input can also be switched during execution of a program in flash memory.

•Do not apply FWE if program runaway has occurred.

During FWE application, the program execution state must be monitored using the

watchdog timer or some other means.

• Disconnect FWE only when the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 are

cleared.

Make sure that the SWE, ESU, PSU, EV, PV, E, and P bits are not set by mistake when

applying or disconnecting FWE.

4. Do not apply a constant high level to the FWE pin.

T prevent erroneous programming or erasing due to program runaway, etc., apply a high level

to the FWE pin only when programming or erasing flash memory (including execution of flash

memory emulation using RAM). A system configuration in which a high level is constantly

applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin,

the watchdog timer should be activated to prevent overprogramming or overerasing due to

program runaway, etc.

5. Use the recommended algorithm when programming and erasing flash memory.

The recommended algorithm enables programming and erasing to be carried out without

subjecting the device to voltage stress or sacrificing program data reliability. When setting the

PSU or ESU bit in FLMCR1, the watchdog timer should be set beforehand as a precaution

against program runaway, etc.

Also note that access to the flash memory space by means of a MOV instruction, etc., is not

permitted while the P bit or E bit is set.

6. Do not set or clear the SWE bit during execution of a program in flash memory.

Clear the SWE bit before executing a program or reading data in flash memory. When the

SWE bit is set, data in flash memory can be rewritten, but flash memory should only be

accessed for verify operations (verification during programming/erasing).

Similarly, when using the RAM emulation function while a high level is being input to the

FWE pin, the SWE bit must be cleared before executing a program or reading data in flash

memory. However, the RAM area overlapping flash memory space can be read and written to

regardless of whether the SWE bit is set or cleared.

A wait time is necessary after the SWE bit is cleared. For details see table 21.10 in section

21.1.6, Flash Memory Characteristics.

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 645 of 910

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7. Do not use interrupts while flash memory is being programmed or erased.

All interrupt requests, including NMI, should be disabled during FWE application to give

priority to program/erase operations (including emulation in RAM).

Bus release must also be disabled.

8. Do not perform additional programming. Erase the memory before reprogramming.

In on-board programming, perform only one programming operation on a 128-byte

programming unit block. Programming should be carried out with the entire programming unit

block erased.

9. Before programming, check that the chip is correctly mounted in the PROM writer.

Overcurrent damage to the device can result if the index marks on the PROM writer socket,

socket adapter, and chip are not correctly aligned.

10.Do not touch the socket adapter or chip during programming.

Touching either of these can cause contact faults and write errors.

11.A wait time of 100 µs or more is necessary when performing a read after a transition to

normal mode from program, erase, or verify mode.

12.Use byte access on the registers that control the flash memory (FLMCR1, FLMCR2,

EBR1, EBR2, and RAMCR).

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 646 of 910

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Period during which flash memory access is prohibited

(x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations

prohibited)

FWE

OSC1

Min 0 µs

MDS

to MD

0*1

RES

SWE bit

SWE set SWE cleared

Program-

ming/

erasing

possible

Wait time:

xWait time:

Min 0 µs

Notes: 1. Except when switching modes, the level of the mode pins (MD

2–

) must be fixed until power-off

by pulling the pins up or down.

2. See section 21.1.6, Flash Memory Characteristics.

Figure 18.16 Power-On/Off Timing (Boot Mode)

Section 18 Flash Memory

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Period during which flash memory access is prohibited

(x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations

prohibited)

FWE

OSC1

Min 0 µs

MDS

to MD

0*1

RES

SWE bit

SWE set SWE cleared

Program-

ming/

erasing

possible

Wait time:

xWait time:

Notes: 1. Except when switching modes, the level of the mode pins (MD

–

) must be fixed until power-off

by pulling the pins up or down.

2. See section 21.1.6, Flash Memory Characteristics.

Figure 18.17 Power-On/Off Timing (User Program Mode)

Section 18 Flash Memory

Rev. 3.00 Sep 14, 2005 page 648 of 910

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Period during which flash memory access is prohibited

(x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)

FWE

OSC1

Min 0µs

MDS

RESW

to MD

RES

SWE bit

Mode

change

User

mode

Boot

mode User program mode

SWE set SWE

cleared

Programming/

erasing possible

Wait time: x

Wait time: y

Programming/

erasing possible

Wait time: x

Wait time: y

Programming/

erasing possible

Wait time: x

Programming/

erasing possible

Wait time: x

Wait time: y

Mode

change

User

mode User program

mode

Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried

out by means of RES input. The state of ports with multiplexed address functions and bus control output pins

(CSn, AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low),

and therefore these pins should not be used as output signals during this time.

2. When making a transition from boot mode to another mode, the mode programming setup time t

MDS

must be

satisfied with respect to RES clearance timing.

See section 21.1.6, Flash Memor

Characteristics.

Figure 18.18 Mode Transition Timing

(Example: Boot Mode →

→→

→ User Mode ↔

↔↔

↔ User Program Mode)

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 14, 2005 page 649 of 910

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Section 19 Clock Pulse Generator

19.1 Overview

The H8/3068F has a built-in clock pulse generator (CPG) that generates the system clock (φ) and

other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides the

clock frequency to generate the system clock (φ). The system clock is output at the φ pin*1 and

furnished as a master clock to prescalers that supply clock signals to the on-chip supporting

modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency

divider by settings in a division control register (DIVCR)*2. Power consumption in the chip is

reduced in almost direct proportion to the frequency division ratio.

Notes: 1. Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit

setting in the module standby control register (MSTCR). For details, see section 20.7,

System Clock Output Disabling Function.

2. The division ratio of the frequency divider can be changed dynamically during

operation. The clock output at the φ pin also changes when the division ratio is

changed. The frequency output at the φ pin is shown below.

φ = EXTAL × n

where, EXTAL: Frequency of crystal resonator or external clock signal

n: Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 14, 2005 page 650 of 910

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19.1.1 Block Diagram

Figure 19.1 shows a block diagram of the clock pulse generator.

XTAL

EXTAL

CPG

φ pin φ/2 to φ/4096

Oscillator Duty

adjustment

circuit Frequency

divider

Division

control

Prescalers

Data bus

Figure 19.1 Block Diagram of Clock Pulse Generator

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 14, 2005 page 651 of 910

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19.2 Oscillator Circuit

Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock

signal.

19.2.1 Connecting a Crystal Resonator

Circuit Configuration: A crystal resonator can be connected as in the example in figure 19.2.

Damping resistance Rd should be selected according to table 19.1 (1), and external capacitances

CL1 and CL2 according to table 19.1 (2). An AT-cut parallel-resonance crystal should be used.

EXTAL

XTAL

CL1

CL2

Figure 19.2 Connection of Crystal Resonator (Example)

If a crystal resonator with a frequency higher than 20 MHz is connected, the external load

capacitance values in table 19.1 (2) should not exceed 10 [pF]. Also, in order to improve the

accuracy of the oscillation frequency, a thorough study of oscillation matching evaluation, etc.,

should be carried out when deciding the circuit constants.

Table 19.1 (1) Damping Resistance Value

Damping

Resistance Frequency f (MH z)

Value 22 <

< f ≤

≤≤

≤ 44 <

< f ≤

≤≤

≤88 <

< f ≤

≤≤

≤ 10 10 <

< f ≤

≤≤

≤ 13 13 <

< f ≤

≤≤

≤ 16 16 <

< f ≤

≤≤

≤ 18 18 <

< f ≤

≤≤

≤ 25

Rd (Ω)1 k50020000000

Note: A crystal resonator between 2 MHz and 25 MHz can be used. If the chip is to be operated

at less than 2 MHz, the on-chip frequency divider should be used. (A crystal resonator of

less than 2 MHz cannot be used.)

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 14, 2005 page 652 of 910

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Table 19.1 (2) External Capacitance Values

External Capacitance Value 5 V Version

Frequency f (MHz) 20 <

< f ≤

≤≤

≤ 25 2 ≤

≤≤

≤ f ≤

≤≤

≤ 20

CL1 = CL2 (pF) 10 10 to 22

Crystal Resonator: Figure 19.3 shows an equivalent circuit of the crystal resonator. The crystal

resonator should have the characteristics listed in table 19.2.

XTAL

LRs

EXTAL

AT-cut parallel-resonance type

Figure 19.3 Crystal Resonator Equivalent Circuit

Table 19.2 Crystal Resonator Parameters

Frequency (MHz) 2 4 8 10 12 16 18 20 25

Rs max (Ω) 500 120 80 70 60 50 40 40 40

Co (pF) 7 pF

max 7 pF

max

Use a crystal resonator with a frequency equal to the system clock frequency (φ).

Notes on Board Design: When a crystal resonator is connected, the following points should be

noted:

Other signal lines should be routed away from the oscillator circuit to prevent induction from

interfering with correct oscillation. See figure 19.4.

When the board is designed, the crystal resonator and its load capacitors should be placed as close

as possible to the XTAL and EXTAL pins.

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 14, 2005 page 653 of 910

REJ09B0258-0300

XTAL

EXTAL

H8/3068F chip

Avoid Signal A Signal B

Figure 19.4 Oscillator Circuit Block Board Design Precautions

19.2.2 External Clock Input

Circuit Configuration: An external clock signal can be input as shown in the examples in figure

19.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray

capacitance at the XTAL pin exceeds 10 pF in configuration a, use the connection shown in

configuration b instead, and hold the external clock high in standby mode.

EXTAL

XTAL

EXTAL

XTAL

External clock input

Open

External clock input

a. XTAL pin left open

b. Complementary clock input at XTAL pin

Figure 19.5 External Clock Input (Examples)

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 14, 2005 page 654 of 910

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External Clock: The external clock frequency should be equal to the system clock frequency

when not divided by the on-chip frequency divider. Table 19.3 shows the clock timing, figure 19.6

shows the external clock input timing, and figure 19.7 shows the external clock output settling

delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is

corrected by the on-chip oscillator and duty adjustment circuit.

When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the

on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external

devices after the external clock settling time (tDEXT) has passed after the clock input. The system

must remain reset with the reset signal low during tDEXT, while the clock output is unstable.

Table 19.3 Clock Timing

VCC = 5.0 V ± 10%

Item Symbol Min Max Unit Test Conditions

External cl ock input low

pulse width tEXL 15 — ns Figure 19.6

External clock input high

pulse width tEXH 15 — ns

External clock rise time tEXr —5 ns

External cl ock fall time tEXf —5 ns

Clock lo w pulse width tCL 0.4 0.6 tcyc φ ≥ 5 MHz Figure 19.17

80 — ns φ < 5 MHz

Clock high pulse width tCH 0.4 0.6 tcyc φ ≥ 5 MHz

80 — ns φ < 5 MHz

External cl ock output

settling delay ti me tDEXT*500 — µs Figure 19.7

Note: * tDEXT includes a

RES

pulse width (tRESW). tRESW = 20 tcyc

EXTAL

tEXr tEXf

VCC × 0.7

0.3 V

tEXH tEXL

VCC × 0.5

Figure 19.6 External Clock Input Timing

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 14, 2005 page 655 of 910

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VCC

STBY

EXTAL

φ (internal or

external)

RES

tDEXT

VIH

Figure 19.7 External Clock Output Settling Delay Timing

19.3 Duty Adjustment Circuit

When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty

cycle of the clock signal from the oscillator to generate φ.

19.4 Prescalers

The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 14, 2005 page 656 of 910

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19.5 Fre quency Divi der

The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The

frequency division ratio can be changed dynamically by modifying the value in DIVCR, as

described below. Power consumption in the chip is reduced in almost direct proportion to the

frequency division ratio. The system clock generated by the frequency divider can be output at the

φ pin.

19.5.1 Register Configuration

Table 19.4 summarizes the frequency division register.

Table 19.4 Frequency Division Register

Address*Name Abbreviation R/W Initial Value

H'EE01B Division control register DIVCR R/W H'FC

Note: *Lower 20 bits of the address in advanced mode.

19.5.2 Division Control Register (DIVCR)

DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency

divider.

Bit

Initial value

Read/Write

—

DIV0

R/W

—

DIV1

R/W

Reserved bits Divide bits 1 and 0

These bits select the

frequency division ratio

DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 14, 2005 page 657 of 910

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Bits 1 and 0—Divide (DIV1, DIV0): These bits select the frequency division ratio, as follows.

Bit 1

DIV1 Bit 0

DIV0 Frequency Division Ratio

0 0 1/1 (Initial value)

011/2

101/4

111/8

19.5.3 Usage Notes

The DIVCR setting changes the φ frequency, so note the following points.

• Select a frequency division ratio that stays within the assured operation range specified for the

clock cycle time tcyc in the AC electrical characteristics. Note that ømin = lower limit of the

operating frequency range. Ensure that ø is not below this lower limit.

• All on-chip module operations are based on φ. Note that the timing of timer operations, serial

communication, and other time-dependent processing differs before and after any change in

the division ratio. The waiting time for exit from software standby mode also changes when

the division ratio is changed. For details, see section 20.4.3, Selection of Waiting Time for

Exit from Software Standby Mode.

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 14, 2005 page 658 of 910

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Section 20 Power-Down State

Rev. 3.00 Sep 14, 2005 page 659 of 910

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Section 20 Power-Do wn State

20.1 Overview

The H8/3068F has a power-down state that greatly reduces power consumption by halting the

CPU, and a module standby function that reduces power consumption by selectively halting on-

chip modules.

The power-down state includes the following three modes:

• Sleep mode

• Software standby mode

• Hardware standby mode

The module standby function can halt on-chip supporting modules independently of the power-

down state. The modules that can be halted are the 16-bit timer, 8-bit timer, SCI0, SCI1, SCI2,

DMAC, DRAM interface, and A/D converter.

Table 20.1 indicates the methods of entering and exiting the power-down modes and module

standby mode, and gives the status of the CPU and on-chip supporting modules in each mode.

Section 20 Power-Down State

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Table 20.1 Power-Down State and Module Standby Function

Clock

Active

Halted

Active

Exiting

Conditions

• Interrupt

• RES

• STBY

• NMI

• IRQ

to IRQ

• RES

• STBY

• RES

• STBY

• RES

• Clear MSTCR

bit to 0

I/O

Ports

Held

High

impedance

—

φ clock

output

φ output

High

output

High

impedance

High

impedance

RAM

Held

—

Other

Modules

Active

Halted

and

reset

Halted

and

reset

Active

DRAM

Interface

Active

Halted

and

held

Halted

and

reset

Halted

and

held*

DMAC

Active

Halted

and

reset

Halted

and

reset

Halted

and

reset

CPU

Held

Undeter-

mined

—

CPU

Halted

Active

Entering

Conditions

SLEEP instruc-

tion executed

while SSBY = 0

in SYSCR

SLEEP instruc-

tion executed

while SSBY = 1

in SYSCR

Low input at

STBY pin

Corresponding

bit set to 1 in

MSTCR

Mode

Sleep

mode

Software

standby

mode

Hardware

standby

mode

Module

standby

16-Bit

Timer

Active

Halted

and

reset

Halted

and

reset

Halted

and

reset

8-Bit

Timer

Active

Halted

and

reset

Halted

and

reset

Halted

and

reset

SCI0

Active

Halted

and

reset

Halted

and

reset

Halted

and

reset

SCI1

Active

Halted

and

reset

Halted

and

reset

Halted

and

reset

SCI2

Active

Halted

and

reset

Halted

and

reset

Halted

and

reset

A/D

Active

Halted

and

reset

Halted

and

reset

Halted

and

reset

State

Notes: 1. RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states.

2. State in which the corresponding MSTCR bit was set to 1. For details see section 20.2.2, Module Standby Control Register H (MSTCRH) and section 20.2.3,

Module Standby Control Register L (MSTCRL).

3. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode.

4. When P6

is used as the φ output pin.

5. When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR bit to

0, then set up the module registers again.

Legend

SYSCR: System control register

SSBY: Software standby bit

MSTCRH: Module standby control register H

MSTCRL: Module standby control register L

Section 20 Power-Down State

Rev. 3.00 Sep 14, 2005 page 661 of 910

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20.2 Register Conf iguration

The H8/3068F has a system control register (SYSCR) that controls the power-down state, and

module standby control registers H (MSTCRH) and L (MSTCRL) that control the module

standby function. Table 20.2 summarizes these registers.

Table 20.2 Control Register

Address*Name Abbreviation R/W Initial Value

H'EE012 System control regis ter SYSCR R/W H'09

H'EE01C Module standby control register H MSTCRH R/W H'78

H'EE01D Module standby control register L MSTCRL R/W H'00

Note: * Lower 20 bits of the address in advanced mode.

20.2.1 System Control Register (SYSCR)

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

SSOE

R/W

Software standby

Enables transition to

software standby mode

RAM enable

Standby timer select 2 to 0

These bits select the

waiting time of the CPU

and peripheral functions

User bit enable

NMI edge select

Software standby

output port enable

SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY), bits 6 to 4 (STS2 to STS0), and bit 1

(SSOE) control the power-down state. For information on the other SYSCR bits, see section 3.3,

System Control Register (SYSCR).

Section 20 Power-Down State

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Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software

standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal

operation. To clear this bit, write 0.

Bit 7

SSBY Description

0 SLEEP instruction causes tra nsition to sleep mode (Initial value)

1 SLEEP instruction causes tra nsition to software standby mode

Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the

CPU and on-chip supporting modules wait for the clock to settle when software standby mode is

exited by an external interrupt. If the clock is generated by a crystal resonator, set these bits

according to the clock frequency so that the waiting time will be at least 7 ms (oscillation settling

time). See table 20.3. If an external clock is used, set these bits so that the waiting time will be at

least 100 µs.

Bit 6

STS2 Bit 5

STS1 Bit 4

STS0 Description

0 0 0 Waiting time = 8,192 states (Ini tial value)

1 Waiting time = 16,384 states

1 0 Waiting time = 32,768 states

1 Waiting time = 65,536 states

1 0 0 Waiting time = 131,072 states

1 Waiting time = 262,144 states

1 0 Waiting time = 1,024 states

1 Illegal setting

Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and

bus control signals (

0 to

HWR

LWR

UCAS

LCAS

, and

RFSH

) are kept as

outputs or fixed high, or placed in the high-impedance state in software standby mode.

Bit 1

SSOE Description

0 In software standby mode, the address bus and bus control signals

are all high-impedance (Initi al value)

1 In software standby mode, the address bus retains its output state

and bus control si gnals are fixed high

Section 20 Power-Down State

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20.2.2 Module Standby Control Register H (MSTCRH)

MSTCRH is an 8-bit readable/writable register that controls output of the system clock (φ). It also

controls the module standby function, which places individual on-chip supporting modules in the

standby state. Module standby can be designated for the SCI0, SCI1, SCI2.

Bit

Initial value

Read/Write

PSTOP

R/W

—

MSTPH0

R/W

MSTPH2

R/W

MSTPH1

R/W

φ clock stop

Enables or disables

output of the system clock

Module standby H2 to 0

These bits select modules

to be placed in standby

Reserved bit

MSTCRH is initialized to H'78 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—φ

φφ

φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).

Bit 1

PSTOP Description

0 System clock output is enabled (Initial val ue)

1 System clock output is disabled

Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 1.

Bit 2—Module Standby H2 (MSTPH2): Selects whether to place the SCI2 in standby.

Bit 2

MSTPH2 Description

0 SCI2 operates normal ly (Initi al value)

1 SCI2 is in standby state

Section 20 Power-Down State

Rev. 3.00 Sep 14, 2005 page 664 of 910

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Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby.

Bit 1

MSTPH1 Description

0 SCI1 operates normally (Initi al

value)

1 SCI1 is in standby state

Bit 0—Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby.

Bit 0

MSTPH0 Description

0 SCI0 operates normally (Initi al

value)

1 SCI0 is in standby state

20.2.3 Module Standby Control Register L (MSTCRL)

MSTCRL is an 8-bit readable/writable register that controls the module standby function, which

places individual on-chip supporting modules in the standby state. Module standby can be

designated for the DMAC, 16-bit timer, DRAM interface, 8-bit timer, and A/D converter

modules.

MSTPL2

R/W

—

R/W

MSTPL0

R/W

Reserved bits

Module standby L7, L5 to L2, L0

These bits select modules to be

placed in standby

Bit

Initial value

Read/Write

MSTPL7

R/W

—

R/W

MSTPL5

R/W

MSTPL4

R/W

MSTPL3

R/W

MSTCRL is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Section 20 Power-Down State

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Bit 7—Module Standby L7 (MSTPL7): Selects whether to place the DMAC in standby.

Bit 7

MSTPL7 Description

0 DMAC operates normally (Initial value)

1 DMAC is in standby state

Bit 6—Reserved: This bit can be written and read.

Bit 5—Module Standby L5 (MSTPL5): Selects whether to place the DRAM interface in

standby.

Bit 5

MSTPL5 Description

0 DRAM interface operates normally (Initi al value)

1 DRAM interface is in standby state

Bit 4—Module Standby L4 (MSTPL4): Selects whether to place the 16-bit timer in standby.

Bit 4

MSTPL4 Description

0 16-bit timer operates normally (Initial value)

1 16-bit timer is in standby state

Bit 3—Module Standby L3 (MSTPL3): Selects whether to place 8-bit timer channels 0 and 1 in

standby.

Bit 3

MSTPL3 Description

0 8-bit timer channels 0 and 1 operate normally (Initial value)

1 8-bit timer channels 0 and 1 are in standby state

Section 20 Power-Down State

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Bit 2—Module Standby L2 (MSTPL2): Selects whether to place 8-bit timer channels 2 and 3 in

standby.

Bit 2

MSTPL2 Description

0 8-bit timer channels 2 and 3 operate normally (Initial value)

1 8-bit timer channels 2 and 3 are in standby state

Bit 1—Reserved: This bit can be written and read.

Bit 0—Module Standby L0 (MSTPL0): Selects whether to place the A/D converter in standby.

Bit 0

MSTPL0 Description

0 A/D converter operates normally (Initi al value)

1 A/D converter is in standby state

Section 20 Power-Down State

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20.3 Sleep Mode

20.3.1 Transition to Sleep Mode

When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a

transition from the program execution state to sleep mode. Immediately after executing the

SLEEP instruction the CPU halts, but the contents of its internal registers are retained. The DMA

controller (DMAC), DRAM interface, and on-chip supporting modules do not halt in sleep mode.

Modules which have been placed in standby by the module standby function, however, remain

halted.

20.3.2 Exit from Sleep Mode

Sleep mode is exited by an interrupt, or by input at the

RES

STBY

pin.

Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt

exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting

module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by

an interrupt other than NMI if the interrupt is masked by interrupt priority settings and the

settings of the I and UI bits in CCR, IPR.

Exit by

RES

Input: Low input at the

RES

pin exits from sleep mode to the reset state.

Exit by

STBY

Input: Low input at the

STBY

pin exits from sleep mode to hardware standby

mode.

Section 20 Power-Down State

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20 .4 Softwa re Standby Mode

20.4.1 Transition to Software Standby Mode

To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in

SYSCR.

In software standby mode, current dissipation is reduced to an extremely low level because the

CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting

modules are reset and halted. As long as the specified voltage is supplied, however, CPU register

contents and on-chip RAM data are retained. The settings of the I/O ports and DRAM interface*

are also held. When the WDT is used as a watchdog timer (WT/

= 1), the TME bit must be

cleared to 0 before setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0.

Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software

standby mode.

Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their

previous states.

20.4.2 Exit from Software Standby Mode

Software standby mode can be exited by input of an external interrupt at the NMI,

IRQ

1, or

IRQ

2 pin, or by input at the

RES

STBY

pin.

Exit by Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is received, the

clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0

in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and

interrupt exception handling begins. Software standby mode is not exited if the interrupt enable

bits of interrupts IRQ0, IRQ1, and IRQ2 are cleared to 0, or if these interrupts are masked in the

CPU.

Exit by

RES

Input: When the

RES

input goes low, the clock oscillator starts and clock pulses are

supplied immediately to the entire chip. The

RES

signal must be held low long enough for the

clock oscillator to stabilize. When

RES

goes high, the CPU starts reset exception handling.

Exit by

STBY

Input: Low input at the

STBY

pin causes a transition to hardware standby mode.

Section 20 Power-Down State

Rev. 3.00 Sep 14, 2005 page 669 of 910

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20.4.3 Selection of Waiting Time for Exit from Software Standby Mode

Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.

Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to

stabilize) is at least 7 ms. Table 20.3 indicates the waiting times that are selected by STS2 to

STS0, DIV1, and DIV0 settings at various system clock frequencies.

External Clock: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time is at least 100 µs.

Table 20.3 Clock Frequency and Waiting Time for Clock to Settle

DIV1 D IV0 STS2 ST S1 STS0 Waiting Time 25 MHz 20 MHz 18 MHz 1 6 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 MHz Unit

0 0 0 0 0 8192 states 0.3 0.4 0.46 0.51 0.65 0.8 1.0 1.3 2.0 4.1 8.2*ms

0 0 1 16384 states 0.7 0.8 0.91 1.0 1.3 1.6 2.0 2.7 4.1 8.2*16.4

0 1 0 32768 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2*16.4 32.8

0 1 1 65536 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2*10.9*16.4 32.8 65.5

1 0 0 131072 states 5.2 6.6 7.3*8.2*10.9*13.1*16.4 21.8 32.8 65.5 131.1

1 0 1 262144 states 10.5*13.1*14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1

1 1 0 1024 states 0.04 0.05 0.057 0.064 0.085 0.10 0.13 0.17 0.26 0.51 1.0

1 1 1 Illegal setting

0 1 0 0 0 8192 states 0.7 0.8 0.91 1.02 1.4 1.6 2.0 2.7 4.1 8.2*16.4*ms

0 0 1 16384 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2*16.4 32.8

0 1 0 32768 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2*10.9*16.4 32.8 65.5

0 1 1 65536 states 5.2 6.6 7.3*8.2*10.9*13.1*16.4 21.8 32.8 65.5 131.1

1 0 0 131072 states 10.5*13.1*14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1

1 0 1 262144 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3

1 1 0 1024 states 0.08 0.10 0.11 0.13 0.17 0.20 0.26 0.34 0.51 1.0 2.0

1 1 1 Illegal setting

1 0 0 0 0 8192 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2*16.4*32.8*ms

0 0 1 16384 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2*10.9*16.4 32.8 65.5

0 1 0 32768 states 5.2 6.6 7.3*8.2*10.9*13.1*16.4 21.8 32.8 65.5 131.1

0 1 1 65536 states 10.5*13.1*14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1

1 0 0 131072 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3

1 0 1 262144 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1048.6

1 1 0 1024 states 0.16 0.20 0.23 0.26 0.34 0.41 0.51 0.68 1.02 2.0 4.1

1 1 1 Illegal setting

1 1 0 0 0 8192 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2*10.9*16.4*32.8*65.5 ms

0 0 1 16384 states 5.2 6.6 7.3*8.2*10.9*13.1*16.4 21.8 32.8 65.5 131.1

0 1 0 32768 states 10.5 13.1*14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1

0 1 1 65536 states 21.0*26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3

1 0 0 131072 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1048.6

1 0 1 262144 states 83.9 104.9 116.5 131.1 174.8 209.7 262.1 349.5 524.3 1048.6 2097.1

1 1 0 1024 states 0.33 0.41 0.46 0.51 0.68 0.82 1.0 1.4 2.0 4.1 8.2*

1 1 1 Illegal setting

* : Recom men ded setting

Section 20 Power-Down State

Rev. 3.00 Sep 14, 2005 page 670 of 910

REJ09B0258-0300

20.4.4 Sample Application of Software Standby Mode

Figure 20.1 shows an example in which software standby mode is entered at the fall of NMI and

exited at the rise of NMI.

With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an

NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit

is set to 1; then the SLEEP instruction is executed to enter software standby mode.

Software standby mode is exited at the next rising edge of the NMI signal.

NMI

NMIEG

SSBY

NMI interrupt

handler

NMIEG = 1

SSBY = 1

Software standby

mode (power-

down state)

Oscillator

settling time

(tosc2)

SLEEP

instruction

NMI exception

handling

Clock

oscillator

Figure 20.1 NMI Timing for Software Standby Mode (Example)

20.4.5 Note

The I/O ports retain their existing states in software standby mode. If a port is in the high output

state, its output current is not reduced.

Section 20 Power-Down State

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20 .5 Hardwar e Standby Mode

20.5.1 Transition to Hardware Standby Mode

Regardless of its current state, the chip enters hardware standby mode whenever the

STBY

goes low. Hardware standby mode reduces power consumption drastically by halting all functions

of the CPU, DMAC, DRAM interface, and on-chip supporting modules. All modules are reset

except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is

retained. I/O ports are placed in the high-impedance state.

Clear the RAME bit to 0 in SYSCR before

STBY

goes low to retain on-chip RAM data.

The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby

mode.

20.5.2 Exit from Hardware Standby Mode

Hardware standby mode is exited by inputs at the

STBY

and

RES

pins. While

RES

is low, when

STBY

goes high, the clock oscillator starts running.

RES

should be held low long enough for the

clock oscillator to settle. When

RES

goes high, reset exception handling begins, followed by a

transition to the program execution state.

20.5.3 Timing for Hardware Standby Mode

Figure 20.2 shows the timing relationships for hardware standby mode. To enter hardware

standby mode, first drive

RES

low, then drive

STBY

low. To exit hardware standby mode, first

drive

STBY

high, wait for the clock to settle, then bring

RES

from low to high.

Section 20 Power-Down State

Rev. 3.00 Sep 14, 2005 page 672 of 910

REJ09B0258-0300

RES

STBY

Clock

oscillator

Oscillator

settling time

Reset

exception

handling

Figure 20.2 Hardware Standby Mode Timing

Section 20 Power-Down State

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20 .6 Module Standby Functio n

20.6.1 Module Standby Timing

The module standby function can halt several of the on-chip supporting modules (SCI2, SCI1,

SCI0, the DMAC, 16-bit timer, 8-bit timer, DRAM interface, and A/D converter) independently

in the power-down state. This standby function is controlled by bits MSTPH2 to MSTPH0 in

MSTCRH and bits MSTPL7 to MSTPL0 in MSTCRL. When one of these bits is set to 1, the

corresponding on-chip supporting module is placed in standby and halts at the beginning of the

next bus cycle after the MSTCR write cycle.

20.6.2 Read/Write in Module Standby

When an on-chip supporting module is in module standby, read/write access to its registers is

disabled. Read access always results in H'FF data. Write access is ignored.

20.6.3 Usage Notes

When using the module standby function, note the following points.

DMAC: When setting a bit in MSTCR to 1 to place the DMAC in module standby, make sure

that the DMAC is not currently requesting the bus right. If the corresponding bit in MSTCR is set

to 1 when a bus request is present, operation of the bus arbiter becomes ambiguous and a

malfunction may occur.

DRAM Interface: When the module standby function is used on the DRAM interface, set the

MSTCR bit to 1 while DRAM space is deselected.

On-Chip Supporting Module Interrupts: Before setting a module standby bit, first disable

interrupts by that module. When an on-chip supporting module is placed in standby by the module

standby function, its registers are initialized, including registers with interrupt request flags.

Pin States: Pins used by an on-chip supporting module lose their module functions when the

module is placed in module standby. What happens after that depends on the particular pin. For

details, see section 8, I/O Ports. Pins that change from the input to the output state require special

care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data

function and becomes a port pin. If its port DDR bit is set to 1, the pin becomes a data output pin,

and its output may collide with external SCI transmit data. Data collision should be prevented by

clearing the port DDR bit to 0 or taking other appropriate action.

function, all its registers are initialized. To restart the module, after its MSTCR bit is cleared to 0,

Section 20 Power-Down State

Rev. 3.00 Sep 14, 2005 page 674 of 910

REJ09B0258-0300

its registers must be set up again. It is not possible to write to the registers while the MSTCR bit

is set to 1.

MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be

accessed from the CPU. It can be read by the DMAC, but it cannot be written by the DMAC.

20.7 System Clock Output Disabling Function

Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCRH. When the

PSTOP bit is set to 1, output of the system clock halts and the φ pin is placed in the high-

impedance state. Figure 20.3 shows the timing of the stopping and starting of system clock

output. When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 20.4

indicates the state of the φ pin in various operating states.

T1 T2

(PSTOP = 1)

T3 T1 T2

(PSTOP = 0)

MSTCRH write cycle MSTCRH write cycle

High impedance

φ pin

Figure 20.3 Starting and Stopping of System Clock Output

Table 20.4 φ

φφ

φ Pin State in Various Operating States

Operating State PSTOP = 0 PSTOP = 1

Hardware standby High impedance High impedance

Software standby Always high High impedance

Sleep mode System cl ock output High impedance

Normal operation System clock output High impedance

Section 21 Electrical Characteristics

Rev. 3.00 Sep 14, 2005 page 675 of 910

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Section 21 Electrical Characteristics

21.1 Electrical Characteristics of H8/3068F-ZTAT

21.1.1 Absolute Maximum Ratings

Table 21.1 lists the absolute maximum ratings.

Table 21.1 Absolute Maximum Ratings

Item Symbol Value Unit

Power supply voltage VCC*1–0.3 to +7.0 V

Input voltage (FWE)*2Vin –0.3 to VCC +0.3 V

Input voltage (except for port 7)*2Vin –0.3 to VCC +0.3 V

Input voltage (port 7) Vin –0.3 to AVCC +0.3 V

Reference voltage VREF –0.3 to AVCC +0.3 V

Analog power supply voltage AVCC –0.3 to +7.0 V

Analog input voltage VAN –0.3 to AVCC +0.3 V

Operating temperature Topr –20 to +75*3°C

Storage temperature Tstg –55 to +125 °C

Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.

Notes: 1. Do not apply the power supply voltage to the VCL pin. Connect an external capacitor

between this pin and GND.

2. 12 V must not be applied to any pin, as this may cause permanent damage to the

device.

3. The operating temperature range for flash memory programming/erasing is 0°C to

+75°C.

Section 21 Electrical Characteristics

Rev. 3.00 Sep 14, 2005 page 676 of 910

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21.1.2 DC Characteristics

Table 21.2 lists the DC characteristics. Table 21.3 lists the permissible output currents.

Table 21.2 DC Characteristics (1)

Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC*1,

VSS = AVSS = 0 V*1, Ta = –20°C to +75°C

[Programming/erasing conditions: Ta = 0°C to +75°C]

Item Symbol Min Typ Max Unit Test

Conditions

Schmitt

trigger input

voltages

Port A,

P80 to P82

VT–

VT+

VT+ – VT–

1.0

—

0.4

—

VCC × 0.7

—

Input high

voltage

STBY

RES

NMI, MD2 to

MD0, FWE

VIH VCC – 0.7 — VCC + 0.3 V

EXTAL VCC × 0.7 — VCC + 0.3 V

Port 7 2 .0 — AVCC + 0.3 V

Ports 1 to 6,

P83, P84, P90

to P95, port B

2.0 — VCC + 0.3 V

Input low

voltage

STBY

RES

FWE, MD2 to

MD0

VIL –0.3 — 0.5 V

NMI, EXTAL,

ports 1 to 7,

P83, P84, P90

to P95, port B

–0.3 — 0.8 V

Output high

voltage All output pins VOH VCC – 0.5

3.5 —

——

—V

VIOH = –200 µA

IOH = –1 mA

All output pins VOL ——0.4VI

OL = 1.6 mAOutput low

voltage Ports 1, 2,

and 5 ——1.0VI

OL = 10 mA

Section 21 Electrical Characteristics

Rev. 3.00 Sep 14, 2005 page 677 of 910

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Item Symbol Min Typ Max Unit Test

Conditions

STBY

RES

NMI, FWE,

MD2 to MD0

|Iin|— —1.0 µAV

in = 0.5 V to

VCC – 0.5 V

Input

leakage

current Port 7 — — 1.0 µA Vin = 0.5 V to

AVCC – 0.5 V

Three-state

leakage

current

Ports 1 to 6

Ports 8 to B |ITSI|— —1.0 µAV

in = 0.5 V to

VCC – 0.5 V

Input pull -up

MOS current Ports 2, 4,

and 5 –Ip50 — 300 µA Vin = 0 V

Input

capacitance FWE Cin — — 80 pF Vin = 0 V

f = fmin

NMI — — 50 pF Ta = 25°C

All input pins

except NMI — — 15 pF

Current

dissipation*2Normal

operation ICC*4—32

(5.0 V) 47 mA f = 20 MHz

(5.0 V) 58 f = 25 MHz

Sleep mode — 24

(5.0 V) 38 mA f = 20 MHz

(5.0 V) 47 f = 25 MHz

Module

standby mode —19

(5.0 V) 31 mA f = 20 MHz

(5.0 V) 37 f = 25 MHz

—1.010µAT

a ≤ 50°CStandby

mode*3— — 80 µA 50°C < Ta

Flash memory

programming/

erasing*5

— 37 57 mA f = 20 MHz

42 68 f = 25 MHz

Section 21 Electrical Characteristics

Rev. 3.00 Sep 14, 2005 page 678 of 910

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Item Symbol Min Typ Max Unit Test

Conditions

Analog

power supply

current

During A/D

conversion AICC —0.61.5mA

During A/D

and D/A

conversion

—0.61.5mA

Idle — 0.01 5 µA DASTE = 0

Reference

current During A/D

conversion AICC — 0.45 0.8 mA

During A/D

and D/A

conversion

—2.03.0mA

Idle — 0.01 5 µA DASTE = 0

RAM standby voltage VRAM 2.0 — — V

Notes: 1. If the A/D converter is not used, do not leave the AVCC, VREF, and AVSS pins open.

Connect AVCC and VREF to VCC, and connect AVSS to VSS.

2. Current dissipation values are for VIH min = VCC – 0.5 V and VIL max = 0.5 V with all

output pins unl oaded and the on-chip MOS pull-up transistors in the off state.

3. The values are for VRAM ≤ VCC < 4.5 V, VIH min = V CC × 0.9, and VIL max = 0.3 V.

4. ICC max. (normal operation) = 3.0 (mA) + 0.40 (mA/(MHz × V)) × VCC × f

ICC max. (sleep mode) = 3.0 (mA) + 0.32 (mA/(MHz × V)) × VCC × f

ICC max. (sleep mode + module standby mode)

= 3.0 (mA) + 0.25 (mA/(MHz × V)) × VCC × f

The Typ values for power consumpti on are reference values.

5. Sum of current dissipation in normal operation and current dissipation in

program/erase operations.

Section 21 Electrical Characteristics

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Table 21.3 Permissible Output Currents

Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VREF = 4.5 V to AVCC,

VSS = AVSS = 0 V, Ta = –40°C to +75°C

Item Symbol Min Typ Max Unit

Permissible output

low current (per pin) Ports 1, 2, and 5

Other output pins IOL —

——

—10

2.0 mA

Permissible output

low current (total) Total of 20 pins in

Ports 1, 2, and 5 ΣIOL ——80mA

Total of al l output pins,

including the above — — 120 mA

Permissible output

high current (per pi n) All output pins | –IOH | — — 2.0 mA

Permissible output

high current (total ) Total of all output pins | ΣIOH |——40mA

Notes: 1. To protect chip reliability, do not exceed the output current values in table 21.3.

2. When directly driving a darlington pair or LED, always insert a current-limiting resistor

in the output line, as shown in figures 21.1 and 21.2.

H8/3068F-ZTAT

Port 2 kΩ

Darlington pair

Figure 21.1 Darlington Pair Drive Circuit (Example)

Section 21 Electrical Characteristics

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H8/3068F-ZTAT

Ports 1, 2, 5 LED

600Ω

Figure 21.2 Sample LED Circuit

Section 21 Electrical Characteristics

Rev. 3.00 Sep 14, 2005 page 681 of 910

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21.1.3 AC Characteristics

Clock timing parameters are listed in table 21.4, control signal timing parameters in table 21.5,

and bus timing parameters in table 21.6. Timing parameters of the on-chip supporting modules

are listed in table 21.7.

Table 21.4 Clock Timing

Condition: Ta = –20°C to +75°C

Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 20 MHz

Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 25 MHz

Condition

Item Symbol Min Max Min Max Unit T est Conditions

Clock cycle time

Clock pulse low width tcyc

tCL

15 500

—40

10 500

—ns

ns Figure 21.4 to figure

21.6

Clock pulse high width tCH 15 —10 —ns

Clock rise time tCr —10 —10 ns

Clock fall time tCf —10 —10 ns

Clock oscillator settling

time at reset tOSC1 20 —20 —ms Figure 21.4

Clock oscillator settling

time in software standby tOSC2 7 — 7 — ms

Section 21 Electrical Characteristics

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Table 21.5 Control Signal Timing

Condition: Ta = –20°C to +75°C

Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 20 MHz

Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 25 MHz

Condition

A and B

Item Symbol Min Max Unit Test Conditions

RES

setup time tRESS 150 —ns Fi gure 21.5

RES

pulse width tRESW 20 — tcyc

Mode programming setup time tMDS 200 —ns

NMI, IRQ setup time tNMIS 150 —ns Figure 21.7

NMI, IRQ hold time tNMIH 10 —ns

NMI, IRQ pulse width tNMIW 200 —ns

Section 21 Electrical Characteristics

Rev. 3.00 Sep 14, 2005 page 683 of 910

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Table 21.6 Bus Timing

Condition: Ta = –20°C to +75°C

Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 20 MHz

Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 25 MHz

Condition

A and B

Item Symbol Min Max Unit Test

Conditions

Address delay time tAD —25 ns Figure 21.8,

Address hold time tAH 0.5 tcyc – 20 —ns figure 21.9

Read strobe delay time tRSD —25 ns

Address strobe delay time tASD —25 ns

Write strobe delay time tWSD —25 ns

Strobe delay time tSD —25 ns

Write strobe pulse width 1 tWSW1 1.0 tcyc – 25 —ns

Write strobe pulse width 2 tWSW2 1.5 tcyc – 25 —ns

Address setup time 1 tAS1 0.5 tcyc – 20 —ns

Address setup time 2 tAS2 1.0 tcyc – 20 —ns

Read data setup time tRDS 25 —ns

Read data hold time tRDH 0 — ns

Write data delay time tWDD —35 ns

Write data setup time 1 tWDS1 1.0 tcyc – 30 —ns

Write data setup time 2 tWDS2 2.0 tcyc – 30 —ns

Write data hold time tWDH 0.5 tcyc – 15 —ns

Read data access time 1 tACC1 —2.0 tcyc – 45 ns Figure 21.17,

Read data access time 2 tACC2 —3.0 tcyc – 45 ns figure 21.18

Read data access time 3 tACC3 —1.5 tcyc – 45 ns

Read data access time 4 tACC4 —2.5 tcyc – 45 ns

Precharge time 1 tPCH1 1.0 tcyc – 20 —ns

Precharge time 2 tPCH2 0.5 tcyc – 20 —ns

Section 21 Electrical Characteristics

Rev. 3.00 Sep 14, 2005 page 684 of 910

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Condition

A and B

Item Symbol Min Max Unit Test

Conditions

Wait setup time tWTS 25 —ns Figure 21.19

Wait hold time tWTH 5 — ns

Bus request setup time tBRQS 25 —ns Figure 21.20

Bus acknowledge delay time 1 tBACD1 —30 ns

Bus acknowledge delay time 2 tBACD2 —30 ns

Bus-floating time tBZD —30 ns

RAS

precharge time tRP 1.5 tcyc – 25 —ns

CAS

precharge time tCP 0.5 tcyc – 15 —ns

Figure 21.17 to

figure 21.19

Low address hold time t RAH 0.5 tcyc – 15 —ns

RAS

delay time 1 tRAD1 —25 ns

RAS

delay time 2 tRAD2 —30 ns

CAS

delay time 1 tCASD1 —25 ns

CAS

delay time 2 tCASD2 —25 ns

delay time tWCD —25 ns

CAS

pulse width 1 tCAS1 1.5 tcyc – 20 —ns

CAS

pulse width 2 tCAS2 1.0 tcyc – 20 —ns

CAS

pulse width 3 tCAS3 1.0 tcyc – 20 —ns

RAS

access time tRAC —2.5 tcyc – 40 ns

Address access time tAA —2.0 tcyc – 50 ns

CAS

access time tCAC —1.5 tcyc – 50 ns

setup time tWCS 0.5 tcyc – 20 —ns

hold ti me tWCH 0.5 tcyc – 15 —ns

Write data setup time tWDS 0.5 tcyc – 20 —ns

write data hold time tWDH 0.5 tcyc – 15 —ns

CAS

setup time 1 tCSR1 0.5 tcyc – 20 —ns

CAS

setup time 2 tCSR2 0.5 tcyc – 15 —ns

CAS

hold ti me tCHR 0.5 tcyc – 15 —ns

RAS

pulse width tRAS 1.5 tcyc – 15 —ns

Note: In order to secure the address hol d time relative to the rise of the

strobe, address

update mode 2 should be used. For details see section 6.3.5, Address Output Method.

Section 21 Electrical Characteristics

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Table 21.7 Timing of On-Chip Supporting Modules

Condition: Ta = –20°C to +75°C

Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 20 MHz

Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 25 MHz

Condition

A and B

Module Item Symbol Min Max Unit Test Conditions

Output data delay time tPWD —50 ns Figure 21.21Ports and

TPC Input data setup time tPRS 50 —ns

Input data hold ti me tPRH 50 —ns

16-bit ti mer Timer output delay time tTOCD —50 ns Figure 21.22

Timer input setup time tTICS 50 —ns

Timer clock input setup time tTCKS 50 —ns Figure 21.23

Single edge tTCKWH 1.5 — tcyc

Timer clock

pulse width Both edges tTCKWL 2.5 — tcyc

8-bit ti mer Timer output delay time t TOCD —50 ns Figure 21.22

Timer input setup time tTICS 50 —ns

Timer clock input setup time tTCKS 50 —ns Figure 21.23

Single edge tTCKWH 1.5 — tcyc

Timer clock

pulse width Both edges tTCKWL 2.5 — tcyc

Section 21 Electrical Characteristics

Rev. 3.00 Sep 14, 2005 page 686 of 910

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Condition

A and B

Module Item Symbol Min Max Unit Test Conditions

SCI Asynchronous tScyc 4 — tcyc Figure 21.24Input clock

cycle Synchronous 6 — tcyc

Input clock rise time tSCKr —1.5 tcyc

Input clock fall time tSCKf —1.5 tcyc

Input clock

pulse width tSCKW 0.4 0.6 tScyc

Transmit data delay time tTXD —100 ns Fi gure 21.25

Receive data setup time

(synchronous) tRXS 100 —ns

Clock input tRXH 100 —nsReceive

data hold

time (syn-

chronous)

Clock output 0 —ns

DMAC

TEND

delay time 1 tTED1 —50 ns

TEND

delay time 2 tTED2 —50 ns

Figure 21.25,

figure 21.26

DREQ

setup time tDRQS 25 —ns Figure 21.27

DREQ

hold ti me tDRQH 10 —ns

H8/3068F-ZTAT

output pin

C = 90 pF: ports 1 to 6, 8

C = 30 pF: ports 9, A, B

Input/output timing measurement

levels

• Low: 0.8 V

• High: 2.0 V

R = 2.4 k

R = 12 k

H Ω

Ω

Figure 21.3 Output Load Circuit

Section 21 Electrical Characteristics

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21.1.4 A/D Conversion Characteristics

Table 21.8 lists the A/D conversion characteristics.

Table 21.8 A/D Conversion Characteristics

Condition: Ta = –20°C to +75°C

Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 20 MHz

Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 25 MHz

Condition

A and B

Item Min Typ Max Unit

Conversion time: Resol ution 10 10 10 b its

134 states Conversion time (singl e mode) ——134 tcyc

Analog input capacitance ——20 pF

Permissible signal- φ ≤ 13 MHz ——10 kΩ

source impedance φ > 13 MHz ——5kΩ

4.0 V ≤ AVCC ≤ 5.5 V ——— kΩ

3.0 V ≤ AVCC < 4.0 V ——— kΩ

Nonlinearity error ——±3.5 LSB

Offset error ——±3.5 LSB

Full-scale error ——±3.5 LSB

Quantization error ——±0.5 LSB

Absolute accuracy ——±4.0 LSB

Section 21 Electrical Characteristics

Rev. 3.00 Sep 14, 2005 page 688 of 910

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Condition

A and B

Item Min Typ Max Unit

Conversion time: Resol ution 10 10 10 b its

70 states Conversion time (single mode) ——70 tcyc

Analog input capacitance ——20 pF

Permissible signal- φ ≤ 13 MHz ——5kΩ

source impedance φ > 13 MHz ——3kΩ

4.0 V ≤ AVCC ≤ 5.5 V ——— kΩ

3.0 V ≤ AVCC < 4.0 V ——— kΩ

Nonlinearity error ——±7.5 LSB

Offset error ——±7.5 LSB

Full-scale error ——±7.5 LSB

Quantization error ——±0.5 LSB

Absolute accuracy ——±8.0 LSB

Section 21 Electrical Characteristics

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21.1.5 D/A Conversion Characteristics

Table 21.9 lists the D/A conversion characteristics.

Table 21.9 D/A Conversion Characteristics

Condition: Ta = –20°C to +75°C

Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 20 MHz

Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,

fmax = 25 MHz

Condition

A and B

Item Min Typ Max Unit Test Conditions

Resolution 8 8 8 bits

Conversion time (centering time) ——10 µs 20 pF capaciti ve load

Absolute accuracy —±1.5 ±2.0 LSB 2 MΩ resistive load

——±1.5 LSB 4 MΩ resistive load

Section 21 Electrical Characteristics

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21.1.6 Flash Memory Characteristics

Table 21.10 shows the flash memory characteristics.

Table 21.10 Flash Memory Characteristics

Conditions: VCC = 4.5 to 5.5 V, AVCC = 4.5 to 5.5 V, VSS = AVSS = 0 V,

Ta = 0°C to +75°C (operating temperature range for programming/erasing)

Item Symbol Min Typ Max Unit Notes

Programming time*1 *2 *4tP— 10 200 ms/

128 bytes

Erase time*1 *3 *5tE— 100 1200 ms/block

Reprogramming count NWEC 100*610,000*7—Times

Data retention period tDRP 10*8— — Years

Programming Wait time after SWE bit setting*1tsswe 11 —µs

Wait time after PSU bit setting*1tspsu 50 50 — µs

Wait time after P bit setting*1 *4tsp30 28 30 32 µs Programming

time wait

tsp200 198 200 202 µs Programming

time wait

tsp10 8 10 12 µs Additional-

programming

time wait

Wait time after P bit clear*1tcp 55 —µs

Wait time after PSU bit clear*1tcpsu 55 —µs

Wait time after PV bit setting*1tspv 44 —µs

Wait time after H'FF dummy

write*1tspvr 22 —µs

Wait time after PV bit clear*1tcpv 22 —µs

Wait time after SWE bit clear*1tcswe 100 100 — µs

Maximum p rogra mming

count*1 *4N — — 1000 Times

Erase Wait time after SWE bit setting*1tsswe 11 —µs

Wait time after ESU bit setting*1tsesu 100 100 — µs

Wait time after E bit setting*1 *5tse 10 10 100 ms Erase time

wait

Wait time after E bit clear*1tce 10 10 — µs

Wait time after ESU bit clear*1tcesu 10 10 — µs

Section 21 Electrical Characteristics

Rev. 3.00 Sep 14, 2005 page 691 of 910

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Item Symbol Min Typ Max Unit Notes

Erase Wait time after EV bit setting*1tsev 20 20 — µs

Wait time after H'FF dummy

write*1tsevr 22 —µs

Wait time after EV bit clear*1tcev 44 —µs

Wait time after SWE bit clear*1tcswe 100 100 — µs

Maximum erase count*1 *4N12— 120Times

Notes: 1. Make each time setting i n accordance with the program/program-verify flowchart or

erase/erase-verify fl owchart.

2. Programming time per 128 bytes (Shows the total period for which the P-bit in the fl ash

memory control register (FLMCR1) is set. It does not include the programming

verification ti me.)

3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does

not include the erase verifi cation time.)

4. To specify the maximum programmi ng time (tP(max)) in the 128-byte programming

flowchart, set the maximum value (1000) for the maximum programming count (N).

The wait time after P bit setting should be changed as foll ows according to the val ue of

the programming counter (n).

Programming counter (n) = 1 to 6: tsp30 = 30 µ s

Programming counter (n) = 7 to 1000: tsp200 = 200 µs

Programming counter (n) [in additional programming] = 1 to 6: tsp10 = 10 µs

5. For the maximum erase time (tE(max)), the fol lowing relationship applies between the

wait time after E bit setting (tse) and the maximum erase count (N):

tE(max) = Wai t time after E bit setting (tse) × maximum erase count (N)

To set the ma ximum erase time, the values of tse and N should be set so as to satisfy

the above formula.

Examples: When tse = 100 [ms], N = 12 times

When tse = 10 [ms], N = 120 times

6. Minimum number of times at which all characteristics are guaranteed after

reprogramming. (Reprogramming count from 1 to minimum value is guaranteed.)

7. Reference characteristics at 25°C. (This is an indication that reprogramming operations

can normally be performed up to this figure.)

8. Data retention characteri stics when reprogramming is performed correctly within the

specifi cation values, including the minimum data retenti on period.

Section 21 Electrical Characteristics

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21.2 Operational Timing

This section shows timing diagrams.

21.2.1 Clock Timing

Clock timing is shown as follows:

• Oscillator settling timing

Figure 21.4 shows the oscillator settling timing.

STBY

RES

OSC1

Figure 21.4 Oscillator Settling Timing

Section 21 Electrical Characteristics

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21.2.2 Control Signal Timing

Control signal timing is shown as follows:

• Reset input timing

Figure 21.5 shows the reset input timing.

• Reset output timing*

Figure 21.6 shows the reset output timing.

• Interrupt input timing

Figure 21.7 shows the interrupt input timing for NMI and

IRQ

5 to

IRQ

φt

RESS

RESW

MDS

RES

FWE

to MD

Figure 21.5 Reset Input Timing

RESO

RESD

RESOW

RESD

Figure 21.6 Reset Output Timing*

Note: * This function is used only in mask ROM models, and is not provided in flash memory

models.

Section 21 Electrical Characteristics

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NMI

IRQ

NMIS

NMIH

NMIS

NMIH

NMIS

NMIW

NMI

IRQ

IRQ : Edge-sensitive IRQ

: Level-sensitive IRQ (i = 0 to 5)

IRQ

(j = 0 to 5)

Figure 21.7 Interrupt Input Timing

21.2.3 Bus Timing

Bus timing is shown as follows:

• Basic bus cycle: two-state access

Figure 21.8 shows the timing of the external two-state access cycle.

• Basic bus cycle: three-state access

Figure 21.9 shows the timing of the external three-state access cycle.

• Basic bus cycle: three-state access with one wait state

Figure 21.10 shows the timing of the external three-state access cycle with one wait state

inserted.

• Bus-release mode timing

Figure 21.11 shows the bus-release mode timing.

Section 21 Electrical Characteristics

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ASD

ACC3

AS1

cyc

RDS

PCH1

PCH2

RDH

PCH1

ASD

ACC3

AS1

ACC1

ASD

AS1

WSW1

WDS1

WDH

WDD

to A

(read)

to D

(read)

HWR, LWR

(write)

to D

(write)

Note:

Specification from the earliest negation timing of A

to A

, CS

, and RD.

RSD

Figure 21.8 Basic Bus Cycle: Two-State Access

Section 21 Electrical Characteristics

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ACC4

AS2

WDS2

WSW2

WSD

WDD

ACC2

RDS

to A

(read)

to D

(read)

HWR, LWR

(write)

to D

(write)

Figure 21.9 Basic Bus Cycle: Three-State Access

Section 21 Electrical Characteristics

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WTS

WTH

RD (read)

to D

(read)

HWR, LWR

(write)

to D

(write)

WAIT

WTH

to A

Figure 21.10 Basic Bus Cycle: Three-State Access with One Wait State

Section 21 Electrical Characteristics

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ASD

AS1

ACC4

RDS

ASD

AS1

ASD

AS1

ACC4

ACC2

RSD

RDH

ACC1

to A

CSn

to A

to D

Note: * Specification from the earliest ne

ation timin

of A23 to A0, CSn, and RD.

Figure 21.11 Burst ROM Access Timing: Two-State Access

Section 21 Electrical Characteristics

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ASD

AS1

ACC4

RDS

ASD

AS1

ASD

AS1

ACC4

ACC2

RSD

RDH*

ACC2

to A

CSn

to A

to D

Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD.

Figure 21.12 Burst ROM Access Timing: Three-State Access

BREQ

BACK

to A

AS, RD,

HWR, LWR

BRQS

BACD1

BZD

BACD2

BZD

Figure 21.13 Bus-Release Mode Timing

Section 21 Electrical Characteristics

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21.2.4 DRAM Interface Bus Timing

DRAM interface bus timing is shown as follows:

• DRAM bus timing: read and write access

Figure 21.14 shows the timing of the read and write access.

• DRAM bus timing: CAS before RAS refresh

Figure 21.15 shows the timing of the CAS before RAS refresh.

• DRAM bus timing: self-refresh

Figure 21.16 shows the timing of the self-refresh.

Section 21 Electrical Characteristics

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AS1

RAD1

RAD2

CASD2

ASD

CAS1

RDH

CASD2

CAS2

CASD1

CAC

RDS

RAC

RAH

WCD

WCH

WCS

WDD

WDS

WDH

ASD

to A

to CS

(RAS

to RAS

)

UCAS, LCAS

(read)

RD (WE)

(read) High

High

UCAS, LCAS

(write)

RD (WE)

(write)

to D

(read)

to D

(write)

RFSH

Note: * Specification from the earliest negation timing of RAS and CAS.

Figure 21.14 DRAM Bus Timing (Read/Write)

Section 21 Electrical Characteristics

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RAD1

CASD1

CASD2

RAD2

RAS

to CS

(RAS

RAS

)

UCAS,

LCAS

RD (WE)

(high)

RFSH

CSR1

RAD1

CSR1

CHR

RAS

RAD2

CHR

CAS3

Figure 21.15 DRAM Bus Timing (CAS Before RAS Refresh)

Section 21 Electrical Characteristics

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CSR2

to CS

(RAS

RAS

)

UCAS,

LCAS

RD (WE)

(high)

RFSH

Figure 21.16 DRAM Bus Timing (Self-Refresh)

21.2.5 TPC and I/O Port Timing

Figure 21.17 shows the TPC and I/O port input/output timing.

Port 1 to

B (read)

Port 1 to

6, 8 to B

(write)

PRS

PRH

PWD

Figure 21.17 TPC and I/O Port Input/Output Timing

Section 21 Electrical Characteristics

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21.2.6 Timer Input/Output Timing

16-bit timer and 8-bit timer timing is shown below.

• Timer input/output timing

Figure 21.18 shows the timer input/output timing.

• Timer external clock input timing

Figure 21.19 shows the timer external clock input timing.

Output

compare

Input

capture

TOCD

TICS

Notes: 1. TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TMO0, TMO2, TMIO1, TMIO3

2. TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TMIO1, TMIO3

Figure 21.18 Timer Input/Output Timing

φt

TCKS

TCKWH

TCKWL

TCLKA to

TCLKD

Figure 21.19 Timer External Clock Input Timing

Section 21 Electrical Characteristics

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21.2.7 SCI Input/Output Timing

SCI timing is shown as follows:

• SCI input clock timing

Figure 21.20 shows the SCI input clock timing.

• SCI input/output timing (synchronous mode)

Figure 21.21 shows the SCI input/output timing in synchronous mode.

SCK

, SCK

SCKW

Scyc

SCKr

SCKf

Figure 21.20 SCI Input Clock Timing

Scyc

TXD

RXS

RXH

SCK

TxD

, TxD

(transmit

data)

RxD

, RxD

(receive

data

)

Figure 21.21 SCI Input/Output Timing in Synchronous Mode

Section 21 Electrical Characteristics

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21.2.8 DMAC Timing

DMAC timing is shown as follows.

• DMAC

TEND

output timing for 2 state access

Figure 21.22 shows the DMAC

TEND

output timing for 2 state access.

• DMAC

TEND

output timing for 3 state access

Figure 21.23 shows the DMAC

TEND

output timing for 3 state access.

• DMAC

DREQ

input timing

Figure 21.24 shows DMAC

DREQ

input timing.

TED1

TED2

TEND

Figure 21.22 DMAC

TEND

Output Timing for 2 State Access

TED1

TED2

TEND

Figure 21.23 DMAC

TEND

Output Timing for 3 State Access

DRQH

DRQS

DREQ

Figure 21.24 DMAC

DREQ

Input Timing

Appendix A Instruction Set

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Appendix A Instruction Set

A.1 Instruction List

Operand Notation

Symbol Description

Rd General destination register

Rs General source register

Rn General register

ERd General destination register (address register or 32-bit register)

ERs General source register (address register or 32-bit register)

ERn General register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

PC Program counter

SP Stack pointer

CCR Condition code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

disp Displacement

→Transfer from the operand on the left to the operand on the right, or transition from

the state on the left to the state on the right

+ Addition of the operands on both sides

– Subtraction of the operand on the right from the operand on the left

×Multiplication of the operands on both sides

÷ Division of the operand on the left by the operand on the right

∧Logical AND of the operands on both sides

∨Logical OR of the operands on both sides

⊕Exclusive logical OR of the operands on both sides

¬ NOT (logical complement)

( ), < > Contents of operand

Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers

(R0 to R7 and E0 to E7).

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 708 of 910

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Condition Code Notation

Symbol Description

Changed according to execution result

*Undetermined (no guaranteed value)

0 Cleared to 0

1 Set to 1

— Not affected by execution of the instructi o n

∆Varies depending on conditions, described in notes

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 709 of 910

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Table A.1 Instruction Set

1. Data transfer instructions

Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States*1

I H N Z V C

MOV.B #xx:8, Rd

MOV.B Rs, Rd

MOV.B @ERs, Rd

MOV.B @(d:16,

ERs), Rd

MOV.B @(d:24,

ERs), Rd

MOV.B @ERs+, Rd

MOV.B @aa:8, Rd

MOV.B @aa:16, Rd

MOV.B @aa:24, Rd

MOV.B Rs, @ERd

MOV.B Rs, @(d:16,

ERd)

MOV.B Rs, @(d:24,

ERd)

MOV.B Rs, @–ERd

MOV.B Rs, @aa:8

MOV.B Rs, @aa:16

MOV.B Rs, @aa:24

MOV.W #xx:16, Rd

MOV.W Rs, Rd

MOV.W @ERs, Rd

MOV.W @(d:16,

ERs), Rd

MOV.W @(d:24,

ERs), Rd

MOV.W @ERs+, Rd

MOV.W @aa:16, Rd

#xx:8 → Rd8

Rs8 → Rd8

@ERs → Rd8

@(d:16, ERs) → Rd8

@(d:24, ERs) → Rd8

@ERs → Rd8

ERs32+1 → ERs32

@aa:8 → Rd8

@aa:16 → Rd8

@aa:24 → Rd8

Rs8 → @ERd

Rs8 → @(d:16, ERd)

Rs8 → @(d:24, ERd)

ERd32–1 → ERd32

Rs8 → @ERd

Rs8 → @aa:8

Rs8 → @aa:16

Rs8 → @aa:24

#xx:16 → Rd16

Rs16 → Rd16

@ERs → Rd16

@(d:16, ERs) → Rd16

@(d:24, ERs) → Rd16

@ERs → Rd16

ERs32+2 → @ERd32

@aa:16 → Rd16

— — 0 —

↔

↔↔

↔

↔↔

↔

↔↔

↔

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 710 of 910

REJ09B0258-0300

Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States

I H N Z V C

MOV.W @aa:24, Rd

MOV.W Rs, @ERd

MOV.W Rs, @(d:16,

ERd)

MOV.W Rs, @(d:24,

ERd)

MOV.W Rs, @–ERd

MOV.W Rs, @aa:16

MOV.W Rs, @aa:24

MOV.L #xx:32, Rd

MOV.L ERs, ERd

MOV.L @ERs, ERd

MOV.L @(d:16, ERs),

ERd

MOV.L @(d:24, ERs),

ERd

MOV.L @ERs+, ERd

MOV.L @aa:16, ERd

MOV.L @aa:24, ERd

MOV.L ERs, @ERd

MOV.L ERs, @(d:16,

ERd)

MOV.L ERs, @(d:24,

ERd)

MOV.L ERs, @–ERd

MOV.L ERs, @aa:16

MOV.L ERs, @aa:24

POP.W Rn

POP.L ERn

@aa:24 → Rd16

Rs16 → @ERd

Rs16 → @(d:16, ERd)

Rs16 → @(d:24, ERd)

ERd32–2 → ERd32

Rs16 → @ERd

Rs16 → @aa:16

Rs16 → @aa:24

#xx:32 → Rd32

ERs32 → ERd32

@ERs → ERd32

@(d:16, ERs) → ERd32

@(d:24, ERs) → ERd32

@ERs → ERd32

ERs32+4 → ERs32

@aa:16 → ERd32

@aa:24 → ERd32

ERs32 → @ERd

ERs32 → @(d:16, ERd)

ERs32 → @(d:24, ERd)

ERd32–4 → ERd32

ERs32 → @ERd

ERs32 → @aa:16

ERs32 → @aa:24

@SP → Rn16

SP+2 → SP

@SP → ERn32

SP+4 → SP

— — 0 —

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 711 of 910

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Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States*1

I H N Z V C

PUSH.W Rn

PUSH.L ERn

MOVFPE @aa:16,

MOVTPE Rs,

@aa:16

SP–2 → SP

Rn16 → @SP

SP–4 → SP

ERn32 → @SP

Cannot be used in the

H8/3068F

Cannot be used in the

H8/3068F

— — 0 —

Cannot be used in the

H8/3068F

Cannot be used in the

H8/3068F

↔

↔↔

↔

Appendix A Instruction Set

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2. Arithmetic instructions

Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States

I H N Z V C

ADD.B #xx:8, Rd

ADD.B Rs, Rd

ADD.W #xx:16, Rd

ADD.W Rs, Rd

ADD.L #xx:32, ERd

ADD.L ERs, ERd

ADDX.B #xx:8, Rd

ADDX.B Rs, Rd

ADDS.L #1, ERd

ADDS.L #2, ERd

ADDS.L #4, ERd

INC.B Rd

INC.W #1, Rd

INC.W #2, Rd

Rd8+#xx:8 → Rd8

Rd8+Rs8 → Rd8

Rd16+#xx:16 → Rd16

Rd16+Rs16 → Rd16

ERd32+#xx:32 →

ERd32

ERd32+ERs32 →

ERd32

Rd8+#xx:8 +C → Rd8

Rd8+Rs8 +C → Rd8

ERd32+1 → ERd32

ERd32+2 → ERd32

ERd32+4 → ERd32

Rd8+1 → Rd8

Rd16+1 → Rd16

Rd16+2 → Rd16

—

— (1)

— (2)

— (3)

— — — — — —

— — —

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔↔ ↔↔

↔

Appendix A Instruction Set

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Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States*1

I H N Z V C

INC.L #1, ERd

INC.L #2, ERd

DAA Rd

SUB.B Rs, Rd

SUB.W #xx:16, Rd

SUB.W Rs, Rd

SUB.L #xx:32, ERd

SUB.L ERs, ERd

SUBX.B #xx:8, Rd

SUBX.B Rs, Rd

SUBS.L #1, ERd

SUBS.L #2, ERd

SUBS.L #4, ERd

DEC.B Rd

DEC.W #1, Rd

DEC.W #2, Rd

DEC.L #1, ERd

DEC.L #2, ERd

DAS.Rd

MULXU. B Rs, Rd

MULXU. W Rs, ERd

MULXS. B Rs, Rd

MULXS. W Rs, ERd

DIVXU. B Rs, Rd

ERd32+1 → ERd32

ERd32+2 → ERd32

Rd8 decimal adjust

→ Rd8

Rd8–Rs8 → Rd8

Rd16–#xx:16 → Rd16

Rd16–Rs16 → Rd16

ERd32–#xx:32

→ ERd32

ERd32–ERs32

→ ERd32

Rd8–#xx:8–C → Rd8

Rd8–Rs8–C → Rd8

ERd32–1 → ERd32

ERd32–2 → ERd32

ERd32–4 → ERd32

Rd8–1 → Rd8

Rd16–1 → Rd16

Rd16–2 → Rd16

ERd32–1 → ERd32

ERd32–2 → ERd32

Rd8 decimal adjust

→ Rd8

Rd8 × Rs8 → Rd16

(unsigned multiplication)

Rd16 × Rs16 → ERd32

(unsigned multiplication)

Rd8 × Rs8 → Rd16

(signed multiplication)

Rd16 × Rs16 → ERd32

(signed multiplication)

Rd16 ÷ Rs8 → Rd16

(RdH: remainder, RdL:

quotient)

(unsigned division)

— — —

— * * —

—

— (1)

— (2)

— (3)

— — — — — —

— — —

— * * —

— — — — — —

— — — —

— — (6) (7) — —

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 714 of 910

REJ09B0258-0300

Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States

I H N Z V C

DIVXU. W Rs, ERd

DIVXS. B Rs, Rd

DIVXS. W Rs, ERd

CMP.B #xx:8, Rd

CMP.B Rs, Rd

CMP.W #xx:16, Rd

CMP.W Rs, Rd

CMP.L #xx:32, ERd

CMP.L ERs, ERd

NEG.B Rd

NEG.W Rd

NEG.L ERd

EXTU.W Rd

EXTU.L ERd

EXTS.W Rd

EXTS.L ERd

ERd32 ÷ Rs16 → ERd32

(Ed: remainder,

Rd: quotient)

(unsigned division)

Rd16 ÷ Rs8 → Rd16

(RdH: remainder,

RdL: quotient)

(signed division)

ERd32 ÷ Rs16 → ERd32

(Ed: remainder,

Rd: quotient)

(signed division)

Rd8–#xx:8

Rd8–Rs8

Rd16–#xx:16

Rd16–Rs16

ERd32–#xx:32

ERd32–ERs32

0–Rd8 → Rd8

0–Rd16 → Rd16

0–ERd32 → ERd32

0 → (<bits 15 to 8>

of Rd16)

0 → (<bits 31 to 16>

of ERd32)

(<bit 7> of Rd16) →

(<bits 15 to 8> of Rd16)

(<bit 15> of ERd32) →

(<bits 31 to 16> of

ERd32)

— — (6) (7) — —

— — (8) (7) — —

—

— (1)

— (2)

—

— — 0 0 —

— — 0 —

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔↔↔

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 715 of 910

REJ09B0258-0300

3. Logic instructions

Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States

I H N Z V C

AND.B #xx:8, Rd

AND.B Rs, Rd

AND.W #xx:16, Rd

AND.W Rs, Rd

AND.L #xx:32, ERd

AND.L ERs, ERd

OR.B #xx:8, Rd

OR.B Rs, Rd

OR.W #xx:16, Rd

OR.W Rs, Rd

OR.L #xx:32, ERd

OR.L ERs, ERd

XOR.B #xx:8, Rd

XOR.B Rs, Rd

XOR.W #xx:16, Rd

XOR.W Rs, Rd

XOR.L #xx:32, ERd

XOR.L ERs, ERd

NOT.B Rd

NOT.W Rd

NOT.L ERd

Rd8∧#xx:8 → Rd8

Rd8∧Rs8 → Rd8

Rd16∧#xx:16 → Rd16

Rd16∧Rs16 → Rd16

ERd32∧#xx:32 → ERd32

ERd32∧ERs32 → ERd32

Rd8∨#xx:8 → Rd8

Rd8∨Rs8 → Rd8

Rd16∨#xx:16 → Rd16

Rd16∨Rs16 → Rd16

ERd32∨#xx:32 → ERd32

ERd32∨ERs32 → ERd32

Rd8⊕#xx:8 → Rd8

Rd8⊕Rs8 → Rd8

Rd16⊕#xx:16 → Rd16

Rd16⊕Rs16 → Rd16

ERd32⊕#xx:32 → ERd32

ERd32⊕ERs32 → ERd32

¬Rd8 → Rd8

¬Rd16 → Rd16

¬Rd32 → Rd32

— — 0 —

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔

↔↔

↔

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 716 of 910

REJ09B0258-0300

4. Shift instructions

Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States

I H N Z V C

SHAL.B Rd

SHAL.W Rd

SHAL.L ERd

SHAR.B Rd

SHAR.W Rd

SHAR.L ERd

SHLL.B Rd

SHLL.W Rd

SHLL.L ERd

SHLR.B Rd

SHLR.W Rd

SHLR.L ERd

ROTXL.B Rd

ROTXL.W Rd

ROTXL.L ERd

ROTXR.B Rd

ROTXR.W Rd

ROTXR.L ERd

ROTL.B Rd

ROTL.W Rd

ROTL.L ERd

ROTR.B Rd

ROTR.W Rd

ROTR.L ERd

— —

— — 0

↔

↔↔

↔

↔↔↔

↔

↔↔

↔

↔↔↔

↔

↔↔

↔

↔↔↔

↔

↔↔

↔

↔↔↔

↔

↔↔

↔

↔↔↔

↔

↔↔

↔

↔↔↔

↔

↔↔

↔

↔↔↔

↔

↔↔

↔

↔↔↔

MSB LSB

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 717 of 910

REJ09B0258-0300

5. Bit manipulation instructions

Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States

I H N Z V C

BSET #xx:3, Rd

BSET #xx:3, @ERd

BSET #xx:3, @aa:8

BSET Rn, Rd

BSET Rn, @ERd

BSET Rn, @aa:8

BCLR #xx:3, Rd

BCLR #xx:3, @ERd

BCLR #xx:3, @aa:8

BCLR Rn, Rd

BCLR Rn, @ERd

BCLR Rn, @aa:8

BNOT #xx:3, Rd

BNOT #xx:3, @ERd

BNOT #xx:3, @aa:8

BNOT Rn, Rd

BNOT Rn, @ERd

BNOT Rn, @aa:8

BTST #xx:3, Rd

BTST #xx:3, @ERd

BTST #xx:3, @aa:8

BTST Rn, Rd

BTST Rn, @ERd

BTST Rn, @aa:8

BLD #xx:3, Rd

(#xx:3 of Rd8) ← 1

(#xx:3 of @ERd) ← 1

(#xx:3 of @aa:8) ← 1

(Rn8 of Rd8) ← 1

(Rn8 of @ERd) ← 1

(Rn8 of @aa:8) ← 1

(#xx:3 of Rd8) ← 0

(#xx:3 of @ERd) ← 0

(#xx:3 of @aa:8) ← 0

(Rn8 of Rd8) ← 0

(Rn8 of @ERd) ← 0

(Rn8 of @aa:8) ← 0

(#xx:3 of Rd8) ←

¬ (#xx:3 of Rd8)

(#xx:3 of @ERd) ←

¬ (#xx:3 of @ERd)

(#xx:3 of @aa:8) ←

¬ (#xx:3 of @aa:8)

(Rn8 of Rd8) ←

¬ (Rn8 of Rd8)

(Rn8 of @ERd) ←

¬ (Rn8 of @ERd)

(Rn8 of @aa:8) ←

¬ (Rn8 of @aa:8)

¬ (#xx:3 of Rd8) → Z

¬ (#xx:3 of @ERd) → Z

¬ (#xx:3 of @aa:8) → Z

¬ (Rn8 of @Rd8) → Z

¬ (Rn8 of @ERd) → Z

¬ (Rn8 of @aa:8) → Z

(#xx:3 of Rd8) → C

— — — — — —

— — — — —

↔↔↔↔↔

↔

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 718 of 910

REJ09B0258-0300

Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States

I H N Z V C

BLD #xx:3, @ERd

BLD #xx:3, @aa:8

BILD #xx:3, Rd

BILD #xx:3, @ERd

BILD #xx:3, @aa:8

BST #xx:3, Rd

BST #xx:3, @ERd

BST #xx:3, @aa:8

BIST #xx:3, Rd

BIST #xx:3, @ERd

BIST #xx:3, @aa:8

BAND #xx:3, Rd

BAND #xx:3, @ERd

BAND #xx:3, @aa:8

BIAND #xx:3, Rd

BIAND #xx:3, @ERd

BIAND #xx:3, @aa:8

BOR #xx:3, Rd

BOR #xx:3, @ERd

BOR #xx:3, @aa:8

BIOR #xx:3, Rd

BIOR #xx:3, @ERd

BIOR #xx:3, @aa:8

BXOR #xx:3, Rd

BXOR #xx:3, @ERd

BXOR #xx:3, @aa:8

BIXOR #xx:3, Rd

BIXOR #xx:3, @ERd

BIXOR #xx:3, @aa:8

(#xx:3 of @ERd) → C

(#xx:3 of @aa:8) → C

¬ (#xx:3 of Rd8) → C

¬ (#xx:3 of @ERd) → C

¬ (#xx:3 of @aa:8) → C

C → (#xx:3 of Rd8)

C → (#xx:3 of @ERd24)

C → (#xx:3 of @aa:8)

¬ C → (#xx:3 of Rd8)

¬ C → (#xx:3 of @ERd24)

¬ C → (#xx:3 of @aa:8)

C∧(#xx:3 of Rd8) → C

C∧(#xx:3 of @ERd24) → C

C∧(#xx:3 of @aa:8) → C

C∧ ¬ (#xx:3 of Rd8) → C

C∧ ¬ (#xx:3 of @ERd24) → C

C∧ ¬ (#xx:3 of @aa:8) → C

C∨(#xx:3 of Rd8) → C

C∨(#xx:3 of @ERd24) → C

C∨(#xx:3 of @aa:8) → C

C∨ ¬ (#xx:3 of Rd8) → C

C∨ ¬ (#xx:3 of @ERd24) → C

C∨ ¬ (#xx:3 of @aa:8) → C

C⊕(#xx:3 of Rd8) → C

C⊕(#xx:3 of @ERd24) → C

C⊕(#xx:3 of @aa:8) → C

C⊕ ¬ (#xx:3 of Rd8) → C

C⊕

(#xx:3 of @ERd24) → C

C⊕ ¬ (#xx:3 of @aa:8) → C

— — — — —

— — — — — —

— — — — —

↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 719 of 910

REJ09B0258-0300

6. Branching instructions

Mnemonic Operation Branch

Condition

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States

I H N Z V C

BRA d:8 (BT d:8)

BRA d:16 (BT d:16)

BRN d:8 (BF d:8)

BRN d:16 (BF d:16)

BHI d:8

BHI d:16

BLS d:8

BLS d:16

BCC d:8 (BHS d:8)

BCC d:16 (BHS d:16)

BCS d:8 (BLO d:8)

BCS d:16 (BLO d:16)

BNE d:8

BNE d:16

BEQ d:8

BEQ d:16

BVC d:8

BVC d:16

BVS d:8

BVS d:16

BPL d:8

BPL d:16

BMI d:8

BMI d:16

BGE d:8

BGE d:16

BLT d:8

BLT d:16

BGT d:8

BGT d:16

—

If condition

is true then

PC ←

PC+d else

next;

— — — — — —

Always

Never

C ∨ Z = 0

C ∨ Z = 1

C = 0

C = 1

Z = 0

Z = 1

V = 0

V = 1

N = 0

N = 1

N⊕V = 0

N⊕V = 1

Z ∨ (N⊕V)

= 0

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 720 of 910

REJ09B0258-0300

Mnemonic OperationOperation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States

I H N Z V C

BLE d:8

BLE d:16

JMP @ERn

JMP @aa:24

JMP @@aa:8

BSR d:8

BSR d:16

JSR @ERn

JSR @aa:24

JSR @@aa:8

RTS

—

PC ← ERn

PC ← aa:24

PC ← @aa:8

PC → @–SP

PC ← PC+d:8

PC → @–SP

PC ← PC+d:16

PC → @–SP

PC ← @ERn

PC → @–SP

PC ← @aa:24

PC → @–SP

PC ← @aa:8

PC ← @SP+

— — — — — —

Branch

Condition

If condition

is true then

PC ← PC+d

else next;

Z ∨ (N⊕V) = 1

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 721 of 910

REJ09B0258-0300

7. System control instructions

Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States*1

I H N Z V C

TRAPA #x:2

RTE

SLEEP

LDC #xx:8, CCR

LDC Rs, CCR

LDC @ERs, CCR

LDC @(d:16, ERs),

CCR

LDC @(d:24, ERs),

CCR

LDC @ERs+, CCR

LDC @aa:16, CCR

LDC @aa:24, CCR

STC CCR, Rd

STC CCR, @ERd

STC CCR, @(d:16,

ERd)

STC CCR, @(d:24,

ERd)

STC CCR, @–ERd

STC CCR, @aa:16

STC CCR, @aa:24

ANDC #xx:8, CCR

ORC #xx:8, CCR

XORC #xx:8, CCR

NOP

—

PC → @–SP

CCR → @–SP

<vector> → PC

CCR ← @SP+

PC ← @SP+

Transition to

powerdown state

#xx:8 → CCR

Rs8 → CCR

@ERs → CCR

@(d:16, ERs) → CCR

@(d:24, ERs) → CCR

@ERs → CCR

ERs32+2 → ERs32

@aa:16 → CCR

@aa:24 → CCR

CCR → Rd8

CCR → @ERd

CCR → @(d:16, ERd)

CCR → @(d:24, ERd)

ERd32–2 → ERd32

CCR → @ERd

CCR → @aa:16

CCR → @aa:24

CCR∧#xx:8 → CCR

CCR∨#xx:8 → CCR

CCR⊕#xx:8 → CCR

PC ← PC+2

1 — — — — —

— — — — — —

14 16

↔

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 722 of 910

REJ09B0258-0300

8. Block transfer instructions

Mnemonic Operation

Condition Code

Operand Size

#xx

@ERn

@(d, ERn)

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

Addressing Mode and

Instruction Length (bytes)

Normal

Advanced

No. of

States

I H N Z V C

EEPMOV. B

EEPMOV. W

—

if R4L ≠ 0

repeat @R5 → @R6

R5+1 → R5

R6+1 → R6

R4L–1 → R4L

until R4L=0

else next;

if R4 ≠ 0

repeat @R5 → @R6

R5+1 → R5

R6+1 → R6

R4–1 → R4

until R4=0

else next;

— — — — — —

Notes: 1. The number of states is the number of states required for execution when the

instruction and its operands are located in on-chip memory. For other cases see

section A.3, Number of States Required for Execution.

2. n is the value set in register R4L or R4.

(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.

(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.

(3) Retains its previous value when the result is zero; otherwise cleared to 0.

(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous val ue.

(5) The number of states required for execution of an instruction that transfers data in

synchronization with the E clock is variable.

(6) Set to 1 when the divisor is negative; otherwise cleared to 0.

(7) Set to 1 when the divisor is zero; otherwise cleared to 0.

(8) Set to 1 when the quotient is negative; otherwise cleared to 0.

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 723 of 910

REJ09B0258-0300

A.2 Operation Code Maps

Table A.2 Operation Code Map (1)

AH AL 0123456789ABCDEF

NOP

BRA

MULXU

BSET

BRN

DIVXU

BNOT

STC

BHI

MULXU

BCLR

LDC

BLS

DIVXU

BTST

ORC

OR.B

BCC

RTS

XORC

XOR.B

BCS

BSR

XOR

BOR

BIOR

BXOR

BIXOR

BAND

BIAND

ANDC

AND.B

BNE

RTE

AND

LDC

BNQ

TRAPA

BLD

BILD

BST

BIST

BVC

MOV

BPL

JMP

BMI

ADDX

SUBX

BGT

JSR

BLE

MOV

ADD

ADDX

CMP

SUBX

XOR

AND

MOV

Instruction when most significant bit of BH is 0.

Instruction when most significant bit of BH is 1.

Instruction code:

Table A.2

(2) Table A.2

(2)

BVS BLTBGE

BSR

Table A.2

(2)

Table A.2

(2)

Table A.2

(2)

Table A.2

(2)

Table A.2

(2)

Table A.2

(2)

Table A.2

(2)

Table A.2

(2)

Table A.2

(2) Table A.2

(3)

1st byte 2nd byte

AH BHAL BL

ADD

SUB

MOV

CMP

MOV.B

EEPMOV

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 724 of 910

REJ09B0258-0300

Table A.2 Operation Code Map (2)

AH ALBH 0123456789ABCDEF

MOV

INC

ADDS

DAA

DEC

SUBS

DAS

BRA

MOV

BHI

CMP

LDC/STC

BCC

BPL BGT

Instruction code:

BVS

SLEEP

BVC BGE

Table A.2

(3)

Table A.2

(3) Table A.2

(3)

BNE

AND

INC

EXTU

DEC

BEQ

INC

EXTU

DEC

BCS

XOR

SHLL

SHLR

ROTXL

ROTXR

NOT

BLS

SUB

BRN

ADD

INC

EXTS

DEC

BLT

INC

EXTS

DEC

BLE

SHAL

SHAR

ROTL

ROTR

NEG

BMI

1st byte 2nd byte

AH BHAL BL

SUBS

ADDS

ADD

MOV

SUB

CMP

SHLL

SHLR

ROTXL

ROTXR

NOT

SHAL

SHAR

ROTL

ROTR

NEG

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 725 of 910

REJ09B0258-0300

Table A.2 Operation Code Map (3)

ALBH

BLCH

0123456789ABCDEF

01406

01C05

01D05

01F06

7Cr06

7Cr07

7Dr06

7Dr07

7Eaa6

7Eaa7

7Faa6

7Faa7

MULXS

BSET

DIVIXS

BNOT

MULXS

BCLR

DIVXS

BTST

OR XOR

BOR

BIOR

BXOR

BIXOR

BAND

BIAND

AND

BLD

BILD

BST

BIST

Instruction when most significant bit of DH is 0.

Instruction when most significant bit of DH is 1.

Instruction code:

BOR

BIOR

BXOR

BIXOR

BAND

BIAND

BLD

BILD

BST

BIST

Notes: 1.

2. r is the register designation field.

aa is the absolute address field.

1st byte 2nd byte

AH BHAL BL 3rd byte

CH DHCL DL

4th byte

LDCSTC LDC LDC LDC

STC STC STC

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 726 of 910

REJ09B0258-0300

A.3 Number of States Required for Execution

The tables in this section can be used to calculate the number of states required for instruction

execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data

read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of

states required per cycle according to the bus size. The number of states required for execution of

an instruction can be calculated from these two tables as follows:

Number of states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN

Examples of Calculation of Number of States Required for Execution

Examples: Advanced mode, stack located in external address space, on-chip supporting modules

accessed with 8-bit bus width, external devices accessed in three states with one wait state and

16-bit bus width.

BSET #0, @FFFFC7:8

From table A.4, I = L = 2 and J = K = M = N = 0

From table A.3, SI = 4 and SL = 3

Number of states = 2 × 4 + 2 × 3 = 14

JSR @@30

From table A.4, I = J = K = 2 and L = M = N = 0

From table A.3, SI = SJ = SK = 4

Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 727 of 910

REJ09B0258-0300

Table A.3 Number of States per Cycle

Access Conditions

On-Chip Sup- External Device

porting Module 8-Bit Bus 16-Bit Bus

Execution State

(Cycle) On-Chip

Memory 8-Bit

Bus 16-Bit

Bus 2-State

Access 3-State

Access 2-State

Access 3-State

Access

Instruction fetch SI2 6 3 4 6 + 2m 2 3 + m

Branch address read SJ

Stack operation SK

Byte data access SL323 + m

Word data access SM6 4 6 + 2m

Internal operati on SN1

Legend

m: Number of wait states inserted into external device access

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 728 of 910

REJ09B0258-0300

Table A.4 Number of Cycles per Instruction

Instruction Mnemonic

Instruction

Fetch

Branch

Addr. Read

Stack

Operation

Byte Data

Access

Word Data

Access

Internal

Operation

ADD ADD.B #x x :8, Rd

ADD.B Rs, Rd

ADD.W #xx:16, Rd

ADD.W Rs, Rd

ADD.L #xx:32, ERd

ADD.L ERs, ERd

ADDS ADDS #1/2/4, ERd 1

ADDX ADDX #xx:8, Rd

ADDX Rs , Rd 1

AND AND.B #x x :8, Rd

AND.B Rs, Rd

AND.W #xx:16, Rd

AND.W Rs, Rd

AND.L #xx:32, ERd

AND.L ERs, ERd

ANDC ANDC #xx:8, CCR 1

BAND BAND #xx:3, Rd

BAND #xx:3, @ERd

BAND #xx:3, @aa:8

Bcc BRA d:8 (BT d:8)

BRN d:8 (BF d:8)

BHI d:8

BLS d:8

BCC d:8 (BHS d:8)

BCS d:8 (BLO d:8)

BNE d:8

BEQ d:8

BVC d:8

BVS d:8

BPL d:8

BMI d:8

BGE d:8

BLT d:8

BGT d:8

BLE d:8

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 729 of 910

REJ09B0258-0300

Instruction Mnemonic

Instruction

Fetch

Branch

Addr. Read

Stack

Operation

Byte Data

Access

Word Data

Access

Internal

Operation

Bcc BRA d:16 (BT d:16)

BRN d:16 (BF d:16)

BHI d:16

BLS d:16

BCC d:16 (BHS d:16)

BCS d:16 (BLO d:16)

BNE d:16

BEQ d:16

BVC d:16

BVS d:16

BPL d:16

BMI d:16

BGE d:16

BLT d:16

BGT d:16

BLE d:16

BCLR BCLR #xx:3, Rd

BCLR #xx:3, @ERd

BCLR #xx:3, @aa:8

BCLR Rn, Rd

BCLR Rn, @ERd

BCLR Rn, @aa:8

BIAND BIAND #xx:3, Rd

BIAND #xx :3, @ERd

BIAND #xx:3, @aa:8

BILD BILD #xx:3, Rd

BILD #xx:3, @ERd

BILD #xx:3, @aa:8

BIOR BIOR #xx:8, Rd

BIOR #xx:8, @ERd

BIOR #xx:8, @aa:8

BIST BIST #xx:3, Rd

BIST #xx:3, @ERd

BIST #xx:3, @aa:8

BIXOR BIXOR #xx:3, Rd

BIXOR #xx:3, @ERd

BIXOR #xx:3, @aa:8

BLD BLD #xx:3, Rd

BLD #xx:3, @ERd

BLD #xx:3, @aa:8

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 730 of 910

REJ09B0258-0300

Instruction Mnemonic

Instruction

Fetch

Branch

Addr. Read

Stack

Operation

Byte Data

Access

Word Data

Access

Internal

Operation

BNOT BNOT #xx:3, Rd

BNOT #xx:3, @ERd

BNOT #xx:3, @aa:8

BNOT Rn, Rd

BNOT Rn, @ERd

BNOT Rn, @aa:8

BOR BOR #xx:3, Rd

BOR #xx:3, @E Rd

BOR #xx:3, @aa:8

BSET BSET #xx:3, Rd

BSET #xx:3, @ERd

BSET #xx:3, @aa:8

BSET Rn, Rd

BSET Rn, @ERd

BSET Rn, @aa:8

BSR BSR d:8 Normal 2 1

Advanced 2 2

BSR d:16 Normal 2 1 2

Advanced 2 2 2

BST BST #xx:3, Rd

BST #xx:3, @ERd

BST #xx:3, @aa:8

BTST BTST #xx:3, Rd

BTST #xx:3, @ERd

BTST #xx:3, @aa:8

BTST Rn, Rd

BTST Rn, @ERd

BTST Rn, @aa:8

BXOR BXOR #xx:3, Rd

BXOR #xx :3, @ERd

BXOR #xx:3, @aa:8

CMP CMP.B #xx:8, Rd

CMP.B Rs, Rd

CMP.W #xx:16, Rd

CMP.W Rs, Rd

CMP.L #xx:32, ERd

CMP.L ERs, ERd

DAA DAA Rd 1

DAS DAS Rd 1

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 731 of 910

REJ09B0258-0300

Instruction Mnemonic

Instruction

Fetch

Branch

Addr. Read

Stack

Operation

Byte Data

Access

Word Data

Access

Internal

Operation

DEC DEC.B Rd

DEC.W #1/2, Rd

DEC.L #1/2, ERd

DIVXS DIVXS.B Rs, Rd

DIVXS.W Rs, ERd 2

212

DIVXU DIVX U.B Rs, Rd

DIVXU.W Rs, ERd 1

112

EEPMOV EEPMOV.B

EEPMOV.W 2

22n + 2*1

2n + 2*1

EXTS EXTS.W Rd

EXTS.L ERd 1

EXTU EXTU.W Rd

EXTU.L ERd 1

INC INC.B Rd

INC.W #1/2, Rd

INC.L #1/2, ERd

JMP JMP @ERn 2

JMP @aa:24 2 2

JMP @@aa:8 Normal 2 1 2

Advanced 2 2 2

JSR JSR @ERn Normal 2 1

Advanced 2 2

JSR @aa:24 Normal 2 1 2

Advanced 2 2 2

JSR @@aa:8 Normal 2 1 1

Advanced 2 2 2

LDC LDC #x x :8, CCR

LDC Rs, CCR

LDC @ERs , CCR

LDC @(d:16, ERs), CCR

LDC @(d:24, ERs), CCR

LDC @ERs +, CCR

LDC @aa:16, CCR

LDC @aa:24, CCR

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 732 of 910

REJ09B0258-0300

Instruction Mnemonic

Instruction

Fetch

Branch

Addr. Read

Stack

Operation

Byte Data

Access

Word Data

Access

Internal

Operation

MOV MOV.B #xx:8, Rd

MOV.B Rs, Rd

MOV.B @ERs, Rd

MOV.B @(d:16, ERs), Rd

MOV.B @(d:24, ERs), Rd

MOV.B @ERs+, Rd

MOV.B @aa:8, Rd

MOV.B @aa:16, Rd

MOV.B @aa:24, Rd

MOV.B Rs, @ERd

MOV.B Rs, @(d:16, ERd)

MOV.B Rs, @(d:24, ERd)

MOV.B Rs, @–ERd

MOV.B Rs, @aa:8

MOV.B Rs, @aa:16

MOV.B Rs, @aa:24

MOV.W #xx:16, Rd

MOV.W Rs, Rd

MOV.W @ERs, Rd

MOV.W @(d:16, ERs), Rd

MOV.W @(d:24, ERs), Rd

MOV.W @ERs+, Rd

MOV.W @aa:16, Rd

MOV.W @aa:24, Rd

MOV.W Rs, @ERd

MOV.W Rs, @(d:16, ERd)

MOV.W Rs, @(d:24, ERd)

MOV.W Rs, @–ERd

MOV.W Rs, @aa:16

MOV.W Rs, @aa:24

MOV.L #xx:32, ERd

MOV.L ERs, ERd

MOV.L @ERs, ERd

MOV.L @(d:16, ERs), ERd

MOV.L @(d:24, ERs), ERd

MOV.L @ERs+, ERd

MOV.L @aa:16, ERd

MOV.L @aa:24, ERd

MOV.L ERs, @ERd

MOV.L ERs, @(d:16, ERd)

MOV.L ERs, @(d:24, ERd)

MOV.L ERs, @–ERd

MOV.L ERs, @aa:16

MOV.L ERs, @aa:24

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 733 of 910

REJ09B0258-0300

Instruction Mnemonic

Instruction

Fetch

Branch

Addr. Read

Stack

Operation

Byte Data

Access

Word Data

Access

Internal

Operation

MOVFPE MOVFPE @aa:16, Rd*221

MOVTPE MOVTPE Rs, @aa:16*221

MULXS MULXS.B Rs, Rd

MULXS.W Rs, ERd 2

212

MULXU MULXU.B Rs, Rd

MULXU.W Rs, ERd 1

112

NEG NEG.B Rd

NEG.W Rd

NEG.L ERd

NOP NOP 1

NOT NOT.B Rd

NOT .W Rd

NOT .L ERd

OR OR.B #xx:8, Rd

OR.B Rs, Rd

OR.W #xx:16, Rd

OR.W Rs, Rd

OR.L #xx:32, ERd

OR.L ERs, ERd

ORC ORC #xx: 8, CCR 1

POP POP.W Rn

POP.L ERn 1

PUSH PUSH.W Rn

PUSH.L ERn 1

ROT L ROTL.B Rd

ROT L.W Rd

ROTL.L ERd

ROT R ROTR.B Rd

ROT R.W Rd

ROTR.L ERd

ROTXL ROTXL.B Rd

ROT XL.W Rd

ROTXL.L ERd

ROTXR ROTXR.B Rd

ROT XR.W Rd

ROT XR.L ERd

RTE RTE 2 2 2

Appendix A Instruction Set

Rev. 3.00 Sep 14, 2005 page 734 of 910

REJ09B0258-0300

Instruction Mnemonic

Instruction

Fetch

Branch

Addr. Read

Stack

Operation

Byte Data

Access

Word Data

Access

Internal

Operation

RTS RTS Normal 2 1 2

Advanced 2 2 2

SHAL SHAL.B Rd

SHAL.W Rd

SHAL.L ERd

SHAR SHAR.B Rd

SHAR.W Rd

SHAR.L ERd

SHLL SHLL.B Rd

SHLL.W Rd

SHLL.L ERd

SHLR SHLR.B Rd

SHLR.W Rd

SHLR.L ERd

SLEEP SLEEP 1

STC STC CCR, Rd

STC CCR, @ERd

ST C CCR, @(d :1 6, ERd )

ST C CCR, @(d :2 4, ERd )

STC CCR, @–ERd

STC CCR, @a a:16

STC CCR, @a a:24

SUB SUB.B Rs, Rd

SUB.W #xx:16, Rd

SUB.W Rs, Rd

SUB.L #xx:32, ERd

SUB.L ERs, ERd

SUBS SUBS #1/2/4, ERd 1

SUBX SUBX #xx:8, Rd

SUBX Rs, Rd 1

TRAPA TRAPA #x:2 Normal 2 1 2 4

Advanced 2 2 2 4

XOR XOR.B #xx:8, Rd

XOR. B Rs, Rd

XOR.W #xx:16, Rd

XOR. W Rs, Rd

XOR.L #xx:32, ERd

XOR.L ERs, ERd

XORC XO RC #xx:8, CCR 1

Notes: 1. n is the value set in regi ster R4L or R4. The source and destination are accessed n + 1

times each.

2. Not available in the H8/3067 Group.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 735 of 910

REJ09B0258-0300

Appendix B Internal I/O R egisters

B.1 Addresses (E MC = 1)

Address

(Low) Register

Name

Data

Bus

Width

Bit Name s

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

H'EE000 P1DDR 8 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1

H'EE001 P2DDR 8 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2

H'EE002 P3DDR 8 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3

H'EE003 P4DDR 8 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4

H'EE004 P5DDR 8 — — — — P53DDR P52DDR P51DDR P50DDR Port 5

H'EE005 P6DDR 8 — P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6

H'EE006— —————— — —

H'EE007 P8DDR 8 — — — P84DDR P83DDR P82DDR P81DDR P80DDR Port 8

H'EE008 P9DDR 8 — — P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Port 9

H'EE009 PADDR 8 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Port A

H'EE00A PBDDR 8 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR P ort B

H'EE00B— —————— — —

H'EE00C— —————— — —

H'EE00D— —————— — —

H'EE00E— —————— — —

H'EE00F— —————— — —

H'EE010— —————— — —

H'EE011 MDCR 8 — — — — — MDS2 MDS1 MDS0 System

H'EE012 SYSCR 8 SSBY STS2 STS1 STS0 UE NMIEG SSOE RAME control

H'EE013 BRCR 8 A23E A22E A21E A20E — — — BRLE Bus controller

H'EE014 ISCR 8 — — IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC

H'EE015 IER 8 — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E

Interrupt

controller

H'EE016 ISR 8 — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F

H'EE017— —————— — —

H'EE018 IPRA 8 IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0

H'EE019 IPRB 8 IPRB7 IPRB6 IPRB5 — IPRB3 IPRB2 IPRB1 —

H'EE01A DASTCR 8 — — — — — — — DASTE D/A converter

H'EE01B DIVCR 8 — — — — — — DIV1 DIV0

H'EE01C MSTCRH 8 PSTOP — — — — MSTPH2 MSTPH1 MSTPH0

System

control

H'EE01D MSTCRL 8 MSTPL7 — MSTPL5 MSTPL4 MSTPL3 MSTPL2 — MSTPL0

H'EE01E ADRCR 8 — — — — — — — A DRCTL Bus controller

H'EE01F CSCR 8 CS7E CS6E CS5E CS4E — — — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 736 of 910

REJ09B0258-0300

Address

(Low) Register

Name

Data

Bus

Width

Bit Name s

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

H'EE020 ABWCR 8 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0

H'EE021 ASTCR 8 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0

Bus controller

H'EE022 WCRH 8 W71 W70 W61 W60 W51 W50 W41 W40

H'EE023 WCRL 8 W31 W30 W21 W20 W11 W10 W01 W00

H'EE024 BCR 8 ICIS1 ICIS0 BROME BRSTS1 BRSTS0 — RDEA WAITE

H'EE025— —————— — —

H'EE026 DRCRA 8 DRAS2 DRAS1 DRAS0 — BE RDM SRFMD RFSHE

H'EE027 DRCRB 8 MXC1 MXC0 CSEL RCYCE — TPC RCW RLW

DRAM

Interface

H'EE028 RTMCSR 8 CMF CMIE CKS2 CKS1 CKS0 — — —

H'EE029 RTCNT 8

H'EE02A RTCOR 8

H'EE02B Reserved area (access prohibited)

H'EE02C

H'EE02D

H'EE02E

H'EE02F

H'EE030 FLMCR1 8 FWE SWE ESU PSU EV PV E P

H'EE031 FLMCR2 8 FLER — — — — — — —

Flash

memory

H'EE032 EBR1 8 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

H'EE033 EBR2 8 — — EB13 EB12 EB11 EB10 EB9 EB8

H'EE034 Reserved area (access prohibited)

H'EE035

H'EE036

H'EE037

H'EE038

H'EE039

H'EE03A

H'EE03B

H'EE03C P2PCR 8 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P27PCR P20PCR Port 2

H'EE03D— —————— — —

H'EE03E P4PCR 8 P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR Port 4

H'EE03F P5PCR 8 — — — — P53PCR P52PCR P51PCR P50PCR Po rt 5

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 737 of 910

REJ09B0258-0300

Address

(Low) Register

Name

Data

Bus

Width

Bit Name s

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

H'EE040— —————— — —

H'EE041— —————— — —

H'EE042— —————— — —

H'EE043— —————— — —

H'EE044— —————— — —

H'EE045— —————— — —

H'EE046— —————— — —

H'EE047— —————— — —

H'EE048— —————— — —

H'EE049— —————— — —

H'EE04A— —————— — —

H'EE04B— —————— — —

H'EE04C— —————— — —

H'EE04D— —————— — —

H'EE04E— —————— — —

H'EE04F— —————— — —

H'EE050— —————— — —

H'EE051— —————— — —

H'EE052— —————— — —

H'EE053— —————— — —

H'EE054— —————— — —

H'EE055— —————— — —

H'EE056— —————— — —

H'EE057— —————— — —

H'EE058— —————— — —

H'EE059— —————— — —

H'EE05A— —————— — —

H'EE05B— —————— — —

H'EE05C— —————— — —

H'EE05D— —————— — —

H'EE05E— —————— — —

H'EE05F— —————— — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 738 of 910

REJ09B0258-0300

Address

(Low) Register

Name

Data

Bus

Width

Bit Name s

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

H'EE060— —————— — —

H'EE061— —————— — —

H'EE062— —————— — —

H'EE063— —————— — —

H'EE064— —————— — —

H'EE065— —————— — —

H'EE066— —————— — —

H'EE067— —————— — —

H'EE068— —————— — —

H'EE069— —————— — —

H'EE06A— —————— — —

H'EE06B— —————— — —

H'EE06C— —————— — —

H'EE06D— —————— — —

H'EE06E— —————— — —

H'EE06F— —————— — —

H'EE070— —————— — —

H'EE071— —————— — —

H'EE072— —————— — —

H'EE073— —————— — —

H'EE074 Reserved area (access prohibited)

H'EE075

H'EE076

H'EE077 RAMCR

*18 — — — — RAMS RAM2 RAM1 RAM0 Flash

memory*1

H'EE078 Reserved area (access prohibited)

H'EE079

H'EE07A

H'EE07B

H'EE07C

H'EE07D

H'EE07E

H'EE07F

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 739 of 910

REJ09B0258-0300

Address

(Low) Register

Name

Data

Bus

Width

Bit Name s

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

H'EE080 Reserved area (access prohibited) Flash memory*1

H'EE081

H'FFF20 MAR0AR 8 DMAC channel 0A

H'FFF21 MAR0AE 8

H'FFF22 MAR0AH 8

H'FFF23 MAR0AL 8

H'FFF24 ETCR0AH 8

H'FFF25 ETCR0AL 8

H'FFF26 IOAR0A 8

H'FFF27 DTCR0A 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode

DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Full address mode

H'FFF28 MAR0BR 8 DMAC channel 0B

H'FFF29 MAR0BE 8

H'FFF2A MAR0BH 8

H'FFF2B MAR0BL 8

H'FFF2C ETCR0BH 8

H'FFF2D ETCR0BL 8

H'FFF2E IOAR0B 8

H'FFF2F DTCR0B 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode

DTME — DAID DAIDE TMS DTS2B DTS1B DTS0B Full address m ode

H'FFF30 MAR1AR 8 DMAC channel 1A

H'FFF31 MAR1AE 8

H'FFF32 MAR1AH 8

H'FFF33 MAR1AL 8

H'FFF34 ETCR1AH 8

H'FFF35 ETCR1AL 8

H'FFF36 IOAR1A 8

H'FFF37 DTCR1A 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode

DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Full address mode

H'FFF38 MAR1BR 8 DMAC channel 1B

H'FFF39 MAR1BE 8

H'FFF3A MAR1BH 8

H'FFF3B MAR1BL 8

H'FFF3C ETCR1BH 8

H'FFF3D ETCR1BL 8

H'FFF3E IOAR1B 8

H'FFF3F DTCR1B 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode

DTME — DAID DAIDE TMS DTS2B DTS1B DTS0B Full address m ode

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 740 of 910

REJ09B0258-0300

Address

(Low) Register

Name

Data

Bus

Width

Bit Name s

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

H'FFF40 — — — — — — — — —

H'FFF41 — — — — — — — — —

H'FFF42 — — — — — — — — —

H'FFF43 — — — — — — — — —

H'FFF44 — — — — — — — — —

H'FFF45 — — — — — — — — —

H'FFF46 — — — — — — — — —

H'FFF47 — — — — — — — — —

H'FFF48 — — — — — — — — —

H'FFF49 — — — — — — — — —

H'FFF4A — — — — — — — — —

H'FFF4B — — — — — — — — —

H'FFF4C — — — — — — — — —

H'FFF4D — — — — — — — — —

H'FFF4E — — — — — — — — —

H'FFF4F — — — — — — — — —

H'FFF50 — — — — — — — — —

H'FFF51 — — — — — — — — —

H'FFF52 — — — — — — — — —

H'FFF53 — — — — — — — — —

H'FFF54 — — — — — — — — —

H'FFF55 — — — — — — — — —

H'FFF56 — — — — — — — — —

H'FFF57 — — — — — — — — —

H'FFF58 — — — — — — — — —

H'FFF59 — — — — — — — — —

H'FFF5A — — — — — — — — —

H'FFF5B — — — — — — — — —

H'FFF5C — — — — — — — — —

H'FFF5D — — — — — — — — —

H'FFF5E — — — — — — — — —

H'FFF5F — — — — — — — — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 741 of 910

REJ09B0258-0300

Address

(Low) Register

Name

Data

Bus

Width

Bit Name s

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

H'FFF60 TSTR 8 — — — — — STR2 STR1 STR0

H'FFF61 TSNC 8 — — — — — SYNC2 SYNC1 SYNC0

16-bit timer,

(all channels)

H'FFF62 TMDR 8 — MDF FDIR — — PWM2 PWM1 PWM0

H'FFF63 TOLR 8 — — TOB2 TOA2 TOB1 TOA1 TOB0 TOA0

H'FFF64 TISRA 8 — IMIEA2 IMIEA1 IMIEA0 — IMFA2 IMFA1 IMFA0

H'FFF65 TISRB 8 — IMIEB2 IMIEB1 IMIEB0 — IMFB2 IMFB1 IMFB0

H'FFF66 TISRC 8 — OVIE2 OVIE1 OVIE0 — OVF2 OVF1 OVF0

H'FFF67

H'FFF68 TCR0 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

H'FFF69 TIOR0 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0

16-bit timer

channel 0

H'FFF6A TCNT0H 16

H'FFF6B TCNT0L

H'FFF6C GRA0H 16

H'FFF6D GRA0L

H'FFF6E GRB0H 16

H'FFF6F GRB0L

H'FFF70 TCR1 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

H'FFF71 TIOR1 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0

16-bit timer

channel 1

H'FFF72 TCNT1H 16

H'FFF73 TCNT1L

H'FFF74 GRA1H 16

H'FFF75 GRA1L

H'FFF76 GRB1H 16

H'FFF77 GRB1L

H'FFF78 TCR2 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

H'FFF79 TIOR2 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0

16-bit timer

channel 2

H'FFF7A TCNT2H 16

H'FFF7B TCNT2L

H'FFF7C GRA2H 16

H'FFF7D GRA2L

H'FFF7E GRB2H 16

H'FFF7F GRB2L

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 742 of 910

REJ09B0258-0300

Address

(Low) Register

Name

Data

Bus

Width

Bit Name s

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

H'FFF80 TCR0 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

H'FFF81 TCR1 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

H'FFF82 TCSR0 8 CMFB CMFA OVF ADTE OIS3 OIS2 OS1 OS0

8-bit timer

channels 0

and 1

H'FFF83 TCSR1 8 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0

H'FFF84 TCORA0 8

H'FFF85 TCORA1 8

H'FFF86 TCORB0 8

H'FFF87 TCORB1 8

H'FFF88 TCNT0 8

H'FFF89 TCNT1 8

H'FFF8A — — — — — — — — —

H'FFF8B — — — — — — — — —

H'FFF8C TCSR*28OVFWT/

TME — — CKS2 CKS1 CKS0 WDT

H'FFF8D TCNT*28

H'FFF8E — — — — — — — — —

H'FFF8F RSTCSR

*28WRSTRSTOE———— — —

H'FFF90 TCR2 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

H'FFF91 TCR3 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

H'FFF92 TCSR2 8 CMFB CMFA OVF — OIS3 OIS2 OS1 OS0

8-bit timer

channels 2

and 3

H'FFF93 TCSR3 8 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0

H'FFF94 TCORA2 8

H'FFF95 TCORA3 8

H'FFF96 TCORB2 8

H'FFF97 TCORB3 8

H'FFF98 TCNT2 8

H'FFF99 TCNT3 8

H'FFF9A — — — — — — — — —

H'FFF9B — — — — — — — — —

H'FFF9C DADR0 8 D/A converter

H'FFF9D DADR1 8

H'FFF9E DACR 8 DAOE1 DAOE0 DAE — — — — —

H'FFF9F — 8 — — — — — — — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 743 of 910

REJ09B0258-0300

Address

(Low) Register

Name

Data

Bus

Width

Bit Name s

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

H'FFFA0 TPMR 8 ————G3NOVG2NOVG1NOVG0NOVTPC

H'FFFA1 TPCR 8 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0

H'FFFA2 NDERB 8 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8

H'FFFA3 NDERA 8 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0

H'FFFA4 NDRB*38 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8

NDER15 NDER14 NDER13 NDER12 — — — —

H'FFFA5 NDRA*38 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0

NDER7 NDER6 NDER5 NDER4 — — — —

H'FFFA6 NDRB*38————————

————NDER11NDER10NDER9NDER8

H'FFFA7 NDRA*38————————

————NDER3NDER2NDER1NDER0

H'FFFA8

H'FFFA9

H'FFFAA

H'FFFAB

H'FFFAC

H'FFFAD

H'FFFAE

H'FFFAF

H'FFFB0 SMR 8 C/

CHR PE O/

STOP MP CKS1 CKS0

H'FFFB1 BRR 8 SCI

channel 0

H'FFFB2 SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FFFB3 TDR 8

H'FFFB4 SSR 8 TDRE RDRF ORER FER/ERS PER TEND MPB MPBT

H'FFFB5 RDR 8

H'FFFB6 SCMR 8 ————SDIRSINV—SMIF

H'FFFB7 Reserved area (access prohibited)

H'FFFB8 SMR 8 C/

CHR PE O/

STOP MP CKS1 CKS0

H'FFFB9 BRR 8 SCI

channel 1

H'FFFBA SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FFFBB TDR 8

H'FFFBC SSR 8 TDRE RDRF ORER FER/ERS PER TEND MPB MPBT

H'FFFBD RDR 8

H'FFFBE SCMR 8 ————SDIRSINV—SMIF

H'FFFBF Reserved area (access prohibited)

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 744 of 910

REJ09B0258-0300

Address

(Low) Register

Name

Data

Bus

Width

Bit Name s

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

H'FFFC0 SMR 8 C/

CHR PE O/

STOP MP CKS1 CKS0

H'FFFC1 BRR 8

SCI

channel 2

H'FFFC2 SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FFFC3 TDR 8

H'FFFC4 SSR 8 TDRE RDRF ORER FER/ERS PER TEND MPB MPBT

H'FFFC5 RDR 8

H'FFFC6 SCMR 8 — — — — SDIR SINV — SMIF

H'FFFC7 Reserved area (access prohibited)

H'FFFC8 — — — — — — — — —

H'FFFC9 — — — — — — — — —

H'FFFCA — — — — — — — — —

H'FFFCB — — — — — — — — —

H'FFFCC — — — — — — — — —

H'FFFCD — — — — — — — — —

H'FFFCE — — — — — — — — —

H'FFFCF — — — — — — — — —

H'FFFD0 P1DR 8 P17P16P15P14P13P12P11P10Port1

H'FFFD1 P2DR 8 P27P26P25P24P23P22P21P20Port2

H'FFFD2 P3DR 8 P37P36P35P34P33P32P31P30Port3

H'FFFD3 P4DR 8 P47P46P45P44P43P42P41P40Port4

H'FFFD4 P5DR 8 — — — — P53P52P51P50Port5

H'FFFD5 P6DR 8 P67P66P65P64P63P62P61P60Port6

H'FFFD6 P7DR 8 P77P76P75P74P73P72P71P70Port7

H'FFFD7 P8DR 8 — — — P84P83P82P81P80Port8

H'FFFD8 P9DR 8 — — P95P94P93P92P91P90Port9

H'FFFD9 PADR 8 PA7PA6PA5PA4PA3PA2PA1PA0PortA

H'FFFDA PBDR 8 PB7PB6PB5PB4PB3PB2PB1PB0PortB

H'FFFDB — — — — — — — — —

H'FFFDC — — — — — — — — —

H'FFFDD — — — — — — — — —

H'FFFDE — — — — — — — — —

H'FFFDF — — — — — — — — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 745 of 910

REJ09B0258-0300

Address

(Low) Register

Name

Data

Bus

Width

Bit Name s

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Name

H'FFFE0 ADDRAH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

H'FFFE1 ADDRAL 8 AD1 AD0 — — — — — —

A/D converter

H'FFFE2 ADDRBH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

H'FFFE3 ADDRBL 8 AD1 AD0 — — — — — —

H'FFFE4 ADDRCH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

H'FFFE5 ADDRCL 8 AD1 AD0 — — — — — —

H'FFFE6 ADDRDH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

H'FFFE7 ADDRDL 8 AD1 AD0 — — — — — —

H'FFFE8 ADCSR 8 ADF ADIE ADST SCAN CKS CH2 CH1 CH0

H'FFFE9 ADCR 8 TRGE — — — — — — —

Notes: 1. The RAMCR and FLMCR registers are used only in the flash memory and flash

me mory R versions, and are not provided in the mask ROM versions.

2. For write access to TCSR, TCNT, and RSTCSR, see section 12.2.4, Notes on Register

Access.

3. The address depends on the output trigger setting.

Legend

WDT: Watchdog timer

TPC: Programmable timing pattern controller

SCI: Serial communication i nterface

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 746 of 910

REJ09B0258-0300

B.2 Addresses (E MC = 0)

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'EE000 P1DDR 8 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Por t 1

H'EE001 P2DDR 8 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Por t 2

H'EE002 P3DDR 8 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Por t 3

H'EE003 P4DDR 8 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Por t 4

H'EE004 P5DDR 8 — — — — P53DDR P52DDR P51DDR P50DDR Port 5

H'EE005 P6DDR 8 — P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Por t 6

H'EE006— ——————— — —

H'EE007 P8DDR 8 — — — P84DDR P83DDR P82DDR P81DDR P80DDR Port 8

H'EE008 P9DDR 8 — — P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Po r t 9

H'EE009 PADDR 8 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR P ort A

H'EE00A PBDDR 8 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR P ort B

H'EE00B— —————— — —

H'EE00C— —————— — —

H'EE00D— —————— — —

H'EE00E— —————— — —

H'EE00F— —————— — —

H'EE010— —————— — —

H'EE011 MDCR 8 — — — — — MDS2 MDS1 MDS0

H'EE012 SYSCR 8 SSBY STS2 STS1 STS0 UE NMIEG SSOE RAME

System

control

H'EE013 BRCR 8 A23E A22E A21E A20E — — — BRLE Bus

controller

H'EE014 ISCR 8 — — IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC

H'EE015 IER 8 — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E

Interrupt

controller

H'EE016 ISR 8 — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F

H'EE017— 8—————— — —

H'EE018 IPRA 8 IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0

H'EE019 IPRB 8 IPRB7 IPRB6 IPRB5 — IPRB3 IPRB2 IPRB1 —

H'EE01A DASTCR 8 — — — — — — — DASTE D/A

converter

H'EE01B DIVCR 8 — — — — — — DIV1 DIV0

H'EE01C MSTCRH 8 PSTOP — — — — MSTPH2 MSTPH1 MSTPH0

System

control

H'EE01D MSTCRL 8 MSTPL7 — MSTPL5 MSTPL4 MSTPL3 MSTPL2 — MSTPL0

H'EE01E ADRCR 8 — — — — — — — ADRCTL Bus

controller

H'EE01F CSCR 8 CS7E CS6E CS5E CS4E — — — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 747 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'EE020 ABWCR 8 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0

H'EE021 ASTCR 8 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0

Bus

controller

H'EE022 WCRH 8 W71 W70 W61 W60 W51 W50 W41 W40

H'EE023 WCRL 8 W31 W30 W21 W20 W11 W10 W01 W00

H'EE024 BCR 8 ICIS1 ICIS0 BROME BRSTS1 BRSTS0 EMC RDEA WAITE

H'EE025 (FLWCR) — — — — — — — —

H'EE026 DRCRA 8 DRAS2 DRAS1 DRAS0 — BE RDM SRFMD RFSHE

H'EE027 DRCRB 8 MXC1 MXC0 CSEL RCYCE — TPC RCW RLW

DRAM

interface

H'EE028 RTMCSR 8 CMF CMIE CKS2 CKS1 CKS0 — — —

H'EE029 RTCNT 8

H'EE02A RTCOR 8

H'EE02B — 8

H'EE02C DCR0 8

Bus

controller

H'EE02D DCR1 8

H'EE02E DCR2 8

H'EE02F DCR3 8

H'EE030 FLMCR1 8 FWE SWE ESU PSU EV PV E P

H'EE031 FLMCR2 8 FLER

Flash

memory

H'EE032 EBR1 8 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

H'EE033 EBR2 8 — — EB13 EB12 EB11 EB10 EB9 EB8

H'EE034 Reserved area (access prohibited)

H'EE035

H'EE036

H'EE037

H'EE03C P2PCR 8 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P27PCR P20PCR Port 2

H'EE03D— 8—————— — —

H'EE03E P4PCR 8 P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR Port 4

H'EE03F P5PCR 8 — — — — P53PCR P52PCR P51PCR P50PCR Port 5

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 748 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'EE040— —————— — —

H'EE041— —————— — —

H'EE042— —————— — —

H'EE043— —————— — —

H'EE044— —————— — —

H'EE045— —————— — —

H'EE046— —————— — —

H'EE047— —————— — —

H'EE048— —————— — —

H'EE049— —————— — —

H'EE04A— —————— — —

H'EE04B— —————— — —

H'EE04C— —————— — —

H'EE04D— —————— — —

H'EE04E— —————— — —

H'EE04F— —————— — —

H'EE050— —————— — —

H'EE051— —————— — —

H'EE052— —————— — —

H'EE053— —————— — —

H'EE054— —————— — —

H'EE055— —————— — —

H'EE056— —————— — —

H'EE057— —————— — —

H'EE058— —————— — —

H'EE059— —————— — —

H'EE05A— —————— — —

H'EE05B— —————— — —

H'EE05C— —————— — —

H'EE05D— —————— — —

H'EE05E— —————— — —

H'EE05F— —————— — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 749 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'EE060— —————— — —

H'EE061— —————— — —

H'EE062— —————— — —

H'EE063— —————— — —

H'EE064— —————— — —

H'EE065— —————— — —

H'EE066— —————— — —

H'EE067— —————— — —

H'EE068— —————— — —

H'EE069— —————— — —

H'EE06A— —————— — —

H'EE06B— —————— — —

H'EE06C— —————— — —

H'EE06D— —————— — —

H'EE06E— —————— — —

H'EE06F— —————— — —

H'EE070 Reserved area (access prohibited)

H'EE071

H'EE072

H'EE073

H'EE074

H'EE075

H'EE076

H'EE077 RAMCR

*18 — — — — RAMS RAM2 RAM1 RAM0

H'EE078 Reserved area (access prohibited)

Flash

memory*1

H'EE079

H'EE07A

H'EE07B

H'EE07C

H'EE07D

H'EE07E

H'EE07F

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 750 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'EE090 TCSR*28OVFWT/

TME — — CKS2 CKS1 CKS0 WDT

H'EE091 TCNT*28

H'EE092— —————— — —

H'EE093 RSTCSR*28WRST————— — —

H'EE094 Reserved area (access prohibited)

H'EE095

H'EE096

H'EE097

H'EE098

H'EE099

H'EE09A

H'EE09B

H'EE09C

H'EE09D

H'EE09E

H'EE09F

H'EE0A0

H'EE0A1

H'EE0A2

H'EE0A3

H'EE0A4

H'EE0A5

H'EE0A6

H'EE0A7

H'EE0A8

H'EE0A9

H'EE0AA

H'EE0AB

H'EE0AC

H'EE0AD

H'EE0AE

H'EE0AF

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 751 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'EE0B0 Reserved area (access prohibited)

H'EE0B1

H'EE0B2

H'EE0B3

H'EE0B4

H'EE0B5

H'EE0B6

H'EE0B7

H'EE0B8

H'EE0B9

H'EE0BA

H'EE0BB

H'EE0BC

H'EE0BD

H'EE0BE

H'EE0BF

H'EE0C0

H'EE0C1

H'EE0C2

H'EE0C3

H'EE0C4

H'EE0C5

H'EE0C6

H'EE0C7

H'EE0C8

H'EE0C9

H'EE0CA

H'EE0CB

H'EE0CC

H'EE0CD

H'EE0CE

H'EE0CF

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 752 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'EE0D0 Reserved area (access prohibited)

H'EE0D1

H'EE0D2

H'EE0D3

H'EE0D4

H'EE0D5

H'EE0D6

H'EE0D7

H'EE0D8

H'EE0D9

H'EE0DA

H'EE0DB

H'EE0DC

H'EE0DD

H'EE0DE

H'EE0DF

H'EE0E0

H'EE0E1

H'EE0E2

H'EE0E3

H'EE0E4

H'EE0E5

H'EE0E6

H'EE0E7

H'EE0E8

H'EE0E9

H'EE0EA

H'EE0EB

H'EE0EC

H'EE0ED

H'EE0EE

H'EE0EF

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 753 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'EE0F0 Reserved area (access prohibited)

H'EE0F1

H'EE0F2

H'EE0F3

H'EE0F4

H'EE0F5

H'EE0F6

H'EE0F7

H'EE0F8

H'EE0F9

H'EE0FA

H'EE0FB

H'EE0FC

H'EE0FD

H'EE0FE

H'EE0FF

H'FFE00— —————— — —

H'FFE01— —————— — —

H'FFE02— —————— — —

H'FFE03— —————— — —

H'FFE04— —————— — —

H'FFE05— —————— — —

H'FFE06— —————— — —

H'FFE07— —————— — —

H'FFE08— —————— — —

H'FFE09— —————— — —

H'FFE0A— —————— — —

H'FFE0B— —————— — —

H'FFE0C— —————— — —

H'FFE0D— —————— — —

H'FFE0E— —————— — —

H'FFE0F— —————— — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 754 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'FFE10— —————— — —

H'FFE11— —————— — —

H'FFE12— —————— — —

H'FFE13— —————— — —

H'FFE14— —————— — —

H'FFE15— —————— — —

H'FFE16— —————— — —

H'FFE17— —————— — —

H'FFE18— —————— — —

H'FFE19— —————— — —

H'FFE1A— —————— — —

H'FFE1B— —————— — —

H'FFE1C— —————— — —

H'FFE1D— —————— — —

H'FFE1E— —————— — —

H'FFE1F— —————— — —

H'FFE20— —————— — —

H'FFE21— —————— — —

H'FFE22— —————— — —

H'FFE23— —————— — —

H'FFE24— —————— — —

H'FFE25— —————— — —

H'FFE26— —————— — —

H'FFE27— —————— — —

H'FFE28— —————— — —

H'FFE29— —————— — —

H'FFE2A— —————— — —

H'FFE2B— —————— — —

H'FFE2C— —————— — —

H'FFE2D— —————— — —

H'FFE2E— —————— — —

H'FFE2F— —————— — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 755 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'FFE30— —————— — —

H'FFE31— —————— — —

H'FFE32— —————— — —

H'FFE33— —————— — —

H'FFE34— —————— — —

H'FFE35— —————— — —

H'FFE36— —————— — —

H'FFE37— —————— — —

H'FFE38— —————— — —

H'FFE39— —————— — —

H'FFE3A— —————— — —

H'FFE3B— —————— — —

H'FFE3C— —————— — —

H'FFE3D— —————— — —

H'FFE3E— —————— — —

H'FFE3F— —————— — —

H'FFE40— —————— — —

H'FFE41— —————— — —

H'FFE42— —————— — —

H'FFE43— —————— — —

H'FFE44— —————— — —

H'FFE45— —————— — —

H'FFE46— —————— — —

H'FFE47— —————— — —

H'FFE48— —————— — —

H'FFE49— —————— — —

H'FFE4A— —————— — —

H'FFE4B— —————— — —

H'FFE4C— —————— — —

H'FFE4D— —————— — —

H'FFE4E— —————— — —

H'FFE4F— —————— — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 756 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'FFE50— —————— — —

H'FFE51— —————— — —

H'FFE52— —————— — —

H'FFE53— —————— — —

H'FFE54— —————— — —

H'FFE55— —————— — —

H'FFE56— —————— — —

H'FFE57— —————— — —

H'FFE58— —————— — —

H'FFE59— —————— — —

H'FFE5A— —————— — —

H'FFE5B— —————— — —

H'FFE5C— —————— — —

H'FFE5D— —————— — —

H'FFE5E— —————— — —

H'FFE5F— —————— — —

H'FFE60— —————— — —

H'FFE61— —————— — —

H'FFE62— —————— — —

H'FFE63— —————— — —

H'FFE64— —————— — —

H'FFE65— —————— — —

H'FFE66— —————— — —

H'FFE67— —————— — —

H'FFE68— —————— — —

H'FFE69— —————— — —

H'FFE6A— —————— — —

H'FFE6B— —————— — —

H'FFE6C— —————— — —

H'FFE6D— —————— — —

H'FFE6E— —————— — —

H'FFE6F— —————— — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 757 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'FFE70— —————— — —

H'FFE71— —————— — —

H'FFE72— —————— — —

H'FFE73— —————— — —

H'FFE74— —————— — —

H'FFE75— —————— — —

H'FFE76— —————— — —

H'FFE77— —————— — —

H'FFE78— —————— — —

H'FFE79— —————— — —

H'FFE7A— —————— — —

H'FFE7B— —————— — —

H'FFE7C— —————— — —

H'FFE7D— —————— — —

H'FFE7E— —————— — —

H'FFE7F— —————— — —

H'FFE80 MAR0AR 8

H'FFE81 MAR0AE 8

DMAC

channel 0A

H'FFE82 MAR0AH 8

H'FFE83 MAR0AL 8

H'FFE84 ETCR0AH 8

H'FFE85 ETCR0AL 8

H'FFE86 IOAR0A 8

H'FFE87 DTCR0A 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short

address

mode

DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Full address

mode

H'FFE88 MAR0BR 8

H'FFE89 MAR0BE 8

DMAC

channel 0B

H'FFE8A MAR0BH 8

H'FFE8B MAR0BL 8

H'FFE8C ETCR0BH 8

H'FFE8D ETCR0BL 8

H'FFE8E IOAR0B 8

H'FFE8F DTCR0B 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short

address

mode

DTME — DAID DAIDE TMS DTS2B DTS1B DTS0B Full address

mode

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 758 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'FFE90 MAR1AR 8 DMAC

channel 1A

H'FFE91 MAR1AE 8

H'FFE92 MAR1AH 8

H'FFE93 MAR1AL 8

H'FFE94 ETCR1AH 8

H'FFE95 ETCR1AL 8

H'FFE96 IOAR1A 8

H'FFE97 DTCR1A 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short

address

mode

DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Full address

mode

H'FFE98 MAR1BR 8 DMAC

H'FFE99 MAR1BE 8 channel 1B

H'FFE9A MAR1BH 8

H'FFE9B MAR1BL 8

H'FFE9C ETCR1BH 8

H'FFE9D ETCR1BL 8

H'FFE9E IOAR1B 8

H'FFE9F DTCR1B 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short

address

mode

DTME — DAID DAIDE TMS DTS2B DTS1B DTS0B Full address

mode

H'FFEA0 TSTR 8 — — — — — STR2 STR1 STR0

H'FFEA1 TSNC 8 — — — — — SYNC2 SYNC1 SYNC0

16-bit timer,

(all channels)

H'FFEA2 TMDR 8 — MDF FDIR — — PWM2 PWM1 PWM0

H'FFEA3 TOLR 8 — — TOB2 TOA2 TOB1 TOA1 TOB0 TOA0

H'FFEA4 TISRA 8 — IMIEA2 IMIEA1 IMIEA0 — IMFA2 IMFA1 IMFA0

H'FFEA5 TISRB 8 — IMIEB2 IMIEB1 IMIEB0 — IMFB2 IMFB1 IMFB0

H'FFEA6 TISRC 8 — OVIE2 OVIE1 OVIE0 — OVF2 OVF1 OVF0

H'FFEA7 —

H'FFEA8 16TCR0 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

H'FFEA9 TIOR0 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0

16-bit timer

channel 0

H'FFEAA 16TCNT0H 16

H'FFEAB 16TCNT0L

H'FFEAC GRA0H 16

H'FFEAD GRA0L

H'FFEAE GRB0H 16

H'FFEAF GRB0L

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 759 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'FFEB0 16TCR1 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

H'FFEB1 TIOR1 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0

16-bit timer

channel 1

H'FFEB2 16TCNT1H 16

H'FFEB3 16TCNT1L

H'FFEB4 GRA1H 16

H'FFEB5 GRA1L

H'FFEB6 GRB1H 16

H'FFEB7 GRB1L

H'FFEB8 16TCR2 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

H'FFEB9 TIOR2 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0

16-bit timer

channel 2

H'FFEBA 16TCNT2H 16

H'FFEBB 16TCNT2L

H'FFEBC GRA2H 16

H'FFEBD GRA2L

H'FFEBE GRB2H 16

H'FFEBF GRB2L

H'FFEC0 8TCR0 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

H'FFEC1 8TCR1 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

H'FFEC2 8TCSR0 8 CMFB CMFA OVF ADTE OIS3 OIS2 OS1 OS0

8-bit timer

channels 0

and 1

H'FFEC3 8TCSR1 8 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0

H'FFEC4 TCORA0 8

H'FFEC5 TCORA1 8

H'FFEC6 TCORB0 8

H'FFEC7 TCORB1 8

H'FFEC8 8TCNT0 8

H'FFEC9 8TCNT1 8

H'FFECA Reserved area (access prohibited)

H'FFECB

H'FFECC

H'FFECD

H'FFECE

H'FFECF

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 760 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'FFED0 8TCR2 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

H'FFED1 8TCR3 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

H'FFED2 8TCSR2 8 CMFB CMFA OVF — OIS3 OIS2 OS1 OS0

8-bit timer

channels 2

and 3

H'FFED3 8TCSR3 8 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0

H'FFED4 TCORA2 8

H'FFED5 TCORA3 8

H'FFED6 TCORB2 8

H'FFED7 TCORB3 8

H'FFED8 8TCNT2 8

H'FFED9 8TCNT3 8

H'FFEDA Reserved area (access prohibited)

H'FFEDB

H'FFEDC

H'FFEDD

H'FFEDE

H'FFEDF

H'FFEE0 SMR 8 C/

CHR PE O/

STOP MP CKS1 CKS0

H'FFEE1 BRR 8

SCI

channel 0

H'FFEE2 SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FFEE3 TDR 8

H'FFEE4 SSR 8 TDRE RDRF ORER FER/

ERS PER TEND MPB MPBT

H'FFEE5 RDR 8

H'FFEE6 SCMR 8 — — — — SDIR SINV — SMIF

H'FFEE7— —————— — —

H'FFEE8 SMR 8 C/

CHR PE O/

STOP MP CKS1 CKS0

H'FFEE9 BRR 8

SCI

channel 1

H'FFEEA SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FFEEB TDR 8

H'FFEEC SSR 8 TDRE RDRF ORER FER/

ERS PER TEND MPB MPBT

H'FFEED RDR 8

H'FFEEE SCMR 8 — — — — SDIR SINV — SMIF

H'FFEEF— —————— — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 761 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'FFEF0 SMR 8 C/

CHR PE O/

STOP MP CKS1 CKS0

H'FFEF1 BRR 8

SCI

channel 2

H'FFEF2 SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FFEF3 TDR 8

H'FFEF4 SSR 8 TDRE RDRF ORER FER/

ERS PER TEND MPB MPBT

H'FFEF5 RDR 8

H'FFEF6 SCMR 8 — — — — SDIR SINV — SMIF

H'FFEF7 — — — — — — — — —

H'FFEF8 TPMR 8 — — — — G3NOV G2NOV G1NOV G0NOV

H'FFEF9 TPCR 8 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0

H'FFEFA NDERB 8 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8

H'FFEFB NDERA 8 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0

H'FFEFC NDRB*38 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8

NDR15 NDR14 NDR13 NDR12 — — — —

H'FFEFD NDRA*38 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0

NDR7 NDR6 NDR5 NDR4 — — — —

H'FFEFE NDRB*38—————— — —

— — — — NDR11 NDR10 NDR9 NDR8

H'FFEFF NDRA*38—————— — —

— — — — NDR3 NDR2 NDR1 NDR0

H'FFFE0 ADDRAH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

H'FFFE1 ADDRAL 8 AD1 AD0 — — — — — —

A/D

converter

H'FFFE2 ADDRBH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

H'FFFE3 ADDRBL 8 AD1 AD0 — — — — — —

H'FFFE4 ADDRCH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

H'FFFE5 ADDRCL 8 AD1 AD0 — — — — — —

H'FFFE6 ADDRDH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

H'FFFE7 ADDRDL 8 AD1 AD0 — — — — — —

H'FFFE8 ADCSR 8 ADF ADIE ADST SCAN CKS CH2 CH1 CH0

H'FFFE9 ADCR 8 TRGE — — — — — — —

H'FFFEA Reserved area (access prohibited)

H'FFFEB

H'FFFEC DADR0 8

H'FFFED DADR1 8

D/A

converter

H'FFFEE DACR 8 — — — — — — — —

H'FFFEF — 8 — — — — — — — —

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 762 of 910

REJ09B0258-0300

Address Register Data

Bus Bit Nam es Module

(Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name

H'FFFF0 P1DR 8 P17P16P15P14P13P12P11P10Port1

H'FFFF1 P2DR 8 P27P26P25P24P23P22P21P20Port2

H'FFFF2 P3DR 8 P37P36P35P34P33P32P31P30Port3

H'FFFF3 P4DR 8 P47P46P45P44P43P42P41P40Port4

H'FFFF4 P5DR 8 — — — — P53P52P51P50Port5

H'FFFF5 P6DR 8 P67P66P65P64P63P62P61P60Port6

H'FFFF6 P7DR 8 P77P76P75P74P73P72P71P70Port7

H'FFFF7 P8DR 8 — — — P84P83P82P81P80Port8

H'FFFF8 P9DR 8 — — P95P94P93P92P91P90Port9

H'FFFF9 PADR 8 PA7PA6PA5PA4PA3PA2PA1PA0PortA

H'FFFFA PBDR 8 PB7PB6PB5PB4PB3PB2PB1PB0PortB

H'FFFFB — — — — — — — — —

H'FFFFC — — — — — — — — —

H'FFFFD — — — — — — — — —

H'FFFFE — — — — — — — — —

H'FFFFF — — — — — — — — —

Notes: 1. The RAMCR and FLMCR registers are used only in the flash memory and flash

me mory R versions, and are not provided in the mask ROM versions.

2. For write access to TCSR, TCNT, and RSTCSR, see section 12.2.4, Notes on Register

Access.

3. The address depends on the output trigger setting.

Legend

WDT: Watchdog timer

TPC: Programmable timing pattern controller

SCI: Serial communication i nterface

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 763 of 910

REJ09B0258-0300

B.3 Functions

Bit

Initial value

R/W: 0

R/W

ICIAE

R/W

ICIBE

R/W

ICICE

R/W

OCIDE

R/W

OCIAE

R/W

OCIBE

R/W

OVIE

Timer overflow interrupt enable

Interrupt requested by OVF flag is disabled

Interrupt requested by OVF flag is enabled

Output compare interrupt B enable

Interrupt requested by OCFB flag is disabled

Interrupt requested by OCFB flag is enabled

Output compare interrupt A enable

Interrupt requested by OCFA flag is disabled

Interrupt requested by OCFA flag is enabled

Input capture interrupt D enable

Interrupt requested by ICFD flag is disabled

Interrupt requested by ICFD flag is enabled

TIER—Timer Interrupt Enable Register H' 90 FRT

Address to which register

is mapped*Name of on-chip

supporting module

Names of the bits.

Dashes (—) indicate

reserved bits.

Full name of bit

Descriptions of

bit settings

Bit numbers

Initial bit values

Possible types of

access

R/W

Read only

Write only

Read and write

Note: * When the EMC bit in BCR is cleared to 0, addresses of some registers are changed.

Appendix B Internal I/O Registers

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REJ09B0258-0300

P1DDR—Port 1 Data Direction Register H'EE000 Port 1

Bit

Initial value

Read/Write 0

DDR

Port 1 input/output select

Generic input

Generic output

Initial value

Read/Write 11111111

Modes 1 to 4

Modes 5 to 7

P2DDR—Port 2 Data Direction Register H'EE001 Port 2

Bit

Initial value

Read/Write 0

DDR

Port 2 input/output select

Generic input

Generic output

Initial value

Read/Write 11111111

Modes 1 to 4

Modes 5 to 7

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 765 of 910

REJ09B0258-0300

P3DDR—Port 3 Data Direction Register H'EE002 Port 3

Bit

Initial value

Read/Write 0

DDR

Port 3 input/output select

Generic input

Generic output

P4DDR—Port 4 Data Direction Register H'EE003 Port 4

Bit

Initial value

Read/Write 0

DDR

Port 4 input/output select

Generic input

Generic output

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 766 of 910

REJ09B0258-0300

P5DDR—Port 5 Data Direction Register H'EE004 Port 5

Bit

Initial value

Read/Write

7654

DDR

Port 5 input/output select

Generic input pin

Generic output pin

Initial value

Read/Write 11111111

Modes 1 to 4

Modes 5 to 7 1111

P6DDR—Port 6 Data Direction Register H'EE005 Port 6

Bit 76

DDR

Initial value

Read/Write 10

Port 6 input/output select

Generic input

Generic output

Appendix B Internal I/O Registers

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REJ09B0258-0300

P8DDR—Port 8 Data Direction Register H'EE007 Port 8

Bit

Initial value

Read/Write

7654

DDR

Port 8 input/output select

Generic input

Generic output

Initial value

Read/Write 111 0

Modes 1 to 4

Modes 5 to 7 1110

Appendix B Internal I/O Registers

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REJ09B0258-0300

P9DDR—Port 9 Data Direction Register H'EE008 Port 9

Bit

Initial value

Read/Write

DDR

Port 9 input/output select

Generic input

Generic output

PADDR—Port A Data Direction Register H'EE00 9 Port A

Bit

Initial value

Read/Write

DDR

Initial value

Read/Write 10

Modes 3, 4

Modes

1, 2, 5, 6, 7 0

Port A input/output select

Generic input

Generic output

PBDDR—Port B Dat a Direction Registe r H'EE00A Port B

Bit

Initial value

Read/Write

DDR

Port B input/output select

Generic input

Generic output

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 769 of 910

REJ09B0258-0300

MDCR—Mode Control Registe r H'EE011 Syst em control

Bit

Initial value

Read/Write 1

MDS2

MDS1

MDS0

Mode select 2 to 0

Operating Mode

***

Bit 2

Bit 1

Bit 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

Note: * Determined by the state of the mode pins (MD

to MD

Appendix B Internal I/O Registers

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REJ09B0258-0300

SYSCR—System Control Register H'EE012 System control

Bit

Initial value

Read/Write 0

R/W

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

NMIEG

R/W

SSOE

R/W

RAME

NMI edge select

1An interrupt is requested at the falling edge of NMI

An interrupt is requested at the rising edge of NMI

RAM enable

1On-chip RAM is disabled

On-chip RAM is enabled

User bit enable

1CCR bit 6 (UI) is used as an interrupt mask bit

CCR bit 6 (UI) is used as a user bit

Standby timer select 2 to 0

Bit 6

STS2 Waiting Time = 8,192 states

Waiting Time = 16,384 states

Waiting Time = 32,768 states

Waiting Time = 65,536 states

Waiting Time = 131,072 states

Waiting Time = 26,2144 states

Waiting Time = 1,024 states

Illegal setting

Bit 5

STS1 Bit 4

STS0 Standby Timer

Software standby

1SLEEP instruction causes transition to sleep mode

SLEEP instruction causes transition to software standby mode

Software standby output port enable

In software standby mode,

all address bus and bus

control signals are high-

impedance

In software standby mode,

address bus retains output

state and bus control

signals are fixed high

Appendix B Internal I/O Registers

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REJ09B0258-0300

BRCR—Bus Release Control Register H'EE013 Bus controller

Bit 7

A23E

A22E

A21E

A20E

3210

BRLE

Initial value

Read/Write 11111110

R/W

Modes

1, 2, 6, 7

Initial value

Read/Write 1

R/W 1

R/W 1110

R/W

Address 23 to 20 enable

Address output

Other input/output

Mode 5

Bus release enable

The bus cannot be

released to an

external device

The bus can be

released to an

external device

Initial value

Read/Write 1

R/W 1

R/W 01110

R/W

Modes

3, 4

ISCR—IRQ Se nse Control Regis ter H'EE014 Interrupt Co ntro ller

Bit

Initial value

Read/Write 0

R/W

IRQ5SC

R/W

IRQ4SC

R/W

IRQ3SC

R/W

IRQ2SC

R/W

IRQ1SC

R/W

IRQ0SC

IRQ5 to IRQ0 sense control

Interrupts are requested when IRQ

to IRQ

are low

Interrupts are requested by falling-edge input at IRQ

to IRQ

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 772 of 910

REJ09B0258-0300

IER—IRQ Enable Register H'EE015 Interrupt Controller

Bit

Initial value

Read/Write 0

R/W

IRQ5E

R/W

IRQ4E

R/W

IRQ3E

R/W

IRQ2E

R/W

IRQ1E

R/W

IRQ0E

IRQ5 to IRQ0 enable

IRQ5 to IRQ0 interrupts are disabled

IRQ5 to IRQ0 interrupts are enabled

ISR—IRQ Status Register H'EE016 Interrupt Controller

Bit

Initial value

Read/Write 0

R/(W)*

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

IRQ0F

IRQ5 to IRQ0 flags

Note: * Onl

0 can be written, to clear the fla

Bits 5 to 0

IRQ5F to IRQ0F Setting and Clearing Conditions

(n = 5 to 0)

[Clearing conditions]

• Read IRQnF when IRQnF = 1, then write 0 in IRQnF.

• IRQnSC = 0, IRQn input is high, and interrupt exception

handling is being carried out.

• IRQnSC = 1 and IRQn interrupt exception handling is being

carried out.

[Setting conditions]

• IRQnSC = 0 and IRQn input is low.

• IRQnSC = 1 and IRQn input changes from high to low.

Appendix B Internal I/O Registers

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REJ09B0258-0300

IPRA—Interrupt Priori ty Register A H'EE018 Interrupt Contro ller

Bit

Initial value

Read/Write 0

R/W

IPRA7

R/W

IPRA6

R/W

IPRA5

R/W

IPRA4

R/W

IPRA3

R/W

IPRA2

R/W

IPRA1

R/W

IPRA0

Priority level A7 to A0

Priority level 0 (low priority)

Priority level 1 (high priority)

• Interrupt sources controlled by each bit

IPRA

Bit

Interrupt

source

Bit 7

IPRA7

IRQ

Bit 6

IPRA6

IRQ

Bit 5

IPRA5

IRQ

Bit 4

IPRA4

IRQ

Bit 3

IPRA3

Bit 2

IPRA2

Bit 1

IPRA1

Bit 0

IPRA0

WDT,

DRAM

interface,

A/D converter

16-bit

timer

channel 0

16-bit

timer

channel 1

16-bit

timer

channel 2

IPRB—Interrupt Priorit y Register B H'EE019 Interrupt Controller

Bit

Initial value

Read/Write 0

R/W

IPRB7

R/W

IPRB6

R/W

IPRB5

R/W

IPRB3

R/W

IPRB2

R/W

IPRB1

R/W

Priority level B7 to B5, B3 to B1

Priority level 0 (low priority)

Priority level 1 (high priority)

Bit 7

IPRB7

Bit 6

IPRB6

Bit 5

IPRB5

Bit 4 Bit 3

IPRB3

Bit 2

IPRB2

Bit 1

IPRB1

Bit 0

8-bit timer

channels

0 and 1

8-bit timer

channels

2 and 3

DMAC SCI

channel 0

SCI

channel 1

SCI

channel 2

• Interrupt sources controlled by each bit

IPRB

Bit

Interrupt

source

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 774 of 910

REJ09B0258-0300

DASTCR—D/A Standby Control Re gister H'EE01A D/A

Bit

Initial value

Read/Write 1

R/W

DASTE

D/A standby enable

D/A output is disabled in software standby mode

D/A output is enabled in software standby mode

(Initial value)

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 775 of 910

REJ09B0258-0300

DIVCR—Division Control Register H'EE01B System control

Bit

Initial value

Read/Write 1

R/W

DIV1

R/W

DIV0

Divide 1 and 0

Frequency Division Ratio

Bit 1

DIV1

Bit 0

DIV0 1/1

1/2

1/4

1/8

(Initial value)

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 776 of 910

REJ09B0258-0300

MSTCRH—Module St andby Control Reg ister H H'EE0 1C System control

7654321 0

PSTOP MSTPH2 MSTPH1 MSTPH0

R/W R/W

0111100 0

Module standby H2 to H0

Selection bits for placing modules

in standby state.

Bit

Initial value

Read/Write

Reserved bits

φ clock stop

Enables or disables ø clock output.

MSTCRL—Module Standby Control Register L H'EE01D System control

7654321 0

MSTPL7 MSTPL2MSTPL3MSTPL4MSTPL5 MSTPL0

R/W R/W

R/WR/WR/WR/WR/W R/W

0000000 0

Module standby L7, L5 to L2, L0

Selection bits for placing modules

in standby state.

Reserved bits

Bit

Initial value

Read/Write

Appendix B Internal I/O Registers

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REJ09B0258-0300

ADRCR—Address Control Register H'EE01E Bus controller



Bit

Initial value

Read/Write



ADRCTL

R/W



Reserved bits Address control

Selects address update

mode 1 or address

update mode 2.

Description

ADRCTL

Address update mode 2 is selected

Address update mode 1 is selected (Initial value)

Note: * This re

ister is used onl

in the flash memor

R version and mask ROM version.

CSCR—Chip Select Control Register H'EE01F Bus controller

Bit

Initial value

Read/Write 0

R/W

CS7E

(n = 7 to 4)

R/W

CS6E

R/W

CS5E

R/W

CS4E

Chip select 7 to 4 enable

Description

Bit n

CSnE Output of chip select signal CSn is disabled (Initial value)

Output of chip select signal CSn is enabled

Appendix B Internal I/O Registers

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REJ09B0258-0300

ABWCR—Bus Width Control Register H'EE020 Bus controller

Bit

Initial value

Read/Write

R/W

ABW7

R/W

ABW6

R/W

ABW5

R/W

ABW4

R/W

ABW3

R/W

ABW2

R/W

ABW1

R/W

ABW0

Area 7 to 0 bus width control

Bus Width of Access Area

Bits 7 to 0

ABW7

to ABW0

Areas 7 to 0 are 16-bit access areas

Areas 7 to 0 are 8-bit access areas

Modes 1, 3, 5, 6, 7

Modes 2, 4

ASTCR—Access State Control Register H'EE021 Bus controller

Bit

Initial value

Read/Write 1

R/W

AST7

R/W

AST6

R/W

AST5

R/W

AST4

R/W

AST3

R/W

AST2

R/W

AST1

R/W

AST0

Area 7 to 0 access state control

Number of States in Access Area

Bits 7 to 0

AST7

to AST0

Areas 7 to 0 are two-state access areas

Areas 7 to 0 are three-state access areas

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 779 of 910

REJ09B0258-0300

WCRH—Wait Control Register H H'EE022 Bus controller

R/W

W71

R/W

W70

R/W

W61

R/W

W60

R/W

W51

R/W

W50

R/W

W41

R/W

W40

Area 4 wait control 1 and 0

No program wait is inserted

1 program wait state is inserted

2 program wait states are inserted

3 program wait states are inserted

Area 5 wait control 1 and 0

No program wait is inserted

1 program wait state is inserted

2 program wait states are inserted

3 program wait states are inserted

Area 6 wait control 1 and 0

No program wait is inserted

1 program wait state is inserted

2 program wait states are inserted

3 program wait states are inserted

Area 7 wait control 1 and 0

No program wait is inserted

1 program wait state is inserted

2 program wait states are inserted

3 program wait states are inserted

Bit

Initial value

Read/Write

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 780 of 910

REJ09B0258-0300

WCRL—Wait Control Register L H'EE023 Bus controller

Bit

Initial value

Read/Write 1

R/W

W31

R/W

W30

R/W

W21

R/W

W20

R/W

W11

R/W

W10

R/W

W01

R/W

W00

Area 0 wait control 1 and 0

No program wait is inserted

1 program wait state is inserted

2 program wait states are inserted

3 program wait states are inserted

Area 1 wait control 1 and 0

No program wait is inserted

1 program wait state is inserted

2 program wait states are inserted

3 program wait states are inserted

Area 2 wait control 1 and 0

No program wait is inserted

1 program wait state is inserted

2 program wait states are inserted

3 program wait states are inserted

Area 3 wait control 1 and 0

No program wait is inserted

1 program wait state is inserted

2 program wait states are inserted

3 program wait states are inserted

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 781 of 910

REJ09B0258-0300

BCR—Bus Cont rol Register H'EE024 Bus controller

Bit

Initial value

Read/Write 1

R/W

ICIS1

R/W

ICIS0

R/W

BROME

R/W

BRSTS1

R/W

BRSTS0

—

R/W

RDEA

R/W

WAITE

WAIT pin wait input is disabled

WAIT pin wait input is enabled

Burst cycle select 1

Burst access cycle comprises 2 states

Burst access cycle comprises 3 states

Burst ROM enable

Area 0 is a basic bus interface area

Area 0 is a burst ROM interface area

Idle cycle insertion 0

No idle cycle is inserted in case of consecutive external read and write cycles

Idle cycle is inserted in case of consecutive external read and write cycles

Idle cycle insertion 1

No idle cycle is inserted in case of consecutive external read cycles for different areas

Idle cycle is inserted in case of consecutive external read cycles for different areas

Burst cycle select 0

Max. 4 words in burst access

Max. 8 words in burst access

Area division unit select

Area divisions are as follows:

Areas 0 to 7 are the same size

(2 MB)

Wait pin enable

Area 0: 2 MB Area 4: 1.93 MB

Area 1: 2 MB Area 5: 4 kB

Area 2: 8 MB Area 6: 23.75 kB

Area 3: 2 MB Area 7: 22 B

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 782 of 910

REJ09B0258-0300

DRCRA—DRAM Control Register A H'EE026 DRAM interface

DRAS2

R/W

DRAS1

R/W

DRAS0

R/W

RDM

R/W

SRFMD

R/W

RFSHE

R/W

Bit

Initial value

Read/Write

Refresh pin enable

Self-refresh mode

RAS down mode

Burst access enable

RFSH pin refresh signal output is disabled

RFSH pin refresh signal output is enabled

DRAM self-refreshing is disabled in

software standby mode

DRAM self-refreshing is enabled

in software standby mode

DRAM interface: RAS up mode selected

DRAM interface: RAS down mode selected

Burst disabled (always full access)

DRAM space access performed in fast page mode

DRAM area select

DRAS2 DRAS1 DRAS0 Area 5

Normal

DRAM space

(CS

)

Area 4

Normal

DRAM space

(CS

)

DRAM space

(CS

)

Area 3

Normal

DRAM space

(CS

)

DRAM space

(CS

DRAM space

(CS

)

Area 2

Normal

DRAM space

(CS

)

DRAM space

(CS

)

DRAM space

(CS

)

DRAM space

(CS

)

DRAM space(

Note: * A single CSn pin serves as a common RAS output pin for a number of

areas. Unused CSn pins can be used as input/output ports.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 783 of 910

REJ09B0258-0300

DRCRB—DRAM Control Register B H'EE027 DRAM interface

MXC1

R/W

MXC0

R/W

CSEL

R/W

RCYCE

R/W

TPC

R/W

RCW

R/W

RLW

R/W

Bit

Initial value

Read/Write

Refresh cycle wait control

RAS-CAS wait

TP cycle control

Refresh cycle enable

Wait state (T

) insertion is disabled

1 wait state (T

) is inserted

1-state precharge cycle is inserted

2-state precharge cycle is inserted

Refresh cycles are disabled

DRAM refresh cycles are enabled

Multiplex control 1 and 0

MXC1 MXC0

Wait state (T

) insertion is disabled

1 wait state (T

) is inserted

CAS output pin select

PB4 and PB5 selected as UCAS and LCAS output pins

HWR and LWR selected as UCAS and LCAS output pins

Column address: 8 bits

Compared address:

Modes 1, 2 8-bit access space A

to A

16-bit access space A

to A

Modes 3, 4, 5 8-bit access space A

to A

16-bit access space A

to A

Column address: 9 bits

Compared address:

Modes 1, 2 8-bit access space A

to A

16-bit access space A

to A

Modes 3, 4, 5 8-bit access space A

to A

16-bit access space A

to A

Column address: 10 bits

Compared address:

Modes 1, 2 8-bit access space A

to A

16-bit access space A

to A

Modes 3, 4, 5 8-bit access space A

to A

16-bit access space A

to A

Illegal setting

Description

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 784 of 910

REJ09B0258-0300

RTMCSR—Refresh Timer Control/Status Register H'EE028 DRAM interface

CMF

R/(

W)*

CMIE

R/W

CKS2

CKS1

CKS0

Bit

Initial value

Read/Write R/W R/W R/W

Refresh counter clock select

CKS2 CKS1 CKS0 Count operation halted

φ/2 used as counter clock

φ/8 used as counter clock

φ/32 used as counter clock

φ/128 used as counter clock

φ/512 used as counter clock

φ/2048 used as counter clock

φ/4096 used as counter clock

Compare match interrupt enable

The CMI interrupt requested by the CMF flag is disabled

The CMI interrupt requested by the CMF flag is enabled

Compare match flag

[Clearing conditions]

• Cleared by a reset and in standby mode

• Cleared by reading CMF when CMF = 1, then writing 0 in CMF

[Setting condition]

When RTCNT = RTCOR

Description

Note: * Onl

0 can be written to clear the fla

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 785 of 910

REJ09B0258-0300

RTCNT—Refresh Timer Counter H'EE029 DRAM interface

R/W

Bit

Initial value

Read/Write

Incremented by internal clock selected

by bits CKS2 to CKS0 in RTMCSR

RTCOR—Refresh Time Constant Register H'EE02A DRAM interface

R/W

Bit

Initial value

Read/Write

RTCNT compare match period

Note: Only byte access can be used on this register.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 786 of 910

REJ09B0258-0300

FLMCR1—Flash Memory Control Register 1 H'EE030 Flash Memory

Bit

Initial value

Read/Write 1/0

FWE

R/W

SWE

R/W

ESU

R/W

PSU

R/W

Initial value

Read/Write

Modes 5

and 7

Modes 1 to

4, and 6 0

Program mode cleared (Initial value)

Transition to program mode

[Setting condition]

When FWE = 1, SWE = 1, and PSU = 1

Program mode

Erase mode cleared (Initial value)

Transition to erase mode

[Setting condition]

When FWE = 1, SWE = 1, and ESU = 1

Erase mode

Program-verify mode cleared (Initial value)

Transition to program-verify mode

[Setting condition]

When FWE = 1 and SWE = 1

Program-verify mode

Erase-verify mode cleared (Initial value)

Transition to erase-verify mode

[Setting condition]

When FWE = 1 and SWE = 1

Erase-verify mode

Program setup cleared (Initial value)

Program setup

[Setting condition]

When FWE = 1 and SWE = 1

Program setup

Erase setup cleared (Initial value)

Erase setup

[Setting condition]

When FWE = 1 and SWE = 1

Erase setup bit

Write/erase disabled (Initial value)

Write/erase enabled

[Setting condition]

When FWE = 1

Software write enable bit

When a low level is input to the FWE pin (hardware protection state)

When a high level is input to the FWE pin

Flash write enable bit

Note: This register is used only in the flash memory and flash memory R versions.

Reading the corresponding address in a mask ROM version will always return

1s, and writes to this address are disabled.

Fix the FWE pin low in mode 6.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 787 of 910

REJ09B0258-0300

FLMCR (FLMCR2)—Flash Memory Control Register 2 H'EE031 Flash Memory

Bit

Initial value

Read/Write

FLER

—

Flash memory error Reserved bits

Note: Writes to FLMCR2 are prohibited.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 788 of 910

REJ09B0258-0300

EBR (EBR1)—Erase Block Register H'EE032 Flash Memory

Bit 7

EB7

EB6

EB5

EB4

EB3

EB2

EB1

EB0

Block EB7 to EB0 is not selected (Initial value)

Block EB7 to EB0 is selected

Block 7 to 0

Note: When not erasing, clear EBR to H'00.

Writes are invalid.

A value of 1 cannot be set in this register in mode 6.

Initial value

Read/Write 0

R/W 0

R/W

Initial value

Read/Write

Modes 5

and 7

Modes 1 to

4, and 6 0

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 789 of 910

REJ09B0258-0300

EBR (EBR2)—Erase Block Register 2 H'EE033 Flash Memory

Bit 7

—

EB13

EB12

EB11

EB10

EB9

EB8

Block EB13 to EB8 is not selected (Initial value)

Block EB13 to EB8 is selected

Block 13 to 8

Note: When not erasing, clear EBR to H'00.

A value of 1 cannot be set in this register in mode 6.

Initial value

Read/Write 0

R/W 0

R/W

Initial value

Read/Write

Modes 5

and 7

Modes 1 to

4, and 6 0

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 790 of 910

REJ09B0258-0300

P2PCR—Port 2 Input Pull-Up Control Register H'EE03C Port 2

Bit

Initial value

Read/Write 0

R/W

PCR

R/W

PCR

R/W

PCR

R/W

PCR

R/W

PCR

R/W

PCR

R/W

PCR

R/W

PCR

Port 2 input pull-up control 7 to 0

Input pull-up transistor is off

Input pull-up transistor is on

Note: Valid when the corresponding P2DDR bit is cleared to 0

(designating generic input).

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 791 of 910

REJ09B0258-0300

P4PCR—Port 4 Input Pull-Up Control Register H'EE03E Port 4

Bit

Initial value

Read/Write

R/W

PCR

R/W

PCR

R/W

PCR

R/W

PCR

R/W

PCR

R/W

PCR

R/W

PCR

R/W

PCR

Port 4 input pull-up control 7 to 0

Input pull-up transistor is off

Input pull-up transistor is on

Note: Valid when the corresponding P4DDR bit is cleared to 0

(designating generic input).

P5PCR—Port 5 Input Pull-Up Control Register H'EE03F Port 5

Bit

Initial value

Read/Write 1

R/W

PCR

R/W

PCR

R/W

PCR

R/W

PCR

Port 5 input pull-up control 3 to 0

Input pull-up transistor is off

Input pull-up transistor is on

Note: Valid when the corresponding P5DDR bit is

cleared to 0

(

desi

natin

eneric input

)

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 792 of 910

REJ09B0258-0300

RAM Control Register RAMCR H'EE077 Flash Memory

Bit 3 Bit 2 Bit 1 Bit 0

RAMS RAM2 RAM1 RAM0 RAM Area

0/1

RAM Emulation Status

H'FFE000 to H'FFEFFF

H'000000 to H'000FFF

H'001000 to H'001FFF

H'002000 to H'002FFF

H'003000 to H'003FFF

H'004000 to H'004FFF

H'005000 to H'005FFF

H'006000 to H'006FFF

H'007000 to H'007FFF

Emulation

Mapping RAM

RAM select, RAM2 to RAM0

Note: *In mode 6 (single-chip normal mode), flash memory emulation by RAM is not

supported; these bits can be modified, but must not be set to 1.

Bit 7

—RAMS

6543210

——— RAM2 RAM1 RAM0

Reserved bits

Modes

1 to 4 1

—1

—0

—

Initial value

R/W

Initial value

R/W

Modes

5 to 7 1

—1

—0

R/W*0

R/W*

Note: This register is used only in the flash memory and flash memory R versions.

Reading the corresponding address in a mask ROM version will always return 1s,

and writes to this address are disabled.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 793 of 910

REJ09B0258-0300

MAR0A R/E/H/L—Memory Address Register 0A R/E/H/L H'FFF20 H'FFF21

H'FFF22 H'FFF23 DMAC0

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

111111 11

MAR0AR MAR0AE

Undetermined

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAR0AH MAR0AL

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

Undetermined

Source or destination address

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 794 of 910

REJ09B0258-0300

ETCR0A H/L—Execute Transfer Count Register 0A H/L H'FFF24 H'FFF25 DMAC0

• Short address mode

 I/O mode and idle mode

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

Transfer counter

 Repeat mode

Bit

Initial value

Read/Write

76543210

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

Transfer counter

76543210

ETCR0AH

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

Initial count

ETCR0AL

• Full address mode

 Normal mode

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

Undetermined

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/WR/W

Transfer counter

 Block transfer mode

Bit

Initial value

Read/Write

76543210

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

Block size counter

76543210

ETCR0AH

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

Initial block size

ETCR0AL

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 795 of 910

REJ09B0258-0300

IOAR0A—I/O Address Register 0A H'FFF26 DMAC0

Bit

Initial value

Read/Write R/W

R/W

Short address mode : source or destination address

Full address mode : not used

Undetermined

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 796 of 910

REJ09B0258-0300

DTCR0A—Data Transfer Control Register 0A H'FFF27 DMAC0

• Short address mode

Bit

Initial value

Read/Write 0

R/W

DTE

R/W

DTSZ

R/W

DTID

R/W

RPE

R/W

DTIE

R/W

DTS2

R/W

DTS1

R/W

DTS0

Data transfer interrupt enable

0Interrupt requested by

DTE bit is disabled

1Interrupt requested by

DTE bit is enabled

Repeat enable

0I/O mode

1Repeat mode

Idle mode

RPE DTIE Description

Data transfer increment/decrement

0Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer

If DTSZ = 1, MAR is incremented by 2 after each transfer

1Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer

If DTSZ = 1, MAR is decremented by 2 after each transfer

Data transfer size

1Byte-size transfer

Word-size transfer

Data transfer enable

1Data transfer is disabled

Data transfer is enabled

Data transfer select

Bit 2

DTS2 Bit 1

DTS1 Bit 0

DTS0

Compare match/input capture A

interrupt from 16-bit timer channel 0

Compare match/input capture A

interrupt from 16-bit timer channel 1

Compare match/input capture A

interrupt from 16-bit timer channel 2

A/D converter conversion end interrupt

SCI0 transmit-data-empty interrupt

SCI0 receive-data-full interrupt

Transfer in full address mode

Data Transfer Activation Source

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 797 of 910

REJ09B0258-0300

DTCR0A—Data Transfer Control Register 0A (cont) H'FFF27 DMAC0

• Full address mode

Bit

Initial value

Read/Write 0

R/W

DTE

R/W

DTSZ

R/W

SAID

R/W

SAIDE

R/W

DTIE

R/W

DTS2A

R/W

DTS1A

R/W

DTS0A

Data transfer select 0A

Bit 4

SAIDE

0 MARA is held fixed

Incremented: If DTSZ = 0, MARA is incremented by 1 after each transfer

If DTSZ = 1, MARA is incremented by 2 after each transfer

Increment/Decrement Enable

Data transfer size

1Byte-size transfer

Word-size transfer

Data transfer enable

1Data transfer is disabled

Data transfer is enabled

1Normal mode

Block transfer mode

Data transfer select 2A and 1A

Set both bits to 1

Data transfer interrupt enable

1Interrupt requested by DTE bit is disabled

Interrupt requested by DTE bit is enabled

Source address increment/decrement (bit 5)

Source address increment/decrement enable (bit 4)

1MARA is held fixed

Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer

If DTSZ = 1, MARA is decremented by 2 after each transfer

Bit 5

SAID

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 798 of 910

REJ09B0258-0300

MAR0B R/E/H/L—Memory Address Register 0B R/E/H/L H'FFF28 H'FFF29

H'FFF2A H'FFF2B DMAC0

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

111111 11

MAR0BR MAR0BE

Undetermined

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAR0BH MAR0BL

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

Undetermined

Source or destination address

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 799 of 910

REJ09B0258-0300

ETCR0B H/L—Execute Transfer Count Register 0B H/L H'FFF2C, H'FFF2D DMAC0

• Short address mode

 I/O mode and idle mode

R/W R/W R/W R/W R/W R/W R/WR/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/WR/W

Bit

Initial value

Read/Write Undetermined

Transfer counter

 Repeat mode

76543210

R/W R/W R/W R/W R/W R/W R/WR/W

76543210

R/W R/W R/W R/W R/W R/W R/WR/W

Bit

Initial value

Read/Write Undetermined

Transfer counter

ETCR0BH

Undetermined

Initial count

ETCR0BL

• Full address mode

 Normal mode

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

Undetermined

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/WR/W

Not used

 Block transfer mode

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

Undetermined

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/WR/W

Block transfer counter

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 800 of 910

REJ09B0258-0300

IOAR0B—I/O Address Register 0B H'FFF2E DMAC0

Bit

Initial value

Read/Write R/W

R/W

Short address mode : source or destination address

Full address mode : not used

Undetermined

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 801 of 910

REJ09B0258-0300

DTCR0B—Data Transfer Control Register 0B H'FFF2F DMAC0

• Short address mode

Bit

Initial value

Read/Write 0

R/W

DTE

R/W

DTSZ

R/W

DTID

R/W

RPE

R/W

DTIE

R/W

DTS2

R/W

DTS1

R/W

DTS0

Data transfer select

Bit 2

DTS2 Bit 1

DTS1 Bit 0

DTS0

Compare match/input capture A interrupt

from 16-bit timer channel 0

Compare match/input capture A interrupt

from 16-bit timer channel 1

Compare match/input capture A interrupt

from 16-bit timer channel 2

A/D converter conversion end interrupt

SCI0 transmit-data-empty interrupt

SCI0 receive-data-full interrupt

Falling edge of DREQ input

Low level of DREQ input

Data Transfer Activation Source

Data transfer interrupt enable

0Interrupt requested by

DTE bit is disabled

1Interrupt requested by

DTE bit is enabled

Repeat enable

0I/O mode

1Repeat mode

Idle mode

RPE DTIE Description

Data transfer increment/decrement

0Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer

If DTSZ = 1, MAR is incremented by 2 after each transfer

1Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer

If DTSZ = 1, MAR is decremented by 2 after each transfer

Data transfer size

1Byte-size transfer

Word-size transfer

Data transfer enable

1Data transfer is disabled

Data transfer is enabled

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 802 of 910

REJ09B0258-0300

DTCR0B—Data Transfer Control Register 0B (cont) H'FFF2F DMAC0

• Full address mode

Bit

Initial value

Read/Write 0

R/W

DTME

R/W

DAID

R/W

DAIDE

R/W

TMS

R/W

DTS2B

R/W

DTS1B

R/W

DTS0B

Data transfer select 2B to 0B

Bit 2

DTS2B

Bit 1

DTS1B

Bit 0

DTS0B

Data Transfer Activation Source

Transfer mode select

1Destination is the block area in block transfer mode

Source is the block area in block transfer mode

Data transfer master enable

1Data transfer is disabled

Data transfer is enabled Compare match/input

capture A interrupt from

16-bit timer channel 0

Normal Mode Block Transfer Mode

Auto-request

(burst mode)

Compare match/input

capture A interrupt from

16-bit timer channel 1

Not available

Compare match/input

capture A interrupt from

16-bit timer channel 2

Auto-request

(cycle-steal mode)

A/D converter conversion

end interrupt

Not available

Falling edge input of

DREQ

Not available

Falling edge input of

DREQ

Low level input at DREQ

Bit 4

DAIDE

0 MARB is held fixed

Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer

If DTSZ = 1, MARB is incremented by 2 after each transfer

MARB is held fixed

Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer

If DTSZ = 1, MARB is decremented by 2 after each transfer

Increment/Decrement Enable

Destination address increment/decrement (bit 5)

Destination address increment/decrement enable (bit 4)

Bit 5

DAID

Not available

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 803 of 910

REJ09B0258-0300

MAR1A R/E/H/L—Memory Address Register 1A R/E/H/L H'FFF30 H'FFF31

H'FFF32 H'FFF33 DMAC1

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

111111 11

MAR1AR MAR1AE

Undetermined

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAR1AH MAR1AL

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

Undetermined

Note: Bit functions are the same as for DMAC0.

ETCR1A H/L—Execute Transfer Count Register 1A H/L H'FFF34 H'FFF35 DMAC1

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Undetermined

Note: Bit functions are the same as for DMAC0.

R/W R/W R/W R/W R/W R/W R/WR/W

Bit

Initial value

Read/Write

76543210

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

76543210

ETCR1AH

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

ETCR1AL

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 804 of 910

REJ09B0258-0300

IOAR1A—I/O Address Register 1A H'FFF36 DMAC1

Bit

Initial value

Read/Write R/W

R/W

Note: Bit functions are the same as for DMAC0.

Undetermined

DTCR1A—Data Transfer Control Register 1A H'FFF37 DMAC1

• Short address mode

Bit

Initial value

Read/Write 0

R/W

DTE

R/W

DTSZ

R/W

DTID

R/W

RPE

R/W

DTIE

R/W

DTS2

R/W

DTS1

R/W

DTS0

• Full address mode

Bit

Initial value

Read/Write 0

R/W

DTE

R/W

DTSZ

R/W

SAID

R/W

SAIDE

R/W

DTIE

R/W

DTS2A

R/W

DTS1A

R/W

DTS0A

Note: Bit functions are the same as for DMAC0.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 805 of 910

REJ09B0258-0300

MAR1B R/E/H/L—Memory Address Register 1B R/E/H/L H'FFF38 H'FFF39

H'FFF3A H'FFF3B DMAC1

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

111111 11

MAR1BR MAR1BE

Undetermined

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAR1BH MAR1BL

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

Undetermined

Note: Bit functions are the same as for DMAC0.

ETCR1B H/L—Execute Transfer Count Register 1B H/L H'FFF3C H'FFF3D DMAC1

Bit

Initial value

Read/Write R/W R/W R/W R/W R/W R/W R/WR/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Undetermined

Note: Bit functions are the same as for DMAC0.

R/W R/W R/W R/W R/W R/W R/WR/W

Bit

Initial value

Read/Write

76543210

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

76543210

ETCR1BH

Undetermined

R/W R/W R/W R/W R/W R/W R/WR/W

ETCR1BL

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 806 of 910

REJ09B0258-0300

IOAR1B—I/O Address Register 1B H'FFF3E DMAC1

Note: Bit functions are the same as for DMAC0.

R/W

Bit

Initial value

Read/Write Undetermined

DTCR1B—Data Transfer Control Register 1B H'FFF3F DMAC1

• Short address mode

R/W

DTE

0R/W

DTSZ

0R/W

DTID

0R/W

RPE

0R/W

DTIE

0R/W

DTS2

0R/W

DTS1

0R/W

DTS0

Bit

Initial value

Read/Write

• Full address mode

Note: Bit functions are the same as for DMAC0.

R/W

DTME

0R/W

DAID

0R/W

DAIDE

0R/W

TMS

0R/W

DTS2B

0R/W

DTS1B

R/W

DTS0B

Bit

Initial value

Read/Write

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 807 of 910

REJ09B0258-0300

TSTR—Timer Start Register H'FFF60 16-bit timer (all channels)

—

Bit

Initial value

Read/Write

—

STR2

R/W

Reserved bits

STR1

R/W

STR0

R/W

TCNT0 is halted (Initial value)

TCNT0 is counting

Counter start 0

TCNT1 is halted (Initial value)

TCNT1 is counting

Counter start 1

TCNT2 is halted (Initial value)

TCNT2 is counting

Counter start 2

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 808 of 910

REJ09B0258-0300

TSNC—Timer Synchro Register H'FFF61 16-bit timer (all channels)

—

Bit

Initial value

Read/Write

—

SYNC2

R/W

SYNC1

R/W

SYNC0

R/W

Channel 0 timer counter (TCNT0) operates

independently (TCNT0 presetting/clearing is

unrelated to other channels) (Initial value)

Channel 0 operates synchronously

TCNT0 synchronous presetting/synchronous

clearing is possible

Timer synchronization 0

Channel 1 timer counter (TCNT1) operates

independently (TCNT1 presetting/clearing is

unrelated to other channels) (Initial value)

Channel 1 operates synchronously

TCNT1 synchronous presetting/synchronous

clearing is possible

Timer synchronization 1

Channel 2 timer counter (TCNT2) operates

independently (TCNT2 presetting/clearing is

unrelated to other channels) (Initial value)

Channel 2 operates synchronously

TCNT2 synchronous presetting/synchronous

clearing is possible

Timer synchronization 2

Reserved bits

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 809 of 910

REJ09B0258-0300

TMDR—Timer Mode Register H'FFF62 16-bit timer (all channels)

—

Bit

Initial value

Read/Write

MDF

R/W

FDIR

R/W

—

PWM2

R/W

PWM1

R/W

PWM0

R/W

Channel 0 operates normally (Initial value)

Channel 0 operates in PWM mode

PWM mode 0

Channel 1 operates normally (Initial value)

Channel 1 operates in PWM mode

PWM mode 1

Channel 2 operates normally (Initial value)

Channel 2 operates in PWM mode

PWM mode 2

OVF is set to 1 in TISRC when TCNT2

overflows or underflows (Initial value)

OVF is set to 1 in TISRC when TCNT2

overflows

Flag direction

Channel 2 operates normally (Initial value)

Channel 2 operates in phase counting mode

Phase counting mode flag

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 810 of 910

REJ09B0258-0300

TOLR—Timer Output Level Setting Register H'FFF63 16-bit timer (all channels)

—

Bit

Initial value

Read/Write

—

TOB2

TOA2

TOB1

TOA1

TOB0

TOA0

TIOCA

is 0 (Initial value)

TIOCA

is 1

Output level setting A0

TIOCB

is 0 (Initial value)

TIOCB

is 1

Output level setting B0

TIOCA

is 0 (Initial value)

TIOCA

is 1

Output level setting A1

TIOCB

is 0 (Initial value)

TIOCB

is 1

Output level setting B1

TIOCA

is 0 (Initial value)

TIOCA

is 1

Output level setting A2

TIOCB

is 0 (Initial value)

TIOCB

is 1

Output level setting B2

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 811 of 910

REJ09B0258-0300

TISRA—T imer Interrupt Status Register A H'FFF64 16-bit timer (all channels)

—

IMIEA2

R/W

IMIEA1

R/W

IMIEA0

R/W

—

IMFA2

R/(W)*

IMFA1

R/(W)*

IMFA0

R/(W)*

Input capture/compare match flag A0

[Clearing conditions] (Initial value)

Read IMFA0 when IMFA0=1, then write 0 in IMFA0

DMAC activated by IMIA0 interrupt.

[Setting conditions]

TCNT0=GRA0 when GRA0 functions as an output compare register.

TCNT0 value is transferred to GRA0 by an input capture signal when GRA0

functions as an input capture register.

Input capture/compare match flag A1

[Clearing conditions] (Initial value)

Read IMFA1 when IMFA1=1, then write 0 in IMFA1

DMAC activated by IMIA1 interrupt.

[Setting conditions]

TCNT1=GRA1 when GRA1 functions as an output compare register.

TCNT1 value is transferred to GRA1 by an input capture signal when GRA1

functions as an input capture register.

Input capture/compare match flag A2

[Clearing conditions] (Initial value)

Read IMFA2 when IMFA2=1, then write 0 in IMFA2

DMAC activated by IMIA2 interrupt.

[Setting conditions]

TCNT2=GRA2 when GRA2 functions as an output compare register.

TCNT2 value is transferred to GRA2 by an input capture signal when GRA2

functions as an input capture register.

1IMIA0 interrupt requested by IMFA0 flag is disabled (Initial value)

IMIA0 interrupt requested by IMFA0 is enabled

Input capture/compare match interrupt enable A0

1IMIA1 interrupt requested by IMFA1 flag is disabled (Initial value)

IMIA1 interrupt requested by IMFA1 is enabled

Input capture/compare match interrupt enable A1

1IMIA2 interrupt requested by IMFA2 flag is disabled (Initial value)

IMIA2 interrupt requested by IMFA2 is enabled

Input capture/compare match interrupt enable A2

Bit:

Initial value:

Read/Write:

Note: * Only 0 can be written, to clear the flag.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 812 of 910

REJ09B0258-0300

TISRB—Timer Interrupt Status Register B H'FFF65 16-bit timer (all channels)

—

IMIEB2

R/W

IMIEB1

R/W

IMIEB0

R/W

—

IMFB2

R/(W)*

IMFB1

R/(W)*

IMFB0

R/(W)*

Input capture/compare match flag B0

[Clearing condition] (Initial value)

Read IMFB0 when IMFB0=1, then write 0 in IMFB0.

[Setting conditions]

TCNT0=GRB0 when GRB0 functions as an output compare register.

TCNT0 value is transferred to GRB0 by an input capture signal when GRB0

functions as an input capture register.

Input capture/compare match flag B1

[Clearing condition] (Initial value)

Read IMFB1 when IMFB1=1, then write 0 in IMFB1.

[Setting conditions]

TCNT1=GRB1 when GRB1 functions as an output compare register.

TCNT1 value is transferred to GRB1 by an input capture signal when GRB1

functions as an input capture register.

Input capture/compare match flag B2

[Clearing condition] (Initial value)

Read IMFB2 when IMFB2=1, then write 0 in IMFB2.

[Setting conditions]

TCNT2=GRB2 when GRB2 functions as an output compare register.

TCNT2 value is transferred to GRB2 by an input capture signal when GRB2

functions as an input capture register.

1IMIB0 interrupt requested by IMFB0 flag is disabled (Initial value)

IMIB0 interrupt requested by IMFB0 is enabled

Input capture/compare match interrupt enable B0

1IMIB1 interrupt requested by IMFB1 flag is disabled (Initial value)

IMIB1 interrupt requested by IMFB1 is enabled

Input capture/compare match interrupt enable B1

1IMIB2 interrupt requested by IMFB2 flag is disabled (Initial value)

IMIB2 interrupt requested by IMFB2 is enabled

Input capture/compare match interrupt enable B2

Note: * Only 0 can be written, to clear the fla

Bit:

Initial value:

Read/Write:

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 813 of 910

REJ09B0258-0300

TISRC—Timer Interrupt Status Register C H'FFF66 16-bit timer (all channels)

—

OVIE2

R/W

OVIE1

R/W

OVIE0

R/W

—

OVF2

R/(W)*

OVF1

R/(W)*

OVF0

R/(W)*

1OVI0 interrupt requested by OVF0 flag is disabled (Initial value)

OVI0 interrupt requested by OVF0 flag is enabled

Overflow interrupt enable 0

1OVI1 interrupt requested by OVF1 flag is disabled (Initial value)

OVI1 interrupt requested by OVF1 flag is enabled

Overflow interrupt enable 1

1OVI2 interrupt requested by OVF2 flag is disabled (Initial value)

OVI2 interrupt requested by OVF2 flag is enabled

Overflow interrupt enable 2

Bit:

Initial value:

Read/Write:

[Clearing condition] (Initial value)

Read OVF0 when OVF0 = 1, then write 0 in OVF0.

[Setting condition]

TCNT0 overflowed from H'FFFF to H'0000.

Overflow flag 0

[Clearing condition] (Initial value)

Read OVF1 when OVF1 = 1, then write 0 in OVF1.

[Setting condition]

TCNT1 overflowed from H'FFFF to H'0000.

Overflow flag 1

[Clearing condition] (Initial value)

Read OVF2 when OVF2 = 1, then write 0 in OVF2.

[Setting condition]

TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000

to H'FFFF.

Overflow flag 2

Note: * Only 0 can be written, to clear the flag.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 814 of 910

REJ09B0258-0300

TCR0—Timer Control Register H'FFF68 16-bit timer channel 0

Bit

Initial value

Read/Write 1

—

R/W

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC2

R/W

TPSC1

R/W

TPSC0

Timer prescaler 2 to 0

TCNT Clock Source

Bit 2

TPSC2

Bit 1

TPSC1

Bit 0

TPSC0

Internal clock : φ (Initial value)

Internal clock : φ / 2

Internal clock : φ / 4

Internal clock : φ / 8

External clock A : TCLKA input

External clock B : TCLKB input

External clock C : TCLKC input

External clock D : TCLKD input

Clock edge 1 and 0

Counted Edges of External Clock

Bit 4

CKEG1

Bit 3

CKEG0

Rising edges counted

Falling edges counted

Both edges counted

—

Counter clear 1 and 0

TCNT clear Sources

Bit 6

CCLR1

Bit 5

CCLR0

TCNT is not cleared

TCNT is cleared by GRA compare match or input capture

TCNT is cleared by GRB compare match or input capture

Synchronous clear : TCNT is cleared in synchronization with other

synchronized timers

(Initial value)

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 815 of 910

REJ09B0258-0300

TIOR0—Timer I/O Control Register 0 H'FFF69 16-bit timer channel 0

I/O control A2 to A0

GRA Functions

Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0

—

IOB2

R/W

IOB1

R/W

IOB0

R/W

—

IOA2

R/W

IOA1

R/W

IOA0

R/W

Bit:

Initial value:

Read/Write:

No output at compare match (Initial value)

0 output at GRA compare match

1 output at GRA compare match

Output toggles at GRA compare match

(channel 2 only: 1 output)

GRA captures rising edges of input

GRA captures falling edges of input

GRA captures both edges of input

GRA is an output

compare register

GRA is an input

capture register

I/O control B2 to B0

GRB Functions

Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 No output at compare match (Initial value)

0 output at GRB compare match

1 output at GRB compare match

Output toggles at GRB compare match

(channel 2 only: 1 output)

GRB captures rising edges of input

GRB captures falling edges of input

GRB captures both edges of input

GRB is an output

compare register

GRB is an input

capture register

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 816 of 910

REJ09B0258-0300

TCNT 0 H/L—Timer Counter 0 H/L H'FFF6A, H'FFF6B 16-bit timer channel 0

Bit

Initial value

Read/Write 0

R/W 0

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 0

R/W

Up - counter

GRA0 H/L—General Register A0 H/L H'FFF6C, H'FFF6D 16-bit timer channel 0

Bit

Initial value

Read/Write 1

R/W 1

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 1

R/W

Output compare or input capture register

GRB0 H/L—General Register B0 H/L H'FFF6E, H'FFF6F 16-bit timer channel 0

Bit

Initial value

Read/Write 1

R/W 1

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 1

R/W

Output compare or input capture register

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 817 of 910

REJ09B0258-0300

TCR1 Timer Control Register 1 H'FFF70 16-bit timer channel 1

—

Bit

Initial value

Read/Write

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC2

R/W

TPSC1

R/W

TPSC0

R/W

Note: Bit functions are the same as for 16-bit timer channel 0.

TIOR1—Timer I/O Control Register 1 H'FFF71 16-bit timer channel 1

—

Bit

Initial value

Read/Write

IOB2

R/W

IOB1

R/W

IOB0

R/W

—

IOA2

R/W

IOA1

R/W

IOA0

R/W

Note: Bit functions are the same as for 16-bit timer channel 0.

TCNT 1 H/L—Timer Counter 1 H/L H'FFF72, H'FFF73 16-bit timer channel 1

Bit

Initial value

Read/Write 0

R/W 0

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 0

R/W

Note: Bit functions are the same as for 16-bit timer channel 0.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 818 of 910

REJ09B0258-0300

GRA1 H/L—General Register A1 H/L H'FFF74, H'FFF75 16-bit timer channel 1

Bit

Initial value

Read/Write 1

R/W 1

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 1

R/W

Note: Bit functions are the same as for 16-bit timer channel 0.

GRB1 H/L—General Register B1 H/L H'FFF76, H'FFF77 16-bit timer channel 1

Bit

Initial value

Read/Write 1

R/W 1

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 1

R/W

Note: Bit functions are the same as for 16-bit timer channel 0.

TCR2 Timer Control Register 2 H'FFF78 16-bit timer channel 2

—

Bit

Initial value

Notes: 1. Bit functions are the same as for 16-bit timer channel 0.

2. When phase counting mode is selected in channel 2, the settings of bits

CKEG1 and CKEG0 and TPSC2 to TPSC0 in TCR2 are ignored.

Read/Write

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC2

R/W

TPSC1

R/W

TPSC0

R/W

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 819 of 910

REJ09B0258-0300

TIOR2—Timer I/O Control Register 2 H'FFF79 16-bit timer channel 2

—

Bit

Initial value

Read/Write

IOB2

R/W

IOB1

R/W

IOB0

R/W

—

IOA2

R/W

IOA1

R/W

IOA0

R/W

Note: Bit functions are the same as for 16-bit timer channel 0.

TCNT 2 H/L—Timer Counter 2 H/L H'FFF7A, H'FFF7B 16-bit timer channel 2

Bit

Initial value

Read/Write 0

R/W 0

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 0

R/W

Phase counting mode :

Other mode : up / down counter

up - counter

GRA2 H/L—General Register A2 H/L H'FFF7C, H'FFF7D 16-bit timer channel 2

Bit

Initial value

Read/Write 1

R/W 1

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 1

R/W

Note: Bit functions are the same as for 16-bit timer channel 0.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 820 of 910

REJ09B0258-0300

GRB2 H/L—General Register B2 H/L H'FFF7E, H'FFF7F 16-bit timer channel 2

Bit

Initial value

Read/Write 1

R/W 1

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 1

R/W

Note: Bit functions are the same as for 16-bit timer channel 0.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 821 of 910

REJ09B0258-0300

T CR0—T imer Control Register 0

T CR1—T imer Control Register 1 H'FFF80

H'FFF81 8-bit timer channel 0

8-bit timer channel 1

Bit

Initial value

Read/Write 0

R/W

CMIEB

R/W

CMIEA

R/W

OVIE

R/W

CCLR1

R/W

CCLR0

R/W

CKS2

R/W

CKS1

R/W

CKS0

Clock select 2 to 0

Clock input is disabled

Internal clock, counted on rising

edge of φ/8

Internal clock, counted on rising

edge of φ/64

Internal clock, counted on rising

edge of φ/8192

External clock, counted on falling edge

External clock, counted on rising edge

External clock, counted on both

rising and falling edges

Counter clear 1 and 0

Clearing is disabled

Cleared by compare match A

Cleared by compare match B/input capture B

Cleared by input capture B

Timer overflow interrupt enable

OVI interrupt requested by OVF is disabled

OVI interrupt requested by OVF is enabled

Compare match interrupt enable A

CMIA interrupt requested by CMFA is disabled

CMIA interrupt requested by CMFA is enabled

Compare match interrupt enable B

CMIB interrupt requested by CMFB is disabled

CMIB interrupt requested by CMFB is enabled

Channel 0:

Count on TCNT1 overflow signal*

Channel 1:

Count on TCNT0 compare match

Notes: * If the clock input of channel 0 is the TCNT1

overflow signal and that of channel 1 is the

TCNT0 compare match signal, no

incrementing clock is generated. Do not use

this setting.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 822 of 910

REJ09B0258-0300

TCSR0—Timer Control/Status Register 0 H'FFF82 8-bit timer channel 0

Output select A1 and A0

Description

Bit 1

OS1

Bit 0

OS0

ICE in

TCSR1

Bit 3

OIS3

Bit 4

ADTE

TRGE

Bit 2

OIS2

No change at compare match A

0 output at compare match A

1 output at compare match A

Output toggles at compare

match A

Output/input capture edge select B3 and B2

No change at compare match B

0 output at compare match B

1 output at compare match B

Output toggles at compare match

TCORB input capture on rising

edge

TCORB input capture on falling

edge

TCORB input capture on both

rising and falling edges

A/D trigger enable (TCSR0 only)

A/D converter start requests by compare match

A or an external trigger are disabled

A/D converter start requests by compare match

A or an external trigger are enabled

A/D converter start requests by an external trigger are enabled

A/D converter start requests by compare match A are enabled

Timer overflow flag

0[Clearing condition]

Read OVF when OVF = 1, then write 0 in OVF.

Bit

Initial value

Read/Write 0

R/(W)*

CMFB

R/(W)*

CMFA

R/(W)*

OVF

R/W

ADTE

R/W

OIS3

R/W

OIS2

R/W

OS1

R/W

OS0

1[Setting condition]

TCNT overflows from H'FF to H'00.

Compare match flag A

0 [Clearing condition]

Read CMFA when CMFA = 1, then write 0 in CMFA.

1[Setting condition]

TCNT = TCORA

Compare match/input capture flag B

0[Clearing condition]

Read CMFB when CMFB = 1, then write 0 in CMFB.

1 [Setting conditions]

TCNT = TCORB

The TCNT value is transferred to TCORB by an input capture signal when

TCORB functions as an input capture register.

Note: * Only 0 can be written to bits 7 to 5, to clear these flags.

Note: * TRGE is bit 7 of the A/D control register (ADCR).

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 823 of 910

REJ09B0258-0300

TCSR1—Timer Control/Status Register 1 H'FFF83 8-bit timer channel 1

Output select A1 and A0

Description

Bit 1

OS1

Bit 0

OS0

ICE in

TCSR1

Bit 3

OIS3

Bit 2

OIS2

No change at compare match A

0 output at compare match A

1 output at compare match A

Output toggles at compare

match A

Output/input capture edge select B3 and B2

No change at compare match B

0 output at compare match B

1 output at compare match B

Output toggles at compare match

TCORB input capture on rising

edge

TCORB input capture on falling

edge

TCORB input capture on both

rising and falling edges

Timer overflow flag

0[Clearing condition]

Read OVF when OVF = 1, then write 0 in OVF.

1[Setting condition]

TCNT overflows from H'FF to H'00.

Compare match/input capture flag A

0[Clearing condition]

Read CMFA when CMFA = 1, then write 0 in CMFA.

1 [Setting condition]

TCNT = TCORA

Compare match/input capture flag B

0 [Clearing condition]

Read CMFB when CMFB = 1, then write 0 in CMFB.

1 [Setting conditions]

TCNT = TCORB

The TCNT value is transferred to TCORB by an input capture signal when

TCORB functions as an input capture register.

Note: * Onl

0 can be written to bits 7 to 5, to clear these fla

Bit

Initial value

Read/Write 0

R/(W)*

CMFB

R/(W)*

CMFA

R/(W)*

OVF

R/W

ICE

R/W

OIS3

R/W

OIS2

R/W

OS1

R/W

OS0

Input capture enable

TCORB is a compare match register

TCORB is an input capture register

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 824 of 910

REJ09B0258-0300

TCORA0—Time Constant Register A0

TCORA1—Time Constant Register A1 H'FFF84

H'FFF85 8-bit timer channel 0

8-bit timer channel 1

Bit

Initial value

Read/Write 1

R/W 1

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 1

R/W

TCORA0 TCORA1

T CORB0—Time Constant Register B0

T CORB1—Time Constant Register B1 H'FFF86

H'FFF87 8-bit timer channel 0

8-bit timer channel 1

Bit

Initial value

Read/Write 1

R/W 1

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 1

R/W

TCORB0 TCORB1

TCNT 0—Timer Counter 0

TCNT 1—Timer Counter 1 H'FFF88

H'FFF89 8-bit timer channel 0

8-bit timer channel 1

Bit

Initial value

Read/Write 0

R/W 0

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 0

R/W

TCNT0 TCNT1

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 825 of 910

REJ09B0258-0300

TCSR—Timer Control/Status Register H'FFF8C WDT

Bit

Initial value

Read/Write 0

R/(W)*

OVF

R/W

WT/IT

R/W

TME

R/W

CKS2

R/W

CKS1

Clock select 2 to 0

0φ/2

φ/32

φ/64

φ/128

φ/256

φ/512

φ/2048

φ/4096

CKS0

R/W

Timer enable

Timer disabled

• TCNT is initialized to H'00 and

halted

1Timer enabled

• TCNT is counting

Timer mode select

0Interval timer:

requests interval timer interrupts

1Watchdog timer:

generates a reset signal

Overflow flag

0[Clearing condition]

Read OVF when OVF = 1, then write 0 in OVF

1[Setting condition]

TCNT changes from H'FF to H'00

Note: * Onl

0 can be written, to clear the fla

CKS2 CKS1 CKS0 Description

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 826 of 910

REJ09B0258-0300

TCNT —Timer Counter H'FFF8D (read), H'FFF8C (write) WDT

Bit

Initial value

Read/Write 0

R/W

Count value

RSTCSR—Reset Control/Status Register H'FFF8F (read), H'FFF8E (write) WDT

Bit

Initial value

Read/Write 0

R/(W)*

WRST

R/W

RSTOE

Reset output enable

0External output of reset signal is disabled

External output of reset signal is enabled

Watchdog timer reset

0 [Clearing conditions]

Reset signal at RES pin

Read WRST when WRST = 1, then write 0 in WRST

1[Setting condition]

TCNT overflow generates a reset signal

Note: * Onl

0 can be written in bit 7, to clear the fla

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 827 of 910

REJ09B0258-0300

T CR2—T imer Control Register 2

T CR3—T imer Control Register 3 H'FFF90

H'FFF91 8-bit timer channel 2

8-bit timer channel 3

Bit

Initial value

Read/Write 0

R/W

CMIEB

R/W

CMIEA

R/W

OVIE

R/W

CCLR1

R/W

CCLR0

R/W

CKS2

R/W

CKS1

R/W

CKS0

Clock select 2 to 0

Clock input is disabled

Internal clock, counted on rising edge

of φ/8

Internal clock, counted on rising edge

of φ/64

Internal clock, counted on rising edge

of φ/8192

External clock, counted on falling edge

External clock, counted on rising edge

External clock, counted on both

rising and falling edges

Counter clear 1 and 0

Clearing is disabled

Cleared by compare match A

Cleared by compare match B/input capture B

Cleared by input capture B

Timer overflow interrupt enable

OVI interrupt requested by OVF is disabled

OVI interrupt requested by OVF is enabled

Compare match interrupt enable A

CMIA interrupt requested by CMFA is disabled

CMIA interrupt requested by CMFA is enabled

Compare match interrupt enable B

CMIB interrupt requested by CMFB is disabled

CMIB interrupt requested by CMFB is enabled

CSK2 CSK1 CSK0 Description

Channel 2:

Count on TCNT3 overflow signal*

Channel 3:

Count on TCNT2 compare match A*

Note: * If the clock input of channel 2 is the TCNT3 overflow

signal and that of channel 3 is the TCNT2 compare

match signal, no incrementing clock is generated.

Do not use this setting.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 828 of 910

REJ09B0258-0300

TCSR2—Timer Control/Status Register 2

TCSR3—Timer Control/Status Register 3 H'FFF92

H'FFF93 8-bit timer channel 2

8-bit timer channel 3

Bit

Initial value

Read/Write 0

R/(W)*

CMFB

R/(W)*

CMFA

R/(W)*

OVF

R/W

ICE

R/W

OIS3

R/W

OIS2

R/W

OS1

R/W

OS0

Timer overflow flag

0[Clearing condition]

Read OVF when OVF = 1, then write 0 in OVF.

Bit

Initial value

Read/Write 0

R/(W)*

CMFB

R/(W)*

CMFA

R/(W)*

OVF

R/W

OIS3

R/W

OIS2

R/W

OS1

R/W

OS0

TCSR3

TCSR2

1[Setting condition]

TCNT overflows from H'FF to H'00.

Compare match/input capture flag A

0 [Clearing condition]

Read CMFA when CMFA = 1, then write 0 in CMFA.

1[Setting condition]

TCNT = TCORA

Compare match/input capture flag B

0[Clearing condition]

Read CMFB when CMFB = 1, then write 0 in CMFB.

[Setting conditions]

TCNT = TCORB

The TCNT value is transferred to TCORB by an input capture signal when

TCORB functions as an input capture register.

Note: * Only 0 can be written to bits 7 to 5, to clear these fla

Output select A1 and A0

Description

Bit 1

OS1

Bit 0

OS0

No change at compare match A

0 output at compare match A

1 output at compare match A

Output toggles at compare

match A

Description

ICE in

TCSR3

Bit 3

OIS3

Bit 3

OIS2

Output/input capture edge select B3 and B2

No change at compare match B

0 output at compare match B

1 output at compare match B

Output toggles at compare match

TCORB input capture on rising

edge

TCORB input capture on falling

edge

TCORB input capture on both

rising and falling edges

Input capture enable (TCSR3 only)

TCORB is a compare match register

TCORB is an input capture register

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 829 of 910

REJ09B0258-0300

TCORA2—Time Constant Register A2

TCORA3—Time Constant Register A3 H'FFF94

H'FFF95 8-bit timer channel 2

8-bit timer channel 3

Bit

Initial value

Read/Write 1

R/W 1

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 1

R/W

TCORA2 TCORA3

T CORB2—Time Constant Register B2

T CORB3—Time Constant Register B3 H'FFF96

H'FFF97 8-bit timer channel 2

8-bit timer channel 3

Bit

Initial value

Read/Write 1

R/W 1

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 1

R/W

TCORB2 TCORB3

TCNT 2—Timer Counter 2

TCNT 3—Timer Counter 3 H'FFF98

H'FFF99 8-bit timer channel 2

8-bit timer channel 3

Bit

Initial value

Read/Write 0

R/W 0

R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W 0

R/W

TCNT2 TCNT3

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 830 of 910

REJ09B0258-0300

DADR0—D/A Data Register 0 H'FFF9C D/A

Bit

Initial value

Read/Write 0

R/W

D/A conversion data

DADR1—D/A Data Register 1 H'FFF9D D/A

Bit

Initial value

Read/Write 0

R/W

D/A conversion data

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 831 of 910

REJ09B0258-0300

DACR—D/A Control Register H'FFF9E D/A

Bit

Initial value

Read/Write 0

R/W

DAOE1

R/W

DAOE0

R/W

DAE

D/A enable

Bit 7

DAOE1

D/A conversion is disabled

in channels 0 and 1

D/A conversion is enabled

in channel 0

D/A conversion is disabled

in channel 1

D/A conversion is disabled

in channel 0

D/A conversion is enabled

in channel 1

Description

D/A conversion is enabled

in channels 0 and 1

D/A conversion is enabled

in channels 0 and 1

D/A conversion is enabled

in channels 0 and 1

Bit 6 Bit 5

DAOE0 DAE

D/A output enable 0

0DA

analog output is disabled

1Channel-0 D/A conversion and DA

analog output are enabled

D/A output enable 1

0DA

analog output is disabled

1Channel-1 D/A conversion and DA

analog output are enabled

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 832 of 910

REJ09B0258-0300

TPMR—TPC Output Mode Register H'FFFA0 TPC

Bit

Initial value

Read/Write 1

R/W

G3NOV

R/W

G2NOV

R/W

G1NOV

R/W

G0NOV

Group 0 non-overlap

0Normal TPC output in group 0. Output values

change at compare match A in the selected

16-bit timer channel

1Non-overlapping TPC output in group 0,

controlled by compare match A and B in the

selected 16-bit timer channel

Group 1 non-overlap

0Normal TPC output in group 1. Output values change

at compare match A in the selected 16-bit timer channel

1Non-overlapping TPC output in group 1, controlled by

compare match A and B in the selected 16-bit timer channel

Group 2 non-overlap

0Normal TPC output in group 2. Output values change at

compare match A in the selected 16-bit timer channel

1Non-overlapping TPC output in group 2, controlled by

compare match A and B in the selected 16-bit timer channel

Group 3 non-overlap

0Normal TPC output in group 3. Output values change at

compare match A in the selected 16-bit timer channel

1Non-overlapping TPC output in group 3, controlled by

compare match A and B in the selected 16-bit timer channel

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 833 of 910

REJ09B0258-0300

TPCR—TPC Output Control Register H'FFFA1 TPC

Group 0 compare match select 1 and 0

Bit 1

G0CMS1 16-Bit Timer Channel Selected as Output Trigger

Bit 0

G0CMS0 TPC output group 0 (TP

to TP

) is triggered by

compare match in 16-bit timer channel 0

TPC output group 0 (TP

to TP

) is triggered by

compare match in 16-bit timer channel 1

TPC output group 0 (TP

to TP

) is triggered by

compare match in 16-bit timer channel 2

Group 1 compare match select 1 and 0

Bit 3

G1CMS1 16-Bit Timer Channel Selected as Output Trigger

Bit 2

G1CMS0 TPC output group 1 (TP

to TP

) is triggered by

compare match in 16-bit timer channel 0

TPC output group 1 (TP

to TP

) is triggered by

compare match in 16-bit timer channel 1

TPC output group 1 (TP

to TP

) is triggered by

compare match in 16-bit timer channel 2

Group 2 compare match select 1 and 0

Bit 5

G2CMS1 16-Bit Timer Channel Selected as Output Trigger

Bit 4

G2CMS0 TPC output group 2 (TP

to TP

) is triggered by compare match in 16-bit timer channel 0

TPC output group 2 (TP

to TP

) is triggered by compare match in 16-bit timer channel 1

TPC output group 2 (TP

to TP

) is triggered by compare match in 16-bit timer channel 2

Group 3 compare match select 1 and 0

Bit 7

G3CMS1 16-Bit Timer Channel Selected as Output Trigger

Bit 6

G3CMS0 TPC output group 3 (TP

to TP

) is triggered by compare match in 16-bit timer channel 0

TPC output group 3 (TP

to TP

) is triggered by compare match in 16-bit timer channel 1

TPC output group 3 (TP

to TP

) is triggered by compare match in 16-bit timer channel 2

Bit

Initial value

Read/Write

G3CMS1

G3CMS0

G2CMS1

G2CMS0

R/W

G1CMS1

R/W

G1CMS0

R/W

G0CMS1

R/W

G0CMS0

R/W

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 834 of 910

REJ09B0258-0300

NDERB—Next Data Enable Register B H'FFFA2 TPC

Bit

Initial value

Read/Write 0

R/W

NDER15

R/W

NDER14

R/W

NDER13

R/W

NDER12

R/W

NDER11

R/W

NDER10

R/W

NDER9

R/W

NDER8

Next data enable 15 to 8

Bits 7 to 0

NDER15

to NDER8

Description

TPC outputs TP

to TP

are disabled

(NDR15 to NDR8 are not transferred to PB

to PB

)

TPC outputs TP

to TP

are enabled

(NDR15 to NDR8 are transferred to PB

to PB

)

NDERA—Next Data Enable Register A H'FFFA3 TPC

Bit

Initial value

Read/Write 0

R/W

NDER7

R/W

NDER6

R/W

NDER5

R/W

NDER4

R/W

NDER3

R/W

NDER2

R/W

NDER1

R/W

NDER0

Next data enable 7 to 0

Bits 7 to 0

NDER7

to NDER0

Description

TPC outputs TP

to TP

are disabled

(NDR7 to NDR0 are not transferred to PA

to PA

)

TPC outputs TP

to TP

are enabled

(NDR7 to NDR0 are transferred to PA

to PA

)

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 835 of 910

REJ09B0258-0300

NDRB—Next Dat a Regist er B H'FFFA4/H'FFFA6 TPC

• Same trigger for TPC output groups 2 and 3

 Address H'FFFA4

Bit

Initial value

Read/Write 0

R/W

NDR15

R/W

NDR14

R/W

NDR13

R/W

NDR12

R/W

NDR11

R/W

NDR10

R/W

NDR9

R/W

NDR8

Store the next output data for TPC output group 3 Store the next output data for TPC output group 2

 Address H'FFFA6

Bit

Initial value

Read/Write

• Different triggers for TPC output groups 2 and 3

 Address H'FFFA4

Bit

Initial value

Read/Write 0

R/W

NDR15

R/W

NDR14

R/W

NDR13

R/W

NDR12

Store the next output data for TPC output group 3

 Address H'FFFA6

Bit

Initial value

Read/Write 0

R/W

NDR11

NDR10

NDR9

1111

NDR8

Store the next output data for TPC output group 2

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 836 of 910

REJ09B0258-0300

NDRA—Next Data Register A H'FFFA5/H'FFFA7 TPC

• Same trigger for TPC output groups 0 and 1

 Address H'FFFA5

Bit

Initial value

Read/Write 0

R/W

NDR7

R/W

NDR6

R/W

NDR5

R/W

NDR4

R/W

NDR3

R/W

NDR2

R/W

NDR1

R/W

NDR0

Store the next output data for TPC output group 1 Store the next output data for TPC output group 0

 Address H'FFFA7

Bit

Initial value

Read/Write

• Different triggers for TPC output groups 0 and 1

 Address H'FFFA5

Bit

Initial value

Read/Write 0

R/W

NDR7

R/W

NDR6

R/W

NDR5

R/W

NDR4

Store the next output data for TPC output group 1

 Address H'FFFA7

Bit

Initial value

Read/Write 0

R/W

NDR3

NDR2

NDR1

1111

NDR0

Store the next output data for TPC output group 0

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 837 of 910

REJ09B0258-0300

SMR—Serial Mode Register H'FFFB0 SCI0

Bit

Initial value

Read/Write 0

R/W

C/A

R/W

CHR

R/W

O/E

R/W 0

R/W

STOP

R/W

CKS1

Clock select 1 and 0

Bit 0

φ clock

φ/4 clock

φ/16 clock

φ/64 clock

CKS0

R/W

Multiprocessor mode

0Multiprocessor function disabled

Multiprocessor format selected

Bit 1 Clock Source

CKS0CKS1

Stop bit length

0One stop bit

Two stop bits

Parity mode

0Even parity

Odd parity

Parity enable

0Parity bit is not added or checked

Parity bit is added and checked

GSM mode (for smart card interface)

0TEND flag is set 12.5 etu* after start bit

TEND flag is set 11.0 etu* after start bit

Character length

08-bit data

7-bit data

Communication mode (for serial communication interface)

0Asynchronous mode

Synchronous mode

Note: * etu (Elementary time unit: the time for transfer of one bit)

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 838 of 910

REJ09B0258-0300

BRR—Bit Rate Register H'FFFB1 SCI0

Bit

Initial value

Read/Write 1

R/W

Serial communication bit rate settin

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 839 of 910

REJ09B0258-0300

SCR—Serial Control Register H'FFFB2 SCI0

Bit

Initial value

Read/Write 0

R/W

TIE

R/W

RIE

R/W

MPIE

R/W

TEIE

R/W

CKE1

R/W

CKE0

Clock enable 1 and 0

(for serial communication interface)

Bit 1

CKE1 Bit 0

CKE0

Asynchronous mode

Synchronous mode

Asynchronous mode

Synchronous mode

Asynchronous mode

Synchronous mode

Asynchronous mode

Synchronous mode

Description

Transmit-end interrupt enable

1Transmit-end interrupt requests (TEI) are disabled

Transmit-end interrupt requests (TEI) are enabled

Receive interrupt enable

1Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled

Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled

Internal clock, SCK pin

available for generic I/O

Internal clock, SCK pin

used for serial clock output

Internal clock, SCK pin

used for clock output

Internal clock, SCK pin

used for serial clock output

External clock, SCK pin

used for clock input

External clock, SCK pin

used for serial clock input

External clock, SCK pin

used for clock input

External clock, SCK pin

used for serial clock input

Multiprocessor interrupt enable

1Multiprocessor interrupts are disabled (normal receive operation)

Multiprocessor interrupts are enabled

Receive enable

Receiving is

disabled

Receiving is

enabled

Transmit enable

1Transmitting is disabled

Transmitting is enabled

Transmit interrupt enable

1Transmit-data-empty interrupt request (TXI) is disabled

Transmit-data-empty interrupt request (TXI) is enabled

Clock enable 1 and 0 (for smart card interface)

SMR

GM Bit 1

CKE1 Bit 0

CKE0

Description

SCK pin available for generic I/O

SCK pin used for clock output

SCK pin output fixed low

SCK pin used for clock output

SCK pin output fixed high

SCK pin used for clock output

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 840 of 910

REJ09B0258-0300

TDR—Transmit Data Register H'FFFB3 SCI0

Bit

Initial value

Read/Write 1

R/W

Serial transmit data

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 841 of 910

REJ09B0258-0300

SSR—Serial Status Register H'FFFB4 SCI0

Bit

Initial value

Read/Write 1

R/(W)*

TDRE 0

R/(W)*

RDRF 0

R/(W)*

ORER 0

R/(W)*

FER/ERS 0

R/(W)*

PER 1

TEND 0

MPB 0

R/W

MPBT

Transmit end (for serial communication interface)

Multiprocessor bit transfer

1Multiprocessor bit value in transmit data is 0

Multiprocessor bit value in transmit data is 1

Multiprocessor bit

1Multiprocessor bit value in receive data is 0

Multiprocessor bit value in receive data is 1

[Clearing conditions]

Read TDRE when TDRE = 1, then write 0 in TDRE.

The DMAC writes data in TDR.

[Setting conditions]

Reset or transition to standby mode

TE is cleared to 0 in SCR.

TDRE is 1 when last bit of 1-byte serial character is

transmitted.

Parity error

[Clearing conditions] Reset or transition to standby mode

Read PER when PER = 1, then write 0 in PER.

[Setting condition] Parity error (parity of receive data does not match parity

setting of O/E bit in SMR)

Framing error (for serial communication interface)

0[Clearing conditions] Reset or transition to standby mode

Read FER when FER = 1, then write 0 in FER.

[Setting condition] Framing error (stop bit is 0)

Error signal status (for smart card interface)

0[Clearing conditions] Reset or transition to standby mode

Read ERS when ERS = 1, then write 0 in ERS.

[Setting condition] A low error signal is received.

Overrun error

0[Clearing conditions] Reset or transition to standby mode

Read ORER when ORER = 1, then write 0 in ORER.

[Setting condition] Overrun error (reception of the next serial data ends when RDRF = 1)

Receive data register full

0[Clearing conditions] Reset or transition to standby mode

Read RDRF when RDRF = 1, then write 0 in RDRF.

The DMAC reads data from RDR.

[Setting condition] Serial data is received normally and transferred from RSR to RDR.

Transmit data register empty

Note: * Only 0 can be written, to clear the flag.

0 [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE.

The DMAC writes data in TDR.

[Setting conditions] Reset or transition to standby mode

TE is 0 in SCR.

Data is transferred from TDR to TSR, enabling new data to be written in TDR

Transmit end (for smart card interface)

0[Clearing conditions]

Read TDRE when TDRE = 1, then write 0 in TDRE.

The DMAC writes data in TDR.

[Setting conditions]

Reset or transition to standby mode

TE is cleared to 0 in SCR and FER/ERS is cleared to 0.

TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu*

(when GM = 0) or 1.0 etu (when GM = 1) after 1-byte serial

character is transmitted.

Note: * etu (Elementary time unit: the time for transfer of one bit)

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 842 of 910

REJ09B0258-0300

RDR—Receive Data Register H'FFFB5 SCI0

Bit

Initial value

Read/Write 0

Serial receive data

SCMR—Smart Card Mode Register H'FFFB6 SCI0

R/W

SDIR

R/W

SINV

R/W

SMIF

Smart card interface mode select

Smart card interface function is disabled (Initial value)

Smart card interface function is enabled

Smart card data invert

Unmodified TDR contents are transmitted (Initial value)

Receive data is stored unmodified in RDR

Inverted 1/0 logic levels of TDR contents are transmitted

1/0 logic levels of received data are inverted before storage in RDR

Smart card data transfer direction

TDR contents are transmitted LSB-first (Initial value)

Receive data is stored LSB-first in RDR

TDR contents are transmitted MSB-first

Receive data is stored MSB-first in RDR

Bit

Initial value

Read/Write

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 843 of 910

REJ09B0258-0300

SMR—Serial Mode Register H'FFFB8 SCI1

R/W

C/A

R/W

CHR

R/W

O/E

R/W

STOP

R/W

CKS1

R/W

CKS0

Note: Bit functions are the same as for SCI0.

Bit

Initial value

Read/Write

BRR—Bit Rate Register H'FFFB9 SCI1

R/W

Note: Bit functions are the same as for SCI0.

Bit

Initial value

Read/Write

SCR—Serial Control Register H'FFFBA SCI1

R/W

TIE

R/W

RIE

R/W

MPIE

R/W

TEIE

R/W

CKE1

R/W

CKE0

Note: Bit functions are the same as for SCI0.

Bit

Initial value

Read/Write

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 844 of 910

REJ09B0258-0300

TDR—Transmit Data Register H'FFFBB SCI1

R/W

Bit

Initial value

Read/Write

Note: Bit functions are the same as for SCI0.

SSR—Serial Status Register H'FFFBC SCI1

R/(W)*

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

FER/ERS

R/(W)*

PER

TEND

MPB

R/W

MPBT

Bit

Initial value

Read/Write

Note: Bit functions are the same as for SCI0.

* Only 0 can be written, to clear the flag.

RDR—Receive Data Register H'FFFBD SCI1

Bit

Initial value

Read/Write

Note: Bit functions are the same as for SCI0.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 845 of 910

REJ09B0258-0300

SCMR—Smart Card Mode Register H'FFFBE SCI1

R/W

SDIR

SINV

1111

SMIF

Bit

Initial value

Read/Write

Note: Bit functions are the same as for SCI0.

SMR—Serial Mode Register H'FFFC0 SCI2

R/W

C/A

R/W

CHR

R/W

O/E

R/W

STOP

R/W

CKS1

R/W

CKS0

Bit

Initial value

Read/Write

Note: Bit functions are the same as for SCI0.

BRR—Bit Rate Register H'FFFC1 SCI2

R/W

Bit

Initial value

Read/Write

Note: Bit functions are the same as for SCI0.

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 846 of 910

REJ09B0258-0300

SCR—Serial Control Register H'FFFC2 SCI2

R/W

TIE

R/W

RIE

R/W

MPIE

R/W

TEIE

R/W

CKE1

R/W

CKE0

Bit

Initial value

Read/Write

Note: Bit functions are the same as for SCI0.

TDR—Transmit Data Register H'FFFC3 SCI2

R/W

Bit

Initial value

Read/Write

Note: Bit functions are the same as for SCI0.

SSR—Serial Status Register H'FFFC4 SCI2

R/(W)*

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

FER/ERS

R/(W)*

PER

TEND

MPB

R/W

MPBT

Bit

Initial value

Read/Write

Note: Bit functions are the same as for SCI0.

* Only 0 can be written, to clear the fla

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 847 of 910

REJ09B0258-0300

RDR—Receive Data Register H'FFFC5 SCI2

Bit

Initial value

Read/Write

Note: Bit functions are the same as for SCI0.

SCMR—Smart Card Mode Register H'FFFC6 SCI2

R/W

SDIR

SINV

1111

SMIF

Bit

Initial value

Read/Write

Note: Bit functions are the same as for SCI0.

P1DR—Port 1 Data Register H'FFFD0 Port 1

R/W

Data for port 1 pins

Bit

Initial value

Read/Write

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 848 of 910

REJ09B0258-0300

P2DR—Port 2 Data Register H'FFFD1 Port 2

R/W

Data for port 2 pins

Bit

Initial value

Read/Write

P3DR—Port 3 Data Register H'FFFD2 Port 3

R/W

Data for port 3 pins

Bit

Initial value

Read/Write

P4DR—Port 4 Data Register H'FFFD3 Port 4

R/W

Data for port 4 pins

Bit

Initial value

Read/Write

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 849 of 910

REJ09B0258-0300

P5DR—Port 5 Data Register H'FFFD4 Port 5

R/W

Data for port 5 pins

Bit

Initial value

Read/Write

P6DR—Port 6 Data Register H'FFFD5 Port 6

R/W

Data for port 6 pins

Bit

Initial value

Read/Write

P7DR—Port 7 Data Register H'FFFD6 Port 7

P77

P76

P75

P74

P73

P72

P71

P70

Data for port 7 pins

*******

Note: * Determined b

pins P7

to P7

Bit

Initial value

Read/Write

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 850 of 910

REJ09B0258-0300

P8DR—Port 8 Data Register H'FFFD7 Port 8

R/W

Data for port 8 pins

Bit

Initial value

Read/Write

P9DR—Port 9 Data Register H'FFFD8 Port 9

R/W

Data for port 9 pins

Bit

Initial value

Read/Write

PADR—Port A Data Register H'FFFD9 Port A

R/W

Data for port A pins

Bit

Initial value

Read/Write

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 851 of 910

REJ09B0258-0300

PBDR—Port B Dat a Regis ter H'FFFDA Port B

R/W

Data for port B pins

Bit

Initial value

Read/Write

ADDRA H/L—A/D Data Register A H/L H'FFFE0, H'FFFE1 A/D

AD9

A/D conversion data

10-bit data

ivin

an A/D conversion result

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

ADDRAH ADDRAL

Bit

Initial value

Read/Write

ADDRB H/L—A/D Data Register B H/L H'FFFE2, H'FFFE3 A/D

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

ADDRBH ADDRBL

A/D conversion data

10-bit data

ivin

an A/D conversion result

Bit

Initial value

Read/Write

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 852 of 910

REJ09B0258-0300

ADDRC H/L—A/D Data Register C H/L H'FFFE4, H'FFFE5 A/D

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

ADDRCH ADDRCL

A/D conversion data

10-bit data

ivin

an A/D conversion result

Bit

Initial value

Read/Write

ADDRD H/L—A/D Data Register D H/L H'FFFE6, H'FFFE7 A/D

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

ADDRDH ADDRDL

A/D conversion data

10-bit data

ivin

an A/D conversion result

Bit

Initial value

Read/Write

ADCR—A/D Control Register H'FFFE9 A/D

R/W

TRGE

R/W

Trigger Enable

A/D conversion start by external trigger or 8-bit timer

compare match is disabled

A/D conversion is started by falling edge of external

trigger signal (ADTRG) or 8-bit timer compare match

Bit

Initial value

Read/Write

Appendix B Internal I/O Registers

Rev. 3.00 Sep 14, 2005 page 853 of 910

REJ09B0258-0300

ADCSR—A/D Control/Status Register H'FFFE8 A/D

R/(W)*

ADF

R/W

ADIE

R/W

ADST

R/W

SCAN

R/W

CKS

R/W

CH2

R/W

CH1

R/W

CH0

Channel select 2 to 0

Group Selection

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

CH2

Description

Single Mode Scan Mode

Clock select

Conversion time =

134 states (maximum)

Conversion time =

70 states (maximum)

Channel Selection

CH1 CH0 AN0

AN0, AN1

AN0 to AN2

AN0 to AN3

AN4

AN4, AN5

AN4 to AN6

AN4 to AN7

Scan mode

1Single mode

Scan mode

A/D start

A/D conversion is stopped

Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends

Scan mode: A/D conversion starts and continues, cycling among the selected channels ADST

is cleared to 0 by software, by a reset, or by a transition to standby mode

A/D interrupt enable

1A/D end interrupt request is disabled

A/D end interrupt request is enabled

A/D end flag

0[Clearing condition]

Read ADF when ADF = 1, then write 0 in ADF

The DMAC is activated by an ADI interrupt

[Setting conditions]

Single mode: A/D conversion ends

Scan mode: A/D conversion ends in all selected channels

Note: * Onl

0 can be written, to clear the fla

Bit

Initial value

Read/Write

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 854 of 910

REJ09B0258-0300

Appendix C I/O Port B lock Diagrams

C.1 Port 1 Block Diagram

Reset

P1 DDR

Mode 1 to 4

WP1D

Reset

P1 DR

WP1

RP1

Mode 6/7

Mode

1 to 5

Internal data bus (upper)

Internal address bus

WP1D:

WP1:

RP1:

SSOE:

n = 0 to 7

Write to P1DDR

Write to port 1

Read port 1

Software standby output port enable

External bus

released

Hardware standby

Software

standby

Mode 6/7

SSOE

Figure C.1 Port 1 Block Diagram

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 855 of 910

REJ09B0258-0300

C.2 Port 2 Block Diagram

Reset

P2 DR

WP2

Reset

P2 DDR

WP2D

Reset

P2 PCR

WP2P

Mode 6/7

Mode

1 to 5

Internal data bus (upper)

Internal address bus

RP2P

RP2

WP2P:

RP2P:

WP2D:

WP2:

RP2:

SSOE:

n = 0 to 7

Write to P2PCR

Read P2PCR

Write to P2DDR

Write to port 2

Read port 2

Software standby output port enable

External bus

released

Hardware standby

Software

standby

Mode 6/7

Mode 1 to 4

SSOE

Figure C.2 Port 2 Block Diagram

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 856 of 910

REJ09B0258-0300

C.3 Port 3 Block Diagram

Reset

P3 DDR

WP3D

Reset

P3 DR

WP3

RP3

Mode

1 to 5

Internal data bus (upper)

WP3D:

WP3:

RP3:

n = 0 to 7

Write to P3DDR

Write to port 3

Read port 3

Mode 6/7

Write to external

address

Mode 6/7

Hardware standby

External

bus released

Read external

address

Internal data bus (lower)

Figure C.3 Port 3 Block Diagram

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 857 of 910

REJ09B0258-0300

C.4 Port 4 Block Diagram

RP4P

RP4

WP4

WP4D

WP4P

Reset

P4 PCR

P4 DDR

P4 DR

WP4P:

RP4P:

WP4D:

WP4:

RP4:

n = 0 to 7

Write to P4PCR

Read P4PCR

Write to P4DDR

Write to port 4

Read port 4

Write to external

address

External bus

release

Hardware

standby

Read external

address

Internal data bus (upper)

Internal data bus

(

lower

)

8-bit bus

mode

Mode 6/7 Mode

1 to 5

16-bit bus

mode

Figure C.4 Port 4 Block Diagram

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 858 of 910

REJ09B0258-0300

C.5 Port 5 Block Diagram

RP5P

RP5

WP5

WP5D

WP5P

Reset

P5 PCR

P5 DDR

P5 DR

WP5P:

RP5P:

WP5D:

WP5:

RP5:

SSOE:

n = 0 to 3

Write to P5PCR

Read P5PCR

Write to P5DDR

Write to port 5

Read port 5

Software standby output port enable

Mode 6/7

Mode

1 to 5

Internal data bus (upper)

Internal address bus

External bus

released

Hardware standby

Software

standby

Mode 6/7

Mode 1 to 4

SSOE

Figure C.5 Port 5 Block Diagram

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 859 of 910

REJ09B0258-0300

C.6 Port 6 Block Diagrams

WP6D:

WP6:

RP6:

Write to P6DDR

Write to port 6

Read port 6

RP6

input

WP6D

Reset

P6 DDR

WP6

Reset

P6 DR

Internal data bus

Bus controlle

WAIT

input

enable

Bus controlle

WAIT

Mode 6/7

Hardware standby

Figure C.6 (a) Port 6 Block Diagram (Pin P60)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 860 of 910

REJ09B0258-0300

WP6D:

WP6:

RP6:

Write to P6DDR

Write to port 6

Read port 6

WP6D

Reset

P6 DDR

WP6

Reset

P6 DR

RP6

Internal data bus

Bus

controller

Bus release

enable

BREQ input

Mode 6/7

Hardware standby

Figure C.6 (b) Port 6 Block Diagram (Pin P61)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 861 of 910

REJ09B0258-0300

WP6D

Reset

P6 DDR

WP6

Reset

P6 DR

RP6

WP6D:

WP6:

RP6:

Write to P6DDR

Write to port 6

Read port 6

Internal data bus

Bus controller

Bus release

enable

BACK

output

Mode 6/7

Hardware standby

Figure C.6 (c) Port 6 Block Diagram (Pin P62)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 862 of 910

REJ09B0258-0300

Reset

P6 DDR

WP6D

Reset

P6 DR

WP6

RP6

Mode

1 to 5

Internal data bus

WP6D:

WP6:

RP6:

SSOE:

Write to P6DDR

Write to port 6

Read port 6

Software standby output port enable

Mode 6/7

AS output

Bus controller

External bus

released

Hardware standby

Software

standby Mode 6/7

SSOE

Figure C.6 (d) Port 6 Block Diagram (Pin P63)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 863 of 910

REJ09B0258-0300

P64

Reset

P6 DDR

WP6D

Reset

P6 DR

WP6

RP6

Mode

1 to 5

Internal data bus

WP6D:

WP6:

RP6:

SSOE:

Write to P6DDR

Write to port 6

Read port 6

Software standby output port enable

Mode 6/7

RD output

WE output

enable

Bus controller

WE output

External bus

released

Hardware standby

Software

standby Mode 6/7

SSOE

Figure C.6 (e) Port 6 Block Diagram (Pin P64)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 864 of 910

REJ09B0258-0300

Reset

P6 DDR

WP6D

Reset

P6 DR

WP6

RP6

Mode

1 to 5

Internal data bus

WP6D:

WP6:

RP6:

SSOE:

n = 5 and 6

Write to P6DDR

Write to port 6

Read port 6

Software standby output port enable

Mode 6/7

HWR output

LWR output

CAS output

enable

Bus controller

UCAS output

LCAS output

External bus

released

Hardware standby

Software

standby Mode 6/7

SSOE

Figure C.6 (f) Port 6 Block Diagram (Pins P65 and P66)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 865 of 910

REJ09B0258-0300

Read port 6RP6:

Hardware standby

RP6

φ output

φ output enable

Internal data bus

Figure C.6 (g) Port 6 Block Diagram (Pin P67)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 866 of 910

REJ09B0258-0300

C.7 Port 7 Block Diagrams

RP7

RP7: Read port 7

n = 0 to 5

Internal data bus

A/D converter

Input enable

Channel select signal

Analog input

Figure C.7 (a) Port 7 Block Diagram (Pins P70 to P75)

RP7

RP7: Read port 7

n = 6 and 7

Internal data bus

D/A converter

Analog output

Output enable

A/D converter

Input enable

Channel select signal

Analog input

Figure C.7 (b) Port 7 Block Diagram (Pins P76 and P77)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 867 of 910

REJ09B0258-0300

C.8 Port 8 Block Diagrams

RP8

WP8D

Reset

External bus

released

Hardware

standby SSOE

Software standby

P8 DDR

WP8

Reset

P8 DR

WP8D:

WP8:

RP8:

SSOE:

Write to P8DDR

Write to port 8

Read port 8

Software standby output port enable

Internal data bus

Bus controller

RFSH output

enable

Self-refresh

output enable

output

Interrupt

controller

input

RFSH

IRQ

Mode 6/7

Figure C.8 (a) Port 8 Block Diagram (Pin P80)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 868 of 910

REJ09B0258-0300

WP8D

Reset

P8 DDR

WP8

Reset

P8 DR

RP8

WP8D:

WP8:

RP8:

SSOE:

Write to P8DDR

Write to port 8

Read port 8

Software standby output port enable

Internal data bus

Bus controller

Interrupt

controller

IRQ

input

output

RAS

output

RAS

output enable

Area 3 DRAM

connection enable

Mode

6/7

Mode 1 to 5

SSOE

Hardware standby

Software standby

External bus release

Figure C.8 (b) Port 8 Block Diagram (Pin P81)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 869 of 910

REJ09B0258-0300

WP8D

Reset

P8 DDR

WP8

Reset

P8 DR

RP8

WP8D:

WP8:

RP8:

SSOE:

Write to P8DDR

Write to port 8

Read port 8

Software standb

output port enable

Internal data bus

Bus controller

Interrupt

controller

IRQ

input

output

RAS

output

RAS

output enable

Mode 6/7

Mode 1 to 5

SSOE

Hardware

standby

Software standby

External bus release

Figure C.8 (c) Port 8 Block Diagram (Pin P82)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 870 of 910

REJ09B0258-0300

A/D converter

WP8D

Write to P8DDR

Write to port 8

Read port 8

Software standby output port enable

WP8D:

WP8:

RP8:

SSOE:

WP8

Reset

Internal data bus

RP8

Bus controller

output

Reset

Mode 6/7

Mode 1 to 5

Interrupt controller

IRQ3

input

ADTRG input

Mode

6/7 SSOE

External bus release

Software standby

Hardware standby P8

DDR

Figure C.8 (d) Port 8 Block Diagram (Pin P83)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 871 of 910

REJ09B0258-0300

WP8D

P8 DDR

WP8

Reset

Reset Mode 1 to 4

P8 DR

RP8

WP8D:

WP8:

RP8:

SSOE:

Write to P8DDR

Write to port 8

Read port 8

Software standb

output port enable

Internal data bus

Bus controller

outpu

Mode 6/7

Mode 1 to 5

Mode

6/7 SSOE

External bus release

Software standby

Hardware standby

Figure C.8 (e) Port 8 Block Diagram (Pin P84)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 872 of 910

REJ09B0258-0300

C.9 Port 9 Block Diagrams

WP9D:

WP9:

RP9:

Write to P9DDR

Write to port 9

Read port 9

RP9

WP9D

Reset

Hardware

standby QD

P9 DDR

WP9

Reset

P9 DR

Internal data bus

SCI

Output

enable

Serial

transmit

data

Guard

time

Figure C.9 (a) Port 9 Block Diagram (Pin P90)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 873 of 910

REJ09B0258-0300

WP9D:

WP9:

RP9:

Write to P9DDR

Write to port 9

Read port 9

RP9

WP9D

Reset

P9 DDR

WP9

Reset

P9 DR

Internal data bus

SCI

Output

enable

Serial

transmit

data

Guard time

Hardware

standby

Figure C.9 (b) Port 9 Block Diagram (Pin P91)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 874 of 910

REJ09B0258-0300

WP9D:

WP9:

RP9:

Write to P9DDR

Write to port 9

Read port 9

WP9D

Reset

P9 DDR

WP9

Reset

P9 DR

RP9

Internal data bus

Input enable

Serial receive

data

SCI

Hardware standby

Figure C.9 (c) Port 9 Block Diagram (Pin P92)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 875 of 910

REJ09B0258-0300

DDR

WP9D

RP9

Serial receive data

Input enable

Write to P9DDR

Write to port 9

Read port 9

WP9D:

WP9:

RP9:

WP9

Reset

Internal data bus

Reset

SCI

Hardware standby

Figure C.9 (d) Port 9 Block Diagram (Pin P93)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 876 of 910

REJ09B0258-0300

WP9D:

WP9:

RP9:

Write to P9DDR

Write to port 9

Read port 9

WP9D

Reset

P9 DDR

WP9

Reset

P9 DR

RP9

Internal data bus

SCI

Clock input

enable

Clock outpu

enable

Clock outpu

Clock input

Interrupt

controller

inputIRQ

Hardware standby

Figure C.9 (e) Port 9 Block Diagram (Pin P94)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 877 of 910

REJ09B0258-0300

DDR

Reset

WP9D

WP9

RP9

Reset

SCI

Clock input

enable

Clock output

enable

Clock output

Interrupt controller

IRQ

input

Clock input

: Write to P9DDR

: Write to port 9

: Read port 9

WP9D

WP9

RP9

Internal data bus

Hardware standby

Figure C.9 (f) Port 9 Block Diagram (Pin P95)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 878 of 910

REJ09B0258-0300

C.10 Port A Block Diagrams

WPAD:

WPA:

RPA:

n = 0 and 1

Write to PADDR

Write to port A

Read port A

WPAD

Reset

PA DDR

Reset

PA DR

RPA

WPA

Internal data bus

TPC

output

enable

TPC

Next data

Output

trigger

Output

enable

Transfer

end output

DMA controlle

Counter

clock input

16-bit timer

Counter

clock input

8-bit timer

Hardware standby

Figure C.10 (a) Port A Block Diagram (Pins PA0, PA1)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 879 of 910

REJ09B0258-0300

WPAD:

WPA:

RPA:

n = 2 and 3

Write to PADDR

Write to port A

Read port A

RPA

WPA

WPAD

Reset

PA DDR

Reset

PA DR

Internal data bus

TPC

output

enable

TPC

data

Output

trigger

Output

enable

Compare

match

output

Input

capture

Counter

clock

input

16-bit timer

Counter

clock input

8-bit timer

Hardware standby

Figure C.10 (b) Port A Block Diagram (Pins PA2, PA3)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 880 of 910

REJ09B0258-0300

WPAD:

WPA:

RPA:

SSOE:

n = 4 to 7

Note: The PA

address output enable setting is fixed at 1 in modes 3 and 4.

Write to PADDR

Write to port A

Read port A

Software standby output port enable

WPAD

Reset

PRA

WPA

DDR

Reset

Internal address bus

Internal data bus

TPC

16-bit timer

TPC output

enable

Next data

Output trigger

Output enable

Compare match

output

Input capture

Software standby

SSOE

Bus released

Mode 3/4

Address output enable

Hardware

standby

Figure C.10 (c) Port A Block Diagram (Pins PA4 to PA7)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 881 of 910

REJ09B0258-0300

C.11 Port B Block Diagrams

WPBD:

WPB:

RPB:

SSOE:

Write to PBDDR

Write to port B

Read port B

Software standby output port enable

Reset

PB DDR

WPBD

Reset

PB DR

WPB

RPB

Internal data bus

TPC output

enable

TPC

Next data

Output trigger

Output enable

Compare

match output

8-bit timer

Mode

1 to 5

Bus released

Bus controller

CS output enable

CS7

output

Software

standby

SSOE

Hardware standby

Figure C.11 (a) Port B Block Diagram (Pin PB0)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 882 of 910

REJ09B0258-0300

DDR

Reset

Mode

1 to 5

WPBD

WPB

RPB

Reset

TPC

8-bit timer

TPC output enable

Bus controller

CS output enable

CS6 output

Next data

Output trigger

Output enable

Compare match output

DMAC

DREQ0

DREQ1 input

TMO2

TMO3 input

Write to PBDDR

Write to port B

Read port B

Software standby output port enable

WPBD:

WPB:

RPB:

SSOE:

Bus released

Software standby

SSOE

Internal data bus

Hardware

standby

Figure C.11 (b) Port B Block Diagram (Pin PB1)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 883 of 910

REJ09B0258-0300

DDR

Reset

WPBD

WPB

RPB

Reset

TPC

8-bit timer

TPC output enable

Bus controller

RAS

output enable

RAS

output

output enable

Area 5 DRAM connection

output enable

Next data

Output trigger

Output enable

Compare match output

Write to PBDDR

Write to port B

Read port B

Software standby output port enable

WPBD:

WPB:

RPB:

SSOE:

Internal data bus

Software standby

External bus release

SSOE

Hardware

standby

Mode

6/7

Figure C.11 (c) Port B Block Diagram (Pin PB2)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 884 of 910

REJ09B0258-0300

PB2DDR

Reset

WPBD

WPB

RPB

PB2DR

Reset

PB3

TPC

8-bit timer

TMIO3 input

DREQ1 input

DMAC

TPC output enable

Bus controller

RAS5 output enable

RAS5 output

CS5 output

CS5 output enable

Area 5 DRAM connection

output enable

Next data

Output trigger

Output enable

Compare match output

Write to PBDDR

Write to port B

Read port B

Software standby output port enable

WPBD:

WPB:

RPB:

SSOE:

Internal data bus

Software standby

External bus release

SSOE

Hardware

standby

Mode

6/7

Figure C.11 (d) Port B Block Diagram (Pin PB3)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 885 of 910

REJ09B0258-0300

WPBD:

WPB:

RPB:

SSOE:

Write to PBDDR

Write to port B

Read port B

Software standb

output port enable

Note: In modes 6 and 7, CAS output enable is fixed at 0.

WPB

RPB

Reset

Hardware standby

External bus release

SSOE

Software standby

PB DDR

WPBD

Reset

PB DR

Internal data bus

TPC output

enable

Next data

Output trigger

Output enable

CAS output

TPC

Bus controller

Figure C.11 (e) Port B Block Diagram (Pin PB4)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 886 of 910

REJ09B0258-0300

DDR

Reset

WPBD

WPB

RPB

Reset

TPC

SCI

TPC output enable

SCI

Next data

Output trigger

Clock output

enable

Clock input

enable

Clock output

Clock input

Write to PBDDR

Write to port B

Read port B

Software standby output port enable

Bus controller

CAS output enable

CAS output

WPBD:

WPB:

RPB:

SSOE:

Internal data bus

Hardware

standby

External bus release

SSOE

Software standby

Note: In modes 6 and 7, CAS output enable is fixed at 0.

Figure C.11 (f) Port B Block Diagram (Pin PB5)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 887 of 910

REJ09B0258-0300

WPBD

Reset

Hardware standby

Reset

PB DDR

PB DR

RPB

WPB

TPC

SCI

WPBD:

WPB:

RPB:

Write to PBDDR

Write to port B

Read port B

TPC

output

enable

Next data

Output

trigger

Output enable

Serial transmit data

Guard time

Internal data bus

PB6

Figure C.11 (g) Port B Block Diagram (Pin PB6)

Appendix C I/O Port Block Di agrams

Rev. 3.00 Sep 14, 2005 page 888 of 910

REJ09B0258-0300

WPBD

Reset

PB DDR

PB DR

RPB

WPB

SCI

TPC

SCI

WPBD:

WPB:

RPB:

Write to PBDDR

Write to port B

Read port B

TPC

output

enable

Input enable

Next data

Output

trigger

Internal data bus

Serial receive

data

Hardware standby

Figure C.11 (h) Port B Block Diagram (Pin PB7)

Appendix D Pin States

Rev. 3.00 Sep 14, 2005 page 889 of 910

REJ09B0258-0300

Appendix D Pin States

D.1 Port States in Each Mode

Table D.1 Port States

Name Mode Reset

Hardware

Standby

Mode Software Standby

Mode Bus-Released

Mode Program Execution

Mode

P17 to

P10

1 to 4 L T (SSOE=0)

(SSOE=1)

Keep

7 to A0

5 T T (DDR = 0)

Keep

(DDR=1, SSOE=0)

(DDR=1, SSOE=1)

Keep

T (DDR=0)

Input port

(DDR=1)

A7 to A0

6, 7 T T Keep — I/O port

P27 to

P20

1 to 4 L T (SSOE = 0)

(SSOE = 1)

Keep

15 to A8

5 T T (DDR = 0)

Keep

(DDR=1,SSOE=0)

(DDR=1,SSOE=1)

Keep

T (DDR=0)

Input port

(DDR=1)

A15 to A8

6, 7 T T Keep — I/O port

P37 to

P30

1 to 5 T T T T D15 to D8

6, 7 T T Keep — I/O port

P47 to

P40

1, 3, 5 T T Keep Keep I/O port

2, 4TTTTD

7 to D0

6, 7 T T Keep — I/O port

Appendix D Pin States

Rev. 3.00 Sep 14, 2005 page 890 of 910

REJ09B0258-0300

Name Mode Reset

Hardware

Standby

Mode Software Standby

Mode Bus-Released

Mode Program Execution

Mode

P53 to

P50

1 to 4 L T (SSOE=0)

(SSOE=1)

Keep

19 to A16

5 T T (DDR=0)

Keep

(DDR=1, SSOE=0)

(DDR=1, SSOE=1)

Keep

T (DDR=0)

Input port

(DDR=1)

A19 to A16

6, 7 T T Keep — I/O port

P601 to 5 T T Keep Keep I/O port

WAIT

6, 7 T T Keep — I/O port

P611 to 5 T T (BRLE=0)

Keep

(BRLE=1)

T I/O port

BREQ

6, 7 T T Keep — I/O port

P621 to 5 T T (BRLE=0)

Keep

(BRLE=1)

L(BRLE=0)

I/O port

(BRLE=1)

BACK

6, 7 T T Keep — I/O port

P66 to

P63

1 to 5 H T (SSOE=0)

(SSOE=1)

HWR

LWR

6, 7 T T Keep — I/O port

P671 to 7 Clock

output T (PSTOP=0)

(PSTOP=1)

Keep

(PSTOP=0)

(PSTOP=1)

Keep

(PSTOP=0)

(PSTOP=1)

Input port

P77 to

P70

1 to 7 T T T T Input port

Appendix D Pin States

Rev. 3.00 Sep 14, 2005 page 891 of 910

REJ09B0258-0300

Name Mode Reset

Hardware

Standby

Mode Software Standby

Mode Bus-Released

Mode Program Execution

Mode

P801 to 5 T T When DRAM space is

not selected*1

(RFSHE=0)

Keep

(RFSHE=1)

Illega l s etting

When DRAM space is

selected*2

(RFSHE=0)

Keep

(RFSHE=1 , SRFMD=0,

SSOE=0)

(RFSHE=1 , SRFMD=0,

SSOE=1)

(RFSHE=1 , SRFMD=1)

RFSH

When DRAM space is

selected*1

(RFSHE=0)

Keep

(RFSHE=1)

Illega l s etting

When DRAM space is

selected*2

(RFSHE=0)

Keep

(RFSHE=1)

(RFSHE=0)

I/O port

(RFSHE=1)

RFSH

6, 7 T T Keep — I/O port

P811 to 5 T T When DRAM space is

selected*3

(SSOE=0)

(SSOE=1)

When DRAM space is

selected*4

Keep

Otherwise*5 *1

(DDR=0)

(DDR=1, SSOE=0)

(DDR=1, SSOE=1)

When DRAM space is

selected*3

When DRAM space is

selected*4

Keep

Otherwise*1

(DDR=0)

Keep

(DDR=1)

When DRAM space is

selected and RAS3 is

output

RAS

When DRAM space is

selected and RAS3 is

not output

I/O port

Otherwise

(DDR=0)

Input port

(DDR=1)

6, 7 T T Keep — I/O port

Appendix D Pin States

Rev. 3.00 Sep 14, 2005 page 892 of 910

REJ09B0258-0300

Name Mode Reset

Hardware

Standby

Mode Software Standby

Mode Bus-Released

Mode Program Execution

Mode

P821 to 5 T T RAS2 output*2

(SSOE=0)

(SSOE=1)

Otherwise*1

(DDR=0)

(DDR=1, SSOE=0)

(DDR=1, SSOE=1)

RAS2 output*2

Otherwise*1

(DDR=0)

Keep

(DDR=1)

RAS2 output

RAS

Otherwise

(DDR=0)

I/O port

(DDR=1)

6, 7 T T Keep — I/O port

P831 to 5 T T (DDR=0)

(DDR=1, SSOE=0)

(DDR=1, SSOE=1)

(DDR=0)

Keep

(DDR=1)

(DDR=0)

Input port

(DDR=1)

6, 7 T T Keep — I/O port

P841 to 4 H T (DDR=0)

(DDR=1, SSOE=0)

(DDR=1, SSOE=1)

(DDR = 0)

Keep

(DDR = 1)

(DDR = 0)

Input port

(DDR = 1)

5 T T (DDR=0)

(DDR=1, SSOE=0)

(DDR=1, SSOE=1)

(DDR=0)

Keep

(DDR=1)

(DDR=0)

Input port

(DDR=1)

6, 7 T T Keep — I/O port

P95 to

P90

1 to 7 T T Keep Keep I/O port

PA3 to

PA0

1 to 7 T T Keep Keep I/O port

PA6 to

PA4

1, 2, 6,

7T T Keep Keep I/O port

Appendix D Pin States

Rev. 3.00 Sep 14, 2005 page 893 of 910

REJ09B0258-0300

Name Mode Reset

Hardware

Standby

Mode Software Standby

Mode Bus-Released

Mode Program Execution

Mode

PA6 to

PA4

3 to 5 T T Address output*5

(SSOE=0)

(SSOE=1)

Keep

Otherwise*6

Keep

Address output*5

Otherwise*6

Keep

Address output

A23 to A21

Otherwise

I/O port

PA71, 2 T T Keep Keep I/O port

3, 4 L T (SSOE=0)

(SSOE=1)

Keep

5 L T When A20E = 0

SSOE = 0

SSOE = 1

Keep

When A20E = 1

Keep

When A20E = 0

When A20E = 1

Keep

When A20E = 0

A20

When A20E = 1

I/O port

6, 7 T T Keep — I/O port

PB1 to

PB0

1 to 5 T T CS output*7

(SSOE=0)

(SSOE=1)

Otherwise*8

Keep

CS output*7

Otherwise*8

Keep

CS output

7 to

Otherwise

I/O port

6, 7 T T Keep — I/O port

PB21 to 5 T T RAS5 output*9

(SSOE=0)

(SSOE=1)

CS output*10

(SSOE=0)

(SSOE=1)

Otherwise*11

Keep

RAS5 output*9

CS output*10

Otherwise*11

Keep

RAS5 output

RAS5

CS output

CS5

Otherwise

I/O port

6, 7 T T Keep — I/O port

Appendix D Pin States

Rev. 3.00 Sep 14, 2005 page 894 of 910

REJ09B0258-0300

Name Mode Reset

Hardware

Standby

Mode Software Standby

Mode Bus-Released

Mode Program Execution

Mode

PB31 to 5 T T RAS4 output*12

(SSOE=0)

(SSOE=1)

CS output*13

(SSOE=0)

(SSOE=1)

Otherwise*14

Keep

RAS4 output*12

CS output*13

Otherwise*14

Keep

RAS4 output

RAS4

CS output

CS4

Otherwise

I/O port

6, 7 T T Keep — I/O port

PB5 to

PB4

1 to 5 T T CAS output*15

(SSOE=0)

(SSOE=1)

Otherwise*16

Keep

CAS output*15

Otherwise*16

Keep

CAS output

UCAS

LCAS

Otherwise

I/O port

6, 7 T T Keep — I/O port

PB7 to

PB6

1 to 7 T T Keep Keep I/O port

Legend

H: High

L: Low

T: High-impedance state

Keep: Input pins are in the high-impedance state; output pins maintain their previous state.

DDR: Data d irection register

Notes: 1. When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all

cleared to 0.

2. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is

set to 1.

3. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control

4. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control

5. When bit A23E, A22E, or A21E, respectively, i n BRCR (bus release control register)

is cleared to 0.

6. When bit A23E, A22E, or A21E, respectively, i n BRCR (bus release control register)

is set to 1.

7. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to

Appendix D Pin States

Rev. 3.00 Sep 14, 2005 page 895 of 910

REJ09B0258-0300

8. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is

cleared to 0.

9. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control

10. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control

set to 1.

11. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control

cleared to 0.

12. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control

13. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control

14. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control

15. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is

set to 1, and bit CSEL in DRCRB (DRAM control register B) is cleared to 0.

16. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is

set to 1, and bit CSEL in DRCRB (DRAM control register B) is set to 1; or, when bits

DRAS2, DRAS1, and DRAS0 are all cleared to 0.

Appendix D Pin States

Rev. 3.00 Sep 14, 2005 page 896 of 910

REJ09B0258-0300

D.2 Pin States at Reset

Modes 1 and 2: Figure D.1 is a timing diagram for the case in which

RES

goes low during an

external memory access in mode 1 or 2. As soon as

RES

goes low, all ports are initialized to the

input state.

HWR

LWR

, and

0 go high, and D15 to D0 go to the high-impedance state.

The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of

RES

is sampled. Clock pin P67/φ goes to the output state at the next rise of φ after

RES

goes low.

AS, RD

(read)

to D

(write)

HWR, LWR

(write)

Internal reset

signal

RES

/φ

I/O port,

to CS

to A

T1 T2 T3

Access to external

memory

H'00000

High impedance

Figure D.1 Reset during Memory Access (Modes 1 and 2)

Modes 3 and 4: Figure D.2 is a timing diagram for the case in which

RES

goes low during an

external memory access in mode 3 or 4. As soon as

RES

goes low, all ports are initialized to the

input state.

HWR

LWR

, and

0 go high, and D15 to D0 go to the high-impedance state.

The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of

RES

is sampled. However, when PA4 to PA6 are used as address bus pins, or when P83 to P81 and PB0

Appendix D Pin States

Rev. 3.00 Sep 14, 2005 page 897 of 910

REJ09B0258-0300

to PB3 are used as CS output pins, they go to the high-impedance state at the same time as

RES

goes low. Clock pin P67/φ goes to the output state at the next rise of φ after

RES

goes low.

T1 T2 T3

Access to external

memory

H'000000

High impedance

AS, RD

(read)

to D

(write)

HWR, LWR

(write)

Internal reset

signal

RES

/φ

I/O port,

to PA

to CS

to A

Figure D.2 Reset during Memory Access (Modes 3 and 4)

Mode 5: Figure D.3 is a timing diagram for the case in which

RES

goes low during an external

memory access in mode 5. As soon as

RES

goes low, all ports are initialized to the input state.

HWR

, and

LWR

go high, and the address bus and D15 to D0 go to the high-impedance

state. Clock pin P67/φ goes to the output state at the next rise of φ after

RES

goes low.

Appendix D Pin States

Rev. 3.00 Sep 14, 2005 page 898 of 910

REJ09B0258-0300

T1 T2 T3

Access to external

memory

High impedance

AS, RD

(read)

D15 to D0

(write)

HWR, LWR

(write)

Internal reset

signal

RES

P67/φ

I/O port,

CS7 to CS1

A23 to A0

Figure D.3 Reset during Memory Access (Mode 5)

Modes 6 and 7: Figure D.4 is a timing diagram for the case in which

RES

goes low during an

operation in mode 6 or 7. As soon as

RES

goes low, all ports are initialized to the input state.

Clock pin P67/φ goes to the output state at the next rise of φ after

RES

goes low.

Internal reset

signal

RES

/φ

I/O port High impedance

Figure D.4 Reset during Operation (Modes 6 and 7)

Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

Rev. 3.00 Sep 14, 2005 page 899 of 910

REJ09B0258-0300

Appendix E Timing of Transition to and Recovery from

Hardware Standby Mode

Timing of Transition to Hardware Standby Mode

1. To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the

RES

signal low 10

system clock cycles before the

STBY

signal goes low, as shown below.

RES

must remain low

until

STBY

goes low (minimum delay from

STBY

low to

RES

high: 0 ns).

≥ 10t

cyc

≥ 0 ns

STBY

RES

2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR,

RES

does not have to be

driven low as in (1).

Timing of Recovery from Hardware Standby Mode: Drive the

RES

signal low approximately

100 ns before

STBY

goes high.

STBY

RES

t≥100 ns t

OSC

Appendix D Pin States

Rev. 3.00 Sep 14, 2005 page 900 of 910

REJ09B0258-0300

Appendix F Product Code Lineup

Product Type Product Code Mark Code Package

(Package Code)

H8/3068F On-chip flash 5 V HD64F3068F HD64F3068F 100-pin QFP (FP-100B)

memory HD64F3068TE HD64F3068TE 100-pin TQFP (TFP-100B)

Appendix G Package Dimensions

Rev. 3.00 Sep 14, 2005 page 901 of 910

REJ09B0258-0300

Appendix G Package Dimensio ns

Figures G.1 show the FP-100B package dimensions of the H8/3067 Group. Figure G.2 shows the

TFP-100B package dimensions. Figure G.3 shows the FP-100A package dimentions.

NOTE)

1. DIMENSIONS"*1"AND"*2"

DO NOT INCLUDE MOLD FLASH

2. DIMENSION"*3"DOES NOT

INCLUDE TRIM OFFSET.

*3p

100

12 5

75 51

xMy

Terminal cross section

Detail F

PRQP0100KA-AP-QFP100-14x14-0.50

1.0

0.08

0.10

0.5

0.250.12

0.15

0.20

0.00

0.270.220.17

0.220.170.12

3.05

16.316.015.7

MASS[Typ.]

1.2gFP-100B/FP-100BV

RENESAS CodeJEITA Package Code Previous Code

0.70.50.3

MaxNomMin

Dimension in Millimeters

Symbol

Reference

2.70

16.316.015.7

1.0

Figure G.1 Package Dimensions (FP-100B)

Appendix G Package Dimensions

Rev. 3.00 Sep 14, 2005 page 902 of 910

REJ09B0258-0300

NOTE)

1. DIMENSIONS"*1"AND"*2"

DO NOT INCLUDE MOLD FLASH

2. DIMENSION"*3"DOES NOT

INCLUDE TRIM OFFSET.

PTQP0100KA-AP-TQFP100-14x14-0.50

1.00

0.08

0.10

0.5

15.8 16.0 16.2

0.15

0.20

1.20

0.200.100.00

0.270.220.17

0.220.170.12

MASS[Typ.]

0.5gTFP-100B/TFP-100BV

RENESAS CodeJEITA Package Code Previous Code

0.60.50.4

MaxNomMin

Dimension in Millimeters

Symbol

Reference

1.00

16.216.015.8

1.0

Index mark

*3p

100

xMy

Detail F

Terminal cross section

Figure G.2 Package Dimensions (TFP-100B)

Appendix H Comparison of H8/300H Series Product Specifications

Rev. 3.00 Sep 14, 2005 page 903 of 910

REJ09B0258-0300

Appendix H Comparison of H 8/300H Series Pro duct

Specifications

H.1 Differences between H8/3068F and H8 /3067 Group and

H8/3062 Group, H8/3048 Group

Item H8/3068F H8/3067 Group,

H8/3062 Group H8/3048

Group

1Operating

mode Mode 5 16 Mbytes ROM enabled

expanded mode 16 Mbytes ROM enabled

expanded mode 1 Mbyte ROM

enabled

expanded

mode

Mode 6 64 kbytes single-chip mode 64 kbytes single-chip mode 16 Mbyte

ROM enabled

expanded

mode

2 Interrupt

controller Internal interrupt

sources 36 36 (H8/3067)

27 (H8/3062)

3Bus

controller Burst ROM

interface Yes Yes (H8/3067)

No (H8/3062)

Idle cycle insertio n

function Yes Yes No

Wait mode 2 modes 2 modes 4 modes

Wait state

number setting Per area Per area Common

to all areas

Address output

method Choice of address

update fixed Choice of address update

mode (mask ROM and flash

memory R versions only)

Fixed

4 DRAM

interface Connectable

areas Area 2/3/4/5 Area 2/3/4/5

(H8/3067 only) Area 3

Precharge cycle

insertion function Yes Yes (H8/3067 only) No

Fast page mode Yes Yes (H8/3067 only) No

Address shift

amount 8 bit/9 bit/10 bit 8 bit/9 bit/10 bit

(H8/3067 only) 8 bit/9 bit

Appendix H Comparison of H8/300H Series Product Specifications

Rev. 3.00 Sep 14, 2005 page 904 of 910

REJ09B0258-0300

Item H8/3068F H8/3067 Group,

H8/3062 Group H8/3048

Group

5 Timer functions 16-bit

timers 8-bit

timers 16-bit

timers 8-bit

timers ITU

Number of

channels 16 bits × 3 8 bits × 4

(16 bits × 2) 16 bits × 3 8 bits × 4

(16 bits × 2) 16 bits × 5

Pulse output 6 pins 4 pins

(2 pins) 6 pins 4 pins

(2 pins) 12 pins

Input capture 6 2 6 2 10

External clock 4 systems

(selectable) 4 systems

(fixed) 4 sy st ems

(selectable) 4 systems

(fixed) 4 sy st ems

(selectable)

Internal clock φ, φ/2, φ/4,

φ/8 φ/8, φ/64,

φ/8192 φ, φ/2, φ/4,

φ/8 φ/8, φ/64,

φ/8192 φ, φ/2, φ/4,

φ/8

Complementary

PWM function No No No No Yes

Reset-

synchronous

PWM function

No No No No Yes

Buffer operation No No No No Yes

Output

initialization

function

Yes No Yes No No

PWM output 3 4 (2) 3 4 (2) 5

DMAC activation 3 channels No 3 channels

(H8/3067

only)

No 4 channels

A/D conversion

activation No Yes No Yes No

Inte rrupt sou rce s 3 sources

× 3 8 sources 3 sources

× 5

6 TPC Time base 3 kinds, 16-bit timer

base 3 kinds, 16-bit timer

base 4 kinds,

ITU base

7 WDT Reset s ign al

external output

function

No Yes (except products

with on-chip flash memory) Yes

8 SCI Number of

channels 3 channels 3 channels (H8/3067)

2 channels (H8/3062)

2 channels

Smart card

interface Supported on all channels Supported on all channels Supported

on SCI0 only

Appendix H Comparison of H8/300H Series Product Specifications

Rev. 3.00 Sep 14, 2005 page 905 of 910

REJ09B0258-0300

Item H8/3068F H8/3067 Group,

H8/3062 Group H8/3048

Group

9A/D

converter Conversion start

trigger input External trigger/8-bit timer

compare match External trigger/8-bit timer

compare match External

trigger

10 Pin

control φ pin φ/input port multiplexing φ/input port multiplexing φ output

only

A20 in 16 MB ROM

enabled expanded

mode

A20 / I/O port multiplexing A20 / I/O port multiplexing A20 output

Address bus,

HWR

LWR

7–

RFSH

in software

standby state

High-level o utput/h igh -

impedance selectable High-level output/ high-

impedance selectable

(

RFSH

: H8/3067 only)

High-level

output (except

Low-level

output (

7–

0 in bus-

released state High-impedance High-impedance High-level

output

11 Flash

memory

functions

Program/erase

voltage 12 V application

unnecessary.

Single-power-supply

programming.

12 V application

unnecessary.

Single-power-supply

programming.

12 V

application

from off-chip

Block divisions 14 blocks 8 blocks 16 blocks

Appendix H Comparison of H8/300H Series Product Specifications

Rev. 3.00 Sep 14, 2005 page 906 of 910

REJ09B0258-0300

H.2 Comparison of Pin Functions of 100-Pin Package Products

(FP-100B, TFP-100B)

Table H.1 Pin Arrangement of Each Product (FP-100B, TFP-100B)

Pin No. H8/3068F H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group

CL VCC VCC/VCL VCC VCC

2PB0/TP8/TMO0/

PB0/TP8/TMO0/

PB0/TP8/

TIOCA3

PB0/TP8/

TIOCA3

3PB1/TP9/TMIO1/

DREQ

PB1/TP9/TMIO1/

DREQ

PB1/TP9/TMIO1/

PB1/TP9/

TIOCB3

PB1/TP9/

TIOCB3

4PB2/TP10/TMO2/

PB2/TP10/TMO2/

PB2/TP10/

TIOCA4

PB2/TP10/

TIOCA4

5PB3/TP11/TMIO3/

DREQ

PB3/TP11/TMIO3/

DREQ

PB3/TP11/TMIO3/

PB3/TP11/TIOCB4PB3/TP11/TIOCB4

6PB4/TP12/

UCAS

PB4/TP12/

UCAS

PB4/TP12 PB4/TP12/TOCXA4PB4/TP12/TOCXA4

7PB5/TP13/

LCAS

SCK2

PB5/TP13/

LCAS

SCK2

PB5/TP13 PB5/TP13/TOCXB4PB5/TP13/TOCXB4

8PB6/TP14/TxD2PB6/TP14/TxD2PB6/TP14 PB6/TP14/

DREQ

PB6/TP14/

DREQ

9PB7/TP15/RxD2PB7/TP15/RxD2PB7/TP15 PB7/TP15/

DREQ

ADTRG

PB7/TP15/

DREQ

ADTRG

10 FWE

RESO

/FWE*

RESO

/FWE*

RESO

/VPP*

RESO

11 Vss Vss Vss Vss Vss

12 P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0

13 P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1

14 P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0

15 P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1

16 P94/SCK0/

IRQ

4P94/SCK0/

IRQ

4P94/SCK0/

IRQ

4P94/SCK0/

IRQ

4P94/SCK0/

IRQ

17 P95/SCK1/

IRQ

5P95/SCK1/

IRQ

5P95/SCK1/

IRQ

5P95/SCK1/

IRQ

5P95/SCK1/

IRQ

18 P40/D0P40/D0P40/D0P40/D0P40/D0

19 P41/D1P41/D1P41/D1P41/D1P41/D1

20 P42/D2P42/D2P42/D2P42/D2P42/D2

21 P43/D3P43/D3P43/D3P43/D3P43/D3

22 Vss Vss Vss Vss Vss

23 P44/D4P44/D4P44/D4P44/D4P44/D4

24 P45/D5P45/D5P45/D5P45/D5P45/D5

25 P46/D6P46/D6P46/D6P46/D6P46/D6

26 P47/D7P47/D7P47/D7P47/D7P47/D7

Appendix H Comparison of H8/300H Series Product Specifications

Rev. 3.00 Sep 14, 2005 page 907 of 910

REJ09B0258-0300

Pin No. H8/3068F H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group

27 P30/D8P30/D8P30/D8P30/D8P30/D8

28 P31/D9P31/D9P31/D9P31/D9P31/D9

29 P32/D10 P32/D10 P32/D10 P32/D10 P32/D10

30 P33/D11 P33/D11 P33/D11 P33/D11 P33/D11

31 P34/D12 P34/D12 P34/D12 P34/D12 P34/D12

32 P35/D13 P35/D13 P35/D13 P35/D13 P35/D13

33 P36/D14 P36/D14 P36/D14 P36/D14 P36/D14

34 P37/D15 P37/D15 P37/D15 P37/D15 P37/D15

35 Vcc Vcc Vcc Vcc Vcc

36 P10/A0P10/A0P10/A0P10/A0P10/A0

37 P11/A1P11/A1P11/A1P11/A1P11/A1

38 P12/A2P12/A2P12/A2P12/A2P12/A2

39 P13/A3P13/A3P13/A3P13/A3P13/A3

40 P14/A4P14/A4P14/A4P14/A4P14/A4

41 P15/A5P15/A5P15/A5P15/A5P15/A5

42 P16/A6P16/A6P16/A6P16/A6P16/A6

43 P17/A7P17/A7P17/A7P17/A7P17/A7

44 Vss Vss Vss Vss Vss

45 P20/A8P20/A8P20/A8P20/A8P20/A8

46 P21/A9P21/A9P21/A9P21/A9P21/A9

47 P22/A10 P22/A10 P22/A10 P22/A10 P22/A10

48 P23/A11 P23/A11 P23/A11 P23/A11 P23/A11

49 P24/A12 P24/A12 P24/A12 P24/A12 P24/A12

50 P25/A13 P25/A13 P25/A13 P25/A13 P25/A13

51 P26/A14 P26/A14 P26/A14 P26/A14 P26/A14

52 P27/A15 P27/A15 P27/A15 P27/A15 P27/A15

53 P50/A16 P50/A16 P50/A16 P50/A16 P50/A16

54 P51/A17 P51/A17 P51/A17 P51/A17 P51/A17

55 P52/A18 P52/A18 P52/A18 P52/A18 P52/A18

56 P53/A19 P53/A19 P53/A19 P53/A19 P53/A19

57 Vss Vss Vss Vss Vss

58 P60/

WAIT

P60/

WAIT

P60/

WAIT

P60/

WAIT

P60/

WAIT

59 P61/

BREQ

P61/

BREQ

P61/

BREQ

P61/

BREQ

P61/

BREQ

60 P62/

BACK

P62/

BACK

P62/

BACK

P62/

BACK

P62/

BACK

61 P67/φP67/φP67/φ φ φ

Appendix H Comparison of H8/300H Series Product Specifications

Rev. 3.00 Sep 14, 2005 page 908 of 910

REJ09B0258-0300

Pin No. H8/3068F H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group

STBY STBY STBY STBY STBY

RES RES RES RES RES

64 NMI NMI NMI NMI NMI

65 Vss Vss Vss Vss Vss

66 EXTAL EXTAL EXTAL EXTAL EXTAL

67 XTAL XTAL XTAL XTAL XTAL

68 Vcc Vcc Vcc Vcc Vcc

69 P63/

P63/

70 P64/

P64/

71 P65/

HWR

P65/

HWR

P65/

HWR

P65/

HWR

P65/

HWR

72 P66/

LWR

P66/

LWR

P66/

LWR

P66/

LWR

P66/

LWR

73 MD0MD0MD0MD0MD0

74 MD1MD1MD1MD1MD1

75 MD2MD2MD2MD2MD2

76 AVcc AVcc AVcc AVcc AVcc

77 VREF VREF VREF VREF VREF

78 P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0

79 P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1

80 P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2

81 P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3

82 P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4

83 P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5

84 P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0

85 P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1

86 AVss AVss AVss AVss AVss

87 P80/

RFSH

IRQ

0P80/

RFSH

IRQ

0P80/

IRQ

0P80/

RFSH

IRQ

0P80/

RFSH

IRQ

88 P81/

IRQ

1P81/

IRQ

1P81/

IRQ

1P81/

IRQ

1P81/

IRQ

89 P82/

IRQ

2P82/

IRQ

2P82/

IRQ

2P82/

IRQ

2P82/

IRQ

90 P83/

IRQ

ADTRG

P83/

IRQ

ADTRG

P83/

IRQ

ADTRG

P83/

IRQ

3P83/

IRQ

91 P84/

0P84/

92 Vss Vss Vss Vss Vss

93 PA0/TP0/

TEND

TCLKA PA0/TP0/

TEND

TCLKA PA0/TP0/TCLKA PA0/TP0/

TEND

TCLKA PA0/TP0/

TEND

TCLKA

94 PA1/TP1/

TEND

TCLKB PA1/TP1/

TEND

TCLKB PA1/TP1/TCLKB PA1/TP1/

TEND

TCLKB PA1/TP1/

TEND

TCLKB

Appendix H Comparison of H8/300H Series Product Specifications

Rev. 3.00 Sep 14, 2005 page 909 of 910

REJ09B0258-0300

Pin No. H8/3068F H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group

95 PA2/TP2/TIOCA0/

TCLKC PA2/TP2/TIOCA0/

TCLKC

96 PA3/TP3/TIOCB0/

TCLKD PA3/TP3/TIOCB0/

TCLKD

97 PA4/TP4/TIOCA1/

A23

PA4/TP4/TIOCA1/

A23

PA4/TP4/TIOCA1/

A23

PA4/TP4/TIOCA1/

6/A23

PA4/TP4/TIOCA1/

A23

98 PA5/TP5/TIOCB1/

A22

PA5/TP5/TIOCB1/

A22

PA5/TP5/TIOCB1/

A22

PA5/TP5/TIOCB1/

5/A22

PA5/TP5/TIOCB1/

A22

99 PA6/TP6/TIOCA2/

A21

PA6/TP6/TIOCA2/

A21

PA6/TP6/TIOCA2/

A21

PA6/TP6/TIOCA2/

4/A21

PA6/TP6/TIOCA2/

A21

100 PA7/TP7/TIOCB2/

A20

PA7/TP7/TIOCB2/

A20

PA7/TP7/TIOCB2/

A20

PA7/TP7/TIOCB2/

A20

PA7/TP7/TIOCB2/

A20

Note: *Functions as

RESO

in the mask ROM versions, and as FWE in the flash memory and flash

memory R versions.

Appendix H Comparison of H8/300H Series Product Specifications

Rev. 3.00 Sep 14, 2005 page 910 of 910

REJ09B0258-0300

Renesas 16-Bit Single-Chip Microcomputer

Hardware Manual

H8/3068F-ZTAT



Publication Date: 1st Edition, March, 2001

Rev.3.00, September 14, 2005

Published by: Sales Strat egic Planning Div.

Renesas Technol ogy Corp.

Edited by: Customer Support Department

G lobal Strategic Communic ation Div.

Renesas Solutions Corp.

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.

Renesas Technology America, Inc.

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Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501

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Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900

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7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2730-6071

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Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999

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Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952

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Tel: <65> 6213-0200, Fax: <65> 6278-8001

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Tel: <82> 2-796-3115, Fax: <82> 2-796-2145

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H8/3068F-ZTATTM

REJ09B0258-0300

Hardware Manual