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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. User's Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. TM H8/3068F-ZTAT 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series H8/3068F HD64F3068F, HD64F3068TE Rev.3.00 2005.09 Keep safety first in your circuit designs! 1. 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Rev. 3.00 Sep 14, 2005 page ii of xxii Preface The H8/3068F is a group of high-performance single-chip microcontrollers that integrate system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. The on-chip supporting functions include ROM, RAM, 16-bit timers, 8-bit timers, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a DMA controller (DMAC), and other facilities. The three-channel SCI has been expanded to support the ISO/IEC7816-3 smart card interface. Functions have also been added to reduce power consumption in battery-powered applications: individual modules can be placed in standby, and the frequency of the system clock supplied to the chip can be divided down under software control. The address space is divided into eight areas. The data bus width and access cycle length can be selected independently in each area, simplifying the connection of different types of memory. Seven MCU operating modes (modes 1 to 7) are provided, offering a choice of data bus width and address space size. With these features, the H8/3068F offers easy implementation of compact, high-performance systems. The H8/3068F has an F-ZTATTM* version with on-chip flash memory that can be programmed on-board. This version enables users to respond quickly and flexibly to changing application specifications. This manual describes the H8/3068F hardware. For details of the instruction set, refer to the H8/300H Series Programming Manual. Note: * F-ZTATTM (Flexible ZTAT) is a registered trademark of Renesas Technology Corp. Rev. 3.00 Sep 14, 2005 page iii of xxii Rev. 3.00 Sep 14, 2005 page iv of xxii Main Revisions for this Edition Item Page Revision (See Manual for Details) All All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. Designation for categories changed from "series" to "group" 19.2.1 Connecting 651 a Crystal Resonator Table 19.1 (1) Damping Resistance Value Note amended Note: A crystal resonator between 2 MHz and 25 MHz can be used. If the chip is to be operated at less than 2 MHz, the on-chip frequency divider should be used. (A crystal resonator of less than 2 MHz cannot be used.) "Preliminary" deleted Section 21 Electrical Characteristics 675 to 706 21.1.2 DC Characteristics 677, 678 Table and note amended Table 21.2 DC Characteristics (1) Item Symbol Min Typ Max Normal Current 2 dissipation* operation ICC*4 -- 32 47 (5.0 V) Unit Test Conditions mA f = 20 MHz 37 58 (5.0 V) Sleep mode -- 24 38 (5.0 V) f = 25 MHz mA 29 47 (5.0 V) Module standby mode -- 19 31 (5.0 V) f = 20 MHz f = 25 MHz mA 21 37 (5.0 V) f = 20 MHz f = 25 MHz Standby 3 mode* -- 1.0 10 A Ta -- -- 80 A 50C 50C Flash memory programming/ 5 erasing* -- 37 57 mA f = 20 MHz 42 68 Ta f = 25 MHz Notes: 3. The values are for VRAM VCC < 4.5 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 4. ICC max. (normal operation) = 3.0 (mA) + 0.40 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode) = 3.0 (mA) + 0.32 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode + module standby mode) = 3.0 (mA) + 0.25 (mA/(MHz x V)) x VCC x f The Typ values for power consumption are reference values. 5. Sum of current dissipation in normal operation and current dissipation in program/erase operations. Rev. 3.00 Sep 14, 2005 page v of xxii Item Page 21.1.6 Flash Memory Characteristics 690, 691 Table amended and notes added Table 21.10 Flash Memory Characteristics Revision (See Manual for Details) Item Symbol Min Typ Max Unit 1 2 4 Programming time* * * tP -- 10 200 ms/ 128 bytes Erase time* * * 1 tE -- 100 1200 Reprogramming count NWEC 100*6 10,000*7 -- Times Data retention period tDRP 10*8 -- Years 3 5 -- Notes ms/block Notes: 6. Minimum number of times at which all characteristics are guaranteed after reprogramming. (Reprogramming count from 1 to minimum value is guaranteed.) 7. Reference characteristics at 25C. (This is an indication that reprogramming operations can normally be performed up to this figure.) 8. Data retention characteristics when reprogramming is performed correctly within the specification values, including the minimum data retention period. Rev. 3.00 Sep 14, 2005 page vi of xxii Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1 Overview........................................................................................................................... 1 Block Diagram.................................................................................................................. 6 Pin Description ................................................................................................................. 7 1.3.1 Pin Arrangement.................................................................................................. 7 1.3.2 Pin Functions ....................................................................................................... 8 1.3.3 Pin Assignments in Each Mode ........................................................................... 13 Section 2 CPU ...................................................................................................................... 19 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Differences from H8/300 CPU ............................................................................ CPU Operating Modes...................................................................................................... Address Space................................................................................................................... Register Configuration...................................................................................................... 2.4.1 Overview.............................................................................................................. 2.4.2 General Registers................................................................................................. 2.4.3 Control Registers ................................................................................................. 2.4.4 Initial CPU Register Values................................................................................. Data Formats..................................................................................................................... 2.5.1 General Register Data Formats............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set................................................................................................................... 2.6.1 Instruction Set Overview ..................................................................................... 2.6.2 Instructions and Addressing Modes..................................................................... 2.6.3 Tables of Instructions Classified by Function...................................................... 2.6.4 Basic Instruction Formats .................................................................................... 2.6.5 Notes on Use of Bit Manipulation Instructions ................................................... Addressing Modes and Effective Address Calculation..................................................... 2.7.1 Addressing Modes ............................................................................................... 2.7.2 Effective Address Calculation ............................................................................. Processing States............................................................................................................... 2.8.1 Overview.............................................................................................................. 2.8.2 Program Execution State ..................................................................................... 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Exception-Handling Sequences ........................................................................... 2.8.5 Bus-Released State .............................................................................................. 19 19 20 21 22 23 23 24 25 26 27 27 29 30 30 31 32 41 42 44 44 46 50 50 51 51 53 54 Rev. 3.00 Sep 14, 2005 page vii of xxii 2.9 2.8.6 Reset State ........................................................................................................... 2.8.7 Power-Down State ............................................................................................... Basic Operational Timing ................................................................................................. 2.9.1 Overview.............................................................................................................. 2.9.2 On-Chip Memory Access Timing........................................................................ 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 2.9.4 Access to External Address Space....................................................................... 54 55 56 56 56 57 58 Section 3 MCU Operating Modes .................................................................................. 59 3.1 3.2 3.3 3.4 3.5 3.6 Overview........................................................................................................................... 3.1.1 Operating Mode Selection ................................................................................... 3.1.2 Register Configuration......................................................................................... Mode Control Register (MDCR) ...................................................................................... System Control Register (SYSCR) ................................................................................... Operating Mode Descriptions ........................................................................................... 3.4.1 Mode 1................................................................................................................. 3.4.2 Mode 2................................................................................................................. 3.4.3 Mode 3................................................................................................................. 3.4.4 Mode 4................................................................................................................. 3.4.5 Mode 5................................................................................................................. 3.4.6 Mode 6................................................................................................................. 3.4.7 Mode 7................................................................................................................. Pin Functions in Each Operating Mode ............................................................................ Memory Map in Each Operating Mode ............................................................................ 3.6.1 Note on Reserved Areas ...................................................................................... 59 59 60 61 62 64 64 64 64 65 65 65 65 66 67 67 Section 4 Exception Handling ......................................................................................... 73 4.1 4.2 4.3 4.4 4.5 4.6 Overview........................................................................................................................... 4.1.1 Exception Handling Types and Priority............................................................... 4.1.2 Exception Handling Operation ............................................................................ 4.1.3 Exception Vector Table ....................................................................................... Reset ................................................................................................................................. 4.2.1 Overview.............................................................................................................. 4.2.2 Reset Sequence .................................................................................................... 4.2.3 Interrupts after Reset............................................................................................ Interrupts........................................................................................................................... Trap Instruction ................................................................................................................ Stack Status after Exception Handling.............................................................................. Notes on Stack Usage ....................................................................................................... Rev. 3.00 Sep 14, 2005 page viii of xxii 73 73 73 74 76 76 76 79 80 81 82 83 Section 5 Interrupt Controller .......................................................................................... 85 5.1 5.2 5.3 5.4 5.5 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Block Diagram..................................................................................................... 5.1.3 Pin Configuration................................................................................................. 5.1.4 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 5.2.1 System Control Register (SYSCR) ...................................................................... 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 5.2.3 IRQ Status Register (ISR).................................................................................... 5.2.4 IRQ Enable Register (IER) .................................................................................. 5.2.5 IRQ Sense Control Register (ISCR) .................................................................... Interrupt Sources............................................................................................................... 5.3.1 External Interrupts ............................................................................................... 5.3.2 Internal Interrupts ................................................................................................ 5.3.3 Interrupt Vector Table ......................................................................................... Interrupt Operation ........................................................................................................... 5.4.1 Interrupt Handling Process .................................................................................. 5.4.2 Interrupt Sequence ............................................................................................... 5.4.3 Interrupt Response Time...................................................................................... Usage Notes ...................................................................................................................... 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 5.5.2 Instructions that Inhibit Interrupts ....................................................................... 5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 85 85 86 87 87 88 88 89 96 97 98 99 99 100 100 104 104 109 110 111 111 112 112 Section 6 Bus Controller ................................................................................................... 113 6.1 6.2 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram..................................................................................................... 6.1.3 Pin Configuration................................................................................................. 6.1.4 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 6.2.1 Bus Width Control Register (ABWCR)............................................................... 6.2.2 Access State Control Register (ASTCR) ............................................................. 6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 6.2.4 Bus Release Control Register (BRCR) ................................................................ 6.2.5 Bus Control Register (BCR) ................................................................................ 6.2.6 Chip Select Control Register (CSCR).................................................................. 6.2.7 DRAM Control Register A (DRCRA)................................................................. 6.2.8 DRAM Control Register B (DRCRB) ................................................................. 113 113 115 116 117 118 118 119 120 124 126 129 130 132 Rev. 3.00 Sep 14, 2005 page ix of xxii 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.2.9 Refresh Timer Control/Status Register (RTMCSR) ............................................ 6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 6.2.12 Address Control Register (ADRCR) ................................................................... Operation .......................................................................................................................... 6.3.1 Area Division....................................................................................................... 6.3.2 Bus Specifications ............................................................................................... 6.3.3 Memory Interfaces............................................................................................... 6.3.4 Chip Select Signals .............................................................................................. 6.3.5 Address Output Method....................................................................................... Basic Bus Interface ........................................................................................................... 6.4.1 Overview.............................................................................................................. 6.4.2 Data Size and Data Alignment............................................................................. 6.4.3 Valid Strobes ...................................................................................................... 6.4.4 Memory Areas ..................................................................................................... 6.4.5 Basic Bus Control Signal Timing ........................................................................ 6.4.6 Wait Control ........................................................................................................ DRAM Interface ............................................................................................................... 6.5.1 Overview.............................................................................................................. 6.5.2 DRAM Space and RAS Output Pin Settings ....................................................... 6.5.3 Address Multiplexing .......................................................................................... 6.5.4 Data Bus .............................................................................................................. 6.5.5 Pins Used for DRAM Interface ........................................................................... 6.5.6 Basic Timing........................................................................................................ 6.5.7 Precharge State Control ....................................................................................... 6.5.8 Wait Control ........................................................................................................ 6.5.9 Byte Access Control and CAS Output Pin .......................................................... 6.5.10 Burst Operation.................................................................................................... 6.5.11 Refresh Control.................................................................................................... 6.5.12 Examples of Use .................................................................................................. 6.5.13 Usage Notes......................................................................................................... Interval Timer ................................................................................................................... 6.6.1 Operation ............................................................................................................. Interrupt Sources............................................................................................................... Burst ROM Interface ........................................................................................................ 6.8.1 Overview.............................................................................................................. 6.8.2 Basic Timing........................................................................................................ 6.8.3 Wait Control ........................................................................................................ Idle Cycle.......................................................................................................................... 6.9.1 Operation ............................................................................................................. Rev. 3.00 Sep 14, 2005 page x of xxii 135 136 137 138 139 139 141 142 143 144 146 146 146 147 148 150 157 159 159 159 160 161 162 162 164 165 166 168 174 178 183 186 186 192 192 192 192 193 194 194 6.9.2 Pin States in Idle Cycle........................................................................................ 6.10 Bus Arbiter........................................................................................................................ 6.10.1 Operation ............................................................................................................. 6.11 Register and Pin Input Timing .......................................................................................... 6.11.1 Register Write Timing ......................................................................................... 6.11.2 BREQ Pin Input Timing ...................................................................................... 197 198 198 201 201 202 Section 7 DMA Controller ................................................................................................ 203 7.1 7.2 7.3 7.4 7.5 Overview........................................................................................................................... 7.1.1 Features................................................................................................................ 7.1.2 Block Diagram..................................................................................................... 7.1.3 Functional Overview............................................................................................ 7.1.4 Input/Output Pins................................................................................................. 7.1.5 Register Configuration......................................................................................... Register Descriptions (1) (Short Address Mode).............................................................. 7.2.1 Memory Address Registers (MAR) ..................................................................... 7.2.2 I/O Address Registers (IOAR)............................................................................. 7.2.3 Execute Transfer Count Registers (ETCR).......................................................... 7.2.4 Data Transfer Control Registers (DTCR) ............................................................ Register Descriptions (2) (Full Address Mode) ................................................................ 7.3.1 Memory Address Registers (MAR) ..................................................................... 7.3.2 I/O Address Registers (IOAR)............................................................................. 7.3.3 Execute Transfer Count Registers (ETCR).......................................................... 7.3.4 Data Transfer Control Registers (DTCR) ............................................................ Operation .......................................................................................................................... 7.4.1 Overview.............................................................................................................. 7.4.2 I/O Mode.............................................................................................................. 7.4.3 Idle Mode............................................................................................................. 7.4.4 Repeat Mode........................................................................................................ 7.4.5 Normal Mode....................................................................................................... 7.4.6 Block Transfer Mode ........................................................................................... 7.4.7 DMAC Activation................................................................................................ 7.4.8 DMAC Bus Cycle................................................................................................ 7.4.9 Multiple-Channel Operation ................................................................................ 7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 7.4.11 NMI Interrupts and DMAC ................................................................................. 7.4.12 Aborting a DMAC Transfer................................................................................. 7.4.13 Exiting Full Address Mode.................................................................................. 7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode ......................... Interrupts........................................................................................................................... 203 203 204 205 206 207 208 208 209 210 211 214 214 214 215 217 223 223 225 227 230 234 237 242 244 250 251 252 253 254 255 256 Rev. 3.00 Sep 14, 2005 page xi of xxii 7.6 Usage Notes ...................................................................................................................... 7.6.1 Note on Word Data Transfer ............................................................................... 7.6.2 DMAC Self-Access ............................................................................................. 7.6.3 Longword Access to Memory Address Registers................................................ 7.6.4 Note on Full Address Mode Setup....................................................................... 7.6.5 Note on Activating DMAC by Internal Interrupts ............................................... 7.6.6 NMI Interrupts and Block Transfer Mode ........................................................... 7.6.7 Memory and I/O Address Register Values .......................................................... 7.6.8 Bus Cycle when Transfer is Aborted ................................................................... 7.6.9 Transfer Requests by A/D Converter................................................................... 257 257 257 257 257 258 259 259 260 261 Section 8 I/O Ports .............................................................................................................. 263 8.1 8.2 Overview........................................................................................................................... Port 1................................................................................................................................. 8.2.1 Overview.............................................................................................................. 8.2.2 Register Descriptions........................................................................................... 8.3 Port 2................................................................................................................................. 8.3.1 Overview.............................................................................................................. 8.3.2 Register Descriptions........................................................................................... 8.4 Port 3................................................................................................................................. 8.4.1 Overview.............................................................................................................. 8.4.2 Register Descriptions........................................................................................... 8.5 Port 4................................................................................................................................. 8.5.1 Overview.............................................................................................................. 8.5.2 Register Descriptions........................................................................................... 8.6 Port 5................................................................................................................................. 8.6.1 Overview.............................................................................................................. 8.6.2 Register Descriptions........................................................................................... 8.7 Port 6................................................................................................................................. 8.7.1 Overview.............................................................................................................. 8.7.2 Register Descriptions........................................................................................... 8.8 Port 7................................................................................................................................. 8.8.1 Overview.............................................................................................................. 8.8.2 Register Description ............................................................................................ 8.9 Port 8................................................................................................................................. 8.9.1 Overview.............................................................................................................. 8.9.2 Register Descriptions........................................................................................... 8.10 Port 9................................................................................................................................. 8.10.1 Overview.............................................................................................................. 8.10.2 Register Descriptions........................................................................................... Rev. 3.00 Sep 14, 2005 page xii of xxii 263 266 266 267 269 269 270 273 273 273 275 275 276 279 279 280 283 283 284 287 287 288 289 289 291 295 295 296 8.11 Port A................................................................................................................................ 8.11.1 Overview.............................................................................................................. 8.11.2 Register Descriptions........................................................................................... 8.12 Port B ................................................................................................................................ 8.12.1 Overview.............................................................................................................. 8.12.2 Register Descriptions........................................................................................... 300 300 302 312 312 314 Section 9 16-Bit Timer....................................................................................................... 321 9.1 9.2 9.3 9.4 9.5 9.6 Overview........................................................................................................................... 9.1.1 Features................................................................................................................ 9.1.2 Block Diagrams ................................................................................................... 9.1.3 Pin Configuration................................................................................................. 9.1.4 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 9.2.1 Timer Start Register (TSTR) ............................................................................... 9.2.2 Timer Synchro Register (TSNC) ......................................................................... 9.2.3 Timer Mode Register (TMDR)............................................................................ 9.2.4 Timer Interrupt Status Register A (TISRA)......................................................... 9.2.5 Timer Interrupt Status Register B (TISRB) ......................................................... 9.2.6 Timer Interrupt Status Register C (TISRC) ......................................................... 9.2.7 Timer Counters (16TCNT) .................................................................................. 9.2.8 General Registers (GRA, GRB)........................................................................... 9.2.9 Timer Control Registers (16TCR) ....................................................................... 9.2.10 Timer I/O Control Register (TIOR)..................................................................... 9.2.11 Timer Output Level Setting Register C (TOLR) ................................................. CPU Interface ................................................................................................................... 9.3.1 16-Bit Accessible Registers ................................................................................. 9.3.2 8-Bit Accessible Registers ................................................................................... Operation .......................................................................................................................... 9.4.1 Overview.............................................................................................................. 9.4.2 Basic Functions.................................................................................................... 9.4.3 Synchronization ................................................................................................... 9.4.4 PWM Mode ......................................................................................................... 9.4.5 Phase Counting Mode.......................................................................................... 9.4.6 16-Bit Timer Output Timing................................................................................ Interrupts........................................................................................................................... 9.5.1 Setting of Status Flags ......................................................................................... 9.5.2 Timing of Clearing of Status Flags ...................................................................... 9.5.3 Interrupt Sources.................................................................................................. Usage Notes ...................................................................................................................... 321 321 323 326 327 328 328 329 331 333 336 339 341 342 343 346 348 350 350 352 353 353 354 361 363 367 369 370 370 372 373 374 Rev. 3.00 Sep 14, 2005 page xiii of xxii Section 10 8-Bit Timers..................................................................................................... 10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.1.2 Block Diagram..................................................................................................... 10.1.3 Pin Configuration ................................................................................................ 10.1.4 Register Configuration......................................................................................... 10.2 Register Descriptions........................................................................................................ 10.2.1 Timer Counters (8TCNT) .................................................................................... 10.2.2 Time Constant Registers A (TCORA)................................................................. 10.2.3 Time Constant Registers B (TCORB) ................................................................. 10.2.4 Timer Control Register (8TCR)........................................................................... 10.2.5 Timer Control/Status Registers (8TCSR) ............................................................ 10.3 CPU Interface ................................................................................................................... 10.3.1 8-Bit Registers ..................................................................................................... 10.4 Operation .......................................................................................................................... 10.4.1 8TCNT Count Timing ......................................................................................... 10.4.2 Compare Match Timing....................................................................................... 10.4.3 Input Capture Signal Timing ............................................................................... 10.4.4 Timing of Status Flag Setting .............................................................................. 10.4.5 Operation with Cascaded Connection.................................................................. 10.4.6 Input Capture Setting........................................................................................... 10.5 Interrupt ............................................................................................................................ 10.5.1 Interrupt Sources.................................................................................................. 10.5.2 A/D Converter Activation.................................................................................... 10.6 8-Bit Timer Application Example .................................................................................... 10.7 Usage Notes ...................................................................................................................... 10.7.1 Contention between 8TCNT Write and Clear...................................................... 10.7.2 Contention between 8TCNT Write and Increment .............................................. 10.7.3 Contention between TCOR Write and Compare Match ...................................... 10.7.4 Contention between TCOR Read and Input Capture........................................... 10.7.5 Contention between Counter Clearing by Input Capture and Counter Increment ............................................................................................................. 10.7.6 Contention between TCOR Write and Input Capture .......................................... 10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection)........................................................................................ 10.7.8 Contention between Compare Matches A and B ................................................. 10.7.9 8TCNT Operation and Internal Clock Source Switchover .................................. 387 387 387 389 390 391 392 392 393 394 395 398 403 403 405 405 406 407 408 409 412 414 414 415 415 416 416 417 418 419 420 421 422 423 423 Section 11 Programmable Timing Pattern Controller (TPC) ................................. 427 11.1 Overview........................................................................................................................... 427 Rev. 3.00 Sep 14, 2005 page xiv of xxii 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram..................................................................................................... 11.1.3 TPC Pins .............................................................................................................. 11.1.4 Registers .............................................................................................................. 11.2 Register Descriptions........................................................................................................ 11.2.1 Port A Data Direction Register (PADDR) ........................................................... 11.2.2 Port A Data Register (PADR).............................................................................. 11.2.3 Port B Data Direction Register (PBDDR) ........................................................... 11.2.4 Port B Data Register (PBDR) .............................................................................. 11.2.5 Next Data Register A (NDRA) ............................................................................ 11.2.6 Next Data Register B (NDRB) ............................................................................ 11.2.7 Next Data Enable Register A (NDERA).............................................................. 11.2.8 Next Data Enable Register B (NDERB) ............................................................... 11.2.9 TPC Output Control Register (TPCR) ................................................................. 11.2.10 TPC Output Mode Register (TPMR)................................................................... 11.3 Operation .......................................................................................................................... 11.3.1 Overview.............................................................................................................. 11.3.2 Output Timing...................................................................................................... 11.3.3 Normal TPC Output............................................................................................. 11.3.4 Non-Overlapping TPC Output............................................................................. 11.3.5 TPC Output Triggering by Input Capture ............................................................ 11.4 Usage Notes ...................................................................................................................... 11.4.1 Operation of TPC Output Pins............................................................................. 11.4.2 Note on Non-Overlapping Output ....................................................................... 427 428 429 430 431 431 431 432 432 433 435 437 438 439 442 444 444 445 446 448 450 451 451 451 Section 12 Watchdog Timer ............................................................................................. 453 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram..................................................................................................... 12.1.3 Register Configuration......................................................................................... 12.2 Register Descriptions........................................................................................................ 12.2.1 Timer Counter (TCNT)........................................................................................ 12.2.2 Timer Control/Status Register (TCSR)................................................................ 12.2.3 Reset Control/Status Register (RSTCSR)............................................................ 12.2.4 Notes on Register Access .................................................................................... 12.3 Operation .......................................................................................................................... 12.3.1 Watchdog Timer Operation ................................................................................. 12.3.2 Interval Timer Operation ..................................................................................... 12.3.3 Timing of Setting of Overflow Flag (OVF)......................................................... 12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 453 453 454 454 455 455 456 458 459 461 461 462 463 464 Rev. 3.00 Sep 14, 2005 page xv of xxii 12.4 Interrupts........................................................................................................................... 465 12.5 Usage Notes ...................................................................................................................... 465 Section 13 Serial Communication Interface ................................................................ 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram..................................................................................................... 13.1.3 Input/Output Pins................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions........................................................................................................ 13.2.1 Receive Shift Register (RSR) .............................................................................. 13.2.2 Receive Data Register (RDR).............................................................................. 13.2.3 Transmit Shift Register (TSR)............................................................................. 13.2.4 Transmit Data Register (TDR) ............................................................................ 13.2.5 Serial Mode Register (SMR) ............................................................................... 13.2.6 Serial Control Register (SCR) ............................................................................. 13.2.7 Serial Status Register (SSR) ................................................................................ 13.2.8 Bit Rate Register (BRR) ...................................................................................... 13.3 Operation .......................................................................................................................... 13.3.1 Overview.............................................................................................................. 13.3.2 Operation in Asynchronous Mode ....................................................................... 13.3.3 Multiprocessor Communication .......................................................................... 13.3.4 Synchronous Operation ....................................................................................... 13.4 SCI Interrupts.................................................................................................................... 13.5 Usage Notes ...................................................................................................................... 13.5.1 Notes on Use of SCI ............................................................................................ 467 467 467 469 470 471 472 472 472 473 473 474 478 483 488 497 497 499 509 516 525 526 526 Section 14 Smart Card Interface ..................................................................................... 14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram..................................................................................................... 14.1.3 Pin Configuration ................................................................................................ 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions........................................................................................................ 14.2.1 Smart Card Mode Register (SCMR).................................................................... 14.2.2 Serial Status Register (SSR) ................................................................................ 14.2.3 Serial Mode Register (SMR) ............................................................................... 14.2.4 Serial Control Register (SCR) ............................................................................. 14.3 Operation .......................................................................................................................... 14.3.1 Overview.............................................................................................................. 533 533 533 534 535 536 537 537 539 540 541 542 542 Rev. 3.00 Sep 14, 2005 page xvi of xxii 14.3.2 Pin Connections ................................................................................................... 14.3.3 Data Format ......................................................................................................... 14.3.4 Register Settings .................................................................................................. 14.3.5 Clock.................................................................................................................... 14.3.6 Transmitting and Receiving Data ........................................................................ 14.4 Usage Notes ...................................................................................................................... 542 544 545 547 549 557 Section 15 A/D Converter ................................................................................................. 561 15.1 Overview........................................................................................................................... 15.1.1 Features................................................................................................................ 15.1.2 Block Diagram..................................................................................................... 15.1.3 Input Pins............................................................................................................. 15.1.4 Register Configuration......................................................................................... 15.2 Register Descriptions........................................................................................................ 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 15.2.2 A/D Control/Status Register (ADCSR) ............................................................... 15.2.3 A/D Control Register (ADCR) ............................................................................ 15.3 CPU Interface ................................................................................................................... 15.4 Operation .......................................................................................................................... 15.4.1 Single Mode (SCAN = 0) .................................................................................... 15.4.2 Scan Mode (SCAN = 1)....................................................................................... 15.4.3 Input Sampling and A/D Conversion Time ......................................................... 15.4.4 External Trigger Input Timing............................................................................. 15.5 Interrupts........................................................................................................................... 15.6 Usage Notes ...................................................................................................................... 561 561 562 563 564 565 565 566 569 570 572 572 574 576 578 579 579 Section 16 D/A Converter ................................................................................................. 585 16.1 Overview........................................................................................................................... 16.1.1 Features................................................................................................................ 16.1.2 Block Diagram..................................................................................................... 16.1.3 Input/Output Pins................................................................................................. 16.1.4 Register Configuration......................................................................................... 16.2 Register Descriptions........................................................................................................ 16.2.1 D/A Data Registers 0 and 1 (DADR0/1) ............................................................. 16.2.2 D/A Control Register (DACR) ............................................................................ 16.2.3 D/A Standby Control Register (DASTCR).......................................................... 16.3 Operation .......................................................................................................................... 16.4 D/A Output Control .......................................................................................................... 585 585 586 586 587 588 588 588 590 591 592 Rev. 3.00 Sep 14, 2005 page xvii of xxii Section 17 RAM .................................................................................................................. 17.1 Overview........................................................................................................................... 17.1.1 Block Diagram..................................................................................................... 17.1.2 Register Configuration......................................................................................... 17.2 System Control Register (SYSCR) ................................................................................... 17.3 Operation .......................................................................................................................... 593 593 594 594 595 596 Section 18 Flash Memory ................................................................................................. 597 18.1 Overview........................................................................................................................... 597 18.2 Features............................................................................................................................. 598 18.2.1 Block Diagram..................................................................................................... 599 18.2.2 Pin Configuration ................................................................................................ 600 18.2.3 Register Configuration......................................................................................... 600 18.3 Register Descriptions........................................................................................................ 601 18.3.1 Flash Memory Control Register 1 (FLMCR1) .................................................... 601 18.3.2 Flash Memory Control Register 2 (FLMCR2) .................................................... 604 18.3.3 Erase Block Register 1 (EBR1) ........................................................................... 605 18.3.4 Erase Block Register 2 (EBR2) ........................................................................... 606 18.3.5 RAM Control Register (RAMCR)....................................................................... 607 18.4 Overview of Operation ..................................................................................................... 609 18.4.1 Mode Transitions ................................................................................................. 609 18.4.2 On-Board Programming Modes........................................................................... 611 18.4.3 Flash Memory Emulation in RAM ...................................................................... 613 18.4.4 Block Configuration ............................................................................................ 615 18.5 On-Board Programming Mode ......................................................................................... 616 18.5.1 Boot Mode ........................................................................................................... 617 18.5.2 User Program Mode............................................................................................. 622 18.6 Flash Memory Programming/Erasing............................................................................... 624 18.6.1 Program Mode ..................................................................................................... 626 18.6.2 Program-Verify Mode ......................................................................................... 627 18.6.3 Erase Mode .......................................................................................................... 631 18.6.4 Erase-Verify Mode .............................................................................................. 631 18.7 Flash Memory Protection.................................................................................................. 633 18.7.1 Hardware Protection ............................................................................................ 633 18.7.2 Software Protection ............................................................................................. 634 18.7.3 Error Protection ................................................................................................... 635 18.8 Flash Memory Emulation in RAM ................................................................................... 637 18.9 NMI Input Disabling Conditions ...................................................................................... 640 18.10 Flash Memory PROM Mode ............................................................................................ 641 18.10.1 Socket Adapters and Memory Map ..................................................................... 641 Rev. 3.00 Sep 14, 2005 page xviii of xxii 18.10.2 Notes on Use of PROM Mode ............................................................................. 642 18.11 Flash Memory Programming and Erasing Precautions..................................................... 643 Section 19 Clock Pulse Generator .................................................................................. 649 19.1 Overview........................................................................................................................... 19.1.1 Block Diagram..................................................................................................... 19.2 Oscillator Circuit............................................................................................................... 19.2.1 Connecting a Crystal Resonator........................................................................... 19.2.2 External Clock Input............................................................................................ 19.3 Duty Adjustment Circuit................................................................................................... 19.4 Prescalers .......................................................................................................................... 19.5 Frequency Divider ............................................................................................................ 19.5.1 Register Configuration......................................................................................... 19.5.2 Division Control Register (DIVCR) .................................................................... 19.5.3 Usage Notes ......................................................................................................... 649 650 651 651 653 655 655 656 656 656 657 Section 20 Power-Down State ......................................................................................... 659 20.1 Overview........................................................................................................................... 659 20.2 Register Configuration...................................................................................................... 661 20.2.1 System Control Register (SYSCR) ...................................................................... 661 20.2.2 Module Standby Control Register H (MSTCRH)................................................ 663 20.2.3 Module Standby Control Register L (MSTCRL)................................................. 664 20.3 Sleep Mode ....................................................................................................................... 667 20.3.1 Transition to Sleep Mode..................................................................................... 667 20.3.2 Exit from Sleep Mode.......................................................................................... 667 20.4 Software Standby Mode.................................................................................................... 668 20.4.1 Transition to Software Standby Mode ................................................................. 668 20.4.2 Exit from Software Standby Mode ...................................................................... 668 20.4.3 Selection of Waiting Time for Exit from Software Standby Mode ..................... 669 20.4.4 Sample Application of Software Standby Mode.................................................. 670 20.4.5 Note ..................................................................................................................... 670 20.5 Hardware Standby Mode .................................................................................................. 671 20.5.1 Transition to Hardware Standby Mode................................................................ 671 20.5.2 Exit from Hardware Standby Mode..................................................................... 671 20.5.3 Timing for Hardware Standby Mode ................................................................... 671 20.6 Module Standby Function................................................................................................. 673 20.6.1 Module Standby Timing ...................................................................................... 673 20.6.2 Read/Write in Module Standby ........................................................................... 673 20.6.3 Usage Notes ......................................................................................................... 673 20.7 System Clock Output Disabling Function......................................................................... 674 Rev. 3.00 Sep 14, 2005 page xix of xxii Section 21 Electrical Characteristics ............................................................................. 21.1 Electrical Characteristics of H8/3068F-ZTAT.................................................................. 21.1.1 Absolute Maximum Ratings ................................................................................ 21.1.2 DC Characteristics ............................................................................................... 21.1.3 AC Characteristics ............................................................................................... 21.1.4 A/D Conversion Characteristics .......................................................................... 21.1.5 D/A Conversion Characteristics .......................................................................... 21.1.6 Flash Memory Characteristics ............................................................................. 21.2 Operational Timing........................................................................................................... 21.2.1 Clock Timing ....................................................................................................... 21.2.2 Control Signal Timing ......................................................................................... 21.2.3 Bus Timing .......................................................................................................... 21.2.4 DRAM Interface Bus Timing .............................................................................. 21.2.5 TPC and I/O Port Timing..................................................................................... 21.2.6 Timer Input/Output Timing ................................................................................. 21.2.7 SCI Input/Output Timing..................................................................................... 21.2.8 DMAC Timing..................................................................................................... 675 675 675 676 681 687 689 690 692 692 693 694 700 703 704 705 706 Appendix A Instruction Set .............................................................................................. 707 A.1 A.2 A.3 Instruction List.................................................................................................................. 707 Operation Code Maps ....................................................................................................... 723 Number of States Required for Execution ........................................................................ 726 Appendix B Internal I/O Registers ................................................................................. B.1 Addresses (EMC = 1) ......................................................................................................... B.2 Addresses (EMC = 0) ......................................................................................................... B.3 Functions .......................................................................................................................... 735 735 746 763 Appendix C I/O Port Block Diagrams .......................................................................... 854 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 Port 1 Block Diagram ....................................................................................................... Port 2 Block Diagram ....................................................................................................... Port 3 Block Diagram ....................................................................................................... Port 4 Block Diagram ....................................................................................................... Port 5 Block Diagram ....................................................................................................... Port 6 Block Diagrams...................................................................................................... Port 7 Block Diagrams...................................................................................................... Port 8 Block Diagrams...................................................................................................... Port 9 Block Diagrams...................................................................................................... Port A Block Diagrams..................................................................................................... Port B Block Diagrams ..................................................................................................... Rev. 3.00 Sep 14, 2005 page xx of xxii 854 855 856 857 858 859 866 867 872 878 881 Appendix D Pin States ....................................................................................................... 889 D.1 D.2 Port States in Each Mode.................................................................................................. 889 Pin States at Reset............................................................................................................. 896 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode ............................................................................................................... 899 Appendix F Product Code Lineup .................................................................................. 900 Appendix G Package Dimensions .................................................................................. 901 Appendix H Comparison of H8/300H Series Product Specifications.................. 903 H.1 H.2 Differences between H8/3068F and H8/3067 Group and H8/3062 Group, H8/3048 Group ................................................................................................................. 903 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)....... 906 Rev. 3.00 Sep 14, 2005 page xxi of xxii Rev. 3.00 Sep 14, 2005 page xxii of xxii Section 1 Overview Section 1 Overview 1.1 Overview The H8/3068F is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas Technology architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series. The on-chip system supporting functions include ROM, RAM, a 16-bit timer, an 8-bit timer, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), and other facilities. The H8/3068F has 384 kbytes of ROM and 16 kbytes of RAM. Seven MCU operating modes offer a choice of bus width and address space size. The modes (modes 1 to 7) include two single-chip modes and five expanded modes. The H8/3068F includes an F-ZTATTM* version with on-chip flash memory that can be programmed on-board. This version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. Table 1.1 summarizes the features of the H8/3068F. Note: * F-ZTATTM (Flexible ZTAT) is a trademark of Renesas Technology Corp. Rev. 3.00 Sep 14, 2005 page 1 of 910 REJ09B0258-0300 Section 1 Overview Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine * Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation * Maximum clock rate: 25 MHz * Add/subtract: 80 ns * Multiply/divide: 560 ns 16-Mbyte address space Instruction features Memory * 8/16/32-bit data transfer, arithmetic, and logic instructions * Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits) * Signed and unsigned divide instructions (16 bits / 8 bits, 32 bits / 16 bits) * Bit accumulator function * Bit manipulation instructions with register-indirect specification of bit positions H8/3068F * ROM: 384 kbytes * RAM: 16 kbytes Interrupt * Seven external interrupt pins: NMI, IRQ0 to IRQ5 controller * 36 internal interrupts * Three selectable interrupt priority levels * Address space can be partitioned into eight areas, with independent bus specifications in each area * Chip select output available for areas 0 to 7 * 8-bit access or 16-bit access selectable for each area * Two-state or three-state access selectable for each area * Selection of two wait modes * Number of program wait states selectable for each area * Direct connection of burst ROM * Direct connection of up to 8-Mbyte DRAM (or DRAM interface can be used as interval timer) * Bus arbitration function Bus controller Rev. 3.00 Sep 14, 2005 page 2 of 910 REJ09B0258-0300 Section 1 Overview Feature Description DMA controller (DMAC) Short address mode * Maximum four channels available * Selection of I/O mode, idle mode, or repeat mode * Can be activated by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, conversion-end interrupts from the A/D converter, transmit-data-empty and receive-data-full interrupts from the SCI, or external requests Full address mode 16-bit timer, 3 channels 8-bit timer, 4 channels Programmable timing pattern controller (TPC) Watchdog timer (WDT), 1 channel * Maximum two channels available * Selection of normal mode or block transfer mode * Can be activated by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, conversion-end interrupts from the A/D converter, external requests, or auto-request * Three 16-bit timer channels, capable of processing up to six pulse outputs or six pulse inputs * 16-bit timer counter (channels 0 to 2) * Two multiplexed output compare/input capture pins (channels 0 to 2) * Operation can be synchronized (channels 0 to 2) * PWM mode available (channels 0 to 2) * Phase counting mode available (channel 2) * DMAC can be activated by compare match/input capture A interrupts (channels 0 to 2) * 8-bit up-counter (external event count capability) * Two time constant registers * Two channels can be connected * Maximum 16-bit pulse output, using 16-bit timer as time base * Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups) * Non-overlap mode available * Output data can be transferred by DMAC * Reset signal can be generated by overflow * Reset signal can be output externally (not in the F-ZTAT version) * Usable as an interval timer Rev. 3.00 Sep 14, 2005 page 3 of 910 REJ09B0258-0300 Section 1 Overview Feature Description Serial communication interface (SCI), 3 channels * Selection of asynchronous or synchronous mode * Full duplex: can transmit and receive simultaneously * On-chip baud-rate generator * Smart card interface functions added * Resolution: 10 bits * Eight channels, with selection of single or scan mode A/D converter D/A converter I/O ports * Variable analog conversion voltage range * Sample-and-hold function * A/D conversion can be started by an external trigger or 8-bit timer comparematch * DMAC can be activated by an A/D conversion end interrupt * Resolution: 8 bits * Two channels * D/A outputs can be sustained in software standby mode * 70 input/output pins * 9 input-only pins Operating modes * Power-down state Other features Seven MCU operating modes Mode Address Space Address Pins Initial Bus Width Max. Bus Width Mode 1 1 Mbyte A19 to A0 8 bits 16 bits Mode 2 1 Mbyte A19 to A0 16 bits 16 bits Mode 3 16 Mbytes A23 to A0 8 bits 16 bits Mode 4 16 Mbytes A23 to A0 16 bits 16 bits Mode 5 16 Mbytes A23 to A0 8 bits 16 bits Mode 6 64 kbyte -- -- -- Mode 7 1 Mbyte -- -- -- * On-chip ROM is disabled in modes 1 to 4 * Sleep mode * Software standby mode * Hardware standby mode * Module standby function * Programmable system clock frequency division * On-chip clock pulse generator Rev. 3.00 Sep 14, 2005 page 4 of 910 REJ09B0258-0300 Section 1 Overview Feature Description Product lineup Product Type Product Code Package H8/3068 F-ZTAT 5 V operation HD64F3068F 100-pin QFP (FP-100B) HD64F3068TE 100-pin TQFP (TFP-100B) Rev. 3.00 Sep 14, 2005 page 5 of 910 REJ09B0258-0300 Section 1 Overview 1.2 Block Diagram Port 3 P40 /D0 P41 /D1 P42 /D2 P43 /D3 P44 /D4 P45 /D5 P46 /D6 P47 /D7 P30 /D8 P31 /D9 P32 /D10 P33 /D11 P34 /D12 P35 /D13 P36 /D14 P37 /D15 VSS VSS VSS VSS VSS VSS VCC VCC VCL Figure 1.1 shows an internal block diagram. Port 4 Address bus Data bus (upper) MD1 Data bus (lower) P53 /A 19 Port 5 MD2 MD0 P52 /A 18 P51 /A 17 P50 /A 16 EXTAL P27 /A 15 Clock pulse generator RES FWE P26 /A 14 H8/300H CPU P25 /A 13 Port 2 XTAL STBY NMI LWR/P66 DMA controller (DMAC) RD/P64 AS/P63 Port 6 HWR/P65 P23 /A 11 P22 /A 10 Bus controller Interrupt controller /P67 P24 /A 12 P21 /A 9 P20 /A 8 P17 /A 7 ROM (flash memory) P16 /A 6 P15 /A 5 Port 1 BACK/P62 BREQ/P61 WAIT/P60 P14 /A 4 P13 /A 3 P12 /A 2 RAM P11 /A 1 CS0/P84 CS2/IRQ2/P82 CS3/IRQ1/P81 Port 8 ADTRG/CS1/IRQ3/P83 P10 /A 0 Watchdog timer (WDT) 16-bit timer unit RFSH/IRQ0/P80 Serial communication interface (SCI) x 3 channels 8-bit timer unit P95 /SCK 1 /IRQ 5 Programmable timing pattern controller (TPC) P94 /SCK 0 /IRQ 4 Port 9 A/D converter D/A converter P93 /RxD1 P92 /RxD0 P91 /TxD 1 P90 /TxD 0 Figure 1.1 Block Diagram Rev. 3.00 Sep 14, 2005 page 6 of 910 REJ09B0258-0300 AN0/P70 AN1/P71 AN2/P72 AN3/P73 AN4/P74 AN5/P75 DA0/AN6/P76 DA1/AN7/P77 AVSS VREF AVCC TEND0/TCLKA/TP0/PA0 TEND1/TCLKB/TP1/PA1 Port 7 TCLKC/TIOCA0/TP2/PA2 TCLKD/TIOCB0/TP3/PA3 A23/TIOCA1/TP4/PA4 A22/TIOCB1/TP5/PA5 A21/TIOCA2/TP6/PA6 A20/TIOCB2/TP7/PA7 CS7/TMO0/TP8/PB0 CS6/DREQ0/TMIO1/TP9/PB1 Port A CS5/TMO2/TP10/PB2 CS4/DREQ1/TMIO3/TP11/PB3 UCAS/TP12/PB4 TxD2/TP14/PB6 SCK2/LCAS/TP13/PB5 RxD2/TP15/PB7 Port B Section 1 Overview 1.3 Pin Description 1.3.1 Pin Arrangement P52 /A 18 P51 /A 17 P50 /A 16 P27 /A 15 P26 /A 14 54 53 52 51 STBY 62 P53 /A 19 RES 63 55 NMI 64 VSS VSS 65 56 EXTAL 66 P60 /WAIT XTAL 67 57 VCC 68 P61 /BREQ P63 /AS 69 58 P64 /RD 70 59 P65 /HWR 71 P67/ P66 /LWR 72 P62 /BACK MD0 73 60 MD1 74 61 MD2 75 The pin arrangement of the H8/3068F FP-100B and TFP-100B packages is shown in figure 1.2. AVCC 76 50 A13/P25 VREF 77 49 A12/P24 P70/AN0 78 48 A11/P23 P71/AN1 79 47 A10/P22 P72/AN2 80 46 A9/P21 P73/AN3 81 45 A8/P20 P74/AN4 82 44 VSS P75/AN5 83 43 A7/P17 P76/AN6/DA0 84 42 A6/P16 P77/AN7/DA1 85 41 A5/P15 AVSS 86 40 A4/P14 P80/IRQ0/RFSH 87 39 A3/P13 P81/IRQ1/CS3 88 38 A2/P12 P82/IRQ2/CS2 89 37 A1/P11 P83/IRQ3/CS1/ADTRG 90 36 A0/P10 P84/CS0 91 35 VCC VSS 92 34 D15/P37 PA0/TP0/TCLKA/TEND0 93 33 D14/P36 PA1/TP1/TCLKB/TEND1 94 32 D13/P35 PA2/TP2/TIOCA0/TCLKC 95 31 D12/P34 PA3/TP3/TIOCB0/TCLKD 96 30 D11/P33 PA4/TP4/TIOCA1/A23 97 29 D10/P32 PA5/TP5/TIOCB1/A22 98 28 D9/P31 PA6/TP6/TIOCA2/A21 99 27 D8/P30 PA7/TP7/TIOCB2/A20 100 26 D7/P47 Top view 14 15 16 17 18 19 20 21 22 23 24 25 RxD1 /P93 IRQ4 /SCK0 /P94 IRQ5 /SCK1 /P95 D0 /P40 D1 /P41 D2 /P42 D3 /P43 VSS D4 /P44 D5 /P45 D6 /P46 9 RxD2/TP15/PB7 RxD0 /P92 8 TxD2/TP14/PB6 13 7 SCK2/LCAS/TP13/PB5 TxD1 /P91 6 UCAS/TP12/PB4 12 5 CS4/DREQ1/TMIO3/TP11/PB3 TxD0 /P90 4 CS5/TMO2/TP10/PB2 11 3 CS6/DREQ0/TMIO1/TP9/PB1 10 2 FWE VSS 1 VCL* CS7/TMO0/TP8/PB0 (FP-100B, TFP-100B) 1 0.1 F Note: * Functions as VCL pin. When functioning as VCL pin, the connection of an external capacitor is required. Figure 1.2 Pin Arrangement (FP-100B or TFP-100B, Top View) Rev. 3.00 Sep 14, 2005 page 7 of 910 REJ09B0258-0300 Section 1 Overview 1.3.2 Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Pin No. Type Symbol FP-100B TFP-100B I/O Power VCC 35, 68 Input Power: For connection to the power supply. Connect all VCC pins to the system power supply. VSS 11, 22, 44, Input 57, 65, 92 Ground: For connection to ground (0 V). Connect all VSS pins to the 0-V system power supply. XTAL 67 Input For connection to a crystal resonator. For examples of crystal resonator and external clock input, see section 19, Clock Pulse Generator. EXTAL 66 Input For connection to a crystal resonator or input of an external clock signal. For examples of crystal resonator and external clock input, see section 19, Clock Pulse Generator. 61 Output System clock: Supplies the system clock to external devices. VCL 1 Output Connect an external capacitor between this pin and GND (0 V). Do not connect to VCC. Clock Internal step-down pin Name and Function VCL Operating mode control MD2 to MD0 75 to 73 Input Mode 2 to mode 0: For setting the operating mode, as follows. Inputs at these pins must not be changed during operation. MD2 Rev. 3.00 Sep 14, 2005 page 8 of 910 REJ09B0258-0300 0.1 F MD1 MD0 Operating Mode 0 0 0 -- 0 0 1 Mode 1 0 1 0 Mode 2 0 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 1 1 0 Mode 6 1 1 1 Mode 7 Section 1 Overview Pin No. Type Symbol FP-100B TFP-100B I/O System control RES 63 Input Reset input: When driven low, this pin resets the chip FWE 10 Input Write enable signal: Flash memory write control signal STBY 62 Input Standby: When driven low, this pin forces a transition to hardware standby mode BREQ 59 Input Bus request: Used by an external bus master to request the bus right BACK 60 Output Bus request acknowledge: Indicates that the bus has been granted to an external bus master NMI 64 Input Nonmaskable interrupt: Requests a nonmaskable interrupt 17, 16, 90 to 87 Input Interrupt request 5 to 0: Maskable interrupt request pins Interrupts IRQ5 to IRQ0 Name and Function Address bus A23 to A0 97 to 100, 56 to 45, 43 to 36 Output Address bus: Outputs address signals Data bus D15 to D0 34 to 23, 21 to 18 Input/ output Bus control CS7 2 to 5, 88 to 91 Output Chip select: Select signals for areas 7 to 0 CS0 AS 69 Output Address strobe: Goes low to indicate valid address output on the address bus RD 70 Output Read: Goes low to indicate reading from the external address space HWR 71 Output High write: Goes low to indicate writing to the external address space; indicates valid data on the upper data bus (D15 to D8). LWR 72 Output Low write: Goes low to indicate writing to the external address space; indicates valid data on the lower data bus (D7 to D0). WAIT 58 Input to Data bus: Bidirectional data bus Wait: Requests insertion of wait states in bus cycles during access to the external address space Rev. 3.00 Sep 14, 2005 page 9 of 910 REJ09B0258-0300 Section 1 Overview Pin No. Type Symbol FP-100B TFP-100B I/O DRAM interface RFSH 87 Output Refresh: Indicates a refresh cycle CS5 89, 88, 5, 4 Output Row address strobe RAS: Row address strobe signal for DRAM RD 70 Output Write enable WE: Write enable signal for DRAM HWR 71 6 Output Upper column address strobe UCAS: Column address strobe signal for DRAM 72 7 Output Lower column address strobe LCAS: Column address strobe signal for DRAM 5, 3 Input 94, 93 Output Transfer end 1 and 0: These signals indicate that the DMAC has ended a data transfer CS2 to UCAS LWR LCAS DMA controller (DMAC) , DREQ1 DREQ0 , TEND1 TEND0 16-bit timer TCLKD to 96 to 93 TCLKA 8-bit timer Programmable timing pattern controller (TPC) Name and Function DMA request 1 and 0: DMAC activation requests Input Clock input D to A: External clock inputs TIOCA2 to 99, 97, 95 TIOCA0 Input/ output Input capture/output compare A2 to A0: GRA2 to GRA0 output compare or input capture, or PWM output TIOCB2 to 100, 98, TIOCB0 96 Input/ output Input capture/output compare B2 to B0: GRB2 to GRB0 output compare or input capture, or PWM output TMO0, TMO2 2, 4 Output Compare match output: Compare match output pins TMIO1, TMIO3 3, 5 Input/ output Input capture input/compare match output: Input capture input or compare match output pins TCLKD to 96 to 93 TCLKA Input Counter external clock input: These pins input an external clock to the counters. TP15 to TP0 Output TPC output 15 to 0: Pulse output 9 to 2, 100 to 93 Rev. 3.00 Sep 14, 2005 page 10 of 910 REJ09B0258-0300 Section 1 Overview Pin No. FP-100B TFP-100B I/O Type Symbol Serial communication interface (SCI) TxD2 to TxD0 8, 13, 12 Output Transmit data (channels 0, 1, 2): SCI data output RxD2 to RxD0 9, 15, 14 Input Receive data (channels 0, 1, 2): SCI data input SCK2 to SCK0 7, 17, 16 Input/ output Serial clock (channels 0, 1, 2): SCI clock input/output AN7 to AN0 85 to 78 Input Analog 7 to 0: Analog input pins ADTRG 90 Input A/D conversion external trigger input: External trigger input for starting A/D conversion D/A converter DA1, DA0 85, 84 Output Analog output: Analog output from the D/A converter A/D and D/A converters AVCC 76 Input Power supply pin for the A/D and D/A converters. Connect to the system power supply when not using the A/D and D/A converters. AVSS 86 Input Ground pin for the A/D and D/A converters. Connect to system ground (0 V). VREF 77 Input Reference voltage input pin for the A/D and D/A converters. Connect to the system power supply when not using the A/D and D/A converters. P17 to P10 43 to 36 Input/ output Port 1: Eight input/output pins. The direction of each pin can be selected in the port 1 data direction register (P1DDR). P27 to P20 52 to 45 Input/ output Port 2: Eight input/output pins. The direction of each pin can be selected in the port 2 data direction register (P2DDR). P37 to P30 34 to 27 Input/ output Port 3: Eight input/output pins. The direction of each pin can be selected in the port 3 data direction register (P3DDR). P47 to P40 26 to 23, 21 to 18 Input/ output Port 4: Eight input/output pins. The direction of each pin can be selected in the port 4 data direction register (P4DDR). P53 to P50 56 to 53 Input/ output Port 5: Four input/output pins. The direction of each pin can be selected in the port 5 data direction register (P5DDR). A/D converter I/O ports Name and Function Rev. 3.00 Sep 14, 2005 page 11 of 910 REJ09B0258-0300 Section 1 Overview Pin No. FP-100B TFP-100B I/O Type Symbol I/O ports P67 to P60 61, 72 to 69, 60 to 58 Input/ output Port 6: Eight input/output pins. The direction of each pin can be selected in the port 6 data direction register (P6DDR). P77 to P70 85 to 78 Input Port 7: Eight input pins P84 to P80 91 to 87 Input/ output Port 8: Five input/output pins. The direction of each pin can be selected in the port 8 data direction register (P8DDR). P95 to P90 17 to 12 Input/ output Port 9: Six input/output pins. The direction of each pin can be selected in the port 9 data direction register (P9DDR). PA7 to PA0 100 to 93 Input/ output Port A: Eight input/output pins. The direction of each pin can be selected in the port A data direction register (PADDR). PB7 to PB0 9 to 2 Input/ output Port B: Eight input/output pins. The direction of each pin can be selected in the port B data direction register (PBDDR). Rev. 3.00 Sep 14, 2005 page 12 of 910 REJ09B0258-0300 Name and Function Section 1 Overview 1.3.3 Pin Assignments in Each Mode Table 1.3 lists the pin assignments in each mode. Table 1.3 Pin No. Pin Assignments in Each Mode (FP-100B or TFP-100B) Pin Name FP-100B TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 1 VCL*1 VCL*1 VCL*1 VCL*1 VCL*1 VCL*1 VCL*1 2 PB0/TP8/ TMO0/CS7 PB0/TP8/ TMO0/CS7 PB0/TP8/ TMO0/CS7 PB0/TP8/ TMO0/CS7 PB0/TP8/ TMO0/CS7 PB0/TP8/ TMO0 PB0/TP8/ TMO0 3 PB1/TP9/ TMIO1/ DREQ0/ PB1/TP9/ TMIO1/ DREQ0/ PB1/TP9/ TMIO1/ DREQ0/ PB1/TP9/ TMIO1/ DREQ0/ PB1/TP9/ TMIO1/ DREQ0/ PB1/TP9/ TMIO1/ PB1/TP9/ TMIO1/ 4 PB2/TP10/ TMO2/CS5 PB2/TP10/ TMO2/CS5 PB2/TP10/ TMO2/CS5 PB2/TP10/ TMO2/CS5 PB2/TP10/ TMO2/CS5 PB2/TP10/ TMO2 PB2/TP10/ TMO2 5 PB3/TP11/ TMIO3/ DREQ1/ PB3/TP11/ TMIO3/ DREQ1/ PB3/TP11/ TMIO3/ DREQ1/ PB3/TP11/ TMIO3/ DREQ1/ PB3/TP11/ TMIO3/ DREQ1/ PB3/TP11/ TMIO3/ PB3/TP11/ TMIO3/ 6 PB4/TP12/ PB4/TP12/ PB4/TP12/ PB4/TP12/ PB4/TP12/ PB4/TP12 PB4/TP12 7 PB5/TP13/ LCAS/ SCK2 PB5/TP13/ LCAS/ SCK2 PB5/TP13/ LCAS/ SCK2 PB5/TP13/ LCAS/ SCK2 PB5/TP13/ LCAS/ SCK2 PB5/TP13/ SCK2 PB5/TP13/ SCK2 8 PB6/TP14/ TxD2 PB6/TP14/ TxD2 PB6/TP14/ TxD2 PB6/TP14/ TxD2 PB6/TP14/ TxD2 PB6/TP14/ TxD2 PB6/TP14/ TxD2 9 PB7/TP15/ RxD2 PB7/TP15/ RxD2 PB7/TP15/ RxD2 PB7/TP15/ RxD2 PB7/TP15/ RxD2 PB7/TP15/ RxD2 PB7/TP15/ RxD2 10 FWE FWE FWE FWE FWE FWE FWE 11 VSS VSS VSS VSS VSS VSS VSS 12 P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 13 P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 14 P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 15 P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 16 P94/IRQ4/ SCK0 P94/IRQ4/ SCK0 P94/IRQ4/ SCK0 P94/IRQ4/ SCK0 P94/IRQ4/ SCK0 P94/IRQ4/ SCK0 P94/IRQ4/ SCK0 CS6 CS4 UCAS CS6 CS4 UCAS CS6 CS4 UCAS CS6 CS4 UCAS CS6 CS4 UCAS DREQ0 DREQ1 DREQ0 DREQ1 Rev. 3.00 Sep 14, 2005 page 13 of 910 REJ09B0258-0300 Section 1 Overview Pin No. Pin Name FP-100B TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 17 P95/IRQ5/ SCK1 P95/IRQ5/ SCK1 P95/IRQ5/ SCK1 P95/IRQ5/ SCK1 P95/IRQ5/ SCK1 P95/IRQ5/ SCK1 P95/IRQ5/ SCK1 18 P40/D0* 2 P40 P40 2 P41 P41 2 P42 P42 2 2 3 P40/D0* 2 P41/D1* 2 P42/D2* 19 P41/D1* 20 P42/D2* 2 2 P40/D0* 3 P41/D1* 3 P42/D2* 3 3 P40/D0* 2 P41/D1* 2 P42/D2* 2 P40/D0* 3 P41/D1* 3 P42/D2* 3 21 P43/D3* P43/D3* P43/D3* P43/D3* P43/D3* P43 P43 22 VSS VSS VSS VSS VSS 23 24 2 P44/D4* 2 P45/D5* 3 P44/D4* 3 P45/D5* 2 P46/D6* 2 2 P44/D4* 2 P45/D5* 3 P46/D6* 3 3 P44/D4* 3 P45/D5* 2 P46/D6* 2 VSS VSS 2 P44 P44 2 P45 P45 2 2 P44/D4* P45/D5* 3 P46/D6* 3 25 P46/D6* P46 P46 26 P47/D7* P47/D7* P47/D7* P47/D7* P47/D7* P47 P47 27 D8 D8 D8 D8 D8 P30 P30 28 D9 D9 D9 D9 D9 P31 P31 29 D10 D10 D10 D10 D10 P32 P32 30 D11 D11 D11 D11 D11 P33 P33 31 D12 D12 D12 D12 D12 P34 P34 32 D13 D13 D13 D13 D13 P35 P35 33 D14 D14 D14 D14 D14 P36 P36 34 D15 D15 D15 D15 D15 P37 P37 35 VCC VCC VCC VCC VCC VCC VCC 36 A0 A0 A0 A0 P10/A0 P10 P10 37 A1 A1 A1 A1 P11/A1 P11 P11 38 A2 A2 A2 A2 P12/A2 P12 P12 39 A3 A3 A3 A3 P13/A3 P13 P13 40 A4 A4 A4 A4 P14/A4 P14 P14 41 A5 A5 A5 A5 P15/A5 P15 P15 42 A6 A6 A6 A6 P16/A6 P16 P16 43 A7 A7 A7 A7 P17/A7 P17 P17 44 VSS VSS VSS VSS VSS VSS VSS 45 A8 A8 A8 A8 P20/A8 P20 P20 46 A9 A9 A9 A9 P21/A9 P21 P21 47 A10 A10 A10 A10 P22/A10 P22 P22 Rev. 3.00 Sep 14, 2005 page 14 of 910 REJ09B0258-0300 Section 1 Overview Pin No. Pin Name FP-100B TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 48 A11 A11 A11 A11 P23/A11 P23 P23 49 A12 A12 A12 A12 P24/A12 P24 P24 50 A13 A13 A13 A13 P25/A13 P25 P25 51 A14 A14 A14 A14 P26/A14 P26 P26 52 A15 A15 A15 A15 P27/A15 P27 P27 53 A16 A16 A16 A16 P50/A16 P50 P50 54 A17 A17 A17 A17 P51/A17 P51 P51 55 A18 A18 A18 A18 P52/A18 P52 P52 56 A19 A19 A19 A19 P53/A19 P53 P53 57 VSS VSS VSS VSS VSS VSS VSS 58 P60/WAIT P60/WAIT P60/WAIT P60/WAIT P60/WAIT P60 P60 59 P61/BREQ P61/BREQ P61/BREQ P61/BREQ P61/BREQ P61 P61 60 P62/BACK P62/BACK P62/BACK P62/BACK P62/BACK P62 P62 61 P67/ P67/ P67/ 63 STBY RES STBY RES STBY RES STBY RES STBY RES STBY RES STBY RES 64 NMI NMI NMI NMI NMI NMI NMI 65 VSS VSS VSS VSS VSS VSS VSS 66 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL 67 XTAL XTAL XTAL XTAL XTAL XTAL XTAL 68 VCC VCC VCC VCC VCC VCC VCC AS RD HWR LWR AS RD HWR LWR AS RD HWR LWR AS RD HWR LWR P63 P63 P64 P64 P65 P65 72 AS RD HWR LWR P66 P66 73 MD0 MD0 MD0 MD0 MD0 MD0 MD0 74 MD1 MD1 MD1 MD1 MD1 MD1 MD1 75 MD2 MD2 MD2 MD2 MD2 MD2 MD2 76 AVCC AVCC AVCC AVCC AVCC AVCC AVCC 77 VREF VREF VREF VREF VREF VREF VREF 78 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 79 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 62 69 70 71 Rev. 3.00 Sep 14, 2005 page 15 of 910 REJ09B0258-0300 Section 1 Overview Pin No. Pin Name FP-100B TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 80 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 81 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 82 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 83 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 84 P76/AN6/ DA0 P76/AN6/ DA0 P76/AN6/ DA0 P76/AN6/ DA0 P76/AN6/ DA0 P76/AN6/ DA0 P76/AN6/ DA0 85 P77/AN7/ DA1 P77/AN7/ DA1 P77/AN7/ DA1 P77/AN7/ DA1 P77/AN7/ DA1 P77/AN7/ DA1 P77/AN7/ DA1 86 AVSS AVSS AVSS AVSS AVSS AVSS AVSS P80/IRQ0/ P80/IRQ0/ P80/IRQ0/ P80/IRQ0 P80/IRQ0 P81/IRQ1 P81/IRQ1 P82/IRQ2 P82/IRQ2 P83/IRQ3/ P83/IRQ3/ P84/CS0 RFSH P81/IRQ1/ CS3 P82/IRQ2/ CS2 P83/IRQ3/ CS1/ ADTRG P84/CS0 P80/IRQ0/ 91 P80/IRQ0/ RFSH P81/IRQ1/ CS3 P82/IRQ2/ CS2 P83/IRQ3/ CS1/ ADTRG P84/CS0 P84 P84 92 VSS VSS VSS VSS VSS VSS VSS 93 PA0/TP0/ TCLKA/ PA0/TP0/ TCLKA/ PA0/TP0/ TCLKA/ PA0/TP0/ TCLKA/ PA0/TP0/ TCLKA/ PA0/TP0/ TCLKA/ PA0/TP0/ TCLKA/ PA1/TP1/ TCLKB/ PA1/TP1/ TCLKB/ PA1/TP1 /TCLKB/ PA1/TP1/ TCLKB/ PA1/TP1/ TCLKB/ PA1/TP1/ TCLKB/ PA1/TP1/ TCLKB/ 95 PA2/TP2/ TIOCA0/ TCLKC PA2/TP2/ TIOCA0/ TCLKC PA2/TP2/ TIOCA0/ TCLKC PA2/TP2/ TIOCA0/ TCLKC PA2/TP2/ TIOCA0/ TCLKC PA2/TP2/ TIOCA0/ TCLKC PA2/TP2/ TIOCA0/ TCLKC 96 PA3/TP3/ TIOCB0/ TCLKD PA3/TP3/ TIOCB0/ TCLKD PA3/TP3/ TIOCB0/ TCLKD PA3/TP3/ TIOCB0/ TCLKD PA3/TP3/ TIOCB0/ TCLKD PA3/TP3/ TIOCB0/ TCLKD PA3/TP3/ TIOCB0/ TCLKD 97 PA4/TP4/ TIOCA1 PA4/TP4/ TIOCA1 PA4/TP4/ TIOCA1/ A23 PA4/TP4/ TIOCA1/ A23 PA4/TP4/ TIOCA1/ A23 PA4/TP4/ TIOCA1 PA4/TP4/ TIOCA1 87 88 89 90 TEND0 94 TEND1 RFSH P81/IRQ1/ CS3 P82/IRQ2/ CS2 P83/IRQ3/ CS1/ ADTRG P84/CS0 TEND0 TEND1 RFSH P81/IRQ1/ CS3 P82/IRQ2/ CS2 P83/IRQ3/ CS1/ ADTRG TEND0 TEND1 Rev. 3.00 Sep 14, 2005 page 16 of 910 REJ09B0258-0300 TEND0 TEND1 RFSH P81/IRQ1/ CS3 P82/IRQ2/ CS2 P83/IRQ3/ CS1/ ADTRG P84/CS0 TEND0 TEND1 ADTRG TEND0 TEND1 ADTRG TEND0 TEND1 Section 1 Overview Pin No. Pin Name FP-100B TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 98 PA5/TP5/ TIOCB1 PA5/TP5/ TIOCB1 PA5/TP5/ TIOCB1/ A22 PA5/TP5/ TIOCB1/ A22 PA5/TP5/ TIOCB1/ A22 PA5/TP5/ TIOCB1 PA5/TP5/ TIOCB1 99 PA6/TP6/ TIOCA2 PA6/TP6/ TIOCA2 PA6/TP6/ TIOCA2/ A21 PA6/TP6/ TIOCA2/ A21 PA6/TP6/ TIOCA2/ A21 PA6/TP6/ TIOCA2 PA6/TP6/ TIOCA2 100 PA7/TP7/ TIOCB2 PA7/TP7/ TIOCB2 A20 A20 PA7/TP7/ TIOCB2/ A20 PA7/TP7/ TIOCB2 PA7/TP7/ TIOCB2 Notes: 1. Functions as VCL pin. 2. In modes 1, 3, 5 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected after a reset, but they can be changed by software. 3. In modes 2 and 4 the D0 to D7 functions of pins P40/D0 to P47/D7 are selected after a reset, but they can be changed by software. Rev. 3.00 Sep 14, 2005 page 17 of 910 REJ09B0258-0300 Section 1 Overview Rev. 3.00 Sep 14, 2005 page 18 of 910 REJ09B0258-0300 Section 2 CPU Section 2 CPU 2.1 Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features. * Upward compatibility with H8/300 CPU Can execute H8/300 Series object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-two basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, or @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8, PC) or @(d:16, PC)] Memory indirect [@@aa:8] * 16-Mbyte linear address space Rev. 3.00 Sep 14, 2005 page 19 of 910 REJ09B0258-0300 Section 2 CPU * High-speed operation All frequently-used instructions execute in two to four states Maximum clock frequency: 25 MHz 8/16/32-bit register-register add/subtract: 80 ns 8 x 8-bit register-register multiply: 560 ns 16 / 8-bit register-register divide: 560 ns 16 x 16-bit register-register multiply: 880 ns 32 / 16-bit register-register divide: 880 ns * Two CPU operating modes Normal mode Advanced mode * Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8/300H has the following enhancements. * More general registers Eight 16-bit registers have been added. * Expanded address space Advanced mode supports a maximum 16-Mbyte address space. Normal mode supports the same 64-kbyte address space as the H8/300 CPU. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Data transfer, arithmetic, and logic instructions can operate on 32-bit data. Signed multiply/divide instructions and other instructions have been added. Rev. 3.00 Sep 14, 2005 page 20 of 910 REJ09B0258-0300 Section 2 CPU 2.2 CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. Normal mode Maximum 64 kbytes, program and data areas combined Advanced mode Maximum 16 Mbytes, program and data areas combined CPU operating modes Figure 2.1 CPU Operating Modes Rev. 3.00 Sep 14, 2005 page 21 of 910 REJ09B0258-0300 Section 2 CPU 2.3 Address Space Figure 2.2 shows a simple memory map for the H8/3068F. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode. The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are ignored. H'0000 H'00000 H'000000 H'FFFF H'FFFFF H'FFFFFF a. 1-Mbyte mode Normal mode b. 16-Mbyte mode Advanced mode Figure 2.2 Memory Map Rev. 3.00 Sep 14, 2005 page 22 of 910 REJ09B0258-0300 Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 0 7 0 7 0 ER0 E0 R0H R0L ER1 E1 R1H R1L ER2 E2 R2H R2L ER3 E3 R3H R3L ER4 E4 R4H R4L ER5 E5 R5H R5L ER6 E6 R6H R6L R7H R7L (SP) E7 ER7 Control Registers (CR) 23 0 PC 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C Legend SP: Stack pointer PC: Program counter CCR: Condition code register Interrupt mask bit I: User bit or interrupt mask bit UI: Half-carry flag H: User bit U: Negative flag N: Zero flag Z: Overflow flag V: Carry flag C: Figure 2.3 CPU Registers Rev. 3.00 Sep 14, 2005 page 23 of 910 REJ09B0258-0300 Section 2 CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) E0 to E7 RH registers R0H to R7H ER registers ER0 to ER7 R registers R0 to R7 RL registers R0L to R7L Figure 2.4 Usage of General Registers Rev. 3.00 Sep 14, 2005 page 24 of 910 REJ09B0258-0300 Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. Free area SP (ER7) Stack area Figure 2.5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0. Condition Code Register (CCR): This 8-bit register contains internal CPU status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details see section 5, Interrupt Controller. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Rev. 3.00 Sep 14, 2005 page 25 of 910 REJ09B0258-0300 Section 2 CPU Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Stores the value of the most significant bit of data, regarded as the sign bit. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and UI bits, see section 5, Interrupt Controller. 2.4.4 Initial CPU Register Values In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the initial value of the stack pointer (ER7) is also undefined. The stack pointer (ER7) must therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 3.00 Sep 14, 2005 page 26 of 910 REJ09B0258-0300 Section 2 CPU 2.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figures 2.6 and 2.7 show the data formats in general registers. Data Type General Register 1-bit data RnH 7 6 5 4 3 2 1 0 1-bit data RnL Don't care 4-bit BCD data RnH Upper digit Lower digit 4-bit BCD data RnL Don't care Byte data RnH Data Format 7 0 Don't care 7 7 4 3 0 Don't care 7 7 RnL 4 3 0 Upper digit Lower digit 0 Don't care MSB Byte data 0 7 6 5 4 3 2 1 0 LSB 7 0 MSB LSB Don't care Legend RnH: General register RH RnL: General register RL Figure 2.6 General Register Data Formats Rev. 3.00 Sep 14, 2005 page 27 of 910 REJ09B0258-0300 Section 2 CPU Data Type General Register Word data Rn Word data Data Format 15 0 MSB LSB 15 0 MSB LSB En 31 16 15 0 Longword data ERn MSB Legend ERn: General register En: General register E Rn: General register R MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats Rev. 3.00 Sep 14, 2005 page 28 of 910 REJ09B0258-0300 LSB Section 2 CPU 2.5.2 Memory Data Formats Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address Data Format 7 1-bit data Address L 7 Byte data Address L MSB Word data Address 2M MSB 0 6 5 4 Address 2N 2 1 0 LSB Address 2M + 1 Longword data 3 LSB MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Rev. 3.00 Sep 14, 2005 page 29 of 910 REJ09B0258-0300 Section 2 CPU 2.6 Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Data transfer Instruction Types 1 1 2 MOV, PUSH* , POP* , MOVTPE* , MOVFPE* 2 3 Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, 18 MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU Logic operations AND, OR, XOR, NOT 4 Shift operations SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8 Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, 14 BIXOR, BLD, BILD, BST, BIST Branch Bcc*3, JMP, BSR, JSR, RTS 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9 Block data transfer EEPMOV 1 Total 62 types Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn. PUSH.W Rn is identical to MOV.W Rn, @-SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @-SP. 2. Not available in the H8/3068F. 3. Bcc is a generic branching instruction. Rev. 3.00 Sep 14, 2005 page 30 of 910 REJ09B0258-0300 Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Addressing Modes @ (d:24, ERn) @ERn+/ @-ERn @ aa:8 @ aa:16 @ aa:24 @ (d:8, PC) @ (d:16, PC) @@ aa:8 Function Instruction #xx Rn @ERn @ (d:16, ERn) Data transfer MOV BWL BWL BWL BWL BWL BWL B BWL BWL -- -- -- -- POP, PUSH -- -- -- -- -- -- -- -- -- -- -- -- WL MOVFPE, -- -- -- -- -- -- -- -- -- -- -- -- -- -- MOVTPE ADD, CMP BWL BWL -- -- -- -- -- -- -- -- -- -- -- SUB WL BWL -- -- -- -- -- -- -- -- -- -- -- ADDX, SUBX B B -- -- -- -- -- -- -- -- -- -- -- ADDS, SUBS -- L -- -- -- -- -- -- -- -- -- -- -- INC, DEC -- BWL -- -- -- -- -- -- -- -- -- -- -- DAA, DAS -- B -- -- -- -- -- -- -- -- -- -- -- MULXU, -- BW -- -- -- -- -- -- -- -- -- -- -- NEG -- BWL -- -- -- -- -- -- -- -- -- -- -- EXTU, EXTS -- WL -- -- -- -- -- -- -- -- -- -- -- AND, OR, XOR -- BWL -- -- -- -- -- -- -- -- -- -- -- NOT -- BWL -- -- -- -- -- -- -- -- -- -- -- Shift instructions -- BWL -- -- -- -- -- -- -- -- -- -- -- Bit manipulation -- B B -- -- -- B -- -- -- -- -- -- Branch Bcc, BSR -- -- -- -- -- -- -- -- -- -- -- -- -- JMP, JSR -- -- -- -- -- -- -- -- -- -- RTS -- -- -- -- -- -- -- -- -- -- TRAPA -- -- -- -- -- -- -- -- -- -- -- -- RTE -- -- -- -- -- -- -- -- -- -- -- -- SLEEP -- -- -- -- -- -- -- -- -- -- -- -- LDC B B W W W W -- W W -- -- -- STC -- B W W W W -- W W -- -- -- -- ANDC, ORC, XORC B -- -- -- -- -- -- -- -- -- -- -- -- NOP -- -- -- -- -- -- -- -- -- -- -- -- Block data transfer -- -- -- -- -- -- -- -- -- -- -- -- Arithmetic operations MULXS, DIVXU, DIVXS Logic operations System control -- BW Rev. 3.00 Sep 14, 2005 page 31 of 910 REJ09B0258-0300 Section 2 CPU 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register or address register) (EAd) Destination operand (EAs) Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag of CCR C C (carry) flag of CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition - Subtraction x Multiplication / Division AND logical OR logical Exclusive OR logical Move NOT (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7). Rev. 3.00 Sep 14, 2005 page 32 of 910 REJ09B0258-0300 Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size* Function MOV (EAs) Rd, Rs (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) Rd Cannot be used in this LSI. MOVTPE B Rs (EAs) Cannot be used in this LSI. POP W/L @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @-SP. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Sep 14, 2005 page 33 of 910 REJ09B0258-0300 Section 2 CPU Table 2.4 Arithmetic Operation Instructions Instruction Size* Function ADD,SUB Rd Rs Rd, Rd #IMM Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register. Use the SUBX or ADD instruction.) ADDX, SUBX B INC, DEC B/W/L ADDS, SUBS L DAA, DAS B MULXU B/W Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rev. 3.00 Sep 14, 2005 page 34 of 910 REJ09B0258-0300 Section 2 CPU Instruction Size* Function EXTS Rd (sign extension) Rd W/L Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit. EXTU W/L Rd (zero extension) Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.5 Logic Operation Instructions Instruction Size* Function AND Rd Rs Rd, Rd #IMM Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L Rd Rd Takes the one's complement (logical complement) of general register contents. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Sep 14, 2005 page 35 of 910 REJ09B0258-0300 Section 2 CPU Table 2.6 Shift Instructions Instruction Size* Function SHAL, SHAR B/W/L Rd (shift) Rd SHLL, SHLR B/W/L Rd (shift) Rd ROTL, ROTR B/W/L Rd (rotate) Rd ROTXL, ROTXR B/W/L Performs an arithmetic shift on general register contents. Performs a logical shift on general register contents. Rotates general register contents. Rd (rotate) Rd Rotates general register contents, including the carry bit. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Sep 14, 2005 page 36 of 910 REJ09B0258-0300 Section 2 CPU Table 2.7 Bit Manipulation Instructions Instruction Size* Function BSET 1 (<bit-No.> of <EAd>) B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register. BCLR B 0 (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register. BNOT B (<bit-No.> of <EAd>) (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register. BTST B (<bit-No.> of <EAd>) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register. BAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIAND B C [ (<bit-No.> of <EAd>)] C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C (<bit-No.> of <EAd>) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C [ (<bit-No.> of <EAd>)] C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BXOR B C (<bit-No.> of <EAd>) C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. Rev. 3.00 Sep 14, 2005 page 37 of 910 REJ09B0258-0300 Section 2 CPU Instruction Size* Function BIXOR C [ (<bit-No.> of <EAd>)] C B Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B (<bit-No.> of <EAd>) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B C (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte Rev. 3.00 Sep 14, 2005 page 38 of 910 REJ09B0258-0300 Section 2 CPU Table 2.8 Branching Instructions Instruction Size Function Bcc Branches to a specified address if address specified condition is met. The branching conditions are listed below. -- Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never BHI High CZ=0 BLS Low or same CZ=1 Bcc (BHS) Carry clear (high or same) C = 0 BCS (BLO) Carry set (low) C=1 BNE Not equal Z=0 BEQ Equal Z=1 BVC Overflow clear V=0 BVS Overflow set V=1 BPL Plus N=0 BMI Minus N=1 BGE Greater or equal NV=0 BLT Less than NV=1 BGT Greater than Z (N V) = 0 BLE Less or equal Z (N V) = 1 JMP -- Branches unconditionally to a specified address BSR -- Branches to a subroutine at a specified address JSR -- Branches to a subroutine at a specified address RTS -- Returns from a subroutine Rev. 3.00 Sep 14, 2005 page 39 of 910 REJ09B0258-0300 Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA -- Starts trap-instruction exception handling RTE -- Returns from an exception-handling routine SLEEP -- Causes a transition to the power-down state LDC B/W (EAs) CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. ANDC B CCR #IMM CCR ORC B CCR #IMM CCR Logically ANDs the condition code register with immediate data. Logically ORs the condition code register with immediate data. XORC B CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data. NOP -- PC + 2 PC Only increments the program counter. Note: * Size refers to the operand size. B: Byte W: Word Rev. 3.00 Sep 14, 2005 page 40 of 910 REJ09B0258-0300 Section 2 CPU Table 2.10 Block Transfer Instruction Instruction Size Function EEPMOV.B -- if R4L 0 then repeat @ER5+ @ER6+, R4L - 1 R4L until R4L = 0 else next; EEPMOV.W -- if R4 0 then repeat @ER5+ @ER6+, R4 - 1 R4 until R4 = 0 else next; Block transfer instruction. This instruction transfers the number of data bytes specified by R4L or R4, starting from the address indicated by ER5, to the location starting at the address indicated by ER6. At the end of the transfer, the next instruction is executed. 2.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first 4 bits of the instruction. Some instructions have two operation fields. Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the first 8 bits are 0 (H'00). Condition Field: Specifies the branching condition of Bcc instructions. Figure 2.9 shows examples of instruction formats. Rev. 3.00 Sep 14, 2005 page 41 of 910 REJ09B0258-0300 Section 2 CPU Operation field only op NOP, RTS, etc. Operation field and register fields op rn rm ADD.B Rn, Rm, etc. Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm EA (disp) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:8 Figure 2.9 Instruction Formats 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used to access registers with write-only bits, or to access ports. Step 1 Description Read Read one data byte at the specified address 2 Modify Modify one bit in the data byte 3 Write Write the modified data byte back to the specified address Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under the following conditions. P47, P46: Input pins P45 - P40: Output pins The intended purpose of this BCLR instruction is to switch P40 from output to input. Rev. 3.00 Sep 14, 2005 page 42 of 910 REJ09B0258-0300 Section 2 CPU Before Execution of BCLR Instruction P47 P46 P45 P44 P43 P42 P41 P40 Input/output Input Input Output Output Output Output Output Output DDR 0 0 1 1 1 1 1 1 P42 P41 P40 Execution of BCLR Instruction BCLR #0, @P4DDR ;Clear bit 0 in data direction register After Execution of BCLR Instruction P47 P46 P45 P44 P43 Input/output Output Output Output Output Output Output Output Input DDR 1 1 1 1 1 1 1 0 Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction. As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR are set to 1, making P47 and P46 output pins. The BCLR instruction can be used to clear flags in the on-chip registers to 0. In an interrupthandling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead of time. Rev. 3.00 Sep 14, 2005 page 43 of 910 REJ09B0258-0300 Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16, ERn)/@(d:24, ERn) 4 Register indirect with post-increment Register indirect with pre-decrement @ERn+ @-ERn 5 Absolute address @aa:8/@aa:16/@aa:24 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8, PC)/@(d:16, PC) 8 Memory indirect @@aa:8 1 Register Direct--Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2 Register Indirect--@ERn: The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand. 3 Register Indirect with Displacement--@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit displacement contained in the instruction code is added to the contents of an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev. 3.00 Sep 14, 2005 page 44 of 910 REJ09B0258-0300 Section 2 CPU 4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn: * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result become the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the resulting register value should be even. 5 Absolute Address--@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible address ranges. Table 2.12 Absolute Address Access Ranges Absolute Address 1-Mbyte Modes 16-Mbyte Modes 8 bits (@aa:8) H'FFF00 to H'FFFFF (1048320 to 1048575) H'FFFF00 to H'FFFFFF (16776960 to 16777215) 16 bits (@aa:16) H'00000 to H'07FFF, H'F8000 to H'FFFFF (0 to 32767, 1015808 to 1048575) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF (0 to 32767, 16744448 to 16777215) 24 bits (@aa:24) H'00000 to H'FFFFF (0 to 1048575) H'000000 to H'FFFFFF (0 to 16777215) 6 Immediate--#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data specifying a vector address. Rev. 3.00 Sep 14, 2005 page 45 of 910 REJ09B0258-0300 Section 2 CPU 7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is signextended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 8 Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to 255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area. For further details see section 5, Interrupt Controller. Specified by @aa:8 Reserved Branch address Figure 2.10 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address. See section 2.5.2, Memory Data Formats. 2.7.2 Effective Address Calculation Table 2.13 explains how an effective address is calculated in each addressing mode. In the 1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to generate a 20-bit effective address. Rev. 3.00 Sep 14, 2005 page 46 of 910 REJ09B0258-0300 4 3 2 r r r op r Register indirect with pre-decrement @-ERn op Register indirect with post-increment @ERn+ Register indirect with post-increment or pre-decrement op Register indirect with displacement @(d:16, ERn)/@(d:24, ERn) op Register indirect (@ERn) rm rn Register direct (Rn) 1 op Addressing Mode and Instruction Format No. 31 31 1 for a byte operand, 2 for a word operand, 4 for a longword operand 1, 2, or 4 General register contents 1, 2, or 4 General register contents disp General register contents General register contents Sign extension 31 31 Effective Address Calculation Table 2.13 Effective Address Calculation 0 0 0 0 23 23 23 23 Operand is general register contents Effective Address 0 0 0 0 Section 2 CPU Rev. 3.00 Sep 14, 2005 page 47 of 910 REJ09B0258-0300 Rev. 3.00 Sep 14, 2005 page 48 of 910 REJ09B0258-0300 7 6 5 No. abs abs abs IMM op disp Program-counter relative @(d:8, PC) or @(d:16, PC) op Immediate #xx:8, #xx:16, or #xx:32 op @aa:24 op @aa:16 op Absolute address @aa:8 Addressing Mode and Instruction Format disp PC contents Sign extension 23 Effective Address Calculation 0 16 15 H'FFFF 8 7 23 Operand is immediate data 23 Sign extension 23 23 Effective Address 0 0 0 0 Section 2 CPU Memory indirect @@aa:8 8 abs Legend r, rm, rn: op: disp: IMM: abs: abs Register field Operation field Displacement Immediate data Absolute address op Advanced mode op Normal mode Addressing Mode and Instruction Format No. 31 8 7 abs 0 H'0000 8 7 abs 0 0 15 0 Memory contents H'0000 Memory contents 23 23 Effective Address Calculation 23 23 16 15 H'00 Effective Address 0 0 Section 2 CPU Rev. 3.00 Sep 14, 2005 page 49 of 910 REJ09B0258-0300 Section 2 CPU 2.8 Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing states. Figure 2.13 indicates the state transitions. Processing states Program execution state The CPU executes program instructions in sequence Exception-handling state A transient state in which the CPU executes a hardware sequence (saving PC and CCR, fetching a vector, etc.) in response to a reset, interrupt, or other exception Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU Reset state The CPU and all on-chip supporting modules are initialized and halted Power-down state Sleep mode The CPU is halted to conserve power Software standby mode Hardware standby mode Figure 2.11 Processing States Rev. 3.00 Sep 14, 2005 page 50 of 910 REJ09B0258-0300 Section 2 CPU 2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt and trap exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition code register. Types of Exception Handling and Their Priority: Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their priority. Trap instruction exceptions are accepted at all times in the program execution state. Table 2.14 Exception Handling Types and Priority Priority Type of Exception Detection Timing Start of Exception Handling High Reset Synchronized with clock Exception handling starts immediately when RES changes from low to high Interrupt End of instruction execution or end of exception handling* When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Trap instruction When TRAPA instruction Exception handling starts when a trap is executed (TRAPA) instruction is executed Low Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. Figure 2.12 classifies the exception sources. For further details about exception sources, vector numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt Controller. Rev. 3.00 Sep 14, 2005 page 51 of 910 REJ09B0258-0300 Section 2 CPU Reset External interrupts Exception sources Interrupt Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2.12 Classification of Exception Sources Bus request End of bus release Program execution state End of bus release Bus request Exception handling source Bus-released state End of exception handling Interrupt source Exception-handling state NMI, IRQ 0 , IRQ 1, or IRQ 2 interrupt SLEEP instruction with SSBY = 0 Sleep mode SLEEP instruction with SSBY = 1 Software standby mode RES = "High" Reset state *1 STBY="High", RES ="Low" Hardware standby mode *2 Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. Figure 2.13 State Transitions Rev. 3.00 Sep 14, 2005 page 52 of 910 REJ09B0258-0300 Section 2 CPU 2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during the reset exception-handling sequence and immediately after it ends. Interrupt Exception Handling and Trap Instruction Exception Handling: When these exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the program counter and condition code register on the stack. Next, if the UE bit in the system control register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then the CPU fetches a start address from the exception vector table and execution branches to that address. Figure 2.14 shows the stack after the exception-handling sequence. Rev. 3.00 Sep 14, 2005 page 53 of 910 REJ09B0258-0300 Section 2 CPU SP-4 SP (ER7) SP-3 SP+1 SP-2 SP+2 SP-1 SP+3 Stack area SP (ER7) Before exception handling starts CCR PC SP+4 Pushed on stack Even address After exception handling ends Legend CCR: Condition code register SP: Stack pointer Notes: 1. PC is the address of the first instruction executed after the return from the exception-handling routine. 2. Registers must be saved and restored by word access or longword access, starting at an even address. Figure 2.14 Stack Structure after Exception Handling 2.8.5 Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the DRAM interface, and an external bus master. While the bus is released, the CPU halts except for internal operations. Interrupt requests are not accepted. For details see section 6.10, Bus Arbiter. 2.8.6 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details see section 12, Watchdog Timer. Rev. 3.00 Sep 14, 2005 page 54 of 910 REJ09B0258-0300 Section 2 CPU 2.8.7 Power-Down State In the power-down state the CPU stops operating to conserve power. There are three modes: sleep mode, software standby mode, and hardware standby mode. Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop immediately after execution of the SLEEP instruction, but the contents of CPU registers are retained. Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. For further information see section 20, Power-Down State. Rev. 3.00 Sep 14, 2005 page 55 of 910 REJ09B0258-0300 Section 2 CPU 2.9 Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (o). The interval from one rise of the system clock to the next rise is referred to as a "state." A memory cycle or bus cycle consists of two or three states. The CPU uses different methods to access on-chip memory, the on-chip supporting modules, and the external address space. Access to the external address space can be controlled by the bus controller. 2.9.2 On-Chip Memory Access Timing On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin states. Bus cycle T1 state T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2.15 On-Chip Memory Access Cycle Rev. 3.00 Sep 14, 2005 page 56 of 910 REJ09B0258-0300 Section 2 CPU T1 T2 Address bus AS , RD, HWR , LWR Address High High impedance D15 to D0 Figure 2.16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting module access timing. Figure 2.18 indicates the pin states. Bus cycle T1 state T2 state T3 state Address bus Read access Address Internal read signal Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.17 Access Cycle for On-Chip Supporting Modules Rev. 3.00 Sep 14, 2005 page 57 of 910 REJ09B0258-0300 Section 2 CPU T1 T2 T3 Address bus AS , RD, HWR , LWR Address High High impedance D15 to D0 Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in two or three states. For details see section 6, Bus Controller. Rev. 3.00 Sep 14, 2005 page 58 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3068F has seven operating modes (modes 1 to 7) that are selected by the mode pins (MD2 to MD0) as indicated in table 3.1. The input at these pins determines the size of the address space and the initial bus mode. Table 3.1 Operating Mode Selection Description Mode Pins Operating Mode MD2 MD1 MD0 Address Space Initial Bus On-Chip Mode*1 ROM On-Chip RAM -- 0 0 0 -- -- -- -- Mode 1 0 0 1 Expanded mode 8 bits Disabled Enabled*2 Mode 2 0 1 0 Expanded mode 16 bits Disabled Enabled*2 Mode 3 0 1 1 Expanded mode 8 bits Disabled Enabled*2 Mode 4 1 0 0 Expanded mode 16 bits Disabled Enabled*2 Mode 5 1 0 1 Expanded mode 8 bits Enabled Enabled*2 Mode 6 1 1 0 Single-chip normal mode -- Enabled Enabled Mode 7 1 1 1 Single-chip advanced mode -- Enabled Enabled Notes: 1. In modes 1 to 5, an 8-bit or 16-bit data bus can be selected on a per-area basis by settings made in the area bus width control register (ABWCR). For details see section 6, Bus Controller. 2. If the RAME bit in SYSCR is cleared to 0, these addresses become external addresses. For the address space size there are three choices: 64 kbytes, 1 Mbyte, or 16 Mbyte.The external data bus is either 8 or 16 bits wide depending on ABWCR settings. If 8-bit access is selected for all areas, 8-bit bus mode is used. For details see section 6, Bus Controller. Modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum address space of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes. Rev. 3.00 Sep 14, 2005 page 59 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes Mode 5 is an externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space of 16 Mbytes. Modes 6 and 7 are single-chip modes that operate using the on-chip ROM, RAM, and registers, and makes all I/O ports available. Mode 6 supports a maximum address space of 64 kbytes. Mode 7 supports a maximum address space of 1 Mbyte. The H8/3068F can be used only in modes 1 to 7. The inputs at the mode pins must select one of these seven modes. The inputs at the mode pins must not be changed during operation. 3.1.2 Register Configuration The H8/3068F has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers. Table 3.2 Registers Address* Name Abbreviation R/W Initial Value H'EE011 Mode control register MDCR R Undetermined H'EE012 System control register SYSCR R/W H'09 Note: * Lower 20 bits of the address in advanced mode. Rev. 3.00 Sep 14, 2005 page 60 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes 3.2 Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3068F. Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- MDS2 MDS1 MDS0 Initial value 1 1 0 0 0 --* --* --* Read/Write -- -- -- -- -- R R R Reserved bits Reserved bits Mode select 2 to 0 Bits indicating the current operating mode Note: * Determined by pins MD2 to MD0. Bits 7 and 6--Reserved: These bits can not be modified and are always read as 1. Bits 5 to 3--Reserved: These bits can not be modified and are always read as 0. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched into these bits when MDCR is read. Rev. 3.00 Sep 14, 2005 page 61 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes 3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3068F. Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 UE NMIEG SSOE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W RAM enable Enables or disables on-chip RAM Software standby output port enable Selects the output state of the address bus and bus control signals in software standby mode NMI edge select Selects the valid edge of the NMI input User bit enable Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit Standby timer select 2 to 0 These bits select the waiting time at recovery from software standby mode Software standby Enables transition to software standby mode Bit 7--Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 20, Power-Down State.) When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear this bit, write 0. Bit 7 SSBY Description 0 SLEEP instruction causes transition to sleep mode 1 SLEEP instruction causes transition to software standby mode Rev. 3.00 Sep 14, 2005 page 62 of 910 REJ09B0258-0300 (Initial value) Section 3 MCU Operating Modes Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate. For further information about waiting time selection, see section 20.4.3, Selection of Waiting Time for Exit from Software Standby Mode. Bit 6 STS2 Bit 5 STS1 Bit 4 STS0 Description 0 0 0 Waiting time = 8,192 states 0 0 1 Waiting time = 16,384 states 0 1 0 Waiting time = 32,768 states 0 1 1 Waiting time = 65,536 states 1 0 0 Waiting time = 131,072 states 1 0 1 Waiting time = 262,144 states 1 1 0 Waiting time = 1,024 states 1 1 1 Illegal setting (Initial value) Bit 3--User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR is used as an interrupt mask bit 1 UI bit in CCR is used as a user bit (Initial value) Bit 2--NMI Edge Select (NMIEG): Selects the valid edge of the NMI input. Bit 2 NMIEG Description 0 An interrupt is requested at the falling edge of NMI 1 An interrupt is requested at the rising edge of NMI (Initial value) Rev. 3.00 Sep 14, 2005 page 63 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes Bit 1--Software Standby Output Port Enable (SSOE): Specifies whether the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as outputs or fixed high, or placed in the high-impedance state in software standby mode. Bit 1 SSOE Description 0 In software standby mode, the address bus and bus control signals are all highimpedance (Initial value) 1 In software standby mode, the address bus retains its output state and bus control signals are fixed high Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by the rising edge of the RES signal. It is not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled 3.4 Operating Mode Descriptions 3.4.1 Mode 1 (Initial value) Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. 3.4.2 Mode 2 Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits. 3.4.3 Mode 3 Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to Rev. 3.00 Sep 14, 2005 page 64 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes 16 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register (BRCR). (In this mode A20 is always used for address output.) 3.4.4 Mode 4 Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20 is always used for address output.) 3.4.5 Mode 5 Ports 1, 2, and 5 and part of port A can function as address pins A23 to A0, permitting access to a maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set to 1. For A23 to A20 output, write 0 in bits 7 to 4 of BRCR. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. 3.4.6 Mode 6 This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available. Mode 6 supports a maximum address space of 64 kbytes. 3.4.7 Mode 7 This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available. Mode 7 supports a 1-Mbyte address space. Rev. 3.00 Sep 14, 2005 page 65 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes 3.5 Pin Functions in Each Operating Mode The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 Pin Functions in Each Mode Port Port 1 Mode 1 Mode 2 A7 to A0 Mode 3 A7 to A0 Mode 4 A7 to A0 Mode 5 A7 to A0 Mode 6 Mode 7 2 P17 to P10 P17 to P10 2 P17 to P10* Port 2 A15 to A8 A15 to A8 A15 to A8 A15 to A8 P27 to P20* P27 to P20 P27 to P20 Port 3 D15 to D8 D15 to D8 D15 to D8 D15 to D8 D15 to D8 P37 to P30 P37 to P30 1 P47 to P40 P47 to P40 2 P53 to P50 P53 to P50 PA7 to PA4 PA7 to PA4 1 1 1 1 Port 4 P47 to P40* D7 to D0* P47 to P40* D7 to D0* P47 to P40* Port 5 A19 to A16 A19 to A16 A19 to A16 A19 to A16 P53 to P50* Port A PA7 to PA4 PA7 to PA4 PA6 to PA4, A20*3 PA6 to PA4, A20*3 4 PA7 to PA4* Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function as P47 to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode. 2. Initial state. These pins become address output pins when the corresponding bits in the data direction registers (P1DDR, P2DDR, P5DDR) are set to 1. 3. Initial state. A20 is always an address output pin. PA6 to PA4 are switched over to A23 to A21 output by writing 0 in bits 7 to 5 of BRCR. 4. Initial state. PA7 to PA4 are switched over to A23 to A20 output by writing 0 in bits 7 to 4 of BRCR. Rev. 3.00 Sep 14, 2005 page 66 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes 3.6 Memory Map in Each Operating Mode Figure 3.1 to 3.2 show a memory maps of the H8/3068F. The address space is divided into eight areas. The EMC bit in BCR can be read and written to select either of the two memory maps. For details, see section 6.2.5, Bus Control Register (BCR). The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4. The address locations of the on-chip RAM and on-chip registers differ between the 64-kbyte mode (mode 6), the 1-Mbyte modes (modes 1, 2, and 7), and the 16-Mbyte modes (modes 3, 4, and 5). The address range specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs. 3.6.1 Note on Reserved Areas The H8/3068F memory map includes reserved areas to which read/write access is prohibited. Note that normal operation is not guaranteed if the following reserved areas are accessed. The reserved area in the internal I/O register space. The H8/3068F internal I/O register space includes a reserved area to which access is prohibited. For details see Appendix B, Internal I/O Registers. Rev. 3.00 Sep 14, 2005 page 67 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes H'EE0FF H'F8000 H'FBF1F H'FBF20 H'FFFE9 H'FFFEA H'FFFFF Area 1 Area 1 Area 2 H'3FFFFF H'400000 Area 3 Area 2 Area 4 H'5FFFFF H'600000 Area 5 Area 6 H'7FFFFF H'800000 Area 7 Internal I/O registers (2) External address space External address space Area 3 Area 4 H'9FFFFF H'A00000 External address space On-chip RAM* 16-bit absolute addresses H'1FFFFF H'200000 Internal I/O registers (1) H'FFF00 H'FFF1F H'FFF20 Area 0 Area 0 Area 5 16-bit absolute addresses H'EE000 H'007FFF H'BFFFFF H'C00000 Area 6 H'DFFFFF H'E00000 H'FEE000 Area 7 Internal I/O registers (1) H'FEE0FF H'FF8000 H'FFBF1F H'FFBF20 H'FFFF00 H'FFFF1F H'FFFF20 H'FFFFE9 H'FFFFEA H'FFFFFF External address space On-chip RAM* Internal I/O registers (2) External address space 16-bit absolute addresses H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'0000FF Memory-indirect branch addresses H'07FFF Vector area 8-bit absolute addresses H'000FF Modes 3 and 4 (16-Mbyte expanded modes with on-chip ROM disabled) H'000000 16-bit absolute addresses Vector area 8-bit absolute addresses H'00000 Memory-indirect branch addresses Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3.1(1) H8/3068F Memory Map in Each Operating Mode Rev. 3.00 Sep 14, 2005 page 68 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes H'DFFF H'E000 Area 0 Area 3 H'E720 On-chip RAM Area 5 H'FF00 Area 6 H'FF1F H'FF20 Area 7 Internal I/O registers (2) H'FFFF Internal I/O registers (1) H'EE0FF H'F8000 H'FBF20 On-chip RAM H'FFF00 16-bit absolute addresses External address space H'EE000 H'FFF1F H'FFF20 H'FFFE9 H'FFFFF Internal I/O registers(2) 16-bit absolute addresses Area 4 8-bit absolute addresses H'FFFFE9 H'FFFFEA Internal I/O registers (2) H'07FFF H'5FFFF External address space H'FFFF1F H'FFFF20 On-chip ROM H'E0FF Area 2 H'FEE0FF H'FFBF1F H'FFBF20 On-chip RAM* H'FFFF00 H'000FF Internal I/O registers (1) Area 1 Internal I/O registers (1) H'FF8000 Vector area 16-bit absolute addresses On-chip ROM H'FFE9 H'FEE000 H'FFFFFF H'00FF H'00000 Memory-indirect branch addresses H'007FFF H'05FFFF H'060000 H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000 External address space H'7FFFFF H'800000 H'9FFFFF H'A00000 H'BFFFFF H'C00000 H'DFFFFF H'E00000 Vector area Mode 7 (single-chip advanced mode) 8-bit absolute addresses On-chip ROM H'0000 Memory-indirect branch addresses H'0000FF Mode 6 (single-chip normal mode) 8-bit absolute addresses Vector area 16-bit absolute addresses H'000000 Memory-indirect branch addresses Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3.1(2) H8/3068F Memory Map in Each Operating Mode (EMC = 1) Rev. 3.00 Sep 14, 2005 page 69 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 Area 0 Area 0 H'1FFFFF H'200000 Area 1 Area 2 External address space Area 1 H'3FFFFF H'400000 Area 3 External address Area 2 space Area 4 H'5FFFFF H'600000 Area 5 Area 6 Area 3 Area 7 H'7FFFFF H'800000 Area 4 Internal I/O registers (1) H'9FFFFF H'A00000 External address space Area 5 H'F8000 H'FFF00 H'FFF80 H'FFFE0 H'FFFFF On-chip RAM (16 kbytes minus 96 bytes) Internal I/O registers (2) External address space On-chip RAM (96 bytes) Internal I/O registers (3) 16-bit absolute addresses H'FFE80 H'BFFFFF H'C00000 8-bit absolute addresses H'FBEE0 16-bit absolute addresses H'0000FF H'007FFF H'EE000 H'EE100 Vector area Area 6 H'DFFFFF H'E00000 Area 7 H'FEE000 H'FEE100 H'FF8000 Internal I/O registers (1) External address space H'FFBEE0 On-chip RAM (16 kbytes minus 96 bytes) H'FFFE80 H'FFFF00 H'FFFF80 H'FFFFE0 Internal I/O registers (2) External address space On-chip RAM (96 bytes) Internal I/O registers (3) 16-bit absolute addresses H'07FFF H'000000 8-bit absolute addresses H'000FF 16-bit absolute addresses Vector area Memory-indirect branch addresses H'00000 Memory-indirect branch addresses Modes 3 and 4 (16-Mbyte expanded modes with on-chip ROM disabled) Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'FFFFFF Figure 3.2(1) H8/3068F Memory Map in Each Operating Mode (EMC = 0) Rev. 3.00 Sep 14, 2005 page 70 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes On-chip ROM (384 kbytes) H'007FFF Vector area H'000FF On-chip ROM H'07FFF 16-bit absolute addresses H'0000FF H'00000 Memory-indirect branch addresses Vector area Mode 7 (single-chip advanced mode) 16-bit absolute addresses H'000000 Memory-indirect branch addresses Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'05FFFF H'060000 H'5FFFF H'60000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 External address Area 2 space H'5FFFFF H'600000 Area 3 H'7FFFFF H'800000 H'EE000 Area 4 H'9FFFFF H'A00000 H'EE100 Area 5 H'FBEE0 Area 6 H'DFFFFF H'E00000 H'FFE80 Area 7 H'FF8000 H'FFF00 Internal I/O registers (1) H'FFF80 External address space H'FFFE0 H'FFBEE0 H'FFFF80 H'FFFFE0 Internal I/O registers (2) External address space On-chip RAM (96 bytes) Internal I/O registers (3) 8-bit absolute addresses H'FFFF00 On-chip RAM (96 bytes) Internal I/O registers (3) 16-bit absolute addresses H'FFFFF On-chip RAM (16 kbytes minus 96 bytes) H'FFFE80 Internal I/O registers (2) 8-bit absolute addresses H'FEE100 On-chip RAM (16 kbytes minus 96 bytes) 16-bit absolute addresses H'F8000 H'BFFFFF H'C00000 H'FEE000 Internal I/O registers (1) H'FFFFFF Figure 3.2(2) H8/3068F Memory Map in Each Operating Mode (EMC = 0) Rev. 3.00 Sep 14, 2005 page 71 of 910 REJ09B0258-0300 Section 3 MCU Operating Modes Rev. 3.00 Sep 14, 2005 page 72 of 910 REJ09B0258-0300 Section 4 Exception Handling Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are accepted at all times in the program execution state. Table 4.1 Exception Types and Priority Priority Exception Type Start of Exception Handling High Reset Starts immediately after a low-to-high transition at the RES pin Interrupt Interrupt requests are handled when execution of the current instruction or handling of the current exception is completed Low 4.1.2 Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA) Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows. 1. The program counter (PC) and condition code register (CCR) are pushed onto the stack. 2. The CCR interrupt mask bit is set to 1. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. Rev. 3.00 Sep 14, 2005 page 73 of 910 REJ09B0258-0300 Section 4 Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. * Reset External interrupts: NMI, IRQ 0 to IRQ5 Exception sources * Interrupts * Trap instruction Internal interrupts: 36 interrupts from on-chip supporting modules Figure 4.1 Exception Sources Rev. 3.00 Sep 14, 2005 page 74 of 910 REJ09B0258-0300 Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Address*1 Exception Source Vector Number Advanced Mode Normal Mode Reset 0 H'0000 to H'0003 H'0000 to H'0001 Reserved for system use 1 H'0004 to H'0007 H'0002 to H'0003 2 H'0008 to H'000B H'0004 to H'0005 3 H'000C to H'000F H'0006 to H'0007 4 H'0010 to H'0013 H'0008 to H'0009 5 H'0014 to H'0017 H'000A to H'000B 6 H'0018 to H'001B H'000C to H'000D External interrupt (NMI) 7 H'001C to H'001F H'000E to H'000F Trap instruction (4 sources) 8 H'0020 to H'0023 H'0010 to H'0011 9 H'0024 to H'0027 H'0012 to H'0013 10 H'0028 to H'002B H'0014 to H'0015 11 H'002C to H'002F H'0016 to H'0017 External interrupt IRQ0 12 H'0030 to H'0033 H'0018 to H'0019 External interrupt IRQ1 13 H'0034 to H'0037 H'001A to H'001B External interrupt IRQ2 14 H'0038 to H'003B H'001C to H'001D External interrupt IRQ3 15 H'003C to H'003F H'001E to H'001F External interrupt IRQ4 16 H'0040 to H'0043 H'0020 to H'0021 External interrupt IRQ5 17 H'0044 to H'0047 H'0022 to H'0023 Reserved for system use 18 H'0048 to H'004B H'0024 to H'0025 19 H'004C to H'004F H'0026 to H'0027 20 to 63 H'0050 to H'0053 to H'00FC to H'00FF H'0028 to H'0029 to H'007E to H'007F 2 Internal interrupts* Notes: 1. Lower 16 bits of the address. 2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table. Rev. 3.00 Sep 14, 2005 page 75 of 910 REJ09B0258-0300 Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the RES pin changes from low to high. The chip can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer. 4.2.2 Reset Sequence The chip enters the reset state when the RES pin goes low. To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 10 system clock () cycles. When the flash memory and flash memory R versions are used, the RES pin must be held low for at least 20 system clock cycles. See appendix D.2, Pin States at Reset, for the states of the pins in the reset state. When the RES pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows. * The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit is set to 1 in CCR. * The contents of the reset vector address (H'0000 to H'0003 in advanced mode, H'0000 to H'0001 in normal mode) are read, and program execution starts from the address indicated in the vector address. Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in modes 2 and 4. Figure 4.4 shows the reset sequence in mode 6. Rev. 3.00 Sep 14, 2005 page 76 of 910 REJ09B0258-0300 (2) (4) (3) (6) (5) (8) (7) Internal processing Address of reset vector: (1) = H'000000, (3) = H'000001, (5) = H'000002, (7) = H'000003 Start address (contents of reset exception handling vector address) Start address First instruction of program High (1) Note: After a reset, the wait-state controller inserts three wait states in every bus cycle. (1), (3), (5), (7) (2), (4), (6), (8) (9) (10) D15 to D8 HWR , LWR RD Address bus RES Vector fetch (10) (9) Prefetch of first program instruction Section 4 Exception Handling Figure 4.2 Reset Sequence (Modes 1 and 3) Rev. 3.00 Sep 14, 2005 page 77 of 910 REJ09B0258-0300 Section 4 Exception Handling Internal processing Vector fetch Prefetch of first program instruction RES Address bus (1) (3) (5) RD HWR , LWR D15 to D0 (1), (3) (2), (4) (5) (6) High (2) (4) (6) Address of reset vector: (1) = H'000000, (3) = H'000002 Start address (contents of reset exception handling vector address) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle. Figure 4.3 Reset Sequence (Modes 2 and 4) Rev. 3.00 Sep 14, 2005 page 78 of 910 REJ09B0258-0300 Section 4 Exception Handling Vector fetch Internal processing Prefetch of first program instruction RES Internal address bus (1) (2) Internal read signal Internal write signal Internal data bus (16 bits wide) (2) (3) (1) Address of reset vector (H'0000) (2) Start address (contents of reset exception handling vector address) (3) First instruction of program Figure 4.4 Reset Sequence (Mode 6) 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. The first instruction of the program is always executed immediately after the reset state ends. This instruction should initialize the stack pointer (example: MOV.L #xx:32, SP). Rev. 3.00 Sep 14, 2005 page 79 of 910 REJ09B0258-0300 Section 4 Exception Handling 4.3 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ0 to IRQ5), and 36 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication interface (SCI), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt and is always accepted*. Interrupts are controlled by the interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt priority registers A and B (IPRA and IPRB) in the interrupt controller. Note: * In the flash memory and flash memory R versions, NMI input is sometimes disabled. For details see section18.9, NMI Input Disable Conditions. For details on interrupts see section 5, Interrupt Controller. External interrupts NMI (1) IRQ 0 to IRQ 5 (6) Internal interrupts WDT*1 (1) DRAM interface*2 (1) 16-bit timer (9) 8-bit timer (8) DMAC (4) SCI (12) A/D converter (1) Interrupts Notes: Numbers in parentheses are the number of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at every counter overflow. 2. When the DRAM interface is used as an interval timer, it generates an interrupt request at compare match. Figure 4.5 Interrupt Sources and Number of Interrupts Rev. 3.00 Sep 14, 2005 page 80 of 910 REJ09B0258-0300 Section 4 Exception Handling 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code. Rev. 3.00 Sep 14, 2005 page 81 of 910 REJ09B0258-0300 Section 4 Exception Handling 4.5 Stack Status after Exception Handling Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP-4 SP-3 SP-2 SP-1 SP (ER7) SP (ER7) SP+1 SP+2 SP+3 SP+4 Stack area Before exception handling CCR CCR* PC H PC L Even address After exception handling Pushed on stack a. Normal mode SP-4 SP-3 SP-2 SP-1 SP (ER7) SP (ER7) SP+1 SP+2 SP+3 SP+4 Stack area Before exception handling CCR PC E PC H PC L Even address After exception handling Pushed on stack b. Advanced mode Legend PCE: Bits 23 to 16 of program counter (PC) PCH: Bits 15 to 8 of program counter (PC) PCL: Bits 7 to 0 of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: * Ignored at return. 1. PC indicates the address of the first instruction that will be executed after return. 2. Registers must be saved in word or longword size at even addresses. Figure 4.6 Stack after Completion of Exception Handling Rev. 3.00 Sep 14, 2005 page 82 of 910 REJ09B0258-0300 Section 4 Exception Handling 4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3068F regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.7 shows an example of what happens when the SP value is odd. Rev. 3.00 Sep 14, 2005 page 83 of 910 REJ09B0258-0300 Section 4 Exception Handling CCR SP R1L H'FFFEFA H'FFFEFB SP PC PC H'FFFEFC H'FFFEFD H'FFFEFF SP TRAPA instruction executed SP set to H'FFFEFF MOV. B R1L, @-ER7 Data saved above SP CCR contents lost Legend CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: The diagram illustrates modes 3 and 4. Figure 4.7 Operation when SP Value is Odd Rev. 3.00 Sep 14, 2005 page 84 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: * Interrupt priority registers (IPRs) for setting interrupt priorities * Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). * Three-level masking by the I and UI bits in the CPU condition code register (CCR) * Seven external interrupt pins NMI has the highest priority and is always accepted*; either the rising or falling edge can be selected. For each of IRQ0 to IRQ5, sensing of the falling edge or level sensing can be selected independently. Note: * In the flash memory and flash memory R versions, NMI input is sometimes disabled. For details see section18.9, NMI Input Disable Conditions. Rev. 3.00 Sep 14, 2005 page 85 of 910 REJ09B0258-0300 Section 5 Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. CPU ISCR IER IPRA, IPRB NMI input IRQ input section ISR IRQ input OVF TME . . . . . . . TEI TEIE Priority decision logic Interrupt request Vector number . . . I UI Interrupt controller UE SYSCR Legend ISCR: IER: ISR: IPRA: IPRB: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B System control register Figure 5.1 Interrupt Controller Block Diagram Rev. 3.00 Sep 14, 2005 page 86 of 910 REJ09B0258-0300 CCR Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Abbreviation I/O Nonmaskable interrupt NMI External interrupt request 5 to 0 IRQ5 Function Input Nonmaskable interrupt*, rising edge or falling edge selectable to IRQ0 Input Maskable interrupts, falling edge or level sensing selectable Note: * NMI input is sometimes disabled. For details see 18.9, NMI Input Disabling Conditions. 5.1.4 Register Configuration Table 5.2 lists the registers of the interrupt controller. Table 5.2 Interrupt Controller Registers Address*1 Name Abbreviation R/W Initial Value H'EE012 System control register SYSCR R/W H'09 H'EE014 IRQ sense control register ISCR R/W H'00 H'EE015 IRQ enable register IER R/W H'00 H'EE016 IRQ status register ISR R/(W)*2 H'00 H'EE018 Interrupt priority register A IPRA R/W H'00 H'EE019 Interrupt priority register B IPRB R/W H'00 Notes: 1. Lower 20 bits of the address in advanced mode. 2. Only 0 can be written, to clear flags. Rev. 3.00 Sep 14, 2005 page 87 of 910 REJ09B0258-0300 Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register (SYSCR). SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 UE NMIEG SSOE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W RAM enable Software standby output port enable Standby timer select 2 to 0 Software standby Rev. 3.00 Sep 14, 2005 page 88 of 910 REJ09B0258-0300 NMI edge select Selects the NMI input edge User bit enable Selects whether to use the UI bit in CCR as a user bit or interrupt mask bit Section 5 Interrupt Controller Bit 3--User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI bit in CCR is used as user bit (Initial value) Bit 2--NMI Edge Select (NMIEG): Selects the NMI input edge. Bit 2 NMIEG Description 0 Interrupt is requested at falling edge of NMI input 1 Interrupt is requested at rising edge of NMI input 5.2.2 (Initial value) Interrupt Priority Registers A and B (IPRA, IPRB) IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority. Rev. 3.00 Sep 14, 2005 page 89 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 6 5 4 3 2 1 0 IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Priority level A0 Selects the priority level of 16-bit timer channel 2 interrupt requests Priority level A1 Selects the priority level of 16-bit timer channel 1 interrupt requests Priority level A2 Selects the priority level of 16-bit timer channel 0 interrupt requests Priority level A3 Selects the priority level of WDT, DRAM interface, and A/D converter interrupt requests Priority level A4 Selects the priority level of IRQ4 and IRQ 5 interrupt requests Priority level A5 Selects the priority level of IRQ 2 and IRQ 3 interrupt requests Priority level A6 Selects the priority level of IRQ1 interrupt requests Priority level A7 Selects the priority level of IRQ 0 interrupt requests IPRA is initialized to H'00 by a reset and in hardware standby mode. Rev. 3.00 Sep 14, 2005 page 90 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Bit 7--Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests. Bit 7 IPRA7 Description 0 IRQ0 interrupt requests have priority level 0 (low priority) 1 IRQ0 interrupt requests have priority level 1 (high priority) (Initial value) Bit 6--Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests. Bit 6 IPRA6 Description 0 IRQ1 interrupt requests have priority level 0 (low priority) 1 IRQ1 interrupt requests have priority level 1 (high priority) (Initial value) Bit 5--Priority Level A5 (IPRA5): Selects the priority level of IRQ2 and IRQ3 interrupt requests. Bit 5 IPRA5 Description 0 IRQ2 and IRQ3 interrupt requests have priority level 0 (low priority) 1 IRQ2 and IRQ3 interrupt requests have priority level 1 (high priority) (Initial value) Bit 4--Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ5 interrupt requests. Bit 4 IPRA4 Description 0 IRQ4 and IRQ5 interrupt requests have priority level 0 (low priority) 1 IRQ4 and IRQ5 interrupt requests have priority level 1 (high priority) (Initial value) Rev. 3.00 Sep 14, 2005 page 91 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Bit 3--Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and A/D converter interrupt requests. Bit 3 IPRA3 Description 0 WDT, DRAM interface, and A/D converter interrupt requests have priority level 0 (low priority) (Initial value) 1 WDT, DRAM interface, and A/D converter interrupt requests have priority level 1 (high priority) Bit 2--Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests. Bit 2 IPRA2 Description 0 16-bit timer channel 0 interrupt requests have priority level 0 (low priority)(Initial value) 1 16-bit timer channel 0 interrupt requests have priority level 1 (high priority) Bit 1--Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt requests. Bit 1 IPRA1 Description 0 16-bit timer channel 1 interrupt requests have priority level 0 (low priority)(Initial value) 1 16-bit timer channel 1 interrupt requests have priority level 1 (high priority) Bit 0--Priority Level A0 (IPRA0): Selects the priority level of 16-bit timer channel 2 interrupt requests. Bit 0 IPRA0 Description 0 16-bit timer channel 2 interrupt requests have priority level 0 (low priority)(Initial value) 1 16-bit timer channel 2 interrupt requests have priority level 1 (high priority) Rev. 3.00 Sep 14, 2005 page 92 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 6 5 4 3 2 1 0 IPRB7 IPRB6 IPRB5 IPRB3 IPRB2 IPRB1 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reserved bit Priority level B1 Selects the priority level of SCI channel 2 interrupt requests Priority level B2 Selects the priority level of SCI channel 1 interrupt requests Priority level B3 Selects the priority level of SCI channel 0 interrupt requests Reserved bit Priority level B5 Selects the priority level of DMAC interrupt requests (channels 0 and 1) Priority level B6 Selects the priority level of 8-bit timer channel 2, 3 interrupt requests Priority level B7 Selects the priority level of 8-bit timer channel 0, 1 interrupt requests IPRB is initialized to H'00 by a reset and in hardware standby mode. Rev. 3.00 Sep 14, 2005 page 93 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Bit 7--Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt requests. Bit 7 IPRB7 Description 0 8-bit timer channel 0, 1 interrupt requests have priority level 0 (low priority)(Initial value) 1 8-bit timer channel 0, 1 interrupt requests have priority level 1 (high priority) Bit 6--Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests. Bit 6 IPRB6 Description 0 8-bit timer channel 2, 3 interrupt requests have priority level 0 (low priority)(Initial value) 1 8-bit timer channel 2, 3 interrupt requests have priority level 1 (high priority) Bit 5--Priority Level B5 (IPRB5): Selects the priority level of DMAC interrupt requests (channels 0 and 1). Bit 5 IPRB5 Description 0 DMAC interrupt requests (channels 0 and 1) have priority level 0 (low priority) (Initial value) 1 DMAC interrupt requests (channels 0 and 1) have priority level 1 (high priority) Bit 4--Reserved: This bit can be written and read, but it does not affect interrupt priority. Bit 3--Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit 3 IPRB3 Description 0 SCI0 interrupt requests have priority level 0 (low priority) 1 SCI0 interrupt requests have priority level 1 (high priority) Rev. 3.00 Sep 14, 2005 page 94 of 910 REJ09B0258-0300 (Initial value) Section 5 Interrupt Controller Bit 2--Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests. Bit 2 IPRB2 Description 0 SCI1 interrupt requests have priority level 0 (low priority) 1 SCI1 interrupt requests have priority level 1 (high priority) (Initial value) Bit 1--Priority Level B1 (IPRB1): Selects the priority level of SCI channel 2 interrupt requests. Bit 1 IPRB1 Description 0 SCI channel 2 interrupt requests have priority level 0 (low priority) 1 SCI channel 2 interrupt requests have priority level 1 (high priority) (Initial value) Bit 0--Reserved: This bit can be written and read, but it does not affect interrupt priority. Rev. 3.00 Sep 14, 2005 page 95 of 910 REJ09B0258-0300 Section 5 Interrupt Controller 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt requests. Bit 7 6 5 4 3 2 1 0 -- -- IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Reserved bits IRQ 5 to IRQ0 flags These bits indicate IRQ 5 to IRQ 0 interrupt request status Note: * Only 0 can be written, to clear flags. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6--Reserved: These bits can not be modified and are always read as 0. Bits 5 to 0--IRQ5 to IRQ0 Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to IRQ0 interrupt requests. Bits 5 to 0 IRQ5F to IRQ0F Description 0 [Clearing conditions] (Initial value) 0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1. IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out. IRQnSC = 1 and IRQn interrupt exception handling is carried out. 1 [Setting conditions] IRQnSC = 0 and IRQn input is low. IRQnSC = 1 and IRQn input changes from high to low. Note: n = 5 to 0 Rev. 3.00 Sep 14, 2005 page 96 of 910 REJ09B0258-0300 Section 5 Interrupt Controller 5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ5 to IRQ0 interrupt requests. Bit 7 6 5 4 3 2 1 0 IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reserved bits IRQ 5 to IRQ0 enable These bits enable or disable IRQ 5 to IRQ 0 interrupts IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6--Reserved: These bits can be written and read, but they do not enable or disable interrupts. Bits 5 to 0--IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits enable or disable IRQ5 to IRQ0 interrupts. Bits 5 to 0 IRQ5E to IRQ0E Description 0 IRQ5 to IRQ0 interrupts are disabled 1 IRQ5 to IRQ0 interrupts are enabled (Initial value) Rev. 3.00 Sep 14, 2005 page 97 of 910 REJ09B0258-0300 Section 5 Interrupt Controller 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ5 to IRQ0. Bit 7 6 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Reserved bits IRQ 5 to IRQ0 sense control These bits select level sensing or falling-edge sensing for IRQ 5 to IRQ 0 interrupts ISCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6--Reserved: These bits can be written and read, but they do not select level or falling-edge sensing. Bits 5 to 0--IRQ5 to IRQ0 Sense Control (IRQ5SC to IRQ0SC): These bits select whether interrupts IRQ5 to IRQ0 are requested by level sensing of pins IRQ5 to IRQ0, or by falling-edge sensing. Bits 5 to 0 IRQ5SC to IRQ0SC Description 0 Interrupts are requested when IRQ5 to IRQ0 inputs are low 1 Interrupts are requested by falling-edge input at IRQ5 to IRQ0 Rev. 3.00 Sep 14, 2005 page 98 of 910 REJ09B0258-0300 (Initial value) Section 5 Interrupt Controller 5.3 Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ0 to IRQ5) and 36 internal interrupts. 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ0 to IRQ5. Of these, NMI, IRQ0, IRQ1, and IRQ2 can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I and UI bits in CCR*. The NMIEG bit in SYSCR selects whether an interrupt is requested by the rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector number 7. Note: * NMI input is sometimes disabled. For details see section18.9, NMI Input Disabling Conditions. IRQ0 to IRQ5 Interrupts: These interrupts are requested by input signals at pins IRQ0 to IRQ5. The IRQ0 to IRQ5 interrupts have the following features. * ISCR settings can select whether an interrupt is requested by the low level of the input at pins IRQ0 to IRQ5, or by the falling edge. * IER settings can enable or disable the IRQ0 to IRQ5 interrupts. Interrupt priority levels can be assigned by four bits in IPRA (IPRA7 to IPRA4). * The status of IRQ0 to IRQ5 interrupt requests is indicated in ISR. The ISR flags can be cleared to 0 by software. Figure 5.2 shows a block diagram of interrupts IRQ0 to IRQ5. IRQnSC IRQnE IRQnF Edge/level sense circuit IRQn input S Q IRQn interrupt request R Clear signal Note: n = 5 to 0 Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5 Rev. 3.00 Sep 14, 2005 page 99 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). IRQn input pin IRQnF Note: n = 5 to 0 Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ0 to IRQ5 have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output. When using a pin for external interrupt input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, SCI input/output, or A/D external trigger input. 5.3.2 Internal Interrupts Thirty-Six internal interrupts are requested from the on-chip supporting modules. * Each on-chip supporting module has status flags for indicating interrupt status, and enable bits for enabling or disabling interrupts. * Interrupt priority levels can be assigned in IPRA and IPRB. * 16-bit timer, SCI, and A/D converter interrupt requests can activate the DMAC, in which case no interrupt request is sent to the interrupt controller, and the I and UI bits are disregarded. 5.3.3 Interrupt Vector Table Table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. In the default priority order, smaller vector numbers have higher priority. The priority of interrupts other than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order shown in table 5.3. Rev. 3.00 Sep 14, 2005 page 100 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Table 5.3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source Origin NMI External pins Vector Address* Vector Number Advanced Mode Normal Mode IPR 7 H'001C to H'001F H'000E to H'000F -- 12 H'0030 to H'0033 H'0018 to H'0019 IRQ1 13 H'0034 to H0037 H'001A to H'001B IPRA6 IRQ2 IRQ3 14 15 H'0038 to H'003B H'001C to H'001D IPRA5 H'003C to H'003F H'001E to H'001F IRQ4 IRQ5 16 17 H'0040 to H'0043 H'0044 to H'0047 IRQ0 H'0020 to H'0021 H'0022 to H'0023 Reserved -- 18 19 H'0048 to H'004B H'0024 to H'0025 H'004C to H'004F H'0026 to H'0027 WOVI (interval timer) Watchdog timer 20 H'0050 to H'0053 H'0028 to H'0029 CMI (compare match) DRAM interface 21 H'0054 to H'0057 H'002A to H'002B Reserved -- 22 H'0058 to H'005B H'002C to H'002D ADI (A/D end) A/D 23 H'005C to H'005F H'002E to H'002F IMIA0 (compare match/ input capture A0) IMIB0 (compare match/ input capture B0) OVI0 (overflow 0) 16-bit timer 24 channel 0 H'0060 to H'0063 H'0030 to H'0031 25 H'0064 to H'0067 H'0032 to H'0033 26 H'0068 to H'006B H'0034 to H'0035 Reserved -- 27 H'006C to H'006F H'0036 to H'0037 IMIA1 (compare match/ inputcapture A1) IMIB1 (compare match/ input capture B1) OVI1 (overflow 1) 16-bit timer 28 channel 1 H'0070 to H'0073 H'0038 to H'0039 29 H'0074 to H'0077 H'003A to H'003B 30 H'0078 to H'007B H'003C to H'003D Reserved -- 31 H'007C to H'007F H'003E to H'003F Priority High IPRA7 IPRA4 IPRA3 IPRA2 IPRA1 Low Note: * Lower 16 bits of the address. Rev. 3.00 Sep 14, 2005 page 101 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Vector Address* Vector Number Advanced Mode Normal Mode Interrupt Source Origin IMIA2 (compare match/ input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) 16-bit timer 32 channel 2 H'0080 to H'0083 H'0040 to H'0041 33 H'0084 to H'0087 H'0042 to H'0043 34 H'0088 to H'008B H'0044 to H'0045 Reserved -- 35 H'008C to H'008F H'0046 to H'0047 CMIA0 (compare match A0) CMIB0 (compare match B0) CMIA1/CMIB1 (compare match A1/B1) TOVI0/TOVI1 (overflow 0/1) 8-bit timer 36 channel 0/1 H'0090 to H'0093 H'0048 to H'0049 37 H'0094 to H'0097 H'004A to H'004B 38 H'0098 to H'009B H'004C to H'004D 39 H'009C to H'009F H'004E to H'004F CMIA2 (compare match A2) CMIB2 (compare match B2) CMIA3/CMIB3 (compare match A3/B3) TOVI2/TOVI3 (overflow 2/3) 8-bit timer 40 channel 2/3 H'00A0 to H'00A3 H'0050 to H'0051 41 H'00A4 to H'00A7 H'0052 to H'0053 42 H'00A8 to H'00AB H'0054 to H'0055 43 H'00AC to H'00AF H'0056 to H'0057 DEND0A DEND0B DEND1A DEND1B DMAC 44 45 46 47 H'00B0 to H'00B3 H'00B4 to H'00B7 H'00B8 to H'00BB H'00BC to H'00BF H'0058 to H'0059 IPRB5 H'005A to H'005B H'005C to H'005D H'005E to H'005F Reserved -- 48 49 50 51 H'00C0 to H'00C3 H'00C4 to H'00C7 H'00C8 to H'00CB H'00CC to H'00CF H'0060 to H'0061 H'0062 to H'0063 H'0064 to H'0065 H'0066 to H'0067 Note: * Lower 16 bits of the address. Rev. 3.00 Sep 14, 2005 page 102 of 910 REJ09B0258-0300 IPR Priority IPRA0 High IPRB7 IPRB6 -- Low Section 5 Interrupt Controller Interrupt Source Origin ERI0 (receive error 0) RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) SCI channel 0 ERI1 (receive error 1) RXI1 (receive data full 1) TXI1 (transmit data empty 1) TEI1 (transmit end 1) SCI channel 1 ERI2 (receive error 2) RXI2 (receive data full 2) TXI2 (transmit data empty 2) TEI2 (transmit end 2) SCI channel 2 Vector Address* Vector Number Advanced Mode Normal Mode IPR Priority 52 H'00D0 to H'00D3 H'0068 to H'0069 IPRB3 High 53 H'00D4 to H'00D7 H'006A to H'006B 54 H'00D8 to H'00DB H'006C to H'006D 55 H'00DC to H'00DF H'006E to H'006F 56 H'00E0 to H'00E3 H'0070 to H'0071 57 H'00E4 to H'00E7 H'0072 to H'0073 58 H'00E8 to H'00EB H'0074 to H'0075 59 H'00EC to H'00EF H'0076 to H'0077 60 H'00F0 to H'00F3 H'0078 to H'0079 61 H'00F4 to H'00F7 H'007A to H'007B 62 H'00F8 to H'00FB H'007C to H'007D 63 H'00FC to H'00FF H'007E to H'007F IPRB2 IPRB1 Low Note: * Lower 16 bits of the address. Rev. 3.00 Sep 14, 2005 page 103 of 910 REJ09B0258-0300 Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3068F handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I, and UI bits. NMI interrupts are always accepted except in the reset and hardware standby states*. IRQ interrupts and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests are ignored when the enable bits are cleared to 0. Note: * NMI input is sometimes disabled. For details see section 18.9, NMI Input Disabling Conditions. Table 5.4 UE, I, and UI Bit Settings and Interrupt Handling SYSCR CCR UE I UI Description 1 0 -- All interrupts are accepted. Interrupts with priority level 1 have higher priority. 1 -- No interrupts are accepted except NMI. 0 -- All interrupts are accepted. Interrupts with priority level 1 have higher priority. 1 0 NMI and interrupts with priority level 1 are accepted. 1 No interrupts are accepted except NMI. 0 UE = 1: Interrupts IRQ0 to IRQ5 and interrupts from the on-chip supporting modules can all be masked by the I bit in the CPU's CCR. Interrupts are masked when the I bit is set to 1, and unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure 5.4 is a flowchart showing how interrupts are accepted when UE = 1. Rev. 3.00 Sep 14, 2005 page 104 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Program execution state No Interrupt requested? Yes Yes NMI No No Pending Priority level 1? Yes IRQ 0 No Yes IRQ 1 IRQ 0 No Yes No IRQ 1 Yes No Yes TEI2 TEI2 Yes Yes No I=0 Yes Save PC and CCR I 1 Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when UE = 1 Rev. 3.00 Sep 14, 2005 page 105 of 910 REJ09B0258-0300 Section 5 Interrupt Controller * If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. * When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. * The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held pending. * When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. * In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. * Next the I bit is set to 1 in CCR, masking all interrupts except NMI. * The vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. UE = 0: The I and UI bits in the CPU's CCR and the IPR bits enable three-level masking of IRQ0 to IRQ5 interrupts and interrupts from the on-chip supporting modules. * Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked when the I bit is cleared to 0. * Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and are unmasked when either the I bit or the UI bit is cleared to 0. For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to H'20, and IPRB is set to H'00 (giving IRQ2 and IRQ3 interrupt requests priority over other interrupts), interrupts are masked as follows: a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ2 > IRQ3 >IRQ0 ...). b. If I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 are unmasked. c. If I = 1 and UI = 1, all interrupts are masked except NMI. Rev. 3.00 Sep 14, 2005 page 106 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Figure 5.5 shows the transitions among the above states. I0 a. All interrupts are unmasked I0 b. Only NMI, IRQ 2 , and IRQ 3 are unmasked I 1, UI 0 Exception handling, or I 1, UI 1 UI 0 Exception handling, or UI 1 c. All interrupts are masked except NMI Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0. * If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. * When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. * The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted; interrupt requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1, only NMI is accepted; all other interrupt requests are held pending. * When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. * In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. * The I and UI bits are set to 1 in CCR, masking all interrupts except NMI. * The vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. Rev. 3.00 Sep 14, 2005 page 107 of 910 REJ09B0258-0300 Section 5 Interrupt Controller Program execution state No Interrupt requested? Yes Yes NMI No No Pending Priority level 1? Yes IRQ 0 No IRQ 0 Yes IRQ 1 No Yes No IRQ 1 Yes No Yes TEI2 TEI2 Yes Yes No I=0 No I=0 Yes Yes No UI = 0 Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt service routine Figure 5.6 Process Up to Interrupt Acceptance when UE = 0 Rev. 3.00 Sep 14, 2005 page 108 of 910 REJ09B0258-0300 (2) (1) (4) High (3) Instruction Internal prefetch processing (8) (7) (10) (9) (12) (11) Vector fetch (14) (13) (6), (8) PC and CCR saved to stack (9), (11) Vector address (10), (12) Starting address of interrupt service routine (contents of vector address) (13) Starting address of interrupt service routine; (13) = (10), (12) (14) First instruction of interrupt service routine (6) (5) Stack Prefetch of interrupt Internal service routine processing instruction Note: Mode 2, with program code and stack in external memory area accessed in two states via 16-bit bus. Instruction prefetch address (not executed; return address, same as PC contents) (2), (4) Instruction code (not executed) (3) Instruction prefetch address (not executed) (5) SP - 2 (7) SP - 4 (1) D15 to D0 HWR , LWR RD Address bus Interrupt request signal Interrupt level decision and wait for end of instruction 5.4.2 Interrupt accepted Section 5 Interrupt Controller Interrupt Sequence Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Sequence Rev. 3.00 Sep 14, 2005 page 109 of 910 REJ09B0258-0300 Section 5 Interrupt Controller 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time External Memory No. On-Chip Memory Item 1 8-Bit Bus 2 States 1 3 States 1 16-Bit Bus 2 States 1 3 States 2*1 1 Interrupt priority decision 2* 2* 2* 2* 2 Maximum number of states until end of current instruction 1 to 23*5 1 to 27*5 1 to 41*4,*6 1 to 23*5 1 to 25*4,*5 3 Saving PC and CCR to stack 4 8 12*4 4 6*4 4 Vector fetch 4 8 12*4 4 6*4 5 Instruction prefetch*2 4 8 12*4 4 6*4 6 3 4 4 4 4 4 19 to 41 31 to 57 43 to 83 19 to 41 25 to 49 Total Internal processing* Notes: 1. 1 state for internal interrupts. 2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine. 3. Internal processing after the interrupt is accepted and internal processing after vector fetch. 4. The number of states increases if wait states are inserted in external memory access. 5. Example for DIVXS.W Rs,ERd and MULXS.W Rs,ERd 6. Example for MOV.L @(d:24,ERs),ERd and MOV.L ERs,@(d:24,ERd) Rev. 3.00 Sep 14, 2005 page 110 of 910 REJ09B0258-0300 Section 5 Interrupt Controller 5.5 Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored. This also applies to the clearing of an interrupt flag to 0. Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in the 16-bit timer's TISRA register. TISRA write cycle by CPU IMIA exception handling Internal address bus TISRA address Internal write signal IMIEA IMIA IMFA interrupt signal Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction This type of contention will not occur if the interrupt is masked when the interrupt enable bit or flag is cleared to 0. Rev. 3.00 Sep 14, 2005 page 111 of 910 REJ09B0258-0300 Section 5 Interrupt Controller 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction. 5.5.3 Interrupts during EEPMOV Instruction Execution The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests. When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the transfer is completed, not even NMI. When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction. Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution: L1: EEPMOV.W MOV.W R4,R4 BNE L1 Rev. 3.00 Sep 14, 2005 page 112 of 910 REJ09B0258-0300 Section 6 Bus Controller Section 6 Bus Controller 6.1 Overview The H8/3068F has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function that controls the operation of the internal bus masters-the CPU, DMA controller (DMAC), and DRAM interface and can release the bus to an external device. 6.1.1 Features The features of the bus controller are listed below. * Manages external address space in area units Manages the external space as eight areas (0 to 7) of 128 kbytes in 1M-byte modes, or 2 Mbytes in 16-Mbyte modes Bus specifications can be set independently for each area DRAM/burst ROM interfaces can be set * Basic bus interface Chip select (CS0 to CS7) can be output for areas 0 to 7 8-bit access or 16-bit access can be selected for each area Two-state access or three-state access can be selected for each area Program wait states can be inserted for each area Pin wait insertion capability is provided * DRAM interface DRAM interface can be set for areas 2 to 5 Row address/column address multiplexed output (8/9/10 bits) 2-CAS byte access mode Burst operation (fast page mode) TP cycle insertion to secure RAS precharging time Choice of CAS-before-RAS refreshing or self-refreshing * Burst ROM interface Burst ROM interface can be set for area 0 Selection of two- or three-state burst access Rev. 3.00 Sep 14, 2005 page 113 of 910 REJ09B0258-0300 Section 6 Bus Controller * Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle * Bus arbitration function A built-in bus arbiter grants the bus right to the CPU, DMAC, DRAM interface, or an external bus master * Other features Refresh counter (refresh timer) can be used as interval timer Choice of two address update modes Rev. 3.00 Sep 14, 2005 page 114 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS7 ABWCR ASTCR BCR Internal address bus Area decoder Chip select control signals CSCR Internal signals ADRCR Bus mode control signal Bus size control signal Bus control circuit Internal data bus Access state control signal Wait state controller WAIT Wait request signal WCRH WCRL Internal signals CPU bus request signal DMAC bus request signal DRAM interface bus request signal CPU bus acknowledge signal DMAC bus acknowledge signal DRAM interface bus acknowledge signal BRCR Bus arbiter BACK BREQ DRAM interface DRAM control DRCRA DRCRB RTMCSR RTCNT Legend ABWCR ASTCR WCRH WCRL BRCR CSCR DRCRA DRCRB RTMCSR RTCNT RTCOR ADRCR BCR RTCOR : Bus width control register : Access state control register : Wait control register H : Wait control register L : Bus release control register : Chip select control register : DRAM control register A : DRAM control register B : Refresh timer control/status register : Refresh timer counter : Refresh time constant register : Address control register : Bus control register Figure 6.1 Block Diagram of Bus Controller Rev. 3.00 Sep 14, 2005 page 115 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation I/O Function Output Strobe signals selecting areas 0 to 7 Output Strobe signal indicating valid address output on the address bus Address strobe CS0 to CS7 AS Read RD Output Strobe signal indicating reading from the external address space High write HWR Output Strobe signal indicating writing to the external address space, with valid data on the upper data bus (D15 to D8) Low write LWR Output Strobe signal indicating writing to the external address space, with valid data on the lower data bus (D7 to D0) Wait WAIT Input Wait request signal for access to external three-state access areas Bus request BREQ Input Request signal for releasing the bus to an external device Bus acknowledge BACK Output Acknowledge signal indicating release of the bus to an external device Chip select 0 to 7 Rev. 3.00 Sep 14, 2005 page 116 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the bus controller's registers. Table 6.2 Bus Controller Registers Address*1 Name Abbreviation R/W Initial Value H'EE020 Bus width control register ABWCR R/W H'FF*2 H'EE021 Access state control register ASTCR R/W H'FF H'EE022 Wait control register H WCRH R/W H'FF H'EE023 Wait control register L WCRL R/W H'FF H'EE013 Bus release control register BRCR R/W H'FE*3 H'EE01F Chip select control register CSCR R/W H'0F H'EE01E Address control register ADRCR R/W H'FF H'EE024 Bus control register BCR R/W H'C6 H'EE026 DRAM control register A DRCRA R/W H'10 H'EE027 DRAM control register B DRCRB R/W H'08 4 H'EE028 Refresh timer control/status register RTMCSR R(W)* H'07 H'EE029 Refresh timer counter RTCNT R/W H'00 Refresh time constant register RTCOR R/W H'FF H'EE02A Notes: 1. 2. 3. 4. Lower 20 bits of the address in advanced mode. In modes 2 and 4, the initial value is H'00. In modes 3 and 4, the initial value is H'EE. For Bit 7, only 0 can be written to clear the flag. Rev. 3.00 Sep 14, 2005 page 117 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.2 Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. 7 Bit ABW7 Modes Initial value 1 1, 3, 5, 6, and 7 Read/Write R/W Modes 2 and 4 Initial value 0 Read/Write R/W 6 5 4 3 2 1 0 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus mode: the upper data bus (D15 to D8) is valid, and port 4 is an input/output port. When at least one bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D15 to D0). In modes 1, 3, 5, 6, and 7, ABWCR is initialized to H'FF by a reset and in hardware standby mode. In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access for the corresponding areas. Bits 7 to 0 ABW7 to ABW0 Description 0 Areas 7 to 0 are 16-bit access areas 1 Areas 7 to 0 are 8-bit access areas ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip memory and registers is fixed, and does not depend on ABWCR settings. These settings are therefore meaningless in the single-chip modes (modes 6 and 7). Rev. 3.00 Sep 14, 2005 page 118 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.2.2 Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. 7 6 5 4 3 2 1 0 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W Bit R/W R/W Bits selecting number of states for access to each area ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is accessed in two or three states. Bits 7 to 0 AST7 to AST0 Description 0 Areas 7 to 0 are accessed in two states 1 Areas 7 to 0 are accessed in three states (Initial value) ASTCR specifies the number of states in which external areas are accessed. On-chip memory and registers are accessed in a fixed number of states that does not depend on ASTCR settings. These settings are therefore meaningless in the single-chip modes (modes 6 and 7). When the corresponding area is designated as DRAM space by bits DRAS2 to DRAS0 in DRAM control register A (DRCRA), the number of access states does not depend on the AST bit setting. When an AST bit is cleared to 0, programmable wait insertion is not performed. Rev. 3.00 Sep 14, 2005 page 119 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. On-chip memory and registers are accessed in a fixed number of states that does not depend on WCRH/WCRL settings. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode. WCRH 7 6 5 4 3 2 1 0 W71 W70 W61 W60 W51 W50 W41 W40 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W Bit R/W R/W Bits 7 and 6--Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 Bit 6 W70 Description 0 0 Program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (Initial value) 1 Rev. 3.00 Sep 14, 2005 page 120 of 910 REJ09B0258-0300 Section 6 Bus Controller Bits 5 and 4--Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 Bit 4 W60 Description 0 0 Program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (Initial value) 1 Bits 3 and 2--Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 Bit 2 W50 Description 0 0 Program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (Initial value) 1 Bits 1 and 0--Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 Bit 0 W40 Description 0 0 Program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (Initial value) 1 Rev. 3.00 Sep 14, 2005 page 121 of 910 REJ09B0258-0300 Section 6 Bus Controller WCRL 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W Bit R/W R/W Bits 7 and 6--Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 Bit 6 W30 Description 0 0 Program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (Initial value) 1 Bits 5 and 4--Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 Bit 4 W20 Description 0 0 Program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (Initial value) 1 Rev. 3.00 Sep 14, 2005 page 122 of 910 REJ09B0258-0300 Section 6 Bus Controller Bits 3 and 2--Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 Bit 2 W10 Description 0 0 Program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (Initial value) 1 Bits 1 and 0--Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 Bit 0 W00 Description 0 0 Program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (Initial value) 1 Rev. 3.00 Sep 14, 2005 page 123 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A20 and enables or disables release of the bus to an external device. Bit Modes 1, 2, 6, and 7 7 6 5 4 3 2 1 0 A23E A22E A21E A20E -- -- -- BRLE 1 1 1 1 1 1 1 0 Read/Write -- -- -- -- -- -- -- R/W Initial value Modes Initial value 1 3 and 4 Read/Write R/W Mode 5 Initial value 1 1 0 1 1 1 0 R/W R/W -- -- -- -- R/W 1 1 1 1 1 1 0 R/W R/W R/W -- -- -- R/W 1 Read/Write R/W Reserved bits Address 23 to 20 enable These bits enable PA7 to PA4 to be used for A23 to A20 address output Bus release enable Enables or disables release of the bus to an external device BRCR is initialized to H'FE in modes 1, 2, 5, 6, and 7, and to H'EE in modes 3 and 4, by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin. Writing 0 in this bit enables A23 output from PA4. In modes other than 3, 4, and 5, this bit cannot be modified and PA4 has its ordinary port functions. Bit 7 A23E Description 0 PA4 is the A23 address output pin 1 PA4 is an input/output pin Rev. 3.00 Sep 14, 2005 page 124 of 910 REJ09B0258-0300 (Initial value) Section 6 Bus Controller Bit 6--Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin. Writing 0 in this bit enables A22 output from PA5. In modes other than 3, 4, and 5, this bit cannot be modified and PA5 has its ordinary port functions. Bit 6 A22E Description 0 PA5 is the A22 address output pin 1 PA5 is an input/output pin (Initial value) Bit 5--Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin. Writing 0 in this bit enables A21 output from PA6. In modes other than 3, 4, and 5, this bit cannot be modified and PA6 has its ordinary port functions. Bit 5 A21E Description 0 PA6 is the A21 address output pin 1 PA6 is an input/output pin (Initial value) Bit 4--Address 20 Enable (A20E): Enables PA7 to be used as the A20 address output pin. Writing 0 in this bit enables A20 output from PA7. This bit can only be modified in mode 5. Bit 4 A20E Description 0 PA7 is the A20 address output pin (Initial value when in mode 3 or 4) 1 PA7 is an input/output pin (Initial value when in mode 1, 2, 5, 6, or 7) Bits 3 to 1--Reserved: These bits cannot be modified and are always read as 1. Bit 0--Bus Release Enable (BRLE): Enables or disables release of the bus to an external device. Bit 0 BRLE Description 0 The bus cannot be released to an external device BREQ and BACK can be used as input/output pins 1 The bus can be released to an external device (Initial value) Rev. 3.00 Sep 14, 2005 page 125 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.2.5 Bus Control Register (BCR) 7 6 ICIS1 ICIS0 Initial value 1 1 0 Read/Write R/W R/W R/W Bit 5 4 3 2 1 0 EMC RDEA WAITE 0 1 1 0 R/W R/W R/W BROME BRSTS1 BRSTS0 0 R/W R/W BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the address map, selects the area division unit, and enables or disables WAIT pin input. BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read cycles for different areas. Bit 7 ICIS1 Description 0 No idle cycle inserted in case of consecutive external read cycles for different areas 1 Idle cycle inserted in case of consecutive external read cycles for different areas (Initial value) Bit 6--Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read and write cycles. Bit 6 ICIS0 Description 0 No idle cycle inserted in case of consecutive external read and write cycles 1 Idle cycle inserted in case of consecutive external read and write cycles (Initial value) Bit 5--Burst ROM Enable (BROME): Selects whether area 0 is a burst ROM interface area. Bit 5 BROME Description 0 Area 0 is a basic bus interface area 1 Area 0 is a burst ROM interface area Rev. 3.00 Sep 14, 2005 page 126 of 910 REJ09B0258-0300 (Initial value) Section 6 Bus Controller Bit 4--Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycle states for the burst ROM interface. Bit 4 BRSTS1 Description 0 Burst access cycle comprises 2 states 1 Burst access cycle comprises 3 states (Initial value) Bit 3--Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access (burst access on match of address bits above A3) (Initial value) 1 Max. 8 words in burst access (burst access on match of address bits above A4) Bit 2--Expansion Memory Map Control (EMC): Selects either of the two memory maps. Bit 2 EMC Description 0 Selects the memory map shown in figure 3.2: see section 3.6, Memory Map in Each Operating Mode 1 Selects the memory map shown in figure 3.1: see section 3.6, Memory Map in Each Operating Mode (Initial value) When EMC is cleared to 0, addresses of some internal I/O registers are moved. For details, refer to appendix B.2, Address List (when EMC = 0). This bit is invalid in mode 6. In mode 6 and when the RDEA bit is 0, EMC must not be cleared to 0. Rev. 3.00 Sep 14, 2005 page 127 of 910 REJ09B0258-0300 Section 6 Bus Controller Bit 1--Area Division Unit Select (RDEA): Selects the memory map area division units. This bit is valid in modes 3, 4, and 5, and is invalid in modes 1, 2, 6, and 7. When the EMC bit is 0, RDEA must not be cleared to 0. Bit 1 RDEA Description 0 Area divisions are as follows: 1 Area 0: 2 Mbytes Area 4: 1.93 Mbytes Area 1: 2 Mbytes Area 5: 4 kbytes Area 2: 8 Mbytes Area 6: 23.75 kbytes Area 3: 2 Mbytes Area 7: 22 bytes Areas 0 to 7 are the same size (2 Mbytes) (Initial value) Bit 0--WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT pin. Bit 0 WAITE Description 0 WAIT pin wait input is disabled, and the WAIT pin can be used as an input/output port 1 WAIT pin wait input is enabled Rev. 3.00 Sep 14, 2005 page 128 of 910 REJ09B0258-0300 (Initial value) Section 6 Bus Controller 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals (CS7 to CS4). If output of a chip select signal is enabled by a setting in this register, the corresponding pin functions as a chip select signal (CS7 to CS4) output regardless of any other settings. CSCR cannot be modified in single-chip mode. Bit 7 6 5 4 3 2 1 0 CS7E CS6E CS5E CS4E -- -- -- -- Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W -- -- -- -- R/W Reserved bits Chip select 7 to 4 enable These bits enable or disable chip select signal output CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 4--Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of the corresponding chip select signal. Bit n CSnE Description 0 Output of chip select signal 1 CSn is disabled Output of chip select signal CSn is enabled (Initial value) Note: n = 7 to 4 Bits 3 to 0--Reserved: These bits cannot be modified and are always read as 1. Rev. 3.00 Sep 14, 2005 page 129 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.2.7 DRAM Control Register A (DRCRA) 7 6 5 4 3 2 1 0 DRAS2 DRAS1 DRAS0 -- BE RDM SRFMD RFSHE Initial value 0 0 0 1 0 0 0 0 Read/Write R/W R/W R/W -- R/W R/W R/W Bit R/W DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface function, and the access mode, and enables or disables self-refreshing and refresh pin output. DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 5--DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5 are to function as DRAM interface areas (DRAM space) in expanded mode, and at the same time select the RAS output pin corresponding to each DRAM space. Description Bit 7 Bit 6 Bit 5 DRAS2 DRAS1 DRAS0 Area 5 Area 4 Area 3 Area 2 0 0 1 1 0 1 0 Normal Normal Normal Normal 1 Normal Normal Normal DRAM space (CS2) 0 Normal Normal DRAM space (CS3) DRAM space (CS2) 1 Normal Normal DRAM space (CS2)* DRAM space (CS2)* 0 Normal DRAM space (CS4) DRAM space (CS3) DRAM space (CS2) 1 DRAM space (CS5) DRAM space (CS4) DRAM space (CS3) DRAM space (CS2) 0 DRAM space (CS4)* DRAM space (CS4)* DRAM space (CS2)* DRAM space (CS2)* 1 DRAM space (CS2)* DRAM space (CS2)* DRAM space (CS2)* DRAM space (CS2)* Note: * A single CSn pin serves as a common RAS output pin for a number of areas. Unused CSn pins can be used as input/output ports. Rev. 3.00 Sep 14, 2005 page 130 of 910 REJ09B0258-0300 Section 6 Bus Controller When any of bits DRAS2 to DRAS0 is set to 1 in expanded mode, it is not possible to write to DRCRB, RTMCSR, RTCNT, or RTCOR. However, 0 can be written to the CMF flag in RTMCSR to clear the flag. When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than 000 must not be performed. Bit 4--Reserved: This bit cannot be modified and is always read as 1. Bit 3--Burst Access Enable (BE): Enables or disables burst access to DRAM space. DRAM space burst access is performed in fast page mode. Bit 3 BE Description 0 Burst disabled (always full access) 1 DRAM space access performed in fast page mode (Initial value) Bit 2--RAS Down Mode (RDM): Selects whether to wait for the next DRAM access with the RAS signal held low (RAS down mode), or to drive the RAS signal high again (RAS up mode), when burst access is enabled for DRAM space (BE = 1), and access to DRAM is interrupted. Caution is required when the HWR and LWR are used as the UCAS and LCAS output pins. For details, see RAS Down Mode and RAS Up Mode in section 6.5.10, Burst Operation. Bit 2 RDM Description 0 DRAM interface: RAS up mode selected 1 DRAM interface: RAS down mode selected (Initial value) Rev. 3.00 Sep 14, 2005 page 131 of 910 REJ09B0258-0300 Section 6 Bus Controller Bit 1--Self-Refresh Mode (SRFMD): Specifies DRAM self-refreshing in software standby mode. When any of areas 2 to 5 is designated as DRAM space, DRAM self-refreshing is possible when a transition is made to software standby mode after the SRFMD bit has been set to 1. The normal access state is restored when software standby mode is exited, regardless of the SRFMD setting. Bit 1 SRFMD Description 0 DRAM self-refreshing disabled in software standby mode 1 DRAM self-refreshing enabled in software standby mode (Initial value) Bit 0--Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1. Bit 0 RFSHE Description RFSH pin refresh signal output disabled (RFSH pin can be used as input/output port) RFSH pin refresh signal output enabled 0 1 6.2.8 (Initial value) DRAM Control Register B (DRCRB) 7 6 5 4 3 2 1 0 MXC1 MXC0 CSEL RCYCE -- TPC RCW RLW Initial value 0 0 0 0 1 0 0 0 Read/Write R/W R/W R/W -- R/W R/W Bit R/W R/W DRCRB is an 8-bit readable/writable register that selects the number of address multiplex column address bits for the DRAM interface, the column address strobe output pin, enabling or disabling of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state insertion between RAS and CAS, and enabling or disabling of wait state insertion in refresh cycles. DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 3.00 Sep 14, 2005 page 132 of 910 REJ09B0258-0300 Section 6 Bus Controller The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0. Bits 7 and 6--Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row address/column address multiplexing method used on the DRAM interface. In burst operation, the row address used for comparison is determined by the setting of these bits and the bus width of the relevant area set in ABWCR. Bit 7 MXC1 Bit 6 MXC0 Description 0 0 Column address: 8 bits Compared address: Modes 1, 2 Modes 3, 4, 5 1 8-bit access space A19 to A8 16-bit access space A19 to A9 8-bit access space A23 to A8 16-bit access space A23 to A9 8-bit access space A19 to A9 16-bit access space A19 to A10 8-bit access space A23 to A9 16-bit access space A23 to A10 8-bit access space A19 to A10 16-bit access space A19 to A11 8-bit access space A23 to A10 16-bit access space A23 to A11 Column address: 9 bits Compared address: Modes 1, 2 Modes 3, 4, 5 1 0 Column address: 10 bits Compared address: Modes 1, 2 Modes 3, 4, 5 1 Illegal setting Bit 5--CAS Output Pin Select (CSEL): Selects the UCAS and LCAS output pins when areas 2 to 5 are designated as DRAM space. Bit 5 CSEL 0 1 Description PB4 and PB5 selected as UCAS and LCAS output pins HWR and LWR selected as UCAS and LCAS output pins (Initial value) Rev. 3.00 Sep 14, 2005 page 133 of 910 REJ09B0258-0300 Section 6 Bus Controller Bit 4--Refresh Cycle Enable (RCYCE): Enables or disables CAS-before-RAS refresh cycle insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not inserted regardless of the setting of this bit. Bit 4 RCYCE Description 0 Refresh cycles disabled 1 DRAM refresh cycles enabled (Initial value) Bit 3--Reserved: This bit cannot be modified and is always read as 1. Bit 2--TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (TP) is to be used for DRAM read/write cycles and CAS-before-RAS refresh cycles. The setting of this bit does not affect the self-refresh function. Bit 2 TPC Description 0 1-state precharge cycle inserted 1 2-state precharge cycle inserted (Initial value) Bit 1--RAS-CAS Wait (RCW): Controls wait state (Trw) insertion between Tr and Tc1 in DRAM read/write cycles. The setting of this bit does not affect refresh cycles. Bit 1 RCW Description 0 Wait state (Trw) insertion disabled 1 One wait state (Trw) inserted (Initial value) Bit 0--Refresh Cycle Wait Control (RLW): Controls wait state (TRW) insertion for CASbefore-RAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles. Bit 0 RLW Description 0 Wait state (TRW ) insertion disabled 1 One wait state (TRW ) inserted Rev. 3.00 Sep 14, 2005 page 134 of 910 REJ09B0258-0300 (Initial value) Section 6 Bus Controller 6.2.9 Refresh Timer Control/Status Register (RTMCSR) 7 6 5 4 3 2 1 0 CMF CMIE CKS2 CKS1 CKS0 -- -- -- Initial value 0 0 0 0 0 1 1 1 Read/Write R(W)* R/W R/W R/W -- -- -- Bit R/W RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests. Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes. Bits 5 to 3 are initialized to 0 by a reset and in hardware standby mode; they are not initialized in software standby mode. Note: * Only 0 can be written to clear the flag. Bit 7--Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. Bit 7 CMF 0 1 Description Clearing conditions When the chip is reset and in standby mode Read CMF when CMF = 1, then write 0 in CMF (Initial value) Setting condition When RTCNT = RTCOR Bit 6--Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when any of areas 2 to 5 is designated as DRAM space. Bit 6 CMIE Description 0 The CMI interrupt requested by CMF is disabled 1 The CMI interrupt requested by CMF is enabled (Initial value) Rev. 3.00 Sep 14, 2005 page 135 of 910 REJ09B0258-0300 Section 6 Bus Controller Bits 5 to 3--Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 clocks obtained by dividing the system clock (). When the input clock is selected with bits CKS2 to CKS0, RTCNT begins counting up. Bit 5 Bit 4 Bit 3 CKS2 CKS1 CKS0 Description 0 0 1 1 0 1 0 Count operation halted 1 /2 used as counter clock (Initial value) 0 /8 used as counter clock 1 /32 used as counter clock 0 /128 used as counter clock 1 /512 used as counter clock 0 /2048 used as counter clock 1 /4096 used as counter clock Bits 2 to 0--Reserved: These bits cannot be modified and are always read as 1. 6.2.10 Refresh Timer Counter (RTCNT) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W RTCNT is an 8-bit readable/writable up-counter. RTCNT is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When RTCNT matches RTCOR (compare match), the CMF flag in RTMCSR is set to 1 and RTCNT is cleared to H'00. If the RCYCE bit in DRCRB is set to 1 at this time, a refresh cycle is started. Also, if the CMIE bit in RTMCSR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 136 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.2.11 Refresh Time Constant Register (RTCOR) Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W RTCOR is an 8-bit readable/writable register that determines the interval at which RTCNT is cleared. RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1 in RTMCSR, and RTCNT is simultaneously cleared to H'00. RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: Only byte access can be used on this register. Rev. 3.00 Sep 14, 2005 page 137 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.2.12 Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- ADRCTL Initial value 1 1 1 1 1 1 1 1 R/W -- -- -- -- -- -- -- R/W Bit Reserved bits Address control Selects address update mode 1 or address update mode 2 ADRCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 2--Reserved: These bits cannot be modified and are always read as 1. Bit 1--Reserved: This bit is always read as 1. Do not write 0 to this bit. Bit 0--Address Control (ADRCTL): Selects the address output method. Bit 0 ADRCTL Description 0 Address update mode 2 is selected 1 Address update mode 1 is selected Rev. 3.00 Sep 14, 2005 page 138 of 910 REJ09B0258-0300 (Initial value) Section 6 Bus Controller 6.3 Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1-Mbyte modes, or 2-Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the memory map. H' 00000 H' 000000 Area 0 (128 kbytes) H' 1FFFF Area 0 (2 Mbytes) H' 1FFFFF H' 20000 H' 200000 Area 1 (128 kbytes) H' 3FFFF Area 1 (2 Mbytes) H' 3FFFFF H' 40000 H' 400000 Area 2 (128 kbytes) H' 5FFFF Area 2 (2 Mbytes) H' 5FFFFF H' 60000 H' 600000 Area 3 (128 kbytes) H' 7FFFF Area 3 (2 Mbytes) H' 7FFFFF H' 80000 H' 800000 Area 4 (128 kbytes) H' 9FFFF Area 4 (2 Mbytes) H' 9FFFFF H' A0000 H' A00000 Area 5 (128 kbytes) H' BFFFF H' C0000 H' DFFFF Area 5 (2 Mbytes) H' BFFFFF H' C00000 Area 6 (128 kbytes) H' E0000 H' DFFFFF Area 6 (2 Mbytes) H' E00000 Area 7 (128 kbytes) Area 7 (2 Mbytes) H' FFFFF H' FFFFFF (a) 1-Mbyte modes (modes 1, and 2) (b) 16-Mbyte modes (modes 3, 4, and 5) Figure 6.2 Access Area Map for Each Operating Mode Chip select signals (CS0 to CS7) can be output for areas 0 to 7. The bus specifications for each area are selected in ABWCR, ASTCR, WCRH, and WCRL. In 16-Mbyte mode, the area division units can be selected with the RDEA bit in BCR. Rev. 3.00 Sep 14, 2005 page 139 of 910 REJ09B0258-0300 Section 6 Bus Controller Area 0 2 Mbytes Area 0 2 Mbytes Area 1 2 Mbytes Area 1 2 Mbytes 2 Mbytes H'000000 2 Mbytes H'1FFFFF H'200000 Area 2 2 Mbytes H'5FFFFF 2 Mbytes H'3FFFFF H'400000 Area 2 8 Mbytes 2 Mbytes H'600000 Area 3 2 Mbytes 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes 2 Mbytes H'9FFFFF H'A00000 Area 5 2 Mbytes Area 6 2 Mbytes Area 3 2 Mbytes Area 7 1.93 Mbytes Area 4 1.93 Mbytes On-chip registers (1) On-chip registers (1) 2 Mbytes H'BFFFFF H'C00000 H'DFFFFF H'E00000 H'FEE000 H'FEE0FF H'FEE100 Reserved 39.75 kbytes H'FF7FFF H'FF8000 Area 6 23.75 kbytes On-chip RAM 4 kbytes On-chip RAM 4 kbytes* On-chip registers (2) On-chip registers (2) Area 7 22 bytes Area 7 22 bytes (A) Memory map when RDEA = 1 (b) Memory map when RDEA = 0 H'FFEF1F H'FFEF20 H'FFFF1F H'FFFF20 H'FFFFE9 H'FFFFEA H'FFFFFF Note: * Area 6 when the RAME bit is cleared. Figure 6.3 Memory Map in 16-Mbyte Mode Rev. 3.00 Sep 14, 2005 page 140 of 910 REJ09B0258-0300 Absolute address 8 bits H'FFFEFF H'FFFF00 2 Mbytes Area 7 67.5 kbytes Absolute address 16 bits Area 5 4 kbytes H'FF8FFF H'FF9000 Section 6 Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip memory and registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16bit access, 16-bit bus mode is set. Number of Access States: Two or three access states can be selected with ASTCR. An area for which two-state access is selected functions as a two-state access space, and an area for which three-state access is selected functions as a three-state access space. DRAM space is accessed in four states regardless of the ASTCR settings. When two-state access space is designated, wait insertion is disabled. Number of Program Wait States: When three-state access space is designated in ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. When ASTCR is cleared to 0 for DRAM space, a program wait (Tc1-Tc2 wait) is not inserted. Also, no program wait is inserted in burst ROM space burst cycles. Table 6.3 shows the bus specifications for each basic bus interface area. Rev. 3.00 Sep 14, 2005 page 141 of 910 REJ09B0258-0300 Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH/WCRL Bus Specifications (Basic Bus Interface) ABWn ASTn Wn1 Wn0 Bus Width Access States Program Wait States 0 0 -- -- 16 2 0 1 0 0 3 0 1 1 1 1 0 2 1 3 0 -- -- 1 0 0 1 8 2 0 3 0 1 1 0 2 1 3 Note: n = 7 to 0 6.3.3 Memory Interfaces The H8/3068F memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface is designated functions as DRAM space, and area 0 for which the burst ROM interface is designated functions as burst ROM space. Rev. 3.00 Sep 14, 2005 page 142 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.3.4 Chip Select Signals For each of areas 0 to 7, the H8/3068F can output a chip select signal (CS0 to CS7) that goes low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing of a CSn signal. Output of CS0 to CS3: Output of CS0 to CS3 is enabled or disabled in the data direction register (DDR) of the corresponding port. In the expanded modes with on-chip ROM disabled, a reset leaves pin CS0 in the output state and pins CS1 to CS3 in the input state. To output chip select signals CS1 to CS3, the corresponding DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins CS0 to CS3 in the input state. To output chip select signals CS0 to CS3, the corresponding DDR bits must be set to 1. For details, see section 8, I/O Ports. Output of CS4 to CS7: Output of CS4 to CS7 is enabled or disabled in the chip select control register (CSCR). A reset leaves pins CS4 to CS7 in the input state. To output chip select signals CS4 to CS7, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports. Address External address in area n CSn Figure 6.4 CSn Signal Output Timing (n = 0 to 7) When the on-chip ROM, on-chip RAM, and on-chip registers are accessed, CS0 to CS7 remain high. The CSn signals are decoded from the address signals. They can be used as chip select signals for SRAM and other devices. Rev. 3.00 Sep 14, 2005 page 143 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.3.5 Address Output Method The H8/3068F provides a choice of two address update methods: either the same method as in the previous H8/300H Series (address update mode 1), or a method in which address update is restricted to external space accesses or self-refresh cycles (address update mode 2). Figure 6.5 shows examples of address output in these two update modes. On-chip memory cycle External read cycle On-chip memory cycle External read cycle On-chip memory cycle Address update mode 1 Address update mode 2 RD Figure 6.5 Sample Address Output in Each Address Update Mode (Basic Bus Interface, 3-State Space) Address Update Mode 1: Address update mode 1 is compatible with the previous H8/300H Series. Addresses are always updated between bus cycles. Address Update Mode 2: In address update mode 2, address updating is performed only in external space accesses or self-refresh cycles. In this mode, the address can be retained between an external space read cycle and an instruction fetch cycle (on-chip memory) by placing the program in on-chip memory. Address update mode 2 is therefore useful when connecting a device that requires address hold time with respect to the rise of the RD strobe. Switching between address update modes 1 and 2 is performed by means of the ADRCTL bit in ADRCR. The initial value of ADRCR is the address update mode 1 setting, providing compatibility with the previous H8/300H Series. Rev. 3.00 Sep 14, 2005 page 144 of 910 REJ09B0258-0300 Section 6 Bus Controller Cautions: When using address update modes, the following points should be noted. * When address update mode 2 is selected, the address in an internal space (on-chip memory or internal I/O) access cycle is not output externally. * In order to secure address holding with respect to the rise of RD, when address update mode 2 is used an external space read access must be completed within a single access cycle. For example, in a word access to 8-bit access space, the bus cycle is split into two as shown in figure 6.6., and so there is not a single access cycle. In this case, address holding is not guaranteed at the rise of RD between the first (even address) and second (odd address) access cycles (area inside the ellipse in the figure). On-chip memory cycle Address update mode 2 External read cycle (8-bit space word access) Even address On-chip memory cycle Odd address RD Figure 6.6 Example of Consecutive External Space Accesses in Address Update Mode 2 * When address update mode 2 is selected, in a DRAM space CAS-before-RAS (CBR) refresh cycle the previous address is retained (the area 2 start address is not output). Rev. 3.00 Sep 14, 2005 page 145 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access area or 16-bit access area) and the data size. 8-Bit Access Areas: Figure 6.7 illustrates data alignment control for 8-bit access space. With 8bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size Word size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Area) 16-Bit Access Areas: Figure 6.8 illustrates data alignment control for 16-bit access areas. With 16-bit access areas, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. Rev. 3.00 Sep 14, 2005 page 146 of 910 REJ09B0258-0300 Section 6 Bus Controller In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus Lower data bus D15 D8 D7 D0 Byte size * Even address Byte size * Odd address Word size Longword size 1st bus cycle 2nd bus cycle Figure 6.8 Access Sizes and Data Alignment Control (16-Bit Access Area) 6.4.3 Valid Strobes Table 6.4 shows the data buses used, and the valid strobes, for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Rev. 3.00 Sep 14, 2005 page 147 of 910 REJ09B0258-0300 Section 6 Bus Controller Table 6.4 Data Buses Used and Valid Strobes Access Size Read/Write Address 8-bit access area Byte Read -- Write -- RD HWR 16-bit access Byte Read Even RD Area Valid Strobe Odd area Write Word Even HWR Odd LWR Read -- Write -- RD HWR, LWR Upper Data Bus Lower Data Bus (D15 to D8) (D7 to D0) Valid Invalid Undetermined data Valid Invalid Invalid Valid Valid Undetermined data Undetermined data Valid Valid Valid Valid Valid Notes: 1. Undetermined data means that unpredictable data is output. 2. Invalid means that the bus is in the input state and the input is ignored. 6.4.4 Memory Areas The initial state of each area is basic bus interface, three-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the following sections should be referred to for further details: 6.4, Basic Bus Interface, 6.5, DRAM Interface, 6.8, Burst ROM Interface. Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. The size of area 0 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5. Areas 1 and 6: In external expansion mode, areas 1 and 6 are entirely external space. When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 and 6. The size of areas 1 and 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5. Rev. 3.00 Sep 14, 2005 page 148 of 910 REJ09B0258-0300 Section 6 Bus Controller Areas 2 to 5: In external expansion mode, areas 2 to 5 are entirely external space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS signals. The size of areas 2 to 5 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5. Area 7: Area 7 includes the on-chip RAM and registers. In external expansion mode, the space excluding the on-chip RAM and registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. The size of area 7 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5. Rev. 3.00 Sep 14, 2005 page 149 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas Figure 6.9 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The LWR pin is always high. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus External address in area n CSn AS RD Read access D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write access D15 to D8 D7 to D0 Valid Undetermined data Note: n = 7 to 0 Figure 6.9 Bus Control Signal Timing for 8-Bit, Three-State-Access Area Rev. 3.00 Sep 14, 2005 page 150 of 910 REJ09B0258-0300 Section 6 Bus Controller 8-Bit, Two-State-Access Areas Figure 6.10 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The LWR pin is always high. Wait states cannot be inserted. Bus cycle T2 T1 Address bus External address in area n CSn AS RD Read access D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write access D15 to D8 Valid D7 to D0 Undetermined data Note: n = 7 to 0 Figure 6.10 Bus Control Signal Timing for 8-Bit, Two-State-Access Area Rev. 3.00 Sep 14, 2005 page 151 of 910 REJ09B0258-0300 Section 6 Bus Controller 16-Bit, Three-State-Access Areas Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D15 to D8) is used in accesses to even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus Even external address in area n CSn AS RD Read access D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write access D15 to D8 Valid D7 to D0 Undetermined data Note: n = 7 to 0 Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1) (Byte Access to Even Address) Rev. 3.00 Sep 14, 2005 page 152 of 910 REJ09B0258-0300 Section 6 Bus Controller Bus cycle T1 T2 T3 Address bus Odd external address in area n CSn AS RD Read access D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write access D15 to D8 Undetermined data D7 to D0 Valid Note: n = 7 to 0 Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address) Rev. 3.00 Sep 14, 2005 page 153 of 910 REJ09B0258-0300 Section 6 Bus Controller Bus cycle T1 T2 T3 Address bus External address in area n CSn AS RD Read access D15 to D8 Valid D7 to D0 Valid HWR LWR Write access D15 to D8 Valid D7 to D0 Valid Note: n = 7 to 0 Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access) Rev. 3.00 Sep 14, 2005 page 154 of 910 REJ09B0258-0300 Section 6 Bus Controller 16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D15 to D8) is used in accesses to even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait states cannot be inserted. Bus cycle T1 T2 Address bus Even external address in area n CSn AS RD Read access D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write access D15 to D8 Valid D7 to D0 Undetermined data Note: n = 7 to 0 Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1) (Byte Access to Even Address) Rev. 3.00 Sep 14, 2005 page 155 of 910 REJ09B0258-0300 Section 6 Bus Controller Bus cycle T1 T2 Address bus Odd external address in area n CSn AS RD Read access D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write access D15 to D8 Undetermined data D7 to D0 Valid Note: n = 7 to 0 Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address) Rev. 3.00 Sep 14, 2005 page 156 of 910 REJ09B0258-0300 Section 6 Bus Controller Bus cycle T1 T2 Address bus External address in area n CSn AS RD Read access D15 to D8 Valid D7 to D0 Valid HWR LWR Write access D15 to D8 Valid D7 to D0 Valid Note: n = 7 to 0 Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) (Word Access) 6.4.6 Wait Control When accessing external space, the H8/3068F can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: (1) program wait insertion and (2) pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in three-state access space, according to the settings of WCRH and WCRL. Rev. 3.00 Sep 14, 2005 page 157 of 910 REJ09B0258-0300 Section 6 Bus Controller Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of in the last T2 or TW state, another TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes high. This is useful when inserting four or more TW states, or when changing the number of TW states for different external devices. The WAITE bit setting applies to all areas. Pin waits cannot be inserted in DRAM space. Figure 6.17 shows an example of the timing for insertion of one program wait state in 3-state space. T1 Inserted by program wait Inserted by WAIT pin T2 Tw Tw Tw T3 WAIT Address bus AS RD Read access Data bus Read data HWR, LWR Write access Data bus Note: Write data indicates the timing of WAIT pin sampling. Figure 6.17 Example of Wait State Insertion Timing Rev. 3.00 Sep 14, 2005 page 158 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.5 DRAM Interface 6.5.1 Overview The H8/3068F is provided with a DRAM interface with functions for DRAM control signal (RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct connection of DRAM. In the expanded modes, external address space areas 2 to 5 can be designated as DRAM space accessed via the DRAM interface. A data bus width of 8 or 16 bits can be selected for DRAM space by means of a setting in ABWCR. When a 16-bit data bus width is selected, CAS is used for byte access control. In the case of x 16-bit organization DRAM, therefore, the 2-CAS type can be connected. A fast page mode is supported in addition to the normal read and write access modes. 6.5.2 DRAM Space and RAS Output Pin Settings Designation of areas 2 to 5 as DRAM space, and selection of the RAS output pin for each area designated as DRAM space, is performed by setting bits in DRCRA. Table 6.5 shows the correspondence between the settings of bits DRAS2 to DRAS0 and the selected DRAM space and RAS output pin. When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than 000 must not be performed. Rev. 3.00 Sep 14, 2005 page 159 of 910 REJ09B0258-0300 Section 6 Bus Controller Settings of Bits DRAS2 to DRAS0 and Corresponding DRAM Space (RAS Output Pin) Table 6.5 DRAS2 DRAS1 DRAS0 Area 5 Area 4 Area 3 Area 2 0 0 1 1 0 1 0 Normal space Normal space Normal space Normal space 1 Normal space Normal space Normal space DRAM space (CS2) 0 Normal space Normal space DRAM space (CS3) DRAM space (CS2) 1 Normal space Normal space DRAM space (CS2)* DRAM space (CS2)* 0 Normal space DRAM space (CS4) DRAM space (CS3) DRAM space (CS2) 1 DRAM space (CS5) DRAM space (CS4) DRAM space (CS3) DRAM space (CS2) 0 DRAM space (CS4)* DRAM space (CS4)* DRAM space (CS2)* DRAM space (CS2)* 1 DRAM space (CS2)* DRAM space (CS2)* DRAM space (CS2)* DRAM space (CS2)* Note: * A single CSn pin serves as a common RAS output pin for a number of areas. Unused CSn pins can be used as input/output ports. 6.5.3 Address Multiplexing When DRAM space is accessed, the row address and column address are multiplexed. The address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number of bits in the DRAM column address. Table 6.6 shows the correspondence between the settings of MXC1 and MXC0 and the address multiplexing method. Rev. 3.00 Sep 14, 2005 page 160 of 910 REJ09B0258-0300 Section 6 Bus Controller Table 6.6 Settings of Bits MXC1 and MXC0 and Address Multiplexing Method DRCRB Row address Address Pins MXC1 MXC0 Bits A23 to A13 A12 A11 A10 A9 A1 A0 0 A8 1 Column address Column Address -- A8 A7 A6 A5 A4 A3 A2 0 8 bits A23 to A13 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 1 9 bits A23 to A13 A12 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 0 10 bits A23 to A13 A12 A11 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 1 Illegal setting -- -- -- -- -- -- -- -- -- -- -- -- -- A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 -- -- -- Note: * Row address bit A20 is not multiplexed in 1-Mbyte mode. 6.5.4 Data Bus If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, x 16-bit organization DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data Size and Data Alignment. Rev. 3.00 Sep 14, 2005 page 161 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.5.5 Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.7 DRAM Interface Pins Pin With DRAM Designated Name I/O Function PB4 UCAS Upper column address strobe Output Upper column address strobe for DRAM space access (when CSEL = 0 in DRCRB) PB5 LCAS Lower column address strobe Output Lower column address strobe for DRAM space access (when CSEL = 0 in DRCRB) HWR UCAS Upper column address strobe Output Upper column address strobe for DRAM space access (when CSEL = 1 in DRCRB) LWR LCAS Lower column address strobe Output Lower column address strobe for DRAM space access (when CSEL = 1 in DRCRB) CS2 RAS2 Row address strobe 2 Output Row address strobe for DRAM space access CS3 RAS3 Row address strobe 3 Output Row address strobe for DRAM space access CS4 RAS4 Row address strobe 4 Output Row address strobe for DRAM space access CS5 RAS5 Row address strobe 5 Output Row address strobe for DRAM space access RD WE Write enable Output Write enable for DRAM space write access* P80 RFSH Refresh Output Goes low in refresh cycle A12 to A0 A12 to A0 Address Output Row address/column address multiplexed output D15 to D0 D15 to D0 Data I/O Data input/output pins Note: * Fixed high in a read access. 6.5.6 Basic Timing Figure 6.18 shows the basic access timing for DRAM space. The basic DRAM access timing is four states: one precharge cycle (Tp) state, one row address output cycle (Tr) state, and two column address output cycle (Tc1, Tc2) states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion between Tc1 and Tc2, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted between Tc1 and Tc2 in the DRAM access cycle. Rev. 3.00 Sep 14, 2005 page 162 of 910 REJ09B0258-0300 Section 6 Bus Controller If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM space when HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is inserted unconditionally immediately after the DRAM access cycle. See section 6.9, Idle Cycle, for details. Tp Tr Tc1 Tc2 A23 to A0 AS Row Column High level CSn (RAS) PB4 /PB5 (UCAS / LCAS) Read access RD(WE) High level D15 to D0 PB4 /PB5 (UCAS / LCAS) Write access RD(WE) D15 to D0 Note: n = 2 to 5 Figure 6.18 Basic Access Timing (CSEL = 0 in DRCRB) Rev. 3.00 Sep 14, 2005 page 163 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.5.7 Precharge State Control In the H8/3068F, provision is made for the DRAM RAS precharge time by always inserting one RAS precharge state (Tp) when DRAM space is accessed. This can be changed to two Tp states by setting the TPC bit to 1 in DRCRB. The optimum number of Tp cycles should be set according to the DRAM connected and the operating frequency of the H8/3068F chip. Figure 6.19 shows the timing when two Tp states are inserted. When the TCP bit is set to 1, two Tp states are also used for CAS-before-RAS refresh cycles. Tp1 Tp2 Tr Tc1 Tc2 A23 to A0 AS Row Column High level CSn (RAS) PB4 /PB5 (UCAS /LCAS) RD(WE) Read access High level D15 to D0 PB4 /PB5 (UCAS /LCAS) RD(WE) Write access D15 to D0 Note: n = 2 to 5 Figure 6.19 Timing with Two Precharge States (CSEL = 0 in DRCRB) Rev. 3.00 Sep 14, 2005 page 164 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.5.8 Wait Control In a DRAM access cycle, wait states can be inserted (1) between the Tr state and Tc1 state, and (2) between the Tc1 state and Tc2 state. Insertion of Trw Wait State between Tr and Tc1: One Trw state can be inserted between Tr and Tc1 by setting the RCW bit to 1 in DRCRB. Insertion of Tw Wait State(s) between Tc1 and Tc2: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted between the T c1 state and Tc2 state by means of settings in WCRH and WCRL. Figure 6.20 shows an example of the timing for wait state insertion. The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin. Rev. 3.00 Sep 14, 2005 page 165 of 910 REJ09B0258-0300 Section 6 Bus Controller Tp Tr Trw Tc1 Tw Tw Tc2 A23 to A0 AS Row Column High level CSn(RAS) Read access PB4/PB5 (UCAS /LCAS) RD(WE) D15 to D0 High level Read data PB4/PB5 (UCAS /LCAS) Write access RD(WE) D15 to D0 Write data Note: n = 2 to 5 Figure 6.20 Example of Wait State Insertion Timing (CSEL = 0) 6.5.9 Byte Access Control and CAS Output Pin When an access is made to DRAM space designated as a 16-bit-access area in ABWCR, column address strobes (UCAS and LCAS) corresponding to the upper and lower halves of the external data bus are output. In the case of x 16-bit organization DRAM, the 2-CAS type can be connected. Either PB4 and PB5, or HWR and LWR, can be used as the UCAS and LCAS output pins, the selection being made with the CSEL bit in DRCRB. Table 6.8 shows the CSEL bit settings and corresponding output pin selections. Rev. 3.00 Sep 14, 2005 page 166 of 910 REJ09B0258-0300 Section 6 Bus Controller When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0, PB5 can be used as an input/output port. Note that RAS down mode cannot be used when a device other than DRAM is connected to external space and HWR and LWR are used as write strobes. In this case, also, an idle cycle (Ti) is always inserted when an external access to other than DRAM space occurs after a DRAM space access. For details, see section 6.9, Idle Cycle. CSEL Settings and UCAS and LCAS Output Pins Table 6.8 CSEL UCAS LCAS 0 PB4 PB5 1 HWR LWR Figure 6.21 shows the control timing. Tp Tr Tc1 Row Column Tc2 A23 to A0 CSn (RAS) PB4(UCAS) Byte control PB5(LCAS) RD(WE) Note: n = 2 to 5 Figure 6.21 Control Timing (Upper-Byte Write Access When CSEL = 0) Rev. 3.00 Sep 14, 2005 page 167 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRCRA. Burst Access (Fast Page Mode) Operation Timing: Figure 6.22 shows the operation timing for burst access. When there are consecutive access cycles for DRAM space, the column address and CAS signal output cycles (two states) continue as long as the row address is the same for consecutive access cycles. In burst access, too, the bus cycle can be extended by inserting wait states between Tc1 and Tc2. The wait state insertion method and timing are the same as for full access: see section 6.5.8, Wait Control, for details. The row address used for the comparison is determined by the bus width of the relevant area set in bits MXC1 and MXC0 in BRCRB, and in ABWCR. Table 6.9 shows the compared row addresses corresponding to the various settings of bits MXC1 and MXC0, and ABWCR. Rev. 3.00 Sep 14, 2005 page 168 of 910 REJ09B0258-0300 Section 6 Bus Controller Tp Tr Tc1 Tc2 Tc1 Tc2 A23 to A0 AS Row Column 1 Column 2 High level CSn(RAS) PB4/PB5 (UCAS /LCAS) Read access RD(WE) D15 to D0 PB4/PB5 (UCAS/LCAS) Write access RD(WE) D15 to D0 Note: n = 2 to 5 Figure 6.22 Operation Timing in Fast Page Mode Rev. 3.00 Sep 14, 2005 page 169 of 910 REJ09B0258-0300 Section 6 Bus Controller Table 6.9 Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and Row Address Compared in Burst Access DRCRB ABWCR Operating Mode MXC1 MXC0 ABWn Bus Width Compared Row Address Modes 1 and 2 (1-Mbyte) 0 0 0 16 bits A19 to A9 1 8 bits A19 to A8 0 16 bits A19 to A10 1 8 bits A19 to A9 1 1 Modes 3, 4, and 5 (16-Mbyte) 0 0 0 16 bits A19 to A11 1 8 bits A19 to A10 1 -- -- Illegal setting 0 0 16 bits A23 to A9 1 8 bits A23 to A8 1 1 0 1 0 16 bits A23 to A10 1 8 bits A23 to A9 0 16 bits A23 to A11 1 8 bits A23 to A10 -- -- Illegal setting Note: n = 2 to 5 RAS Down Mode and RAS Up Mode: With DRAM provided with fast page mode, as long as accesses are to the same row address, burst operation can be continued without interruption even if accesses are not consecutive by holding the RAS signal low. * RAS Down Mode To select RAS down mode, set the BE and RDM bits to 1 in DRCRA. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed if the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6.23 shows an example of the timing in RAS down mode. Rev. 3.00 Sep 14, 2005 page 170 of 910 REJ09B0258-0300 Section 6 Bus Controller External space access DRAM access Tp Tr Tc1 Tc2 T1 T2 DRAM access Tc1 Tc2 A23 to A0 AS CSn (RAS) PB4/PB5 (UCAS/LCAS) D15 to D0 Note: n = 2 to 5 Figure 6.23 Example of Operation Timing in RAS Down Mode (CSEL = 0) When RAS down mode is selected, the conditions for an asserted RASn signal to return to the high level are as shown below. The timing in these cases is shown in figure 6.24. When DRAM space with a different row address is accessed Immediately before a CAS-before-RAS refresh cycle When the BE bit or RDM bit is cleared to 0 in DRCRA Immediately before release of the external bus Rev. 3.00 Sep 14, 2005 page 171 of 910 REJ09B0258-0300 Section 6 Bus Controller DRAM access cycle RASn (a) Access to DRAM space with a different row address CBR refresh cycle RASn (b) CAS-before-RAS refresh cycle DRCRA write cycle RASn (c) BE bit or RDM bit cleared to 0 in DRCRA External bus released High-impedance RASn (d) External bus released Note: n = 2 to 5 Figure 6.24 RASn Negation Timing when RAS Down Mode is Selected Rev. 3.00 Sep 14, 2005 page 172 of 910 REJ09B0258-0300 Section 6 Bus Controller When RAS down mode is selected, the CAS-before-RAS refresh function provided with this DRAM interface must always be used as the DRAM refreshing method. When a refresh operation is performed, the RAS signal goes high immediately beforehand. The refresh interval setting must be made so that the maximum DRAM RAS pulse width specification is observed. When the self-refresh function is used, the RDM bit must be cleared to 0, and RAS up mode selected, before executing a SLEEP instruction in order to enter software standby mode. Select RAS down mode again after exiting software standby mode. Note that RAS down mode cannot be used when HWR and LWR are selected for UCAS and LCAS, a device other than DRAM is connected to external space, and HWR and LWR are used as write strobes. * RAS Up Mode To select RAS up mode, clear the RDM bit to 0 in DRCRA. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal returns to the high level. Burst operation is only performed if DRAM space is continuous. Figure 6.25 shows an example of the timing in RAS up mode. DRAM access Tp Tr Tc1 DRAM access Tc2 Tc1 Tc2 External space access T1 T2 A23 to A0 AS CSn(RAS) PB4/PB5 (UCAS/LCAS) D15 to D0 Note: n = 2 to 5 Figure 6.25 Example of Operation Timing in RAS Up Mode Rev. 3.00 Sep 14, 2005 page 173 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.5.11 Refresh Control The H8/3068F is provided with a CAS-before-RAS (CBR) function and self-refresh function as DRAM refresh control functions. CAS-Before-RAS (CBR) Refreshing: To select CBR refreshing, set the RCYCE bit to 1 in DRCRB. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in RTMCSR, and a refresh request is generated when the count matches the value set in RTCOR (compare match). At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. A refresh cycle is executed after this refresh request has been accepted and the DRAM interface has acquired the bus. Set a value in bits CKS2 to CKS0 in RTCOR that will meet the refresh interval specification for the DRAM used. When RAS down mode is used, set the refresh interval so that the maximum RAS pulse width specification is met. RTCNT starts counting up when bits CKS2 to CKS0 are set. RTCNT and RTCOR settings should therefore be completed before setting bits CKS2 to CKS0. Also note that a repeat refresh request generated during a bus request, or a refresh request during refresh cycle execution, will be ignored. RTCNT operation is shown in figure 6.26, compare match timing in figure 6.27, and CBR refresh timing in figures 6.28 and 6.29. RTCNT RTCOR H'00 Refresh request Figure 6.26 RTCNT Operation Rev. 3.00 Sep 14, 2005 page 174 of 910 REJ09B0258-0300 Section 6 Bus Controller RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.27 Compare Match Timing TRp TR1 TR2 Address bus* Area 2 start address CSn(RAS) PB4/PB5 (UCAS/LCAS) RD(WE) High RFSH AS High level Note: * In address update mode 1, the area 2 start address is output. In address update mode 2, the address in the preceding bus cycle is retained. Figure 6.28 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0) The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (TRP) state, and two RAS output cycle (TR1, TR2) states. Either one or two states can be selected for the RAS Rev. 3.00 Sep 14, 2005 page 175 of 910 REJ09B0258-0300 Section 6 Bus Controller precharge cycle. When the TPC bit is set to 1 in DRCRB, RAS signal output is delayed by one cycle. This does not affect the timing of UCAS and LCAS output. Use the RLW bit in DRCRB to adjust the RAS signal width. A single refresh wait state (TRW) can be inserted between the TR1 state and TR2 state by setting the RLW bit to 1. The RLW bit setting is valid only for CBR refresh cycles, and does not affect DRAM read/write cycles. The number of states in the CBR refresh cycle is not affected by the settings in ASTCR, WCRH, or WCRL, or by the state of the WAIT pin. Figure 6.29 shows the timing when the TPC bit and RLW bit are both set to 1. TRp1 TRP2 TR1 TRW TR2 Address bus* Area 2 start address CSn(RAS) PB4/PB5 (UCAS/LCAS) RD(WE) High RFSH AS High level Note: * In address update mode 1, the area 2 start address is output. In address update mode 2, the address in the preceding bus cycle is retained. Figure 6.29 CBR Refresh Timing (CSEL = 0, TPC = 1, RLW = 1) DRAM must be refreshed immediately after powering on in order to stabilize its internal state. When using the H8/3068F CAS-before-RAS refresh function, therefore, a DRAM stabilization period should be provided by means of interrupts by another timer module, or by counting the Rev. 3.00 Sep 14, 2005 page 176 of 910 REJ09B0258-0300 Section 6 Bus Controller number of times bit 7 (CMF) of RTMCSR is set, for instance, immediately after bits DRAS2 to DRAS0 have been set in DRCRA. Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. The H8/3068F has a function that places the DRAM in self-refresh mode when the chip enters software standby mode. To use the self-refresh function, set the SRFMD bit to 1 in DRCRA. When a SLEEP instruction is subsequently executed in order to enter software standby mode, the CAS and RAS signals are output and the DRAM enters self-refresh mode, as shown in figure 6.30. When the chip exits software standby mode, CAS and RAS outputs go high. The following conditions must be observed when the self-refresh function is used: * When burst access is selected, RAS up mode must be selected before executing a SLEEP instruction in order to enter software standby mode. Therefore, if RAS down mode has been selected, the RDM bit in DRCRA must be cleared to 0 and RAS up mode selected before executing the SLEEP instruction. Select RAS down mode again after exiting software standby mode. * The instruction immediately following a SLEEP instruction must not be located in an area designated as DRAM space. The self-refresh function will not work properly unless the above conditions are observed. Rev. 3.00 Sep 14, 2005 page 177 of 910 REJ09B0258-0300 Section 6 Bus Controller Software standby mode Oscillation stabilization time High-impedance Address bus CSn(RAS) PB4(UCAS) PB5(LCAS) RD(WE) RFSH Figure 6.30 Self-Refresh Timing (CSEL = 0) Refresh Signal (RFSH): A refresh signal (RFSH) that transmits a refresh cycle off-chip can be output by setting the RFSHE bit to 1 in DRCRA. RFSH output timing is shown in figures 6.28, 6.29, and 6.30. 6.5.12 Examples of Use Examples of DRAM connection and program setup procedures are shown below. When the DRAM interface is used, check the DRAM device characteristics and choose the most appropriate method of use for that device. Connection Examples * Figure 6.31 shows typical interconnections when using two 2-CAS type 16-Mbit DRAMs using a x 16-bit organization, and the corresponding address map. The DRAMs used in this example are of the 10-bit row address x 10-bit column address type. Up to four DRAMs can be connected by designating areas 2 to 5 as DRAM space. Rev. 3.00 Sep 14, 2005 page 178 of 910 REJ09B0258-0300 Section 6 Bus Controller 2-CAS 16-Mbit DRAM 10-bit row address x 10-bit column address x16-bit organization H8/3067 Group chip CS2 (RAS2) CS3 (RAS3) PB4(UCAS) PB5(LCAS) RD (WE) RAS UCAS LCAS WE A10-A1 A9-A0 D15-D0 D15-D0 No.1 OE RAS UCAS LCAS WE No.2 A9-A0 D15-D0 OE (a) Interconnections (example) PB5 (LCAS) PB4 (UCAS) 15 87 0 H'400000 Area 2 DRAM (No.1) CS2(RAS2) DRAM (No.2) CS3(RAS3) H'5FFFFE H'600000 Area 3 H'7FFFFE H'800000 Area 4 Normal CS4 Normal CS5 H'9FFFFE H'A00000 Area 5 H'BFFFFE (b) Address map Figure 6.31 Interconnections and Address Map for 2-CAS 16-Mbit DRAMs with x 16-Bit Organization * Figure 6.32 shows typical interconnections when using two 16-Mbit DRAMs using a x 8-bit organization, and the corresponding address map. The DRAMs used in this example are of the 11-bit row address x 10-bit column address type. The CS2 pin is used as the common RAS output pin for areas 2 and 3. When the DRAM address space spans a number of contiguous Rev. 3.00 Sep 14, 2005 page 179 of 910 REJ09B0258-0300 Section 6 Bus Controller areas, as in this example, the appropriate setting of bits DRAS2 to DRAS0 enables a single CS pin to be used as the common RAS output pin for a number of areas, and makes it possible to directly connect large-capacity DRAM with address space that spans a maximum of four areas. Any unused CS pins (in this example, the CS3 pin) can be used as input/output ports. 2-CAS 16-Mbit DRAM 11-bit row address x 10-bit column address x8-bit organization H8/3067 Group chip RAS CS2 (RAS2) PB4 (UCAS) PB5 (LCAS) RD (WE) CAS WE A21, A10-A1 No.1 A10-A0 D7-D0 D15-D8 D7-D0 OE RAS CAS WE No.2 A10-A0 D7-D0 OE (a) Interconnections (example) PB4 PB5 (UCAS) (LCAS) 15 87 0 H'400000 Area 2 H'5FFFFE H'600000 DRAM (No.1) DRAM (No.2) CS2(RAS2) Area 3 H'7FFFFE H'800000 Area 4 Normal CS4 Normal CS5 H'9FFFFE H'A00000 Area 5 H'BFFFFE 16-Mbyte mode (b) Address map Figure 6.32 Interconnections and Address Map for 16-Mbit DRAMs with x 8-Bit Organization Rev. 3.00 Sep 14, 2005 page 180 of 910 REJ09B0258-0300 Section 6 Bus Controller * Figure 6.33 shows typical interconnections when using two 4-Mbit DRAMs, and the corresponding address map. The DRAMs used in this example are of the 9-bit row address x 10-bit column address type. In this example, upper address decoding allows multiple DRAMs to be connected to a single area. The RFSH pin is used in this case, since both DRAMs must be refreshed simultaneously. However, note that RAS down mode cannot be used in this interconnection example. Rev. 3.00 Sep 14, 2005 page 181 of 910 REJ09B0258-0300 Section 6 Bus Controller 2-CAS 4-Mbit DRAM 9-bit row address x 9-bit column address x16-bit organization H8/3067 Group chip CS2 (RAS2) PB4 (UCAS) RAS UCAS PB5 (LCAS) RD (WE) LCAS WE No.1 RFSH A19 A9-A1 A8-A0 D15-D0 D15-D0 RAS UCAS LCAS WE OE No.2 A8-A0 D15-D0 OE (a) Interconnections (example) PB4 (UCAS) 15 PB5 (LCAS) 87 0 H'400000 DRAM (No.1) H'47FFFE H'480000 DRAM (No.2) Area 2 H'4FFFFE H'500000 CS2 (RAS2) Not used H'5FFFFE 16-Mbyte mode (b) Address map Figure 6.33 Interconnections and Address Map for 2-CAS 4-Mbit DRAMs with x 16-Bit Organization Rev. 3.00 Sep 14, 2005 page 182 of 910 REJ09B0258-0300 Section 6 Bus Controller Example of Program Setup Procedure: Figure 6.34 shows an example of the program setup procedure. Set ABWCR Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Set DRCRB Set DRCRA Wait for DRAM stabilization time DRAM can be accessed Figure 6.34 Example of Setup Procedure when Using DRAM Interface 6.5.13 Usage Notes Note the following points when using the DRAM refresh function. * Refresh cycles will not be executed when the external bus released state, software standby mode, or a bus cycle is extended by means of wait state insertion. Refreshing must therefore be performed by other means in these cases. * If a refresh request is generated internally while the external bus is released, the first request is retained and a single refresh cycle will be executed after the bus-released state is cleared. Figure 6.35 shows the bus cycle in this case. * When a bus cycle is extended by means of wait state insertion, the first request is retained in the same way as when the external bus has been released. Rev. 3.00 Sep 14, 2005 page 183 of 910 REJ09B0258-0300 Section 6 Bus Controller * In the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the BACK and strobe states may be indeterminate after the transition to software standby mode (see figure 6.36). When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before executing the SLEEP instruction. Similar contention in a transition to self-refresh mode may prevent dependable strobe waveform output. This can also be avoided by clearing the BRLW bit to 0 in BRCR. * Immediately after self-refreshing is cleared, external bus release is possible during a given period until the start of a CPU cycle. Attention must be paid to the RAS state to ensure that the specification for the RAS precharge time immediately after self-refreshing is met. External bus released Refresh cycle CPU cycle RFSH Refresh request BACK Figure 6.35 Bus-Released State and Refresh Cycles Rev. 3.00 Sep 14, 2005 page 184 of 910 REJ09B0258-0300 Refresh cycle Section 6 Bus Controller Software standby mode BREQ BACK Address bus Strobe Figure 6.36 Bus-Released State and Software Standby Mode Oscillation stabilization CPU internal cycle time on exit from software (period in which external standby mode bus can be released) CPU cycle Address @SP RAS CAS Figure 6.37 Self-Refresh Clearing Rev. 3.00 Sep 14, 2005 page 185 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.6 Interval Timer 6.6.1 Operation When DRAM is not connected to the H8/3068F chip, the refresh timer can be used as an interval timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR, selection a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1. Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag in RTMCSR is set to 1 by a compare match output when the RTCOR and RTCNT values match. The compare match signal is generated in the last state in which the values match (when RTCNT is updated from the matching value to a new value). Accordingly, when RTCNT and RTCOR match, the compare match signal is not generated until the next counter clock pulse. Figure 6.38 shows the timing. RTCNT N H'00 N RTCOR Compare match signal CMF flag Figure 6.38 Timing of CMF Flag Setting Rev. 3.00 Sep 14, 2005 page 186 of 910 REJ09B0258-0300 Section 6 Bus Controller Operation in Power-Down State: The interval timer operates in sleep mode. It does not operate in hardware standby mode. In software standby mode, RTCNT and RTMCSR bits 7 and 6 are initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to software standby mode. Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the T3 state of an RTCNT write cycle, clearing of the counter takes priority and the write is not performed. See Figure 6.39. T1 T2 T3 Address bus RTCNT address Internal write signal Counter clear signal RTCNT N H'00 Figure 6.39 Contention between RTCNT Write and Clear Rev. 3.00 Sep 14, 2005 page 187 of 910 REJ09B0258-0300 Section 6 Bus Controller Contention between RTCNT Write and Increment: If an increment pulse occurs in the T3 state of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See Figure 6.40. T1 T2 T3 Address bus RTCNT address Internal write signal RTCNT input clock RTCNT N M Counter write data Figure 6.40 Contention between RTCNT Write and Increment Rev. 3.00 Sep 14, 2005 page 188 of 910 REJ09B0258-0300 Section 6 Bus Controller Contention between RTCOR Write and Compare Match: If a compare match occurs in the T3 state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See Figure 6.41. T1 T2 T3 Address bus RTCOR address Internal write signal RTCNT N N+1 RTCOR N M RTCOR write data Compare match signal Inhibited Figure 6.41 Contention between RTCOR Write and Compare Match RTCNT Operation at Internal Clock Source Switchover: Switching internal clock sources may cause RTCNT to increment, depending on the switchover timing. Table 6.10 shows the relation between the time of the switchover (by writing to bits CKS2 to CKS0) and the operation of RTCNT. The RTCNT input clock is generated from the internal clock source by detecting the falling edge of the internal clock. If a switchover is made from a high clock source to a low clock source, as in case No. 3 in table 6.10, the switchover will be regarded as a falling edge, an RTCNT clock pulse will be generated, and RTCNT will be incremented. Rev. 3.00 Sep 14, 2005 page 189 of 910 REJ09B0258-0300 Section 6 Bus Controller Table 6.10 Internal Clock Switchover and RTCNT Operation No. 1 CKS2 to CKS0 Write Timing Low Low switchover*1 RTCNT Operation Old clock source New clock source RTCNT clock RTCNT N N+1 CKS bits rewritten 2 Low High switchover*2 Old clock source New clock source RTCNT clock RTCNT N N+1 N+2 CKS bits rewritten Rev. 3.00 Sep 14, 2005 page 190 of 910 REJ09B0258-0300 Section 6 Bus Controller No. 3 CKS2 to CKS0 Write Timing High Low switchover*3 RTCNT Operation Old clock source New clock source *4 RTCNT clock RTCNT N N+1 N+2 CKS bits rewritten 4 High High switchover*4 Old clock source New clock source RTCNT clock RTCNT N N+1 N+2 CKS bits rewritten Notes: 1. 2. 3. 4. Including switchovers from a low clock source to the halted state, and from the halted state to a low clock source. Including switchover from the halted state to a high clock source. Including switchover from a high clock source to the halted state. The switchover is regarded as a falling edge, causing RTCNT to increment. Rev. 3.00 Sep 14, 2005 page 191 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.7 Interrupt Sources Compare match interrupts (CMI) can be generated when the refresh timer is used as an interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit in RTMCSR. 6.8 Burst ROM Interface 6.8.1 Overview With the H8/3068F, external space area 0 can be designated as burst ROM space, and burst ROM space interfacing can be performed. The burst ROM space interface enables 16-bit organization ROM with burst access capability to be accessed at high speed. Area 0 is designated as burst ROM space by means of the BROME bit in BCR. Continuous burst access of a maximum or four or eight words can be performed on external space area 0. Two or three states can be selected for burst access. 6.8.2 Basic Timing The number of states in the initial cycle (full access) and a burst cycle of the burst ROM interface is determined by the setting of the AST0 bit in ASTCR. When the AST0 bit is set to 1, wait states can also be inserted in the initial cycle. Wait states cannot be inserted in a burst cycle. Burst access of up to four words is performed when the BRSTS0 bit is cleared to 0 in BCR, and burst access of up to eight words when the BRSTS0 bit is set to 1. The number of burst access states is two when the BRSTS1 bit is cleared to 0, and three when the BRSTS1 bit is set to 1. The basic access timing for burst ROM space is shown in figure 6.42. Rev. 3.00 Sep 14, 2005 page 192 of 910 REJ09B0258-0300 Section 6 Bus Controller Full access T1 T2 Burst access T3 T1 T2 T1 T2 Address bus Only lower address changes CS0 AS RD Data bus Read data Read data Read data Figure 6.42 Example of Burst ROM Access Timing 6.8.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. Wait states cannot be inserted in a burst cycle. Rev. 3.00 Sep 14, 2005 page 193 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.9 Idle Cycle 6.9.1 Operation When the H8/3068F chip accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following cases: (1) when read accesses between different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) immediately after a DRAM space access. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, which has a long output floating time, and high-speed memory, I/O interfaces, and so on. The ICIS1 and ICIS0 bits in BCR both have an initial value of 1, so that an idle cycle is inserted in the initial state. If there are no data collisions, the ICIS bits can be cleared. Consecutive Reads between Different Areas: If consecutive reads between different areas occur while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle. Figure 6.43 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A Bus cycle B T1 T2 T3 T1 T2 Bus cycle A Bus cycle B Address bus Address bus RD RD Data bus Data bus Long buffer-off time (a) Idle cycle not inserted T1 T2 T3 Ti T1 Data collision (b) Idle cycle inserted Figure 6.43 Example of Idle Cycle Operation (1) (ICIS1 = 1) Rev. 3.00 Sep 14, 2005 page 194 of 910 REJ09B0258-0300 T2 Section 6 Bus Controller Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A Bus cycle B T1 T2 T3 T1 T2 Bus cycle A Bus cycle B Address bus T1 T2 T3 Ti T1 T2 Address bus RD RD HWR HWR Data bus Data bus Long buffer-off time (a) Idle cycle not inserted Data collision (b) Idle cycle inserted Figure 6.44 Example of Idle Cycle Operation (2) (ICIS0 = 1) External Address Space Access Immediately after DRAM Space Access: If a DRAM space access is followed by a non-DRAM external access when HWR and LWR have been selected as the UCAS and LCAS output pins by means of the CSEL bit in DRCRB, a Ti cycle is inserted regardless of the settings of bits ICIS0 and ICIS1 in BCR. Figure 6.45 shows an example of the operation. This is done to prevent simultaneous changing of the HWR and LWR signals used as UCAS and LCAS in DRAM space and CSn for the space in the next cycle, and so avoid an erroneous write to the external device in the next cycle. A Ti cycle is not inserted when PB4 and PB5 have been selected as the UCAS and LCAS output pins. In the case of consecutive DRAM space access precharge cycles (Tp), the ICIS0 and ICIS1 bit settings are invalid. In the case of consecutive reads between different areas, for example, if the second access is a DRAM access, only a Tp cycle is inserted, and a Ti cycle is not. The timing in this case is shown in figure 6.46. Rev. 3.00 Sep 14, 2005 page 195 of 910 REJ09B0258-0300 Section 6 Bus Controller Bus cycle A (DRAM access cycle) Bus cycle B Tp Tr Tc1 Tc2 T1 Bus cycle A (DRAM access cycle) Bus cycle B T2 Address bus Address bus HWR/LWR (UCAS/LCAS) HWR/LWR (UCAS/LCAS) CSn CSn Tp Tr Tc1 Tc2 Ti T1 T2 Simultaneous change of HWR/LWR and CSn (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.45 Example of Idle Cycle Operation (3) (HWR/LWR Used as UCAS/LCAS) External read T1 T2 T3 DRAM space read Tp Tr Tc1 Tc2 Address bus RD UCAS/LCAS Address bus Figure 6.46 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles) Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall (assertion) of CSn may occur simultaneously. An example of the operation is shown in figure 6.47. If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0 bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal, it is possible that the low-level output of RD in the preceding read cycle and the low-level output of CSn in the following bus cycle will overlap. Rev. 3.00 Sep 14, 2005 page 196 of 910 REJ09B0258-0300 Section 6 Bus Controller A setting whereby idle cycle insertion is not performed can be made only when RD and CSn do not change simultaneously, or when it does not matter if they do. Bus cycle A T1 T2 T3 Bus cycle B T1 Bus cycle A T2 Address bus Address bus RD RD CSn CSn T1 T2 T3 Bus cycle B Ti T1 T2 Simultaneous change of RD and CSn Possibility of mutual overlap (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.47 Example of Idle Cycle Operation (5) 6.9.2 Pin States in Idle Cycle Table 6.11 shows the pin states in an idle cycle. Table 6.11 Pin States in Idle Cycle Pins Pin State A23 to A0 Next cycle address value D15 to D0 High impedance CSn UCAS, LCAS AS RD HWR LWR High* High High High High High Note: * Remains low in DRAM space RAS down mode. Rev. 3.00 Sep 14, 2005 page 197 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.10 Bus Arbiter The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), DRAM interface, and an external bus master. When a bus master has the bus right it can carry out read, write, or refresh access. Each bus master uses a bus request signal to request the bus right. At fixed times the bus arbiter determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can the operate using the bus. The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and returns an acknowledge signal to the bus master. When two or more bus masters request the bus, the highest-priority bus master receives an acknowledge signal. The bus master that receives an acknowledge signal can continue to use the bus until the acknowledge signal is deactivated. The bus master priority order is: (High) External bus master > DRAM interface > DMAC > CPU (Low) The bus arbiter samples the bus request signals and determines priority at all times, but it does not always grant the bus immediately, even when it receives a bus request from a bus master with higher priority than the current bus master. Each bus master has certain times at which it can release the bus to a higher-priority bus master. 6.10.1 Operation CPU: The CPU is the lowest-priority bus master. If the DMAC, DRAM interface, or an external bus master requests the bus while the CPU has the bus right, the bus arbiter transfers the bus right to the bus master that requested it. The bus right is transferred at the following times: * The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two consecutive byte accesses, however, the bus right is not transferred between the two byte accesses. * If another bus master requests the bus while the CPU is performing internal operations, such as executing a multiply or divide instruction, the bus right is transferred immediately. The CPU continues its internal operations. * If another bus master requests the bus while the CPU is in sleep mode, the bus right is transferred immediately. Rev. 3.00 Sep 14, 2005 page 198 of 910 REJ09B0258-0300 Section 6 Bus Controller DMAC: When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If the DMAC is bus master and the DRAM interface or an external bus master requests the bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the bus. The bus right is transferred at the following times. The bus right is transferred when the DMAC finishes transferring one byte or one word. A DMAC transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred between the read cycle and the write cycle. There is a priority order among the DMAC channels. For details see section 7.4.9, MultipleChannel Operation. DRAM Interface: The DRAM interface requests the bus right from the bus arbiter when a refresh cycle request is issued, and releases the bus at the end of the refresh cycle. For details see section 6.5, DRAM Interface. External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an external bus master. The external bus master has highest priority, and requests the bus right from the bus arbiter y driving the BREQ signal low. Once the external bus master acquires the bus, it keeps the bus until the BREQ signal goes high. While the bus is released to an external bus master, the H8/3068F chip holds the address bus, data bus, bus control signals (AS, RD, HWR, and LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds the BACK pin in the low output state. The bus arbiter samples the BREQ pin at the rise of the system clock (). If BREQ is low, the bus is released to the external bus master at the appropriate opportunity. The BREQ signal should be held low until the BACK signal goes low. When the BREQ pin is high in two consecutive samples, the BACK pin is driven high to end the bus-release cycle. Figure 6.48 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state access area. There is a minimum interval of three states from when the BREQ signal goes low until the bus is released. Rev. 3.00 Sep 14, 2005 page 199 of 910 REJ09B0258-0300 Section 6 Bus Controller CPU cycles T0 T1 External bus released High-impedance Address Address bus CPU cycles T2 High-impedance Data bus High-impedance AS RD High-impedance High High-impedance HWR, LWR BREQ BACK Minimum 3 cycles (1) (2) (3) (4) (5) (6) Figure 6.48 Example of External Bus Master Operation In the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the BACK and strobe states may be indeterminate after the transition to software standby mode (see figure 6.36). When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before executing the SLEEP instruction. Rev. 3.00 Sep 14, 2005 page 200 of 910 REJ09B0258-0300 Section 6 Bus Controller 6.11 Register and Pin Input Timing 6.11.1 Register Write Timing ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR, WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.49 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. T1 T2 T3 T1 T2 T3 T1 T2 Address bus ASTCR address 3-state access to area 0 2-state access to area 0 Figure 6.49 ASTCR Write Timing DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the CSn pin to switch between CSn output and generic input takes effect starting from the T3 state of the DDR write cycle. Figure 6.50 shows the timing when the CS1 pin is changed from generic input to CS1 output. T1 T2 T3 Address bus P8DDR address CS1 High-impedance Figure 6.50 DDR Write Timing Rev. 3.00 Sep 14, 2005 page 201 of 910 REJ09B0258-0300 Section 6 Bus Controller BRCR Write Timing: Data written to BRCR to switch between A23, A22, A21, or A20 output and generic input or output takes effect starting from the T3 state of the BRCR write cycle. Figure 6.51 shows the timing when a pin is changed from generic input to A23, A22, A21, or A20 output. T1 T2 T3 Address bus BRCR address PA7 to PA4 (A23 to A20) High-impedance Figure 6.51 BRCR Write Timing 6.11.2 BREQ Pin Input Timing After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes lows, the bus arbiter may operate incorrectly. To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If BREQ is high for too short an interval, the bus arbiter may operate incorrectly. Rev. 3.00 Sep 14, 2005 page 202 of 910 REJ09B0258-0300 Section 7 DMA Controller Section 7 DMA Controller 7.1 Overview The H8/3068F has an on-chip DMA controller (DMAC) that can transfer data on up to four channels. When the DMA controller is not used, it can be independently halted to conserve power. For details see section 20.6, Module Standby Function. 7.1.1 Features DMAC features are listed below. * Selection of short address mode or full address mode Short address mode 8-bit source address and 24-bit destination address, or vice versa Maximum four channels available Selection of I/O mode, idle mode, or repeat mode Full address mode 24-bit source and destination addresses Maximum two channels available Selection of normal mode or block transfer mode * Directly addressable 16-Mbyte address space * Selection of byte or word transfer * Activation by internal interrupts, external requests, or auto-request (depending on transfer mode) 16-bit timer compare match/input capture interrupts (x3) Serial communication interface (SCI channel 0) transmit-data-empty/receive-data-full interrupts External requests Auto-request A/D converter conversion-end interrupt Rev. 3.00 Sep 14, 2005 page 203 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.1.2 Block Diagram Figure 7.1 shows a DMAC block diagram. Internal address bus Address buffer IMIA0 IMIA1 IMIA2 ADI TXI0 RXI0 DREQ0 DREQ1 TEND0 TEND1 Arithmetic-logic unit MAR0A Channel 0A Control logic ETCR0A Channel 0 MAR0B Channel 0B DTCR0A Interrupt DEND0A signals DEND0B DEND1A DEND1B MAR1A Channel 1A DTCR1A MAR1B Internal data bus Legend DTCR: Data transfer control register MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register Figure 7.1 Block Diagram of DMAC Rev. 3.00 Sep 14, 2005 page 204 of 910 REJ09B0258-0300 IOAR1A ETCR1A Channel 1 Channel 1B Data buffer IOAR0B ETCR0B DTCR0B DTCR1B IOAR0A IOAR1B ETCR1B Module data bus Internal interrupts Section 7 DMA Controller 7.1.3 Functional Overview Table 7.1 gives an overview of the DMAC functions. Table 7.1 DMAC Functional Overview Transfer Mode Short I/O mode address * Transfers one byte or one word mode per request * Increments or decrements the memory address by 1 or 2 * Executes 1 to 65,536 transfers Idle mode * Transfers one byte or one word per request * Holds the memory address fixed Full address mode * Executes 1 to 65,536 transfers Repeat mode * Transfers one byte or one word per request * Increments or decrements the memory address by 1 or 2 * Executes a specified number (1 to 255) of transfers, then returns to the initial state and continues Normal mode * Auto-request Retains the transfer request internally Executes a specified number(1 to 65,536) of transfers continuously Selection of burst mode or cyclesteal mode * External request Transfers one byte or one word per request Executes 1 to 65,536 transfers Block transfer * Transfers one block of a specified size per request * Executes 1 to 65,536 transfers * Allows either the source or destination to be a fixed block area * Block size can be 1 to 255 bytes or words Activation * Compare match/input capture A interrupts from 16bit timer channels 0 to 2 * Transmit-data-empty interrupt from SCI channel 0 * Address Reg. Length DestinaSource tion 24 8 8 24 * Conversion-end interrupt from A/D converter Receive-data-full interrupt from SCI channel 0 External request 24 8 * * Auto-request External request 24 24 * Compare match/ input 24 capture A interrupts from 16bit timer channels 0 to 2 External request Conversion-end interrupt from A/D converter 24 * * * Rev. 3.00 Sep 14, 2005 page 205 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.1.4 Input/Output Pins Table 7.2 lists the DMAC pins. Table 7.2 DMAC Pins Channel Name 0 DMA request 0 Transfer end 0 1 DMA request 1 Transfer end 1 Abbreviation DREQ0 TEND0 DREQ1 TEND1 Input/ Output Function Input External request for DMAC channel 0 Output Transfer end on DMAC channel 0 Input External request for DMAC channel 1 Output Transfer end on DMAC channel 1 Note: External requests cannot be made to channel A in short address mode. Rev. 3.00 Sep 14, 2005 page 206 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.1.5 Register Configuration Table 7.3 lists the DMAC registers. Table 7.3 DMAC Registers Channel Address* Name Abbreviation R/W Initial Value 0 H'FFF20 Memory address register 0AR MAR0AR R/W Undetermined H'FFF21 Memory address register 0AE MAR0AE R/W Undetermined H'FFF22 Memory address register 0AH MAR0AH R/W Undetermined H'FFF23 Memory address register 0AL MAR0AL R/W Undetermined H'FFF26 I/O address register 0A IOAR0A R/W Undetermined H'FFF24 Execute transfer count register 0AH ETCR0AH R/W Undetermined H'FFF25 Execute transfer count register 0AL ETCR0AL R/W Undetermined H'FFF27 Data transfer control register 0A DTCR0A R/W H'00 H'FFF28 Memory address register 0BR MAR0BR R/W Undetermined H'FFF29 Memory address register 0BE MAR0BE R/W Undetermined H'FFF2A Memory address register 0BH MAR0BH R/W Undetermined H'FFF2B Memory address register 0BL MAR0BL R/W Undetermined H'FFF2E I/O address register 0B IOAR0B R/W Undetermined H'FFF2C Execute transfer count register 0BH ETCR0BH R/W Undetermined H'FFF2D Execute transfer count register 0BL ETCR0BL R/W Undetermined H'FFF2F Data transfer control register 0B DTCR0B R/W H'00 H'FFF30 Memory address register 1AR MAR1AR R/W Undetermined H'FFF31 Memory address register 1AE MAR1AE R/W Undetermined H'FFF32 Memory address register 1AH MAR1AH R/W Undetermined H'FFF33 Memory address register 1AL MAR1AL R/W Undetermined H'FFF36 I/O address register 1A IOAR1A R/W Undetermined H'FFF34 Execute transfer count register 1AH ETCR1AH R/W Undetermined H'FFF35 Execute transfer count register 1AL ETCR1AL R/W Undetermined H'FFF37 Data transfer control register 1A DTCR1A R/W H'00 H'FFF38 Memory address register 1BR MAR1BR R/W Undetermined H'FFF39 Memory address register 1BE MAR1BE R/W Undetermined H'FFF3A Memory address register 1BH MAR1BH R/W Undetermined H'FFF3B Memory address register 1BL MAR1BL R/W Undetermined 1 Rev. 3.00 Sep 14, 2005 page 207 of 910 REJ09B0258-0300 Section 7 DMA Controller Channel Address* Name Abbreviation R/W Initial Value 1 H'FFF3E I/O address register 1B IOAR1B R/W Undetermined H'FFF3C Execute transfer count register 1BH ETCR1BH R/W Undetermined H'FFF3D Execute transfer count register 1BL ETCR1BL R/W Undetermined H'FFF3F Data transfer control register 1B R/W H'00 DTCR1B Note: * The lower 20 bits of the address are indicated. 7.2 Register Descriptions (1) (Short Address Mode) In short address mode, transfers can be carried out independently on channels A and B. Short address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA) as indicated in table 7.4. Table 7.4 Selection of Short and Full Address Modes Bit 2 Channel DTS2A Bit 1 DTS1A Description 0 1 DMAC channel 0 operates as one channel in full address mode 1 1 Other than above DMAC channels 0A and 0B operate as two independent channels in short address mode 1 DMAC channel 1 operates as one channel in full address mode 1 Other than above 7.2.1 DMAC channels 1A and 1B operate as two independent channels in short address mode Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or destination address. The transfer direction is determined automatically from the activation source. An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits of MARR are reserved; they cannot be modified and are always read as 1. Rev. 3.00 Sep 14, 2005 page 208 of 910 REJ09B0258-0300 Section 7 DMA Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Initial value Read/Write 8 7 6 5 4 3 2 1 0 Undetermined -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MARR MARE MARH MARL Source or destination address An MAR functions as a source or destination address register depending on how the DMAC is activated: as a destination address register if activation is by a receive-data-full interrupt from serial communication interface (SCI) channel 0 or by an A/D converter conversion-end interrupt, and as a source address register otherwise. The MAR value is incremented or decremented each time one byte or word is transferred, automatically updating the source or destination memory address. For details, see section 7.3.4, Data Transfer Control Registers (DTCR). The MARs are not initialized by a reset or in standby mode. 7.2.2 I/O Address Registers (IOAR) An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits are all 1 (H'FFFF). Bit 7 6 5 Initial value Read/Write 4 3 2 1 0 R/W R/W R/W Undetermined R/W R/W R/W R/W R/W Source or destination address An IOAR functions as a source or destination address register depending on how the DMAC is activated: as a destination address register if activation is by a receive-data-full interrupt from serial communication interface (SCI) channel 0 or by an A/D converter conversion-end interrupt, and as a source address register otherwise. The IOAR value is held fixed. It is not incremented or decremented when a transfer is executed. The IOARs are not initialized by a reset or in standby mode. Rev. 3.00 Sep 14, 2005 page 209 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.2.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. These registers function in one way in I/O mode and idle mode, and another way in repeat mode. * I/O mode and idle mode Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Undetermined Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter In I/O mode and idle mode, ETCR functions as a 16-bit counter. The count is decremented by 1 each time one transfer is executed. The transfer ends when the count reaches H'0000. * Repeat mode Bit 7 6 5 Initial value Read/Write 4 3 2 1 0 R/W R/W R/W 2 1 0 R/W R/W R/W Undetermined R/W R/W R/W R/W R/W ETCRH Transfer counter Bit 7 6 5 Initial value Read/Write 4 3 Undetermined R/W R/W R/W R/W R/W ETCRL Initial count In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated. The ETCRs are not initialized by a reset or in standby mode. Rev. 3.00 Sep 14, 2005 page 210 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.2.4 Data Transfer Control Registers (DTCR) A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the operation of one DMAC channel. Bit 7 6 5 4 3 2 1 0 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data transfer enable Enables or disables data transfer Data transfer select These bits select the data transfer activation source Data transfer size Selects byte or word size Data transfer interrupt enable Enables or disables the CPU interrupt at the end of the transfer Data transfer increment/decrement Selects whether to increment or decrement the memory address register Repeat enable Selects repeat mode The DTCRs are initialized to H'00 by a reset and in standby mode. Bit 7--Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when activated as specified by bits DTS2 to DTS0. When DTE is 0, the channel is disabled and does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1. Bit 7 DTE Description 0 Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0 (Initial value) when the specified number of transfers have been completed 1 Data transfer is enabled If DTIE is set to 1, a CPU interrupt is requested when DTIE is cleared to 0. Rev. 3.00 Sep 14, 2005 page 211 of 910 REJ09B0258-0300 Section 7 DMA Controller Bit 6--Data Transfer Size (DTSZ): Selects the data size of each transfer. Bit 6 DTSZ Description 0 Byte-size transfer 1 Word-size transfer (Initial value) Bit 5--Data Transfer Increment/Decrement (DTID): Selects whether to increment or decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode. Bit 5 DTID Description 0 MAR is incremented after each data transfer 1 * If DTSZ = 0, MAR is incremented by 1 after each transfer * If DTSZ = 1, MAR is incremented by 2 after each transfer (Initial value) MAR is decremented after each data transfer * If DTSZ = 0, MAR is decremented by 1 after each transfer * If DTSZ = 1, MAR is decremented by 2 after each transfer MAR is not incremented or decremented in idle mode. Bit 4--Repeat Enable (RPE): Selects whether to transfer data in I/O mode, idle mode, or repeat mode. Bit 4 RPE Bit 3 DTIE Description 0 0 I/O mode (Initial value) 1 1 0 Repeat mode 1 Idle mode Operations in these modes are described in sections 7.4.2, I/O Mode, 7.4.3, Idle Mode, and 7.4.4, Repeat Mode. Rev. 3.00 Sep 14, 2005 page 212 of 910 REJ09B0258-0300 Section 7 DMA Controller Bit 3--Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE Description 0 The DEND interrupt requested by DTE is disabled 1 The DEND interrupt requested by DTE is enabled (Initial value) Bits 2 to 0--Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer activation source. Some of the selectable sources differ between channels A and B. Bit 2 DTS2 Bit 1 DTS1 Bit 0 DTS0 0 0 0 Compare match/input capture A interrupt from 16-bit timer channel 0 (Initial value) 1 Compare match/input capture A interrupt from 16-bit timer channel 1 0 Compare match/input capture A interrupt from 16-bit timer channel 2 1 Conversion-end interrupt from A/D converter 0 Transmit-data-empty interrupt from SCI channel 0 1 Receive-data-full interrupt from SCI channel 0 0 Falling edge of DREQ input (channel B) Transfer in full address mode (channel A) 1 Low level of DREQ input (channel B) Transfer in full address mode (channel A) 1 1 0 1 Description Note: See section 7.3.4, Data Transfer Control Registers (DTCR). The same internal interrupt can be selected as an activation source for two or more channels at once. In that case the channels are activated in a priority order, highest-priority channel first. For the priority order, see section 7.4.9, Multiple-Channel Operation. When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a CPU interrupt. Rev. 3.00 Sep 14, 2005 page 213 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.3 Register Descriptions (2) (Full Address Mode) In full address mode the A and B channels operate together. Full address mode is selected as indicated in table 7.4. 7.3.1 Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the source address register of the transfer, and MARB as the destination address register. An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits of MARR are reserved; they cannot be modified and are always read as 1. (Write is invalid.) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Undetermined Read/Write -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MARR MARE MARH MARL Source or destination address The MAR value is incremented or decremented each time one byte or word is transferred, automatically updating the source or destination memory address. For details, see section 7.3.4, Data Transfer Control Registers (DTCR). The MARs are not initialized by a reset or in standby mode. 7.3.2 I/O Address Registers (IOAR) The I/O address registers (IOARs) are not used in full address mode. Rev. 3.00 Sep 14, 2005 page 214 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.3.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. The functions of these registers differ between normal mode and block transfer mode. * Normal mode ETCRA Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Undetermined Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter ETCRB: Is not used in normal mode. In normal mode ETCRA functions as a 16-bit transfer counter. The count is decremented by 1 each time one transfer is executed. The transfer ends when the count reaches H'0000. ETCRB is not used. Rev. 3.00 Sep 14, 2005 page 215 of 910 REJ09B0258-0300 Section 7 DMA Controller * Block transfer mode ETCRA Bit 7 6 5 4 Initial value Read/Write 3 2 1 0 R/W R/W R/W 2 1 0 R/W R/W R/W Undetermined R/W R/W R/W R/W R/W ETCRAH Block size counter Bit 7 6 5 4 Initial value Read/Write 3 Undetermined R/W R/W R/W R/W R/W ETCRAL Initial block size ETCRB Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Undetermined Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Block transfer counter In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the initial block size. ETCRAH is decremented by 1 each time one byte or word is transferred. When the count reaches H'00, ETCRAH is reloaded from ETCRAL. Blocks consisting of an arbitrary number of bytes or words can be transferred repeatedly by setting the same initial block size value in ETCRAH and ETCRAL. In block transfer mode ETCRB functions as a 16-bit block transfer counter. ETCRB is decremented by 1 each time one block is transferred. The transfer ends when the count reaches H'0000. The ETCRs are not initialized by a reset or in standby mode. Rev. 3.00 Sep 14, 2005 page 216 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.3.4 Data Transfer Control Registers (DTCR) The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address mode. DTCRA Bit 7 6 5 4 3 2 1 0 DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data transfer enable Enables or disables data transfer Data transfer size Selects byte or word size Data transfer interrupt enable Enables or disables the CPU interrupt at the end of the transfer Source address increment/decrement Source address increment/ decrement enable These bits select whether the source address register (MARA) is incremented, decremented, or held fixed during the data transfer Data transfer select 0A Selects block transfer mode Data transfer select 2A and 1A These bits must both be set to 1 DTCRA is initialized to H'00 by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 217 of 910 REJ09B0258-0300 Section 7 DMA Controller Bit 7--Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the channel waits for transfers to be requested. When the specified number of transfers have been completed, the DTE bit is automatically cleared to 0. When DTE is 0, the channel is disabled and does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1. Bit 7 DTE Description 0 Data transfer is disabled (DTE is cleared to 0 when the specified number (Initial value) of transfers have been completed) 1 Data transfer is enabled If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0. Bit 6--Data Transfer Size (DTSZ): Selects the data size of each transfer. Bit 6 DTSZ Description 0 Byte-size transfer 1 Word-size transfer (Initial value) Bit 5--Source Address Increment/Decrement (SAID) and, Bit 4--Source Address Increment/Decrement Enable (SAIDE): These bits select whether the source address register (MARA) is incremented, decremented, or held fixed during the data transfer. Bit 5 SAID Bit 4 SAIDE Description 0 0 MARA is held fixed 1 MARA is incremented after each data transfer 1 * If DTSZ = 0, MARA is incremented by 1 after each transfer * If DTSZ = 1, MARA is incremented by 2 after each transfer 0 MARA is held fixed 1 MARA is decremented after each data transfer (Initial value) * If DTSZ = 0, MARA is decremented by 1 after each transfer * If DTSZ = 1, MARA is decremented by 2 after each transfer Rev. 3.00 Sep 14, 2005 page 218 of 910 REJ09B0258-0300 Section 7 DMA Controller Bit 3--Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE Description 0 The DEND interrupt requested by DTE is disabled 1 The DEND interrupt requested by DTE is enabled (Initial value) Bits 2 and 1--Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full address mode when DTS2A and DTS1A are both set to 1. Bit 0--Data Transfer Select 0A (DTS0A): Selects normal mode or block transfer mode. Bit 0 DTS0A Description 0 Normal mode 1 Block transfer mode (Initial value) Operations in these modes are described in sections 7.4.5, Normal Mode, and 7.4.6, Block Transfer Mode. Rev. 3.00 Sep 14, 2005 page 219 of 910 REJ09B0258-0300 Section 7 DMA Controller DTCRB Bit 7 6 5 4 3 2 1 0 DTME DAID DAIDE TMS DTS2B DTS1B DTS0B Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data transfer master enable Enables or disables data transfer, together with the DTE bit, and is cleared to 0 by an interrupt Reserved bit Transfer mode select Selects whether the block area is the source or destination in block transfer mode Destination address increment/decrement Destination address increment/decrement enable These bits select whether the destination address register (MARB) is incremented, decremented, or held fixed during the data transfer Data transfer select 2B to 0B These bits select the data transfer activation source DTCRB is initialized to H'00 by a reset and in standby mode. Bit 7--Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further information on operation in block transfer mode, see section 7.6.6, NMI Interrupts and Block Transfer Mode. DTME is set to 1 by reading the register while DTME = 0, then writing 1. Bit 7 DTME Description 0 Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt occurs) 1 Data transfer is enabled Rev. 3.00 Sep 14, 2005 page 220 of 910 REJ09B0258-0300 (Initial value) Section 7 DMA Controller Bit 6--Reserved: Although reserved, this bit can be written and read. Bit 5--Destination Address Increment/Decrement (DAID) and, Bit 4--Destination Address Increment/Decrement Enable (DAIDE): These bits select whether the destination address register (MARB) is incremented, decremented, or held fixed during the data transfer. Bit 5 DAID Bit 4 DAIDE Description 0 0 MARB is held fixed 1 MARB is incremented after each data transfer 1 (Initial value) * If DTSZ = 0, MARB is incremented by 1 after each data transfer * If DTSZ = 1, MARB is incremented by 2 after each data transfer 0 MARB is held fixed 1 MARB is decremented after each data transfer * If DTSZ = 0, MARB is decremented by 1 after each data transfer * If DTSZ = 1, MARB is decremented by 2 after each data transfer Bit 3--Transfer Mode Select (TMS): Selects whether the source or destination is the block area in block transfer mode. Bit 3 TMS Description 0 Destination is the block area in block transfer mode 1 Source is the block area in block transfer mode (Initial value) Rev. 3.00 Sep 14, 2005 page 221 of 910 REJ09B0258-0300 Section 7 DMA Controller Bits 2 to 0--Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the data transfer activation source. The selectable activation sources differ between normal mode and block transfer mode. Normal mode Bit 2 DTS2B Bit 1 DTS1B Bit 0 DTS0B Description 0 0 0 Auto-request (burst mode) 1 Cannot be used 0 Auto-request (cycle-steal mode) 1 Cannot be used 0 Cannot be used 1 Cannot be used 0 Falling edge of DREQ 1 1 0 1 1 (Initial value) Low level input at DREQ Block transfer mode Bit 2 Bit 1 Bit 0 DTS2B DTS1B DTS0B Description 0 0 0 Compare match/input capture A interrupt from 16-bit timer channel 0 (Initial value) 1 Compare match/input capture A interrupt from 16-bit timer channel 1 0 Compare match/input capture A interrupt from 16-bit timer channel 2 1 Conversion-end interrupt from A/D converter 0 0 Cannot be used 1 Cannot be used 1 0 Falling edge of DREQ 1 Cannot be used 1 1 The same internal interrupt can be selected to activate two or more channels. The channels are activated in a priority order, highest priority first. For the priority order, see section 7.4.9, Multiple-Channel Operation. Rev. 3.00 Sep 14, 2005 page 222 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4 Operation 7.4.1 Overview Table 7.5 summarizes the DMAC modes. Table 7.5 DMAC Modes Transfer Mode Short address mode Activation I/O mode Idle mode Repeat mode Notes Compare match/input * capture A interrupt from 16-bit timer channels 0 to 2 Transmit-data-empty and receive-data-full interrupts from SCI channel 0 Up to four channels can operate independently * Only the B channels support external requests * A and B channels are paired; up to two channels are available Conversion-end interrupt from A/D converter External request Full address mode Normal mode Auto-request External request Block transfer mode Compare match/input * capture A interrupt from 16-bit timer channels 0 to 2 Conversion-end interrupt from A/D converter Burst mode transfer or cycle-steal mode transfer can be selected for autorequests External request A summary of operations in these modes follows. I/O Mode: One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. One 24-bit address and one 8-bit address are specified. The transfer direction is determined automatically from the activation source. Idle Mode: One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The transfer direction is determined automatically from the activation source. Rev. 3.00 Sep 14, 2005 page 223 of 910 REJ09B0258-0300 Section 7 DMA Controller Repeat Mode: One byte or word is transferred per request. A designated number of these transfers are executed. When the designated number of transfers are completed, the initial address and counter value are restored and operation continues. No CPU interrupt is requested. One 24bit address and one 8-bit address are specified. The transfer direction is determined automatically from the activation source. Normal Mode * Auto-request The DMAC is activated by register setup alone, and continues executing transfers until the designated number of transfers have been completed. A CPU interrupt can be requested at completion of the transfers. Both addresses are 24-bit addresses. Cycle-steal mode The bus is released to another bus master after each byte or word is transferred. Burst mode Unless requested by a higher-priority bus master, the bus is not released until the designated number of transfers have been completed. * External request One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. Both addresses are 24-bit addresses. Block Transfer Mode: One block of a specified size is transferred per request. A designated number of block transfers are executed. At the end of each block transfer, one address is restored to its initial value. When the designated number of blocks have been transferred, a CPU interrupt can be requested. Both addresses are 24-bit addresses. Rev. 3.00 Sep 14, 2005 page 224 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4.2 I/O Mode I/O mode can be selected independently for each channel. One byte or word is transferred at each transfer request in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 7.6 indicates the register functions in I/O mode. Table 7.6 Register Functions in I/O Mode Function Activated by SCI 0 ReceiveData-Full Other Interrupt Activation Initial Setting Operation 0 Destination address register Source address register Destination or source start address Incremented or decremented once per transfer 0 Source address register Destination address register Source or destination address Held fixed 0 Transfer counter Number of transfers Decremented once per transfer until H'0000 is reached and transfer ends Register 23 MAR 23 7 All 1s IOAR 15 ETCR Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address, which is incremented or decremented as each byte or word is transferred. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented. Rev. 3.00 Sep 14, 2005 page 225 of 910 REJ09B0258-0300 Section 7 DMA Controller Figure 7.2 illustrates how I/O mode operates. Transfer Address T IOAR 1 byte or word is transferred per request Address B Legend L = initial setting of MAR N = initial setting of ETCR Address T = L Address B = L + (-1) DTID * (2 DTSZ * N - 1) Figure 7.2 Operation in I/O Mode The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count is 65,536, obtained by setting ETCR to H'0000. Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0, conversion-end interrupts from the A/D converter, and external request signals. Rev. 3.00 Sep 14, 2005 page 226 of 910 REJ09B0258-0300 Section 7 DMA Controller For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR). Figure 7.3 shows a sample setup procedure for I/O mode. I/O mode setup Set source and destination addresses 1 Set transfer count 2 Read DTCR 3 Set DTCR 4 1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in ETCR. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. * Select the DMAC activation source with bits DTS2 to DTS0. * Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. * Clear the RPE bit to 0 to select I/O mode. * Select MAR increment or decrement with the DTID bit. * Select byte size or word size with the DTSZ bit. * Set the DTE bit to 1 to enable the transfer. I/O mode Figure 7.3 I/O Mode Setup Procedure (Example) 7.4.3 Idle Mode Idle mode can be selected independently for each channel. One byte or word is transferred at each transfer request in idle mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 7.7 indicates the register functions in idle mode. Rev. 3.00 Sep 14, 2005 page 227 of 910 REJ09B0258-0300 Section 7 DMA Controller Table 7.7 Register Functions in Idle Mode Function Activated by SCI 0 ReceiveData-Full Other Interrupt Activation Register 23 7 All 1s Destination address register Source address register Destination or Held fixed source address 0 Source address register Destination address register Source or destination address Held fixed 0 Transfer counter Number of transfers Decremented once per transfer until H'0000 is reached and transfer ends IOAR 15 Operation 0 MAR 23 Initial Setting ETCR Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. MAR and IOAR are not incremented or decremented. Figure 7.4 illustrates how idle mode operates. Transfer MAR 1 byte or word is transferred per request Figure 7.4 Operation in Idle Mode Rev. 3.00 Sep 14, 2005 page 228 of 910 REJ09B0258-0300 IOAR Section 7 DMA Controller The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to H'0000. Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0, conversion-end interrupts from the A/D converter, and external request signals. For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR). Figure 7.5 shows a sample setup procedure for idle mode. Idle mode setup Set source and destination addresses 1 Set transfer count 2 Read DTCR 3 Set DTCR 4 1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in ETCR. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. * Select the DMAC activation source with bits DTS2 to DTS0. * Set the DTIE and RPE bits to 1 to select idle mode. * Select byte size or word size with the DTSZ bit. * Set the DTE bit to 1 to enable the transfer. Idle mode Figure 7.5 Idle Mode Setup Procedure (Example) Rev. 3.00 Sep 14, 2005 page 229 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4.4 Repeat Mode Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable timing pattern controller (TPC) in synchronization, for example, with 16-bit timer compare match. Repeat mode can be selected for each channel independently. One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). At the end of the designated number of transfers, MAR and ETCRH are restored to their original values and operation continues. The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-datafull interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 7.8 indicates the register functions in repeat mode. Rev. 3.00 Sep 14, 2005 page 230 of 910 REJ09B0258-0300 Section 7 DMA Controller Table 7.8 Register Functions in Repeat Mode Function Register Activated by SCI 0 ReceiveData-Full Other Interrupt Activation Initial Setting 23 Destination address register Source address register Source address register Destination Source or address destination register address 0 Destination or source start address MAR 7 23 All 1s 0 IOAR 7 0 Incremented or decremented at each transfer until ETCRH reaches H'0000, then restored to initial value Held fixed Transfer counter Number of transfers Decremented once per transfer until H'0000 is reached, then reloaded from ETCRL Initial transfer count Number of transfers Held fixed 0 ETCRH 7 Operation ETCRL Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID bits in DTCR. Specifically, MAR is restored as follows: MAR MAR - (-1)DTID * 2DTSZ * ETCRL ETCRH and ETCRL should be initially set to the same value. In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0, if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No CPU interrupt is requested. Rev. 3.00 Sep 14, 2005 page 231 of 910 REJ09B0258-0300 Section 7 DMA Controller As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented. Figure 7.6 illustrates how repeat mode operates. Transfer Address T IOAR 1 byte or word is transferred per request Legend L = initial setting of MAR N = initial setting of ETCRH and ETCRL Address T = L Address B = L + (-1) DTID * (2DTSZ * N - 1) Address B Figure 7.6 Operation in Repeat Mode The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer count is 255, obtained by setting both ETCRH and ETCRL to H'FF. Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0, conversion-end interrupts from the A/D converter, and external request signals. For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR). Figure 7.7 shows a sample setup procedure for repeat mode. Rev. 3.00 Sep 14, 2005 page 232 of 910 REJ09B0258-0300 Section 7 DMA Controller Repeat mode Set source and destination addresses 1 Set transfer count 2 Read DTCR 3 Set DTCR 4 1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in both ETCRH and ETCRL. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. * Select the DMAC activation source with bits DTS2 to DTS0. * Clear the DTIE bit to 0 and set the RPE bit to 1 to select repeat mode. * Select MAR increment or decrement with the DTID bit. * Select byte size or word size with the DTSZ bit. * Set the DTE bit to 1 to enable the transfer. Repeat mode Figure 7.7 Repeat Mode Setup Procedure (Example) Rev. 3.00 Sep 14, 2005 page 233 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4.5 Normal Mode In normal mode the A and B channels are combined. One byte or word is transferred per request. A designated number of these transfers are executed. Addresses are specified in MARA and MARB. Table 7.9 indicates the register functions in I/O mode. Table 7.9 Register Functions in Normal Mode Register Function Initial Setting Operation MARA 0 Source address register Source start address Incremented or decremented once per transfer, or held fixed MARB 0 Destination address register Destination start address Incremented or decremented once per transfer, or held fixed 0 Transfer counter Number of transfers Decremented once per transfer 23 23 15 ETCRA Legend MARA: Memory address register A MARB: Memory address register B ETCRA: Execute transfer count register A The source and destination addresses are both 24-bit addresses. MARA specifies the source address. MARB specifies the destination address. MARA and MARB can be independently incremented, decremented, or held fixed as data is transferred. The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by 1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count is 65,536, obtained by setting ETCRA to H'0000. Rev. 3.00 Sep 14, 2005 page 234 of 910 REJ09B0258-0300 Section 7 DMA Controller Figure 7.8 illustrates how normal mode operates. Transfer Address TA Address T B Address BA Address B B Legend L A = initial setting of MARA L B = initial setting of MARB N = initial setting of ETCRA TA = LA BA = L A + SAIDE * (-1)SAID * (2 DTSZ * N - 1) TB = LB BB = L B + DAIDE * (-1)DAID * (2DTSZ * N - 1) Figure 7.8 Operation in Normal Mode Transfers can be requested (activated) by an external request or auto-request. An auto-requested transfer is activated by the register settings alone. The designated number of transfers are executed automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode the DMAC releases the bus temporarily after each transfer. In burst mode the DMAC keeps the bus until the transfers are completed, unless there is a bus request from a higher-priority bus master. For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR). Rev. 3.00 Sep 14, 2005 page 235 of 910 REJ09B0258-0300 Section 7 DMA Controller Figure 7.9 shows a sample setup procedure for normal mode. Normal mode Set initial source address 1 Set initial destination address 2 1. 2. 3. 4. 5. Set transfer count 3 Set DTCRB (1) 4 Set DTCRA (1) 5 Read DTCRB 6 Set DTCRB (2) 7 Read DTCRA 8 Set DTCRA (2) 9 6. 7. 8. 9. Set the initial source address in MARA. Set the initial destination address in MARB. Set the transfer count in ETCRA. Set the DTCRB bits as follows. * Clear the DTME bit to 0. * Set the DAID and DAIDE bits to select whether MARB is incremented, decremented, or held fixed. * Select the DMAC activation source with bits DTS2B to DTS0B. Set the DTCRA bits as follows. * Clear the DTE bit to 0. * Select byte or word size with the DTSZ bit. * Set the SAID and SAIDE bits to select whether MARA is incremented, decremented, or held fixed. * Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. * Clear the DTS0A bit to 0 and set the DTS2A and DTS1A bits to 1 to select normal mode. Read DTCRB with DTME cleared to 0. Set the DTME bit to 1 in DTCRB. Read DTCRA with DTE cleared to 0. Set the DTE bit to 1 in DTCRA to enable the transfer. Normal mode Note: Carry out settings 1 to 9 with the DEND interrupt masked in the CPU. If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in which case the transfer will not start. Figure 7.9 Normal Mode Setup Procedure (Example) Rev. 3.00 Sep 14, 2005 page 236 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4.6 Block Transfer Mode In block transfer mode the A and B channels are combined. One block of a specified size is transferred per request. A designated number of block transfers are executed. Addresses are specified in MARA and MARB. The block area address can be either held fixed or cycled. Table 7.10 indicates the register functions in block transfer mode. Table 7.10 Register Functions in Block Transfer Mode Register Function Initial Setting Operation 23 0 Source address register Source start address Incremented or decremented once per transfer, or held fixed 0 Destination address register Destination start address Incremented or decremented once per transfer, or held fixed 0 Block size counter Block size Decremented once per transfer until H'00 is reached, then reloaded from ETCRL Initial block size Block size Held fixed Block transfer counter Number of block transfers Decremented once per block transfer until H'0000 is reached and the transfer ends MARA 23 MARB 7 ETCRAH 7 0 ETCRAL 15 0 ETCRB Legend MARA: Memory address register A MARB: Memory address register B ETCRA: Execute transfer count register A ETCRB: Execute transfer count register B The source and destination addresses are both 24-bit addresses. MARA specifies the source address. MARB specifies the destination address. MARA and MARB can be independently incremented, decremented, or held fixed as data is transferred. One of these registers operates as a block area register: even if it is incremented or decremented, it is restored to its initial value at the end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or destination. Rev. 3.00 Sep 14, 2005 page 237 of 910 REJ09B0258-0300 Section 7 DMA Controller If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and ETCRB should initially be set to N. Figure 7.10 illustrates how block transfer mode operates. In this figure, bit TMS is cleared to 0, meaning the block area is the destination. TA Address T B Transfer Block 1 Block area BA Address B B Block 2 M bytes or words are transferred per request Block N Legend L A = initial setting of MARA L B = initial setting of MARB M = initial setting of ETCRAH and ETCRAL N = initial setting of ETCRB T A = LA B A = L A + SAIDE * (-1)SAID * (2 DTSZ * M - 1) T B = LB B B = L B + DAIDE * (-1)DAID * (2DTSZ * M - 1) Figure 7.10 Operation in Block Transfer Mode Rev. 3.00 Sep 14, 2005 page 238 of 910 REJ09B0258-0300 Section 7 DMA Controller When activated by a transfer request, the DMAC executes a burst transfer. During the transfer MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented. When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The memory address register of the block area is also restored to its initial value, and ETCRB is decremented. If ETCRB is not H'0000, the DMAC then waits for the next transfer request. ETCRAH and ETCRAL should be initially set to the same value. The above operation is repeated until ETCRB reaches H'0000, at which point the DTE bit is cleared to 0 and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. Figure 7.11 shows examples of a block transfer with byte data size when the block area is the destination. In (a) the block area address is cycled. In (b) the block area address is held fixed. Transfers can be requested (activated) by compare match/input capture A interrupts from ITU channels 0 to 2, by an A/D converter conversion-end interrupt, and by external request signals. For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR). Rev. 3.00 Sep 14, 2005 page 239 of 910 REJ09B0258-0300 Section 7 DMA Controller Start (DTE = DTME = 1) Transfer requested? Start (DTE = DTME = 1) No Transfer requested? Yes No Yes Get bus Get bus Read from MARA address Read from MARA address MARA = MARA + 1 MARA = MARA + 1 Write to MARB address Write to MARB address MARB = MARB + 1 ETCRAH = ETCRAH - 1 ETCRAH = ETCRAH - 1 No ETCRAH = H'00 No ETCRAH = H'00 Yes Yes Release bus Release bus ETCRAH = ETCRAL MARB = MARB - ETCRAL ETCRAH = ETCRAL ETCRB = ETCRB - 1 ETCRB = ETCRB - 1 ETCRB = H'0000 No ETCRB = H'0000 Yes Yes Clear DTE to 0 and end transfer Clear DTE to 0 and end transfer a. DTSZ = TMS = 0 SAID = DAID = 0 SAIDE = DAIDE = 1 b. DTSZ = TMS = 0 SAID = 0 SAIDE = 1 DAIDE = 0 Figure 7.11 Block Transfer Mode Flowcharts (Examples) Rev. 3.00 Sep 14, 2005 page 240 of 910 REJ09B0258-0300 No Section 7 DMA Controller Figure 7.12 shows a sample setup procedure for block transfer mode. Block transfer mode Set source address 1 Set destination address 2 Set block transfer count 3 Set block size 4 Set DTCRB (1) 5 Set DTCRA (1) 6 Read DTCRB 7 Set DTCRB (2) 8 Read DTCRA 9 Set DTCRA (2) 10 Set the source address in MARA. Set the destination address in MARB. Set the block transfer count in ETCRB. Set the block size (number of bytes or words) in both ETCRAH and ETCRAL. 5. Set the DTCRB bits as follows. * Clear the DTME bit to 0. * Set the DAID and DAIDE bits to select whether MARB is incremented, decremented, or held fixed. * Set or clear the TMS bit to make the block area the source or destination. * Select the DMAC activation source with bits DTS2B to DTS0B. 6. Set the DTCRA bits as follows. * Clear the DTE to 0. * Select byte size or word size with the DTSZ bit. * Set the SAID and SAIDE bits to select whether MARA is incremented, decremented, or held fixed. * Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. * Set bits DTS2A to DTS0A all to 1 to select block transfer mode. 7. Read DTCRB with DTME cleared to 0. 8. Set the DTME bit to 1 in DTCRB. 9. Read DTCRA with DTE cleared to 0. 10. Set the DTE bit to 1 in DTCRA to enable the transfer. 1. 2. 3. 4. Block transfer mode Note: Carry out settings 1 to 10 with the DEND interrupt masked in the CPU. If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in which case the transfer will not start. Figure 7.12 Block Transfer Mode Setup Procedure (Example) Rev. 3.00 Sep 14, 2005 page 241 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4.7 DMAC Activation The DMAC can be activated by an internal interrupt, external request, or auto-request. The available activation sources differ depending on the transfer mode and channel as indicated in table 7.11. Table 7.11 DMAC Activation Sources Short Address Mode Activation Source Internal interrupts External requests Channels 0A and 1A 0B and 1B Full Address Mode Normal Block IMIA0 x IMIA1 x IMIA2 x ADI x TXI0 x x RXI0 x x Falling edge of DREQ x Low input at x DREQ Auto-request Channels x x x x Activation by Internal Interrupts: When an interrupt request is selected as a DMAC activation source and the DTE bit is set to 1, that interrupt request is not sent to the CPU. It is not possible for an interrupt request to activate the DMAC and simultaneously generate a CPU interrupt. When the DMAC is activated by an interrupt request, the interrupt request flag is cleared automatically. If the same interrupt is selected to activate two or more channels, the interrupt request flag is cleared when the highest-priority channel is activated, but the transfer request is held pending on the other channels in the DMAC, which are activated in their priority order. Rev. 3.00 Sep 14, 2005 page 242 of 910 REJ09B0258-0300 Section 7 DMA Controller Activation by External Request: If an external request (DREQ pin) is selected as an activation source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output pin, regardless of the port data direction register (DDR) settings. The DREQ input can be levelsensitive or edge-sensitive. In short address mode and normal mode, an external request operates as follows. If edge sensing is selected, one byte or word is transferred each time a high-to-low transition of the DREQ input is detected. If the next edge is input before the transfer is completed, the next transfer may not be executed. If level sensing is selected, the transfer continues while DREQ is low, until the transfer is completed. The bus is released temporarily after each byte or word has been transferred, however. If the DREQ input goes high during a transfer, the transfer is suspended after the current byte or word has been transferred. When DREQ goes low, the request is held internally until one byte or word has been transferred. The TEND signal goes low during the last write cycle. In block transfer mode, an external request operates as follows. Only edge-sensitive transfer requests are possible in block transfer mode. Each time a high-to-low transition of the DREQ input is detected, a block of the specified size is transferred. The TEND signal goes low during the last write cycle in each block. Activation by Auto-Request: The transfer starts as soon as enabled by register setup, and continues until completed. Cycle-steal mode or burst mode can be selected. In cycle-steal mode the DMAC releases the bus temporarily after transferring each byte or word. Normally, DMAC cycles alternate with CPU cycles. In burst mode the DMAC keeps the bus until the transfer is completed, unless there is a higherpriority bus request. If there is a higher-priority bus request, the bus is released after the current byte or word has been transferred. Rev. 3.00 Sep 14, 2005 page 243 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4.8 DMAC Bus Cycle Figure 7.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address and writes to the destination address. During these read and write operations the bus is not released even if there is another bus request. DMAC cycles comply with bus controller settings in the same way as CPU cycles. CPU cycle T1 T2 T1 DMAC cycle (1 word transfer) T2 Td T1 T2 T1 T2 T3 T1 T2 CPU cycle T3 Source address Destination address Address bus RD HWR LWR Figure 7.13 DMA Transfer Bus Timing (Example) Rev. 3.00 Sep 14, 2005 page 244 of 910 REJ09B0258-0300 T1 T2 T1 T2 Section 7 DMA Controller Figure 7.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This example shows a word-size transfer from a 16-bit two-state access area to another 16-bit twostate access area. The DMAC continues the transfer while the DREQ pin is held low. CPU cycle T1 T2 T3 DMAC cycle Td T1 T2 T1 DMAC cycle (last transfer cycle) CPU cycle T2 T1 T2 Td T1 T2 T1 T2 CPU cycle T1 T2 DREQ Source Destination address address Source Destination address address Address bus RD HWR , LWR TEND Figure 7.14 Bus Timing of DMA Transfer Requested by Low DREQ Input Rev. 3.00 Sep 14, 2005 page 245 of 910 REJ09B0258-0300 Section 7 DMA Controller Figure 7.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three words from a 16-bit two-state access area to another 16-bit two-state access area. CPU cycle T1 T2 CPU cycle DMAC cycle Td T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 Source address Destination address Address bus RD HWR , LWR Figure 7.15 Burst DMA Bus Timing When the DMAC is activated from a DREQ pin there is a minimum interval of four states from when the transfer is requested until the DMAC starts operating. The DREQ pin is not sampled during the time between the transfer request and the start of the transfer. In short address mode and normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the pin is next sampled at the end of one block transfer. Rev. 3.00 Sep 14, 2005 page 246 of 910 REJ09B0258-0300 Section 7 DMA Controller Figure 7.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal mode. CPU cycle T2 T1 T2 T1 CPU cycle DMAC cycle T2 Td T1 T2 T1 T2 T1 T2 DMAC cycle Td T1 T2 DREQ Address bus RD HWR , LWR Minimum 4 states Next sampling point Figure 7.16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode Rev. 3.00 Sep 14, 2005 page 247 of 910 REJ09B0258-0300 Section 7 DMA Controller Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in normal mode. CPU cycle T2 T1 T2 T1 DMAC cycle T2 Td T1 T2 T1 CPU cycle T2 T1 T2 T1 T2 T1 DREQ Address bus RD HWR , LWR Minimum 4 states Next sampling point Figure 7.17 Timing of DMAC Activation by Low DREQ Level in Normal Mode Rev. 3.00 Sep 14, 2005 page 248 of 910 REJ09B0258-0300 Section 7 DMA Controller Figure 7.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block transfer mode. End of 1 block transfer DMAC cycle T1 T2 T1 T2 T1 CPU cycle T2 T1 T2 T1 T2 T1 T2 DMAC cycle Td T1 T2 DREQ Address bus RD HWR , LWR TEND Next sampling Minimum 4 states Figure 7.18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode Rev. 3.00 Sep 14, 2005 page 249 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4.9 Multiple-Channel Operation The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B. Table 7.12 shows the complete priority order. Table 7.12 Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0 High Channel 0B Channel 1A Channel 1 Channel 1B Low If transfers are requested on two or more channels simultaneously, or if a transfer on one channel is requested during a transfer on another channel, the DMAC operates as follows. * When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it starts a transfer on the highest-priority channel at that time. * Once a transfer starts on one channel, requests to other channels are held pending until that channel releases the bus. * After each transfer in short address mode, and each externally-requested or cycle-steal transfer in normal mode, the DMAC releases the bus and returns to step 1. After releasing the bus, if there is a transfer request for another channel, the DMAC requests the bus again. * After completion of a burst-mode transfer, or after transfer of one block in block transfer mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a higher-priority channel or a bus request from a higher-priority bus master, however, the DMAC releases the bus after completing the transfer of the current byte or word. After releasing the bus, if there is a transfer request for another channel, the DMAC requests the bus again. Figure 7.19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst mode, and a transfer request for channel 0A is received while channel 1 is active. Rev. 3.00 Sep 14, 2005 page 250 of 910 REJ09B0258-0300 Section 7 DMA Controller DMAC cycle (channel 1) T1 CPU cycle T2 T1 T2 DMAC cycle (channel 0A) Td T1 T2 T1 CPU cycle T2 T1 T2 DMAC cycle (channel 1) Td T1 T2 T1 T2 Address bus RD HWR , LWR Figure 7.19 Timing of Multiple-Channel Operations 7.4.10 External Bus Requests, DRAM Interface, and DMAC During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer of the current byte or word. If there is a transfer request at this point, the DMAC requests the bus right again. Figure 7.20 shows an example of the timing of insertion of a refresh cycle during a burst transfer on channel 0. Refresh cycle DMAC cycle (channel 0) T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 DMAC cycle (channel 0) Td T1 T2 T1 T2 T1 T2 Address bus RD HWR , LWR Figure 7.20 Bus Timing of DRAM Interface, and DMAC Rev. 3.00 Sep 14, 2005 page 251 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4.11 NMI Interrupts and DMAC NMI interrupts do not affect DMAC operations in short address mode. If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations. In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI input clears the DTME bit to 0. After transferring the current byte or word, the DMAC releases the bus to the CPU. In normal mode, the suspended transfer resumes when the CPU sets the DTME bit to 1 again. Check that the DTE bit is set to 1 and the DTME bit is cleared to 0 before setting the DTME bit to 1. Figure 7.21 shows the procedure for resuming a DMAC transfer in normal mode on channel 0 after the transfer was halted by NMI input. Resuming DMAC transfer in normal mode 1. Check that DTE = 1 and DTME = 0. 2. Read DTCRB while DTME = 0, then write 1 in the DTME bit. 1 DTE = 1 DTME = 0 No Yes Set DTME to 1 2 DMA transfer continues End Figure 7.21 Procedure for Resuming a DMAC Transfer Halted by NMI (Example) For information about NMI interrupts in block transfer mode, see section 7.6.6, NMI Interrupts and Block Transfer Mode. Rev. 3.00 Sep 14, 2005 page 252 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4.12 Aborting a DMAC Transfer When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode, the DTME bit can be used for the same purpose. Figure 7.22 shows the procedure for aborting a DMAC transfer by software. DMAC transfer abort Set DTCR 1. Clear the DTE bit to 0 in DTCR. To avoid generating an interrupt when aborting a DMA transfer, clear the DTIE bit to 0 simultaneously. 1 DMAC transfer aborted Figure 7.22 Procedure for Aborting a DMAC Transfer Rev. 3.00 Sep 14, 2005 page 253 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4.13 Exiting Full Address Mode Figure 7.23 shows the procedure for exiting full address mode and initializing the pair of channels. To set the channels up in another mode after exiting full address mode, follow the setup procedure for the relevant mode. Exiting full address mode Halt the channel 1 Initialize DTCRB 2 Initialize DTCRA 3 1. Clear the DTE bit to 0 in DTCRA, or wait for the transfer to end and the DTE bit to be cleared to 0. 2. Clear all DTCRB bits to 0. 3. Clear all DTCRA bits to 0. Initialized and halted Figure 7.23 Procedure for Exiting Full Address Mode (Example) Rev. 3.00 Sep 14, 2005 page 254 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode When the chip is reset or enters software standby mode, the DMAC is initialized and halts. DMAC operations continue in sleep mode. Figure 7.24 shows the timing of a cycle-steal transfer in sleep mode. Sleep mode CPU cycle T2 DMAC cycle Td T1 T2 T1 DMAC cycle T2 Td T1 T2 T1 T2 Td Address bus RD HWR , LWR Figure 7.24 Timing of Cycle-Steal Transfer in Sleep Mode Rev. 3.00 Sep 14, 2005 page 255 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.5 Interrupts The DMAC generates only DMA-end interrupts. Table 7.13 lists the interrupts and their priority. Table 7.13 DMAC Interrupts Description Interrupt Short Address Mode Full Address Mode Interrupt Priority DEND0A End of transfer on channel 0A End of transfer on channel 0 High DEND0B End of transfer on channel 0B -- DEND1A End of transfer on channel 1A End of transfer on channel 1 DEND1B End of transfer on channel 1B -- Low Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control register (DTCR). Separate interrupt signals are sent to the interrupt controller. The interrupt priority order among channels is channel 0 > channel 1 and channel A > channel B. Figure 7.25 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and DTIE = 1. DTE DMA-end interrupt DTIE Figure 7.25 DMA-End Interrupt Logic The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The DTME bit does not affect interrupt operations. Rev. 3.00 Sep 14, 2005 page 256 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.6 Usage Notes 7.6.1 Note on Word Data Transfer Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set even values in the memory and I/O address registers (MAR and IOAR). 7.6.2 DMAC Self-Access The DMAC itself cannot be accessed during a DMAC cycle. DMAC registers cannot be specified as source or destination addresses. 7.6.3 Longword Access to Memory Address Registers A memory address register can be accessed as longword data at the MARR address. Example MOV.L #LBL, ER0 MOV.L ER0, @MARR Four byte accesses are performed. Note that the CPU may release the bus between the second byte (MARE) and third byte (MARH). Memory address registers should be written and read only when the DMAC is halted. 7.6.4 Note on Full Address Mode Setup Full address mode is controlled by two registers: DTCRA and DTCRB. Care must be taken to prevent the B channel from operating in short address mode during the register setup. The enable bits (DTE and DTME) should not be set to 1 until the end of the setup procedure. Rev. 3.00 Sep 14, 2005 page 257 of 910 REJ09B0258-0300 Section 7 DMA Controller 7.6.5 Note on Activating DMAC by Internal Interrupts When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as the activating source does not occur during the interval after it has been selected but before the DMAC has been enabled. The on-chip supporting module that will generate the interrupt should not be activated until the DMAC has been enabled. If the DMAC must be enabled while the onchip supporting module is active, follow the procedure in figure 7.26. Enabling of DMAC Yes Interrupt handling by CPU Selected interrupt requested? 1 No Clear selected interrupt's enable bit to 0 2 Enable DMAC 3 Set selected interrupt's enable bit to 1 4 1. While the DTE bit is cleared to 0, interrupt requests are sent to the CPU. 2. Clear the interrupt enable bit to 0 in the interrupt-generating on-chip supporting module. 3. Enable the DMAC. 4. Enable the DMAC-activating interrupt. DMAC operates Figure 7.26 Procedure for Enabling DMAC while On-Chip Supporting Module is Operating (Example) If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt, for example, the selected activating source cannot generate CPU interrupts. To terminate DMAC operations in this state, clear the DTE bit to 0 to allow CPU interrupts to be requested. To continue DMAC operations, carry out steps 2 and 4 in figure 7.26 before and after setting the DTME bit to 1. Rev. 3.00 Sep 14, 2005 page 258 of 910 REJ09B0258-0300 Section 7 DMA Controller When 16-bit timer interrupt activates the DMAC, make sure the next interrupt does not occur before the DMA transfer ends. If one 16-bit timer interrupt activates two or more channels, make sure the next interrupt does not occur before the DMA transfers end on all the activated channels. If the next interrupt occurs before a transfer ends, the channel or channels for which that interrupt was selected may fail to accept further activation requests. 7.6.6 NMI Interrupts and Block Transfer Mode If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows. * When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word, then clears the DTME bit to 0 and halts. The halt may occur in the middle of a block. It is possible to find whether a transfer was halted in the middle of a block by checking the block size counter. If the block size counter does not have its initial value, the transfer was halted in the middle of a block. * If the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0. The activation request is not held pending. * While the DTE bit is set to 1 and the DTME bit is cleared to 0, the DMAC is halted and does not accept activating interrupt requests. If an activating interrupt occurs in this state, the DMAC does not operate and does not hold the transfer request pending internally. Neither is a CPU interrupt requested. For this reason, before setting the DTME bit to 1, first clear the enable bit of the activating interrupt to 0. Then, after setting the DTME bit to 1, set the interrupt enable bit to 1 again. See section 7.6.5, Note on Activating DMAC by Internal Interrupts. * When the DTME bit is set to 1, the DMAC waits for the next transfer request. If it was halted in the middle of a block transfer, the rest of the block is transferred when the next transfer request occurs. Otherwise, the next block is transferred when the next transfer request occurs. 7.6.7 Memory and I/O Address Register Values Table 7.14 indicates the address ranges that can be specified in the memory and I/O address registers (MAR and IOAR). Rev. 3.00 Sep 14, 2005 page 259 of 910 REJ09B0258-0300 Section 7 DMA Controller Table 7.14 Address Ranges Specifiable in MAR and IOAR 1-Mbyte Mode 16-Mbyte Mode MAR H'00000 to H'FFFFF (0 to 1048575) H'000000 to H'FFFFFF (0 to 16777215) IOAR H'FFF00 to H'FFFFF (1048320 to 1048575) H'FFFF00 to H'FFFFFF (16776960 to 16777215) MAR bits 23 to 20 are ignored in 1-Mbyte mode. 7.6.8 Bus Cycle when Transfer is Aborted When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead cycle may occur. This dead cycle does not update the halted channel's address register or counter value. Figure 7.27 shows an example in which an auto-requested transfer in cycle-steal mode on channel 0 is aborted by clearing the DTE bit in channel 0. CPU cycle T1 T2 DMAC cycle Td T1 T2 T1 DMAC cycle CPU cycle T2 T1 T2 T3 Td Td CPU cycle T1 Address bus RD HWR, LWR DTE bit is cleared Figure 7.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode Rev. 3.00 Sep 14, 2005 page 260 of 910 REJ09B0258-0300 T2 Section 7 DMA Controller 7.6.9 Transfer Requests by A/D Converter When the A/D converter is set to scan mode and conversion is performed on more than one channel, the A/D converter generates a transfer request when all conversions are completed. The converted data is stored in the appropriate ADDR registers. Block transfer mode and full address mode should therefore be used to transfer all the conversion results at one time. Rev. 3.00 Sep 14, 2005 page 261 of 910 REJ09B0258-0300 Section 7 DMA Controller Rev. 3.00 Sep 14, 2005 page 262 of 910 REJ09B0258-0300 Section 8 I/O Ports Section 8 I/O Ports 8.1 Overview The H8/3068F has 11 input/output ports (ports 1, 2, 3, 4, 5, 6, 7, 8, 9, A, and B). Table 8.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 8.1. Each port has a data direction register (DDR) for selecting input or output, and a data register (DR) for storing output data. In addition to these registers, ports 2, 4, and 5 have an input pull-up control register (PCR) for switching input pull-up transistors on and off. Ports 1 to 6 and port 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can drive one TTL load and a 30-pF capacitive load. Ports 1 to 6 and 8 to B can drive a darlington pair. Ports 1, 2, and 5 can drive LEDs (with 10-mA current sink). Pins P82 to P80, PA7 to PA0 have Schmitt-trigger input circuits. For block diagrams of the ports see appendix C, I/O Port Block Diagrams. Rev. 3.00 Sep 14, 2005 page 263 of 910 REJ09B0258-0300 Section 8 I/O Ports Table 8.1 Port Functions Expanded Modes Port Description Mode 1 P17 to P10/ A7 to A0 Address output pins (A7 to A0) Address output (A7 to A0) and generic input DDR = 0: generic input DDR = 1: address output Generic input/output P27 to P20/ A15 to A8 Address output pins (A15 to A8) Address output (A15 to A8) and generic input DDR = 0: generic input DDR = 1: address output Generic input/output Port 3 * 8-bit I/O port P37 to P30/ D15 to D8 Data input/output (D15 to D8) Generic input/output Port 4 * 8-bit I/O port P47 to P40/ D7 to D0 Data input/output (D7 to D0) and 8-bit generic input/output 8-bit bus mode: generic input/output 16-bit bus mode: data input/output Generic input/output P53 to P50/ A19 to A16 Address output (A19 to A16) Generic input/output Port 1 * 8-bit I/O port * Can drive LEDs Port 2 * 8-bit I/O port * Built-in input pullup transistors Mode 2 Mode 3 Single-Chip Modes Pins Mode 4 Mode 5 * Can drive LEDs * Built-in input pullup transistors Port 5 * 4-bit I/O port * Built-in input pullup transistors * Can drive LEDs Port 6 * 8-bit I/O port Port 7 * 8-bit I/O port Address output (A19 to A16) and 4-bit generic input DDR = 0: generic input DDR = 1: address output P67/ Clock output () and generic input P66/LWR P65/HWR P64/RD P63/AS Bus control signal output (LWR, HWR, RD, AS) P62/BACK P61/BREQ P60/WAIT Bus control signal input/output (BACK, BREQ, WAIT) and 3-bit generic input/output P77/AN7/DA1 P76/AN6/DA0 Analog input (AN7, AN6) to A/D converter, analog output (DA1, DA0) from D/A converter, and generic input P75 to P70/ AN5 to AN0 Analog input (AN5 to AN0) to A/D converter, and generic input Rev. 3.00 Sep 14, 2005 page 264 of 910 REJ09B0258-0300 Mode 6 Mode 7 Generic input/output Section 8 I/O Ports Expanded Modes Port Description Port 8 * 5-bit I/O port Pins Mode 1 P84/CS0 DDR = 0: generic input DDR = 1 (reset value): CS0 output P83/IRQ3/ CS1/ADTRG IRQ3 input, CS1 output, external trigger input (ADTRG) to A/D converter, and * P82 to P80 have Schmitt inputs Port 9 * 6-bit I/O port Port A * 8-bit I/O port * Schmitt inputs Port B * 8-bit I/O port Mode 2 Mode 3 Mode 4 Single-Chip Modes Mode 5 Mode 6 DDR = 0 (reset value): generic input DDR = 1: CS0 output Generic input/output generic input DDR = 0 (after reset): generic input DDR = 1: CS1 output Mode 7 IRQ3 input, external trigger input (ADTRG) to A/D converter, and generic input/output P82/IRQ2/CS2 IRQ2 and IRQ1 input, CS2 and CS3 output, and generic input* P81/IRQ1/CS3 DDR = 0 (reset value): generic input DDR = 1: CS2 and CS3 output IRQ2 and IRQ1 input and P80/IRQ0 /RFSH IRQ0 input, RFSH output, and generic input/output IRQ0 input and generic P95/IRQ5 /SCK1 P94/IRQ4 /SCK0 P93/RxD1 P92/RxD0 P91/TxD1 P90/TxD0 Input and output (SCK1, SCK0, RxD1, RxD0, TxD1, TxD0) for serial communication interfaces 1 and 0 (SCI1/0), IRQ5 and IRQ4 input, and 6-bit generic input/output PA7/TP7/ Address output Output (TP7) from programmable timing pattern (A20) controller (TPC), input or output (TIOCB2) for 16-bit timer and generic input/output TIOCB2/A20 generic input/output input/output Address output (A20), TPC output (TP7), input or output (TIOCB2) for 16-bit timer, and generic input/output TPC output (TP7), 16-bit timer input or output (TIOCB2), and generic input/output PA6/TP6/ TIOCA2/A21 PA5/TP5/ TIOCB1/A22 PA4/TP4/ TIOCA1/A23 TPC output (TP6 to TP4), TPC output (TP6 to TP4),16-bit timer input and 16-bit timer input and output (TIOCA2, TIOCB1, TIOCA1), address output output (TIOCA2, TIOCB1, (A23 to A21), and generic input/output TIOCA1) , and generic input/output PA3/TP3/ TIOCB0/ TCLKD PA2/TP2/ TIOCA0/ TCLKC PA1/TP1/ TCLKB /TEND1 PA0/TP0/ TCLKA /TEND0 TPC output (TP3 to TP0), 16-bit timer input and output (TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA), 8-bit timer input (TCLKD, TCLKC, TCLKB, TCLKA), output (TEND1, TEND0) from DMA controller (DMAC), and generic input/output PB7/TP15/ RXD2 PB6/TP14/ TXD2 PB5/TP13/ SCK2/LCAS PB4/TP12/ TPC output (TP15 to TP12), SCI2 input and output (SCK2 , RxD2, TxD2), DRAM TPC output (TP15 to interface output (LCAS, UCAS), and generic input/output TP12), SCI2 input and output (SCK2, RxD2, TxD2), and generic input/output PB3/TP11/ TMIO3/ DREQ1/CS4 PB2/TP10/ TMO2/CS5 PB1/TP9/ TMIO1/ DREQ0/CS6 PB0/TP8/ TMO0/CS7 TPC output (TP11 to TP8), 8-bit timer input and output (TMIO3, TMO2, TMIO1, TMO0), DMAC input (DREQ1, DREQ0), CS7 to CS4 output, and generic input/output TPC output (TP6 to TP4), 16-bit timer input and output (TIOCA2, TIOCB1, TIOCA1) and generic input/output UCAS TPC output (TP11 to TP8), 8-bit timer input and output (TMIO3, TMO2, TMIO1, TMO0), DMAC input (DREQ1, DREQ0), and generic input/output Note: * P81 can be used as an output port by making a setting in DRCRA. Rev. 3.00 Sep 14, 2005 page 265 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.2 Port 1 8.2.1 Overview Port 1 is an 8-bit input/output port also used for address output, with the pin configuration shown in figure 8.1. The pin functions differ between the expanded modes with on-chip ROM disabled, expanded modes with on-chip ROM enabled, and single-chip mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), they are address bus output pins (A7 to A0). In modes 5 (expanded modes with on-chip ROM enabled), settings in the port 1 data direction register (P1DDR) can designate pins for address bus output (A7 to A0) or generic input. In mode 6 and 7 (single-chip mode), port 1 is a generic input/output port. When DRAM is connected to area 2, 3, 4, 5, A7 to A0 output row and column addresses in read and write cycles. For details see section 6.5, DRAM Interface. Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or a darlington transistor pair. Port 1 pins Port 1 Modes 1 to 4 Modes 5 Mode 6 and 7 P17 /A 7 A 7 (output) P17 (input)/A 7 (output) P17 (input/output) P16 /A 6 A 6 (output) P16 (input)/A 6 (output) P16 (input/output) P15 /A 5 A 5 (output) P15 (input)/A 5 (output) P15 (input/output) P14 /A 4 A 4 (output) P14 (input)/A 4 (output) P14 (input/output) P13 /A 3 A 3 (output) P13 (input)/A 3 (output) P13 (input/output) P12 /A 2 A 2 (output) P12 (input)/A 2 (output) P12 (input/output) P11 /A 1 A 1 (output) P11 (input)/A 1 (output) P11 (input/output) P10 /A 0 A 0 (output) P10 (input)/A 0 (output) P10 (input/output) Figure 8.1 Port 1 Pin Configuration Rev. 3.00 Sep 14, 2005 page 266 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.2.2 Register Descriptions Table 8.2 summarizes the registers of port 1. Table 8.2 Port 1 Registers Initial Value Address* Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7 H'EE000 Port 1 data direction register P1DDR W H'FF H'00 H'FFFD0 Port 1 data register R/W H'00 H'00 P1DR Note: * Lower 20 bits of the address in advanced mode. Port 1 Data Direction Register (P1DDR): P1DDR is an 8-bit write-only register that can select input or output for each pin in port 1. Bit 7 6 5 4 3 2 1 0 P1 7 DDR P1 6 DDR P1 5 DDR P1 4 DDR P1 3 DDR P1 2 DDR P1 1 DDR P1 0 DDR Modes Initial value 1 to 4 Read/Write Modes Initial value 5 to 7 Read/Write 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 W W W W W W W W Port 1 data direction 7 to 0 These bits select input or output for port 1 pins Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P1DDR values are fixed at 1. Port 1 functions as an address bus. Modes 5 (Expanded Modes with On-Chip ROM Enabled): After a reset, port 1 functions as an input port.A pin in port 1 becomes an address output pin if the corresponding P1DDR bit is set to 1, and a generic input pin if this bit is cleared to 0. Mode 6 and 7 (Single-Chip Mode): Port 1 functions as an input/output port. A pin in port 1 becomes an output port if the corresponding P1DDR bit is set to 1, and an input port if this bit is cleared to 0. Rev. 3.00 Sep 14, 2005 page 267 of 910 REJ09B0258-0300 Section 8 I/O Ports In modes 1 to 4, P1DDR bits are always read as 1, and cannot be modified. In modes 5 to 7, P1DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P1DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 to 7, by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 1 is functioning as an input/output port and a P1DDR bit is set to 1, the corresponding pin maintains its output state. Port 1 Data Register (P1DR): P1DR is an 8-bit readable/writable register that stores port 1 output data. When port 1 functions as an output port, the value of this register is output. When this register is read, the pin logic level is read for bits for which the P1DDR setting is 0, and the P1DR value is read for bits for which the P1DDR setting is 1. Bit 7 6 5 4 3 2 1 0 P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 1 data 7 to 0 These bits store data for port 1 pins P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 3.00 Sep 14, 2005 page 268 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.3 Port 2 8.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 8.2. The pin functions differ according to the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus output pins (A15 to A8). In modes 5 (expanded modes with on-chip ROM enabled), settings in the port 2 data direction register (P2DDR) can designate pins for address bus output (A15 to A8) or generic input. In mode 6 and 7 (single-chip mode), port 2 is a generic input/output port. When DRAM is connected to areas 2 to 5, A12 to A8 output row and column addresses in read and write cycles. For details see section 6.5, DRAM Interface. Port 2 has software-programmable built-in pull-up transistors. Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or a darlington transistor pair. Port 2 Port 2 pins Modes 1 to 4 Modes 5 Mode 6 and 7 P27 /A 15 A15 (output) P27 (input)/A15 (output) P27 (input/output) P26 /A 14 A14 (output) P26 (input)/A14 (output) P26 (input/output) P25 /A 13 A13 (output) P25 (input)/A13 (output) P25 (input/output) P24 /A 12 A12 (output) P24 (input)/A12 (output) P24 (input/output) P23 /A 11 A11 (output) P23 (input)/A11 (output) P23 (input/output) P22 /A 10 A10 (output) P22 (input)/A10 (output) P22 (input/output) P21 /A 9 A9 (output) P21 (input)/A9 (output) P21 (input/output) P20 /A 8 A8 (output) P20 (input)/A8 (output) P20 (input/output) Figure 8.2 Port 2 Pin Configuration Rev. 3.00 Sep 14, 2005 page 269 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.3.2 Register Descriptions Table 8.3 summarizes the registers of port 2. Table 8.3 Port 2 Registers Initial Value Address* Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7 H'EE001 Port 2 data direction register P2DDR W H'FF H'00 H'FFFD1 Port 2 data register P2DR R/W H'00 H'00 H'EE03C Port 2 input pull-up MOS control register P2PCR R/W H'00 H'00 Note: * Lower 20 bits of the address in advanced mode. Port 2 Data Direction Register (P2DDR): P2DDR is an 8-bit write-only register that can select input or output for each pin in port 2. Bit 7 6 5 4 3 2 1 0 P2 7 DDR P2 6 DDR P2 5 DDR P2 4 DDR P2 3 DDR P2 2 DDR P2 1 DDR P2 0 DDR Modes Initial value 1 to 4 Read/Write Modes Initial value 5 to 7 Read/Write 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 W W W W W W W W Port 2 data direction 7 to 0 These bits select input or output for port 2 pins Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P2DDR values are fixed at 1. Port 2 functions as an address bus. Modes 5 (Expanded Modes with On-Chip ROM Enabled): Following a reset, port 2 is an input port. A pin in port 2 becomes an address output pin if the corresponding P2DDR bit is set to 1, and a generic input port if this bit is cleared to 0. Mode 6 and 7 (Single-Chip Mode): Port 2 functions as an input/output port. A pin in port 2 becomes an output port if the corresponding P2DDR bit is set to 1, and an input port if this bit is cleared to 0. Rev. 3.00 Sep 14, 2005 page 270 of 910 REJ09B0258-0300 Section 8 I/O Ports In modes 1 to 4, P2DDR bits are always read as 1, and cannot be modified. In modes 5 to 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P2DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 to 7, by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 2 is functioning as an input/output port and a P2DDR bit is set to 1, the corresponding pin maintains its output state. Port 2 Data Register (P2DR): P2DR is an 8-bit readable/writable register that stores output data for Port 2. When port 2 functions as an output port, the value of this register is output. When a bit in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is returned. When a bit in P2DDR is cleared to 0, if port 2 is read the corresponding pin logic level is read. Bit 7 6 5 4 3 2 1 0 P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 2 data 7 to 0 These bits store data for port 2 pins P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 2 Input Pull-Up MOS Control Register (P2PCR): P2PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 2. Bit 7 6 5 4 3 2 1 0 P2 7 PCR P2 6 PCR P2 5 PCR P2 4 PCR P2 3 PCR P2 2 PCR P2 1 PCR P2 0 PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 2 input pull-up MOS control 7 to 0 These bits control input pull-up transistors built into port 2 In modes 5 to 7, when a P2DDR bit is cleared to 0 (selecting generic input), if the corresponding bit in P2PCR is set to 1, the input pull-up transistor is turned on. Rev. 3.00 Sep 14, 2005 page 271 of 910 REJ09B0258-0300 Section 8 I/O Ports P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Table 8.4 Input Pull-Up Transistor States (Port 2) Mode Reset Hardware Standby Mode Software Standby Mode Other Modes 1 2 3 4 Off Off Off Off 5 6 7 Off Off On/off On/off Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0. Otherwise, it is off. Rev. 3.00 Sep 14, 2005 page 272 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.4 Port 3 8.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 8.3. Port 3 is a data bus in modes 1 to 5 (expanded modes) and a generic input/output port in mode 6, 7 (single-chip mode). Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Port 3 Port 3 pins Modes 1 to 5 Mode 6 and 7 P37 /D15 D15 (input/output) P37 (input/output) P36 /D14 D14 (input/output) P36 (input/output) P35 /D13 D13 (input/output) P35 (input/output) P34 /D12 D12 (input/output) P34 (input/output) P33 /D11 D11 (input/output) P33 (input/output) P32 /D10 D10 (input/output) P32 (input/output) P31 /D9 D9 (input/output) P31 (input/output) P30 /D8 D8 (input/output) P30 (input/output) Figure 8.3 Port 3 Pin Configuration 8.4.2 Register Descriptions Table 8.5 summarizes the registers of port 3. Table 8.5 Port 3 Registers Address* Name Abbreviation R/W Initial Value H'EE002 Port 3 data direction register P3DDR W H'00 H'FFFD2 Port 3 data register P3DR R/W H'00 Note: * Lower 20 bits of the address in advanced mode. Rev. 3.00 Sep 14, 2005 page 273 of 910 REJ09B0258-0300 Section 8 I/O Ports Port 3 Data Direction Register (P3DDR): P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3. Bit 7 6 5 4 3 2 1 0 P3 7 DDR P3 6 DDR P3 5 DDR P3 4 DDR P3 3 DDR P3 2 DDR P3 1 DDR P3 0 DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 3 data direction 7 to 0 These bits select input or output for port 3 pins Modes 1 to 5 (Expanded Modes): Port 3 functions as a data bus, regardless of the P3DDR settings. Mode 6 and 7 (Single-Chip Mode): Port 3 functions as an input/output port. A pin in port 3 becomes an output port if the corresponding P3DDR bit is set to 1, and an input port if this bit is cleared to 0. P3DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 3 is functioning as an input/output port and a P3DDR bit is set to 1, the corresponding pin maintains its output state. Port 3 Data Register (P3DR): P3DR is an 8-bit readable/writable register that stores output data for port 3. When port 3 functions as an output port, the value of this register is output. When a bit in P3DDR is set to 1, if port 3 is read the value of the corresponding P3DR bit is returned. When a bit in P3DDR is cleared to 0, if port 3 is read the corresponding pin logic level is read. Bit 7 6 5 4 3 2 1 0 P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 3 data 7 to 0 These bits store data for port 3 pins P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 3.00 Sep 14, 2005 page 274 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.5 Port 4 8.5.1 Overview Port 4 is an 8-bit input/output port with the pin configuration shown in figure 8.4. The pin functions differ depending on the operating mode. In modes 1 to 5 (expanded modes), when the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port. When at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip operates in 16-bit bus mode and port 4 becomes part of the data bus. In mode 6, 7 (single-chip mode), port 4 is a generic input/output port. Port 4 has software-programmable built-in pull-up transistors. Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Port 4 Port 4 pins Modes 1 to 5 Mode 6 and 7 P47 /D7 P47 (input/output)/D7 (input/output) P47 (input/output) P46 /D6 P46 (input/output)/D6 (input/output) P46 (input/output) P45 /D5 P45 (input/output)/D5 (input/output) P45 (input/output) P44 /D4 P44 (input/output)/D4 (input/output) P44 (input/output) P43 /D3 P43 (input/output)/D3 (input/output) P43 (input/output) P42 /D2 P42 (input/output)/D2 (input/output) P42 (input/output) P41 /D1 P41 (input/output)/D1 (input/output) P41 (input/output) P40 /D0 P40 (input/output)/D0 (input/output) P40 (input/output) Figure 8.4 Port 4 Pin Configuration Rev. 3.00 Sep 14, 2005 page 275 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.5.2 Register Descriptions Table 8.6 summarizes the registers of port 4. Table 8.6 Port 4 Registers Address* Name Abbreviation R/W Initial Value H'EE003 Port 4 data direction register P4DDR W H'00 H'FFFD3 Port 4 data register P4DR R/W H'00 H'EE03E Port 4 input pull-up control register P4PCR R/W H'00 Note: * Lower 20 bits of the address in advanced mode. Port 4 Data Direction Register (P4DDR): P4DDR is an 8-bit write-only register that can select input or output for each pin in port 4. Bit 7 6 5 4 3 2 1 0 P4 7 DDR P4 6 DDR P4 5 DDR P4 4 DDR P4 3 DDR P4 2 DDR P4 1 DDR P4 0 DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 4 data direction 7 to 0 These bits select input or output for port 4 pins Modes 1 to 5 (Expanded Modes): When all areas are designated as 8-bit-access areas by the bus controller's bus width control register (ABWCR), selecting 8-bit bus mode, port 4 functions as an input/output port. In this case, a pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1, and an input port if this bit is cleared to 0. When at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4 functions as part of the data bus, regardless of the P4DDR settings. Mode 6 and 7 (Single-Chip Mode): Port 4 functions as an input/output port. A pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1, and an input port if this bit is cleared to 0. P4DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 3.00 Sep 14, 2005 page 276 of 910 REJ09B0258-0300 Section 8 I/O Ports ABWCR and P4DDR are not initialized in software standby mode. Therefore, if a transition is made to software standby mode while port 4 is functioning as an input/output port and a P4DDR bit is set to 1, the corresponding pin maintains its output state. Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data for port 4. When port 4 functions as an output port, the value of this register is output. When a bit in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned. When a bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin logic level is read. Bit 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 4 data 7 to 0 These bits store data for port 4 pins P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 4 Input Pull-Up MOS Control Register (P4PCR): P4PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 4. Bit 7 6 5 4 3 2 1 0 P4 7 PCR P4 6 PCR P4 5 PCR P4 4 PCR P4 3 PCR P4 2 PCR P4 1 PCR P4 0 PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 4 input pull-up control 7 to 0 These bits control input pull-up transistors built into port 4 In mode 6 and 7 (single-chip mode), and in 8-bit bus mode in modes 1 to 5 (expanded modes), when a P4DDR bit is cleared to 0 (selecting generic input), if the corresponding P4PCR bit is set to 1, the input pull-up transistor is turned on. P4PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 3.00 Sep 14, 2005 page 277 of 910 REJ09B0258-0300 Section 8 I/O Ports Table 8.7 summarizes the states of the input pull-ups in each operating mode. Table 8.7 Input Pull-Up Transistor States (Port 4) Mode 1 to 5 8-bit bus mode Reset Hardware Standby Mode Software Standby Mode Other Modes Off Off On/off On/off Off Off On/off On/off 16-bit bus mode 6 and 7 Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off. Rev. 3.00 Sep 14, 2005 page 278 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.6 Port 5 8.6.1 Overview Port 5 is a 4-bit input/output port with the pin configuration shown in figure 8.5. The pin functions differ depending on the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 5 consists of address output pins (A19 to A16). In modes 5 (expanded modes with on-chip ROM enabled), settings in the port 5 data direction register (P5DDR) designate pins for address bus output (A19 to A16) or generic input. In mode 6, 7 (single-chip mode), port 5 is a generic input/output port. Port 5 has software-programmable built-in pull-up transistors. Pins in port 5 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or a darlington transistor pair. Port 5 Port 5 pins Modes 1 to 4 Mode 5 Mode 6 and 7 P53 /A 19 A19 (output) P5 3 (input)/A19 (output) P5 3 (input/output) P52 /A 18 A18 (output) P5 2 (input)/A18 (output) P5 2 (input/output) P51 /A 17 A17 (output) P5 1 (input)/A17 (output) P5 1 (input/output) P50 /A 16 A16 (output) P5 0 (input)/A16 (output) P5 0 (input/output) Figure 8.5 Port 5 Pin Configuration Rev. 3.00 Sep 14, 2005 page 279 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.6.2 Register Descriptions Table 8.8 summarizes the registers of port 5. Table 8.8 Port 5 Registers Initial Value Address* Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7 H'EE004 P5DDR W H'FF H'F0 P5DR R/W H'F0 H'F0 R/W H'F0 H'F0 Port 5 data direction register H'FFFD4 Port 5 data register H'EE03F Port 5 input pull-up control register P5PCR Note: * Lower 20 bits of the address in advanced mode. Port 5 Data Direction Register (P5DDR): P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5. Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified. Bit Modes Initial value 1 to 4 Read/Write Modes Initial value 5 to 7 Read/Write 7 6 5 4 -- -- -- -- 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- 1 1 1 1 0 0 0 0 -- -- -- -- W W W W Reserved bits 3 2 1 0 P5 3 DDR P5 2 DDR P5 1 DDR P5 0 DDR Port 5 data direction 3 to 0 These bits select input or output for port 5 pins Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P5DDR values are fixed at 1. Port 5 functions as an address bus. Modes 5 (Expanded Modes with On-Chip ROM Enabled): Following a reset, port 5 is an input port. A pin in port 5 becomes an address output pin if the corresponding P5DDR bit is set to 1, and an input port if this bit is cleared to 0. Mode 6 and 7 (Single-Chip Mode): Port 5 functions as an input/output port. A pin in port 5 becomes an output port if the corresponding P5DDR bit is set to 1, and an input port if this bit is cleared to 0. Rev. 3.00 Sep 14, 2005 page 280 of 910 REJ09B0258-0300 Section 8 I/O Ports In modes 1 to 4, P5DDR bits are always read as 1, and cannot be modified. In modes 5 to 7, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P5DDR is initialized to H'FF in modes 1 to 4, and to H'F0 in modes 5 to 7, by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 5 is functioning as an input/output port and a P5DDR bit is set to 1, the corresponding pin maintains its output state. Port 5 Data Register (P5DR): P5DR is an 8-bit readable/writable register that stores output data for port 5. When port 5 functions as an output port, the value of this register is output. When a bit in P5DDR is set to 1, if port 5 is read the value of the corresponding P5DR bit is returned. When a bit in P5DDR is cleared to 0, if port 5 is read the corresponding pin logic level is read. Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified. Bit 7 6 5 4 3 2 1 0 -- -- -- -- P5 3 P5 2 P5 1 P5 0 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W Reserved bits Port 5 data 3 to 0 These bits store data for port 5 pins P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 3.00 Sep 14, 2005 page 281 of 910 REJ09B0258-0300 Section 8 I/O Ports Port 5 Input Pull-Up MOS Control Register (P5PCR): P5PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 5. Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified. Bit 7 6 5 4 2 Initial value 1 1 1 1 0 0 0 0 Read/Write R/W R/W R/W R/W 3 1 0 P5 3 PCR P5 2 PCR P5 1 PCR P5 0 PCR Reserved bits Port 5 input pull-up control 3 to 0 These bits control input pull-up transistors built into port 5 In modes 5 to 7, when a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding bit in P5PCR is set to 1, the input pull-up transistor is turned on. P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Table 8.9 summarizes the states of the input pull-ups in each mode. Table 8.9 Input Pull-Up Transistor States (Port 5) Mode Reset Hardware Standby Mode Software Standby Mode Other Modes 1 2 3 4 Off Off Off Off 5 6 7 Off Off On/off On/off Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P5PCR = 1 and P5DDR = 0. Otherwise, it is off. Rev. 3.00 Sep 14, 2005 page 282 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.7 Port 6 8.7.1 Overview Port 6 is an 8-bit input/output port that is also used for input and output of bus control signals (LWR, HWR, RD, AS, BACK, BREQ, WAIT) and for clock () output. In modes 1 to 5 (expanded modes), the pin functions are P67 (generic input)/, LWR, HWR, RD, AS, P62/BACK, P61/BREQ, and P60/WAIT). See table 8.11 for the selection of the pin functions. In modes 6 and 7 (single-chip modes), P67 functions as a generic input port or o output, and P66 to P60 function as generic input/output ports. When DRAM is connected to areas 2 to 5, LWR, HWR, and RD also function as LCAS, UCAS, and WE, respectively. For details see section 6.5, DRAM Interface. Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Port 6 pins P6 7 / Port 6 Mode 6 and 7 (single-chip mode) Modes 1 to 5 (expanded modes) P67 (input)/ (output) P6 7 (input) / (output) P6 6 / LWR LWR (output) P6 6 (input/output) P6 5 / HWR HWR (output) P6 5 (input/output) P6 4 / RD RD (output) P6 4 (input/output) P6 3 / AS AS (output) P6 3 (input/output) P6 2 / BACK P62 (input/output)/ BACK (output) P6 2 (input/output) P6 1 / BREQ P61 (input/output)/ BREQ (input) P6 1 (input/output) P6 0 / WAIT P60 (input/output)/ WAIT (input) P6 0 (input/output) Figure 8.6 Port 6 Pin Configuration Rev. 3.00 Sep 14, 2005 page 283 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.7.2 Register Descriptions Table 8.10 summarizes the registers of port 6. Table 8.10 Port 6 Registers Address* Name Abbreviation R/W Initial Value H'EE005 Port 6 data direction register P6DDR W H'80 H'FFFD5 Port 6 data register P6DR R/W H'80 Note: * Lower 20 bits of the address in advanced mode. Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6. Bit 7 is reserved. It is fixed at 1, and cannot be modified. Bit 7 -- 6 5 4 3 2 1 0 P6 6 DDR P6 5 DDR P6 4 DDR P6 3 DDR P6 2 DDR P6 1 DDR P6 0 DDR Initial value 1 0 0 0 0 0 0 0 Read/Write -- W W W W W W W Reserved bit Port 6 data direction 6 to 0 These bits select input or output for port 6 pins Modes 1 to 5 (Expanded Modes): P67 functions as the clock output pin () or an input port. P67 is the clock output pin (o) if the PSTOP bit in MSTRCH is cleared to 0 (initial value), and an input port if this bit is set to 1. P66 to P63 function as bus control output pins (LWR, HWR, RD, and AS), regardless of the settings of bits P66DDR to P63DDR. P62 to P60 function as bus control input/output pins (BACK, BREQ, and WAIT) or input/output ports. For the method of selecting the pin functions, see table 8.11. When P62 to P60 function as input/output ports, the pin becomes an output port if the corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0. Mode 6 and 7 (Single-Chip Mode): P67 functions as the clock output pin () or an input port. P66 to P60 function as generic input/output ports. P67 is the clock output pin () if the PSTOP bit in MSTCRH is cleared to 0 (initial value), and an input port if this bit is set to 1. A pin in port 6 Rev. 3.00 Sep 14, 2005 page 284 of 910 REJ09B0258-0300 Section 8 I/O Ports becomes an output port if the corresponding bit of P66DDR to P60DDR is set to 1, and an input port if this pin is cleared to 0. P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 6 is functioning as an input/output port and a P6DDR bit is set to 1, the corresponding pin maintains its output state. Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data for port 6. When port 6 functions as an output port, the value of this register is output. For bit 7, a value of 1 is returned if the bit is read while the PSTOP bit in MSTCRH is cleared to 0, and the P67 pin logic level is returned if the bit is read while the PSTOP bit is set to 1. Bit 7 cannot be modified. For bits 6 to 0, the pin logic level is returned if the bit is read while the corresponding bit in P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the corresponding bit in P6DDR is set to 1. Bit 7 6 5 4 3 2 1 0 P67 P6 6 P6 5 P6 4 P6 3 P6 2 P6 1 P6 0 Initial value 1 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Port 6 data 7 to 0 These bits store data for port 6 pins P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 3.00 Sep 14, 2005 page 285 of 910 REJ09B0258-0300 Section 8 I/O Ports Table 8.11 Port 6 Pin Functions in Modes 1 to 5 Pin Pin Functions and Selection Method P67/ Bit PSTOP in MSTCRH selects the pin function. PSTOP Pin function LWR 0 1 output P67 input Functions as LWR regardless of the setting of bit P66DDR P66DDR 0 1 LWR output* Pin function Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1 and bit CSEL in DRCRB is 1, LWR output functions as LCAS. HWR Functions as HWR regardless of the setting of bit P65DDR P65DDR 0 1 HWR output* Pin function Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1 and bit CSEL in DRCRB is 1, HWR output functions as UCAS. RD Functions as RD regardless of the setting of bit P64DDR P64DDR 0 1 RD output* Pin function Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1, RD output functions as WE. AS Functions as AS regardless of the setting of bit P63DDR P63DDR 0 1 AS output Pin function P62/BACK Bit BRLE in BRCR and bit P62DDR select the pin function as follows BRLE P62DDR Pin function P61/BREQ 0 1 -- P62 input P62 output BACK output Bit BRLE in BRCR and bit P61DDR select the pin function as follows BRLE P61DDR Pin function P60/WAIT 1 0 0 1 0 1 -- P61 input P61 output BREQ input Bit WAITE in BCR and bit P60DDR select the pin function as follows. WAITE P60DDR Pin function 0 1 0* P60 input P60 output WAIT input Note: * Do not set bit P60DDR to 1. Rev. 3.00 Sep 14, 2005 page 286 of 910 REJ09B0258-0300 1 0 Section 8 I/O Ports 8.8 Port 7 8.8.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog output from the D/A converter. The pin functions are the same in all operating modes. Figure 8.7 shows the pin configuration of port 7. See section 15, A/D Converter, for details of the A/D converter analog input pins, and section 16, D/A Converter, for details of the D/A converter analog output pins. Port 7 pins P77 (input)/AN 7 (input)/DA 1 (output) P76 (input)/AN 6 (input)/DA 0 (output) P75 (input)/AN 5 (input) Port 7 P74 (input)/AN 4 (input) P73 (input)/AN 3 (input) P72 (input)/AN 2 (input) P71 (input)/AN 1 (input) P70 (input)/AN 0 (input) Figure 8.7 Port 7 Pin Configuration Rev. 3.00 Sep 14, 2005 page 287 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.8.2 Register Description Table 8.12 summarizes the port 7 register. Port 7 is an input port, and port 7 has no data direction register. Table 8.12 Port 7 Data Register Address* Name Abbreviation R/W Initial Value H'FFFD6 Port 7 data register P7DR R Undetermined Note: * Lower 20 bits of the address in advanced mode. Port 7 Data Register (P7DR) Bit 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 Initial value --* --* --* --* --* --* --* --* Read/Write R R R R R R R R Note: * Determined by pins P77 to P70. When port 7 is read, the pin logic levels are always read. P7DR cannot be modified. Rev. 3.00 Sep 14, 2005 page 288 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.9 Port 8 8.9.1 Overview Port 8 is a 5-bit input/output port that is also used for CS3 to CS0 output, RFSH output, IRQ3 to IRQ0 input, and A/D converter ADTRG input. Figure 8.8 shows the pin configuration of port 8. In modes 1 to 5 (expanded modes), port 8 can provide CS3 to CS0 output, RFSH output, IRQ3 to IRQ0 input, and ADTRG input. See table 8.14 for the selection of pin functions in expanded modes. In modes 6 and 7 (single-chip modes), port 8 can provide IRQ3 to IRQ0 input and ADTRG input. See table 8.15 for the selection of pin functions in single-chip mode. See section 15, A/D Converter, for a description of the A/D converter's ADTRG input pin. The IRQ3 to IRQ0 functions are selected by IER settings, regardless of whether the pin is used for input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts. When DRAM is connected to areas 2 to 5, the CS3 and CS2 output pins function as RAS output pins for each area. For details see section 6.5, DRAM Interface. Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Pins P82 to P80 have Schmitt-trigger inputs. Rev. 3.00 Sep 14, 2005 page 289 of 910 REJ09B0258-0300 Section 8 I/O Ports Port 8 Port 8 pins Pin functions in modes 1 to 5 (expanded modes) P84 / CS 0 P84 (input)/ CS 0 (output) P83 / CS 1 / IRQ 3 / ADTRG P83 (input)/ CS 1 (output)/ IRQ 3 (input) / ADTRG (input) P82 / CS 2 / IRQ 2 P82 (input)/ CS 2 (output)/ IRQ 2 (input) P81 / CS 3 / IRQ 1 P81 (input/output)/ CS3 (output)/IRQ1(input) P80 / RFSH /IRQ 0 P80 (input/output)/ RFSH (output)/ IRQ 0 (input) Pin functions in mode 6 and 7 (single-chip mode) P84 /(input/output) P83 /(input/output)/ IRQ 3 (input) / ADTRG (input) P82 /(input/output)/ IRQ 2 (input) P81 /(input/output)/ IRQ 1 (input) P80 /(input/output)/ IRQ 0 (input) Figure 8.8 Port 8 Pin Configuration Rev. 3.00 Sep 14, 2005 page 290 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.9.2 Register Descriptions Table 8.13 summarizes the registers of port 8. Table 8.13 Port 8 Registers Initial Value Address* Name Abbreviation R/W Mode 1 to 4 Mode 5 to 7 H'EE007 Port 8 data direction register P8DDR W H'F0 H'E0 H'FFFD7 Port 8 data register P8DR R/W H'E0 H'E0 Note: * Lower 20 bits of the address in advanced mode. Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8. Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified. Bit 7 6 5 4 3 2 1 0 Modes Initial value 1 to 4 Read/Write 1 1 1 1 0 0 0 0 W W W W W Modes Initial value 5 to 7 Read/Write 1 1 1 0 0 0 0 0 W W W W W Reserved bits P8 4 DDR P8 3 DDR P8 2 DDR P8 1 DDR P8 0 DDR Port 8 data direction 4 to 0 These bits select input or output for port 8 pins Modes 1 to 5 (Expanded Modes): When bits in P8DDR bit are set to 1, P84 to P81 become CS0 to CS3 output pins. When bits in P8DDR are cleared to 0, the corresponding pins become input ports. However, P81 can also be used as an output port, depending on the setting of bits DRAS2 to DRAS0 in DRAM control register A (DRCRA). For details see section 6.5.2, DRAM Space and RAS Output Pin Settings. In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset P84 functions as the CS0 output, while CS1 to CS3 are input ports. In mode 5 (expanded mode with on-chip ROM enabled), following a reset CS0 to CS3 are all input ports. Rev. 3.00 Sep 14, 2005 page 291 of 910 REJ09B0258-0300 Section 8 I/O Ports When the refresh enable bit (RFSHE) in DRCRA is set to 1, P80 is used for RFSH output. When RFSHE is cleared to 0, P80 becomes an input/output port according to the P8DDR setting. For details see table 8.14. Mode 6 and 7 (Single-Chip Mode): Port 8 is a generic input/output port. A pin in port 8 becomes an output port if the corresponding P8DDR bit is set to 1, and an input port if this bit is cleared to 0. P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P8DDR is initialized to H'F0 in modes 1 to 4, and to H'E0 in modes 5 to 7, by a reset and in hardware standby mode. In software standby mode P8DDR retains its previous setting. Therefore, if a transition is made to software standby mode while port 8 is functioning as an input/output port and a P8DDR bit is set to 1, the corresponding pin maintains its output state. Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data for port 8. When port 8 functions as an output port, the value of this register is output. When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is returned. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin logic level is read. Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified. Bit 7 6 5 4 3 2 1 0 P8 4 P8 3 P8 2 P8 1 P8 0 Initial value 1 1 1 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W Reserved bits Port 8 data 4 to 0 These bits store data for port 8 pins P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 3.00 Sep 14, 2005 page 292 of 910 REJ09B0258-0300 Section 8 I/O Ports Table 8.14 Port 8 Pin Functions in Modes 1 to 5 Pin Pin Functions and Selection Method P84/CS0 Bit P84DDR selects the pin function as follows P84DDR Pin function P83/CS1/IRQ3/ADTRG 0 1 P84 input CS0 output Bit P83DDR selects the pin function as follows P83DDR Pin function 0 1 P83 input CS1 output IRQ3 input ADTRG input P82/CS2/IRQ2 The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, and bit P82DDR, select the pin function as follows. DRAM interface settings (1) in table below P82DDR Pin function 0 |(2) in table below 1 -- CS2 output IRQ3 input P82 input CS2 output* Note: * CS2 is output as RAS2. DRAM interface setting (1) (2) DRAS2 0 DRAS1 DRAS0 P81/CS3/IRQ1 1 0 0 1 1 0 0 1 0 1 1 0 1 The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, and bit P81DDR, select the pin function as follows. DRAM interface settings (1) in table below P81DDR Pin function 0 1 P81 input pin CS3 (2) in table below 0 output pin (3) in table below 1 -- CS3 output pin* P81 input P81 output pin pin IRQ1 input pin Note: * CS3 is output as RAS3. DRAM interface setting (1) (3) DRAS2 DRAS1 DRAS0 P80/RFSH/IRQ0 (2) (3) (2) 0 1 0 0 1 1 0 0 1 0 1 1 0 1 Bit RFSHE in DRCRA and bit P80DDR select the pin function as follows. RFSHE P80DDR Pin function 0 1* 0 1 -- P80 input P80 output RFSH output IRQ0 input Note: * If areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1. Rev. 3.00 Sep 14, 2005 page 293 of 910 REJ09B0258-0300 Section 8 I/O Ports Table 8.15 Port 8 Pin Functions in Mode 6 and 7 Pin Pin Functions and Selection Method P84 Bit P84DDR selects the pin function as follows P84DDR Pin function P83/IRQ3/ADTRG 0 1 P84 input P84 output Bit P83DDR selects the pin function as follows P83DDR Pin function 0 1 P83 input P83 output IRQ3 input ADTRG input P82/IRQ2 Bit P82DDR selects the pin function as follows P82DDR Pin function 0 1 P82 input P82 output IRQ2 input P81/IRQ1 Bit P81DDR selects the pin function as follows P81DDR Pin function 0 1 P81 input P81 output IRQ1 input P80/IRQ0 Bit P80DDR select the pin function as follows P80DDR Pin function 0 1 P80 input P80 output IRQ0 input Rev. 3.00 Sep 14, 2005 page 294 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.10 Port 9 8.10.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD0, TxD1, RxD0, RxD1, SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ5 and IRQ4 input. See table 8.17 for the selection of pin functions. The IRQ5 and IRQ4 functions are selected by IER settings, regardless of whether the pin is used for input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts. Port 9 has the same set of pin functions in all operating modes. Figure 8.9 shows the pin configuration of port 9. Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor pair. Port 9 pins P95 (input/output)/SCK 1 (input/output)/IRQ 5 (input) P94 (input/output)/SCK 0 (input/output)/IRQ 4 (input) Port 9 P93 (input/output)/RxD1 (input) P92 (input/output)/RxD0 (input) P91 (input/output)/TxD1 (output) P90 (input/output)/TxD0 (output) Figure 8.9 Port 9 Pin Configuration Rev. 3.00 Sep 14, 2005 page 295 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.10.2 Register Descriptions Table 8.16 summarizes the registers of port 9. Table 8.16 Port 9 Registers Address* Name Abbreviation R/W Initial Value H'EE008 Port 9 data direction register P9DDR W H'C0 H'FFFD8 Port 9 data register P9DR R/W H'C0 Note: * Lower 20 bits of the address in advanced mode. Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9. Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified. Bit 7 6 5 4 3 2 1 0 P9 5 DDR P9 4 DDR P9 3 DDR P9 2 DDR P9 1 DDR P9 0 DDR Initial value 1 1 0 0 0 0 0 0 Read/Write W W W W W W Reserved bits Port 9 data direction 5 to 0 These bits select input or output for port 9 pins When port 9 functions as an input/output port, a pin in port 9 becomes an output port if the corresponding P9DDR bit is set to 1, and an input port if this bit is cleared to 0. For the method of selecting the pin functions, see table 8.17. P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port 9 is functioning as an input/output port and a P9DDR bit is set to 1, the corresponding pin maintains its output state. Rev. 3.00 Sep 14, 2005 page 296 of 910 REJ09B0258-0300 Section 8 I/O Ports Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data for port 9. When port 9 functions as an output port, the value of this register is output. When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin logic level is read. Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified. Bit 7 6 5 4 3 2 1 0 P95 P94 P9 3 P9 2 P9 1 P9 0 Initial value 1 1 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W Reserved bits Port 9 data 5 to 0 These bits store data for port 9 pins P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 3.00 Sep 14, 2005 page 297 of 910 REJ09B0258-0300 Section 8 I/O Ports Table 8.17 Port 9 Pin Functions Pin Pin Functions and Selection Method P95/SCK1/IRQ5 Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P95DDR select the pin function as follows CKE1 0 C/A 0 CKE0 P95DDR Pin function 1 0 1 -- 1 -- -- 0 1 -- -- -- P95 input P95 output SCK1 output SCK1 output SCK1 input IRQ5 input P94/SCK0/IRQ4 Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR, and bit P94DDR select the pin function as follows CKE1 0 C/A CKE0 P94DDR Pin function 1 0 0 1 1 -- -- -- 0 1 -- -- -- P94 input P94 output SCK0 output SCK0 output SCK0 input IRQ4 input P93/RxD1 Bit RE in SCR of SCI1, bit SMIF in SCMR, and bit P93DDR select the pin function as follows. SMIF 0 RE P93DDR Pin function P92/RxD0 0 0 P93 input 1 1 P93 output -- -- -- RxD1 input RxD1 input Bit RE in SCR of SCI0, bit SMIF in SCMR, and bit P92DDR select the pin function as follows SMIF 0 RE P92DDR Pin function Rev. 3.00 Sep 14, 2005 page 298 of 910 REJ09B0258-0300 0 1 1 -- 0 1 -- -- P92 input P92 output RxD0 input RxD0 input Section 8 I/O Ports Pin Pin Functions and Selection Method P91/TxD1 Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P91DDR select the pin function as follows. SMIF 0 TE P91 DDR Pin function 0 1 1 -- 0 1 -- -- P91 input P91 output TxD1 output TxD1 output* Note: * Functions as the TxD1 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance. P90/TxD0 Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P90DDR select the pin function as follows. SMIF 0 TE P90DDR Pin function 0 1 1 -- 0 1 -- -- P90 input P90 output TxD0 output TxD0 output* Note: * Functions as the TxD0 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at highimpedance. Rev. 3.00 Sep 14, 2005 page 299 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.11 Port A 8.11.1 Overview Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the programmable timing pattern controller (TPC), input and output, (TIOCB2, TIOCA2, TIOCB1, TIOCA1, TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit timer, input (TCLKD, TCLKC, TCLKB, TCLKA) to the 8-bit timer, output (TEND1, TEND0) from the DMA controller (DMAC), and address output (A23 to A20). A reset or hardware standby transition leaves port A as an input port, except that in modes 3 and 4, one pin is always used for A20 output. See table 8.19 to 8.21 for the selection of pin functions. Usage of pins for TPC, 16-bit timer, 8-bit timer, and DMAC input and output is described in the sections on those modules. For output of address bits A23 to A20 in modes 3, 4, and 5, see section 6.2.4, Bus Release Control Register (BRCR). Pins not assigned to any of these functions are available for generic input/output. Figure 8.10 shows the pin configuration of port A. Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor pair. Port A has Schmitt-trigger inputs. Rev. 3.00 Sep 14, 2005 page 300 of 910 REJ09B0258-0300 Section 8 I/O Ports Port A pins PA7 /TP7 /TIOCB2 /A 20 PA6 /TP6 /TIOCA2 /A21 PA5 /TP5 /TIOCB1 /A 22 PA4 /TP4 /TIOCA1 /A23 Port A PA3 /TP3 /TIOCB0 /TCLKD PA2 /TP2 /TIOCA0 /TCLKC PA1 /TP1 /TEND1 /TCLKB PA0 /TP0 /TEND0 /TCLKA Pin functions in modes 1, 2, 6, and 7 PA 7 (input/output)/TP7 (output)/TIOCB 2 (input/output) PA 6 (input/output)/TP6 (output)/TIOCA 2 (input/output) PA 5 (input/output)/TP5 (output)/TIOCB 1 (input/output) PA 4 (input/output)/TP4 (output)/TIOCA 1 (input/output) PA 3 (input/output)/TP3 (output)/TIOCB 0 (input/output)/TCLKD (input) PA 2 (input/output)/TP2 (output)/TIOCA 0 (input/output)/TCLKC (input) PA 1 (input/output)/TP1 (output)/TEND 1 (output)/TCLKB (input) PA 0 (input/output)/TP0 (output)/TEND 0 (output)/TCLKA (input) Pin functions in modes 3, 4 A 20 (output) PA 6 (input/output)/TP6 (output)/TIOCA 2 (input/output)/A 21 (output) PA 5 (input/output)/TP5 (output)/TIOCB 1 (input/output)/A 22 (output) PA 4 (input/output)/TP4 (output)/TIOCA 1 (input/output)/A 23 (output) PA 3 (input/output)/TP3 (output)/TIOCB 0 (input/output)/TCLKD (input) PA 2 (input/output)/TP2 (output)/TIOCA 0 (input/output)/TCLKC (input) PA 1 (input/output)/TP1 (output)/TEND 1 (output)/TCLKB (input) PA 0 (input/output)/TP0 (output)/TEND 0 (output)/TCLKA (input) Pin functions in mode 5 PA7 (input/output)/TP7 (output)/TIOCB2 (input/output)/A 20 (output) PA6 (input/output)/TP6 (output)/TIOCA2 (input/output)/A 21 (output) PA5 (input/output)/TP5 (output)/TIOCB1 (input/output)/A 22 (output) PA4 (input/output)/TP4 (output)/TIOCA1 (input/output)/A 23 (output) PA3 (input/output)/TP3 (output)/TIOCB0 (input/output)/TCLKD (input) PA2 (input/output)/TP2 (output)/TIOCA0 (input/output)/TCLKC (input) PA1 (input/output)/TP1 (output)/TEND1 (output)/TCLKB (input) PA0 (input/output)/TP0 (output)/TEND0 (output)/TCLKA (input) Figure 8.10 Port A Pin Configuration Rev. 3.00 Sep 14, 2005 page 301 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.11.2 Register Descriptions Table 8.18 summarizes the registers of port A. Table 8.18 Port A Registers Initial Value Address* Name H'EE009 Port A data direction register H'FFFD9 Port A data register R/W Modes 1, 2, 5, 6, and 7 Modes 3, 4 PADDR W H'00 H'80 PADR R/W H'00 H'00 Note: * Lower 20 bits of the address in advanced mode. Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select input or output for each pin in port A. When pins are used for TPC output, the corresponding PADDR bits must also be set. Bit 7 6 5 4 3 2 1 0 PA7 DDR PA6 DDR PA5 DDR PA4 DDR PA3 DDR PA2 DDR PA1 DDR PA0 DDR Modes Initial value 1 3, 4 Read/Write -- Modes Initial value 0 1, 2, 5, 6 and 7 Read/Write W 0 0 0 0 0 0 0 W W W W W W W 0 0 0 0 0 0 0 W W W W W W W Port A data direction 7 to 0 These bits select input or output for port A pins The pin functions that can be selected for pins PA7 to PA4 differ between modes 1, 2, 6, and 7, and modes 3 to 5. For the method of selecting the pin functions, see tables 8.19 and 8.20. The pin functions that can be selected for pins PA3 to PA0 are the same in modes 1 to 7. For the method of selecting the pin functions, see table 8.21. When port A functions as an input/output port, a pin in port A becomes an output port if the corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4, PA7DDR is fixed at 1 and PA7 functions as the A20 address output pin. PADDR is a write-only register. Its value cannot be read. All bits return 1 when read. Rev. 3.00 Sep 14, 2005 page 302 of 910 REJ09B0258-0300 Section 8 I/O Ports PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, 6, and 7. It is initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port A is functioning as an input/output port and a PADDR bit is set to 1, the corresponding pin maintains its output state. Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output data for port A. When port A functions as an output port, the value of this register is output. When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read. Bit 7 6 5 4 3 2 1 0 PA 7 PA 6 PA 5 PA 4 PA 3 PA 2 PA 1 PA 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port A data 7 to 0 These bits store data for port A pins PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 3.00 Sep 14, 2005 page 303 of 910 REJ09B0258-0300 Section 8 I/O Ports Table 8.19 Port A Pin Functions (Modes 1, 2, 6, 7) Pin Pin Functions and Selection Method PA7/TP7/ TIOCB2 Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit PA7DDR select the pin function as follows. 16-bit timer channel 2 settings (1) in table below PA7DDR (2) in table below -- NDER7 Pin function 0 1 -- -- 0 1 TIOCB2 output PA7 input PA7 output TP7 output TIOCB2 input* Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0. 16-bit timer channel 2 settings 1 (2) IOB2 (1) (2) 0 1 IOB1 0 0 1 -- IOB0 0 1 -- -- Rev. 3.00 Sep 14, 2005 page 304 of 910 REJ09B0258-0300 Section 8 I/O Ports Pin Pin Functions and Selection Method PA6/TP6/ TIOCA2 Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, and bit PA6DDR select the pin function as follows. 16-bit timer channel 2 settings (1) in table below (2) in table below PA6DDR -- 0 1 1 NDER6 -- -- 0 1 TIOCA2 output PA6 input PA6 output TP6 output Pin function TIOCA2 input* Note: * TIOCA2 input when IOA2 = 1. 16-bit timer channel 2 settings (2) (1) PWM2 (1) 0 IOA2 PA5/TP5/ TIOCB1 (2) 1 1 -- IOA1 0 0 0 1 -- -- IOA0 0 1 -- -- -- Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, and bit PA5DDR select the pin function as follows. 16-bit timer channel 1 settings (1) in table below PA5DDR -- NDER5 Pin function (2) in table below 0 1 1 -- -- 0 1 TIOCB1 output PA5 input PA5 output TP5 output TIOCB1 input* Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0. 16-bit timer channel 1 settings (2) IOB2 (1) (2) 0 1 IOB1 0 0 1 -- IOB0 0 1 -- -- Rev. 3.00 Sep 14, 2005 page 305 of 910 REJ09B0258-0300 Section 8 I/O Ports Pin Pin Functions and Selection Method PA4/TP4/ TIOCA1 Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, and bit PA4DDR select the pin function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below PA4DDR -- 0 1 1 NDER4 -- -- 0 1 TIOCA1 output PA4 input PA4 output TP4 output Pin function TIOCA1 input* Note: * TIOCA1 input when IOA2 = 1. 16-bit timer channel 1 settings (2) (1) PWM1 (2) 0 IOA2 (1) 1 1 -- IOA1 0 0 0 1 -- -- IOA0 0 1 -- -- -- Rev. 3.00 Sep 14, 2005 page 306 of 910 REJ09B0258-0300 Section 8 I/O Ports Table 8.20 Port A Pin Functions (Modes 3, 4, 5) Pin Pin Functions and Selection Method PA7/TP7/ Modes 3 and 4: Always used as A20 output. TIOCB2/ A20 Pin function A20 output Mode 5: Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, bit A20E in BRCR, and bit PA 7DDR select the pin function as follows. A20E 16-bit timer channel 2 settings 1 (1) in table below 0 (2) in table below -- PA7DDR -- 0 1 1 -- NDER7 -- -- 0 1 -- TIOCB2 output PA7 input PA7 output TP7 output A20 output Pin function TIOCB2 input* Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0. 16-bit timer channel 2 settings (2) (1) IOB2 PA6/TP6/ TIOCA2/A21 (2) 0 1 IOB1 0 0 1 -- IOB0 0 1 -- -- Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in BRCR, and bit PA 6DDR select the pin function as follows. A21E 16-bit timer channel 2 settings 1 (1) in table below 0 (2) in table below -- PA6DDR -- 0 1 1 -- NDER6 -- -- 0 1 -- TIOCA2 output PA6 input PA6 output TP6 output A21 output Pin function TIOCA2 input* Note: * TIOCA2 input when IOA2 = 1. 16-bit timer channel 2 settings (2) (1) PWM2 (2) 0 IOA2 (1) 1 1 -- IOA1 0 0 0 1 -- -- IOA0 0 1 -- -- -- Rev. 3.00 Sep 14, 2005 page 307 of 910 REJ09B0258-0300 Section 8 I/O Ports Pin Pin Functions and Selection Method PA5/TP5/ TIOCB1/A22 Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, bit A22E in BRCR, and bit PA5DDR select the pin function as follows. A22E 16-bit timer channel 1 settings 1 (1) in table below 0 (2) in table below -- PA5DDR -- 0 1 1 -- NDER5 -- -- 0 1 -- TIOCB1 output PA5 input PA5 output TP5 output A22 output Pin function TIOCB1 input* Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0. 16-bit timer channel 1 settings (2) (1) IOB2 PA4/TP4/ TIOCA1/A23 (2) 0 1 IOB1 0 0 1 -- IOB0 0 1 -- -- Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, bit A23E in BRCR, and bit PA4DDR select the pin function as follows. A23E 16-bit timer channel 1 settings 1 (1) in table below 0 (2) in table below -- PA4DDR -- 0 1 1 -- NDER4 -- -- 0 1 -- TIOCA1 output PA4 input PA4 output TP4 output A23 output Pin function TIOCA1 input* Note: * TIOCA1 input when IOA2 = 1. 16-bit timer channel 1 settings (2) (1) PWM1 (2) (1) 1 -- 0 IOA2 1 0 IOA1 0 0 1 -- -- IOA0 0 1 -- -- -- Rev. 3.00 Sep 14, 2005 page 308 of 910 REJ09B0258-0300 Section 8 I/O Ports Table 8.21 Port A Pin Functions (Modes 1 to 7) Pin Pin Functions and Selection Method PA3/TP3/ TIOCB0/ TCLKD Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR2 of the 8-bit timer, bit NDER3 in NDERA, and bit PA3DDR select the pin function as follows. 16-bit timer channel 0 settings (1) in table below (2) in table below PA3DDR -- 0 1 1 NDER3 -- -- 0 1 TIOCB0 output PA3 input PA3 output TP3 output Pin function TIOCB0 input*1 TCLKD input*2 Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0. 2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR2 are as shown in (3) in the table below. 16-bit timer channel 0 settings (2) (1) IOB2 (2) 0 1 IOB1 0 0 1 -- IOB0 0 1 -- -- 8-bit timer channel 2 settings (4) CKS2 0 CKS1 -- CKS0 -- (3) 1 0 0 1 1 -- Rev. 3.00 Sep 14, 2005 page 309 of 910 REJ09B0258-0300 Section 8 I/O Ports Pin Pin Functions and Selection Method PA2/TP2/ TIOCA0/ TCLKC Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit timer, bit NDER2 in NDERA, and bit PA2DDR select the pin function as follows. 16-bit timer channel 0 settings (1) in table below PA2DDR (2) in table below -- NDER2 Pin function 0 1 1 -- -- 0 1 TIOCA0 output PA2 input PA2 output TP2 output TIOCA0 input*1 TCLKC input*2 Notes: 1. TIOCA0 input when IOA2 = 1. 2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in (3) in the table below. 16-bit timer channel 0 settings (2) (1) PWM0 (2) (1) 1 -- 0 IOA2 1 0 IOA1 0 0 1 -- -- IOA0 0 1 -- -- -- 8-bit timer channel 0 settings (4) CKS2 0 CKS1 -- CKS0 -- Rev. 3.00 Sep 14, 2005 page 310 of 910 REJ09B0258-0300 (3) 1 0 0 1 1 -- Section 8 I/O Ports Pin Pin Functions and Selection Method PA1/TP1/ TCLKB/ Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit PA1DDR select the pin function as follows. TEND1 PA1DDR 0 1 NDER1 -- 0 1 PA1 input PA1 output TP1 output Pin function 1 TCLKB output*1 TEND1 output*2 Notes: 1. TCLKB input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR3 are as shown in (1) in the table below. 2. When an external request is specified as a DMAC activation source, TEND1 output regardless of bits PA1DDR and NDER1. 8-bit timer channel 3 settings PA0/TP0/ TCLKA/ (2) CKS2 0 CKS1 -- CKS0 -- (1) 1 0 0 1 1 -- Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR1 of the 8-bit timer, bit NDER0 in NDERA, and bit PA0DDR select the pin function as follows. TEND0 PA0DDR 0 NDER0 -- Pin function 1 PA0 input 0 1 PA0 output TP0 output TCLKA output*1 TEND0 output*2 Notes: 1. TCLKA input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0 and TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in (1) in the table below. 2. When an external request is specified as a DMAC activation source, TEND0 output regardless of bits PA0DDR and NDER0. 8-bit timer channel 1 settings (2) CKS2 0 CKS1 -- CKS0 -- (1) 1 0 0 1 1 -- Rev. 3.00 Sep 14, 2005 page 311 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.12 Port B 8.12.1 Overview Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the programmable timing pattern controller (TPC), input/output (TMIO3, TMO2, TMIO1, TMO0) by the 8-bit timer, CS7 to CS4 output, input (DREQ1, DREQ0) to the DMA controller (DMAC), input and output (TxD2, RxD2, SCK2) by serial communication interface channel 2 (SCI2), and output (UCAS, LCAS) by the DRAM interface. See table 8.23 to 8.24 for the selection of pin functions. A reset or hardware standby transition leaves port B as an input port. For output of CS7 to CS4 in modes 1 to 5, see section 6.3.4, Chip Select Signals. When DRAM is connected to areas 2, 3, 4, and 5, the CS4 and CS5 output pins become RAS output pins for these areas. For details see section 6.5, DRAM Interface. Pins not assigned to any of these functions are available for generic input/output. Figure 8.11 shows the pin configuration of port B. When DRAM is connected to areas 2, 3, 4, and 5, the CS4 and CS5 output pins become RAS output pins for these areas. For details see 6.5, DRAM Interface. Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive darlington transistor pair. Rev. 3.00 Sep 14, 2005 page 312 of 910 REJ09B0258-0300 Section 8 I/O Ports Port B pins PB7/TP15 /RxD2 PB6/TP14 /TxD2 PB5/TP13 /SCK2/LCAS PB4/TP12 /UCAS Port B PB3/TP11 /TMIO3/DREQ1/CS4 PB2/TP10 /TMO2/CS5 PB1/TP9 /TMIO1/DREQ0/CS6 PB0/TP8 /TMO0/CS7 Pin functions in modes 1 to 5 PB7 (input/output)/TP15 (output) /RxD2 (input) PB6 (input/output)/TP14 (output) /TxD2 (output) PB5 (input/output)/TP13 (output) /SCK2 (input/output) /LCAS (output) PB4 (input/output)/TP12 (output) /UCAS (output) PB3 (input/output)/TP11 (output) /TMIO3 (input/output) /DREQ1 (input) CS4 (output) PB2 (input/output)/TP10 (output) /TMO2 (output) /CS5 (output) PB1 (input/output)/TP9 (output) /TMIO1 (input/output) /DREQ0 (input) /CS6 (output) PB0 (input/output)/TP8 (output) /TMO0 (output) /CS7 (output) Pin functions in mode 6 and 7 PB7 (input/output)/TP15 (output) /RxD2 (input) PB6 (input/output)/TP14 (output) /TxD2 (output) PB5 (input/output)/TP13 (output) /SCK2 (input/output) PB4 (input/output)/TP12 (output) PB3 (input/output)/TP11 (output) /TMIO3 (input/output) /DREQ1 (input) PB2 (input/output)/TP10 (output) /TMO2 (output) PB1 (input/output)/TP9 (output) /TMIO1 (input/output) /DREQ0 (input) PB0 (input/output)/TP8 (output) /TMO0 (output) Figure 8.11 Port B Pin Configuration Rev. 3.00 Sep 14, 2005 page 313 of 910 REJ09B0258-0300 Section 8 I/O Ports 8.12.2 Register Descriptions Table 8.22 summarizes the registers of port B. Table 8.22 Port B Registers Address* Name Abbreviation R/W Initial Value H'EE00A Port B data direction register PBDDR W H'00 H'FFFDA Port B data register PBDR R/W H'00 Note: * Lower 20 bits of the address in advanced mode. Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. When pins are used for TPC output, the corresponding PBDDR bits must also be set. Bit 7 6 5 4 3 2 1 0 PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port B data direction 7 to 0 These bits select input or output for port B pins The pin functions that can be selected for port B differ between modes 1 to 5, and modes 6 and 7. For the method of selecting the pin functions, see tables 8.23 and 8.24. When port B functions as an input/output port, a pin in port B becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if this bit is cleared to 0. PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read. PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port B is functioning as an input/output port and a PBDDR bit is set to 1, the corresponding pin maintains its output state. Rev. 3.00 Sep 14, 2005 page 314 of 910 REJ09B0258-0300 Section 8 I/O Ports Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data for pins port B. When port B functions as an output port, the value of this register is output. When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin logic level is read. Bit 7 6 5 4 3 2 1 0 PB 7 PB 6 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port B data 7 to 0 These bits store data for port B pins PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev. 3.00 Sep 14, 2005 page 315 of 910 REJ09B0258-0300 Section 8 I/O Ports Table 8.23 Port B Pin Functions (Modes 1 to 5) Pin Pin Functions and Selection Method PB7/TP15/ RxD2 Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB7DDR select the pin function as follows. SMIF 0 RE 0 1 -- PB7DDR 0 1 1 -- -- NDER15 -- 0 1 -- -- PB7 input PB7 output TP15 output RxD2 input RxD2 input Pin function PB6/TP14/ TxD2 1 Bit TE in SCR of SCI2, bit SMIF in SCMR, bit NDER14 in NDERB, and bit PB6DDR select the pin function as follows. SMIF 0 TE 1 0 PB6DDR NDER14 Pin function 0 1 1 1 -- -- -- -- 0 1 -- -- PB6 input PB6 output TP14 output TxD2 output TxD2 output* Note: * Functions as the TxD2 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance. PB5/TP13/ Bit C/A in SMR of SCI2, bits CKE0 and CKE1 in SCR, bit NDER13 in NDERB, and bit PB5DDR select the pin SCK2/LCAS function as follows. CKE1 0 C/A 0 CKE0 PB5DDR NDER13 Pin function 1 0 0 1 1 -- 0 1 PB5 input PB5 output TP13 output 1 -- 1 -- -- -- -- -- -- -- -- SCK2 output SCK2 output SCK2 input LCAS output* Note: * LCAS output depending on bits DRAS2 to DRAS0 in DRCRA and bit CSEL in DRCRB, and regardless of bits C/A, CKE0, and CKE1, NDER13, and PB5DDR. For details, see section 6, Bus Controller. PB4/TP12/ UCAS Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows. PB4DDR 0 1 1 NDER12 -- 0 1 PB4 output TP12 output Pin function PB4 input UCAS output* Note: * UCAS output depending on bits DRAS2 to DRAS0 in DRCRA and bit CSEL in DRCRB, and regardless of bits NDER12 and PB4DDR. For details, see section 6, Bus Controller. Rev. 3.00 Sep 14, 2005 page 316 of 910 REJ09B0258-0300 Section 8 I/O Ports Pin Pin Functions and Selection Method The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR3, bits PB3/TP11/ TMIO3/ CCLR1 and CCLR0 in 8TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB3DDR select the pin DREQ1/CS4 function as follows. DRAM interface settings (1) in table below OIS3/2 and OS1/0 (2) in table below All 0 CS4E 0 Not all 0 -- -- 1 -- PB3DDR 0 1 1 -- -- -- NDER11 -- 0 1 -- -- -- PB3 input PB3 output TP11 output CS4 output TMIO3 output output*3 Pin function CS4 TMIO3 input*1 DREQ1 input*2 Notes: 1. TMIO3 input when CCLR1 = CCLR0 = 1. 2. When an external request is specified as a DMAC activation source, DREQ1 input regardless 3. CS4 is output as RAS4. of bits OIS3 and OIS2, OS1 and OS0, CCLR1 and CCLR0, CS4E, NDER11, and PB3DDR. DRAM interface settings (1) DRAS2 0 DRAS1 DRAS0 PB2/TP10/ TMO2/CS5 (2) 1 0 0 1 1 (1) 0 0 1 0 1 1 0 1 The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB2DDR select the pin function as follows. DRAM interface settings (1) in table below OIS3/2 and OS1/0 All 0 CS5E 0 PB2DDR 0 NDER10 Pin function (2) in table below 1 1 Not all 0 -- 1 -- -- -- -- -- -- 0 1 -- -- -- PB2 input PB2 output TP10 output CS5 TMIO2 output CS5 output output* Note: * CS5 is output as RAS5. DRAM interface settings (1) DRAS2 0 DRAS1 DRAS0 (2) 1 0 0 1 1 (1) 0 0 1 0 1 1 0 1 Rev. 3.00 Sep 14, 2005 page 317 of 910 REJ09B0258-0300 Section 8 I/O Ports Pin Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in TCR1, bit CS6E in CSCR, bit NDER9 in PB1/TP9/ TMIO1/ NDERB, and bit PB1DDR select the pin function as follows. DREQ0/CS6 OIS3/2 and OS1/0 All 0 CS6E Not all 0 0 PB1DDR 0 1 1 1 -- -- -- NDER9 -- 0 1 -- -- Pin function PB1 input PB1 output TP9 output CS6 TMIO1 output output TMIO1 input*1 DREQ0 input*2 Notes: 1. TMIO1 input when CCLR1 = CCLR0 = 1. 2. When an external request is specified as a DMAC activation source, DREQ0 input regardless of bits OIS3/2 and OS1/0, bits CCLR1/0, bit CS6E, bit NDER9, and bit PB1DDR. PB0/TP8/ TMO0/CS7 Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit NDER8 in NDERB, and bit PB0DDR select the pin function as follows. OIS3/2 and OS1/0 All 0 CS7E Not all 0 1 -- PB0DDR 0 1 1 -- -- NDER8 -- 0 1 -- -- PB0 input PB0 output TP8 output CS7 output TMO0 output Pin function 0 Rev. 3.00 Sep 14, 2005 page 318 of 910 REJ09B0258-0300 Section 8 I/O Ports Table 8.24 Port B Pin Functions (Modes 6 and 7) Pin Pin Functions and Selection Method PB7/TP15/ RxD2 Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB7DDR select the pin function as follows. SMIF 0 RE 1 -- PB7DDR 0 1 0 1 -- -- NDER15 -- 0 1 -- -- PB7 input PB7 output TP15 output RxD2 input RxD2 input Pin function PB6/TP14/ TxD2 1 Bit TE in SCR of SCI2, bit SMIF in SCMR, bit NDER14 in NDERB, and bit PB6DDR select the pin function as follows. SMIF 0 TE 1 0 PB6DDR 0 NDER14 Pin function 1 1 1 -- -- -- -- 0 1 -- -- PB6 input PB6 output TP14 output TxD2 output TxD2 output* Note: * Functions as the TxD2 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance. PB5/TP13/ SCK2 Bit C/A in SMR of SCI2, bits CKE0 and CKE1 in SCR, bit NDER13 in NDERB, and bit PB5DDR select the pin function as follows. CKE1 0 C/A 0 CKE0 0 1 -- -- 1 -- PB5DDR 0 1 1 -- -- -- NDER13 -- 0 1 -- -- -- PB5 input PB5 output TP13 output Pin function PB4/TP12 1 SCK2 output SCK2 output SCK2 input Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows. PB4DDR 0 1 NDER12 -- 0 1 PB4 input PB4 output TP12 output Pin function 1 Rev. 3.00 Sep 14, 2005 page 319 of 910 REJ09B0258-0300 Section 8 I/O Ports Pin Pin Functions and Selection Method PB3/TP11/ TMIO3/ Bits OIS3/2 and OS1/0 in TCSR3, bits CCLR1 and CCLR0 in TCR3, bit NDER11 in NDERB, and bit PB3DDR select the pin function as follows. DREQ1 OIS3/2 and OS1/0 All 0 Not all 0 PB3DDR 0 1 1 -- NDER11 -- 0 1 -- PB3 input PB3 output TP11 output TMIO3 output Pin function 1 TMIO3 input* DREQ1 input*2 Notes: 1. TMIO3 input when CCLR1 = CCLR0 = 1. 2. When an external request is specified as a DMAC activation source, DREQ1 input regardless of bits OIS3/2 and OS1/0, bit NDER11, and bit PB3DDR. PB2/TP10/ TMO2 Bits OIS3/2 and OS1/0 in TCSR2, bit NDER10 in NDERB, and bit PB2DDR select the pin function as follows. OIS3/2 and OS1/0 All 0 Not all 0 PB2DDR 0 1 1 -- NDER10 -- 0 1 -- PB2 input PB2 output TP10 output TMO2 output Pin function PB1/TP9/ TMIO1/ Bits OIS3/2 and OS1/0 in TCSR1, bits CCLR1 and CCLR0 in TCR1, bit NDER9 in NDERB, and bit PB1DDR select the pin function as follows. DREQ0 OIS3/2 and OS1/0 All 0 Not all 0 PB1DDR 0 1 1 -- NDER9 -- 0 1 -- PB1 input PB1 output TP9 output TMIO1 output Pin function TMIO1 input*1 DREQ0 input*2 Notes: 1. TMIO1 input when CCLR1 = CCLR0 = 1. 2. When an external request is specified as a DMAC activation source, DREQ0 input regardless of bits OIS3/2 and OS1/0, bit NDER9, and bit PB1DDR. PB0/TP8/ TMO0 Bits OIS3/2 and OS1/0 in TCSR0, bit NDER8 in NDERB, and bit PB0DDR select the pin function as follows. OIS3/2 and OS1/0 All 0 Not all 0 PB0DDR 0 1 1 -- NDER8 -- 0 1 -- PB0 input PB0 output TP8 output TMO0 output Pin function Rev. 3.00 Sep 14, 2005 page 320 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Section 9 16-Bit Timer 9.1 Overview The H8/3068F has built-in 16-bit timer module with three 16-bit counter channels. 9.1.1 Features 16-bit timer features are listed below. * Capability to process up to 6 pulse outputs or 6 pulse inputs * Six general registers (GRs, two per channel) with independently-assignable output compare or input capture functions * Selection of eight counter clock sources for each channel: Internal clocks: , /2, /4, /8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD * Five operating modes selectable in all channels: Waveform output by compare match Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2) Input capture function Rising edge, falling edge, or both edges (selectable) Counter clearing function Counters can be cleared by compare match or input capture Synchronization Two or more timer counters (16TCNTs) can be preset simultaneously, or cleared simultaneously by compare match or input capture. Counter synchronization enables synchronous register input and output. PWM mode PWM output can be provided with an arbitrary duty cycle. With synchronization, up to three-phase PWM output is possible * Phase counting mode selectable in channel 2 Two-phase encoder output can be counted automatically. * High-speed access via internal 16-bit bus The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus. * Any initial timer output value can be set Rev. 3.00 Sep 14, 2005 page 321 of 910 REJ09B0258-0300 Section 9 16-Bit Timer * Nine interrupt sources Each channel has two compare match/input capture interrupts and an overflow interrupt. All interrupts can be requested independently. * Output triggering of programmable timing pattern controller (TPC) Compare match/input capture signals from channels 0 to 2 can be used as TPC output triggers. Table 9.1 summarizes the 16-bit timer functions. Table 9.1 16-bit timer Functions Item Channel 0 Channel 1 Clock sources Internal clocks: , /2, /4, /8 Channel 2 External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently General registers (output compare/input capture registers) GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 Input/output pins Counter clearing function TIOCA0, TIOCB0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 GRA0/GRB0 compare match or input capture GRA1/GRB1 compare match or input capture GRA2/GRB2 compare match or input capture Initial output value setting function Available Available Available Compare match output 0 Available Available Available 1 Available Available Available Toggle Available Available Not available Input capture function Available Available Available Synchronization Available Available Available PWM mode Available Available Available Phase counting mode Not available Not available Available Interrupt sources Three sources Three sources Three sources * Compare match/input capture A0 * Compare match/input capture A1 * Compare match/input capture A2 * Compare match/input capture B0 * Compare match/input capture B1 * Compare match/input capture B2 * Overflow * Overflow * Overflow Rev. 3.00 Sep 14, 2005 page 322 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.1.2 Block Diagrams 16-bit timer Block Diagram (Overall): Figure 9.1 is a block diagram of the 16-bit timer. TCLKA to TCLKD IMIA0 to IMIA2 IMIB0 to IMIB2 OVI0 to OVI2 Clock selector , /2, /4, /8 Control logic TIOCA0 to TIOCA2 TIOCB0 to TIOCB2 TOLR TISRA TISRB Internal data bus TMDR Bus interface TSNR 16-bit timer channel 0 16-bit timer channel 1 16-bit timer channel 2 TSTR TISRC Module data bus Legend: TSTR: Timer start register (8 bits) TSNR: Timer synchro register (8 bits) TMDR: Timer mode register (8 bits) TOLR: Timer output level setting register (8 bits) TISRA: Timer interrupt status register A (8 bits) TISRB: Timer interrupt status register B (8 bits) TISRC: Timer interrupt status register C (8 bits) Figure 9.1 16-bit timer Block Diagram (Overall) Rev. 3.00 Sep 14, 2005 page 323 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. Both have the structure shown in figure 9.2. TCLKA to TCLKD , /2, /4, /8 TIOCA0 TIOCB0 Clock selector Control logic IMIA0 IMIB0 OVI0 TIOR 16TCR GRB GRA 16TCNT Comparator Module data bus Legend: 16TCNT: GRA, GRB: TCR: TIOR: Timer counter (16 bits) General registers A and B (input capture/output compare registers) (16 bits x 2) Timer control register (8 bits) Timer I/O control register (8 bits) Figure 9.2 Block Diagram of Channels 0 and 1 Rev. 3.00 Sep 14, 2005 page 324 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Block Diagram of Channel 2: Figure 9.3 is a block diagram of channel 2 TCLKA to TCLKD , /2, /4, /8 TIOCA2 TIOCB2 Clock selector Control logic IMIA2 IMIB2 OVI2 TIOR2 16TCR2 GRB2 GRA2 16TCNT2 Comparator Module data bus Legend: Timer counter 2 (16 bits) 16TCNT2: GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers) (16 bits x 2) Timer control register 2 (8 bits) TCR2: Timer I/O control register 2 (8 bits) TIOR2: Figure 9.3 Block Diagram of Channel 2 Rev. 3.00 Sep 14, 2005 page 325 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.1.3 Pin Configuration Table 9.2 summarizes the 16-bit timer pins. Table 9.2 16-bit timer Pins Abbreviation Input/ Output Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB Input External clock B input pin (phase-B input pin in phase counting mode) Clock input C TCLKC Input External clock C input pin Clock input D TCLKD Input External clock D input pin Input capture/output TIOCA0 compare A0 Input/ output GRA0 output compare or input capture pin PWM output pin in PWM mode Input capture/output TIOCB0 compare B0 Input/ output GRB0 output compare or input capture pin Input capture/output TIOCA1 compare A1 Input/ output GRA1 output compare or input capture pin PWM output pin in PWM mode Input capture/output TIOCB1 compare B1 Input/ output GRB1 output compare or input capture pin Input capture/output TIOCA2 compare A2 Input/ output GRA2 output compare or input capture pin PWM output pin in PWM mode Input capture/output TIOCB2 compare B2 Input/ output GRB2 output compare or input capture pin Channel 0 1 2 Name Rev. 3.00 Sep 14, 2005 page 326 of 910 REJ09B0258-0300 Function Section 9 16-Bit Timer 9.1.4 Register Configuration Table 9.3 summarizes the 16-bit timer registers. Table 9.3 16-bit timer Registers Channel Address*1 Name Abbreviation R/W Initial Value Common H'FFF60 Timer start register TSTR R/W H'F8 H'FFF61 Timer synchro register TSNC R/W H'F8 H'FFF62 Timer mode register TMDR R/W H'98 H'FFF63 Timer output level setting register TOLR W H'FFF64 H'FFF65 0 1 Timer interrupt status register A Timer interrupt status register B TISRA TISRB H'C0 2 H'88 2 H'88 2 R/(W)* R/(W)* H'FFF66 Timer interrupt status register C TISRC R/(W)* H'88 H'FFF68 Timer control register 0 16TCR0 R/W H'80 H'FFF69 Timer I/O control register 0 TIOR0 R/W H'88 H'FFF6A Timer counter 0H 16TCNT0H R/W H'00 H'FFF6B Timer counter 0L 16TCNT0L R/W H'00 H'FFF6C General register A0H GRA0H R/W H'FF H'FFF6D General register A0L GRA0L R/W H'FF H'FFF6E General register B0H GRB0H R/W H'FF H'FFF6F General register B0L GRB0L R/W H'FF H'FFF70 Timer control register 1 16TCR1 R/W H'80 H'FFF71 Timer I/O control register 1 TIOR1 R/W H'88 H'FFF72 Timer counter 1H 16TCNT1H R/W H'00 H'FFF73 Timer counter 1L 16TCNT1L R/W H'00 H'FFF74 General register A1H GRA1H R/W H'FF H'FFF75 General register A1L GRA1L R/W H'FF H'FFF76 General register B1H GRB1H R/W H'FF H'FFF77 General register B1L GRB1L R/W H'FF Rev. 3.00 Sep 14, 2005 page 327 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Channel Address*1 Name Abbreviation R/W Initial Value 2 H'FFF78 Timer control register 2 16TCR2 R/W H'80 H'FFF79 Timer I/O control register 2 TIOR2 R/W H'88 H'FFF7A Timer counter 2H 16TCNT2H R/W H'00 H'FFF7B Timer counter 2L 16TCNT2L R/W H'00 H'FFF7C General register A2H GRA2H R/W H'FF H'FFF7D General register A2L GRA2L R/W H'FF H'FFF7E General register B2H GRB2H R/W H'FF H'FFF7F General register B2L GRB2L R/W H'FF Notes: 1. The lower 20 bits of the address in advanced mode are indicated. 2. Only 0 can be written in bits 3 to 0, to clear the flags. 9.2 Register Descriptions 9.2.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (16TCNT) in channels 0 to 2. Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- STR2 STR1 STR0 Initial value 1 1 1 1 1 0 0 0 Read/Write -- -- -- -- -- R/W R/W R/W Reserved bits Counter start 2 to 0 These bits start and stop 16TCNT2 to 16TCNT0 TSTR is initialized to H'F8 by a reset and in standby mode. Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1. Rev. 3.00 Sep 14, 2005 page 328 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Bit 2--Counter Start 2 (STR2): Starts and stops timer counter 2 (16TCNT2). Bit 2 STR2 Description 0 16TCNT2 is halted 1 16TCNT2 is counting (Initial value) Bit 1--Counter Start 1 (STR1): Starts and stops timer counter 1 (16TCNT1). Bit 1 STR1 Description 0 16TCNT1 is halted 1 16TCNT1 is counting (Initial value) Bit 0--Counter Start 0 (STR0): Starts and stops timer counter 0 (16TCNT0). Bit 0 STR0 Description 0 16TCNT0 is halted 1 16TCNT0 is counting 9.2.2 (Initial value) Timer Synchro Register (TSNC) TSNC is an 8-bit readable/writable register that selects whether channels 0 to 2 operate independently or synchronously. Channels are synchronized by setting the corresponding bits to 1. Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- SYNC2 SYNC1 SYNC0 Initial value 1 1 1 1 1 0 0 0 Read/Write -- -- -- -- -- R/W R/W R/W Reserved bits Timer sync 2 to 0 These bits synchronize channels 2 to 0 TSNC is initialized to H'F8 by a reset and in standby mode. Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1. Rev. 3.00 Sep 14, 2005 page 329 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Bit 2--Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or synchronously. Bit 2 SYNC2 Description 0 Channel 2's timer counter (16TCNT2) operates independently 16TCNT2 is preset and cleared independently of other channels 1 Channel 2 operates synchronously 16TCNT2 can be synchronously preset and cleared (Initial value) Bit 1--Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or synchronously. Bit 1 SYNC1 Description 0 Channel 1's timer counter (16TCNT1) operates independently 16TCNT1 is preset and cleared independently of other channels 1 Channel 1 operates synchronously 16TCNT1 can be synchronously preset and cleared (Initial value) Bit 0--Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or synchronously. Bit 0 SYNC0 Description 0 Channel 0's timer counter (16TCNT0) operates independently 16TCNT0 is preset and cleared independently of other channels 1 Channel 0 operates synchronously 16TCNT0 can be synchronously preset and cleared Rev. 3.00 Sep 14, 2005 page 330 of 910 REJ09B0258-0300 (Initial value) Section 9 16-Bit Timer 9.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. Bit 7 6 5 4 3 2 1 0 -- MDF FDIR -- -- PWM2 PWM1 PWM0 Initial value 1 0 0 1 1 0 0 0 Read/Write -- R/W R/W -- -- R/W R/W R/W Reserved bit PWM mode 2 to 0 These bits select PWM mode for channels 2 to 0 Flag direction Selects the setting condition for the overflow flag (OVF) in TISRC Phase counting mode flag Selects phase counting mode for channel 2 Reserved bit TMDR is initialized to H'98 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bit 6--Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in phase counting mode. Bit 6 MDF Description 0 Channel 2 operates normally 1 Channel 2 operates in phase counting mode (Initial value) When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows. Rev. 3.00 Sep 14, 2005 page 331 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Counting Direction Down-Counting TCLKA pin High Low Low High TCLKB pin Low High High Low Up-Counting In phase counting mode, external clock edge selection by bits CKEG1 and CKEG0 in 16TCR2 and counter clock selection by bits TPSC2 to TPSC0 are invalid, and the above phase counting mode operations take precedence. The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the compare match/input capture settings and interrupt functions of TIOR2, TISRA, TISRB, TISRC remain effective in phase counting mode. Bit 5--Flag Direction (FDIR): Designates the setting condition for the OVF flag in TISRC. The FDIR designation is valid in all modes in channel 2. Bit 5 FDIR Description 0 OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows 1 OVF is set to 1 in TISRC when 16TCNT2 overflows (Initial value) Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 1. Bit 2--PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode. Bit 2 PWM2 Description 0 Channel 2 operates normally 1 Channel 2 operates in PWM mode (Initial value) When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2. Bit 1--PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode. Bit 1 PWM1 Description 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode Rev. 3.00 Sep 14, 2005 page 332 of 910 REJ09B0258-0300 (Initial value) Section 9 16-Bit Timer When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1. Bit 0--PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode. Bit 0 PWM0 Description 0 Channel 0 operates normally 1 Channel 0 operates in PWM mode (Initial value) When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0. 9.2.4 Timer Interrupt Status Register A (TISRA) TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture and enables or disables GRA compare match and input capture interrupt requests. Bit 7 -- 3 2 1 0 IMIEA2 IMIEA1 IMIEA0 -- IMFA2 IMFA1 IMFA0 6 5 4 Initial value 1 0 0 0 1 0 0 0 Read/Write -- R/W R/W R/W -- R/(W)* R/(W)* R/(W)* Input capture/compare match flags A2 to A0 Status flags indicating GRA compare match or input capture Reserved bit Input capture/compare match interrupt enable A2 to A0 These bits enable or disable interrupts by the IMFA flags Reserved bit Note: * Only 0 can be written, to clear the flag. TISRA is initialized to H'88 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Rev. 3.00 Sep 14, 2005 page 333 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Bit 6--Input Capture/Compare Match Interrupt Enable A2 (IMIEA2): Enables or disables the interrupt requested by the IMFA2 when IMFA2 flag is set to 1. Bit 6 IMIEA2 Description 0 IMIA2 interrupt requested by IMFA2 flag is disabled 1 IMIA2 interrupt requested by IMFA2 flag is enabled (Initial value) Bit 5--Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables the interrupt requested by the IMFA1 flag when IMFA1 is set to 1. Bit 5 IMIEA1 Description 0 IMIA1 interrupt requested by IMFA1 flag is disabled 1 IMIA1 interrupt requested by IMFA1 flag is enabled (Initial value) Bit 4--Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables the interrupt requested by the IMFA0 flag when IMFA0 is set to 1. Bit 4 IMIEA0 Description 0 IMIA0 interrupt requested by IMFA0 flag is disabled 1 IMIA0 interrupt requested by IMFA0 flag is enabled (Initial value) Bit 3--Reserved: This bit cannot be modified and is always read as 1. Bit 2--Input Capture/Compare Match Flag A2 (IMFA2): This status flag indicates GRA2 compare match or input capture events. Bit 2 IMFA2 Description 0 [Clearing condition] (Initial value) Read IMFA2 flag when IMFA2 =1, then write 0 in IMFA2 flag 1 [Setting conditions] * 16TCNT2 = GRA2 when GRA2 functions as an output compare register * 16TCNT2 value is transferred to GRA2 by an input capture signal when GRA2 functions as an input capture register Rev. 3.00 Sep 14, 2005 page 334 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Bit 1--Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1 compare match or input capture events. Bit 1 IMFA1 Description 0 [Clearing condition] (Initial value) Read IMFA1 flag when IMFA1 =1, then write 0 in IMFA1 flag 1 [Setting conditions] * 16TCNT1 = GRA1 when GRA1 functions as an output compare register * 16TCNT1 value is transferred to GRA1 by an input capture signal when GRA1 functions as an input capture register Bit 0--Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0 compare match or input capture events. Bit 0 IMFA0 Description 0 [Clearing condition] (Initial value) Read IMFA0 flag when IMFA0 =1, then write 0 in IMFA0 flag 1 [Setting conditions] * 16TCNT0 = GRA0 when GRA0 functions as an output compare register * 16TCNT0 value is transferred to GRA0 by an input capture signal when GRA0 functions as an input capture register Rev. 3.00 Sep 14, 2005 page 335 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.2.5 Timer Interrupt Status Register B (TISRB) TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture and enables or disables GRB compare match and input capture interrupt requests. Bit 7 -- Initial value Read/Write 1 -- 6 5 4 IMIEB2 IMIEB1 IMIEB0 0 R/W 0 R/W 0 R/W 3 2 1 0 -- IMFB2 IMFB1 IMFB0 1 0 0 0 -- R/(W)* R/(W)* R/(W)* Input capture/compare match flags B2 to B0 Status flags indicating GRB compare match or input capture Reserved bit Input capture/compare match interrupt enable B2 to B0 These bits enable or disable interrupts by the IMFB flags Reserved bit Note: * Only 0 can be written, to clear the flag. TISRB is initialized to H'88 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bit 6--Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables the interrupt requested by the IMFB2 when IMFB2 flag is set to 1. Bit 6 IMIEB2 Description 0 IMIB2 interrupt requested by IMFB2 flag is disabled 1 IMIB2 interrupt requested by IMFB2 flag is enabled Rev. 3.00 Sep 14, 2005 page 336 of 910 REJ09B0258-0300 (Initial value) Section 9 16-Bit Timer Bit 5--Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables the interrupt requested by the IMFB1 when IMFB1 flag is set to 1. Bit 5 IMIEB1 Description 0 IMIB1 interrupt requested by IMFB1 flag is disabled 1 IMIB1 interrupt requested by IMFB1 flag is enabled (Initial value) Bit 4--Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables the interrupt requested by the IMFB0 when IMFB0 flag is set to 1. Bit 4 IMIEB0 Description 0 IMIB0 interrupt requested by IMFB0 flag is disabled 1 IMIB0 interrupt requested by IMFB0 flag is enabled (Initial value) Bit 3--Reserved: This bit cannot be modified and is always read as 1. Bit 2--Input Capture/Compare Match Flag B2 (IMFB2): This status flag indicates GRB2 compare match or input capture events. Bit 2 IMFB2 Description 0 [Clearing condition] (Initial value) Read IMFB2 flag when IMFB2 =1, then write 0 in IMFB2 flag 1 [Setting conditions] * 16TCNT2 = GRB2 when GRB2 functions as an output compare register * 16TCNT2 value is transferred to GRB2 by an input capture signal when GRB2 functions as an input capture register Rev. 3.00 Sep 14, 2005 page 337 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Bit 1--Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1 compare match or input capture events. Bit 1 IMFB1 Description 0 [Clearing condition] (Initial value) Read IMFB1 flag when IMFB1 =1, then write 0 in IMFB1 flag 1 [Setting conditions] * 16TCNT1 = GRB1 when GRB1 functions as an output compare register * 16TCNT1 value is transferred to GRB1 by an input capture signal when GRB1 functions as an input capture register Bit 0--Input Capture/Compare Match Flag B0 (IMFB0): This status flag indicates GRB0 compare match or input capture events. Bit 0 IMFB0 Description 0 [Clearing condition] (Initial value) Read IMFB0 flag when IMFB0 =1, then write 0 in IMFB0 flag 1 [Setting conditions] * 16TCNT0 = GRB0 when GRB0 functions as an output compare register * 16TCNT0 value is transferred to GRB0 by an input capture signal when GRB0 functions as an input capture register Rev. 3.00 Sep 14, 2005 page 338 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.2.6 Timer Interrupt Status Register C (TISRC) TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and enables or disables overflow interrupt requests. Bit 7 6 5 4 3 2 1 0 -- OVIE2 OVIE1 OVIE0 -- OVF2 OVF1 OVF0 0 0 Initial value 1 0 0 0 1 Read/Write -- R/W R/W R/W -- R/(W)* R/(W)* 0 R/(W)* Overflow flags 2 to 0 Status flags indicating interrupts by OVF flags Reserved bit Overflow interrupt enable 2 to 0 These bits enable or disable interrupts by the OVF flags Reserved bit Note: * Only 0 can be written, to clear the flag. TISRC is initialized to H'88 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bit 6--Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the OVF2 when OVF2 flag is set to 1. Bit 6 OVIE2 Description 0 OVI2 interrupt requested by OVF2 flag is disabled 1 OVI2 interrupt requested by OVF2 flag is enabled (Initial value) Bit 5--Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the OVF1 when OVF1 flag is set to 1. Bit 5 OVIE1 Description 0 OVI1 interrupt requested by OVF1 flag is disabled 1 OVI1 interrupt requested by OVF1 flag is enabled (Initial value) Rev. 3.00 Sep 14, 2005 page 339 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Bit 4--Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the OVF0 when OVF0 flag is set to 1. Bit 4 OVIE0 Description 0 OVI0 interrupt requested by OVF0 flag is disabled 1 OVI0 interrupt requested by OVF0 flag is enabled (Initial value) Bit 3--Reserved: This bit cannot be modified and is always read as 1. Bit 2--Overflow Flag 2 (OVF2): This status flag indicates 16TCNT2 overflow. Bit 2 OVF2 Description 0 [Clearing condition] (Initial value) Read OVF2 flag when OVF2 =1, then write 0 in OVF2 flag 1 [Setting condition] 16TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF Note: 16TCNT underflow occurs when 16TCNT operates as an up/down-counter. Underflow occurs only when channel 2 operates in phase counting mode (MDF = 1 in TMDR). Bit 1--Overflow Flag 1 (OVF1): This status flag indicates 16TCNT1 overflow. Bit 1 OVF1 Description 0 [Clearing condition] (Initial value) Read OVF1 flag when OVF1 =1, then write 0 in OVF1 flag 1 [Setting condition] 16TCNT1 overflowed from H'FFFF to H'0000 Bit 0--Overflow Flag 0 (OVF0): This status flag indicates 16TCNT0 overflow. Bit 0 OVF0 Description 0 [Clearing condition] Read OVF0 flag when OVF0 =1, then write 0 in OVF0 flag 1 [Setting condition] 16TCNT0 overflowed from H'FFFF to H'0000 Rev. 3.00 Sep 14, 2005 page 340 of 910 REJ09B0258-0300 (Initial value) Section 9 16-Bit Timer 9.2.7 Timer Counters (16TCNT) 16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel. Channel Abbreviation Function 0 16TCNT0 Up-counter 1 16TCNT1 2 16TCNT2 Bit Initial value Read/Write Phase counting mode: up/down-counter Other modes: up-counter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The clock source is selected by bits TPSC2 to TPSC0 in 16TCR. 16TCNT0 and 16TCNT1 are up-counters. 16TCNT2 is an up/down-counter in phase counting mode and an up-counter in other modes. 16TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to GRA or GRB (counter clearing function). When 16TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TISRC of the corresponding channel. When 16TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TISRC of the corresponding channel. The 16TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. Each 16TCNT is initialized to H'0000 by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 341 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.2.8 General Registers (GRA, GRB) The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each channel. Channel Abbreviation Function 0 GRA0, GRB0 Output compare/input capture register 1 GRA1, GRB1 2 GRA2, GRB2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register. The function is selected by settings in TIOR. When a general register is used as an output compare register, its value is constantly compared with the 16TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set to 1 in TISRA/TISRB. Compare match output can be selected in TIOR. When a general register is used as an input capture register, an external input capture signal are detected and the current 16TCNT value is stored in the general register. The corresponding IMFA or IMFB flag in TISRA/TISRB is set to 1 at the same time. The edges of the input capture signal are selected in TIOR. TIOR settings are ignored in PWM mode. General registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. General registers are set as output compare registers (with no pin output) and initialized to H'FFFF by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 342 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.2.9 Timer Control Registers (16TCR) 16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel. Channel Abbreviation Function 0 16TCR0 1 16TCR1 2 16TCR2 16TCR controls the timer counter. The 16TCRs in all channels are functionally identical. When phase counting mode is selected in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in 16TCR2 are ignored. Bit 7 6 5 -- CCLR1 CCLR0 4 3 CKEG1 CKEG0 2 1 0 TPSC2 TPSC1 TPSC0 Initial value 1 0 0 0 0 0 0 0 Read/Write -- R/W R/W R/W R/W R/W R/W R/W Timer prescaler 2 to 0 These bits select the timer counter clock Clock edge 1/0 These bits select external clock edges Counter clear 1/0 These bits select the counter clear source Reserved bit Each 16TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects the edge or edges of external clock sources, and selects how the counter is cleared. 16TCR is initialized to H'80 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Rev. 3.00 Sep 14, 2005 page 343 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Bits 6 and 5--Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is cleared. Bit 6 CCLR1 Bit 5 CCLR0 Description 0 0 16TCNT is not cleared 1 (Initial value) 1 1 16TCNT is cleared by GRA compare match or input capture* 0 16TCNT is cleared by GRB compare match or input capture*1 1 Synchronous clear: 16TCNT is cleared in synchronization with other 2 synchronized timers* Notes: 1. 16TCNT is cleared by compare match when the general register functions as an output compare register, and by input capture when the general register functions as an input capture register. 2. Selected in TSNC. Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input edges when an external clock source is used. Bit 4 CKEG1 Bit 3 CKEG0 Description 0 0 Count rising edges 1 Count falling edges -- Count both edges 1 (Initial value) When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in 16TCR2 are ignored. Phase counting takes precedence. Rev. 3.00 Sep 14, 2005 page 344 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Bits 2 to 0--Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock source. Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Function 0 0 0 Internal clock: 1 Internal clock: /2 0 Internal clock: /4 1 Internal clock: /8 0 External clock A: TCLKA input 1 External clock B: TCLKB input 0 External clock C: TCLKC input 1 External clock D: TCLKD input 1 1 0 1 (Initial value) When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts the edges selected by bits CKEG1 and CKEG0. When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to TPSC0 in 16TCR2 are ignored. Phase counting takes precedence. Rev. 3.00 Sep 14, 2005 page 345 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.2.10 Timer I/O Control Register (TIOR) TIOR is an 8-bit register. The 16-bit timer has three TIORs, one in each channel. Channel Abbreviation Function 0 TIOR0 1 TIOR1 2 TIOR2 Bit TIOR controls the general registers. Some functions differ in PWM mode. 7 6 5 4 3 2 1 0 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 Initial value 1 0 0 0 1 0 0 0 Read/Write -- R/W R/W R/W -- R/W R/W R/W I/O control A2 to A0 These bits select GRA functions Reserved bit I/O control B2 to B0 These bits select GRB functions Reserved bit Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture function for GRA and GRB, and specifies the functions of the TIORA and TIORB pins. If the output compare function is selected, TIOR also selects the type of output. If input capture is selected, TIOR also selects the edges of the input capture signal. TIOR is initialized to H'88 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Rev. 3.00 Sep 14, 2005 page 346 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Bits 6 to 4--I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function. Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 0 0 0 1 1 1 0 GRB is an output compare register No output at compare match (Initial value) 0 output at GRB compare match*1 0 1 output at GRB compare match*1 1 Output toggles at GRB compare match (1 output in channel 2)*1 *2 0 1 1 Function GRB is an input compare register 0 GRB captures rising edge of input GRB captures falling edge of input GRB captures both edges of input 1 Notes: 1. After a reset, the output conforms to the TOLR setting until the first compare match. 2. Channel 2 output cannot be toggled by compare match. When this setting is made, 1 output is selected automatically. Bit 3--Reserved: This bit cannot be modified and is always read as 1. Bits 2 to 0--I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function. Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 0 0 0 1 1 1 0 GRA is an output compare register No output at compare match (Initial value) 0 output at GRA compare match*1 0 1 output at GRA compare match*1 1 Output toggles at GRA compare match 1 2 (1 output in channel 2)* * 0 1 1 Function 0 GRA is an input compare register GRA captures rising edge of input GRA captures falling edge of input GRA captures both edges of input 1 Notes: 1. After a reset, the output conforms to the TOLR setting until the first compare match. 2. Channel 2 output cannot be toggled by compare match. When this setting is made, 1 output is selected automatically. Rev. 3.00 Sep 14, 2005 page 347 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.2.11 Timer Output Level Setting Register C (TOLR) TOLR is an 8-bit write-only register that selects the timer output level for channels 0 to 2. Bit 7 6 5 4 3 2 1 0 -- -- TOB2 TOA2 TOB1 TOA1 TOB0 TOA0 Initial value 1 1 0 0 0 0 0 0 Read/Write -- -- W W W W W W Output level setting A2 to A0, B2 to B0 These bits set the levels of the timer outputs (TIOCA2 to TIOCA0, and TIOCB2 to TIOCB0) Reserved bits A TOLR setting can only be made when the corresponding bit in TSTR is 0. TOLR is a write-only register, and cannot be read. If it is read, all bits will return a value of 1. TOLR is initialized to H'C0 by a reset and in standby mode. Bits 7 and 6--Reserved: These bits cannot be modified. Bit 5--Output Level Setting B2 (TOB2): Sets the value of timer output TIOCB2. Bit 5 TOB2 Description 0 TIOCB2 is 0 1 TIOCB2 is 1 (Initial value) Bit 4--Output Level Setting A2 (TOA2): Sets the value of timer output TIOCA2. Bit 4 TOA2 Description 0 TIOCA2 is 0 1 TIOCA2 is 1 Rev. 3.00 Sep 14, 2005 page 348 of 910 REJ09B0258-0300 (Initial value) Section 9 16-Bit Timer Bit 3--Output Level Setting B1 (TOB1): Sets the value of timer output TIOCB1. Bit 3 TOB1 Description 0 TIOCB1 is 0 1 TIOCB1 is 1 (Initial value) Bit 2--Output Level Setting A1 (TOA1): Sets the value of timer output TIOCA1. Bit 2 TOA1 Description 0 TIOCA1 is 0 1 TIOCA1 is 1 (Initial value) Bit 1--Output Level Setting B0 (TOB0): Sets the value of timer output TIOCB0. Bit 0 TOB0 Description 0 TIOCB0 is 0 1 TIOCB0 is 1 (Initial value) Bit 0--Output Level Setting A0 (TOA0): Sets the value of timer output TIOCA0. Bit 0 TOA0 Description 0 TIOCA0 is 0 1 TIOCA0 is 1 (Initial value) Rev. 3.00 Sep 14, 2005 page 349 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.3 CPU Interface 9.3.1 16-Bit Accessible Registers The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time. Figures 9.4 and 9.5 show examples of word read/write access to a timer counter (16TCNT). Figures 9.6 to 9.9 show examples of byte read/write access to 16TCNTH and 16TCNTL. On-chip data bus H CPU L H Bus interface L 16TCNTH Module data bus 16TCNTL Figure 9.4 16TCNT Access Operation [CPU 16TCNT (Word)] On-chip data bus H CPU L H Bus interface L 16TCNTH 16TCNTL Figure 9.5 Access to Timer Counter (CPU Reads 16TCNT, Word) Rev. 3.00 Sep 14, 2005 page 350 of 910 REJ09B0258-0300 Module data bus Section 9 16-Bit Timer On-chip data bus H CPU L H Bus interface L 16TCNTH Module data bus 16TCNTL Figure 9.6 Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte) On-chip data bus H CPU L H Bus interface L 16TCNTH Module data bus 16TCNTL Figure 9.7 Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte) On-chip data bus H CPU L H Bus interface L 16TCNTH Module data bus 16TCNTL Figure 9.8 Access to Timer Counter H (CPU Reads 16TCNTH, Upper Byte) Rev. 3.00 Sep 14, 2005 page 351 of 910 REJ09B0258-0300 Section 9 16-Bit Timer On-chip data bus H CPU H L Bus interface L 16TCNTH Module data bus 16TCNTL Figure 9.9 Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte) 9.3.2 8-Bit Accessible Registers The registers other than the timer counters and general registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus. Figures 9.10 and 9.11 show examples of byte read and write access to a 16TCR. If a word-size data transfer instruction is executed, two byte transfers are performed. On-chip data bus H CPU L H Bus interface L 16TCR Figure 9.10 16TCR Access (CPU Writes to 16TCR) Rev. 3.00 Sep 14, 2005 page 352 of 910 REJ09B0258-0300 Module data bus Section 9 16-Bit Timer On-chip data bus H CPU H L Bus interface L Module data bus 16TCR Figure 9.11 16TCR Access (CPU Reads 16TCR) 9.4 Operation 9.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. GRA and GRB can be used for input capture or output compare. Synchronous Operation: The timer counters in designated channels are preset synchronously. Data written to the timer counter in any one of these channels is simultaneously written to the timer counters in the other channels as well. The timer counters can also be cleared synchronously if so designated by the CCLR1 and CCLR0 bits in the TCRs. PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB automatically become output compare registers. Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and TCLKB is detected and 16TCNT2 counts up or down accordingly. When phase counting mode is selected TCLKA and TCLKB become clock input pins and 16TCNT2 operates as an up/downcounter. Rev. 3.00 Sep 14, 2005 page 353 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.4.2 Basic Functions Counter Operation: When one of bits STR0 to STR2 is set to 1 in the timer start register (TSTR), the timer counter (16TCNT) in the corresponding channel starts counting. The counting can be free-running or periodic. * Sample setup procedure for counter Figure 9.12 shows a sample procedure for setting up a counter. Counter setup 1 Select counter clock Count operation No Yes Free-running counting Periodic counting Select counter clear source 2 Select output compare register function 3 Set period 4 Start counter 5 Periodic counter Start counter Free-running counter Figure 9.12 Counter Setup Procedure (Example) Rev. 3.00 Sep 14, 2005 page 354 of 910 REJ09B0258-0300 5 Section 9 16-Bit Timer 1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the external clock signal. 2. For periodic counting, set CCLR1 and CCLR0 in 16TCR to have 16TCNT cleared at GRA compare match or GRB compare match. 3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in step 2. 4. Write the count period in GRA or GRB, whichever was selected in step 2. 5. Set the STR bit to 1 in TSTR to start the timer counter. * Free-running and periodic counter operation A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC. After the overflow, the counter continues counting up from H'0000. Figure 9.13 illustrates free-running counting. 16TCNT value H'FFFF H'0000 Time STR0 to STR2 bit OVF Figure 9.13 Free-Running Counter Operation When a channel is set to have its counter cleared by compare match, in that channel 16TCNT operates as a periodic counter. Select the output compare function of GRA or GRB, set bit CCLR1 or CCLR0 in 16TCR to have the counter cleared by compare match, and set the count period in GRA or GRB. After these settings, the counter starts counting up as a periodic counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or GRB, the IMFA or IMFB flag is set to 1 in TISRA/TISRB and the counter is cleared to H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TISRA/TISRB, a CPU interrupt is requested at this time. After the compare match, 16TCNT continues counting up from H'0000. Figure 9.14 illustrates periodic counting. Rev. 3.00 Sep 14, 2005 page 355 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 16TCNT value Counter cleared by general register compare match GR Time H'0000 STR bit IMF Figure 9.14 Periodic Counter Operation * 16TCNT count timing Internal clock source Bits TPSC2 to TPSC0 in 16TCR select the system clock () or one of three internal clock sources obtained by prescaling the system clock (/2, /4, /8). Figure 9.15 shows the timing. Internal clock 16TCNT input clock 16TCNT N-1 N N+1 Figure 9.15 Count Timing for Internal Clock Sources External clock source The external clock pin (TCLKA to TCLKD) can be selected by bits TPSC2 to TPSC0 in 16TCR, and the detected edge by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly. Figure 9.16 shows the timing when both edges are detected. Rev. 3.00 Sep 14, 2005 page 356 of 910 REJ09B0258-0300 Section 9 16-Bit Timer External clock input 16TCNT input clock 16TCNT N-1 N N+1 Figure 9.16 Count Timing for External Clock Sources (when Both Edges are Detected) Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1. * Sample setup procedure for waveform output by compare match Figure 9.17 shows an example of the setup procedure for waveform output by compare match. Output setup 1. Select the compare match output mode (0, 1, or toggle) in TIOR. When a waveform output mode is selected, the pin switches from its generic input/ output function to the output compare function (TIOCA or TIOCB). An output compare pin outputs the value set in TOLR until the first compare match occurs. Select waveform output mode 1 Set output timing 2 2. Set a value in GRA or GRB to designate the compare match timing. Start counter 3 3. Set the STR bit to 1 in TSTR to start the timer counter. Waveform output Figure 9.17 Setup Procedure for Waveform Output by Compare Match (Example) Rev. 3.00 Sep 14, 2005 page 357 of 910 REJ09B0258-0300 Section 9 16-Bit Timer * Examples of waveform output Figure 9.18 shows examples of 0 and 1 output. 16TCNT operates as a free-running counter, 0 output is selected for compare match A, and 1 output is selected for compare match B. When the pin is already at the selected output level, the pin level does not change. 16TCNT value H'FFFF GRB GRA H'0000 Time TIOCB No change No change TIOCA No change No change 1 output 0 output Figure 9.18 0 and 1 Output (TOA = 1, TOB = 0) Figure 9.19 shows examples of toggle output. 16TCNT operates as a periodic counter, cleared by compare match B. Toggle output is selected for both compare match A and B. 16TCNT value Counter cleared by compare match with GRB GRB GRA H'0000 Time TIOCB Toggle output TIOCA Toggle output Figure 9.19 Toggle Output (TOA = 1, TOB = 0) Rev. 3.00 Sep 14, 2005 page 358 of 910 REJ09B0258-0300 Section 9 16-Bit Timer * Output compare output timing The compare match signal is generated in the last state in which 16TCNT and the general register match (when 16TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB). When 16TCNT matches a general register, the compare match signal is not generated until the next counter clock pulse. Figure 9.20 shows the output compare timing. 16TCNT input clock 16TCNT N GR N N+1 Compare match signal TIOCA, TIOCB Figure 9.20 Output Compare Output Timing Input Capture Function: The 16TCNT value can be transferred to a general register when an input edge is detected at an input capture input/output compare pin (TIOCA or TIOCB). Risingedge, falling-edge, or both-edge detection can be selected. The input capture function can be used to measure pulse width or period. Rev. 3.00 Sep 14, 2005 page 359 of 910 REJ09B0258-0300 Section 9 16-Bit Timer * Sample setup procedure for input capture Figure 9.21 shows a sample procedure for setting up input capture. Input selection 1. Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the DDR bit to 0 before making these TIOR settings. Select input-capture input 1 Start counter 2 2. Set the STR bit to 1 in TSTR to start the timer counter. Input capture Figure 9.21 Setup Procedure for Input Capture (Example) * Examples of input capture Figure 9.22 illustrates input capture when the falling edge of TIOCB and both edges of TIOCA are selected as capture edges. 16TCNT is cleared by input capture into GRB. 16TCNT value H'0180 H'0160 H'0005 H'0000 TIOCB TIOCA GRA H'0005 H'0160 GRB H'0180 Figure 9.22 Input Capture (Example) Rev. 3.00 Sep 14, 2005 page 360 of 910 REJ09B0258-0300 Section 9 16-Bit Timer * Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 9.23 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges. Input-capture input Input capture signal N 16TCNT N GRA, GRB Figure 9.23 Input Capture Signal Timing 9.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate 16TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base. Synchronization can be selected for all channels (0 to 2). Sample Setup Procedure for Synchronization: Figure 9.24 shows a sample procedure for setting up synchronization. Rev. 3.00 Sep 14, 2005 page 361 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Setup for synchronization Select synchronization 1 Synchronous preset Write to 16TCNT Synchronous clear 2 Clearing synchronized to this channel? No Yes Synchronous preset Select counter clear source 3 Select counter clear source 4 Start counter 5 Start counter 5 Counter clear Synchronous clear 1. Set the SYNC bits to 1 in TSNC for the channels to be synchronized. 2. When a value is written in 16TCNT in one of the synchronized channels, the same value is simultaneously written in 16TCNT in the other channels. 3. Set the CCLR1 or CCLR0 bit in 16TCR to have the counter cleared by compare match or input capture. 4. Set the CCLR1 and CCLR0 bits in 16TCR to have the counter cleared synchronously. 5. Set the STR bits in TSTR to 1 to start the synchronized counters. Figure 9.24 Setup Procedure for Synchronization (Example) Example of Synchronization: Figure 9.25 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0, TIOCA1, and TIOCA2. For further information on PWM mode, see section 9.4.4, PWM Mode. Rev. 3.00 Sep 14, 2005 page 362 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Value of 16TCNT0 to 16TCNT2 Cleared by compare match with GRB0 GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 H'0000 TIOCA0 TIOCA1 TIOCA2 Figure 9.25 Synchronization (Example) 9.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0. If either GRA or GRB compare match is selected as the counter clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can be selected in all channels (0 to 2). Table 9.4 summarizes the PWM output pins and corresponding registers. If the same value is set in GRA and GRB, the output does not change when compare match occurs. Rev. 3.00 Sep 14, 2005 page 363 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Table 9.4 PWM Output Pins and Registers Channel Output Pin 1 Output 0 Output 0 TIOCA0 GRA0 GRB0 1 TIOCA1 GRA1 GRB1 2 TIOCA2 GRA2 GRB2 Sample Setup Procedure for PWM Mode: Figure 9.26 shows a sample procedure for setting up PWM mode. PWM mode Select counter clock 1 Select counter clear source 2 1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the external clock signal. 2. Set bits CCLR1 and CCLR0 in 16TCR to select the counter clear source. 3. Set the time at which the PWM waveform should go to 1 in GRA. Set GRA 3 Set GRB 4 Select PWM mode 5 Start counter 6 PWM mode 4. Set the time at which the PWM waveform should go to 0 in GRB. 5. Set the PWM bit in TMDR to select PWM mode. When PWM mode is selected, regardless of the TIOR contents, GRA and GRB become output compare registers specifying the times at which the PWM output goes to 1 and 0. The TIOCA pin automatically becomes the PWM output pin. The TIOCB pin conforms to the settings of bits IOB1 and IOB0 in TIOR. If TIOCB output is not desired, clear both IOB1 and IOB0 to 0. 6. Set the STR bit to 1 in TSTR to start the timer counter. Figure 9.26 Setup Procedure for PWM Mode (Example) Rev. 3.00 Sep 14, 2005 page 364 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Examples of PWM Mode: Figure 9.27 shows examples of operation in PWM mode. In PWM mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, 16TCNT is cleared by compare match with GRA or GRB. Synchronized operation and free-running counting are also possible. 16TCNT value Counter cleared by compare match A GRA GRB Time H'0000 TIOCA a. Counter cleared by GRA (TOA = 1) 16TCNT value Counter cleared by compare match B GRB GRA Time H'0000 TIOCA b. Counter cleared by GRB (TOA = 0) Figure 9.27 PWM Mode (Example 1) Rev. 3.00 Sep 14, 2005 page 365 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Figure 9.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%. 16TCNT value Counter cleared by compare match B GRB GRA Time H'0000 TIOCA Write to GRA Write to GRA a. 0% duty cycle (TOA=0) 16TCNT value Counter cleared by compare match A GRA GRB Time H'0000 TIOCA Write to GRB Write to GRB b. 100% duty cycle (TOA=1) Figure 9.28 PWM Mode (Example 2) Rev. 3.00 Sep 14, 2005 page 366 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.4.5 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in 16TCR2. Settings of bits CCLR1, CCLR0 in 16TCR2, and settings in TIOR2, TISRA, TISRB, TISRC, setting of STR2 bit in TSTR, GRA2, and GRB2 are valid. The input capture and output compare functions can be used, and interrupts can be generated. Phase counting is available only in channel 2. Sample Setup Procedure for Phase Counting Mode: Figure 9.29 shows a sample procedure for setting up phase counting mode. Phase counting mode Select phase counting mode 1 1. Set the MDF bit in TMDR to 1 to select phase counting mode. 2. Select the flag setting condition with the FDIR bit in TMDR. Select flag setting condition 2 Start counter 3 3. Set the STR2 bit to 1 in TSTR to start the timer counter. Phase counting mode Figure 9.29 Setup Procedure for Phase Counting Mode (Example) Rev. 3.00 Sep 14, 2005 page 367 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Example of Phase Counting Mode: Figure 9.30 shows an example of operations in phase counting mode. Table 9.5 lists the up-counting and down-counting conditions for 16TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states. 16TCNT2 value Counting up Counting down TCLKB TCLKA Figure 9.30 Operation in Phase Counting Mode (Example) Table 9.5 Up/Down Counting Conditions Counting Direction Up-Counting TCLKB pin High Low HIgh Low TCLKA pin Low High Low HIgh Phase difference Down-Counting Phase difference Pulse width Pulse width TCLKA TCLKB Overlap Overlap Phase difference and overlap: at least 1.5 states at least 2.5 states Pulse width: Figure 9.31 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 3.00 Sep 14, 2005 page 368 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.4.6 16-Bit Timer Output Timing The initial value of 16-bit timer output when a timer count operation begins can be specified arbitrarily by making a setting in TOLR. Figure 9.32 shows the timing for setting the initial value with TOLR. Only write to TOLR when the corresponding bit in TSTR is cleared to 0. T1 T3 T2 Address bus TOLR 16-bit timer output pin TOLR address N N Figure 9.32 Timing for Setting 16-Bit Timer Output Level by Writing to TOLR Rev. 3.00 Sep 14, 2005 page 369 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.5 Interrupts The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 9.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when 16TCNT matches a general register (GR). The compare match signal is generated in the last state in which the values match (when 16TCNT is updated from the matching count to the next count). Therefore, when 16TCNT matches a general register, the compare match signal is not generated until the next 16TCNT clock input. Figure 9.33 shows the timing of the setting of IMFA and IMFB. 16TCNT input clock 16TCNT N GR N+1 N Compare match signal IMF IMI Figure 9.33 Timing of Setting of IMFA and IMFB by Compare Match Rev. 3.00 Sep 14, 2005 page 370 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding general register. Figure 9.34 shows the timing. Input capture signal IMF 16TCNT GR N N IMI Figure 9.34 Timing of Setting of IMFA and IMFB by Input Capture Rev. 3.00 Sep 14, 2005 page 371 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 9.35 shows the timing. 16TCNT Overflow signal OVF OVI Figure 9.35 Timing of Setting of OVF 9.5.2 Timing of Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 9.36 shows the timing. TISR write cycle T1 T2 T3 Address TISR address IMF, OVF Figure 9.36 Timing of Clearing of Status Flags Rev. 3.00 Sep 14, 2005 page 372 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.5.3 Interrupt Sources Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag are set to 1. The priority order of the channels can be modified in interrupt priority registers A (IPRA). For details see section 5, Interrupt Controller. Table 9.6 lists the interrupt sources. Table 9.6 16-bit timer Interrupt Sources Interrupt Source Description Priority* 0 IMIA0 IMIB0 OVI0 Compare match/input capture A0 Compare match/input capture B0 Overflow 0 High 1 IMIA1 IMIB1 OVI1 Compare match/input capture A1 Compare match/input capture B1 Overflow 1 2 IMIA2 IMIB2 OVI2 Compare match/input capture A2 Compare match/input capture B2 Overflow 2 Channel Low Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed by settings in IPRA. Rev. 3.00 Sep 14, 2005 page 373 of 910 REJ09B0258-0300 Section 9 16-Bit Timer 9.6 Usage Notes This section describes contention and other matters requiring special attention during 16-bit timer operations. Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T3 state of a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 9.37. 16TCNT write cycle T2 T1 T3 Address bus 16TCNT address Internal write signal Counter clear signal 16TCNT N H'0000 Figure 9.37 Contention between 16TCNT Write and Clear Rev. 3.00 Sep 14, 2005 page 374 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the T3 state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented. Figure 9.38 shows the timing in this case. 16TCNT word write cycle T2 T1 T3 Address bus 16TCNT address Internal write signal 16TCNT input clock 16TCNT N M 16TCNT write data Figure 9.38 Contention between 16TCNT Word Write and Increment Rev. 3.00 Sep 14, 2005 page 375 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the T2 or T3 state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not incremented. The byte data for which a write was not performed is not incremented, and retains its pre-write value. See figure 9.39, which shows an increment pulse occurring in the T2 state of a byte write to 16TCNTH. 16TCNTH byte write cycle T1 T2 T3 16TCNTH address Address bus Internal write signal 16TCNT input clock 16TCNTH N M 16TCNT write data 16TCNTL X X+1 X Figure 9.39 Contention between 16TCNT Byte Write and Increment Rev. 3.00 Sep 14, 2005 page 376 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Contention between General Register Write and Compare Match: If a compare match occurs in the T3 state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 9.40. General register write cycle T1 T2 T3 GR address Address bus Internal write signal 16TCNT N GR N N+1 M General register write data Compare match signal Inhibited Figure 9.40 Contention between General Register Write and Compare Match Rev. 3.00 Sep 14, 2005 page 377 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the T3 state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1.The same holds for underflow. See figure 9.41. 16TCNT write cycle T1 T2 T3 Address bus 16TCNT address Internal write signal 16TCNT input clock Overflow signal 16TCNT H'FFFF M 16TCNT write data OVF Figure 9.41 Contention between 16TCNT Write and Overflow Rev. 3.00 Sep 14, 2005 page 378 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Contention between General Register Read and Input Capture: If an input capture signal occurs during the T3 state of a general register read cycle, the value before input capture is read. See figure 9.42. General register read cycle T2 T1 T3 GR address Address bus Internal read signal Input capture signal GR Internal data bus X M X Figure 9.42 Contention between General Register Read and Input Capture Rev. 3.00 Sep 14, 2005 page 379 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register. See figure 9.43. Input capture signal Counter clear signal 16TCNT input clock 16TCNT GR N H'0000 N Figure 9.43 Contention between Counter Clearing by Input Capture and Counter Increment Rev. 3.00 Sep 14, 2005 page 380 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Contention between General Register Write and Input Capture: If an input capture signal occurs in the T3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 9.44. General register write cycle T1 T2 T3 Address bus GR address Internal write signal Input capture signal 16TCNT GR M M Figure 9.44 Contention between General Register Write and Input Capture Rev. 3.00 Sep 14, 2005 page 381 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is cleared in the last state at which the 16TCNT value matches the general register value, at the time when this value would normally be updated to the next count. The actual counter frequency is therefore given by the following formula: f= (N+1) (f: counter frequency. : system clock frequency. N: value set in general register.) Note on Writes in Synchronized Operation: When channels are synchronized, if a 16TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 1 and 2 are synchronized * Byte write to channel 1 or byte write to channel 2 16TCNT1 W X 16TCNT2 Y Z Upper byte Lower byte Write A to upper byte of channel 1 16TCNT1 A X 16TCNT2 A X Upper byte Lower byte Write A to lower byte of channel 2 16TCNT1 Y A 16TCNT2 Y A Upper byte Lower byte * Word write to channel 1 or word write to channel 2 16TCNT1 W X 16TCNT2 Y Z Write AB word to channel 1 or 2 Upper byte Lower byte Rev. 3.00 Sep 14, 2005 page 382 of 910 REJ09B0258-0300 16TCNT1 A B 16TCNT2 A B Upper byte Lower byte Section 9 16-Bit Timer 16-bit timer Operating Modes Table 9.7 (a) 16-bit timer Operating Modes (Channel 0) Register Settings TSNC TMDR TIOR0 16TCR0 Operating Mode Synchronization Synchronous preset SYNC0 = 1 -- -- PWM mode -- -- PWM0 = 1 -- Output compare A -- -- PWM0 = 0 IOA2 = 0 Other bits unrestricted Output compare B -- -- Input capture A -- -- PWM0 = 0 Input capture B -- -- PWM0 = 0 Counter By compare clearing match/input capture A -- -- CCLR1 = 0 CCLR0 = 1 By compare match/input capture B -- -- CCLR1 = 1 CCLR0 = 0 SYNC0 = 1 -- -- CCLR1 = 1 CCLR0 = 1 Synchronous clear Legend: MDF FDIR PWM IOA IOB Clear Select Clock Select * IOB2 = 0 Other bits unrestricted IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted Setting available (valid). -- Setting does not affect this mode. Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Rev. 3.00 Sep 14, 2005 page 383 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Table 9.7 (b) 16-bit timer Operating Modes (Channel 1) Register Settings TSNC TMDR TIOR1 16TCR1 Operating Mode Synchronization Synchronous preset SYNC1 = 1 -- -- PWM mode -- -- PWM1 = 1 -- Output compare A -- -- PWM1 = 0 IOA2 = 0 Other bits unrestricted Output compare B -- -- Input capture A -- -- PWM1 = 0 Input capture B -- -- PWM1 = 0 Counter By compare clearing match/input capture A -- -- CCLR1 = 0 CCLR0 = 1 By compare match/input capture B -- -- CCLR1 = 1 CCLR0 = 0 SYNC1 = 1 -- -- CCLR1 = 1 CCLR0 = 1 Synchronous clear MDF FDIR PWM IOA IOB Clear Select Clock Select * IOB2 = 0 Other bits unrestricted IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted Legend: Setting available (valid). -- Setting does not affect this mode. Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Rev. 3.00 Sep 14, 2005 page 384 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Table 9.7 (c) 16-bit timer Operating Modes (Channel 2) Register Settings TSNC Operating Mode Synchronization Synchronous preset SYNC2 = 1 TMDR MDF FDIR PWM TIOR2 IOA IOB 16TCR2 Clear Select -- * PWM mode -- PWM2 = 1 -- Output compare A -- PWM2 = 0 IOA2 = 0 Other bits unrestricted Output compare B -- Input capture A -- PWM2 = 0 Input capture B -- PWM2 = 0 Counter By compare clearing match/input capture A -- CCLR1 = 0 CCLR0 = 1 By compare match/input capture B -- CCLR1 = 1 CCLR0 = 0 -- CCLR1 = 1 CCLR0 = 1 Synchronous clear Phase counting mode Clock Select SYNC2 = 1 MDF = 1 IOB2 = 0 Other bits unrestricted IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted -- Legend: Setting available (valid). -- Setting does not affect this mode. Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Rev. 3.00 Sep 14, 2005 page 385 of 910 REJ09B0258-0300 Section 9 16-Bit Timer Rev. 3.00 Sep 14, 2005 page 386 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Section 10 8-Bit Timers 10.1 Overview The H8/3068F has a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2, and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two 8-bit time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT value to detect compare match events. The timers can be used as multifunctional timers in a variety of applications, including the generation of a rectangular-wave output with an arbitrary duty cycle. 10.1.1 Features The features of the 8-bit timer module are listed below. * Selection of four clock sources The counters can be driven by one of three internal clock signals (/8, /64, or /8192) or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or input capture B. * Timer output controlled by two compare match signals The timer output signal in each channel is controlled by two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output. * A/D converter can be activated by a compare match * Two channels can be cascaded Channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). Channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). Channel 1 can count channel 0 compare match events (compare match count mode). Channel 3 can count channel 2 compare match events (compare match count mode). * Input capture function can be set 8-bit or 16-bit input capture operation is available. Rev. 3.00 Sep 14, 2005 page 387 of 910 REJ09B0258-0300 Section 10 8-Bit Timers * Twelve interrupt sources There are twelve interrupt sources: four compare match sources, four compare match/input capture sources, four overflow sources. Two of the compare match sources and two of the combined compare match/input capture sources each have an independent interrupt vector. The remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources. Rev. 3.00 Sep 14, 2005 page 388 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.1.2 Block Diagram The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. Figure 10.1 shows a block diagram of 8-bit timer group 0. External clock sources TCLKA TCLKC Internal clock sources /8 /64 /8192 Clock 1 Clock 0 Clock select TCORA0 TCORA1 Compare match A1 Compare match A0 Comparator A0 Comparator A1 Overflow 1 TMO0 TMIO1 8TCNT0 8TCNT1 Internal bus Overflow 0 Compare match B1 Control logic Compare match B0 Comparator B0 Input capture B1 Legend: TCORA: TCORB: 8TCNT: 8TCSR: 8TCR: Comparator B1 TCORB0 TCORB1 8TCSR0 8TCSR1 8TCR0 8TCR1 CMIA0 CMIB0 CMIA1/CMIB1 OVI0/OVI1 Interrupt signals Time constant register A Time constant register B Timer counter Timer control/status register Timer control register Figure 10.1 Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0) Rev. 3.00 Sep 14, 2005 page 389 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.1.3 Pin Configuration Table 10.1 summarizes the input/output pins of the 8-bit timer module. Table 10.1 8-Bit Timer Pins Group Channel Name Abbreviation I/O 0 0 Timer output TMO0 Output Compare match output Timer clock input TCLKC Input Counter external clock input Timer input/output TMIO1 I/O Compare match output/input capture input Timer clock input TCLKA Input Counter external clock input Timer output TMO2 Output Compare match output Timer clock input TCLKD Input Counter external clock input Timer input/output TMIO3 I/O Compare match output/input capture input Timer clock input Input Counter external clock input 1 1 2 3 TCLKB Rev. 3.00 Sep 14, 2005 page 390 of 910 REJ09B0258-0300 Function Section 10 8-Bit Timers 10.1.4 Register Configuration Table 10.2 summarizes the registers of the 8-bit timer module. Table 10.2 8-Bit Timer Registers Channel Address*1 Name Abbreviation R/W 0 H'FFF80 Timer control register 0 8TCR0 1 2 3 Initial value R/W H'00 2 H'FFF82 Timer control/status register 0 8TCSR0 R/(W)* H'00 H'FFF84 Time constant register A0 TCORA0 R/W H'FF H'FFF86 Time constant register B0 TCORB0 R/W H'FF H'FFF88 Timer counter 0 8TCNT0 R/W H'00 H'FFF81 Timer control register 1 8TCR1 R/W H'00 2 H'FFF83 Timer control/status register 1 8TCSR1 R/(W)* H'00 H'FFF85 Time constant register A1 TCORA1 R/W H'FF H'FFF87 Time constant register B1 TCORB1 R/W H'FF H'FFF89 Timer counter 1 8TCNT1 R/W H'00 H'FFF90 Timer control register 2 8TCR2 R/W H'00 2 H'FFF92 Timer control/status register 2 8TCSR2 R/(W)* H'10 H'FFF94 Time constant register A2 TCORA2 R/W H'FF H'FFF96 Time constant register B2 TCORB2 R/W H'FF H'FFF98 Timer counter 2 8TCNT2 R/W H'00 H'FFF91 Timer control register 3 8TCR3 R/W H'00 H'FFF93 Timer control/status register 3 8TCSR3 R/(W)*2 H'00 H'FFF95 Time constant register A3 TCORA3 R/W H'FF H'FFF97 Time constant register B3 TCORB3 R/W H'FF H'FFF99 Timer counter 3 8TCNT3 R/W H'00 Notes: 1. Indicates the lower 20 bits of the address in advanced mode. 2. Only 0 can be written to bits 7 to 5, to clear these flags. Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the channel 0 register as the upper 8 bits and the channel 1 register as the lower 8 bits, so they can be accessed together by word access. Similarly, each pair of registers for channel 2 and channel 3 comprises a 16-bit register with the channel 2 register as the upper 8 bits and the channel 3 register as the lower 8 bits, so they can be accessed together by word access. Rev. 3.00 Sep 14, 2005 page 391 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.2 Register Descriptions 10.2.1 Timer Counters (8TCNT) 8TCNT0 8TCNT1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8TCNT2 Bit Initial value Read/Write 8TCNT3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR). The CPU can always read or write to the timer counters. The 8TCNT0 and 8TCNT1 pair, and the 8TCNT2 and 8TCNT3 pair, can each be accessed as a 16-bit register by word access. 8TCNT can be cleared by an input capture signal or compare match signal. Counter clear bits 1 and 0 (CCLR1 and CCLR0) in 8TCR select the method of clearing. When 8TCNT overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status register (8TCSR) is set to 1. Each 8TCNT is initialized to H'00 by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 392 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.2.2 Time Constant Registers A (TCORA) TCORA0 to TCORA3 are 8-bit readable/writable registers. TCORA0 Bit Initial value Read/Write TCORA1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORA2 TCORA3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a 16-bit register by word access. The TCORA value is constantly compared with the 8TCNT value. When a match is detected, the corresponding compare match flag A (CMFA) is set to 1 in 8TCSR. The timer output can be freely controlled by these compare match signals and the settings of output select bits 1 and 0 (OS1, OS0) in 8TCSR. Each TCORA register is initialized to H'FF by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 393 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.2.3 Time Constant Registers B (TCORB) TCORB0 TCORB1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB2 TCORB3 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access. The TCORB value is constantly compared with the 8TCNT value. When a match is detected, the corresponding compare match flag B (CMFB) is set to 1 in 8TCSR*. The timer output can be freely controlled by these compare match signals and the settings of output/input capture edge select bits 3 and 2 (OIS3, OIS2) in 8TCSR. When TCORB is used for input capture, it stores the 8TCNT value on detection of an external input capture signal. At this time, the CMFB flag is set to 1 in the corresponding 8TCSR register. The detected edge of the input capture signal is set in 8TCSR. Each TCORB register is initialized to H'FF by a reset and in standby mode. Note: * When channel 1 and channel 3 are designated for TCORB input capture, the CMFB flag is not set by a channel 0 or channel 2 compare match B. Rev. 3.00 Sep 14, 2005 page 394 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.2.4 Timer Control Register (8TCR) Bit 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT clearing specification, and enables interrupt requests. 8TCR is initialized to H'00 by a reset and in standby mode. For the timing, see section 10.4, Operation. Bit 7--Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt request when the CMFB flag is set to 1 in 8TCSR. Bit 7 CMIEB Description 0 CMIB interrupt requested by CMFB is disabled 1 CMIB interrupt requested by CMFB is enabled (Initial value) Bit 6--Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt request when the CMFA flag is set to 1 in 8TCSR. Bit 6 CMIEA Description 0 CMIA interrupt requested by CMFA is disabled 1 CMIA interrupt requested by CMFA is enabled (Initial value) Bit 5--Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt request when the OVF flag is set to 1 in 8TCSR. Bit 5 OVIE Description 0 OVI interrupt requested by OVF is disabled 1 OVI interrupt requested by OVF is enabled (Initial value) Rev. 3.00 Sep 14, 2005 page 395 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Bits 4 and 3--Counter Clear 1 and 0 (CCLR1, CCLR0): These bits specify the 8TCNT clearing source. Compare match A or B, or input capture B, can be selected as the clearing source. Bit 4 CCLR1 Bit 3 CCLR0 Description 0 0 Clearing is disabled 1 Cleared by compare match A 1 0 Cleared by compare match B/input capture B 1 Cleared by input capture B (Initial value) Note: When input capture B is set as the 8TCNT1 and 8TCNT3 counter clear source, 8TCNT0 and 8TCNT2 are not cleared by compare match B. Bits 2 to 0--Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to 8TCNT is an internal or external clock. Three internal clocks can be selected, all divided from the system clock (): /8, /64, and /8192. The rising edge of the selected internal clock triggers the count. When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. When CKS2, CKS1, CKS0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded. The incrementing clock source is different when 8TCR0 and 8TCR2 are set, and when 8TCR1 and 8TCR3 are set. Rev. 3.00 Sep 14, 2005 page 396 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Bit 2 CSK2 Bit 1 CSK1 Bit 0 CSK0 Description 0 0 0 Clock input disabled 1 Internal clock, counted on falling edge of /8 0 Internal clock, counted on falling edge of /64 1 Internal clock, counted on falling edge of /8192 0 Channel 0 (16-bit count mode): Count on 8TCNT1 overflow 1 signal* 1 1 0 (Initial value) Channel 1 (compare match count mode): Count on 8TCNT0 1 compare match A* Channel 2 (16-bit count mode): Count on 8TCNT3 overflow 2 signal* Channel 3 (compare match count mode): Count on 8TCNT2 2 compare match A* 1 1 External clock, counted on rising edge 0 External clock, counted on falling edge 1 External clock, counted on both rising and falling edges Notes: 1. If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the 8TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. 2. If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is the 8TCNT2 compare match signal, no incrementing clock is generated. Do not use this setting. Rev. 3.00 Sep 14, 2005 page 397 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.2.5 Timer Control/Status Registers (8TCSR) 8TCSR0 Bit 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE OIS3 OIS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CMFB CMFA OVF -- OIS3 OIS2 OS1 OS0 8TCSR2 Bit Initial value 0 0 0 1 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* -- R/W R/W R/W R/W 6 5 4 3 2 1 0 8TCSR1, 8TCSR3 7 Bit CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W Note: * Only 0 can be written to bits 7 to 5, to clear these flags. The timer control/status registers 8TCSR are 8-bit registers that indicate compare match/input capture and overflow statuses, and control compare match output/input capture edge selection. 8TCSR2 is initialized to H'10, and 8TCSR0, 8TCSR1, and 8TCSR3 to H'00, by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 398 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Bit 7--Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the occurrence of a TCORB compare match or input capture. Bit 7 CMFB 0 1 Description [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB (Initial value) [Setting conditions] * 8TCNT = TCORB* * The 8TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register Note: * When bit ICE is set to 1 in 8TCSR1 and 8TCSR3, the CMFB flag is not set when 8TCNT0 = TCORB0 or 8TCNT2 = TCORB2. Bit 6--Compare Match Flag A (CMFA): Status flag that indicates the occurrence of a TCORA compare match. Bit 6 CMFA Description 0 [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA 1 [Setting condition] 8TCNT = TCORA (Initial value) Bit 5--Timer Overflow Flag (OVF): Status flag that indicates that the 8TCNT has overflowed from H'FF to H'00. Bit 5 OVF Description 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] 8TCNT overflows from H'FF to H'00 (Initial value) Rev. 3.00 Sep 14, 2005 page 399 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Bit 4--A/D Trigger Enable (ADTE) (In 8TCSR0): In combination with TRGE in the A/D control register (ADCR), enables or disables A/D converter start requests by compare match A or an external trigger. TRGE* Bit 4 ADTE 0 0 A/D converter start requests by compare match A or external trigger pin (ADTRG) input are disabled (Initial value) 1 A/D converter start requests by compare match A or external trigger pin (ADTRG) input are disabled 1 0 1 Description A/D converter start requests by external trigger pin (ADTRG) input are enabled, and A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled, and A/D converter start requests by external trigger pin (ADTRG) input are disabled Note: * TRGE is bit 7 of the A/D control register (ADCR). Bit 4--Reserved (In 8TCSR1): This bit is a reserved bit, but can be read and written. Bit 4--Input Capture Enable (ICE) (In 8TCSR1 and 8TCSR3): Selects the function of TCORB1 and TCORB3. Bit 4 ICE Description 0 TCORB1 and TCORB3 are compare match registers 1 TCORB1 and TCORB3 are input capture registers (Initial value) When bit ICE is set to 1 in 8TCSR1 or 8TCSR3, the operation of the TCORA and TCORB registers in channels 0 to 3 is as shown in the tables below. Rev. 3.00 Sep 14, 2005 page 400 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Table 10.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register Register Register Function Status Flag Change Timer Output Capture Input Interrupt Request TCORA0 Compare match CMFA changed from 0 TMO0 output controllable operation to 1 in 8TCSR0 by compare match CMIA0 interrupt request generated by compare match TCORB0 Compare match CMFB not changed No output from operation from 0 to 1 in 8TCSR0 TMO0 by compare match CMIB0 interrupt request not generated by compare match TCORA1 Compare match CMFA changed from 0 TMIO1 is operation to 1 in 8TCSR1 by dedicated input compare match capture pin CMIA1 interrupt request generated by compare match TCORB1 Input capture operation CMIB1 interrupt request generated by input capture CMFB changed from 0 TMIO1 is to 1 in 8TCSR1 by dedicated input input capture capture pin Table 10.4 Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register Register Register Function Status Flag Change Timer Output Capture Input Interrupt Request TCORA2 Compare match CMFA changed from 0 TMO2 output operation to 1 in 8TCSR2 by controllable compare match CMIA2 interrupt request generated by compare match TCORB2 Compare match CMFB not changed No output from operation from 0 to 1 in 8TCSR2 TMO2 by compare match CMIB2 interrupt request not generated by compare match TCORA3 Compare match CMFA changed from 0 TMIO3 is operation to 1 in 8TCSR3 by dedicated input compare match capture pin CMIA3 interrupt request generated by compare match TCORB3 Input capture operation CMIB3 interrupt request generated by input capture CMFB changed from 0 TMIO3 is to 1 in 8TCSR3 by dedicated input input capture capture pin Rev. 3.00 Sep 14, 2005 page 401 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Bits 3 and 2--Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the input capture input detected edge. The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3). ICE Bit in 8TCSR1 (8TCSR3) Bit 3 OIS3 Bit 2 OIS2 Description 0 0 0 No change when compare match B occurs 1 0 is output when compare match B occurs 0 1 is output when compare match B occurs 1 Output is inverted when compare match B occurs (toggle output) 0 TCORB input capture on rising edge 1 TCORB input capture on falling edge 0 TCORB input capture on both rising and falling edges 1 1 0 1 (Initial value) 1 * When the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. * If compare match A and B occur simultaneously, the output changes in accordance with the higher-priority compare match. * When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled. Bits 1 and 0--Output Select A1 and A0 (OS1, OS0): These bits select the compare match A output level. Bit 1 OS1 Bit 0 OS0 Description 0 0 No change when compare match A occurs 1 0 is output when compare match A occurs 0 1 is output when compare match A occurs 1 Output is inverted when compare match A occurs (toggle output) 1 (Initial value) * When the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. * If compare match A and B occur simultaneously, the output changes in accordance with the higher-priority compare match. * When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled. Rev. 3.00 Sep 14, 2005 page 402 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.3 CPU Interface 10.3.1 8-Bit Registers 8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time. Figures 10.2 and 10.3 show the operation in word read and write accesses to 8TCNT. Figures 10.4 to 10.7 show the operation in byte read and write accesses to 8TCNT0 and 8TCNT1. Internal data bus H C P U H Bus interface L L Module data bus 8TCNT0 8TCNT1 Figure 10.2 8TCNT Access Operation (CPU Writes to 8TCNT, Word) Internal data bus H C P U L H Bus interface L Module data bus 8TCNT0 8TCNT1 Figure 10.3 8TCNT Access Operation (CPU Reads 8TCNT, Word) Rev. 3.00 Sep 14, 2005 page 403 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Internal data bus H C P U L H Bus interface L Module data bus 8TCNTH0 8TCNTL1 Figure 10.4 8TCNT0 Access Operation (CPU Writes to 8TCNT0, Upper Byte) Internal data bus H C P U L H Bus interface L Module data bus 8TCNTH0 8TCNTL1 Figure 10.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte) Internal data bus H C P U L H Bus interface L Module data bus 8TCNT0 8TCNT1 Figure 10.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte) Internal data bus H C P U L H Bus interface L Module data bus 8TCNT0 8TCNT1 Figure 10.7 8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte) Rev. 3.00 Sep 14, 2005 page 404 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.4 Operation 10.4.1 8TCNT Count Timing 8TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (/8, /64, or /8192) divided from the system clock () can be selected, by setting bits CKS2 to CKS0 in 8TCR. Figure 10.8 shows the count timing. Internal clock 8TCNT input clock 8TCNT N-1 N N+1 Note: Even if the same internal clock is selected for the 16-bit timer and the 8-bit timer, the same operation will not be performed since the incrementing edge is different in each case. Figure 10.8 Count Timing for Internal Clock Input External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in 8TCR: on the rising edge, the falling edge, and both rising and falling edges. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly. Figure 10.9 shows the timing for incrementation on both edges of the external clock signal. Rev. 3.00 Sep 14, 2005 page 405 of 910 REJ09B0258-0300 Section 10 8-Bit Timers External clock input 8TCNT input clock 8TCNT N-1 N N+1 Figure 10.9 Count Timing for External Clock Input (Both-Edge Detection) 10.4.2 Compare Match Timing Timer Output Timing: When compare match A or B occurs, the timer output is as specified by the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output). Figure 10.10 shows the timing when the output is set to toggle on compare match A. Compare match A signal Timer output Figure 10.10 Timing of Timer Output Rev. 3.00 Sep 14, 2005 page 406 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR, 8TCNT can be cleared when compare match A or B occurs, Figure 10.11 shows the timing of this operation. Compare match signal 8TCNT N H'00 Figure 10.11 Timing of Clear by Compare Match Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR, 8TCNT can be cleared when input capture B occurs. Figure 10.12 shows the timing of this operation. Input capture input Input capture signal 8TCNT N H '00 Figure 10.12 Timing of Clear by Input Capture 10.4.3 Input Capture Signal Timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in 8TCSR. Figure 10.13 shows the timing when the rising edge is selected. The pulse width of the input capture input signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Rev. 3.00 Sep 14, 2005 page 407 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Input capture input Input capture signal 8TCNT N TCORB N Figure 10.13 Timing of Input Capture Input Signal 10.4.4 Timing of Status Flag Setting Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: The CMFA and CMFB flags in 8TCSR are set to 1 by the compare match signal output when the TCORA or TCORB and 8TCNT values match. The compare match signal is generated in the last state of the match (when the matched 8TCNT count value is updated). Therefore, after the 8TCNT and TCORA or TCORB values match, the compare match signal is not generated until an incrementing clock pulse signal is generated. Figure 10.14 shows the timing in this case. 8TCNT N TCOR N N+1 Compare match signal CMF Figure 10.14 CMF Flag Setting Timing when Compare Match Occurs Rev. 3.00 Sep 14, 2005 page 408 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture signal, the CMFB flag is set to 1 and at the same time the 8TCNT value is transferred to TCORB. Figure 10.15 shows the timing in this case. 8TCNT N TCORB N Input capture signal CMFB Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow signal generated when 8TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in this case. 8TCNT H'FF H'00 Overflow signal OVF Figure 10.16 Timing of OVF Setting 10.4.5 Operation with Cascaded Connection If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0 and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer (16-bit timer mode), or channel 0 8-bit timer compare matches can be counted in channel 1 (compare match count mode). Similarly, if bits CKS2 to CKS0 are set to (100) in either 8TCR2 Rev. 3.00 Sep 14, 2005 page 409 of 910 REJ09B0258-0300 Section 10 8-Bit Timers or 8TCR3, the 8-bit timers of channels 2 and 3 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer (16-bit timer mode),or channel 2 8-bit timer compare matches can be counted in channel 3 (compare match count mode). In this case, the timer operates as below. 16-Bit Count Mode * Channels 0 and 1: When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. Setting when Compare Match Occurs * The CMFA or CMFB flag is set to 1 in 8TCSR0 when a 16-bit compare match occurs. * The CMFA or CMFB flag is set to 1 in 8TCSR1 when a lower 8-bit compare match occurs. * TMO0 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in accordance with the 16-bit compare match conditions. * TMIO1 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in accordance with the lower 8-bit compare match conditions. Setting when Input Capture Occurs * The CMFB flag is set to 1 in 8TCSR0 and 8TCSR1 when the ICE bit is 1 in TCSR1 and input capture occurs. * TMIO1 pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in 8TCSR0. Counter Clear Specification * If counter clear on compare match or input capture has been selected by the CCLR1 and CCLR0 bits in 8TCR0, the 16-bit counter (both 8TCNT0 and 8TCNT1) is cleared. * The settings of the CCLR1 and CCLR0 bits in 8TCR1 are ignored. The lower 8 bits cannot be cleared independently. OVF Flag Operation * The OVF flag is set to 1 in 8TCSR0 when the 16-bit counter (8TCNT0 and 8TCNT1) overflows (from H'FFFF to H'0000). * The OVF flag is set to 1 in 8TCSR1 when the 8-bit counter (8TCNT1) overflows (from H'FF to H'00). Rev. 3.00 Sep 14, 2005 page 410 of 910 REJ09B0258-0300 Section 10 8-Bit Timers * Channels 2 and 3: When bits CKS2 to CKS0 are set to (100) in 8TCR2, the timer functions as a single 16-bit timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits. Setting when Compare Match Occurs * The CMFA or CMFB flag is set to 1 in 8TCSR2 when a 16-bit compare match occurs. * The CMFA or CMFB flag is set to 1 in 8TCSR3 when a lower 8-bit compare match occurs. * TMO2 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR2 is in accordance with the 16-bit compare match conditions. * TMIO3 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR3 is in accordance with the lower 8-bit compare match conditions. Setting when Input Capture Occurs * The CMFB flag is set to 1 in 8TCSR2 and 8TCSR3 when the ICE bit is 1 in TCSR3 and input capture occurs. * TMIO3 pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in 8TCSR2. Counter Clear Specification * If counter clear on compare match has been selected by the CCLR1 and CCLR0 bits in 8TCR2, the 16-bit counter (both 8TCNT2 and 8TCNT3) is cleared. * The settings of the CCLR1 and CCLR0 bits in 8TCR3 are ignored. The lower 8 bits cannot be cleared independently. OVF Flag Operation * The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3) overflows (from H'FFFF to H'0000). * The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from H'FF to H'00). Compare Match Count Mode * Channels 0 and 1: When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare match A events. CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in accordance with the settings for each channel. Note: When bit ICE = 1 in 8TCSR1, the compare match register function of TCORB0 in channel 0 cannot be used. Rev. 3.00 Sep 14, 2005 page 411 of 910 REJ09B0258-0300 Section 10 8-Bit Timers * Channels 2 and 3: When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare match A events. CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in accordance with the settings for each channel. Note: When bit ICE = 1 in 8TCSR3, the compare match register function of TCORB2 in channel 2 cannot be used. Caution Do not set 16-bit counter mode and compare match count mode simultaneously within the same group, as the 8TCNT input clock will not be generated and the counters will not operate. 10.4.6 Input Capture Setting The 8TCNT value can be transferred to TCORB on detection of an input edge on the input capture/output compare pin (TMIO1 or TMIO3). Rising edge, falling edge, or both edge detection can be selected. In 16-bit count mode, 16-bit input capture can be used. Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation) * Channel 1: Set TCORB1 as an 8-bit input capture register with the ICE bit in 8TCSR1. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR1. Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count. * Channel 3: Set TCORB3 as an 8-bit input capture register with the ICE bit in 8TCSR3. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR3. Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count. Note: When TCORB1 in channel 1 is used for input capture, TCORB0 in channel 0 cannot be used as a compare match register. Similarly, when TCORB3 in channel 3 is used for input capture, TCORB2 in channel 2 cannot be used as a compare match register. Rev. 3.00 Sep 14, 2005 page 412 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Setting Input Capture Operation in 16-Bit Count Mode * Channels 0 and 1: In 16-bit count mode, TCORB0 and TCORB1 function as a 16-bit input capture register when the ICE bit is set to 1 in 8TCSR1. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR0. (In 16-bit count mode, the settings of bits OIS3 and OIS2 in 8TCSR1 are ignored.) Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count. * Channels 2 and 3: In 16-bit count mode, TCORB2 and TCORB3 function as a 16-bit input capture register when the ICE bit is set to 1 in 8TCSR3. Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR2. (In 16-bit count mode, the settings of bits OIS3 and OIS2 in 8TCSR3 are ignored.) Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count. Rev. 3.00 Sep 14, 2005 page 413 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.5 Interrupt 10.5.1 Interrupt Sources The 8-bit timer unit can generate three types of interrupt: compare match A and B (CMIA and CMIB) and overflow (TOVI). Table 10.5 shows the interrupt sources and their priority order. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8TCR. A separate interrupt request signal is sent to the interrupt controller by each interrupt source. Table 10.5 Types of 8-Bit Timer Interrupt Sources and Priority Order Interrupt Source Description Priority CMIA Interrupt by CMFA High CMIB Interrupt by CMFB TOVI Interrupt by OVF Low For compare match interrupts CMIA1/CMIB1 and CMIA3/CMIB3 and the overflow interrupts (TOVI0/TOVI1 and TOVI2/TOVI3), one vector is shared by two interrupts. Table 10.6 lists the interrupt sources. Table 10.6 8-Bit Timer Interrupt Sources Channel Interrupt Source Description 0 CMIA0 TCORA0 compare match CMIB0 TCORB0 compare match/input capture 1 CMIA1/CMIB1 TCORA1 compare match, or TCORB1 compare match/input capture 0, 1 TOVI0/TOVI1 Counter 0 or counter 1 overflow 2 CMIA2 TCORA2 compare match CMIB2 TCORB2 compare match/input capture 3 CMIA3/CMIB3 TCORA3 compare match, or TCORB3 compare match/input capture 2, 3 TOVI2/TOVI3 Counter 2 or counter 3 overflow Rev. 3.00 Sep 14, 2005 page 414 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.5.2 A/D Converter Activation The A/D converter can only be activated by channel 0 compare match A. If the ADTE bit setting is 1 when the CMFA flag in 8TCSR0 is set to 1 by generation of channel 0 compare match A, an A/D conversion start request will be issued to the A/D converter. If the TRGE bit in ADCR is 1 at this time, the A/D converter will be started. If the ADTE bit in 8TCSR0 is 1, A/D converter external trigger pin (ADTRG) input is disabled. 10.6 8-Bit Timer Application Example Figure 10.17 shows how the 8-bit timer module can be used to output pulses with any desired duty cycle. The settings for this example are as follows: * Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1 in 8TCR so that 8TCNT is cleared by a TCORA compare match. * Set bits OIS3, OIS2, OS1, and OS0 to (0110) in 8TCSR so that 1 is output on a TCORA compare match and 0 is output on a TCORB compare match. The above settings enable a waveform with the cycle determined by TCORA and the pulse width detected by TCORB to be output without software intervention. 8TCNT H'FF Counter clear TCORA TCORB H'00 TMO Figure 10.17 Example of Pulse Output Rev. 3.00 Sep 14, 2005 page 415 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.7 Usage Notes Note that the following kinds of contention can occur in 8-bit timer operation. 10.7.1 Contention between 8TCNT Write and Clear If a timer counter clear signal occurs in the T3 state of a 8TCNT write cycle, clearing of the counter takes priority and the write is not performed. Figure 10.18 shows the timing in this case. 8TCNT write cycle T1 T2 T3 Address bus 8TCNT address Internal write signal Counter clear signal 8TCNT N H'00 Figure 10.18 Contention between 8TCNT Write and Clear Rev. 3.00 Sep 14, 2005 page 416 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.7.2 Contention between 8TCNT Write and Increment If an increment pulse occurs in the T3 state of a 8TCNT write cycle, writing takes priority and 8TCNT is not incremented. Figure 10.19 shows the timing in this case. 8TCNT write cycle T1 T2 T3 Address bus 8 TCNT address Internal write signal 8TCNT input clock 8TCNT N M 8TCNT write data Figure 10.19 Contention between 8TCNT Write and Increment Rev. 3.00 Sep 14, 2005 page 417 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.7.3 Contention between TCOR Write and Compare Match If a compare match occurs in the T3 state of a TCOR write cycle, writing takes priority and the compare match signal is inhibited. Figure 10.20 shows the timing in this case. TCOR write cycle T1 T2 T3 TCOR address Address bus Internal write signal 8TCNT N TCOR N N+1 M TCOR write data Compare match signal Figure 10.20 Contention between TCOR Write and Compare Match Rev. 3.00 Sep 14, 2005 page 418 of 910 REJ09B0258-0300 Inhibited Section 10 8-Bit Timers 10.7.4 Contention between TCOR Read and Input Capture If an input capture signal occurs in the T3 state of a TCOR read cycle, the value before input capture is read. Figure 10.21 shows the timing in this case. TCORB read cycle T1 T2 T3 Address bus TCORB address Internal read signal Input capture signal TCORB Internal data bus N M N Figure 10.21 Contention between TCOR Read and Input Capture Rev. 3.00 Sep 14, 2005 page 419 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.7.5 Contention between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. The value before the counter is cleared is transferred to TCORB. Figure 10.22 shows the timing in this case. T1 T2 T3 Input capture signal Counter clear signal 8TCNT internal clock 8TCNT N TCORB X H'00 N Figure 10.22 Contention between Counter Clearing by Input Capture and Counter Increment Rev. 3.00 Sep 14, 2005 page 420 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.7.6 Contention between TCOR Write and Input Capture If an input capture signal occurs in the T3 state of a TCOR write cycle, input capture takes priority and the write to TCOR is not performed. Figure 10.23 shows the timing in this case. TCOR write cycle T1 T2 T3 Address bus TCOR address Internal write signal Input capture signal M 8TCNT TCOR X M Figure 10.23 Contention between TCOR Write and Input Capture Rev. 3.00 Sep 14, 2005 page 421 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection) If an increment pulse occurs in the T3 state of an 8TCNT byte write cycle in 16-bit count mode, the counter write takes priority and the byte data for which the write was performed is not incremented. The byte data for which a write was not performed is incremented. Figure 10.24 shows the timing when an increment pulse occurs in the T2 state of a byte write to 8TCNT (upper byte). If an increment pulse occurs in the T2 state, on the other hand, the increment takes priority. 8TCNT (upper byte) byte write cycle T1 T2 T3 8TCNTH address Address bus Internal write signal 8TCNT input clock 8TCNT (upper byte) N 8TCNT (lower byte) X N+1 8TCNT write data X+1 Figure 10.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode Rev. 3.00 Sep 14, 2005 page 422 of 910 REJ09B0258-0300 Section 10 8-Bit Timers 10.7.8 Contention between Compare Matches A and B If compare matches A and B occur at the same time, the 8-bit timer operates according to the relative priority of the output states set for compare match A and compare match B, as shown in Table 10.7. Table 10.7 Timer Output Priority Order Output Setting Priority Toggle output High 1 output 0 output No change 10.7.9 Low 8TCNT Operation and Internal Clock Source Switchover Switching internal clock sources may cause 8TCNT to increment, depending on the switchover timing. Table 10.8 shows the relation between the time of the switchover (by writing to bits CKS1 and CKS0) and the operation of 8TCNT. The 8TCNT input clock is generated from the internal clock source by detecting the rising edge of the internal clock. If a switchover is made from a low clock source to a high clock source, as in case No. 3 in Table 10.8, the switchover will be regarded as a falling edge, a 8TCNT clock pulse will be generated, and 8TCNT will be incremented. 8TCNT may also be incremented when switching between internal and external clocks. Rev. 3.00 Sep 14, 2005 page 423 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Table 10.8 Internal Clock Switchover and 8TCNT Operation No. CKS1 and CKS0 Write Timing 1 High high switchover* 8TCNT Operation 1 Old clock source New clock source 8TCNT clock 8TCNT N N+1 CKS bits rewritten 2 High low switchover* 2 Old clock source New clock source 8TCNT clock 8TCNT N N+1 N+2 CKS bits rewritten 3 Low high switchover* 3 Old clock source New clock source *4 8TCNT clock 8TCNT N N+1 CKS bits rewritten Rev. 3.00 Sep 14, 2005 page 424 of 910 REJ09B0258-0300 N+2 Section 10 8-Bit Timers No. CKS1 and CKS0 Write Timing 4 Low low switchover* 8TCNT Operation 4 Old clock source New clock source 8TCNT clock 8TCNT N N+1 N+2 CKS bits rewritten Notes: 1. Including switchovers from the high level to the halted state, and from the halted state to the high level. 2. Including switchover from the halted state to the low level. 3. Including switchover from the low level to the halted state. 4. The switchover is regarded as a rising edge, causing 8TCNT to increment. Rev. 3.00 Sep 14, 2005 page 425 of 910 REJ09B0258-0300 Section 10 8-Bit Timers Rev. 3.00 Sep 14, 2005 page 426 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) Section 11 Programmable Timing Pattern Controller (TPC) 11.1 Overview The H8/3068F has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently. 11.1.1 Features TPC features are listed below. * 16-bit output data Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis. * Four output groups Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. * Selectable output trigger signals Output trigger signals can be selected for each group from the compare match signals of three 16-bit timer channels. * Non-overlap mode A non-overlap margin can be provided between pulse outputs. * Can operate together with the DMA controller (DMAC) The compare-match signals selected as trigger signals can activate the DMAC for sequential output of data without CPU intervention. Rev. 3.00 Sep 14, 2005 page 427 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the TPC. 16-bit timer compare match signals Control logic TP 15 TP 14 TP 13 TP 12 TP 11 TP 10 TP 9 TP 8 TP 7 TP 6 TP 5 TP 4 TP 3 TP 2 TP 1 TP 0 Legend TPMR: TPCR: NDERB: NDERA: PBDDR: PADDR: NDRB: NDRA: PBDR: PADR: PADDR PBDDR NDERA NDERB TPMR TPCR Internal data bus Pulse output pins, group 3 PBDR NDRB PADR NDRA Pulse output pins, group 2 Pulse output pins, group 1 Pulse output pins, group 0 TPC output mode register TPC output control register Next data enable register B Next data enable register A Port B data direction register Port A data direction register Next data register B Next data register A Port B data register Port A data register Figure 11.1 TPC Block Diagram Rev. 3.00 Sep 14, 2005 page 428 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.1.3 TPC Pins Table 11.1 summarizes the TPC output pins. Table 11.1 TPC Pins Name Symbol I/O Function TPC output 0 TP0 Output Group 0 pulse output TPC output 1 TP1 Output TPC output 2 TP2 Output TPC output 3 TP3 Output TPC output 4 TP4 Output TPC output 5 TP5 Output TPC output 6 TP6 Output TPC output 7 TP7 Output TPC output 8 TP8 Output TPC output 9 TP9 Output TPC output 10 TP10 Output TPC output 11 TP11 Output TPC output 12 TP12 Output TPC output 13 TP13 Output TPC output 14 TP14 Output TPC output 15 TP15 Output Group 1 pulse output Group 2 pulse output Group 3 pulse output Rev. 3.00 Sep 14, 2005 page 429 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.1.4 Registers Table 11.2 summarizes the TPC registers. Table 11.2 TPC Registers Address*1 Name Abbreviation R/W H'EE009 Port A data direction register PADDR W Function H'00 2 H'FFFD9 Port A data register PADR R/(W)* H'00 H'EE00A Port B data direction register PBDDR W H'00 2 H'FFFDA Port B data register PBDR R/(W)* H'00 H'FFFA0 TPC output mode register TPMR R/W H'F0 H'FFFA1 TPC output control register TPCR R/W H'FF H'FFFA2 Next data enable register B NDERB R/W H'00 H'FFFA3 Next data enable register A NDERA R/W H'00 H'FFFA5/ H'FFFA7*3 Next data register A NDRA R/W H'00 H'FFFA4/ 3 H'FFFA6* Next data register B NDRB R/W H'00 Notes: 1. Lower 20 bits of the address in advanced mode. 2. Bits used for TPC output cannot be written. 3. The NDRA address is H'FFFA5 when the same output trigger is selected for TPC output groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA address is H'FFFA7 for group 0 and H'FFFA5 for group 1. Similarly, the address of NDRB is H'FFFA4 when the same output trigger is selected for TPC output groups 2 and 3 by settings in TPCR. When the output triggers are different, the NDRB address is H'FFFA6 for group 2 and H'FFFA4 for group 3. Rev. 3.00 Sep 14, 2005 page 430 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.2 Register Descriptions 11.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. Bit 7 6 5 4 3 2 1 0 PA7 DDR PA6 DDR PA5 DDR PA4 DDR PA3 DDR PA2 DDR PA1 DDR PA0 DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port A data direction 7 to 0 These bits select input or output for port A pins Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must be set to 1. For further information about PADDR, see section 8.11, Port A. 11.2.2 Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when these TPC output groups are used. Bit 7 6 5 4 3 2 1 0 PA 7 PA 6 PA 5 PA 4 PA 3 PA 2 PA 1 PA 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Port A data 7 to 0 These bits store output data for TPC output groups 0 and 1 Note: * Bits selected for TPC output by NDERA settings become read-only bits. For further information about PADR, see section 8.11, Port A. Rev. 3.00 Sep 14, 2005 page 431 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. Bit 7 6 5 4 3 2 1 0 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port B direction 7 to 0 These bits select input or output for port B pins Port B is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must be set to 1. For further information about PBDDR, see section 8.12, Port B. 11.2.4 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when these TPC output groups are used. Bit 7 PB7 6 5 4 3 2 1 0 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Port B data 7 to 0 These bits store output data for TPC output groups 2 and 3 Note: * Bits selected for TPC output by NDERB settings become read-only bits. For further information about PBDR, see section 8.12, Port B. Rev. 3.00 Sep 14, 2005 page 432 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP7 to TP0). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or different output triggers. NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by the same compare match event, the NDRA address is H'FFFA5. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FFFA7 consists entirely of reserved bits that cannot be modified and always read 1. Address H'FFFA5 Bit 6 7 NDR7 NDR6 5 NDR5 4 NDR4 2 3 NDR3 NDR2 1 NDR1 0 NDR0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Next data 7 to 4 These bits store the next output data for TPC output group 1 Next data 3 to 0 These bits store the next output data for TPC output group 0 Address H'FFFA7 Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Reserved bits Rev. 3.00 Sep 14, 2005 page 433 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5 and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits 7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1. Address H'FFFA5 Bit 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 -- -- -- -- Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W -- -- -- -- Next data 7 to 4 These bits store the next output data for TPC output group 1 Reserved bits Address H'FFFA7 Bit 7 6 5 4 3 2 1 0 -- -- -- -- NDR3 NDR2 NDR1 NDR0 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W Reserved bits Rev. 3.00 Sep 14, 2005 page 434 of 910 REJ09B0258-0300 Next data 3 to 0 These bits store the next output data for TPC output group 0 Section 11 Programmable Timing Pattern Controller (TPC) 11.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP15 to TP8). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or different output triggers. NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by the same compare match event, the NDRB address is H'FFFA4. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FFFA6 consists entirely of reserved bits that cannot be modified and always read 1. Address H'FFFA4 Bit 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Next data 15 to 12 These bits store the next output data for TPC output group 3 Next data 11 to 8 These bits store the next output data for TPC output group 2 Address H'FFFA6 Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Reserved bits Rev. 3.00 Sep 14, 2005 page 435 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4 and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits 7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1. Address H'FFFA4 Bit 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 -- -- -- -- Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W -- -- -- -- Next data 15 to 12 These bits store the next output data for TPC output group 3 Reserved bits Address H'FFFA6 Bit 7 6 5 4 3 2 1 0 -- -- -- -- NDR11 NDR10 NDR9 NDR8 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W Reserved bits Rev. 3.00 Sep 14, 2005 page 436 of 910 REJ09B0258-0300 Next data 11 to 8 These bits store the next output data for TPC output group 2 Section 11 Programmable Timing Pattern Controller (TPC) 11.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis. Bit 6 7 NDER7 4 5 NDER6 NDER5 3 NDER4 NDER3 2 NDER2 1 0 NDER1 NDER0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Next data enable 7 to 0 These bits enable or disable TPC output groups 1 and 0 If a bit is enabled for TPC output by NDERA, then when the 16-bit timer compare match event selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRA to PADR and the output value does not change. NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis. Bits 7 to 0 NDER7 to NDER0 Description 0 TPC outputs TP7 to TP0 are disabled (NDR7 to NDR0 are not transferred to PA7 to PA0) 1 TPC outputs TP7 to TP0 are enabled (NDR7 to NDR0 are transferred to PA7 to PA0) (Initial value) Rev. 3.00 Sep 14, 2005 page 437 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis. Bit 7 6 4 5 3 2 1 0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Next data enable 15 to 8 These bits enable or disable TPC output groups 3 and 2 If a bit is enabled for TPC output by NDERB, then when the 16-bit timer compare match event selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically transferred to the corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRB to PBDR and the output value does not change. NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis. Bits 7 to 0 NDER15 to NDER8 Description 0 TPC outputs TP15 to TP8 are disabled (NDR15 to NDR8 are not transferred to PB7 to PB0) 1 TPC outputs TP15 to TP8 are enabled (NDR15 to NDR8 are transferred to PB7 to PB0) Rev. 3.00 Sep 14, 2005 page 438 of 910 REJ09B0258-0300 (Initial value) Section 11 Programmable Timing Pattern Controller (TPC) 11.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. Bit 7 6 5 4 3 2 1 0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare event that triggers match select 1 and 0 TPC output group 3 These bits select (TP15 to TP12) the compare match Group 1 compare event that triggers TPC output group 2 match select 1 and 0 These bits select (TP11 to TP8) the compare match Group 0 compare event that triggers match select 1 and 0 TPC output group 1 These bits select (TP7 to TP4) the compare match event that triggers TPC output group 0 (TP3 to TP0) TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 3.00 Sep 14, 2005 page 439 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) Bits 7 and 6--Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP15 to TP12). Bit 7 G3CMS1 Bit 6 G3CMS0 0 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16bit timer channel 0 1 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16bit timer channel 1 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16bit timer channel 2 1 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 2 1 Description (Initial value) Bits 5 and 4--Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match event that triggers TPC output group 2 (TP11 to TP8). Bit 5 G2CMS1 Bit 4 G2CMS0 0 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 0 1 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 1 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 2 1 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 2 1 Description Rev. 3.00 Sep 14, 2005 page 440 of 910 REJ09B0258-0300 (Initial value) Section 11 Programmable Timing Pattern Controller (TPC) Bits 3 and 2--Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP7 to TP4). Bit 3 G1CMS1 Bit 2 G1CMS0 0 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 0 1 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 1 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 2 1 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 2 1 Description (Initial value) Bits 1 and 0--Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare match event that triggers TPC output group 0 (TP3 to TP0). Bit 1 G0CMS1 Bit 0 G0CMS0 0 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 0 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 1 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 2 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 2 1 Description (Initial value) Rev. 3.00 Sep 14, 2005 page 441 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. Bit 7 6 5 4 -- -- -- -- Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W 3 2 G3NOV G2NOV 1 0 G1NOV G0NOV Reserved bits Group 3 non-overlap Selects non-overlapping TPC output for group 3 (TP15 to TP12 ) Group 2 non-overlap Selects non-overlapping TPC output for group 2 (TP11 to TP8 ) Group 1 non-overlap Selects non-overlapping TPC output for group 1 (TP7 to TP4 ) Group 0 non-overlap Selects non-overlapping TPC output for group 0 (TP3 to TP0 ) The output trigger period of a non-overlapping TPC output waveform is set in general register B (GRB) in the 16-bit timer channel selected for output triggering. The non-overlap margin is set in general register A (GRA). The output values change at compare match A and B. For details see section 11.3.4, Non-Overlapping TPC Output. TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Rev. 3.00 Sep 14, 2005 page 442 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) Bit 3--Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP15 to TP12). Bit 3 G3NOV Description 0 Normal TPC output in group 3 (output values change at compare match A in the selected 16-bit timer channel) 1 Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value) Bit 2--Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for group 2 (TP11 to TP8). Bit 2 G2NOV Description 0 Normal TPC output in group 2 (output values change at compare match A in the selected 16-bit timer channel) 1 Non-overlapping TPC output in group 2 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value) Bit 1--Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for group 1 (TP7 to TP4). Bit 1 G1NOV Description 0 Normal TPC output in group 1 (output values change at compare match A in the selected 16-bit timer channel) 1 Non-overlapping TPC output in group 1 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value) Bit 0--Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for group 0 (TP3 to TP0). Bit 0 G0NOV Description 0 Normal TPC output in group 0 (output values change at compare match A in the selected 16-bit timer channel) 1 Non-overlapping TPC output in group 0 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) (Initial value) Rev. 3.00 Sep 14, 2005 page 443 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.3 Operation 11.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values. Figure 11.2 illustrates the TPC output operation. Table 11.3 summarizes the TPC operating conditions. DDR NDER Q Q Output trigger signal C Q DR D Q NDR D Internal data bus TPC output pin Figure 11.2 TPC Output Operation Table 11.3 TPC Operating Conditions NDER DDR Pin Function 0 0 Generic input port 1 Generic output port 0 Generic input port (but the DR bit is a read-only bit, and when compare match occurs, the NDR bit value is transferred to the DR bit) 1 TPC pulse output 1 Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and NDRB before the next compare match. For information on non-overlapping operation, see section 11.3.4, Non-Overlapping TPC Output. Rev. 3.00 Sep 14, 2005 page 444 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. N TCNT N+1 N GRA Compare match A signal n NDRB PBDR m n TP8 to TP15 m n Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example) Rev. 3.00 Sep 14, 2005 page 445 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 11.4 shows a sample procedure for setting up normal TPC output. Normal TPC output 16-bit timer setup Port and TPC setup 16-bit timer setup Select GR functions 1 Set GRA value 2 Select counting operation 3 Select interrupt request 4 Set initial output data 5 Select port output 6 Enable TPC output 7 Select TPC output trigger 8 Set next TPC output data 9 Start counter 10 Compare match? 1. Set TIOR to make GRA an output compare register (with output inhibited). 2. Set the TPC output trigger period. 3. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. 4. Enable the IMFA interrupt in TIER. The DMAC can also be set up to transfer data to the next data register. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1. 8. Select the 16-bit timer compare match event to be used as the TPC output trigger in TPCR. 9. Set the next TPC output values in the NDR bits. 10. Set the STR bit to 1 in TSTR to start the timer counter. 11. At each IMFA interrupt, set the next output values in the NDR bits. No Yes Set next TPC output data 11 Figure 11.4 Setup Procedure for Normal TPC Output (Example) Rev. 3.00 Sep 14, 2005 page 446 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT GRA H'0000 Time NDRB 80 PBDR 00 C0 80 40 C0 60 40 20 60 30 20 10 30 18 10 08 18 88 08 80 88 C0 80 40 C0 TP15 TP14 TP13 TP12 TP11 * * * * The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A. The trigger period is set in GRA. The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt. H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Output data H'80 is written in NDRB. The timer counter in this 16-bit timer channel is started. When compare match A occurs, the NDRB contents are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt service routine writes the next output data (H'C0) in NDRB. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be obtained without loading the CPU. Figure 11.5 Normal TPC Output Example (Five-Phase Pulse Output) Rev. 3.00 Sep 14, 2005 page 447 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11.6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output 16-bit timer setup Port and TPC setup 16-bit timer setup Select GR functions 1 Set GR values 2 Select counting operation 3 Select interrupt requests 4 Set initial output data 5 Set up TPC output 6 Enable TPC transfer 7 Select TPC transfer trigger 8 Select non-overlapping groups 9 Set next TPC output data 10 Start counter 11 Compare match A? 1. Set TIOR to make GRA and GRB output compare registers (with output inhibited). 2. Set the TPC output trigger period in GRB and the non-overlap margin in GRA. 3. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. 4. Enable the IMFA interrupt in TISRA. The DMAC can also be set up to transfer data to the next data register. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1. 8. In TPCR, select the 16-bit timer compare match event to be used as the TPC output trigger. 9. In TPMR, select the groups that will operate in non-overlap mode. 10. Set the next TPC output values in the NDR bits. 11. Set the STR bit to 1 in TSTR to start the timer counter. 12. At each IMFA interrupt, write the next output value in the NDR bits. No Yes Set next TPC output data 12 Figure 11.6 Setup Procedure for Non-Overlapping TPC Output (Example) Rev. 3.00 Sep 14, 2005 page 448 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value GRB TCNT GRA H'0000 Time NDRB 95 PBDR 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 65 Non-overlap margin TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 * The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B. The TPC output trigger period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TISRA to enable IMFA interrupts. * H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in NDRB. * The timer counter in this 16-bit timer channel is started. When compare match B occurs, outputs change from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB. * Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95... at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be obtained without loading the CPU. Figure 11.7 Non-Overlapping TPC Output Example (Four-Phase Complementary Non-Overlapping Pulse Output) Rev. 3.00 Sep 14, 2005 page 449 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output will be triggered by the input capture signal. Figure 11.8 shows the timing. TIOC pin Input capture signal N NDR M DR N Figure 11.8 TPC Output Triggering by Input Capture (Example) Rev. 3.00 Sep 14, 2005 page 450 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) 11.4 Usage Notes 11.4.1 Operation of TPC Output Pins TP0 to TP15 are multiplexed with 16-bit timer, DMAC, address bus, and other pin functions. When 16-bit timer, DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin. Pin functions should be changed only under conditions in which the output trigger event will not occur. 11.4.2 Note on Non-Overlapping Output During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as follows. 1. NDR bits are always transferred to DR bits at compare match A. 2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11.9 illustrates the non-overlapping TPC output operation. DDR NDER Q Q Compare match A Compare match B C Q DR D Q NDR D TPC output pin Figure 11.9 Non-Overlapping TPC Output Rev. 3.00 Sep 14, 2005 page 451 of 910 REJ09B0258-0300 Section 11 Programmable Timing Pattern Controller (TPC) Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR, or by having the IMFA interrupt activate the DMAC. The next data must be written before the next compare match B occurs. Figure 11.10 shows the timing relationships. Compare match A Compare match B NDR write NDR write NDR DR 0 output 0/1 output 0 output Write to NDR in this interval Do not write to NDR in this interval 0/1 output Write to NDR in this interval Do not write to NDR in this interval Figure 11.10 Non-Overlapping Operation and NDR Write Timing Rev. 3.00 Sep 14, 2005 page 452 of 910 REJ09B0258-0300 Section 12 Watchdog Timer Section 12 Watchdog Timer 12.1 Overview The H8/3068F has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer. As a watchdog timer, it generates a reset signal for the H8/3068F chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an interval timer interrupt is requested at each TCNT overflow. 12.1.1 Features WDT features are listed below. * Selection of eight counter clock sources /2, /32, /64, /128, /256, /512, /2048, or /4096 * Interval timer option * Timer counter overflow generates a reset signal or interrupt. The reset signal is generated in watchdog timer operation. An interval timer interrupt is generated in interval timer operation. * Watchdog timer reset signal resets the entire H8/3068F internally. The reset signal generated by timer counter overflow during watchdog timer operation resets the entire H8/3068F internally. Rev. 3.00 Sep 14, 2005 page 453 of 910 REJ09B0258-0300 Section 12 Watchdog Timer 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the WDT. Overflow TCNT Interrupt signal (interval timer) Interrupt control TCSR Reset control Internal data bus Internal clock sources /2 RSTCSR Reset (internal, external) Read/ write control /32 /64 Clock Clock selector /128 /256 /512 Legend TCNT: Timer counter TCSR: Timer control/status register RSTCSR: Reset control/status register /2048 /4096 Figure 12.1 WDT Block Diagram 12.1.3 Register Configuration Table 12.1 summarizes the WDT registers. Table 12.1 WDT Registers Address*1 Write*2 Read Name H'FFF8C H'FFF8C Timer control/status register H'FFF8D Timer counter H'FFF8E H'FFF8F Reset control/status register Abbreviation R/W TCSR R/(W)*3 H'18 TCNT R/W RSTCSR Notes: 1. Lower 20 bits of the address in advanced mode. 2. Write word data starting at this address. 3. Only 0 can be written in bit 7, to clear the flag. Rev. 3.00 Sep 14, 2005 page 454 of 910 REJ09B0258-0300 Initial Value H'00 R/(W)* 3 H'3F Section 12 Watchdog Timer 12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable and writable up-counter. Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register Access. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. Rev. 3.00 Sep 14, 2005 page 455 of 910 REJ09B0258-0300 Section 12 Watchdog Timer 12.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and clock source. Bit 7 6 5 4 3 2 1 0 OVF WT/IT TME -- -- CKS2 CKS1 CKS0 Initial value 0 0 0 1 1 0 0 0 Read/Write R/(W)* R/W R/W -- -- R/W R/W R/W Clock select These bits select the TCNT clock source Reserved bits Timer enable Selects whether TCNT runs or halts Timer mode select Selects the mode Overflow flag Status flag indicating overflow Notes: TCSR is write-protected by a password. For details see section 12.2.4, Notes on Register Access. * Only 0 can be written, to clear the flag. Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values. Rev. 3.00 Sep 14, 2005 page 456 of 910 REJ09B0258-0300 Section 12 Watchdog Timer Bit 7--Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed from H'FF to H'00. Bit 7 OVF 0 1 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 in OVF (Initial value) [Setting condition] Set when TCNT changes from H'FF to H'00 Bit 6--Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when TCNT overflows. Bit 6 WT/IT Description 0 Interval timer: requests interval timer interrupts 1 Watchdog timer: generates a reset signal (Initial value) Bit 5--Timer Enable (TME): Selects whether TCNT runs or is halted. When WT/IT = 1, clear the software standby bit (SSBY) to 0 in SYSCR before setting TME. When setting SSBY to 1, TME should be cleared to 0. Bit 5 TME Description 0 TCNT is initialized to H'00 and halted 1 TCNT is counting (Initial value) Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 1. Rev. 3.00 Sep 14, 2005 page 457 of 910 REJ09B0258-0300 Section 12 Watchdog Timer Bits 2 to 0--Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources, obtained by prescaling the system clock (), for input to TCNT. Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Description 0 0 0 /2 1 /32 0 /64 1 /128 0 /256 1 /512 0 /2048 1 /4096 1 1 0 1 12.2.3 (Initial value) Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal. Bit 7 6 5 4 3 2 1 0 WRST -- -- -- -- -- -- -- Initial value 0 0 1 1 1 1 1 1 Read/Write R/(W)* R/W -- -- -- -- -- -- Reserved bits Watchdog timer reset Indicates that a reset signal has been generated Notes: RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on Register Access. * Only 0 can be written in bit 7, to clear the flag. Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by reset signals generated by watchdog timer overflow. Rev. 3.00 Sep 14, 2005 page 458 of 910 REJ09B0258-0300 Section 12 Watchdog Timer Bit 7--Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3068F chip internally. Bit 7 WRST 0 1 Description [Clearing condition] Reset signal at RES pin. Read WRST when WRST =1, then write 0 in WRST. (Initial value) [Setting condition] Set when TCNT overflow generates a reset signal during watchdog timer operation Bit 6--Reserved Bits 5 to 0--Reserved: These bits cannot be modified and are always read as 1. 12.2.4 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte instructions. Figure 12.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT or TCSR. 15 TCNT write Address H'FFF8C* H'5A H'FFF8C* 0 Write data 15 TCSR write Address 8 7 8 7 H'A5 0 Write data Note: * Lower 20 bits of the address in advanced mode. Figure 12.2 Format of Data Written to TCNT and TCSR Rev. 3.00 Sep 14, 2005 page 459 of 910 REJ09B0258-0300 Section 12 Watchdog Timer Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 12.3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. The data (H'00) in the lower byte is written to RSTCSR, clearing the WRST bit to 0. To write to the RSTOE bit, the upper byte must contain H'5A and the lower byte must contain the write data. Writing this word transfers a write data value into the RSTOE bit. Writing 0 in WRST bit Address H'FFF8E* Writing to RSTOE bit Address 15 8 7 H'A5 15 H'FFF8E* 0 H'00 8 7 H'5A 0 Write data Note: * Lower 20 bits of the address in advanced mode. Figure 12.3 Format of Data Written to RSTCSR Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Byte transfer instructions can be used. The read addresses are H'FFF8C for TCSR, H'FFF8D for TCNT, and H'FFF8F for RSTCSR, as listed in table 12.2. Table 12.2 Read Addresses of TCNT, TCSR, and RSTCSR Address* Register H'FFF8C TCSR H'FFF8D TCNT H'FFF8F RSTCSR Note: * Lower 20 bits of the address in advanced mode. Rev. 3.00 Sep 14, 2005 page 460 of 910 REJ09B0258-0300 Section 12 Watchdog Timer 12.3 Operation Operations when the WDT is used as a watchdog timer and as an interval timer are described below. 12.3.1 Watchdog Timer Operation Figure 12.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows due to a system crash etc., the H8/3068F is internally reset for a duration of 518 states. A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR. If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority. WDT overflow H'FF TME set to 1 TCNT count value H'00 OVF = 1 Start Internal reset signal H'00 written in TCNT Reset H'00 written in TCNT 518 states Figure 12.4 Operation in Watchdog Timer Mode Rev. 3.00 Sep 14, 2005 page 461 of 910 REJ09B0258-0300 Section 12 Watchdog Timer 12.3.2 Interval Timer Operation Figure 12.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each TCNT overflow. This function can be used to generate interval timer interrupts at regular intervals. H'FF TCNT count value Time t H'00 WT/ IT = 0 TME = 1 Interval timer interrupt Interval timer interrupt Interval timer interrupt Interval timer interrupt Figure 12.5 Interval Timer Operation Rev. 3.00 Sep 14, 2005 page 462 of 910 REJ09B0258-0300 Section 12 Watchdog Timer 12.3.3 Timing of Setting of Overflow Flag (OVF) Figure 12.6 shows the timing of setting of the OVF flag. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation. TCNT H'FF H'00 Overflow signal OVF Figure 12.6 Timing of Setting of OVF Rev. 3.00 Sep 14, 2005 page 463 of 910 REJ09B0258-0300 Section 12 Watchdog Timer 12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR. Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is generated for the entire H8/3068F chip. This internal reset signal clears OVF to 0, but the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit. H'FF TCNT H'00 Overflow signal OVF WDT internal reset WRST Figure 12.7 Timing of Setting of WRST Bit and Internal Reset Rev. 3.00 Sep 14, 2005 page 464 of 910 REJ09B0258-0300 Section 12 Watchdog Timer 12.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. 12.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not incremented. See figure 12.8. CPU: TCNT write cycle T1 T2 T3 TCNT Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.8 Contention between TCNT Write and Count up Changing CKS2 to CKS0 Bit: Halt TCNT by clearing the TME bit to 0 in TCSR before changing the values of bits CKS2 to CKS0. Rev. 3.00 Sep 14, 2005 page 465 of 910 REJ09B0258-0300 Section 12 Watchdog Timer Rev. 3.00 Sep 14, 2005 page 466 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Section 13 Serial Communication Interface 13.1 Overview The H8/3068F has a serial communication interface (SCI) with three independent channels. All three channels have identical functions. The SCI can communicate in both asynchronous and synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors. When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted independently. For details, see section 20.6, Module Standby Function. The SCI also has a smart card interface function conforming to the ISO/IEC 7816-3 (Identification Card) standard. This function supports serial communication with a smart card. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 13.1.1 Features SCI features are listed below. * Selection of synchronous or asynchronous mode for serial communication Asynchronous mode Serial data communication is synchronized one channel at a time. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), asynchronous communication interface adapter (ACIA), or other chip that employs standard asynchronous communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data transfer formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: even/odd/none Multiprocessor bit: 1 or 0 Receive error detection: parity, overrun, and framing errors Break detection: by reading the RxD level directly when a framing error occurs Rev. 3.00 Sep 14, 2005 page 467 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is a single serial data communication format. Data length: 8 bits Receive error detection: overrun errors * Full-duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. * The following settings can be made for the serial data to be transferred: LSB-first or MSB-first transfer Inversion of data logic level * Built-in baud rate generator with selectable bit rates * Selectable transmit/receive clock sources: internal clock from baud rate generator, or external clock from the SCK pin * Four types of interrupts Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts from SCI0 can activate the DMA controller (DMAC) to transfer data. Features of the smart card interface are listed below. * Asynchronous communication Data length: 8 bits Parity bits generated and checked Error signal output in receive mode (parity error) Error signal detect and automatic data retransmit in transmit mode Supports both direct convention and inverse convention * Built-in baud rate generator with selectable bit rates * Three types of interrupts Transmit-data-empty, receive-data-full, and transmit/receive-error interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can activate the DMA controller (DMAC) to transfer data. Rev. 3.00 Sep 14, 2005 page 468 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 13.1.2 Block Diagram Bus interface Figure 13.1 shows a block diagram of the SCI. Module data bus RDR TDR SSR BRR SCR RxD TxD RSR TSR SMR Baud rate generator SCMR Transmit/receive control Parity generate Parity check SCK Internal data bus / 4 /16 /64 Clock External clock TEI TXI RXI ERI Legend RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register BRR : Bit rate register SCMR : Smart card mode register Figure 13.1 SCI Block Diagram Rev. 3.00 Sep 14, 2005 page 469 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 13.1.3 Input/Output Pins The SCI has serial pins for each channel as listed in table 13.1. Table 13.1 SCI Pins Channel Name Abbreviation I/O Function 0 SCK0 Input/output SCI0 clock input/output Receive data pin RxD0 Input SCI0 receive data input Transmit data pin TxD0 Output SCI0 transmit data output Serial clock pin SCK1 Input/output SCI1 clock input/output Receive data pin RxD1 Input SCI1 receive data input Transmit data pin TxD1 Output SCI1 transmit data output Serial clock pin SCK2 Input/output SCI2 clock input/output Receive data pin RxD2 Input SCI2 receive data input Transmit data pin TxD2 Output SCI2 transmit data output 1 2 Serial clock pin Rev. 3.00 Sep 14, 2005 page 470 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 13.1.4 Register Configuration The SCI has internal registers as listed in table 13.2. These registers select asynchronous or synchronous mode, specify the data format and bit rate, control the transmitter and receiver sections, and specify switching between the serial communication interface and smart card interface. Table 13.2 SCI Registers Channel Address*1 Name Abbreviation R/W Initial Value 0 H'FFFB0 Serial mode register SMR R/W H'00 H'FFFB1 Bit rate register BRR R/W H'FF H'FFFB2 Serial control register SCR R/W H'00 H'FFFB3 Transmit data register TDR R/W 1 2 H'FF 2 H'FFFB4 Serial status register SSR R/(W)* H'84 H'FFFB5 Receive data register RDR R H'00 H'FFFB6 Smart card mode register SCMR R/W H'F2 H'FFFB8 Serial mode register SMR R/W H'00 H'FFFB9 Bit rate register BRR R/W H'FF H'FFFBA Serial control register SCR R/W H'00 H'FFFBB Transmit data register TDR R/W H'FF 2 H'FFFBC Serial status register SSR R/(W)* H'84 H'FFFBD Receive data register RDR R H'00 H'FFFBE Smart card mode register SCMR R/W H'F2 H'FFFC0 Serial mode register SMR R/W H'00 H'FFFC1 Bit rate register BRR R/W H'FF H'FFFC2 Serial control register SCR R/W H'00 H'FFFC3 Transmit data register TDR R/W H'FF 2 H'FFFC4 Serial status register SSR R/(W)* H'84 H'FFFC5 Receive data register RDR R H'00 H'FFFC6 Smart card mode register SCMR R/W H'F2 Notes: 1. Indicates the lower 20 bits of the address in advanced mode. 2. Only 0 can be written, to clear flags. Rev. 3.00 Sep 14, 2005 page 471 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 13.2 Register Descriptions 13.2.1 Receive Shift Register (RSR) RSR is the register that receives serial data. 7 Bit 5 6 4 3 2 1 0 Read/Write The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data. When one byte of data has been received, it is automatically transferred to RDR. The CPU cannot read or write RSR directly. 13.2.2 Receive Data Register (RDR) RDR is the register that stores received serial data. Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R When the SCI has received one byte of serial data, it transfers the received data from RSR into RDR for storage, completing the receive operation. RSR is then ready to receive the next data. This double-buffering allows data to be received continuously. RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to H'00 by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 472 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 13.2.3 Transmit Shift Register (TSR) TSR is the register that transmits serial data. Bit 7 6 5 4 3 2 1 0 Read/Write The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR, however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write RSR directly. 13.2.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for serial transmission. Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR. The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 473 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 13.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI's serial communication format and selects the clock source for the baud rate generator. 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Clock select 1/0 These bits select the baud rate generator's clock source Multiprocessor mode Selects the multiprocessor function Stop bit length Selects the stop bit length Parity mode Selects even or odd parity Parity enable Enables or disables the addition of a parity bit Character length Selects character length in asynchronous mode Communication mode Selects asynchronous or synchronous mode The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 474 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Bit 7--Communication Mode (C/A)/GSM Mode (GM): The function of this bit differs for the normal serial communication interface and for the smart card interface. Its function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7 C/A Description 0 Asynchronous mode 1 Synchronous mode (Initial value) For smart card interface (SMIF bit in SCMR set to 1): Selects GSM mode for the smart card interface. Bit 7 GM Description 0 The TEND flag is set 12.5 etu after the start bit 1 The TEND flag is set 11.0 etu after the start bit (Initial value) Note: etu (Elementary time unit: the time for transfer of one bit) Bit 6--Character Length (CHR): Selects 7-bit or 8-bits data length in asynchronous mode. In synchronous mode, the data length is 8 bits regardless of the CHR setting, Bit 6 CHR Description 0 8-bit data 1 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Rev. 3.00 Sep 14, 2005 page 475 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Bit 5--Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode, the parity bit is neither added nor checked, regardless of the PE bit setting. Bit 5 PE Description 0 Parity bit not added or checked 1 Parity bit added and checked* (Initial value) Note: * When PE bit is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selection by the O/E bit, and the parity bit in receive data is checked to see that it matches the even or odd mode selected by the O/E bit. Bit 4--Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is ignored in synchronous mode, or when parity addition and checking is disabled in asynchronous mode. Bit 4 O/E Description 0 Even parity*1 1 (Initial value) 2 Odd parity* Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined. 2. When odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined. Bit 3--Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting is used only in asynchronous mode. In synchronous mod no stop bit is added, so the STOP bit setting is ignored. Bit 3 STOP Description 0 1 stop bit*1 1 (Initial value) 2 2 stop bits* Notes: 1. One stop bit (with value 1) is added to the end of each transmitted character. 2. Two stop bits (with value 1) are added to the end of each transmitted character. Rev. 3.00 Sep 14, 2005 page 476 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 2--Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is valid only in asynchronous mode. It is ignored in synchronous mode. For further information on the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication. Bit 2 MP Description 0 Multiprocessor function disabled 1 Multiprocessor format selected (Initial value) Bits 1 and 0--Clock Select 1 and 0 (CKS1/0): These bits select the clock source for the on-chip baud rate generator. Four clock sources are available: , /4, /16, and /64. For the relationship between the clock source, bit rate register setting, and baud rate, see section 13.2.8, Bit Rate Register (BRR). Bit 1 CKS1 Bit 0 CKS0 Description 0 0 0 1 /4 1 0 /16 1 1 /64 (Initial value) Rev. 3.00 Sep 14, 2005 page 477 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 13.2.6 Serial Control Register (SCR) SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. Bit 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 R/W R/W R/W R/W Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W Clock enable 1/0 hese bits select the SCI clock source Transmit-end interrupt enable Enables or disables transmit-end interrupts (TEI) Multiprocessor interrupt enable Enables or disables multiprocessor interrupts Receive enable Enables or disables the receiver Transmit enable Enables or disables the transmitter Receive interrupt enable Enables or disables receive-data-full interrupts (RXI) and receive-error interrupts (ERI) Transmit interrupt enable Enables or disables transmit-data-empty interrupts (TXI) The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 478 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7 TIE Description 0 Transmit-data-empty interrupt request (TXI) is disabled* 1 Transmit-data-empty interrupt request (TXI) is enabled (Initial value) Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then clearing it to 0; or by clearing the TIE bit to 0. Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the RDRF flag in SSR is set to 1 due to transfer of serial receive data from RSR to RDR; also enables or disables the receive-error interrupt (ERI). Bit 6 RIE Description 0 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled* (Initial value) 1 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled Note: * RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0; or by clearing the RIE bit to 0. Bit 5--Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations. Bit 5 TE Description 0 Transmitting disabled*1 1 2 (Initial value) Transmitting enabled* Notes: 1. The TDRE flag is fixed at 1 in SSR. 2. In the enabled state, serial transmission starts when the TDRE flag in SSR is cleared to 0 after writing of transmit data into TDR. Select the transmit format in SMR before setting the TE bit to 1. Rev. 3.00 Sep 14, 2005 page 479 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Bit 4--Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4 RE Description 0 Receiving disabled* 1 2 1 (Initial value) Receiving enabled* Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values. 2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. Select the receive format in SMR before setting the RE bit to 1. Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR. The MPIE bit setting is ignored in synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description 0 Multiprocessor interrupts are disabled (normal receive operation)(Initial value) Clearing conditions (1) The MPIE bit is cleared to 0 (2) MPB = 1 in received data 1 Multiprocessor interrupts are enabled* Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of the RDRF, FER, and ORER status flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0, enables RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows the FER and ORER flags to be set. Rev. 3.00 Sep 14, 2005 page 480 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Bit 2--Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted. Bit 2 TEIE Description 0 Transmit-end interrupt requests (TEI) are disabled* 1 Transmit-end interrupt requests (TEI) are enabled* (Initial value) Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing the TEIE bit to 0. Bits 1 and 0--Clock Enable 1 and 0 (CKE1/0): The function of these bits differs for the normal serial communication interface and for the smart card interface. Their function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or serial clock input. The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the CKE1 and CKE0 bits . For further details on selection of the SCI clock source, see table 13.9 in section 13.3, Operation. Bit 1 Bit 0 CKE1 CKE0 Description 0 0 0 1 1 0 1 1 Asynchronous mode Internal clock, SCK pin available for generic input/output*1 Synchronous mode Internal clock, SCK pin used for serial clock output*1 Asynchronous mode Internal clock, SCK pin used for clock output*2 Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode External clock, SCK pin used for clock input*3 Synchronous mode External clock, SCK pin used for serial clock input Asynchronous mode External clock, SCK pin used for clock input*3 Synchronous mode External clock, SCK pin used for serial clock input Notes: 1. Initial value 2. The output clock frequency is the same as the bit rate. 3. The input clock frequency is 16 times the bit rate. Rev. 3.00 Sep 14, 2005 page 481 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface For smart card interface (SMIF bit in SCMR set to 1): These bits, together with the GM bit in SMR, determine whether the SCK pin is used for generic input/output or as the serial clock output pin. SMR GM Bit 1 Bit 0 CKE1 CKE0 Description 0 0 0 SCK pin available for generic input/output 0 0 1 SCK pin used for clock output 1 0 0 SCK pin output fixed low 1 0 1 SCK pin used for clock output 1 1 0 SCK pin output fixed high 1 1 1 SCK pin used for clock output Rev. 3.00 Sep 14, 2005 page 482 of 910 REJ09B0258-0300 (Initial value) Section 13 Serial Communication Interface 13.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the operating status of the SCI. Bit Initial value Read/Write 5 7 6 TDRE RDRF 1 0 R/(W)*1 4 ORER FER/ERS 0 R/(W)*1 0 R/(W)*1 3 2 1 0 PER TEND MPB MPBT 1 0 0 R R R/W 0 R/(W)*1 R/(W) *1 Multiprocessor bit transfer Value of multiprocessor bit to be transmitted Multiprocessor bit Stores the received multiprocessor bit value Transmit end*2 Status flag indicating end of transmission Parity error Status flag indicating detection of a receive parity error Framing error (FER)/Error signal status (ERS)*2 Status flag indicating detection of a receive framing error, or flag indicating detection of an error signal Overrun error Status flag indicating detection of a receive overrun error Receive data register full Status flag indicating that data has been received and stored in RDR Transmit data register empty Status flag indicating that transmit data has been transferred from TDR into TSR and new data can be written in TDR Notes: 1. Only 0 can be written, to clear the flag. 2. Function differs between the normal serial communication interface and the smart card interface. Rev. 3.00 Sep 14, 2005 page 483 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written. SSR is initialized to H'84 by a reset and in standby mode. Bit 7--Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and the next serial data can be written in TDR. Bit 7 TDRE Description 0 TDR contains valid transmit data Clearing conditions Read TDRE when TDRE = 1, then write 0 in TDRE The DMAC writes data in TDR 1 TDR does not contain valid transmit data (Initial value) Setting conditions The chip is reset or enters standby mode The TE bit in SCR is cleared to 0 TDR contents are loaded into TSR, so new data can be written in TDR Bit 6--Receive Data Register Full (RDRF): Indicates that RDR contains new receive data. Bit 6 RDRF Description 0 RDR does not contain new receive data Clearing conditions The chip is reset or enters standby mode Read RDRF when RDRF = 1, then write 0 in RDRF The DMAC reads data from RDR (Initial value) 1 RDR contains new receive data Setting condition Serial data is received normally and transferred from RSR to RDR Note: The RDR contents and the RDRF flag are not affected by detection of receive errors or by clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still set to 1 when reception of the next data ends, an overrun error will occur and the receive data will be lost. Rev. 3.00 Sep 14, 2005 page 484 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Bit 5--Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER Description 0 Receiving is in progress or has ended normally*1 Clearing conditions The chip is reset or enters standby mode Read ORER when ORER = 1, then write 0 in ORER 1 A receive overrun error occurred*2 Setting condition Reception of the next serial data ends when RDRF = 1 (Initial value) Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its previous value. 2. RDR continues to hold the receive data prior to the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In synchronous mode, serial transmitting is also disabled. Bit 4--Framing Error (FER)/Error Signal Status (ERS): The function of this bit differs for the normal serial communication interface and for the smart card interface. Its function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that data reception ended abnormally due to a framing error in asynchronous mode. Bit 4 FER Description 0 Receiving is in progress or has ended normally*1 Clearing conditions The chip is reset or enters standby mode Read FER when FER = 1, then write 0 in FER 1 A receive framing error occurred*2 Setting condition The stop bit at the end of the receive data is checked and found to be 0 (Initial value) Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous value. 2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs the SCI transfers the receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set to 1. In synchronous mode, serial transmitting is also disabled. Rev. 3.00 Sep 14, 2005 page 485 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface For smart card interface (SMIF bit in SCMR set to 1): Indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4 ERS Description 0 Normal reception, no error signal* Clearing conditions The chip is reset or enters standby mode Read ERS when ERS = 1, then write 0 in ERS (Initial value) 1 An error signal has been sent from the receiving side indicating detection of a parity error Setting condition The error signal is low when sampled Note: * Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous value. Bit 3--Parity Error (PER): Indicates that data reception ended abnormally due to a parity error in asynchronous mode. Bit 3 PER Description 0 Receiving is in progress or has ended normally*1 Clearing conditions The chip is reset or enters standby mode Read PER when PER = 1, then write 0 in PER 1 A receive parity error occurred*2 Setting condition The number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of O/E in SMR (Initial value) Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous value. 2. When a parity error occurs the SCI transfers the receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In synchronous mode, serial transmitting is also disabled. Rev. 3.00 Sep 14, 2005 page 486 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Bit 2--Transmit End (TEND): The function of this bit differs for the normal serial communication interface and for the smart card interface. Its function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that when the last bit of a serial character was transmitted TDR did not contain valid transmit data, so transmission has ended. The TEND flag is a read-only bit and cannot be written. Bit 2 TEND Description 0 Transmission is in progress Clearing conditions Read TDRE when TDRE = 1, then write 0 in TDRE The DMAC writes data in TDR 1 End of transmission (Initial value) Setting conditions The chip is reset or enters standby mode The TE bit in SCR is cleared to 0 TDRE is 1 when the last bit of a 1-byte serial transmit character is transmitted For smart card interface (SMIF bit in SCMR set to 1): Indicates that when the last bit of a serial character was transmitted TDR did not contain valid transmit data, so transmission has ended. The TEND flag is a read-only bit and cannot be written. Bit 2 TEND Description 0 Transmission is in progress Clearing conditions Read TDRE when TDRE = 1, then write 0 in TDRE The DMAC writes data in TDR 1 End of transmission (Initial value) Setting conditions The chip is reset or enters standby mode The TE bit is cleared to 0 in SCR and the FER/ERS bit is also cleared to 0 TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu (when GM = 0) or 1.0 etu (when GM = 1) after a 1-byte serial character is transmitted Note: etu (Elementary time unit: the time for transfer of one bit) Rev. 3.00 Sep 14, 2005 page 487 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Bit 1--Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot be written. Bit 1 MPB Description 0 Multiprocessor bit value in receive data is 0* 1 Multiprocessor bit value in receive data is 1 (Initial value) Note: * If the RE bit in SCR is cleared to 0 when a multiprocessor format is selected, MPB retains its previous value. Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format in selected for transmitting in asynchronous mode. The MPBT bit setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI cannot transmit. Bit 1 MPBT Description 0 Multiprocessor bit value in transmit data is 0 1 Multiprocessor bit value in transmit data is 1 13.2.8 (Initial value) Bit Rate Register (BRR) BRR is an 8-bit register that., together with the CKS1 and CKS0 bits in SMR that select the baud rate generator clock source, determines the serial communication bit rate. Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby mode. Each SCI channel has independent baud rate generator control, so different values can be set in the three channels. Table 13.3 shows examples of BRR settings in asynchronous mode. Table 13.4 shows examples of BRR settings in synchronous mode. Rev. 3.00 Sep 14, 2005 page 488 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Table 13.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (MHz) Bit Rate (bit/s) n 2 2.097152 N 110 1 141 0.03 1 148 -0.04 1 174 -0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 -0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 -2.48 0 15 0.00 0 19 -2.34 9600 0 6 -6.99 0 6 -2.48 0 7 0.00 0 9 -2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 -2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 -18.62 0 1 -14.67 0 1 0.00 -- -- -- Error (%) n N 2.4576 Error (%) n N 3 Error (%) n N Error (%) 0.16 (MHz) Bit Rate (bit/s) n 3.6864 4 4.9152 5 N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 -0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 -1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 -6.99 0 7 0.00 0 7 1.73 31250 -- -- -- 0 3 0.00 0 4 -1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 0.16 Rev. 3.00 Sep 14, 2005 page 489 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface (MHz) Bit Rate (bit/s) n 6 6.144 N 110 2 106 -0.44 2 108 0.08 2 130 -0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 Error (%) n N 7.3728 Error (%) n N 8 Error (%) n N Error (%) 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 -2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 -2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 -2.34 0 4 0.00 0 5 0.00 0 6 -6.99 (MHz) Bit Rate (bit/s) 9.8304 n N 110 2 174 -0.26 10 Error (%) n 2 N 12 Error (%) n N 12.288 Error (%) n 177 -0.25 2 212 0.03 2 N Error (%) 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0 64 0.16 0 77 0 79 0.00 0.16 0.00 0.00 0.00 9600 0 31 0.00 0 32 -1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 -2.34 0 19 0.00 31250 0 9 -1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 -2.34 0 9 0.00 Rev. 3.00 Sep 14, 2005 page 490 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface (MHz) Bit Rate (bit/s) 13 n N 14 Error n N (%) 14.7456 Error n N (%) 110 2 230 -0.08 2 248 -0.17 3 64 150 2 168 0.16 300 2 84 600 1 168 0.16 1200 1 84 2400 0 168 0.16 2 181 0.16 -0.43 2 90 0.16 1 181 0.16 -0.43 1 90 0.16 0 181 0.16 16 18 20 Error n N (%) Error n N (%) Error n N (%) Error (%) 0.70 0.03 -0.12 3 88 -0.25 3 70 3 79 2 191 0.00 2 207 0.16 2 233 0.16 3 64 0.16 2 95 0.00 2 103 0.16 2 116 0.16 2 129 0.16 1 191 0.00 1 207 0.16 1 233 0.16 2 64 1 95 0.00 1 103 0.16 1 116 0.16 1 129 0.16 0 191 0.00 0 207 0.16 0 233 0.16 1 64 0 129 0.16 0.16 0.16 4800 0 84 -0.43 0 90 0.16 0 95 0.00 0 103 0.16 0 116 0.16 9600 0 41 0.76 0 45 -0.93 0 47 0.00 0 51 0.16 0 58 -0.69 0 64 0.16 19200 0 20 0.76 0 22 -0.93 0 23 0.00 0 25 0.16 0 28 1.02 0 32 -1.36 31250 0 12 0.00 0 13 0.00 0 14 -1.70 0 15 0.00 0 17 0.00 0 19 0.00 38400 0 10 -3.82 0 10 3.57 0 11 0.00 0.16 0 14 -2.34 0 15 1.73 0 12 Rev. 3.00 Sep 14, 2005 page 491 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Table 13.4 Examples of Bit Rates and BRR Settings in Synchronous Mode (MHz) Bit Rate 2 4 8 10 13 16 18 20 (bit/s) n N n N n N n N n N n N n N n N 110 3 70 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 250 2 124 2 249 3 124 -- -- 3 202 3 249 -- -- -- -- 500 1 249 2 124 2 249 -- -- 3 101 3 124 3 140 3 155 1k 1 124 1 249 2 124 -- -- 2 202 2 249 3 69 3 77 2.5k 0 199 1 99 1 199 1 249 2 80 2 99 2 112 2 124 5k 0 99 0 199 1 99 1 124 1 162 1 199 1 224 1 249 10k 0 49 0 99 0 199 0 249 1 80 1 99 1 112 1 124 25k 0 19 0 39 0 79 0 99 0 129 0 159 0 179 0 199 50k 0 9 0 19 0 39 0 49 0 64 0 79 0 89 0 99 100k 0 4 0 9 0 19 0 24 -- -- 0 39 0 44 0 49 250k 0 1 0 3 0 7 0 9 0 12 0 15 0 17 0 19 500k 0 0* 0 1 0 3 0 4 -- -- 0 7 0 8 0 9 0 0* 0 1 -- -- -- -- 0 3 0 4 0 4 2M 0 0* -- -- -- -- 0 1 -- -- -- -- 2.5M -- -- 0 0* -- -- -- -- -- -- -- -- 0 0* -- -- -- -- 1M 4M Note: Settings with an error of 1% or less are recommended. Legend Blank : No setting available --: Setting possible, but error occurs *: Continuous transmission/reception not possible Rev. 3.00 Sep 14, 2005 page 492 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface The BRR setting is calculated as follows: Asynchronous mode: N= 64 x 22n-1 x B x 106 - 1 Synchronous mode: N= B: N: : n: 8 x 22n-1 x B x 106 - 1 Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) System clock frequency (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (For the clock sources and values of n, see the following table.) SMR Settings n Clock Source CKS1 CKS0 0 0 0 1 /4 0 1 2 /16 1 0 3 /64 1 1 The bit rate error in asynchronous mode is calculated as follows: Error (%) = x 106 (N + 1) x B x 64 x 22n-1 -1 x 100 Rev. 3.00 Sep 14, 2005 page 493 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Table 13.5 shows the maximum bit rates in asynchronous mode for various system clock frequencies. Table 13.6 and 13.7 shows the maximum bit rates with external clock input. Table 13.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings (MHz) Maximum Bit Rate (bit/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 20 625000 0 0 Rev. 3.00 Sep 14, 2005 page 494 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 20 5.0000 312500 Rev. 3.00 Sep 14, 2005 page 495 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 Rev. 3.00 Sep 14, 2005 page 496 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 13.3 Operation 13.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. A smart card interface is also supported as a serial communication function for an IC card interface. Selection of asynchronous or synchronous mode and the transmission format for the normal serial communication interface is made in SMR, as shown in table 13.8. The SCI clock source is selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13.9. For details of the procedures for switching between LSB-first and MSB-first mode and inverting the data logic level, see section 14.2.1, Smart Card Mode Register (SCMR). For selection of the smart card interface format, see section 14.3.3, Data Format. Asynchronous Mode * Data length is selectable: 7 or 8 bits * Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These selections determine the communication format and character length. * In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break state. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode * The communication format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Rev. 3.00 Sep 14, 2005 page 497 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Smart Card Interface * One frame consists of 8-bit data and a parity bit. * In transmitting, a guard time of at least two elementary time units (2 etu) is provided between the end of the parity bit and the start of he next frame. (An elementary time unit is the time required to transmit one bit.) * In receiving, if a parity error is detected, a low error signal level is output for 1 etu, beginning 10.5 etu after the start bit.. * In transmitting, if an error signal is received, the same data is automatically transmitted again after at least 2 etu. * Only asynchronous communication is supported. There is no synchronous communication function. For details of smart card interface operation, see section 14, Smart Card Interface. Table 13.8 SMR Settings and Serial Communication Formats SMR Settings SCI Communication Format Bit 7 C/A Bit 6 CHR Bit 2 MP Bit 5 PE Bit 3 STOP 0 0 0 0 0 1 0 1 Mode AsynChronous mode Data Length Multiprocessor Bit Parity Bit Stop Bit Length 8-bit data Absent Absent 1 bit 2 bits Present 1 1 0 2 bits 0 7-bit data Absent 1 1 0 1 -- 0 -- 1 1 -- 0 -- 1 1 -- -- -- -- 1 bit 2 bits Present 1 0 1 bit 1 bit 2 bits Asyn8-bit data chronous mode (multi7-bit data processor format) Present Synchronous mode Absent Rev. 3.00 Sep 14, 2005 page 498 of 910 REJ09B0258-0300 8-bit data Absent 1 bit 2 bits 1 bit 2 bits None Section 13 Serial Communication Interface Table 13.9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Setting SCI Transmit/Receive clock Bit 7 C/A Bit 1 Bit 0 CKE1 CKE0 Mode Clock Source SCK Pin Function 0 0 0 1 1 Asynchronous mode 0 Internal Outputs clock with frequency matching the bit rate External Inputs clock with frequency 16 times the bit rate Internal Outputs the serial clock External Inputs the serial clock 1 1 0 0 1 1 0 Synchronous mode SCI does not use the SCK pin 1 13.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with one or two stop bits. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full-duplex communication is possible. The transmitter and the receiver are both double-buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous serial communication the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and one or two stop bits (high), in that order. When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Rev. 3.00 Sep 14, 2005 page 499 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Idle (mark) state (LSB) 1 Serial data 0 Start bit 1 bit D0 1 (MSB) D1 D2 D3 D4 D5 D6 Transmit or receive data 7 or 8 bits One unit of data (character or frame) D7 0/1 Parity bit 1 bit, or none 1 1 Stop bit(s) 1 or 2 bits Figure 13.2 Data Format in Asynchronous Communication (Example: 8-Bit Data with Parity and 2 Stop Bits) Communication Formats: Table 13.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in SMR. Rev. 3.00 Sep 14, 2005 page 500 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Table 13.10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOP STOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOP STOP STOP Legend S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 3.00 Sep 14, 2005 page 501 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source selection, see table 13.9. When an external clock is input at the SCK pin, it must have a frequency 16 times the desired bit rate. When the SCI is operated on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure 13.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1frame Figure 13.3 Phase Relationship between Output Clock and Serial Data (Asynchronous Mode) Transmitting and Receiving Data: * SCI Initialization (Asynchronous Mode): Before transmitting or receiving data, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags, or RDR, which retain their previous contents. When an external clock is used the clock should not be stopped during initialization or subsequent operation, since operation will be unreliable in this case. Rev. 3.00 Sep 14, 2005 page 502 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Figure 13.4 shows a sample flowchart for initializing the SCI. Start of initialization Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (leaving TE and RE bits cleared to 0) (1) Select communication format in SMR (2) Set value in BRR (3) Wait (1) Set the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCR. (2) Select the communication format in SMR. (3) Write the value corresponding to the bit rate in BRR. This step is not necessary when an external clock is used. (4) Wait for at least the interval required to transmit or receive one bit, then set the TE or RE bit to 1 in SCR. Set the RIE, TIE, TEIE, and MPIE bits as necessary. Setting the TE or RE bit enables the SCI to use the TxD or RxD pin. No 1-bit interval elapsed? Yes Set TE or RE bit to 1 in SCR Set the RIE, TIE, TEIE, and MPIE bits (4) <End of initialization> Note: In simultaneous transmitting and receiving, the TE and RE bits should be cleared to 0 or set to 1 simultaneously. Figure 13.4 Sample Flowchart for SCI Initialization Rev. 3.00 Sep 14, 2005 page 503 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface * Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. (1) Initialize Start transmitting (2) Read TDRE flag in SSR No TDRE = 1 Write transmit data in TDR and clear TDRE flag to 0 in SSR No Yes (2) SCI status check and transmit data write: read SSR and check that the TDRE flag is set to 1, then write transmit data in TDR and clear the TDRE flag to 0. (3) To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. Yes All data transmitted? (1) SCI initialization: the transmit data output function of the TxD pin is selected automatically. (3) (4) To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0, then clear the TE bit to 0 in SCR. Read TEND flag in SSR TEND = 1 No Yes Output break signal? No (4) Yes Clear DR bit to 0 and set DDR bit to 1 Clear TE bit to 0 in SCR <End> Figure 13.5 Sample Flowchart for Transmitting Serial Data Rev. 3.00 Sep 14, 2005 page 504 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface In transmitting serial data, the SCI operates as follows: * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. * After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: Start bit: One 0 bit is output. Transmit data: 7 or 8 bits are output, LSB first. Parity bit or multiprocessor bit: One parity bit (even or odd parity),or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. Stop bit(s): One or two 1 bits (stop bits) are output. Mark state: Output of 1 bits continues until the start bit of the next transmit data. * The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is requested at this time Figure 13.6 shows an example of SCI transmit operation in asynchronous mode. 1 0 Parity Stop Start bit bit bit Data Start bit D0 D1 D7 0/1 1 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 1 Idle state (mark state) TDRE TEND 1 frame TXI interrupt request TXI interrupt handler writes data in TDR and clears TDRE flag to 0 TXI interrupt request TEI interrupt request Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and One Stop Bit) Rev. 3.00 Sep 14, 2005 page 505 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface * Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. (1) Initialize (1) SCI initialization: the receive data input function of the RxD pin is selected automatically. (2)(3) Receive error handling and break detection: if a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After executing the necessary error handling, clear the ORER, PER, and FER flags all to 0. Receiving cannot resume if any of these flags remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. Start receiving Read ORER, PER, and FER flags in SSR (2) Yes PERFEROPER = 1 (3) Error handling No (continued on next page) Read RDRF flag in SSR No (4) (4) SCI status check and receive data read: read SSR, check that the RDRF flag is set to 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. (5) To continue receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the stop bit of the current frame is received. When the DMAC is activated by a receive-data-full interrupt request (RXI) to read RDR, the RDRF flag is cleared automatically. RDRF = 1 Yes Read receive data from RDR, and clear RDRF flag to 0 in SSR No All data received? (5) Yes Clear RE bit to 0 in SCR <End> Figure 13.7 Sample Flowchart for Receiving Serial Data (1) Rev. 3.00 Sep 14, 2005 page 506 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface (3) Error handling No ORER = 1 Yes Overrun error handling No FER = 1 Yes Break? Yes No Framing error handling No Clear RE bit to 0 in SCR PER = 1 Yes Parity error handling Clear ORER, PER, and FER flags to 0 in SSR <End> Figure 13.7 Sample Flowchart for Receiving Serial Data (2) Rev. 3.00 Sep 14, 2005 page 507 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface In receiving, the SCI operates as follows: * The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI synchronizes internally and starts receiving. * Receive data is stored in RSR in order from LSB to MSB. * The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks: Parity check: The number of 1s in the receive data must match the even or odd parity setting of in the O/E bit in SMR. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first is checked. Status check: The RDRF flag must be 0, indicating that the receive data can be transferred from RSR into RDR. If these all checks pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one of the checks fails (receive error*), the SCI operates as shown in table 13.11. Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag is not set to 1. Be sure to clear the error flags to 0. * When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt (RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also set to 1, a receive-error interrupt (ERI) is requested. Table 13.11 Receive Error Conditions Receive Error Abbreviation Condition Data Transfer Overrun error ORER Receiving of next data ends while Receive data is not transferred RDRF flag is still set to 1 in SSR from RSR to RDR Framing error FER Stop bit is 0 Parity error Parity of received data differs from Receive data is transferred from even/odd parity setting in SMR RSR to RDR PER Rev. 3.00 Sep 14, 2005 page 508 of 910 REJ09B0258-0300 Receive data is transferred from RSR to RDR Section 13 Serial Communication Interface Figure 13.8 shows an example of SCI receive operation in asynchronous mode. 1 Start bit 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 Start bit 0 Data D0 D1 Stop Parity Stop bit bit bit D7 0/1 1 1 Idle (mark) state RDRF FER RXI request 1 frame RXI interrupt handler reads data in RDR and clears RDRF flag to 0 Framing error, ERI request Figure 13.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 13.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor stars by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 13.9 shows an example of communication among different processors using a multiprocessor format. Rev. 3.00 Sep 14, 2005 page 509 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Communication Formats: Four formats are available. Parity bit settings are ignored when a multiprocessor format is selected. For details see table 13.10. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Serial data Receiving processor A Receiving processor B Receiving processor C Receiving processor D (ID=01) (ID=02) (ID=03) (ID=04) H'AA H'01 (MPB=1) ID-sending cycle: receiving processor address (MPB=0) Data-sending cycle: data sent to receiving processor specified by ID Legend MPB : Multiprocessor bit Figure 13.9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) Transmitting and Receiving Data: * Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. Rev. 3.00 Sep 14, 2005 page 510 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface (1) Initialize (1) SCI initialization: the transmit data output function of the TxD pin is selected automatically. (2) SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR. Also set the MPBT flag to 0 or 1 in SSR. Finally, clear the TDRE flag to 0. (3) To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. (4) To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0, then clear the TE bit to 0 in SCR. Start transmitting Read TDRE flag in SSR TDRE = 1 (2) No Yes Write transmit data in TDR and set MPBT bit in SSR Clear TDRE flag to 0 All data transmitted? No (3) Yes Read TEND flag in SSR TEND = 1 No Yes Output break signal? No (4) Yes Clear DR bit to 0 and set DDR to 1 Clear TE bit to 0 in SCR <End> Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data Rev. 3.00 Sep 14, 2005 page 511 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface In transmitting serial data, the SCI operates as follows: * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. * After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: Start bit: One 0 bit is output. Transmit data: 7 or 8 bits are output, LSB first. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. Stop bit(s): One or two 1 bits (stop bits) are output. Mark state: Output of 1 bits continues until the start bit of the next transmit data. * The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is requested at this time Figure 13.11 shows an example of SCI transmit operation using a multiprocessor format. 1 Start bit 0 Data D0 D1 Multiprocessor Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Multiprocessor Stop bit bit D7 0/1 1 Idle (mark) state TDRE TEND TXI interrupt TXI interrupt handler writes data in TDR and request clears TDRE flag to 0 TXI interrupt request TEI interrupt request 1 frame Figure 13.11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) * Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. Rev. 3.00 Sep 14, 2005 page 512 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface (1) Initialize (1) SCI initialization: the receive data input function of the RxD pin is selected automatically. (2) ID receive cycle: set the MPIE bit to 1 in SCR. (3) SCI status check and ID check: read SSR, check that the RDRF flag is set to 1, then read data from RDR and compare it with the processor's own ID. If the ID does not match, set the MPIE bit to 1 again and clear the RDRF flag to 0. If the ID matches, clear the RDRF flag to 0. (4) SCI status check and data receiving: read SSR, check that the RDRF flag is set to 1, then read data from RDR. (5) Receive error handling and break detection: if a receive error occurs, read the ORER and FER flags in SSR to identify the error. After executing the necessary error handling, clear the ORER and FER flags both to 0. Receiving cannot resume while either the ORER or FER flag remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. Start receiving (2) Set MPIE bit to 1 in SCR Read ORER and FER flags in SSR FERORER = 1 Yes No Read RDRF flag in SSR No (3) RDRF = 1 Yes Read RDRF flag in SSR No Own ID? Yes Read ORER and FER flags in SSR FERORER = 1 Yes No (4) Read RDRF flag in SSR RDRF = 1 No Yes Read receive data from RDR No Finished receiving? Yes Clear RE bit to 0 in SCR (5) Error handling (continued on next page) <End> Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1) Rev. 3.00 Sep 14, 2005 page 513 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface (5) Error handling No ORER = 1 Yes Overrun error handling No FER = 1 Yes Break? Yes No Clear RE bit to 0 in SCR Framing error handling Clear ORER, PER, and FER flags to 0 in SSR <End> Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Rev. 3.00 Sep 14, 2005 page 514 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Figure 13.13 shows an example of SCI receive operation using a multiprocessor format. 1 Start bit 0 Stop MPB bit Data (ID1) D0 D7 D1 1 Start bit 0 1 Stop MPB bit Data (data1) D0 D1 D7 1 0 1 Idle (mark) state MPIE RDRF RDR value ID1 MPB detection MPIE = 0 RXI interrupt request (multiprocessor interrupt) RXI interrupt handler reads RDR data and clears RDRF flag to 0 Not own ID, so MPIE bit is set to 1 again No RXI interrupt request, RDR not updated a. Own ID does not match data 1 Start bit 0 Data (ID2) D0 D1 MPB D7 1 Stop bit 1 Start bit Data (data1) 0 D0 D1 MPB D7 0 Stop bit 1 1 Idle (mark) state MPIE RDRF RDR value ID1 MPB detection MPIE = 0 ID2 RXI interrupt request (multiprocessor interrupt) RXI interrupt handler reads RDR data and clears RDRF flag to 0 Data2 Own ID, so receiving MPIE bit is set to continues, with data 1 again received by RXI interrupt handler b. Own ID matches data Figure 13.13 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev. 3.00 Sep 14, 2005 page 515 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 13.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so fullduplex communication is possible. The transmitter and the receiver are also double-buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 13.14 shows the general format in synchronous serial communication. One unit (character or frame) of transfer data * * Serial clock LSB Bit 0 Serial data MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Don't care Note: * High except in continuous transmitting or receiving Figure 13.14 Data Format in Synchronous Communication In synchronous serial communication, each data bit is placed on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock. In each character, the serial data bits are transferred in order from LSB (first) to MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode the SCI receives data by synchronizing with the rise of the serial clock. Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by means of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. See table 13.6 for details of SCI clock source selection. When the SCI operates on an internal clock, it outputs the clock source at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. If receiving in single-character units is required, an external clock should be selected. Rev. 3.00 Sep 14, 2005 page 516 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Transmitting and Receiving Data: * SCI Initialization (Synchronous Mode): Before transmitting or receiving data, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes TSR. Note that clearing RE to 0, however, does not initialize the RDRF, PER, and ORE flags, or RDR, which retain their previous contents. Rev. 3.00 Sep 14, 2005 page 517 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Figure 13.15 shows a sample flowchart for initializing the SCI. Start of initialization Clear TE and RE bits to 0 in SCR Set RIE, TIE, TEIE, MPIE, CKE1, (1) and CKE0 bits in SCR (leaving TE and RE bits cleared to 0) Select communication format in SMR Set value in BRR Wait 1-bit interval elapsed? (2) (3) (1) Set the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0.* (2) Select the communication format in SMR. (3) Write the value corresponding to the bit rate in BRR. This step is not necessary when an external clock is used. (4) Wait for at least the interval required to transmit or receive one bit, then set the TE or RE bit to 1 in SCR.* Set the RIE, TIE, TEIE, and MPIE bits as necessary. Setting the TE or RE bit enables the SCI to use the TxD or RxD pin. Note: * In simultaneous transmitting and receiving, the TE and RE bits should be cleared to 0 or set to 1 simultaneously. No Yes Set TE or RE bit to 1 in SCR Set RIE, TIE, TEIE, and MPIE bits as necessary (4) <Start transmitting or receiving> Figure 13.15 Sample Flowchart for SCI Initialization Rev. 3.00 Sep 14, 2005 page 518 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface * Transmitting Serial Data (Synchronous Mode): Figure 13.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. (1) Initialize (1) SCI initialization: the transmit data output function of the TxD pin is selected automatically. (2) SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. (3) To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. Start transmitting Read TDRE flag in SSR TDRE = 1 (2) No Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR All data transmitted? No (3) Yes Read TEND flag in SSR TEND = 1 No Yes Clear TE bit to 0 in SCR <End> Figure 13.16 Sample Flowchart for Serial Transmitting Rev. 3.00 Sep 14, 2005 page 519 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface In transmitting serial data, the SCI operates as follows. * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. * After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin n order from LSB (bit 0) to MSB (bit 7). * The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB (bit 7), holds the TxD pin in the MSB state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is requested at this time * After the end of serial transmission, the SCK pin is held in a constant state. Figure 13.17 shows an example of SCI transmit operation. Transmit direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request TXI interrupt handler TXI interrupt writes data in TDR request and clears TDRE flag to 0 1 frame Figure 13.17 Example of SCI Transmit Operation Rev. 3.00 Sep 14, 2005 page 520 of 910 REJ09B0258-0300 TEI interrupt request Section 13 Serial Communication Interface * Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous to synchronous mode. make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled. (1) Initialize (1) Start receiving Read ORER flag in SSR (2) Yes ORER = 1 (3) No Error handling (2)(3) Receive error handling: if a receive error occurs, read the ORER flag in SSR, then after executing the necessary error handling, clear the ORER flag to 0. Neither transmitting nor receiving can resume while the ORER flag remains set to 1. (4) SCI status check and receive data read: read SSR, check that the RDRF flag is set to 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. (5) To continue receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. When the DMAC is activated by a receive-data-full interrupt request (RXI) to read RDR, the RDRF flag is cleared automatically. (continued on next page) Read RDRF flag in SSR No (4) RDRF = 1 Yes Read receive data from RDR, and clear RDRF flag to 0 in SSR No Finished receiving? (5) SCI initialization: the receive data input function of the RxD pin is selected automatically. Yes Clear RE bit to 0 in SCR <End> Figure 13.18 Sample Flowchart for Serial Receiving (1) Rev. 3.00 Sep 14, 2005 page 521 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface (3) Error handling Overrun error handling Clear ORER flag to 0 in SSR <End> Figure 13.18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows: * The SCI synchronizes with serial clock input or output and synchronizes internally. * Receive data is stored in RSR in order from LSB to MSB. After receiving the data, the SCI checks that the RDRF flag is 0, so that receive data can be transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received data is stored in RDR. If the checks fails (receive error), the SCI operates as shown in table 13.11. When a receive error has been identified in the error check, subsequent transmit and receive operations are disabled. * When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt (RXI) is requested. If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1, a receive-error interrupt (ERI) is requested. Rev. 3.00 Sep 14, 2005 page 522 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Figure 13.19 shows an example of SCI receive operation. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request RXI interrupt handler reads data in RDR and clears RDRF flag to 0 RXI interrupt request Overrun error, ERI interrupt request 1 frame Figure 13.19 Example of SCI Receive Operation Rev. 3.00 Sep 14, 2005 page 523 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface * Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 13.20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. Initialize (1) (1) SCI initialization: the transmit data output function of the TxD pin and the read data input function of the RxD pin are selected, enabling simultaneous transmitting and receiving. (2) SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. Notification that the TDRE flag has changed from 0 to 1 can also be given by the TXI interrupt. (3) Receive error handling: if a receive error occurs, read the ORER flag in SSR, then after executing the necessary error handling, clear the ORER flag to 0. Neither transmitting nor receiving can resume while the ORER flag remains set to 1. (4) SCI status check and receive data read: read SSR, check that the RDRF flag is 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. (5) To continue transmitting and receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. Also check that the TDRE flag is set to 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is activated by a transmitdata-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. When the DMAC is activated by a receive-data-full interrupt request (RXI) to read RDR, the RDRF flag is cleared automatically. Start of transmitting and receiving Read TDRE flag in SSR No (2) TDRE = 1 Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR Read ORER flag in SSR ORER = 1 Yes (3) No Error handling Read RDRF flag in SSR No (4) RDRF = 1 Yes Read receive data from RDR, and clear RDRF flag to 0 in SSR No End of transmitting and receiving? (5) Yes Clear TE and RE bits to 0 in SCR <End> Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, clear both the TE bit and the RE bit to 0, then set both bits to 1 simultaneously. Figure 13.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving Rev. 3.00 Sep 14, 2005 page 524 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 13.4 SCI Interrupts The SCI has four interrupt request sources: the transmit-end interrupt (TEI), receive-error interrupt (ERI), receive-data-full interrupt (RXI), and transmit-data-empty interrupt (TXI). Table 13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE, and TEIE bits in SCR. Each interrupt request is sent separately to the interrupt controller. A TXI interrupt is requested when the TDRE flag is set to 1 in SSR. A TEI interrupt is requested when the TEND flag is set to 1 in SSR. A TXI interrupt request can activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the TDRE flag to 0. A TEI interrupt request cannot activate the DMAC. An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or FER flag is set to 1 in SSR. An RXI interrupt can activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the RDRF flag to 0. An ERI interrupt request cannot activate the DMAC. The DMAC can be activated by interrupts from SCI channel 0. Table 13.12 SCI Interrupt Sources Interrupt Source Description Priority ERI Receive error (ORER, FER, or PER) High RXI Receive data register full (RDRF) TXI Transmit data register empty (TDRE) TEI Transmit end (TEND) Low Rev. 3.00 Sep 14, 2005 page 525 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 13.5 Usage Notes 13.5.1 Notes on Use of SCI Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR. Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE flag is set to 1. Simultaneous Multiple Receive Errors: Table 13.13 shows the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs the RSR contents are not transferred to RDR, so receive data is lost. Table 13.13 SSR Status Flags and Transfer of Receive Data Receive Data Transfer SSR Status Flags RDRF ORER FER PER RSR RDR Receive Errors 1 1 0 0 x Overrun error 0 0 1 0 Framing error 0 0 0 1 Parity error 1 1 1 0 x Overrun error + framing error 1 1 0 1 x Overrun error + parity error 0 0 1 1 1 1 1 1 Notes: : Receive data is transferred from RSR to RDR. x : Receive data is not transferred from RSR to RDR. Rev. 3.00 Sep 14, 2005 page 526 of 910 REJ09B0258-0300 Framing error + parity error x Overrun error + framing error + parity error Section 13 Serial Communication Interface Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again. Sending a Break Signal: The input/output condition and level of the TxD pin are determined by DR and DDR bits. This feature can be used to send a break signal. After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR bits should therefore be set to 1 beforehand. To send a break signal during serial transmission, clear the DR bit to 0 , then clear the TE bit to 0. When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the TxD pin becomes an input/output outputting the value 0. Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that clearing the RE bit to 0 does not clear the receive error flags to 0. Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See figure 13.21. Rev. 3.00 Sep 14, 2005 page 527 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal base clock Receive data (RxD) D0 Start bit D1 Synchronization sampling timing Data sampling timing Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M= 1 2N (0.5 - ) - (L - 0.5) F - D - 0.5 N (1 + F) x 100% . . . . . . . . (1) M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (L = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). D = 0.5, F = 0 M = (0.5 - 1 2 x 16 ) x 100% = 46.875% . . . . . . . . (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev. 3.00 Sep 14, 2005 page 528 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Restrictions on Use of DMAC: * When an external clock source is used for the serial clock, after the DMAC updates TDR, allow an inversion of at least five system clock () cycles before input of the serial clock to start transmitting. If the serial clock is input within four states of the TDR update, a malfunction may occur. (See figure 13.22) * To have the DMAC read RDR, be sure to select the corresponding SCI receive-data-full interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR. SCK t TDRE D0 D1 D2 D3 D4 D5 D6 D7 Note: In operation with an external clock source, be sure that t >4 states. Figure 13.22 Example of Synchronous Transmission Using DMAC Rev. 3.00 Sep 14, 2005 page 529 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Switching from SCK Pin Function to Port Pin Function: * Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 13.23) Half-cycle low-level output SCK/port 1. End of transmission Data TE Bit 6 4. Low-level output Bit 7 2. TE= 0 C/A 3. C/A = 0 CKE1 CKE0 Figure 13.23 Operation when Switching from SCK Pin Function to Port Pin Function Rev. 3.00 Sep 14, 2005 page 530 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface * Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 ... switchover to port output 5. CKE1 bit = 0 High-level output TE SCK/port 1. End of transmission Data TE Bit 6 Bit 7 2. TE= 0 4. C/A = 0 C/A 3. CKE1= 1 CKE1 5. CKE1= 0 CKE0 Figure 13.24 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) Rev. 3.00 Sep 14, 2005 page 531 of 910 REJ09B0258-0300 Section 13 Serial Communication Interface Rev. 3.00 Sep 14, 2005 page 532 of 910 REJ09B0258-0300 Section 14 Smart Card Interface Section 14 Smart Card Interface 14.1 Overview An IC card (smart card) interface conforming to the ISO/IEC 7816-3 (Identification Card) standard is supported as an extension of the serial communication interface (SCI) functions. Switchover between the normal serial communication interface and the smart card interface is controlled by a register setting. 14.1.1 Features Features of the smart card interface supported by the H8/3068F are listed below. * Asynchronous communication Data length: 8 bits Parity bit generation and checking Transmission of error signal (parity error) in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported * Built-in baud rate generator allows any bit rate to be selected * Three interrupt sources There are three interrupt sources--transmit-data-empty, receive-data-full, and transmit/receive error--that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute data transfer. Rev. 3.00 Sep 14, 2005 page 533 of 910 REJ09B0258-0300 Section 14 Smart Card Interface 14.1.2 Block Diagram Bus interface Figure 14.1 shows a block diagram of the smart card interface. Module data bus RxD RDR TDR RSR TSR TxD SCMR SSR SCR SMR Transmission/ reception control Parity generation BRR Baud rate generator /4 /16 /64 Clock Parity check External clock SCK Legend SCMR: RSR: RDR: TSR: TDR: SMR: SCR: SSR: BRR: Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register TXI RXI ERI Figure 14.1 Block Diagram of Smart Card Interface Rev. 3.00 Sep 14, 2005 page 534 of 910 REJ09B0258-0300 Internal data bus Section 14 Smart Card Interface 14.1.3 Pin Configuration Table 14.1 shows the smart card interface pins. Table 14.1 Smart Card Interface Pins Pin Name Abbreviation I/O Function Serial clock pin SCK I/O Clock input/output Receive data pin RxD Input Receive data input Transmit data pin TxD Output Transmit data output Rev. 3.00 Sep 14, 2005 page 535 of 910 REJ09B0258-0300 Section 14 Smart Card Interface 14.1.4 Register Configuration The smart card interface has the internal registers listed in table 14.2. The BRR, TDR, and RDR registers have their normal serial communication interface functions, as described in section 13, Serial Communication Interface. Table 14.2 Smart Card Interface Registers Channel Address*1 Name Abbreviation R/W Initial Value 0 H'FFFB0 Serial mode register SMR R/W H'00 H'FFFB1 Bit rate register BRR R/W H'FF H'FFFB2 Serial control register SCR R/W H'00 H'FF 1 2 H'FFFB3 Transmit data register TDR R/W H'FFFB4 Serial status register SSR R/(W)*2 H'84 H'FFFB5 Receive data register RDR R H'00 H'FFFB6 Smart card mode register SCMR R/W H'F2 H'FFFB8 Serial mode register SMR R/W H'00 H'FFFB9 Bit rate register BRR R/W H'FF H'FFFBA Serial control register SCR R/W H'00 H'FFFBB Transmit data register TDR R/W H'FF 2 H'FFFBC Serial status register SSR R/(W)* H'84 H'FFFBD Receive data register RDR R H'00 H'FFFBE Smart card mode register SCMR R/W H'F2 H'FFFC0 Serial mode register SMR R/W H'00 H'FFFC1 Bit rate register BRR R/W H'FF H'FFFC2 Serial control register SCR R/W H'00 H'FFFC3 Transmit data register TDR R/W H'FF 2 H'FFFC4 Serial status register SSR R/(W)* H'FFFC5 Receive data register RDR R H'00 H'FFFC6 Smart card mode register SCMR R/W H'F2 Notes: 1. Lower 20 bits of the address in advanced mode. 2. Only 0 can be written in bits 7 to 3, to clear the flags. Rev. 3.00 Sep 14, 2005 page 536 of 910 REJ09B0258-0300 H'84 Section 14 Smart Card Interface 14.2 Register Descriptions This section describes the new or modified registers and bit functions in the smart card interface. 14.2.1 Smart Card Mode Register (SCMR) SCMR is an 8-bit readable/writable register that selects smart card interface functions. 7 6 5 4 3 2 1 0 -- -- -- -- SDIR SINV -- SMIF Initial value 1 1 1 1 0 0 1 0 Read/Write -- -- -- -- R/W R/W -- R/W Bit Reserved bits Reserved bit Smart card interface mode select Enables or disables the smart card interface function Smart card data invert Inverts data logic levels Smart card data transfer direction Selects the serial/parallel conversion format SCMR is initialized to H'F2 by a reset and in standby mode. Bits 7 to 4--Reserved: Read-only bits, always read as 1. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.*1 Bit 3 SDIR Description 0 TDR contents are transmitted LSB-first (Initial value) Receive data is stored LSB-first in RDR 1 TDR contents are transmitted MSB-first Receive data is stored MSB-first in RDR Rev. 3.00 Sep 14, 2005 page 537 of 910 REJ09B0258-0300 Section 14 Smart Card Interface Bit 2--Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used in combination with the SDIR bit to communicate with inverse-convention cards.*2 The SINV bit does not affect the logic level of the parity bit. For parity settings, see section 14.3.4, Register Settings. Bit 2 SINV Description 0 Unmodified TDR contents are transmitted (Initial value) Receive data is stored unmodified in RDR 1 Inverted TDR contents are transmitted Receive data is inverted before storage in RDR Bit 1--Reserved: Read-only bit, always read as 1. Bit 0--Smart Card Interface Mode Select (SMIF): Enables the smart card interface function. Bit 0 SMIF Description 0 Smart card interface function is disabled 1 Smart card interface function is enabled (Initial value) Notes: 1. The function for switching between LSB-first and MSB-first mode can also be used with the normal serial communication interface. Note that when the communication format data length is set to 7 bits and MSB-first mode is selected for the serial data to be transferred, bit 0 of TDR is not transmitted, and only bits 7 to 1 of the received data are valid. 2. The data logic level inversion function can also be used with the normal serial communication interface. Note that, when inverting the serial data to be transferred, parity transmission and parity checking is based on the number of high-level periods at the serial data I/O pin, and not on the register value. Rev. 3.00 Sep 14, 2005 page 538 of 910 REJ09B0258-0300 Section 14 Smart Card Interface 14.2.2 Serial Status Register (SSR) The function of SSR bit 4 is modified in smart card interface mode. This change also causes a modification to the setting conditions for bit 2 (TEND). Bit 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Transmit end Status flag indicating end of transmission Error signal status (ERS) Status flag indicating that an error signal has been received Note: * Only 0 can be written, to clear the flag. Bits 7 to 5: These bits operate as in normal serial communication. For details see section 13.2.7, Serial Status Register (SSR). Bit 4--Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of the error signal sent from the receiving device to the transmitting device. The smart card interface does not detection framing errors. Bit 4 ERS Description 0 Indicates normal transmission, with no error signal returned (Initial value) [Clearing conditions] The chip is reset, or enters standby mode or module stop mode Software reads ERS while it is set to 1, then writes 0. 1 Indicates that the receiving device sent an error signal reporting a parity error [Setting condition] A low error signal was sampled. Note: Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous value. Rev. 3.00 Sep 14, 2005 page 539 of 910 REJ09B0258-0300 Section 14 Smart Card Interface Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13.2.7, Serial Status Register (SSR). The setting conditions for transmit end (TEND), however, are modified as follows. Bit 2 TEND Description 0 Transmission is in progress [Clearing conditions] Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag. The DMAC or DTC writes data in TDR. 1 End of transmission [Setting conditions] (Initial value) The chip is reset or enters standby mode. The TE bit and FER/ERS bit are both cleared to 0 in SCR. TDRE is 1 and FER/ERS is 0 at a time 2.5 etu after the last bit of a 1-byte serial character is transmitted (normal transmission). Note: etu (Elementary time unit: the time for transfer of one bit) 14.2.3 Serial Mode Register (SMR) The function of SMR bit 7 is modified in smart card interface mode. This change also causes a modification to the function of bits 1 and 0 in the serial control register (SCR). 7 6 5 4 3 2 1 0 GM CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Rev. 3.00 Sep 14, 2005 page 540 of 910 REJ09B0258-0300 Section 14 Smart Card Interface Bit 7--GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the TEND flag that indicates completion of transmission, and the type of clock output used. The details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in the serial control register (SCR). Bit 7 GM Description 0 Normal smart card interface mode operation The TEND flag is set 12.5 etu after the beginning of the start bit. Clock output on/off control only. 1 (Initial value) GSM mode smart card interface mode operation The TEND flag is set 11.0 etu after the beginning of the start bit. Clock output on/off and fixed-high/fixed-low control. Note: etu (Elementary time unit: the time for transfer of one bit) Bits 6 to 0: These bits operate as in normal serial communication. For details see section 13.2.5, Serial Mode Register (SMR). 14.2.4 Serial Control Register (SCR) The function of SCR bits 1 and 0 is modified in smart card interface mode 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Bits 7 to 2: These bits operate as in normal serial communication. For details see section 13.2.6, Serial Control Register (SCR). Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. Rev. 3.00 Sep 14, 2005 page 541 of 910 REJ09B0258-0300 Section 14 Smart Card Interface Bit 7 GM Bit 1 CKE1 Bit 0 CKE0 Description 0 0 0 Internal clock/SCK pin is I/O port 1 Internal clock/SCK pin is clock output 0 Internal clock/SCK pin is fixed at low output 1 Internal clock/SCK pin is clock output 0 Internal clock/SCK pin is fixed at high output 1 Internal clock/SCK pin is clock output 1 1 14.3 Operation 14.3.1 Overview (Initial value) The main features of the smart card interface are as follows. * One frame consists of 8-bit data plus a parity bit. * In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of one bit) is provided between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for a1 etu period 10.5 etu after the start bit. * If an error signal is detected during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. * Only asynchronous communication is supported; there is no synchronous communication function. 14.3.2 Pin Connections Figure 14.2 shows a pin connection diagram for the smart card interface. In communication with a smart card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should both be connected to this line. The data transmission line should be pulled up to VCC with a resistor. When the smart card uses the clock generated on the smart card interface, the SCK pin output is input to the CLK pin of the smart card. If the smart card uses an internal clock, this connection is unnecessary. The reset signal should be output from one of the H8/3068F's generic ports. Rev. 3.00 Sep 14, 2005 page 542 of 910 REJ09B0258-0300 Section 14 Smart Card Interface In addition to these pin connections, power and ground connections will normally also be necessary. VCC TxD RxD I/O Data line SCK H8/3068F chip Clock line Px (port) Reset line CLK RST Smart card Card-processing device Figure 14.2 Smart Card Interface Connection Diagram Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a smart card. Rev. 3.00 Sep 14, 2005 page 543 of 910 REJ09B0258-0300 Section 14 Smart Card Interface 14.3.3 Data Format Figure 14.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting device to request retransmission of the data. In transmission, the error signal is sampled and the same data is retransmitted if the error signal is low. No parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp D7 Dp Output from transmitting device Parity error Ds D0 D1 D2 D3 D4 D5 D6 DE Output from transmitting device Legend Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Output from receiving device Figure 14.3 Smart Card Interface Data Format The operating sequence is as follows. 1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. 2. The transmitting device starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). 3. With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. 4. The receiving device carries out a parity check. If there is no parity error and the data is received normally, the receiving device waits for reception of the next data. If a parity error occurs, however, the receiving device outputs an error signal (DE, low-level) to request Rev. 3.00 Sep 14, 2005 page 544 of 910 REJ09B0258-0300 Section 14 Smart Card Interface retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving device places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. 5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data frame. If it receives an error signal, however, it returns to step 2 and transmits the same data again. 14.3.4 Register Settings Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described in this section. Table 14.3 Smart Card Interface Register Settings Bit 1 Register Address* Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMR H'FFFB0 GM 0 1 O/E 1 0 CKS1 CKS0 BRR H'FFFB1 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 2 SCR H'FFFB2 TIE RIE TE RE 0 0 CKE1* CKE0 TDR H'FFFB3 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SSR H'FFFB4 TDRE RDRF ORER ERS PER TEND 0 0 RDR H'FFFB5 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 SCMR H'FFFB6 -- -- -- -- SDIR SINV -- SMIF Notes: -- Unused bit. 1. Lower 20 bits of the address in advanced mode. 2. When GM is cleared to 0 in SMR, the CKE1 bit must also be cleared to 0. Serial Mode Register (SMR) Settings: Clear the GM bit to 0 when using the normal smart card interface mode, or set to 1 when using GSM mode. Clear the O/E bit to 0 if the smart card is of the direct convention type, or set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator. See section 14.3.5, Clock. Bit Rate Register (BRR) Settings: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of calculating the value to be set. Serial Control Register (SCR) Settings: The TIE, RIE, TE, and RE bits have their normal serial communication functions. See section 13, Serial Communication Interface, for details. The CKE1 and CKE0 bits specify clock output. To disable clock output, clear these bits to 00; to enable Rev. 3.00 Sep 14, 2005 page 545 of 910 REJ09B0258-0300 Section 14 Smart Card Interface clock output, set these bits to 01. Clock output is not performed when the GM bit is set to 1 in SMR. Clock output can also be fixed low or high. Smart Card Mode Register (SCMR) Settings: Clear both the SDIR bit and SINV bit cleared to 0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention type. To use the smart card interface, set the SMIF bit to 1. The register settings and examples of starting character waveforms are shown below for two smart cards, one following the direct convention and one the inverse convention. 1. Direct Convention (SDIR = SINV = O/E = 0) (Z) A Z Z A Z Z Z A A Z Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (Z) State With the direct convention type, the logic 0 level corresponds to state Z and the logic 1 level to state A, and transfer is performed in LSB-first order. In the example above, the first character data is H'3B. The parity bit is 1, following the even parity rule designated for smart cards. 2. Indirect Convention (SDIR = SINV = O/E = 1) (Z) A Z Z A A A A A A Z Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp (Z) State With the indirect convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in MSB-first order. In the example above, the first character data is H'3F. The parity bit is 0, corresponding to state Z, following the even parity rule designated for smart cards. In the H8/3068F, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR must be set to odd parity mode. This applies to both transmission and reception. Rev. 3.00 Sep 14, 2005 page 546 of 910 REJ09B0258-0300 Section 14 Smart Card Interface 14.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for calculating the bit rate is shown below. Table 14.5 shows some sample bit rates. If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= x 106 1488 x 22n-1 x (N + 1) where, N: BRR setting (0 N 255) B: Bit rate (bit/s) : Operating frequency (MHz) n: See table 14.4 Table 14.4 n-Values of CKS1 and CKS0 Settings n CKS1 CKS0 0 0 0 1 2 1 1 0 3 1 Note: * If the gear function is used to divide the clock frequency, use the divided frequency to calculate the bit rate. The equation above applies directly to 1/1 frequency division. Table 14.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0) (MHz) N 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5 1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8 2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5 Note: Bit rates are rounded off to one decimal place. Rev. 3.00 Sep 14, 2005 page 547 of 910 REJ09B0258-0300 Section 14 Smart Card Interface The following equation calculates the bit rate register (BRR) setting from the operating frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error. N= 1488 x 22n-1 x B x 106 - 1 Table 14.6 BRR Settings for Typical Bit Rates (bits/s) (When n = 0) (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 bit/s N Error N Error N Error N Error N Error N Error N Error 9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 Table 14.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface Mode) (MHz) Maximum Bit Rate (bits/s) N n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 The bit rate error is given by the following equation: Error (%) = 1488 x 22n-1 x B x (N + 1) Rev. 3.00 Sep 14, 2005 page 548 of 910 REJ09B0258-0300 x 106 - 1 x 100 Section 14 Smart Card Interface 14.3.6 Transmitting and Receiving Data Initialization: Before transmitting or receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits to 0 in the serial control register (SCR). 2. Clear error flags FER/ERS, PER, and ORER to 0 in the serial status register (SSR). 3. Set the parity bit (O/E) and baud rate generator select bits (CKS1 and CKS0) in the serial mode register (SMR). Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCMR). When the SMIF bit is set to 1, the TxD pin and RxD pin are both switched from port to SCI pin functions and go to the high-impedance state. 5. Set a value corresponding to the desired bit rate in the bit rate register (BRR). 6. Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE, and CKE1 bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Transmitting Serial Data: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 14.5 shows a sample transmission processing flowchart. 1. 2. 3. 4. Perform smart card interface mode initialization as described in Initialization above. Check that the FER/ERS error flag is cleared to 0 in SSR. Repeat steps 2 and 3 until it can be confirmed that the TEND flag is set to 1 in SSR. Write the transmit data in TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. 5. To continue transmitting data, go back to step 2. 6. To end transmission, clear the TE bit to 0. The above processing may include interrupt handling DMA transfer. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) will be requested. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (ERI) will be requested. The timing of TEND flag setting depends on the GM bit in SMR (see figure 14.4). Rev. 3.00 Sep 14, 2005 page 549 of 910 REJ09B0258-0300 Section 14 Smart Card Interface If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer by DMAC in this section. Serial data Dp Ds DE Guard time (1) GM = 0 TEND 12.5 etu (2) GM = 1 TEND 11.0 etu Note: etu (Elementary time unit: the time for transfer of one bit) Figure 14.4 Timing of TEND Flag Setting Rev. 3.00 Sep 14, 2005 page 550 of 910 REJ09B0258-0300 Section 14 Smart Card Interface Start Initialization Start transmitting No FER/ERS = 0? Yes Error handling No TEND = 1? Yes Write transmit data in TDR, and clear TDRE flag to 0 in SSR No All data transmitted? Yes No FER/ERS = 0? Yes Error handling No TEND = 1? Yes Clear TE bit to 0 End Figure 14.5 Sample Transmission Processing Flowchart Rev. 3.00 Sep 14, 2005 page 551 of 910 REJ09B0258-0300 Section 14 Smart Card Interface TSR (shift register) TDR 1. Data write Data 1 2. Transfer from TDR to TSR Data 1 3. Serial data output Data 1 Data 1 Data remains in TDR Data 1 I/O signal output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps 2 and 3 above are repeated until the TEND flag is set. Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the retransmit data to be transmitted next has been completed. Figure 14.6 Relation Between Transmit Operation and Internal Registers I/O data Ds Da Db Dc Dd De Df Dg Dh Dp DE Guard time TXI (TEND interrupt) 12.5 etu 11.0 etu When GM = 0 When GM = 1 Note: etu (Elementary time unit: the time for transfer of one bit) Figure 14.7 Timing of TEND Flag Setting Receiving Serial Data: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 14.8 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the ORER flag and PER flag are cleared to 0 in SSR. If either is set, perform the appropriate receive error handling, then clear both the ORER and the PER flag to 0. 3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1. 4. Read the receive data from RDR. Rev. 3.00 Sep 14, 2005 page 552 of 910 REJ09B0258-0300 Section 14 Smart Card Interface 5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2. 6. To end reception, clear the RE bit to 0. Start Initialization Start receiving ORER = 0 and PER = 0? No Yes Error handling No RDRF = 1? Yes Read RDR and clear RDRF flag to 0 in SSR No All data received? Yes Clear RE bit to 0 Figure 14.8 Sample Reception Processing Flowchart The above procedure may include interrupt handling and DMA transfer. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) will be requested. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) will be requested. If the RXI interrupt activates the DMAC, the number of bytes designated in the DMAC will be transferred, skipping receive data in which an error occurred. Rev. 3.00 Sep 14, 2005 page 553 of 910 REJ09B0258-0300 Section 14 Smart Card Interface For details, see Interrupt Operations and Data Transfer by DMAC in this section. If a parity error occurs during reception and the PER flag is set to 1, the received data is transferred to RDR, so the erroneous data can be read. Switching Modes: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE to 0 and setting TE to 1. The RDRF, PER, or ORER flag can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output: When the GM bit is set to 1 in SMR, clock output can be fixed by means of the CKE1 and CKE0 bits in SCR. The minimum clock pulse width can be set to the specified width in this case. Figure 14.9 shows the timing for fixing clock output. In this example, GM = 1, CKE1 = 0, and the CKE0 bit is controlled. Specified pulse width Specified pulse width CKE1 value SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 14.9 Timing for Fixing Cock Output Interrupt Operations: The smart card interface has three interrupt sources: transmit-data-empty (TXI), transmit/receive-error (ERI), and receive-data-full (RXI). The transmit-end interrupt request (TEI) is not available in smart card mode. A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or ERS flag is set to 1 in SSR. These relationships are shown in table 14.8. Rev. 3.00 Sep 14, 2005 page 554 of 910 REJ09B0258-0300 Section 14 Smart Card Interface Table 14.8 Smart Card Interface Mode Operating States and Interrupt Sources Operating State Transmit Mode Receive Mode Normal operation Flag Enable Bit Interrupt Source DMAC Activation TEND TIE TXI Available Error ERS RIE ERI Not available Normal operation RDRF RIE RXI Available Error PER, ORER RIE ERI Not available Data Transfer by DMAC: The DMAC can be used to transmit and receive data in smart card mode, as in normal SCI operations. In transmit mode, when the TEND flag is set to 1 in SSR, the TDRE flag is set simultaneously, generating a TXI interrupt. If the TXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the TXI request and will transfer the next transmit data. This data transfer by the DMAC automatically clears the TDRE and TEND flags to 0. In the event of an error, the SCI automatically retransmits the same data, keeping the TEND flag cleared to 0 so that the DMAC is not activated. The SCI and DMAC will therefore automatically transmit the designated number of bytes, including retransmission when an error occurs. When an error occurs, the ERS flag is not cleared automatically, so the RIE bit should be set to 1 to enable the error to generate an ERI request, and the ERI interrupt handler should clear ERS. When using the DMAC to transmit or receive, first set up and enable the DMAC, then make SCI settings. DMAC settings are described in section 7, DMA controller. In receive operations, an RXI interrupt is requested when the RDRF flag is set to 1 in SSR. If the RXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the RXI request and will transfer the received data. This data transfer by the DMAC automatically clears the RDRF flag to 0. When an error occurs, the RDRF flag is not set and an error flag is set instead. The DMAC is not activated. The ERI interrupt request is directed to the CPU. The ERI interrupt handler should clear the error flags. Rev. 3.00 Sep 14, 2005 page 555 of 910 REJ09B0258-0300 Section 14 Smart Card Interface Examples of Operation in GSM Mode: When switching between smart card interface mode and software standby mode, use the following procedures to maintain the clock duty cycle. * Switching from smart card interface mode to software standby mode 1. Set the P94 data register (DR) and data direction register (DDR) to the values for the fixed output state in software standby mode. 2. Write 0 in the TE and RE bits in the serial control register (SCR) to stop transmit/receive operations. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 in the CKE0 bit in SCR to stop the clock. 4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. Write H'00 in the serial mode register (SMR) and smart card mode register (SCMR). 6. Make the transition to the software standby state. * Returning from software standby mode to smart card interface mode 1. Clear the software standby state. 2. Set the CKE1 bit in SCR to the value for the fixed output state at the start of software standby (the current P94 pin state). 3. Set smart card interface mode and output the clock. Clock signal generation is started with the normal duty cycle. Software standby Normal operation (1) (2) (3) (4) (5) (6) Normal operation (1) (2) (3) Figure 14.10 Procedure for Stopping and Restarting the Clock Use the following procedure to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential. 2. Fix at the output specified by the CKE1 bit in SCR. 3. Set SMR and SCMR, and switch to smart card interface mode operation. 4. Set the CKE0 bit to 1 in SCR to start clock output. Rev. 3.00 Sep 14, 2005 page 556 of 910 REJ09B0258-0300 Section 14 Smart Card Interface 14.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing is shown in figure 14.11. 372 clocks 186 clocks 0 185 185 371 0 371 0 Internal base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 14.11 Receive Data Sampling Timing in Smart Card Interface Mode Rev. 3.00 Sep 14, 2005 page 557 of 910 REJ09B0258-0300 Section 14 Smart Card Interface The receive margin can therefore be expressed as follows. Receive margin in smart card interface mode: M = (0.5 - 1 ) - (L - 0.5) F - 2N M: N: D: L: F: D - 0.5 (1 + F) x 100% N Receive margin (%) Ratio of clock frequency to bit rate (N = 372) Clock duty cycle (L = 0 to 1.0) Frame length (L =10) Absolute deviation of clock frequency From the above equation, if F = 0 and D = 0.5, the receive margin is as follows. When D = 0.5 and F = 0: M = (0.5 - 1/2 x 372) x 100% = 49.866% Retransmission: Retransmission is performed by the SCI in receive mode and transmit mode as described below. * Retransmission when SCI is in Receive Mode Figure 14.12 illustrates retransmission when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit is automatically set to 1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER bit should be cleared to 0 in SSR before the next parity bit sampling timing. 2. The RDRF bit in SSR is not set for the frame in which the error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit is not set to 1 in SSR. 4. If no error is found when the received parity bit is checked, the receive operation is assumed to have been completed normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a DMA transfer activation source, the RDR contents can be read automatically. When the DMAC reads the RDR data, the RDRF flag is automatically cleared to 0. 5. When a normal frame is received, the data pin is held in the high-impedance state at the error signal transmission timing. Rev. 3.00 Sep 14, 2005 page 558 of 910 REJ09B0258-0300 Section 14 Smart Card Interface Frame n Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Frame n+1 Retransmitted frame DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 RDRF [2] [4] [1] [3] PER Figure 14.12 Retransmission in SCI Receive Mode * Retransmission when SCI is in Transmit Mode Figure 14.13 illustrates retransmission when the SCI is in transmit mode. 6. If an error signal is sent back from the receiving device after transmission of one frame is completed, the FER/ERS bit is set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity bit sampling timing. 7. The TEND bit in SSR is not set for the frame for which the error signal was received. 8. If an error signal is not sent back from the receiving device, the ERS flag is not set in SSR. 9. If an error signal is not sent back from the receiving device, transmission of one frame, including retransmission, is assumed to have been completed, and the TEND bit is set to 1 in SSR. If the TIE bit in SCR is set to the enable state, a TXI interrupt is requested. If TXI is enabled as a DMA transfer activation source, the next data can be written in TDR automatically. When the DMAC writes data in TDR, the TDRE bit is automatically cleared to 0. Frame n Frame n+1 Retransmitted frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer from TDR to TSR Transfer from TDR to TSR Transfer from TDR to TSR TEND [7] [9] ERS [6] [8] Figure 14.13 Retransmission in SCI Transmit Mode Rev. 3.00 Sep 14, 2005 page 559 of 910 REJ09B0258-0300 Section 14 Smart Card Interface Rev. 3.00 Sep 14, 2005 page 560 of 910 REJ09B0258-0300 Section 15 A/D Converter Section 15 A/D Converter 15.1 Overview The H8/3068F includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 20.6, Module Standby Function. 15.1.1 Features A/D converter features are listed below. * 10-bit resolution * Eight input channels * Selectable analog conversion voltage range The analog voltage conversion range can be programmed by input of an analog reference voltage at the VREF pin. * High-speed conversion Conversion time: maximum 3.5 s per channel (with 20 MHz system clock) * Two conversion modes Single mode: A/D conversion of one channel Scan mode: continuous conversion on one to four channels * Four 16-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. * Sample-and-hold function * Three conversion start sources The A/D converter can be activated by software, an external trigger, or an 8-bit timer compare match. * A/D interrupt requested at end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested. * DMA controller (DMAC) activation The DMAC can be activated at the end of A/D conversion. Rev. 3.00 Sep 14, 2005 page 561 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the A/D converter. Internal data bus AVSS AN 0 ADCR ADCSR ADDRD - AN 2 AN 4 ADDRC + AN 1 AN 3 ADDRB 10-bit D/A ADDRA VREF Successiveapproximations register AVCC Bus interface Module data bus Analog multiplexer AN 5 o/4 Comparator Control circuit Sample-andhold circuit o/8 AN 6 AN 7 ADI interrupt signal ADTRG Compare match A0 ADTE 8-bit timer TCSR0 Legend ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 15.1 A/D Converter Block Diagram Rev. 3.00 Sep 14, 2005 page 562 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.1.3 Input Pins Table 15.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference voltage. Table 15.1 A/D Converter Pins Pin Name Abbreviation I/O Function Analog power supply pin AVCC Input Analog power supply Analog ground pin AVSS Input Analog ground and reference voltage Reference voltage pin VREF Input Analog reference voltage Analog input pin 0 AN0 Input Group 0 analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input A/D external trigger input pin ADTRG Input Group 1 analog inputs External trigger input for starting A/D conversion Rev. 3.00 Sep 14, 2005 page 563 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.1.4 Register Configuration Table 15.2 summarizes the A/D converter's registers. Table 15.2 A/D Converter Registers Address*1 Name Abbreviation R/W Initial Value H'FFFE0 A/D data register A H ADDRAH R H'00 H'FFFE1 A/D data register A L ADDRAL R H'00 H'FFFE2 A/D data register B H ADDRBH R H'00 H'FFFE3 A/D data register B L ADDRBL R H'00 H'FFFE4 A/D data register C H ADDRCH R H'00 H'FFFE5 A/D data register C L ADDRCL R H'00 H'FFFE6 A/D data register D H ADDRDH R H'00 H'FFFE7 A/D data register D L ADDRDL R H'00 2 H'FFFE8 A/D control/status register ADCSR R/(W)* H'00 H'FFFE9 A/D control register ADCR R/W H'7E Notes: 1. Lower 20 bits of the address in advanced mode. 2. Only 0 can be written in bit 7, to clear the flag. Rev. 3.00 Sep 14, 2005 page 564 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.2 Register Descriptions 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ADDRn 14 12 10 8 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- -- -- -- -- -- 15 Bit 13 11 9 7 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write (n = A to D) R R R R R R R R R R R R R R R R A/D conversion data 10-bit data giving an A/D conversion result Reserved bits The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D data register are reserved bits that are always read as 0. Table 15.3 indicates the pairings of analog input channels and A/D data registers. The CPU can always read and write the A/D data registers. The upper byte can be read directly, but the lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU Interface. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Table 15.3 Analog Input Channels and A/D Data Registers Analog Input Channel Group 0 Group 1 A/D Data Register AN0 AN4 ADDRA AN1 AN5 ADDRB AN2 AN6 ADDRC AN3 AN7 ADDRD Rev. 3.00 Sep 14, 2005 page 565 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.2.2 A/D Control/Status Register (ADCSR) Bit 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable Enables and disables A/D end interrupts A/D end flag Indicates end of A/D conversion Note: * Only 0 can be written, to clear the flag. ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Rev. 3.00 Sep 14, 2005 page 566 of 910 REJ09B0258-0300 Section 15 A/D Converter Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 ADF Description 0 [Clearing condition] Read ADF when ADF =1, then write 0 in ADF. DMAC activated by ADI interrupt. 1 [Setting conditions] Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels (Initial value) Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6 ADIE Description 0 A/D end interrupt request (ADI) is disabled 1 A/D end interrupt request (ADI) is enabled (Initial value) Bit 5--A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin, or by an 8-bit timer compare match. Bit 5 ADST Description 0 A/D conversion is stopped 1 Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends. Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode. (Initial value) Rev. 3.00 Sep 14, 2005 page 567 of 910 REJ09B0258-0300 Section 15 A/D Converter Bit 4--Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4 SCAN Description 0 Single mode 1 Scan mode (Initial value) Bit 3--Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before switching the conversion time. Bit 3 CKS Description 0 Conversion time = 134 states (maximum) 1 Conversion time = 70 states (maximum) (Initial value) Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Group Selection Channel Selection Description CH2 CH1 CH0 Single Mode Scan Mode 0 0 0 AN0 (Initial value) AN0 1 AN1 AN0, AN1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 0 AN4 AN4 1 AN5 AN4, AN5 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 1 1 0 1 Rev. 3.00 Sep 14, 2005 page 568 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.2.3 A/D Control Register (ADCR) Bit 7 6 5 4 3 2 1 0 TRGE -- -- -- -- -- -- -- Initial value 0 1 1 1 1 1 1 0 Read/Write R/W -- -- -- -- -- -- R/W Reserved bits Trigger enable Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by external trigger input or an 8-bit timer compare match signal. ADCR is initialized to H'7F by a reset and in standby mode. Bit 7--Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match. Bit 7 TRGE Description 0 Starting of A/D conversion by an external trigger or 8-bit timer compare match is disabled 1 A/D conversion is started at the falling edge of the external trigger signal (ADTRG) or by an 8-bit timer compare match (Initial value) External trigger pin and 8-bit timer selection are performed by the 8-bit timer. For details, see section 10, 8-Bit Timers. Bits 6 to 1--Reserved: These bits cannot be modified and are always read as 1. Bit 0--Reserved: This bit can be read or written, but must not be set to 1. Rev. 3.00 Sep 14, 2005 page 569 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 15.2 shows the data flow for access to an A/D data register. Rev. 3.00 Sep 14, 2005 page 570 of 910 REJ09B0258-0300 Section 15 A/D Converter Upper-byte read CPU (H'AA) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower-byte read CPU (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 15.2 A/D Data Register Access Operation (Reading H'AA40) Rev. 3.00 Sep 14, 2005 page 571 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 15.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF. When the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 15.3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADCSR, then writes 0 in the ADF flag. 6. The routine reads and processes the conversion result (ADDRB). 7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated. Rev. 3.00 Sep 14, 2005 page 572 of 910 REJ09B0258-0300 Note: * Vertical arrows ( ) indicate instructions executed by software. ADDRD ADDRC ADDRB Read conversion result A/D conversion result (2) Idle Clear* A/D conversion result (1) A/D conversion (2) Set* Read conversion result Idle State of channel 3 (AN 3) ADDRA Idle State of channel 2 (AN 2) Idle Clear* State of channel 1 (AN 1) A/D conversion (1) Set* Idle Idle A/D conversion starts State of channel 0 (AN 0) ADF ADST ADIE Set* Section 15 A/D Converter Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 3.00 Sep 14, 2005 page 573 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are described next. Figure 15.4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev. 3.00 Sep 14, 2005 page 574 of 910 REJ09B0258-0300 Idle Idle Idle A/D conversion (1) Transfer Idle A/D conversion (3) Idle Idle Clear*1 Idle A/D conversion result (4) Idle A/D conversion (5)*2 A/D conversion result (3) A/D conversion result (2) A/D conversion (4) A/D conversion result (1) A/D conversion (2) Idle A/D conversion time Continuous A/D conversion Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. ADDRD ADDRC ADDRB ADDRA State of channel 3 (AN 3) State of channel 2 (AN 2) State of channel 1 (AN 1) State of channel 0 (AN 0) ADF ADST Set*1 Clear*1 Section 15 A/D Converter Figure 15.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) Rev. 3.00 Sep 14, 2005 page 575 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D conversion timing. Table 15.4 indicates the A/D conversion time. As indicated in figure 15.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15.4. In scan mode, the values given in table 15.4 apply to the first conversion. In the second and subsequent conversions the conversion time is fixed at 128 states when CKS = 0 or 66 states when CKS = 1. Rev. 3.00 Sep 14, 2005 page 576 of 910 REJ09B0258-0300 Section 15 A/D Converter (1) Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend (1): ADCSR write cycle (2): ADCSR address tD : Synchronization delay t SPL : Input sampling time t CONV: A/D conversion time Figure 15.5 A/D Conversion Timing Table 15.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Min Typ Max Min Typ Max Synchronization delay tD 6 -- 9 4 -- 5 Input sampling time tSPL -- 31 -- -- 15 -- A/D conversion time tCONV 131 -- 134 69 -- 70 Note: Values in the table are numbers of states. Rev. 3.00 Sep 14, 2005 page 577 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR and the 8-bit timer's ADTE bit is cleared to 0, external trigger input is enabled at the ADTRG pin. A high-tolow transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1 by software. Figure 15.6 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 15.6 External Trigger Input Timing Rev. 3.00 Sep 14, 2005 page 578 of 910 REJ09B0258-0300 Section 15 A/D Converter 15.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. The ADI interrupt request can be designated as a DMAC activation source. In this case, an interrupt request is not sent to the CPU. 15.6 Usage Notes When using the A/D converter, note the following points: 1. Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins should be in the range AVSS ANn VREF. 2. Relationships of AVCC and AVSS to VCC and VSS: AVCC, AVSS, VCC, and VSS should be related as follows: AVSS = VSS. AVCC and AVSS must not be left open, even if the A/D converter is not used. 3. VREF Programming Range: The reference voltage input at the VREF pin should be in the range VREF AVCC. 4. Note on Board Design: In board layout, separate the digital circuits from the analog circuits as much as possible. Particularly avoid layouts in which the signal lines of digital circuits cross or closely approach the signal lines of analog circuits. Induction and other effects may cause the analog circuits to operate incorrectly, or may adversely affect the accuracy of A/D conversion. The analog input signals (AN0 to AN7), analog reference voltage (VREF), and analog supply voltage (AVCC) must be separated from digital circuits by the analog ground (AVSS). The analog ground (AVSS) should be connected to a stable digital ground (VSS) at one point on the board. 5. Note on Noise: To prevent damage from surges and other abnormal voltages at the analog input pins (AN0 to AN7) and analog reference voltage pin (VREF), connect a protection circuit like the one in figure 15.7 between AVCC and AVSS. The bypass capacitors connected to AVCC and VREF and the filter capacitors connected to AN0 to AN7 must be connected to AVSS. If filter capacitors like the ones in figure 15.7 are connected, the voltage values input to the analog input pins (AN0 to AN7) will be smoothed, which may give rise to error. Error can also occur if A/D conversion is frequently performed in scan mode so that the current that charges and discharges the capacitor in the sample-and-hold circuit of the A/D converter becomes greater than that input to the analog input pins via input impedance Rin. The circuit constants should therefore be selected carefully. Rev. 3.00 Sep 14, 2005 page 579 of 910 REJ09B0258-0300 Section 15 A/D Converter AVCC VREF 100 Rin*2 *1 AN0 to AN7 *1 0.1 F AVSS Notes: 1. 10 F 2. 0.01 F Rin: input impedance Figure 15.7 Example of Analog Input Protection Circuit Table 15.5 Analog Input Pin Ratings Item min max Unit Analog input capacitance -- 20 pF Allowable signal-source impedance -- 10* k Note: * When conversion time = 134 states, VCC = 4.0 V to 5.5 V, and o 13 Mhz. For details see section 21, Electrical Characteristics. 10 k AN0 to AN7 To A/D converter 20 pF Figure 15.8 Analog Input Pin Equivalent Circuit Note: Numeric values are approximate, except in table 15.5 Rev. 3.00 Sep 14, 2005 page 580 of 910 REJ09B0258-0300 Section 15 A/D Converter 6. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/3068F is defined as follows: * Resolution: Digital output code length of A/D converter * Offset error: Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 15.10) * Full-scale error: Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from 1111111110 to 1111111111 (figure 15.10) * Quantization error: Intrinsic error of the A/D converter; 1/2 LSB (figure 15.9) * Nonlinearity error: Deviation from ideal A/D conversion characteristic in range from zero volts to full scale, exclusive of offset error, full-scale error, and quantization error. * Absolute accuracy: Deviation of digital value from analog input value, including offset error, full-scale error, quantization error, and nonlinearity error. Digital output 111 Ideal A/D conversion characteristic 110 101 100 011 010 Quantization error 001 000 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage Figure 15.9 A/D Converter Accuracy Definitions (1) Rev. 3.00 Sep 14, 2005 page 581 of 910 REJ09B0258-0300 Section 15 A/D Converter Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 15.10 A/D Converter Accuracy Definitions (2) 7. Allowable Signal-Source Impedance: The analog inputs of the H8/3068F are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 k. The reason for this rating is that it enables the input capacitor in the sample-and-hold circuit in the A/D converter to charge within the sampling time. If the sensor output impedance exceeds 10 k, charging may be inadequate and the accuracy of A/D conversion cannot be guaranteed. If a large external capacitor is provided in single mode, then the internal 10-k input resistance becomes the only significant load on the input. In this case the impedance of the signal source is not a problem. A large external capacitor, however, acts as a low-pass filter. This may make it impossible to track analog signals with high dv/dt (e.g. a variation of 5 mV/s) (figure 15.11). To convert high-speed analog signals or to use scan mode, insert a low-impedance buffer. 8. Effect on Absolute Accuracy: Attaching an external capacitor creates a coupling with ground, so if there is noise on the ground line, it may degrade absolute accuracy. The capacitor must be connected to an electrically stable ground, such as AVSS. Rev. 3.00 Sep 14, 2005 page 582 of 910 REJ09B0258-0300 Section 15 A/D Converter If a filter circuit is used, be careful of interference with digital signals on the same board, and make sure the circuit does not act as an antenna. H8/3067 Group Sensor output impedance Sensor input 10 k Up to 10 k Low-pass filter C Up to 0.1F Equivalent circuit of A/D converter Cin = 15 pF 20 pF Figure 15.11 Analog Input Circuit (Example) Rev. 3.00 Sep 14, 2005 page 583 of 910 REJ09B0258-0300 Section 15 A/D Converter Rev. 3.00 Sep 14, 2005 page 584 of 910 REJ09B0258-0300 Section 16 D/A Converter Section 16 D/A Converter 16.1 Overview The H8/3068F includes a D/A converter with two channels. 16.1.1 Features D/A converter features are listed below. * * * * * Eight-bit resolution Two output channels Conversion time: maximum 10 s (with 20-pF capacitive load) Output voltage: 0 V to VREF D/A outputs can be sustained in software standby mode Rev. 3.00 Sep 14, 2005 page 585 of 910 REJ09B0258-0300 Section 16 D/A Converter 16.1.2 Block Diagram Bus interface Figure 16.1 shows a block diagram of the D/A converter. Module data bus Internal data bus DACR 8-bit D/A DADR1 DA 0 DADR0 AVCC DASTCR VREF DA 1 AVSS Legend DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 DASTCR: D/A standby control register Control circuit Figure 16.1 D/A Converter Block Diagram 16.1.3 Input/Output Pins Table 16.1 summarizes the D/A converter's input and output pins. Table 16.1 D/A Converter Pins Pin Name Abbreviation I/O Function Analog power supply pin AVCC Input Analog power supply and reference voltage Analog ground pin AVSS Input Analog ground and reference voltage Analog output pin 0 DA0 Output Analog output, channel 0 Analog output pin 1 DA1 Output Analog output, channel 1 Input Analog reference voltage Reference voltage input pin VREF Rev. 3.00 Sep 14, 2005 page 586 of 910 REJ09B0258-0300 Section 16 D/A Converter 16.1.4 Register Configuration Table 16.2 summarizes the D/A converter's registers. Table 16.2 D/A Converter Registers Address* Name Abbreviation R/W Initial Value H'FFF9C D/A data register 0 DADR0 R/W H'00 H'FFF9D D/A data register 1 DADR1 R/W H'00 H'FFF9E D/A control register DACR R/W H'1F H'EE01A D/A standby control register DASTCR R/W H'FE Note: * Lower 20 bits of the address in advanced mode. Rev. 3.00 Sep 14, 2005 page 587 of 910 REJ09B0258-0300 Section 16 D/A Converter 16.2 Register Descriptions 16.2.1 D/A Data Registers 0 and 1 (DADR0/1) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins. The D/A data registers are initialized to H'00 by a reset and in standby mode. When the DASTE bit is set to 1 in the D/A standby control register (DASTCR), the D/A registers are not initialized in software standby mode. 16.2.2 D/A Control Register (DACR) Bit 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE -- -- -- -- -- Initial value 0 0 0 1 1 1 1 1 Read/Write R/W R/W R/W -- -- -- -- -- D/A enable Controls D/A conversion D/A output enable 0 Controls D/A conversion and analog output D/A output enable 1 Controls D/A conversion and analog output DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a reset and in standby mode. When the DASTE bit is set to 1 in DASTCR, the DACR is not initialized in software standby mode. Rev. 3.00 Sep 14, 2005 page 588 of 910 REJ09B0258-0300 Section 16 D/A Converter Bit 7--D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 Description 0 DA1 analog output is disabled 1 Channel-1 D/A conversion and DA1 analog output are enabled Bit 6--D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description 0 DA0 analog output is disabled 1 Channel-0 D/A conversion and DA0 analog output are enabled Bit 5--D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1. When the DAE bit is cleared to 0, analog conversion is controlled independently in channels 0 and 1. When the DAE bit is set to 1, analog conversion is controlled together in channels 0 and 1. Output of the conversion results is always controlled independently by DAOE0 and DAOE1. Bit 7 DAOE1 Bit 6 Bit 5 DAOE0 DAE Description 0 0 -- D/A conversion is disabled in channels 0 and 1 1 0 D/A conversion is enabled in channel 0 D/A conversion is disabled in channel 1 1 1 0 0 D/A conversion is enabled in channels 0 and 1 D/A conversion is disabled in channel 0 D/A conversion is enabled in channel 1 1 1 D/A conversion is enabled in channels 0 and 1 -- D/A conversion is enabled in channels 0 and 1 When the DAE bit is set to 1, even if bits DAOE0 and DAOE1 in DACR and the ADST bit in ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D and D/A conversion. Bits 4 to 0--Reserved: These bits cannot be modified and are always read as 1. Rev. 3.00 Sep 14, 2005 page 589 of 910 REJ09B0258-0300 Section 16 D/A Converter 16.2.3 D/A Standby Control Register (DASTCR) DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software standby mode. Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- DASTE Initial value 1 1 1 1 1 1 1 0 Read/Write -- -- -- -- -- -- -- R/W Reserved bits D/A standby enable Enables or disables D/A output in software standby mode DASTCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 1--Reserved: These bits cannot be modified and are always read as 1. Bit 0--D/A Standby Enable (DASTE): Enables or disables D/A output in software standby mode. Bit 0 DASTE Description 0 D/A output is disabled in software standby mode 1 D/A output is enabled in software standby mode Rev. 3.00 Sep 14, 2005 page 590 of 910 REJ09B0258-0300 (Initial value) Section 16 D/A Converter 16.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1. An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 16.2. 1. Data to be converted is written in DADR0. 2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The converted result is output after the conversion time. The output value is DADR contents x VREF 256 Output of this conversion result continues until the value in DADR0 is modified or the DAOE0 bit is cleared to 0. 3. If the DADR0 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin. Rev. 3.00 Sep 14, 2005 page 591 of 910 REJ09B0258-0300 Section 16 D/A Converter DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Address Conversion data 1 DADR0 Conversion data 2 DAOE0 DA 0 Conversion result 2 Conversion result 1 High-impedance state t DCONV t DCONV Legend t DCONV : D/A conversion time Figure 16.2 Example of D/A Converter Operation 16.4 D/A Output Control In the H8/3068F, D/A converter output can be enabled or disabled in software standby mode. When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby mode. The D/A converter registers retain the values they held prior to the transition to software standby mode. When D/A output is enabled in software standby mode, the reference supply current is the same as during normal operation. Rev. 3.00 Sep 14, 2005 page 592 of 910 REJ09B0258-0300 Section 17 RAM Section 17 RAM 17.1 Overview The H8/3068F has 16 kbytes RAM. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM useful for rapid data transfer. The on-chip RAM of the H8/3068F is assigned to addresses H'FBF20 to H'FFF1F in modes 1, 2, and 7, and to addresses H'FFBF20 to H'FFFF1F in modes 3, 4, and 5,and to addresses H'E720 to H'FF1F in mode 6. The RAM enable bit (RAME) in the system control register (SYSCR) can enable or disable the on-chip RAM. Rev. 3.00 Sep 14, 2005 page 593 of 910 REJ09B0258-0300 Section 17 RAM 17.1.1 Block Diagram Figure 17.1 shows a block diagram of the on-chip RAM. On-chip data bus (upper 8 bits) On-chip data bus (lower 8 bits) Bus interface H'FBF20* H'FBF21* H'FBF22* H'FBF23* SYSCR On-chip RAM H'FFF1E* H'FFF1F* Even addresses Odd addresses Legend SYSCR: System control register Note: * Lower 20 bits of the address in mode 7. Figure 17.1 RAM Block Diagram 17.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of SYSCR. Table 17.1 System Control Register Address* Name Abbreviation R/W Initial Value H'EE012 System control register SYSCR R/W H'09 Note: * Lower 20 bits of the address in advanced mode. Rev. 3.00 Sep 14, 2005 page 594 of 910 REJ09B0258-0300 Section 17 RAM 17.2 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 UE NMIEG SSOE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W RAM enable bit Enables or disables on-chip RAM Software standby output port enable NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3, System Control Register (SYSCR). Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized at the rising edge of the input at the RES pin. It is not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled (Initial value) Rev. 3.00 Sep 14, 2005 page 595 of 910 REJ09B0258-0300 Section 17 RAM 17.3 Operation When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FBF20 to H'FFF1F in modes 1, 2, and 7, and to addresses H'FFBF20 to H'FFFF1F in the H8/3068F in modes 3, 4, and 5, and to addresses H'7F20 to H'FF1F in mode 6, are directed to the on-chip RAM. In modes 1 to 5 (expanded modes), when the RAME bit is cleared to 0, the off-chip address space is accessed. In mode 6, 7 (single-chip mode), when the RAME bit is cleared to 0, the on-chip RAM is not accessed: read access always results in H'FF data, and write access is ignored. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written and read by word access. It can also be written and read by byte access. Byte data is accessed in two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed in two states using all 16 bits of the data bus. Rev. 3.00 Sep 14, 2005 page 596 of 910 REJ09B0258-0300 Section 18 Flash Memory Section 18 Flash Memory 18.1 Overview The H8/3068F-ZTAT has 384 kbytes of on-chip flash memory. The flash memory is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, enabling rapid data transfer. The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0) as shown in table 18.1. The on-chip flash memory product (H8/3068F-ZTAT) can be erased and programmed on-board, as well as with a special-purpose PROM programmer. Table 18.1 Operating Modes and ROM Mode Pins Mode MD2 MD1 MD0 On-Chip ROM Mode 1 (expanded 1-Mbyte mode with on-chip ROM disabled) 0 0 1 Disabled (external address area) Mode 2 (expanded 1-Mbyte mode with on-chip ROM disabled) 0 1 0 Mode 3 (expanded 16-Mbyte mode with on-chip ROM disabled) 0 1 1 Mode 4 (expanded 16-Mbyte mode with on-chip ROM disabled) 1 0 0 Mode 5 (expanded 16-Mbyte mode with on-chip ROM enabled) 1 0 1 Mode 6 (single-chip normal mode) 1 1 0 Mode 7 (single-chip advanced mode) 1 1 1 Enabled Rev. 3.00 Sep 14, 2005 page 597 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.2 Features The H8/3068F-ZTAT has 384 kbytes of on-chip flash memory. The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed in block units. To erase the entire flash memory, each block must be erased in turn. In block erasing, 4-kbyte, 32-kbyte, and 64-kbyte blocks can be set arbitrarily. * Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent approximately to 80 s (typ.) per byte, and the erase time is 100 ms (typ.) per block. * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode * Automatic bit rate adjustment For data transfer in boot mode, the H8/3068F-ZTAT chip's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. * Protect modes There are three protect modes--hardware, software, and error--which allow protected status to be designated for flash memory program/erase/verify operations * PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode. Rev. 3.00 Sep 14, 2005 page 598 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.2.1 Block Diagram Internal address bus Module bus Internal data bus (16 bits) FLMCR1 FLMCR2 EBR1 Bus interface/controller Operating mode FWE pin Mode pins EBR2 RAMCR Flash memory (384 kbytes) Legend FLMCR1: FLMCR2: EBR1: EBR2: RAMCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM control register Figure 18.1 Block Diagram of Flash Memory Rev. 3.00 Sep 14, 2005 page 599 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.2.2 Pin Configuration The flash memory is controlled by means of the pins shown in table 18.2. Table 18.2 Flash Memory Pins Pin Name Abbreviation I/O Function Reset RES Input Reset Flash write enable FWE Input Flash program/erase protection by hardware Mode 2 MD2 Input Sets H8/3068F-ZTAT operating mode Mode 1 MD1 Input Sets H8/3068F-ZTAT operating mode Mode 0 MD0 Input Sets H8/3068F-ZTAT operating mode Transmit data TxD1 Output Serial transmit data output Receive data RxD1 Input Serial receive data input 18.2.3 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 18.3. Table 18.3 Flash Memory Registers Register Name Abbreviation R/W Initial Value 2 Address*1 Flash memory control register 1 FLMCR1 R/W H'00* H'EE030 Flash memory control register 2 FLMCR2 R H'00 H'EE031 Erase block register 1 EBR1 R/W H'00 H'EE032 Erase block register 2 EBR2 R/W H'00 H'EE033 RAM control register RAMCR R/W H'F0 H'EE077 Notes: FLMCR1, FLMCR2, EBR1, EBR2, and RAMCR are 8-bit registers, and should be accessed by byte access. 1. Lower 20 bits of address in advanced mode. 2. When a high level is input to the FWE pin, the initial value is H'80. Rev. 3.00 Sep 14, 2005 page 600 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.3 Register Descriptions 18.3.1 Flash Memory Control Register 1 (FLMCR1) Bit 7 6 5 4 3 2 1 0 FWE SWE ESU PSU EV PV E P Initial value --* 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000 to H'5FFFF is entered by setting the SWE bit when FWE = 1, then setting the PV or EV bit. Program mode for addresses H'00000 to H'5FFFF is entered by setting the SWE bit when FWE = 1, then setting the PSU bit, and finally setting the P bit. Erase mode for addresses H'00000 to H'5FFFF is entered by setting the SWE bit when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. In mode 6 the FWE pin must be fixed low since flash memory on-board programming modes are not supported. When the on-chip flash memory is disabled, a read access to this register will return H'00, and writes are invalid. When setting bits 6 to 0 in this register, one bit must be set one at a time. Writes to the SWE bit in FLMCR1 are enabled only when FWE = 1; writes to bits ESU, PSU, EV, and PV only when FWE = 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1. Notes: 1. The programming and erase flowcharts must be followed when setting the bits in this register to prevent erroneous programming or erasing. 2. Transitions are made to program mode, erase mode, program-verify mode, and eraseverify mode according to the settings in this register. When reading flash memory as normal on-chip ROM, bits 6 to 0 in this register must be cleared. Rev. 3.00 Sep 14, 2005 page 601 of 910 REJ09B0258-0300 Section 18 Flash Memory Bit 7--Flash Write Enable (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE Description 0 When a low level is input to the FWE pin (hardware-protected state) 1 When a high level is input to the FWE pin Bit 6--Software Write Enable (SWE): Enables or disables flash memory programming and erasing. (This bit should be set when setting bits 5 to 0, EBR1 bits 7 to 0, and EBR2 bits 3 to 0.) Bit 6 SWE Description 0 Programming/erasing disabled 1 Programming/erasing enabled (Initial value) [Setting condition] When FWE = 1 Note: Do not execute a SLEEP instruction while the SWE bit is set to 1. Bit 5--Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit to 1 in FLMCR1 (do not set the SWE, PSU, EV, PV, E, or P bit at the same time). Bit 5 ESU Description 0 Erase setup cleared 1 Erase setup [Setting condition] When FWE = 1 and SWE = 1 Rev. 3.00 Sep 14, 2005 page 602 of 910 REJ09B0258-0300 (Initial value) Section 18 Flash Memory Bit 4--Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before setting the P bit to 1 in FLMCR1 (do not set the SWE, ESU, EV, PV, E, or P bit at the same time). Bit 4 PSU Description 0 Program setup cleared 1 Program setup (Initial value) [Setting condition] When FWE = 1 and SWE = 1 Bit 3--Erase-Verify Mode (EV): Selects erase-verify mode transition or clearing. (Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time.) Bit 3 EV Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE = 1 Bit 2--Program-Verify Mode (PV): Selects program-verify mode transition or clearing. (Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time.) Bit 2 PV Description 0 Program-verify mode cleared 1 Transition to program-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE = 1 Rev. 3.00 Sep 14, 2005 page 603 of 910 REJ09B0258-0300 Section 18 Flash Memory Bit 1--Erase Mode (E): Selects erase mode transition or clearing. (Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time.) Bit 1 E Description 0 Erase mode cleared 1 Transition to erase mode (Initial value) [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 Note: Do not access the flash memory while the E bit is set. Bit 0--Program (P): Selects program mode transition or clearing. (Do not set the SWE, ESU, PSU, EV, PV, or E bit at the same time.) Bit 0 P Description 0 Program mode cleared 1 Transition to program mode (Initial value) [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Note: Do not access the flash memory while the P bit is set. 18.3.2 Flash Memory Control Register 2 (FLMCR2) Bit 7 6 5 4 3 2 1 0 FLER -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When the on-chip flash memory is disabled, a read will return H'00. Note: FLMCR2 is a read-only register, and should not be written to. Rev. 3.00 Sep 14, 2005 page 604 of 910 REJ09B0258-0300 Section 18 Flash Memory Bit 7--Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. Bit 7 FLER Description 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset (RES pin or WDT reset) or hardware standby mode 1 (Initial value) An error occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting conditions] * When flash memory is read during programming/erasing (including a vector read or instruction fetch, but excluding a read of the RAM area overlapping flash memory space) * Immediately after the start of exception handling during programming/erasing (excluding reset, illegal instruction, trap instruction, and division-by-zero exception handling) * When a SLEEP instruction (including software standby) is executed during programming/erasing * When the bus is released during programming/erasing Bits 6 to 0--Reserved: These bits are always read as 0. 18.3.3 Erase Block Register 1 (EBR1) Bit 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one bit can be set in EBR1 and EBR2 together; do not set two or Rev. 3.00 Sep 14, 2005 page 605 of 910 REJ09B0258-0300 Section 18 Flash Memory more bits at the same time. When the on-chip flash memory is disabled, a read access to this register will return H'00, and erasing is disabled. The flash memory block configuration is shown in table 18.4. To erase the entire flash memory, each block must be erased in turn. As the H8/3068F-ZTAT does not support on-board programming modes in mode 6, EBR1 register bits cannot be set to 1 in this mode. 18.3.4 Erase Block Register 2 (EBR2) Bit 7 6 5 4 3 2 1 0 -- -- EB13 EB12 EB11 EB10 EB9 EB8 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R/W R/W R/W R/W R/W R/W EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and when a low level is input to the FWE pin. When a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set, it is initialized to bit 0. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one bit can be set in EBR1 and EBR2 together; do not set two or more bits at the same time. When the on-chip flash memory is disabled, a read will return H'00, and erasing is disabled. The flash memory block configuration is shown in table 18.4. To erase the entire flash memory, each block must be erased in turn. As the H8/3068F-ZTAT does not support on-board programming modes in mode 6, EBR2 register bits cannot be set to 1 in this mode. Note: Bits 7 and 4 in this register are read-only. These bits must not be set to 1. If bits 7 and 4 are set when an EBR1/EBR2 bit is set, EBR1/EBR2 will be initialized to H'00. Rev. 3.00 Sep 14, 2005 page 606 of 910 REJ09B0258-0300 Section 18 Flash Memory Table 18.4 Flash Memory Erase Blocks Block (Size) Addresses EB0 (4 kbytes) H'000000 to H'000FFF EB1 (4 kbytes) H'001000 to H'001FFF EB2 (4 kbytes) H'002000 to H'002FFF EB3 (4 kbytes) H'003000 to H'003FFF EB4 (4 kbytes) H'004000 to H'004FFF EB5 (4 kbytes) H'005000 to H'005FFF EB6 (4 kbytes) H'006000 to H'006FFF EB7 (4 kbytes) H'007000 to H'007FFF EB8 (32 kbytes) H'008000 to H'00FFFF EB9 (64 kbytes) H'010000 to H'01FFFF EB10 (64 kbytes) H'020000 to H'02FFFF EB11 (64 kbytes) H'030000 to H'03FFFF EB12 (64 kbytes) H'040000 to H'04FFFF EB13 (64 kbytes) H'050000 to H'05FFFF 18.3.5 RAM Control Register (RAMCR) Bit 7 6 5 4 3 2 1 0 -- -- -- -- RAMS RAM2 RAM1 RAM0 Initial value 1 1 1 1 0 0 0 0 Read/Write R R R R R/W R/W R/W R/W RAMCR specifies the area of flash memory to be overlapped with part of RAM when emulating realtime flash memory programming. RAMCR is initialized to H'00 by a reset and in hardware standby mode. RAMCR settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 18.5. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Rev. 3.00 Sep 14, 2005 page 607 of 910 REJ09B0258-0300 Section 18 Flash Memory Bit 3--RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected. Bit 3 RAMS Description 0 Emulation not selected Program/erase-protection of all flash memory blocks is disabled 1 (Initial value) Emulation selected Program/erase-protection of all flash memory blocks is enabled Bits 2 to 0--Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 18.5.) Table 18.5 Flash Memory Area Divisions RAM Area Block Name RAMS RAM2 RAM1 RAM0 H'FFE000 to H'FFEFFF 4-kbyte RAM area 0 * * * H'000000 to H'000FFF EB0 (4 kbytes) 1 0 0 0 H'001000 to H'001FFF EB1 (4 kbytes) 1 0 0 1 H'002000 to H'002FFF EB2 (4 kbytes) 1 0 1 0 H'003000 to H'003FFF EB3 (4 kbytes) 1 0 1 1 H'004000 to H'004FFF EB4 (4 kbytes) 1 1 0 0 H'005000 to H'005FFF EB5 (4 kbytes) 1 1 0 1 H'006000 to H'006FFF EB6 (4 kbytes) 1 1 1 0 H'007000 to H'007FFF EB7 (4 kbytes) 1 1 1 1 *: Don't care Note: Flash memory emulation by RAM is not supported in mode 6 (single-chip normal mode); therefore, although these bits can be written, they should not be set to 1. When performing flash memory emulation by RAM, the RAME bit in SYSCR must be set to 1. Rev. 3.00 Sep 14, 2005 page 608 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.4 Overview of Operation 18.4.1 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the H8/3068F-ZTAT enters one of the operating modes shown in figure 18.2. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode. Boot mode and user program mode cannot be used in the H8/3068F-ZTAT's mode 6 (normal mode with on-chip ROM enabled). Rev. 3.00 Sep 14, 2005 page 609 of 910 REJ09B0258-0300 Section 18 Flash Memory Reset state *3 *1 User mode with on-chip ROM enabled RES = 0 RES = 0 *2 *4 RES = 0 FWE = 0 *5 RES = 0 *4 PROM mode User program mode *1 Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. The H8/3068F-ZTAT is placed in PROM mode by means of a dedicated PROM writer. 3. MD2, MD1, MD0 = (1, 0, 1) (1, 1, 0) (1, 1, 1) FWE = 0 4. MD2, MD1, MD0 = (1, 0, 1) (1, 1, 1) FWE = 1 5. MD2, MD1, MD0 (0, 0, 1) (0, 1, 1) FWE = 1 Figure 18.2 Flash Memory Related State Transitions State transitions between the normal and user modes and on-board programming mode are performed by changing the FWE pin level from high to low or from low to high. To prevent misoperation (erroneous programming or erasing) in these cases, the bits in the flash memory control register (FLMCR1) should be cleared to 0 before making such a transition. After the bits are cleared, a wait time is necessary. Normal operation is not guaranteed if this wait time is insufficient. Rev. 3.00 Sep 14, 2005 page 610 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.4.2 On-Board Programming Modes Example of Boot Mode Operation 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. Host 2. Programming control program transfer When boot mode is entered, the boot program in the H8/3068F-ZTAT (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Programming control program New application program New application program H8/3068F-ZTAT H8/3068F-ZTAT SCI Boot program Flash memory SCI Boot program Flash memory RAM RAM Boot program area Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Host Programming control program 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program H8/3068F-ZTAT H8/3068F-ZTAT SCI Boot program Flash memory RAM Flash memory Boot program area Flash memory prewrite-erase Programming control program SCI Boot program RAM Boot program area New application program Programming control program Program execution state Rev. 3.00 Sep 14, 2005 page 611 of 910 REJ09B0258-0300 Section 18 Flash Memory Example of User Program Mode Operation 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/ erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer When user program mode is entered, user software recognizes this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host Host Programming/erase control program New application program New application program H8/3068F-ZTAT H8/3068F-ZTAT SCI Boot program Flash memory Flash memory RAM SCI Boot program FWE assessment program FWE assessment program Transfer program Transfer program RAM Programming/erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host Host New application program H8/3068F-ZTAT H8/3068F-ZTAT SCI Boot program Flash memory RAM Flash memory FWE assessment program FWE assessment program Transfer program Transfer program Programming/erase control program Flash memory erase SCI Boot program RAM Programming/erase control program New application program Program execution state Rev. 3.00 Sep 14, 2005 page 612 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.4.3 Flash Memory Emulation in RAM In the H8/3068F-ZTAT, flash memory programming can be emulated in real time by overlapping the flash memory with part of RAM ("overlap RAM"). When the emulation block set in RAMCR is accessed while the emulation function is being executed, data written in the overlap RAM is read. Emulation should be performed in user mode or user program mode. SCI Flash memory RAM Emulation block Overlap RAM Application program (Emulation is performed on data written in RAM) Execution state Figure 18.3 Reading Overlap RAM Data in User Mode/User Program Mode When overlap RAM data is confirmed, clear the RAMS bit to cancel RAM overlap, and actually perform writes to the flash memory in user program mode. When the programming control program is transferred to RAM in on-board programming mode, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. Rev. 3.00 Sep 14, 2005 page 613 of 910 REJ09B0258-0300 Section 18 Flash Memory SCI Flash memory RAM Program data Application program Overlap RAM (program data) Programming control program Execution state Figure 18.4 Writing Overlap RAM Data in User Program Mode Rev. 3.00 Sep 14, 2005 page 614 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.4.4 Block Configuration The flash memory in the H8/3068F-ZTAT is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Erasing can be carried out in block units. Address H'00000 4 kbytes x 8 32 kbytes 64 kbytes 64 kbytes 384 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'5FFFF Rev. 3.00 Sep 14, 2005 page 615 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.5 On-Board Programming Mode When pins are set to on-board programming mode and a reset-start is executed, the chip enters the on-board programming state in which on-chip flash memory programming, erasing, and verifying can be carried out. There are two operating modes in this mode--boot mode and user program mode. The pin settings for entering each mode are shown in table 18.6. For a diagram of the transitions to the various flash memory modes, see figure 18.2. Boot mode and user program mode cannot be used in the H8/3068F-ZTAT's mode 6 (on-chip ROM enabled). Table 18.6 On-Board Programming Mode Settings Mode Boot mode User program mode FWE Mode 5 1 1* MD2 MD1 MD0 2 0 1 2 0* Mode 7 0* 1 1 Mode 5 1 0 1 Mode 7 1 1 1 Notes: 1. For the High level input timing, see items 6 and 7 of Notes on Using the Boot Mode. 2. In boot mode, the MD2 setting should be the inverse of the input. In the boot mode in the H8/3068F-ZTAT, the levels of the mode pins (MD2 to MD0) are reflected in mode select bits 2 to 0 (MDS2 to MDS0) in the mode control register (MDCR). Rev. 3.00 Sep 14, 2005 page 616 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.5.1 Boot Mode When boot mode is used, a flash memory programming control program must be prepared beforehand in the host, and SCI channel 1, which is to be used, must be set to asynchronous mode. When a reset-start is executed after setting the H8/3068F-ZTAT' pins to boot mode, the boot program already incorporated in the MCU is activated, and the programming control program prepared beforehand in the host is transmitted sequentially to the H8/3068F-ZTAT, using the SCI. In the H8/3068F-ZTAT, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address (H'FFC720) of the programming control program area and the programming control program execution state is entered (flash memory programming/erasing can be performed). Figure 18.5 shows a system configuration diagram when using boot mode, and figure 18.6 shows the boot program mode execution procedure. H8/3068F-ZTAT Flash memory Host Reception of programming data Transmission of verify data RxD1 SCI1 TxD1 On-chip RAM Figure 18.5 System Configuration When Using Boot Mode Rev. 3.00 Sep 14, 2005 page 617 of 910 REJ09B0258-0300 Section 18 Flash Memory Start Set pins to boot program mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate H8/3068F-ZTAT measures low period of H'00 data transmitted by host H8/3068F-ZTAT calculates bit rate and sets value in bit rate register After bit rate adjustment, H8/3068F-ZTAT transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, H8/3068F-ZTAT transmits one H'AA byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte H8/3068F-ZTAT transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units H8/3068F-ZTAT transmits received programming control program to host as verify data (echo-back) n+1n Transfer received programming control program to on-chip RAM n = N? No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, H8/3068F-ZTAT transmits one H'AA byte to host Execute programming control program transferred to on-chip RAM Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error indication, and the erase operation and subsequent operations are halted. Figure 18.6 Boot Mode Execution Procedure Rev. 3.00 Sep 14, 2005 page 618 of 910 REJ09B0258-0300 Section 18 Flash Memory Automatic SCI Bit Rate Adjustment: Start bit D0 D1 D2 D3 D4 D5 D6 Low period (9 bits) measured (H'00 data) D7 Stop bit High period (1 or more bits) When boot mode is initiated, the H8/3068F-ZTAT measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as 8-bit data, 1 stop bit, no parity. The H8/3068F-ZTAT calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the H8/3068FZTAT. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the H8/3068F-ZTAT's system clock frequency, there will be a discrepancy between the bit rates of the host and the H8/3068F-ZTAT. To ensure correct SCI operation, the host's transfer bit rate should be set to 4800, 9600, or 19,200 bps*. Table 18.7 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the H8/3068F-ZTAT bit rate is possible. The boot program should be executed within this system clock range. Table 18.7 System Clock Frequencies for which Automatic Adjustment of H8/3068FZTAT Bit Rate is Possible Host Bit Rate (bps) System Clock Frequency for which Automatic Adjustment of H8/3068F-ZTAT Bit Rate is Possible (MHz) 19,200 16 to 25 9,600 8 to 25 4,800 4 to 25 Note: * Only use a setting of 4800, 9600, or 19200 bps for the host's bit rate. No other settings can be used. Although the H8/3068F-ZTAT may also perform automatic bit rate adjustment with bit rate and system clock combinations other than those shown in table 18.7, a degree of error will arise between the bit rates of the host and the H8/3068F-ZTAT, and subsequent transfer will not be performed normally. Therefore, only a combination of bit rate and Rev. 3.00 Sep 14, 2005 page 619 of 910 REJ09B0258-0300 Section 18 Flash Memory system clock frequency within one of the ranges shown in table 18.7 can be used for boot mode execution. On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the user program is transferred via the SCI, as shown in figure 18.7. The boot program area becomes available when a transition is made to the execution state for the user program transferred to RAM. H'FFBF20 Boot program area H'FFC71F H'FFC720 User program transfer area H'FFFF1F Note: The boot program area cannot be used until a transition is made to the execution state for the user program transferred to RAM. Note also that the boot program remains in this area in RAM even after control branches to the user program. Figure 18.7 RAM Areas in Boot Mode Notes on Use of Boot Mode: 1. When the H8/3068F-ZTAT chip comes out of reset in boot mode, it measures the low period of the input at the SCI's RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the RxD1 input. 2. In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. 3. Interrupts cannot be used while the flash memory is being programmed or erased. 4. The RxD1 and TxD1 lines should be pulled up on the board. 5. Before branching to the user program the H8/3068F-ZTAT terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits to 0 in the serial Rev. 3.00 Sep 14, 2005 page 620 of 910 REJ09B0258-0300 Section 18 Flash Memory control register (SCR)), but the adjusted bit rate value remains set in the bit rate register (BRR). The transmit data output pin, TxD1, goes to the high-level output state (P91DDR = 1 in P9DDR, P91DR = 1 in P9DR). The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the user program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the user program. The initial values of other on-chip registers are not changed. 6. Boot mode can be entered by setting pins MD0 to MD2 and FWE in accordance with the mode setting conditions shown in table 18.6, and then executing a reset-start. a. When switching from boot mode to normal mode, the boot mode state within the chip must first be cleared by reset input via the RES pin*1. The RES pin must be held low for at least 20 system clock cycles.*3 b. Do not change the input levels of the mode pins (MD2 to MD0) or the FWE pin in boot mode. To change the mode, the RES pin must first be driven low to set the reset state. Also, if a watchdog timer reset occurs in the boot mode state, the MCU's internal state will not be cleared, and the on-chip boot program will be restarted regardless of the mode pin states. c. The FWE pin must not be driven low while the boot program is running or flash memory is being programmed or erased*2. 7. If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output signals (CSn, AS, RD, LWR, HWR) may also change according to the change in the MCU's operating mode. Therefore, care must be taken to make pin settings to prevent these pins from being used directly as output signal pins during a reset, or to prevent collision with signals outside the MCU. Rev. 3.00 Sep 14, 2005 page 621 of 910 REJ09B0258-0300 Section 18 Flash Memory H8/3068F-ZTAT CSn MD2 MD1 MD0 FWE External memory, etc. System control unit RES Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS) with respect to the reset release timing. 2. For further information on FWE application and disconnection, see section 18.11, Flash Memory Programming and Erasing Precautions. 3. See section 4.2.2, Reset Sequence, and section 18.11, Flash Memory Programming and Erasing Precautions. The H8/3068F-ZTAT requires a minimum of 20 system clock cycles for a reset during operation. 18.5.2 User Program Mode When set to user program mode, the H8/3068F-ZTAT can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the onchip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. To select user program mode, select a mode that enables the on-chip ROM (mode 5 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 5 and 7. Flash memory programming/erasing should not be carried out in mode 6. When mode 6 is set, the FWE pin must be driven low. The flash memory itself cannot be read while being programmed or erased, so the program that performs programming should be placed in external memory or transferred to RAM and executed there. Rev. 3.00 Sep 14, 2005 page 622 of 910 REJ09B0258-0300 Section 18 Flash Memory Figure 18.8 shows the execution procedure when user program mode is entered during program execution in RAM. It is also possible to start from user program mode in a reset-start. Write FWE assessment program and transfer program (and programming/erase control program if necessary) beforehand MD2-MD0 = 101 or 111 Reset-start Transfer programming/erase control program to RAM Branch to programming/erase control program in RAM area FWE = high (user program mode) Execute programming/erase control program in RAM (flash memory rewriting) Clear SWE bit, then release FWE (user program mode clearing) Branch to application program in flash memory Notes: 1. Do not apply a constant high level to the FWE pin. A high level should be applied to the FWE pin only when programming or erasing flash memory (including execution of flash memory emulation by RAM). Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 2. For further information on FWE application and disconnection, see section 18.11, Flash Memory Programming and Erasing Precautions. 3. In order to execute a normal read of flash memory in user program mode, the programming/erase program must not be executing. It is thus necessary to ensure that bits 6 to 0 in FLMCR1 are cleared to 0. Figure 18.8 Example of User Program Mode Execution Procedure Rev. 3.00 Sep 14, 2005 page 623 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.6 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses H'000000 to H'03FFFF are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program (user program) that controls flash memory programming/erasing should be located and executed in on-chip RAM or external memory. See section 18.11, Flash Memory Programming and Erasing Precautions, for points to be noted when programming or erasing the flash memory. In the following operation descriptions, wait times after setting or clearing individual bits in FLMCR1 are given as parameters; for details of the wait times, see section 21.1.6, Flash Memory Characteristics. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Programming must be executed in the erased state. Do not perform additional programming on addresses that have already been programmed. Rev. 3.00 Sep 14, 2005 page 624 of 910 REJ09B0258-0300 Section 18 Flash Memory *3 E=1 Erase setup state Erase mode E=0 Normal mode FWE = 1 ESU = 1 ESU = 0 *1 FWE = 0 EV = 1 *2 On-board SWE = 1 Software programming mode programming Software programming enable disable state SWE = 0 state Erase-verify mode EV = 0 PSU = 1 *4 P=1 PSU = 0 Program setup state Program mode P=0 PV = 1 PV = 0 Program-verify mode Notes: In order to perform a normal read of flash memory, SWE must be cleared to 0. Also note that verify-reads can be performed during the programming/erasing process. 1. : Normal mode : On-board programming mode 2. Do not make a state transition by setting or clearing multiple bits simultaneously. 3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. 4. After a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. Figure 18.9 FLMCR1 Bit Settings and State Transitions Rev. 3.00 Sep 14, 2005 page 625 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.6.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 18.10 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N) are shown in table 21.10 in section 21.1.6, Flash Memory Characteristics. Following the elapse of (tsswe) s or more after the SWE bit is set to 1 in FLMCR1, 128-byte data is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 and H'80, 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. Set a value greater than (tspsu + tsp + tcp + tcpsu) s as the WDT overflow period. Preparation for entering program mode (program setup) is performed next by setting the PSU bit in FLMCR1. The operating mode is then switched to program mode by setting the P bit in FLMCR1 after the elapse of at least (tspsu) s. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (tsp) s. The wait time after P bit setting must be changed according to the degree of progress through the programming operation. For details see "Notes on Program/Program-Verify Mode." Rev. 3.00 Sep 14, 2005 page 626 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.6.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least (tcp) s before clearing the PSU bit to exit program mode. After exiting program mode, the watchdog timer setting is also cleared. The operating mode is then switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (tspv) s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (tspvr) s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 18.10) and transferred to RAM. After verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least (tcpv) s, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. The maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (N). Leave a wait time of at least (tcswe) s after clearing SWE. Notes on Program/Program-Verify Procedure 1. The program/program-verify procedure for the H8/3068F-ZTAT uses a 128-byte-unit programming algorithm. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be H'00 or H'80. 2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write H'FF data to the extra addresses. 3. Verify data is read in word units. 4. The write pulse is applied and a flash memory write executed while the P bit in FLMCR1 is set. In the H8/3068F-ZTAT, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. After write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. In the H8/3068F-ZTAT, the number of Rev. 3.00 Sep 14, 2005 page 627 of 910 REJ09B0258-0300 Section 18 Flash Memory loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming count (N). b. After write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. The following processing is necessary for programmed bits. When programming is completed at an early stage in the program/program-verify procedure: If programming is completed in the 1st to 6th reprogramming processing loop, additional programming should be performed on the relevant bits. Additional programming should only be performed on bits which first return 0 in a verify-read in certain reprogramming processing. When programming is completed at a late stage in the program/program-verify procedure: If programming is completed in the 7th or later reprogramming processing loop, additional programming is not necessary for the relevant bits. c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. If a bit for which programming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. 5. The period for which the P bit in FLMCR1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. For detailed wait time specifications, see section 21.1.6, Flash Memory Characteristics. Item Symbol Item Symbol Wait time after P bit setting tsp When reprogramming loop count (n) is 1 to 6 tsp30 When reprogramming loop count (n) is 7 or more tsp200 In case of additional programming processing* tsp10 Note: * Additional programming processing is necessary only when the reprogramming loop count (n) is 1 to 6. 6. The program/program-verify flowchart for the H8/3068F-ZTAT is shown in figure 18.10. To cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. Since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in RAM. Rev. 3.00 Sep 14, 2005 page 628 of 910 REJ09B0258-0300 Section 18 Flash Memory Reprogram Data Computation Table (D) Result of Verify-Read after Write Pulse (X) Application (V) Result of Operation 0 0 1 Programming completed: reprogramming processing not to be executed 0 1 0 Programming incomplete: reprogramming processing to be executed 1 0 1 1 1 1 Still in erased state: no action Comments Legend (D): Source data of bits on which programming is executed (X): Source data of bits on which reprogramming is executed Additional-Programming Data Computation Table Result of Verify-Read after Write Pulse (Y) (X') Application (V) Result of Operation Comments 0 0 0 Programming by write pulse application judged to be completed: additional programming processing to be executed 0 1 1 Programming by write pulse application incomplete: additional programming processing not to be executed 1 0 1 Programming already completed: additional programming processing not to be executed 1 1 1 Still in erased state: no action Legend (Y): Data of bits on which additional programming is executed (X'): Data of bits on which reprogramming is executed in a certain reprogramming loop 7. It is necessary to execute additional programming processing during the course of the H8/3068F-ZTAT program/program-verify procedure. However, once 128-byte-unit programming is finished, additional programming should not be carried out on the same address area. When executing reprogramming, an erase must be executed first. Note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished. Rev. 3.00 Sep 14, 2005 page 629 of 910 REJ09B0258-0300 Section 18 Flash Memory Start of programming Write pulse application subroutine Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. START Sub-Routine Write Pulse Set SWE bit in FLMCR1 WDT enable Wait (tsswe) s Set PSU bit in FLMCR1 Wait (tspsu) s *7 *4 n= 1 Start of programming Set P bit in FLMCR1 *7 Store 128-byte program data in program data area and reprogram data area m= 0 Wait (tsp) s *5*7 Clear P bit in FLMCR1 Programming halted Consecutively write 128-byte data in reprogram data area in RAM to flash memory *1 Sub-Routine-Call Wait (tcp) s Set PV bit in FLMCR1 Clear PSU bit in FLMCR1 Wait (tcpsu) s See Note *6 for pulse width Write pulse *7 Wait (tspv) s *7 *7 H'FF dummy write to verify address Disable WDT Wait (tspvr) s End Sub nn+1 *7 Read verify data *2 Write data = verify data? NG Increment address Note: 6. Write Pulse Width Number of Writes (n) Write Time (tsp) sec 1 2 3 4 5 6 7 8 9 10 11 12 13 30 30 30 30 30 30 200 200 200 200 200 200 200 998 999 1000 200 200 200 m=1 OK NG 6n? OK Additional-programming data computation Transfer additional-programming data to additional-programming data area *4 *3 Reprogram data computation Transfer reprogram data to reprogram data area NG *4 128-byte data verification completed? OK Clear PV bit in FLMCR1 Reprogram Wait (tcpv) s Note: Use a 10 s write pulse for additional programming. *7 NG 6 n? OK Consecutively write 128-byte data in additionalprogramming data area in RAM to flash memory RAM Program data storage area (128 bytes) *1 Sub-Routine-Call Write Pulse (Additional programming) Reprogram data storage area (128 bytes) *7 NG m= 0 ? OK Clear SWE bit in FLMCR1 Additional-programming data storage area (128 bytes) NG n N? OK Clear SWE bit in FLMCR1 Wait (tcswe) s Wait (tcswe) s End of programming Programming failure *7 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional-programming data must be provided in RAM. The contents of the reprogram data area and additional-programming data area are modified as programming proceeds. 5. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 7. The wait times and value of N are shown in section 21.1.6, Flash Memory Characteristics. Reprogram Data Computation Table Additional-Programming Data Computation Table Original Data Verify Data Reprogram Data (D) 0 (V) 0 (X) 1 0 1 0 1 0 1 1 1 1 Comments Reprogram Data (X') Verify Data Additional(V) Programming Data (Y) Programming completed 0 0 0 Programming incomplete; reprogram 0 1 1 1 0 1 1 1 1 Still in erased state; no action Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed Figure 18.10 Program/Program-Verify Flowchart (128-Byte Programming) Rev. 3.00 Sep 14, 2005 page 630 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.6.3 Erase Mode When erasing flash memory, the single-block erase flowchart shown in figure 18.11 should be followed. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of erase operations (N) are shown in table 21.10 in section 21.1.6, Flash Memory Characteristics. To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (EBR1, EBR2) at least (tsswe) s after setting the SWE bit to 1 in FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value greater than (tse) ms + (tsesu + tce + tcesu) s as the WDT overflow period. Preparation for entering erase mode (erase setup) is performed next by setting the ESU bit in FLMCR1. The operating mode is then switched to erase mode by setting the E bit in FLMCR1 after the elapse of at least (tsesu) s. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (tse) ms. Note: With flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 18.6.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (tce) s before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer setting is also cleared. The operating mode is then switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (tsev) s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (tsevr) s after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is indicated by the maximum erase count (N). When verification is completed, exit erase-verify mode, and wait for at least (tcev) s. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1, and leave a wait time of at least (tcswe) s. If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and repeat the erase/erase-verify sequence as before. Rev. 3.00 Sep 14, 2005 page 631 of 910 REJ09B0258-0300 Section 18 Flash Memory Start *1 Perform erasing in block units. Set SWE bit in FLMCR1 Wait (tsswe) s *5 n=1 *3 *4 Set EBR1 or EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (tsesu) s *5 Start of erase Set E bit in FLMCR1 Wait (tse) ms *5 Clear E bit in FLMCR1 End of erase Wait (tce) s *5 Clear ESU bit in FLMCR1 Wait (tcesu) s *5 Disable WDT Set EV bit in FLMCR1 Wait (tsev) s nn+1 *5 Set block start address as verify address H'FF dummy write to verify address Increment address Wait (tsevr) s *5 Read verify data *2 Verify data = all 1s? No Yes No Last address of block? Re-erase Yes Clear EV bit in FLMCR1 Wait (tcev) s Clear EV bit in FLMCR1 *5 Wait (tcev) s *5 *5 n N? Yes Clear SWE bit in FLMCR1 Clear SWE bit in FLMCR1 Wait (tcswe) s End of erasing Notes: 1. 2. 3. 4. 5. No *5 Wait (tcswe) s *5 Erase failure Prewriting (setting erase block data to all 0s) is not necessary. Verify data is read in 16-bit (word) units. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. The wait times and the value of N are shown in section 21.1.6, Flash Memory Characteristics. Figure 18.11 Erase/Erase-Verify Flowchart (Single-Block Erasing) Rev. 3.00 Sep 14, 2005 page 632 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.7 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 18.7.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. In this state, the settings in flash memory control register 1 (FLMCR1) and erase block registers 1 and 2 (EBR1, EBR2) are reset. In the error protection state, the FLMCR1, EBR1, and EBR2 settings are retained; the P bit and E bit can be set, but a transition is not made to program mode or erase mode. (See table 18.8.) Table 18.8 Hardware Protection Function Item Description FWE pin protection * Not Not Not When a low level is input to the FWE pin, 1 3 FLMCR1, EBR1, and EBR2 are initialized, and possible* possible* possible the program/erase-protected state is entered. Reset/ standby protection * In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. * In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section.*4 * When a microcomputer operation error (error Not possible generation (FLER = 1)) was detected while flash memory was being programmed/erased, error protection is enabled. At this time, the FLMCR1, EBR1, and EBR2 settings are held, but programming/erasing is aborted at the time the error was generated. Error protection is released only by a reset via the RES pin or a WDT reset, or in the hardware standby mode. Error protection Program Not possible Erase Verify Not Not 3 possible* possible Not Possible*2 3 possible* Notes: 1. The RAM area that overlapped flash memory is deleted. Rev. 3.00 Sep 14, 2005 page 633 of 910 REJ09B0258-0300 Section 18 Flash Memory 2. It is possible to perform a program-verify operation on the 128 bytes being programmed, or an erase-verify operation on the block being erased. 3. All blocks are unerasable and block-by-block specification is not possible. 4. See section 4.2.2, Reset Sequence, and section 18.11, Flash Memory Programming and Erasing Precautions. The H8/3068F-ZTAT requires a minimum of 20 system clock cycles for a reset during operation. 18.7.2 Software Protection Software protection can be implemented by setting the erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM control register (RAMCR). With software protection, setting the P or E bit in the flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase mode. (See table 18.9.) Table 18.9 Software Protection Functions Item Description Block protection * -- Erase protection can be set for individual blocks by settings in erase block register 1 (EBR1) and erase block register 2 (EBR2)*2. However, programming protection is disabled. * Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. * Setting the RAMS bit 1 in RAMCR places all blocks in the program/erase-protected state. Emulation protection Program Erase Verify Not possible Possible Not Not Possible possible*1 possible*3 Notes: 1. The RAM area overlapping flash memory can be written to. 2. When not erasing, set EBR1 and EBR2 to H'00. 3. All blocks are unerasable and block-by-block specification is not possible. Rev. 3.00 Sep 14, 2005 page 634 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.7.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing*1, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in the flash memory status register (FLMSR2) and the error protection state is entered. FLMCR1, FLMCR2, EBR1, and EBR2 settings*3 are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by resetting the P or E bit in FLMCR. However, PV and EV bit setting is enabled, and a transition can be made to verify mode*2. FLER bit setting conditions are as follows: 1. When flash memory is read during programming/erasing (including a vector read or instruction fetch) 2. Immediately after the start of exception handling during programming/erasing (excluding reset, illegal instruction, trap instruction, and division-by-zero exception handling) 3. When a SLEEP instruction (including software standby) is executed during programming/erasing 4. When the bus is released during programming/erasing Error protection is released only by a RES pin or WDT reset, or in hardware standby mode. Notes: 1. State in which the P bit or E bit in FLMCR1 is set to 1. Note that NMI input is disabled in this state. 2. It is possible to perform a program-verify operation on the 128 bytes being programmed, or an erase-verify on the block being erased. 3. FLMCR1, EBR1, and EBR2 can be written to. However, the registers are initialized if a transition is made to software standby mode while in the error protection state. Figure 18.12 shows the flash memory state transition diagram. Rev. 3.00 Sep 14, 2005 page 635 of 910 REJ09B0258-0300 Section 18 Flash Memory Program mode Erase mode Reset or standby (hardware protection) RES = 0 or STBY = 0 RD VF PR ER INIT FLER = 0 RD VF PR ER FLER = 0 Error occurrence (software standby) RES = 0 or STBY = 0 Error occurrence RES = 0 or STBY = 0 Software standby mode Error protection mode RD VF PR ER FLER = 1 Software standby mode release FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode (software standby) RD VF PR ER INIT FLER = 1 FLMCR1, EBR1, EBR2 initialization state RD: VF: PR: ER: Memory read possible Verify-read possible Programming possible Erasing possible RD: VF: PR: ER: INIT: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Register initialization state Figure 18.12 Flash Memory State Transitions (When High Level is Applied to FWE Pin in Mode 5 or 7 (On-Chip ROM Enabled)) The error protection function is invalid for abnormal operations other than the FLER bit setting conditions. Also, if a certain time has elapsed before this protection state is entered, damage may already have been caused to the flash memory. Consequently, this function cannot provide complete protection against damage to flash memory. To prevent such abnormal operations, therefore, it is necessary to ensure correct operation in accordance with the program/erase algorithm, with the flash write enable (FWE) voltage applied, and to conduct constant monitoring for MCU errors, internally and externally, using the watchdog timer or other means. There may also be cases where the flash memory is in an erroneous programming or erroneous erasing state at the point of transition to this protection mode, or where programming or erasing is not properly carried out because of an abort. In cases such as these, a forced recovery (program rewrite) must be executed using boot mode. However, it may also happen that boot mode cannot be normally initiated because of overprogramming or overerasing. Rev. 3.00 Sep 14, 2005 page 636 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.8 Flash Memory Emulation in RAM Making a setting in the RAM control register (RAMCR) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMCR setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 18.13 shows an example of emulation of realtime flash memory programming. Start of emulation program Set RAMCR Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMCR Write to flash memory emulation block End of emulation program Figure 18.13 Flowchart of Flash Memory Emulation in RAM Rev. 3.00 Sep 14, 2005 page 637 of 910 REJ09B0258-0300 Section 18 Flash Memory This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFE000 H'FFEFFF Flash memory EB8 to EB13 On-chip RAM H'FFFF1F H'5FFFF Figure 18.14 Example of RAM Overlap Operation Example of Flash Memory Block Area EB0 Overlapping 1. Set bits RAMS and RAM2 to RAM0 in RAMCR to 1,0, 0, 0, to overlap part of RAM onto the area (EB0) for which realtime programming is required. 2. Realtime programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting the P or E bit in FLMCR1 will not cause a transition to program mode or erase mode. When actually programming or erasing a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. Rev. 3.00 Sep 14, 2005 page 638 of 910 REJ09B0258-0300 Section 18 Flash Memory 3. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. 4. As in on-board programming mode, care is required when applying and releasing FWE to prevent erroneous programming or erasing. To prevent erroneous programming and erasing due to program runaway during FWE application, in particular, the watchdog timer should be set when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while the emulation function is being used. 5. When the emulation function is used, NMI input is prohibited when the P bit or E bit is set to 1 in FLMCR1, in the same way as with normal programming and erasing. The P and E bits are cleared by a reset (including a watchdog timer reset), in standby mode, when a high level is not being input to the FWE pin, or when the SWE bit in FLMCR1 is 0 while a high level is being input to the FWE pin. Rev. 3.00 Sep 14, 2005 page 639 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.9 NMI Input Disabling Conditions All interrupts, including NMI input, should be disabled while flash memory is being programmed or erased (while the P bit or E bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. NMI input during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the NMI exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If NMI input occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling NMI input, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All interrupt requests (exception handling and bus release), including NMI, must therefore be restricted inside and outside the MCU during FWE application. NMI input is also disabled in the error protection state and while the P or E bit remains set in FLMCR1 during flash memory emulation in RAM. Notes: 1. This is the interval until a branch is made to the boot program area in the on-chip RAM (This branch takes place immediately after transfer of the user program is completed). Consequently, after the branch to the RAM area, NMI input is enabled except during programming and erasing. Interrupt requests must therefore be disabled inside and outside the MCU until the user program has completed initial programming (including the vector table and the NMI interrupt handling routine). 2. The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P bit or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If the entry in the interrupt vector table has not been programmed yet, interrupt exception handling will not be executed correctly. Rev. 3.00 Sep 14, 2005 page 640 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.10 Flash Memory PROM Mode The H8/3068F-ZTAT has a PROM mode as well as the on-board programming modes for programming and erasing flash memory. In PROM mode, the on-chip ROM can be freely programmed using a general-purpose PROM writer that supports the Renesas Technology microcomputer device type with 256-kbyte on-chip flash memory. 18.10.1 Socket Adapters and Memory Map In PROM mode using a PROM writer, memory reading (verification) and writing and flash memory initialization (total erasure) can be performed. For these operations, a special socket adapter is mounted in the PROM writer. The socket adapter product codes are given in table 18.10. In the H8/3068F-ZTAT PROM mode, only the socket adapters shown in this table should be used. Table 18.10 H8/3068F-ZTAT Socket Adapter Product Codes Socket Adapter Product Code Product Code Package Manufacturer HD64F3068F 100-pin QFP (FP-100B) ME3064ESHF1H HD64F3068TE 100-pin TQFP (TFP-100B) ME3064ESNF1H MINATO ELECTRONICS INC. HD64F3068F 100-pin QFP (FP-100B) HF306BQ100D4001 DATA I/O JAPAN CO. HD64F3068TE 100-pin TQFP (TFP-100B) HF306BT100D4001 Figure 18.15 shows the memory map in PROM mode. MCU mode H'000000 H8/3068F-ZTAT PROM mode H'00000 On-chip ROM H'05FFFF H'5FFFF Figure 18.15 Memory Map in PROM Mode Rev. 3.00 Sep 14, 2005 page 641 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.10.2 Notes on Use of PROM Mode 1. A write to a 128-byte programming unit in PROM mode should be performed once only. Erasing must be carried out before reprogramming an address that has already been programmed. 2. When using a PROM writer to reprogram a device on which on-board programming/erasing has been performed, it is recommended that erasing be carried out before executing programming. 3. The memory is initially in the erased state when the device is shipped by Renesas Technology. For samples for which the erasure history is unknown, it is recommended that erasing be executed to check and correct the initialization (erase) level. 4. The H8/3068F-ZTAT does not support a product identification mode as used with generalpurpose EPROMs, and therefore the device name cannot be set automatically in the PROM writer. 5. Refer to the instruction manual provided with the socket adapter, or other relevant documentation, for information on PROM writers and associated program versions that are compatible with the PROM mode of the H8/3068F-ZTAT. Rev. 3.00 Sep 14, 2005 page 642 of 910 REJ09B0258-0300 Section 18 Flash Memory 18.11 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and PROM mode are summarized below. 1. Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas Technology microcomputer device type "F-ZTAT512" with 512-kbyte on-chip flash memory. 2. Powering on and off (see figures 18.16 to 18.18) Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. Failure to do so may result in overprogramming or overerasing due to MCU runaway, and loss of normal memory cell operation. 3. FWE application/disconnection FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: * Apply FWE when the VCC voltage has stabilized within its rated voltage range. If FWE is applied when the MCU's VCC power supply is not within its rated voltage range, MCU operation will be unstable and flash memory may be erroneously programmed or erased. * Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling time). When VCC power is turned on, hold the RES pin low for the duration of the oscillation settling time before applying FWE. Do not apply FWE when oscillation has stopped or is unstable. * In boot mode, apply and disconnect FWE during a reset. In a transition to boot mode, FWE = 1 input and MD2-MD0 setting should be performed while the RES input is low. FWE and MD2-MD0 pin input must satisfy the mode programming setup time (tMDS) with respect to the reset release timing. When making a transition from boot mode to another mode, also, a mode programming setup time is necessary with respect to the reset release timing. Rev. 3.00 Sep 14, 2005 page 643 of 910 REJ09B0258-0300 Section 18 Flash Memory * * * In a reset during operation, the RES pin must be held low for a minimum of 20 system clock cycles. In user program mode, FWE can be switched between high and low level regardless of RES input. FWE input can also be switched during execution of a program in flash memory. Do not apply FWE if program runaway has occurred. During FWE application, the program execution state must be monitored using the watchdog timer or some other means. Disconnect FWE only when the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 are cleared. Make sure that the SWE, ESU, PSU, EV, PV, E, and P bits are not set by mistake when applying or disconnecting FWE. 4. Do not apply a constant high level to the FWE pin. T prevent erroneous programming or erasing due to program runaway, etc., apply a high level to the FWE pin only when programming or erasing flash memory (including execution of flash memory emulation using RAM). A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 5. Use the recommended algorithm when programming and erasing flash memory. The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the PSU or ESU bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Also note that access to the flash memory space by means of a MOV instruction, etc., is not permitted while the P bit or E bit is set. 6. Do not set or clear the SWE bit during execution of a program in flash memory. Clear the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for verify operations (verification during programming/erasing). Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. A wait time is necessary after the SWE bit is cleared. For details see table 21.10 in section 21.1.6, Flash Memory Characteristics. Rev. 3.00 Sep 14, 2005 page 644 of 910 REJ09B0258-0300 Section 18 Flash Memory 7. Do not use interrupts while flash memory is being programmed or erased. All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations (including emulation in RAM). Bus release must also be disabled. 8. Do not perform additional programming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. 9. Before programming, check that the chip is correctly mounted in the PROM writer. Overcurrent damage to the device can result if the index marks on the PROM writer socket, socket adapter, and chip are not correctly aligned. 10. Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. 11. A wait time of 100 s or more is necessary when performing a read after a transition to normal mode from program, erase, or verify mode. 12. Use byte access on the registers that control the flash memory (FLMCR1, FLMCR2, EBR1, EBR2, and RAMCR). Rev. 3.00 Sep 14, 2005 page 645 of 910 REJ09B0258-0300 Section 18 Flash Memory Wait time: x Programming/ erasing possible Wait time: y Min 0 s tOSC1 VCC tMDS FWE Min 0 s MD2 to MD0*1 tMDS RES SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2-MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 21.1.6, Flash Memory Characteristics. Figure 18.16 Power-On/Off Timing (Boot Mode) Rev. 3.00 Sep 14, 2005 page 646 of 910 REJ09B0258-0300 Section 18 Flash Memory Wait time: x Programming/ erasing possible Wait time: y Min 0 s tOSC1 VCC FWE MD2 to MD0*1 tMDS RES SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2-MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 21.1.6, Flash Memory Characteristics. Figure 18.17 Power-On/Off Timing (User Program Mode) Rev. 3.00 Sep 14, 2005 page 647 of 910 REJ09B0258-0300 Programming/ erasing possible Wait time: x Wait time: x Programming/ erasing possible Wait time: y Wait time: x Programming/ erasing possible Wait time: y Wait time: y Wait time: x Programming/ erasing possible Section 18 Flash Memory tOSC1 VCC Min 0s FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE cleared SWE set SWE bit Mode change*1 Boot mode Mode User change*1 mode User program mode User mode User program mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (CSn, AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. 2. When making a transition from boot mode to another mode, the mode programming setup time tMDS must be satisfied with respect to RES clearance timing. 3. See section 21.1.6, Flash Memory Characteristics. Figure 18.18 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) Rev. 3.00 Sep 14, 2005 page 648 of 910 REJ09B0258-0300 Section 19 Clock Pulse Generator Section 19 Clock Pulse Generator 19.1 Overview The H8/3068F has a built-in clock pulse generator (CPG) that generates the system clock () and other internal clock signals (/2 to /4096). After duty adjustment, a frequency divider divides the clock frequency to generate the system clock (). The system clock is output at the pin*1 and furnished as a master clock to prescalers that supply clock signals to the on-chip supporting modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency divider by settings in a division control register (DIVCR)*2. Power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. Notes: 1. Usage of the pin differs depending on the chip operating mode and the PSTOP bit setting in the module standby control register (MSTCR). For details, see section 20.7, System Clock Output Disabling Function. 2. The division ratio of the frequency divider can be changed dynamically during operation. The clock output at the pin also changes when the division ratio is changed. The frequency output at the pin is shown below. = EXTAL x n where, EXTAL: Frequency of crystal resonator or external clock signal n: Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8) Rev. 3.00 Sep 14, 2005 page 649 of 910 REJ09B0258-0300 Section 19 Clock Pulse Generator 19.1.1 Block Diagram Figure 19.1 shows a block diagram of the clock pulse generator. CPG XTAL Oscillator EXTAL Duty adjustment circuit Frequency divider Prescalers Division control register Data bus pin /2 to /4096 Figure 19.1 Block Diagram of Clock Pulse Generator Rev. 3.00 Sep 14, 2005 page 650 of 910 REJ09B0258-0300 Section 19 Clock Pulse Generator 19.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 19.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as in the example in figure 19.2. Damping resistance Rd should be selected according to table 19.1 (1), and external capacitances CL1 and CL2 according to table 19.1 (2). An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 Figure 19.2 Connection of Crystal Resonator (Example) If a crystal resonator with a frequency higher than 20 MHz is connected, the external load capacitance values in table 19.1 (2) should not exceed 10 [pF]. Also, in order to improve the accuracy of the oscillation frequency, a thorough study of oscillation matching evaluation, etc., should be carried out when deciding the circuit constants. Table 19.1 (1) Damping Resistance Value Damping Resistance Value 2 2 < f 4 4 < f 8 8 < f 10 10 < f 13 13 < f 16 16 < f 18 18 < f 25 Rd () 500 1k Frequency f (MHz) 200 0 0 0 0 0 Note: A crystal resonator between 2 MHz and 25 MHz can be used. If the chip is to be operated at less than 2 MHz, the on-chip frequency divider should be used. (A crystal resonator of less than 2 MHz cannot be used.) Rev. 3.00 Sep 14, 2005 page 651 of 910 REJ09B0258-0300 Section 19 Clock Pulse Generator Table 19.1 (2) External Capacitance Values External Capacitance Value 5 V Version Frequency f (MHz) 20 < f 25 2 f 20 CL1 = CL2 (pF) 10 10 to 22 Crystal Resonator: Figure 19.3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 19.2. CL L Rs XTAL EXTAL AT-cut parallel-resonance type C0 Figure 19.3 Crystal Resonator Equivalent Circuit Table 19.2 Crystal Resonator Parameters Frequency (MHz) 2 4 8 10 12 16 18 20 25 Rs max () 500 120 80 70 60 50 40 40 40 Co (pF) 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max Use a crystal resonator with a frequency equal to the system clock frequency (). Notes on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 19.4. When the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Rev. 3.00 Sep 14, 2005 page 652 of 910 REJ09B0258-0300 Section 19 Clock Pulse Generator Avoid C Signal A Signal B H8/3068F chip L2 XTAL EXTAL C L1 Figure 19.4 Oscillator Circuit Block Board Design Precautions 19.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 19.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray capacitance at the XTAL pin exceeds 10 pF in configuration a, use the connection shown in configuration b instead, and hold the external clock high in standby mode. External clock input EXTAL XTAL Open a. XTAL pin left open External clock input EXTAL XTAL b. Complementary clock input at XTAL pin Figure 19.5 External Clock Input (Examples) Rev. 3.00 Sep 14, 2005 page 653 of 910 REJ09B0258-0300 Section 19 Clock Pulse Generator External Clock: The external clock frequency should be equal to the system clock frequency when not divided by the on-chip frequency divider. Table 19.3 shows the clock timing, figure 19.6 shows the external clock input timing, and figure 19.7 shows the external clock output settling delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external devices after the external clock settling time (tDEXT) has passed after the clock input. The system must remain reset with the reset signal low during tDEXT, while the clock output is unstable. Table 19.3 Clock Timing VCC = 5.0 V 10% Item Symbol Min Max Unit Test Conditions External clock input low pulse width tEXL 15 -- ns Figure 19.6 External clock input high pulse width tEXH 15 -- ns External clock rise time tEXr -- 5 ns External clock fall time tEXf -- 5 ns Clock low pulse width tCL 0.4 0.6 tcyc 5 MHz 80 -- ns < 5 MHz 0.4 0.6 tcyc 5 MHz 80 -- ns < 5 MHz 500 -- s Figure 19.7 Clock high pulse width tCH External clock output settling delay time tDEXT* Figure 19.17 Note: * tDEXT includes a RES pulse width (tRESW ). tRESW = 20 tcyc tEXH tEXL VCC x 0.7 EXTAL VCC x 0.5 0.3 V tEXr tEXf Figure 19.6 External Clock Input Timing Rev. 3.00 Sep 14, 2005 page 654 of 910 REJ09B0258-0300 Section 19 Clock Pulse Generator VCC STBY VIH EXTAL (internal or external) RES tDEXT Figure 19.7 External Clock Output Settling Delay Timing 19.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate . 19.4 Prescalers The prescalers divide the system clock () to generate internal clocks (/2 to /4096). Rev. 3.00 Sep 14, 2005 page 655 of 910 REJ09B0258-0300 Section 19 Clock Pulse Generator 19.5 Frequency Divider The frequency divider divides the duty-adjusted clock signal to generate the system clock (). The frequency division ratio can be changed dynamically by modifying the value in DIVCR, as described below. Power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. The system clock generated by the frequency divider can be output at the pin. 19.5.1 Register Configuration Table 19.4 summarizes the frequency division register. Table 19.4 Frequency Division Register Address* Name Abbreviation R/W Initial Value H'EE01B Division control register DIVCR R/W H'FC Note: * Lower 20 bits of the address in advanced mode. 19.5.2 Division Control Register (DIVCR) DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency divider. Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- DIV1 DIV0 Initial value 1 1 1 1 1 1 0 0 Read/Write -- -- -- -- -- -- R/W R/W Reserved bits Divide bits 1 and 0 These bits select the frequency division ratio DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 2--Reserved: These bits cannot be modified and are always read as 1. Rev. 3.00 Sep 14, 2005 page 656 of 910 REJ09B0258-0300 Section 19 Clock Pulse Generator Bits 1 and 0--Divide (DIV1, DIV0): These bits select the frequency division ratio, as follows. Bit 1 DIV1 Bit 0 DIV0 Frequency Division Ratio 0 0 1/1 0 1 1/2 1 0 1/4 1 1 1/8 19.5.3 Usage Notes (Initial value) The DIVCR setting changes the frequency, so note the following points. * Select a frequency division ratio that stays within the assured operation range specified for the clock cycle time tcyc in the AC electrical characteristics. Note that omin = lower limit of the operating frequency range. Ensure that o is not below this lower limit. * All on-chip module operations are based on . Note that the timing of timer operations, serial communication, and other time-dependent processing differs before and after any change in the division ratio. The waiting time for exit from software standby mode also changes when the division ratio is changed. For details, see section 20.4.3, Selection of Waiting Time for Exit from Software Standby Mode. Rev. 3.00 Sep 14, 2005 page 657 of 910 REJ09B0258-0300 Section 19 Clock Pulse Generator Rev. 3.00 Sep 14, 2005 page 658 of 910 REJ09B0258-0300 Section 20 Power-Down State Section 20 Power-Down State 20.1 Overview The H8/3068F has a power-down state that greatly reduces power consumption by halting the CPU, and a module standby function that reduces power consumption by selectively halting onchip modules. The power-down state includes the following three modes: * Sleep mode * Software standby mode * Hardware standby mode The module standby function can halt on-chip supporting modules independently of the powerdown state. The modules that can be halted are the 16-bit timer, 8-bit timer, SCI0, SCI1, SCI2, DMAC, DRAM interface, and A/D converter. Table 20.1 indicates the methods of entering and exiting the power-down modes and module standby mode, and gives the status of the CPU and on-chip supporting modules in each mode. Rev. 3.00 Sep 14, 2005 page 659 of 910 REJ09B0258-0300 tion executed mode Rev. 3.00 Sep 14, 2005 page 660 of 910 REJ09B0258-0300 bit set to 1 in Halted -- mined reset and Halted reset Undeter- and *2 *2 *2 reset held*1 reset reset and reset held*1 reset and Halted and and Halted Halted Halted and Halted reset and Halted and and reset Halted Halted Active and Halted Active Timer Active 8-Bit 16-Bit Interface Timer DRAM *2 reset and Halted reset and Halted reset and Halted Active SCI0 *2 reset and Halted reset and Halted reset and Halted Active SCI1 *2 reset and Halted reset and Halted reset and Halted Active SCI2 *2 reset and Halted reset and Halted reset and Halted Active A/D *2 -- Held Held Held *3 impedance*2 High impedance High output High output Module Standby Control Register L (MSTCRL). * STBY * STBY * RES * IRQ0 to IRQ2 * NMI * STBY * RES * Interrupt Conditions Exiting -- bit to 0*5 * Clear MSTCR * RES * STBY impedance * RES High Held Held Ports I/O Software standby bit MSTCRL: Module standby control register L MSTCRH: Module standby control register H System control register SSBY: 0, then set up the module registers again. 5. When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR bit to 4. When P67 is used as the output pin. 3. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode. SYSCR: Legend Active reset and Halted reset and Halted Active *4 clock Modules RAM output Other 2. State in which the corresponding MSTCR bit was set to 1. For details see section 20.2.2, Module Standby Control Register H (MSTCRH) and section 20.2.3, Notes: 1. RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states. MSTCR Corresponding Active Active standby STBY pin Module mode standby Hardware Low input at Halted Halted while SSBY = 1 mode in SYSCR and reset Halted tion executed Active standby Held Held s Register DMAC CPU Software SLEEP instruc- Halted Halted in SYSCR while SSBY = 0 SLEEP instruc- Active Halted Sleep Clock CPU Conditions Entering Mode State Section 20 Power-Down State Table 20.1 Power-Down State and Module Standby Function Section 20 Power-Down State 20.2 Register Configuration The H8/3068F has a system control register (SYSCR) that controls the power-down state, and module standby control registers H (MSTCRH) and L (MSTCRL) that control the module standby function. Table 20.2 summarizes these registers. Table 20.2 Control Register Address* Name Abbreviation R/W Initial Value H'EE012 System control register SYSCR R/W H'09 H'EE01C Module standby control register H MSTCRH R/W H'78 H'EE01D Module standby control register L MSTCRL R/W H'00 Note: * Lower 20 bits of the address in advanced mode. 20.2.1 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 UE NMIEG SSOE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W RAM enable Software standby output port enable NMI edge select User bit enable Standby timer select 2 to 0 These bits select the waiting time of the CPU and peripheral functions Software standby Enables transition to software standby mode SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY), bits 6 to 4 (STS2 to STS0), and bit 1 (SSOE) control the power-down state. For information on the other SYSCR bits, see section 3.3, System Control Register (SYSCR). Rev. 3.00 Sep 14, 2005 page 661 of 910 REJ09B0258-0300 Section 20 Power-Down State Bit 7--Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY Description 0 SLEEP instruction causes transition to sleep mode 1 SLEEP instruction causes transition to software standby mode (Initial value) Bits 6 to 4--Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the clock to settle when software standby mode is exited by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to the clock frequency so that the waiting time will be at least 7 ms (oscillation settling time). See table 20.3. If an external clock is used, set these bits so that the waiting time will be at least 100 s. Bit 6 STS2 Bit 5 STS1 Bit 4 STS0 Description 0 0 0 Waiting time = 8,192 states 1 Waiting time = 16,384 states 0 Waiting time = 32,768 states 1 Waiting time = 65,536 states 1 1 0 1 0 Waiting time = 131,072 states 1 Waiting time = 262,144 states 0 Waiting time = 1,024 states 1 Illegal setting (Initial value) Bit 1--Software Standby Output Port Enable (SSOE): Specifies whether the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as outputs or fixed high, or placed in the high-impedance state in software standby mode. Bit 1 SSOE Description 0 In software standby mode, the address bus and bus control signals are all high-impedance 1 In software standby mode, the address bus retains its output state and bus control signals are fixed high Rev. 3.00 Sep 14, 2005 page 662 of 910 REJ09B0258-0300 (Initial value) Section 20 Power-Down State 20.2.2 Module Standby Control Register H (MSTCRH) MSTCRH is an 8-bit readable/writable register that controls output of the system clock (). It also controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the SCI0, SCI1, SCI2. Bit 7 6 5 4 3 2 1 0 MSTPH2 MSTPH1 MSTPH0 PSTOP -- -- -- -- Initial value 0 1 1 1 1 0 0 0 Read/Write R/W -- -- -- -- R/W R/W R/W Reserved bit Module standby H2 to 0 These bits select modules to be placed in standby clock stop Enables or disables output of the system clock MSTCRH is initialized to H'78 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7-- Clock Stop (PSTOP): Enables or disables output of the system clock (). Bit 1 PSTOP Description 0 System clock output is enabled 1 System clock output is disabled (Initial value) Bits 6 to 3--Reserved: These bits cannot be modified and are always read as 1. Bit 2--Module Standby H2 (MSTPH2): Selects whether to place the SCI2 in standby. Bit 2 MSTPH2 Description 0 SCI2 operates normally 1 SCI2 is in standby state (Initial value) Rev. 3.00 Sep 14, 2005 page 663 of 910 REJ09B0258-0300 Section 20 Power-Down State Bit 1--Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby. Bit 1 MSTPH1 Description 0 SCI1 operates normally 1 SCI1 is in standby state (Initial value) Bit 0--Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby. Bit 0 MSTPH0 Description 0 SCI0 operates normally 1 SCI0 is in standby state 20.2.3 (Initial value) Module Standby Control Register L (MSTCRL) MSTCRL is an 8-bit readable/writable register that controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the DMAC, 16-bit timer, DRAM interface, 8-bit timer, and A/D converter modules. Bit 7 6 MSTPL7 -- Initial value 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W 5 4 3 2 1 0 -- MSTPL0 0 0 0 R/W R/W R/W MSTPL5 MSTPL4 MSTPL3 MSTPL2 Module standby L7, L5 to L2, L0 These bits select modules to be placed in standby Reserved bits MSTCRL is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 3.00 Sep 14, 2005 page 664 of 910 REJ09B0258-0300 Section 20 Power-Down State Bit 7--Module Standby L7 (MSTPL7): Selects whether to place the DMAC in standby. Bit 7 MSTPL7 Description 0 DMAC operates normally 1 DMAC is in standby state (Initial value) Bit 6--Reserved: This bit can be written and read. Bit 5--Module Standby L5 (MSTPL5): Selects whether to place the DRAM interface in standby. Bit 5 MSTPL5 Description 0 DRAM interface operates normally 1 DRAM interface is in standby state (Initial value) Bit 4--Module Standby L4 (MSTPL4): Selects whether to place the 16-bit timer in standby. Bit 4 MSTPL4 Description 0 16-bit timer operates normally 1 16-bit timer is in standby state (Initial value) Bit 3--Module Standby L3 (MSTPL3): Selects whether to place 8-bit timer channels 0 and 1 in standby. Bit 3 MSTPL3 Description 0 8-bit timer channels 0 and 1 operate normally 1 8-bit timer channels 0 and 1 are in standby state (Initial value) Rev. 3.00 Sep 14, 2005 page 665 of 910 REJ09B0258-0300 Section 20 Power-Down State Bit 2--Module Standby L2 (MSTPL2): Selects whether to place 8-bit timer channels 2 and 3 in standby. Bit 2 MSTPL2 Description 0 8-bit timer channels 2 and 3 operate normally 1 8-bit timer channels 2 and 3 are in standby state (Initial value) Bit 1--Reserved: This bit can be written and read. Bit 0--Module Standby L0 (MSTPL0): Selects whether to place the A/D converter in standby. Bit 0 MSTPL0 Description 0 A/D converter operates normally 1 A/D converter is in standby state Rev. 3.00 Sep 14, 2005 page 666 of 910 REJ09B0258-0300 (Initial value) Section 20 Power-Down State 20.3 Sleep Mode 20.3.1 Transition to Sleep Mode When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained. The DMA controller (DMAC), DRAM interface, and on-chip supporting modules do not halt in sleep mode. Modules which have been placed in standby by the module standby function, however, remain halted. 20.3.2 Exit from Sleep Mode Sleep mode is exited by an interrupt, or by input at the RES or STBY pin. Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by an interrupt other than NMI if the interrupt is masked by interrupt priority settings and the settings of the I and UI bits in CCR, IPR. Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state. Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby mode. Rev. 3.00 Sep 14, 2005 page 667 of 910 REJ09B0258-0300 Section 20 Power-Down State 20.4 Software Standby Mode 20.4.1 Transition to Software Standby Mode To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in SYSCR. In software standby mode, current dissipation is reduced to an extremely low level because the CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting modules are reset and halted. As long as the specified voltage is supplied, however, CPU register contents and on-chip RAM data are retained. The settings of the I/O ports and DRAM interface* are also held. When the WDT is used as a watchdog timer (WT/IT = 1), the TME bit must be cleared to 0 before setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0. Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software standby mode. Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states. 20.4.2 Exit from Software Standby Mode Software standby mode can be exited by input of an external interrupt at the NMI, IRQ0, IRQ1, or IRQ2 pin, or by input at the RES or STBY pin. Exit by Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is received, the clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0 in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and interrupt exception handling begins. Software standby mode is not exited if the interrupt enable bits of interrupts IRQ0, IRQ1, and IRQ2 are cleared to 0, or if these interrupts are masked in the CPU. Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are supplied immediately to the entire chip. The RES signal must be held low long enough for the clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling. Exit by STBY Input: Low input at the STBY pin causes a transition to hardware standby mode. Rev. 3.00 Sep 14, 2005 page 668 of 910 REJ09B0258-0300 Section 20 Power-Down State 20.4.3 Selection of Waiting Time for Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows. Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to stabilize) is at least 7 ms. Table 20.3 indicates the waiting times that are selected by STS2 to STS0, DIV1, and DIV0 settings at various system clock frequencies. External Clock: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time is at least 100 s. Table 20.3 Clock Frequency and Waiting Time for Clock to Settle DIV1 DIV0 STS2 STS1 STS0 Waiting Time 25 MHz 20 MHz 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 MHz Unit 0 1.0 1.3 2.0 4.1 8.2* ms 0 1 1 0 1 0 1 0 0 0 8192 states 0.3 0.4 0.46 0 0 1 16384 states 0.7 0.8 0.91 1.0 1.3 1.6 2.0 2.7 4.1 8.2* 16.4 0 1 0 32768 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2* 16.4 32.8 0 1 1 65536 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4 32.8 65.5 1 0 0 131072 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5 131.1 1 0 1 262144 states 10.5* 13.1* 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1 1 1 0 1024 states 0.05 0.057 0.064 0.085 0.10 0.13 0.17 0.26 0.51 1.0 1 1 1 0.04 0.51 0.65 0.8 Illegal setting 0 0 0 8192 states 0.7 0.8 0.91 1.02 1.4 1.6 2.0 2.7 4.1 8.2* 16.4* 0 0 1 16384 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2* 16.4 32.8 0 1 0 32768 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4 32.8 65.5 0 1 1 65536 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5 131.1 1 0 0 131072 states 10.5* 13.1* 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1 1 0 1 262144 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3 1 1 0 1024 states 0.10 0.11 0.13 0.17 0.20 0.26 0.34 0.51 1.0 2.0 1 1 1 0.08 Illegal setting 0 0 0 8192 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2* 16.4* 32.8* 0 0 1 16384 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4 32.8 65.5 0 1 0 32768 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5 131.1 0 1 1 65536 states 10.5* 13.1* 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1 1 0 0 131072 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3 1 0 1 262144 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1048.6 1 1 0 1024 states 0.20 0.23 0.26 0.34 0.41 0.51 0.68 1.02 2.0 4.1 1 1 1 0.16 0 0 0 8192 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4* 32.8* 65.5 0 1 16384 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5 131.1 0 1 0 32768 states 10.5 13.1* 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1 0 1 1 65536 states 21.0* 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3 1 0 0 131072 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1048.6 1 0 1 262144 states 83.9 104.9 116.5 131.1 174.8 209.7 262.1 349.5 524.3 1048.6 2097.1 1024 states 0.41 0.46 0.51 0.68 0.82 1.0 1.4 2.0 4.1 1 0 1 1 1 ms Illegal setting 0 1 ms 0.33 ms 8.2* Illegal setting * : Recommended setting Rev. 3.00 Sep 14, 2005 page 669 of 910 REJ09B0258-0300 Section 20 Power-Down State 20.4.4 Sample Application of Software Standby Mode Figure 20.1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit is set to 1; then the SLEEP instruction is executed to enter software standby mode. Software standby mode is exited at the next rising edge of the NMI signal. Clock oscillator NMI NMIEG SSBY NMI interrupt handler NMIEG = 1 SSBY = 1 Software standby mode (powerdown state) Oscillator settling time (tosc2) NMI exception handling SLEEP instruction Figure 20.1 NMI Timing for Software Standby Mode (Example) 20.4.5 Note The I/O ports retain their existing states in software standby mode. If a port is in the high output state, its output current is not reduced. Rev. 3.00 Sep 14, 2005 page 670 of 910 REJ09B0258-0300 Section 20 Power-Down State 20.5 Hardware Standby Mode 20.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU, DMAC, DRAM interface, and on-chip supporting modules. All modules are reset except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is retained. I/O ports are placed in the high-impedance state. Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data. The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby mode. 20.5.2 Exit from Hardware Standby Mode Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when STBY goes high, the clock oscillator starts running. RES should be held low long enough for the clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a transition to the program execution state. 20.5.3 Timing for Hardware Standby Mode Figure 20.2 shows the timing relationships for hardware standby mode. To enter hardware standby mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive STBY high, wait for the clock to settle, then bring RES from low to high. Rev. 3.00 Sep 14, 2005 page 671 of 910 REJ09B0258-0300 Section 20 Power-Down State Clock oscillator RES STBY Oscillator settling time Reset exception handling Figure 20.2 Hardware Standby Mode Timing Rev. 3.00 Sep 14, 2005 page 672 of 910 REJ09B0258-0300 Section 20 Power-Down State 20.6 Module Standby Function 20.6.1 Module Standby Timing The module standby function can halt several of the on-chip supporting modules (SCI2, SCI1, SCI0, the DMAC, 16-bit timer, 8-bit timer, DRAM interface, and A/D converter) independently in the power-down state. This standby function is controlled by bits MSTPH2 to MSTPH0 in MSTCRH and bits MSTPL7 to MSTPL0 in MSTCRL. When one of these bits is set to 1, the corresponding on-chip supporting module is placed in standby and halts at the beginning of the next bus cycle after the MSTCR write cycle. 20.6.2 Read/Write in Module Standby When an on-chip supporting module is in module standby, read/write access to its registers is disabled. Read access always results in H'FF data. Write access is ignored. 20.6.3 Usage Notes When using the module standby function, note the following points. DMAC: When setting a bit in MSTCR to 1 to place the DMAC in module standby, make sure that the DMAC is not currently requesting the bus right. If the corresponding bit in MSTCR is set to 1 when a bus request is present, operation of the bus arbiter becomes ambiguous and a malfunction may occur. DRAM Interface: When the module standby function is used on the DRAM interface, set the MSTCR bit to 1 while DRAM space is deselected. On-Chip Supporting Module Interrupts: Before setting a module standby bit, first disable interrupts by that module. When an on-chip supporting module is placed in standby by the module standby function, its registers are initialized, including registers with interrupt request flags. Pin States: Pins used by an on-chip supporting module lose their module functions when the module is placed in module standby. What happens after that depends on the particular pin. For details, see section 8, I/O Ports. Pins that change from the input to the output state require special care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data function and becomes a port pin. If its port DDR bit is set to 1, the pin becomes a data output pin, and its output may collide with external SCI transmit data. Data collision should be prevented by clearing the port DDR bit to 0 or taking other appropriate action. Register Resetting: When an on-chip supporting module is halted by the module standby function, all its registers are initialized. To restart the module, after its MSTCR bit is cleared to 0, Rev. 3.00 Sep 14, 2005 page 673 of 910 REJ09B0258-0300 Section 20 Power-Down State its registers must be set up again. It is not possible to write to the registers while the MSTCR bit is set to 1. MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be accessed from the CPU. It can be read by the DMAC, but it cannot be written by the DMAC. 20.7 System Clock Output Disabling Function Output of the system clock () can be controlled by the PSTOP bit in MSTCRH. When the PSTOP bit is set to 1, output of the system clock halts and the pin is placed in the highimpedance state. Figure 20.3 shows the timing of the stopping and starting of system clock output. When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 20.4 indicates the state of the pin in various operating states. MSTCRH write cycle MSTCRH write cycle (PSTOP = 1) (PSTOP = 0) T1 T2 T3 T1 T2 T3 pin High impedance Figure 20.3 Starting and Stopping of System Clock Output Table 20.4 Pin State in Various Operating States Operating State PSTOP = 0 PSTOP = 1 Hardware standby High impedance High impedance Software standby Always high High impedance Sleep mode System clock output High impedance Normal operation System clock output High impedance Rev. 3.00 Sep 14, 2005 page 674 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics Section 21 Electrical Characteristics 21.1 Electrical Characteristics of H8/3068F-ZTAT 21.1.1 Absolute Maximum Ratings Table 21.1 lists the absolute maximum ratings. Table 21.1 Absolute Maximum Ratings Item Symbol Value Unit VCC* -0.3 to +7.0 V Vin -0.3 to VCC +0.3 V Input voltage (except for port 7)* Vin -0.3 to VCC +0.3 V Input voltage (port 7) Vin -0.3 to AVCC +0.3 V Reference voltage VREF -0.3 to AVCC +0.3 V Analog power supply voltage AVCC -0.3 to +7.0 V Analog input voltage VAN -0.3 to AVCC +0.3 V 1 Power supply voltage Input voltage (FWE)* 2 2 3 Operating temperature Topr -20 to +75* C Storage temperature Tstg -55 to +125 C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Notes: 1. Do not apply the power supply voltage to the VCL pin. Connect an external capacitor between this pin and GND. 2. 12 V must not be applied to any pin, as this may cause permanent damage to the device. 3. The operating temperature range for flash memory programming/erasing is 0C to +75C. Rev. 3.00 Sep 14, 2005 page 675 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics 21.1.2 DC Characteristics Table 21.2 lists the DC characteristics. Table 21.3 lists the permissible output currents. Table 21.2 DC Characteristics (1) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 V to AVCC*1, VSS = AVSS = 0 V*1, Ta = -20C to +75C [Programming/erasing conditions: Ta = 0C to +75C] Item Schmitt trigger input voltages Input high voltage Input low voltage Symbol Port A, P80 to P82 VT - VT + + VT - VT - Min Typ Max Unit 1.0 -- -- V -- -- VCC x 0.7 V 0.4 -- -- V VCC - 0.7 -- VCC + 0.3 V EXTAL VCC x 0.7 -- VCC + 0.3 V Port 7 2.0 -- AVCC + 0.3 V Ports 1 to 6, P83, P84, P90 to P95, port B 2.0 -- VCC + 0.3 V -0.3 -- 0.5 V -0.3 -- 0.8 V -- -- V STBY, RES, VIH Test Conditions NMI, MD2 to MD0, FWE STBY, RES, VIL FWE, MD2 to MD0 NMI, EXTAL, ports 1 to 7, P83, P84, P90 to P95, port B IOH = -200 A Output high voltage All output pins VOH VCC - 0.5 3.5 -- -- V IOH = -1 mA Output low voltage All output pins VOL -- -- 0.4 V IOL = 1.6 mA -- -- 1.0 V IOL = 10 mA Ports 1, 2, and 5 Rev. 3.00 Sep 14, 2005 page 676 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics Item Test Conditions Symbol Min Typ Max Unit |Iin| -- -- 1.0 A Vin = 0.5 V to VCC - 0.5 V -- -- 1.0 A Vin = 0.5 V to AVCC - 0.5 V |ITSI| -- -- 1.0 A Vin = 0.5 V to VCC - 0.5 V Input pull-up Ports 2, 4, MOS current and 5 -Ip 50 -- 300 A Vin = 0 V Input capacitance Cin -- -- 80 pF NMI -- -- 50 pF Vin = 0 V f = fmin Ta = 25C All input pins except NMI -- -- 15 pF -- 32 47 (5.0 V) mA Input leakage current STBY, RES, NMI, FWE, MD2 to MD0 Port 7 Three-state leakage current Ports 1 to 6 Ports 8 to B FWE Current Normal 2 dissipation* operation ICC*4 37 58 (5.0 V) Sleep mode -- 24 38 (5.0 V) f = 25 MHz mA 29 47 (5.0 V) Module standby mode -- 19 31 (5.0 V) f = 20 MHz f = 20 MHz f = 25 MHz mA 21 37 (5.0 V) f = 20 MHz f = 25 MHz Standby mode*3 -- 1.0 10 A Ta 50C -- -- 80 A 50C < Ta Flash memory programming/ erasing*5 -- 37 57 mA f = 20 MHz 42 68 f = 25 MHz Rev. 3.00 Sep 14, 2005 page 677 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics Item Symbol Min Typ Max Unit Analog During A/D power supply conversion current AICC -- 0.6 1.5 mA During A/D and D/A conversion -- 0.6 1.5 mA Idle -- 0.01 5 A -- 0.45 0.8 mA During A/D and D/A conversion -- 2.0 3.0 mA Idle -- 0.01 5 A 2.0 -- -- V Reference current During A/D conversion RAM standby voltage AICC VRAM Test Conditions DASTE = 0 DASTE = 0 Notes: 1. If the A/D converter is not used, do not leave the AVCC, VREF, and AVSS pins open. Connect AVCC and VREF to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip MOS pull-up transistors in the off state. 3. The values are for VRAM VCC < 4.5 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 4. ICC max. (normal operation) = 3.0 (mA) + 0.40 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode) = 3.0 (mA) + 0.32 (mA/(MHz x V)) x VCC x f ICC max. (sleep mode + module standby mode) = 3.0 (mA) + 0.25 (mA/(MHz x V)) x VCC x f The Typ values for power consumption are reference values. 5. Sum of current dissipation in normal operation and current dissipation in program/erase operations. Rev. 3.00 Sep 14, 2005 page 678 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics Table 21.3 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = -40C to +75C Item Permissible output low current (per pin) Ports 1, 2, and 5 Permissible output low current (total) Total of 20 pins in Ports 1, 2, and 5 Symbol Min Typ Max Unit IOL -- -- 10 mA -- -- 2.0 mA -- -- 80 mA -- -- 120 mA Other output pins IOL Total of all output pins, including the above Permissible output high current (per pin) All output pins | -IOH | -- -- 2.0 mA Permissible output high current (total) Total of all output pins | IOH | -- -- 40 mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 21.3. 2. When directly driving a darlington pair or LED, always insert a current-limiting resistor in the output line, as shown in figures 21.1 and 21.2. H8/3068F-ZTAT 2 k Port Darlington pair Figure 21.1 Darlington Pair Drive Circuit (Example) Rev. 3.00 Sep 14, 2005 page 679 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics H8/3068F-ZTAT 600 Ports 1, 2, 5 LED Figure 21.2 Sample LED Circuit Rev. 3.00 Sep 14, 2005 page 680 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics 21.1.3 AC Characteristics Clock timing parameters are listed in table 21.4, control signal timing parameters in table 21.5, and bus timing parameters in table 21.6. Timing parameters of the on-chip supporting modules are listed in table 21.7. Table 21.4 Clock Timing Condition: Ta = -20C to +75C Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 20 MHz Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Condition A Item Symbol Min Clock cycle time tcyc Clock pulse low width tCL Clock pulse high width B Max Min Max Unit Test Conditions 50 500 40 500 ns 15 -- 10 -- ns Figure 21.4 to figure 21.6 tCH 15 -- 10 -- ns Clock rise time tCr -- 10 -- 10 ns Clock fall time tCf -- 10 -- 10 ns Clock oscillator settling time at reset tOSC1 20 -- 20 -- ms Clock oscillator settling time in software standby tOSC2 7 -- 7 -- ms Figure 21.4 Rev. 3.00 Sep 14, 2005 page 681 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics Table 21.5 Control Signal Timing Condition: Ta = -20C to +75C Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 20 MHz Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Condition A and B Item Symbol Min Max Unit Test Conditions Figure 21.5 RES setup time RES pulse width tRESS 150 -- ns tRESW 20 -- tcyc Mode programming setup time tMDS 200 -- ns NMI, IRQ setup time tNMIS 150 -- ns NMI, IRQ hold time tNMIH 10 -- ns NMI, IRQ pulse width tNMIW 200 -- ns Rev. 3.00 Sep 14, 2005 page 682 of 910 REJ09B0258-0300 Figure 21.7 Section 21 Electrical Characteristics Table 21.6 Bus Timing Condition: Ta = -20C to +75C Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 20 MHz Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Condition A and B Item Symbol Min Max Unit Test Conditions Address delay time tAD -- Address hold time tAH 0.5 tcyc - 20 25 ns -- ns Figure 21.8, figure 21.9 Read strobe delay time tRSD -- 25 ns Address strobe delay time tASD -- 25 ns Write strobe delay time tWSD -- 25 ns Strobe delay time tSD -- 25 ns Write strobe pulse width 1 tWSW1 1.0 tcyc - 25 -- ns Write strobe pulse width 2 tWSW2 1.5 tcyc - 25 -- ns Address setup time 1 tAS1 0.5 tcyc - 20 -- ns Address setup time 2 tAS2 1.0 tcyc - 20 -- ns Read data setup time tRDS 25 -- ns Read data hold time tRDH 0 -- ns Write data delay time tWDD -- 35 ns Write data setup time 1 tWDS1 1.0 tcyc - 30 -- ns Write data setup time 2 tWDS2 2.0 tcyc - 30 -- ns Write data hold time tWDH 0.5 tcyc - 15 -- ns Read data access time 1 tACC1 -- 2.0 tcyc - 45 ns Read data access time 2 tACC2 -- 3.0 tcyc - 45 ns Read data access time 3 tACC3 -- 1.5 tcyc - 45 ns Read data access time 4 tACC4 -- 2.5 tcyc - 45 ns Precharge time 1 tPCH1 1.0 tcyc - 20 -- ns Precharge time 2 tPCH2 0.5 tcyc - 20 -- ns Figure 21.17, figure 21.18 Rev. 3.00 Sep 14, 2005 page 683 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics Condition A and B Item Symbol Min Max Unit Test Conditions Wait setup time tWTS 25 -- ns Figure 21.19 Wait hold time tWTH 5 -- ns Bus request setup time tBRQS 25 -- ns Bus acknowledge delay time 1 tBACD1 -- 30 ns Bus acknowledge delay time 2 tBACD2 -- 30 ns Bus-floating time RAS precharge time CAS precharge time Low address hold time RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 WE delay time CAS pulse width 1 CAS pulse width 2 CAS pulse width 3 RAS access time Address access time CAS access time WE setup time WE hold time Write data setup time WE write data hold time CAS setup time 1 CAS setup time 2 CAS hold time RAS pulse width tBZD -- 30 ns tRP 1.5 tcyc - 25 -- ns tCP 0.5 tcyc - 15 -- ns tRAH 0.5 tcyc - 15 -- ns tRAD1 -- 25 ns tRAD2 -- 30 ns tCASD1 -- 25 ns tCASD2 -- 25 ns tWCD -- 25 ns tCAS1 1.5 tcyc - 20 -- ns tCAS2 1.0 tcyc - 20 -- ns tCAS3 1.0 tcyc - 20 -- ns tRAC -- 2.5 tcyc - 40 ns tAA -- 2.0 tcyc - 50 ns tCAC -- 1.5 tcyc - 50 ns tWCS 0.5 tcyc - 20 -- ns tWCH 0.5 tcyc - 15 -- ns tWDS 0.5 tcyc - 20 -- ns tWDH 0.5 tcyc - 15 -- ns tCSR1 0.5 tcyc - 20 -- ns tCSR2 0.5 tcyc - 15 -- ns tCHR 0.5 tcyc - 15 -- ns tRAS 1.5 tcyc - 15 -- ns Figure 21.20 Figure 21.17 to figure 21.19 Note: In order to secure the address hold time relative to the rise of the RD strobe, address update mode 2 should be used. For details see section 6.3.5, Address Output Method. Rev. 3.00 Sep 14, 2005 page 684 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics Table 21.7 Timing of On-Chip Supporting Modules Condition: Ta = -20C to +75C Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 20 MHz Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Condition A and B Module Item Symbol Min Max Unit Test Conditions Ports and TPC Output data delay time tPWD -- 50 ns Figure 21.21 Input data setup time tPRS 50 -- ns Input data hold time tPRH 50 -- ns 16-bit timer Timer output delay time tTOCD -- 50 ns Timer input setup time tTICS 50 -- ns Timer clock input setup time tTCKS 50 -- ns Timer clock Single edge pulse width Both edges tTCKWH 1.5 -- tcyc tTCKWL 2.5 -- tcyc Timer output delay time tTOCD -- 50 ns Timer input setup time tTICS 50 -- ns Timer clock input setup time tTCKS 50 -- ns Timer clock Single edge pulse width Both edges tTCKWH 1.5 -- tcyc tTCKWL 2.5 -- tcyc 8-bit timer Figure 21.22 Figure 21.23 Figure 21.22 Figure 21.23 Rev. 3.00 Sep 14, 2005 page 685 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics Condition A and B Module Item SCI Input clock cycle DMAC Symbol Min Max Unit Test Conditions tScyc 4 -- tcyc Figure 21.24 6 -- tcyc Input clock rise time tSCKr -- 1.5 tcyc Input clock fall time tSCKf -- 1.5 tcyc Input clock pulse width tSCKW 0.4 0.6 tScyc Transmit data delay time tTXD -- 100 ns Receive data setup time (synchronous) tRXS 100 -- ns Receive data hold time (synchronous) tRXH 100 -- ns 0 -- ns tTED1 -- 50 ns tTED2 -- 50 ns Figure 21.25, figure 21.26 tDRQS 25 -- ns Figure 21.27 tDRQH 10 -- ns Asynchronous Synchronous Clock input Clock output TEND delay time 1 TEND delay time 2 DREQ setup time DREQ hold time RL H8/3068F-ZTAT output pin Figure 21.25 C = 90 pF: ports 1 to 6, 8 C = 30 pF: ports 9, A, B R L = 2.4 k R H = 12 k C RH Input/output timing measurement levels * Low: 0.8 V * High: 2.0 V Figure 21.3 Output Load Circuit Rev. 3.00 Sep 14, 2005 page 686 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics 21.1.4 A/D Conversion Characteristics Table 21.8 lists the A/D conversion characteristics. Table 21.8 A/D Conversion Characteristics Condition: Ta = -20C to +75C Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 20 MHz Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Condition A and B Item Min Typ Max Unit Conversion time: Resolution 134 states Conversion time (single mode) 10 10 10 bits -- -- 134 tcyc Analog input capacitance -- -- 20 pF 13 MHz -- -- 10 k > 13 MHz -- -- 5 k 4.0 V AVCC 5.5 V -- -- -- k 3.0 V AVCC < 4.0 V -- -- -- k Nonlinearity error -- -- 3.5 LSB Offset error -- -- 3.5 LSB Full-scale error -- -- 3.5 LSB Quantization error -- -- 0.5 LSB Absolute accuracy -- -- 4.0 LSB Permissible signalsource impedance Rev. 3.00 Sep 14, 2005 page 687 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics Condition A and B Item Min Typ Max Unit Conversion time: Resolution 70 states Conversion time (single mode) 10 10 10 bits -- -- 70 tcyc Analog input capacitance -- -- 20 pF 13 MHz -- -- 5 k > 13 MHz -- -- 3 k 4.0 V AVCC 5.5 V -- -- -- k 3.0 V AVCC < 4.0 V -- -- -- k Nonlinearity error -- -- 7.5 LSB Offset error -- -- 7.5 LSB Full-scale error -- -- 7.5 LSB Quantization error -- -- 0.5 LSB Absolute accuracy -- -- 8.0 LSB Permissible signalsource impedance Rev. 3.00 Sep 14, 2005 page 688 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics 21.1.5 D/A Conversion Characteristics Table 21.9 lists the D/A conversion characteristics. Table 21.9 D/A Conversion Characteristics Condition: Ta = -20C to +75C Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 20 MHz Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V, fmax = 25 MHz Condition A and B Item Min Typ Max Unit Test Conditions Resolution 8 8 8 bits Conversion time (centering time) -- -- 10 s 20 pF capacitive load Absolute accuracy -- 1.5 2.0 LSB 2 M resistive load -- -- 1.5 LSB 4 M resistive load Rev. 3.00 Sep 14, 2005 page 689 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics 21.1.6 Flash Memory Characteristics Table 21.10 shows the flash memory characteristics. Table 21.10 Flash Memory Characteristics Conditions: VCC = 4.5 to 5.5 V, AVCC = 4.5 to 5.5 V, VSS = AVSS = 0 V, Ta = 0C to +75C (operating temperature range for programming/erasing) Item Symbol Min Typ Max Unit Programming time* * * tP -- 10 200 ms/ 128 bytes 1 tE -- 1200 ms/block 1 3 2 4 5 Erase time* * * 100 6 7 Notes Reprogramming count NWEC 100* 10,000* -- Times Data retention period tDRP 10*8 -- -- Years Programming Wait time after SWE bit setting* tsswe 1 1 -- s 1 tspsu 50 50 -- s tsp30 28 30 32 s Programming time wait tsp200 198 200 202 s Programming time wait tsp10 8 10 12 s Additionalprogramming time wait 1 Wait time after PSU bit setting* 1 4 Wait time after P bit setting* * 1 Wait time after P bit clear* tcp 5 5 -- s 1 tcpsu 5 5 -- s 1 Wait time after PV bit setting* tspv 4 4 -- s Wait time after H'FF dummy 1 write* tspvr 2 2 -- s tcpv 2 2 -- s Wait time after SWE bit clear* tcswe 100 100 -- s Maximum programming 1 4 count* * N -- -- 1000 Times tsswe 1 1 -- s Wait time after ESU bit setting* tsesu 100 100 -- s Wait time after E bit setting*1 *5 tse 10 10 100 ms Wait time after E bit clear*1 tce 10 10 -- s tcesu 10 10 -- s Wait time after PSU bit clear* Wait time after PV bit clear*1 1 Erase Wait time after SWE bit setting*1 1 1 Wait time after ESU bit clear* Rev. 3.00 Sep 14, 2005 page 690 of 910 REJ09B0258-0300 Erase time wait Section 21 Electrical Characteristics Item Erase Symbol Min Typ Max Unit Wait time after EV bit setting* tsev 20 20 -- s Wait time after H'FF dummy 1 write* tsevr 2 2 -- s tcev 4 4 -- s tcswe 100 100 -- s N 12 -- 120 Times 1 1 Wait time after EV bit clear* 1 Wait time after SWE bit clear* 1 4 Maximum erase count* * Notes Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. To specify the maximum programming time (tP(max)) in the 128-byte programming flowchart, set the maximum value (1000) for the maximum programming count (N). The wait time after P bit setting should be changed as follows according to the value of the programming counter (n). Programming counter (n) = 1 to 6: tsp30 = 30 s Programming counter (n) = 7 to 1000: tsp200 = 200 s Programming counter (n) [in additional programming] = 1 to 6: tsp10 = 10 s 5. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (tse) and the maximum erase count (N): tE(max) = Wait time after E bit setting (tse) x maximum erase count (N) To set the maximum erase time, the values of tse and N should be set so as to satisfy the above formula. Examples: When tse = 100 [ms], N = 12 times When tse = 10 [ms], N = 120 times 6. Minimum number of times at which all characteristics are guaranteed after reprogramming. (Reprogramming count from 1 to minimum value is guaranteed.) 7. Reference characteristics at 25C. (This is an indication that reprogramming operations can normally be performed up to this figure.) 8. Data retention characteristics when reprogramming is performed correctly within the specification values, including the minimum data retention period. Rev. 3.00 Sep 14, 2005 page 691 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics 21.2 Operational Timing This section shows timing diagrams. 21.2.1 Clock Timing Clock timing is shown as follows: * Oscillator settling timing Figure 21.4 shows the oscillator settling timing. VCC STBY tOSC1 tOSC1 RES Figure 21.4 Oscillator Settling Timing Rev. 3.00 Sep 14, 2005 page 692 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics 21.2.2 Control Signal Timing Control signal timing is shown as follows: * Reset input timing Figure 21.5 shows the reset input timing. * Reset output timing* Figure 21.6 shows the reset output timing. * Interrupt input timing Figure 21.7 shows the interrupt input timing for NMI and IRQ5 to IRQ0. tRESS tRESS RES tMDS tRESW FWE MD2 to MD0 Figure 21.5 Reset Input Timing tRESD tRESD RESO tRESOW Figure 21.6 Reset Output Timing* Note: * This function is used only in mask ROM models, and is not provided in flash memory models. Rev. 3.00 Sep 14, 2005 page 693 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics tNMIS tNMIH tNMIS tNMIH NMI IRQ E tNMIS IRQ L IRQ E : Edge-sensitive IRQ i IRQ L : Level-sensitive IRQ i (i = 0 to 5) tNMIW NMI IRQ j (j = 0 to 5) Figure 21.7 Interrupt Input Timing 21.2.3 Bus Timing Bus timing is shown as follows: * Basic bus cycle: two-state access Figure 21.8 shows the timing of the external two-state access cycle. * Basic bus cycle: three-state access Figure 21.9 shows the timing of the external three-state access cycle. * Basic bus cycle: three-state access with one wait state Figure 21.10 shows the timing of the external three-state access cycle with one wait state inserted. * Bus-release mode timing Figure 21.11 shows the bus-release mode timing. Rev. 3.00 Sep 14, 2005 page 694 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics T1 tcyc T2 tCH tCL tCf tAD tcyc tCr A23 to A0, CSn tPCH1 AS RD (read) tASD tACC3 tASD tACC3 tSD tAH tAS1 tRSD tPCH2 tAS1 tACC1 tRDH* tRDS D15 to D0 (read) tPCH1 tASD HWR, LWR (write) tSD tAH tAS1 tWDD tWSW1 tWDS1 tWDH D15 to D0 (write) Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD. Figure 21.8 Basic Bus Cycle: Two-State Access Rev. 3.00 Sep 14, 2005 page 695 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics T1 T2 T3 A23 to A0, CSn tACC4 AS tACC4 RD (read) tACC2 tRDS D15 to D0 (read) tWSD HWR, LWR (write) tWSW2 tAS2 tWDD tWDS2 D15 to D0 (write) Figure 21.9 Basic Bus Cycle: Three-State Access Rev. 3.00 Sep 14, 2005 page 696 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics T1 T2 TW T3 A23 to A0, CSn AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 21.10 Basic Bus Cycle: Three-State Access with One Wait State Rev. 3.00 Sep 14, 2005 page 697 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics T1 T2 T3 T1 T2 tAD tAD A23 to A3 CSn A2 to A0 tASD AS tACC4 tAH tAS1 tASD tSD tAH tAS1 tASD RD tSD tRSD tACC4 tAS1 tACC2 tRDS tACC1 tRDH* tRDS D15 to D0 Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD. Figure 21.11 Burst ROM Access Timing: Two-State Access Rev. 3.00 Sep 14, 2005 page 698 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics T1 T2 T3 T1 T2 T3 tAD tAD A23 to A3 CSn A2 to A0 tASD AS tACC4 tAH tAS1 tASD tSD tAH tAS1 tASD RD tSD tRSD tACC4 tRDH* tAS1 tACC2 tACC2 tRDS tRDS D15 to D0 Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD. Figure 21.12 Burst ROM Access Timing: Three-State Access tBRQS tBRQS BREQ tBACD2 tBACD1 BACK A23 to A0, AS, RD, HWR, LWR tBZD tBZD Figure 21.13 Bus-Release Mode Timing Rev. 3.00 Sep 14, 2005 page 699 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics 21.2.4 DRAM Interface Bus Timing DRAM interface bus timing is shown as follows: * DRAM bus timing: read and write access Figure 21.14 shows the timing of the read and write access. * DRAM bus timing: CAS before RAS refresh Figure 21.15 shows the timing of the CAS before RAS refresh. * DRAM bus timing: self-refresh Figure 21.16 shows the timing of the self-refresh. Rev. 3.00 Sep 14, 2005 page 700 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics Tp Tr TC1 TC2 tAD tAD tAD A23 to A0 tAS1 tRAH tRAD2 tRP CS5 to CS2 (RAS5 to RAS2) tRAD1 tCASD2 tASD tCAS1 UCAS, LCAS (read) tCP RD (WE) (read) High tRAC tRDS tRDH* tAA D15 to D0 (read) tCAC tCASD2 tCASD1 tCAS2 UCAS, LCAS (write) tCP tASD tWCD RD (WE) (write) tWCS tWDD tWCH tWDS tWDH D15 to D0 (write) RFSH High Note: * Specification from the earliest negation timing of RAS and CAS. Figure 21.14 DRAM Bus Timing (Read/Write) Rev. 3.00 Sep 14, 2005 page 701 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics TRp TR1 TR2 tRAD1 tRAD2 tRP CS5 to CS2 (RAS5 to RAS2) tRAS tCASD1 tCASD2 tCSR1 tCHR tCAS3 UCAS, LCAS RD (WE) (high) tRAD2 tRAD1 tCSR1 tCHR tRAS RFSH Figure 21.15 DRAM Bus Timing (CAS Before RAS Refresh) Rev. 3.00 Sep 14, 2005 page 702 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics tCSR2 CS5 to CS2 (RAS5 to RAS2) UCAS, LCAS RD (WE) (high) tCSR2 RFSH Figure 21.16 DRAM Bus Timing (Self-Refresh) 21.2.5 TPC and I/O Port Timing Figure 21.17 shows the TPC and I/O port input/output timing. T1 T2 T3 tPRS tPRH Port 1 to B (read) tPWD Port 1 to 6, 8 to B (write) Figure 21.17 TPC and I/O Port Input/Output Timing Rev. 3.00 Sep 14, 2005 page 703 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics 21.2.6 Timer Input/Output Timing 16-bit timer and 8-bit timer timing is shown below. * Timer input/output timing Figure 21.18 shows the timer input/output timing. * Timer external clock input timing Figure 21.19 shows the timer external clock input timing. tTOCD Output compare*1 tTICS Input capture*2 Notes: 1. TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TMO0, TMO2, TMIO1, TMIO3 2. TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TMIO1, TMIO3 Figure 21.18 Timer Input/Output Timing tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 21.19 Timer External Clock Input Timing Rev. 3.00 Sep 14, 2005 page 704 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics 21.2.7 SCI Input/Output Timing SCI timing is shown as follows: * SCI input clock timing Figure 21.20 shows the SCI input clock timing. * SCI input/output timing (synchronous mode) Figure 21.21 shows the SCI input/output timing in synchronous mode. tSCKW tSCKr tSCKf SCK0, SCK1 tScyc Figure 21.20 SCI Input Clock Timing tScyc SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) tRXS tRXH RxD0, RxD1 (receive data) Figure 21.21 SCI Input/Output Timing in Synchronous Mode Rev. 3.00 Sep 14, 2005 page 705 of 910 REJ09B0258-0300 Section 21 Electrical Characteristics 21.2.8 DMAC Timing DMAC timing is shown as follows. * DMAC TEND output timing for 2 state access Figure 21.22 shows the DMAC TEND output timing for 2 state access. * DMAC TEND output timing for 3 state access Figure 21.23 shows the DMAC TEND output timing for 3 state access. * DMAC DREQ input timing Figure 21.24 shows DMAC DREQ input timing. T1 T2 tTED1 tTED2 TEND Figure 21.22 DMAC TEND Output Timing for 2 State Access T1 T2 T3 tTED2 tTED1 TEND Figure 21.23 DMAC TEND Output Timing for 3 State Access tDRQS tDRQH DREQ Figure 21.24 DMAC DREQ Input Timing Rev. 3.00 Sep 14, 2005 page 706 of 910 REJ09B0258-0300 Appendix A Instruction Set Appendix A Instruction Set A.1 Instruction List Operand Notation Symbol Description Rd General destination register Rs General source register Rn General register ERd General destination register (address register or 32-bit register) ERs General source register (address register or 32-bit register) ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand PC Program counter SP Stack pointer CCR Condition code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR disp Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + Addition of the operands on both sides - Subtraction of the operand on the right from the operand on the left x Multiplication of the operands on both sides / Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Exclusive logical OR of the operands on both sides NOT (logical complement) ( ), < > Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Rev. 3.00 Sep 14, 2005 page 707 of 910 REJ09B0258-0300 Appendix A Instruction Set Condition Code Notation Symbol Description Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 -- Not affected by execution of the instruction Varies depending on conditions, described in notes Rev. 3.00 Sep 14, 2005 page 708 of 910 REJ09B0258-0300 Appendix A Instruction Set Table A.1 Instruction Set 1. Data transfer instructions 4 Rs8 @(d:16, ERd) -- -- 8 Rs8 @(d:24, ERd) -- -- ERd32-1 ERd32 Rs8 @ERd -- -- 2 Rs8 @aa:8 -- -- 4 Rs8 @aa:16 -- -- 6 Rs8 @aa:24 -- -- #xx:16 Rd16 -- -- Rs16 Rd16 -- -- @ERs Rd16 -- -- -- -- -- -- Rs8 @ERd @aa:24 Rd8 6 -- -- -- -- @aa:16 Rd8 @aa:8 Rd8 4 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- MOV.W @(d:16, ERs), Rd W 4 @(d:16, ERs) Rd16 -- -- MOV.W @(d:24, ERs), Rd W 8 @(d:24, ERs) Rd16 -- -- 0 -- MOV.W @ERs+, Rd W @ERs Rd16 ERs32+2 @ERd32 -- -- 0 -- @aa:16 Rd16 -- -- 0 -- MOV.B Rs, @aa:24 B MOV.W #xx:16, Rd W 4 MOV.W Rs, Rd W MOV.W @ERs, Rd W MOV.W @aa:16, Rd W 2 2 2 2 2 2 2 2 4 Advanced Normal B 2 0 -- B MOV.B Rs, @aa:16 -- -- MOV.B Rs, @aa:8 @ERs Rd8 ERs32+1 ERs32 0 -- B -- -- MOV.B Rs, @-ERd @(d:24, ERs) Rd8 B 8 MOV.B Rs, @(d:24, ERd) -- -- B @(d:16, ERs) Rd8 MOV.B Rs, @(d:16, ERd) 4 B -- -- B MOV.B Rs, @ERd @ERs Rd8 0 -- MOV.B @aa:24, Rd -- -- B -- -- Rs8 Rd8 C B MOV.B @aa:16, Rd #xx:8 Rd8 V MOV.B @aa:8, Rd Z B H N MOV.B @ERs+, Rd I B Condition Code Operation MOV.B @(d:24, ERs), Rd No. of States*1 -- B @@aa MOV.B @(d:16, ERs), Rd @(d, PC) B @aa MOV.B @ERs, Rd @-ERn/@ERn+ 2 B @(d, ERn) B MOV.B Rs, Rd @ERn #xx MOV.B #xx:8, Rd Rn Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 2 0 -- 2 0 -- 4 0 -- 6 10 6 4 6 0 -- 8 0 -- 4 0 -- 6 10 6 4 6 0 -- 8 0 -- 4 0 -- 2 4 0 -- 6 10 6 6 Rev. 3.00 Sep 14, 2005 page 709 of 910 REJ09B0258-0300 Appendix A Instruction Set Operation 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- POP.W Rn W 2 @SP Rn16 SP+2 SP -- -- 0 -- POP.L ERn L 4 @SP ERn32 SP+4 SP -- -- 0 -- Rs16 @ERd -- -- MOV.W Rs, @(d:16, W ERd) 4 Rs16 @(d:16, ERd) -- -- MOV.W Rs, @(d:24, W ERd) 8 Rs16 @(d:24, ERd) -- -- ERd32-2 ERd32 Rs16 @ERd -- -- MOV.W Rs, @ERd W MOV.W Rs, @-ERd W MOV.W Rs, @aa:16 W MOV.W Rs, @aa:24 W MOV.L #xx:32, Rd L MOV.L ERs, ERd L MOV.L @ERs, ERd L 2 2 4 Rs16 @aa:16 -- -- 6 Rs16 @aa:24 -- -- #xx:32 Rd32 -- -- ERs32 ERd32 -- -- @ERs ERd32 -- -- 6 2 4 MOV.L @(d:16, ERs), L ERd 6 @(d:16, ERs) ERd32 -- -- MOV.L @(d:24, ERs), L ERd 10 @(d:24, ERs) ERd32 -- -- MOV.L @ERs+, ERd L 4 @ERs ERd32 ERs32+4 ERs32 -- -- MOV.L @aa:16, ERd L 6 @aa:16 ERd32 -- -- MOV.L @aa:24, ERd L 8 @aa:24 ERd32 -- -- ERs32 @ERd -- -- MOV.L ERs, @ERd L 4 MOV.L ERs, @(d:16, L ERd) 6 ERs32 @(d:16, ERd) -- -- MOV.L ERs, @(d:24, L ERd) 10 ERs32 @(d:24, ERd) -- -- MOV.L ERs, @-ERd L MOV.L ERs, @aa:16 L MOV.L ERs, @aa:24 L ERd32-4 ERd32 ERs32 @ERd 4 -- -- 6 ERs32 @aa:16 -- -- 8 ERs32 @aa:24 -- -- Rev. 3.00 Sep 14, 2005 page 710 of 910 REJ09B0258-0300 6 0 -- C V Z I H N -- -- @aa:24 Rd16 0 -- MOV.W @aa:24, Rd W Normal Condition Code Advanced No. of States*1 -- @@aa @(d, PC) @aa @-ERn/@ERn+ @(d, ERn) @ERn Rn #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 8 0 -- 4 6 10 6 6 8 6 2 8 10 14 10 10 0 -- 12 0 -- 8 10 14 10 10 12 6 10 Appendix A Instruction Set -- -- MOVFPE @aa:16, Rd B 4 Cannot be used in the H8/3068F Cannot be used in the H8/3068F MOVTPE Rs, @aa:16 B 4 Cannot be used in the H8/3068F Cannot be used in the H8/3068F Z V C H N 0 -- 6 I -- Operation Normal 4 SP-4 SP ERn32 @SP @@aa L @(d, PC) PUSH.L ERn @aa -- -- @(d, ERn) 2 SP-2 SP Rn16 @SP @ERn W Rn PUSH.W Rn #xx Mnemonic Condition Code Advanced No. of States*1 Operand Size @-ERn/@ERn+ Addressing Mode and Instruction Length (bytes) 0 -- 10 Rev. 3.00 Sep 14, 2005 page 711 of 910 REJ09B0258-0300 Appendix A Instruction Set 2. Arithmetic instructions H N 2 (3) 2 (3) 2 -- -- -- -- -- -- 2 B ADD.W #xx:16, Rd W 4 ADD.W Rs, Rd W ADD.L #xx:32, ERd L ADD.L ERs, ERd L ADDX.B #xx:8, Rd B ADDX.B Rs, Rd B 2 Rd8+Rs8 +C Rd8 -- ADDS.L #1, ERd L 2 ERd32+1 ERd32 ADDS.L #2, ERd L 2 ERd32+2 ERd32 -- -- -- -- -- -- 2 ADDS.L #4, ERd L 2 ERd32+4 ERd32 INC.B Rd B 2 Rd8+1 Rd8 -- -- INC.W #1, Rd W 2 Rd16+1 Rd16 -- -- 6 ADD.B Rs, Rd INC.W #2, Rd W 2 Rd16+2 Rd16 -- -- -- Rd8+#xx:8 +C Rd8 -- (2) 2 ERd32+ERs32 ERd32 -- (2) -- (1) ERd32+#xx:32 ERd32 Rd16+Rs16 Rd16 2 -- (1) C -- Rd16+#xx:16 Rd16 V Rd8+Rs8 Rd8 Z -- I Rd8+#xx:8 Rd8 Operation Normal Condition Code Advanced No. of States*1 -- @@aa @(d, PC) @aa @-ERn/@ERn+ 2 @(d, ERn) B @ERn #xx ADD.B #xx:8, Rd Rn Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) Rev. 3.00 Sep 14, 2005 page 712 of 910 REJ09B0258-0300 -- -- -- -- -- -- 2 -- 2 -- 2 2 2 2 6 4 2 -- 2 2 Appendix A Instruction Set B 2 Rd8 decimal adjust Rd8 -- * SUB.B Rs, Rd B 2 Rd8-Rs8 Rd8 -- 2 SUB.W #xx:16, Rd W 4 Rd16-#xx:16 Rd16 -- (1) SUB.W Rs, Rd W Rd16-Rs16 Rd16 -- (1) 4 SUB.L #xx:32, ERd L ERd32-#xx:32 ERd32 -- (2) 6 SUB.L ERs, ERd L ERd32-ERs32 ERd32 -- (2) 2 SUBX.B #xx:8, Rd B Rd8-#xx:8-C Rd8 -- 2 Rd8-Rs8-C Rd8 -- 2 B (3) SUBX.B Rs, Rd SUBS.L #1, ERd L 2 ERd32-1 ERd32 -- -- -- -- -- -- 2 SUBS.L #2, ERd L 2 ERd32-2 ERd32 -- -- -- -- -- -- 2 SUBS.L #4, ERd L 2 ERd32-4 ERd32 -- -- -- -- -- -- 2 DEC.B Rd B 2 Rd8-1 Rd8 -- -- DEC.W #1, Rd W 2 Rd16-1 Rd16 -- -- DEC.W #2, Rd W 2 Rd16-2 Rd16 -- -- DEC.L #1, ERd L 2 ERd32-1 ERd32 -- -- DEC.L #2, ERd L 2 ERd32-2 ERd32 -- -- DAS.Rd B 2 Rd8 decimal adjust Rd8 -- * MULXU. B Rs, Rd B MULXU. W Rs, ERd 2 6 2 Normal C -- 2 -- 2 * -- 2 2 2 -- 2 -- 2 -- 2 -- 2 -- 2 * -- 2 2 Rd8 x Rs8 Rd16 -- -- -- -- -- -- (unsigned multiplication) 14 W 2 Rd16 x Rs16 ERd32 -- -- -- -- -- -- (unsigned multiplication) 22 MULXS. B Rs, Rd B 4 Rd8 x Rs8 Rd16 (signed multiplication) -- -- (3) V Z -- -- 16 MULXS. W Rs, ERd W 4 Rd16 x Rs16 ERd32 (signed multiplication) -- -- H N -- I 2 Condition Code Operation Advanced DAA Rd @@aa -- -- @(d, PC) -- -- ERd32+2 ERd32 @aa ERd32+1 ERd32 2 @(d, ERn) 2 L @ERn L INC.L #2, ERd Rn INC.L #1, ERd #xx Mnemonic No. of States*1 Operand Size @-ERn/@ERn+ Addressing Mode and Instruction Length (bytes) -- -- 24 DIVXU. B Rs, Rd B 2 Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division) -- -- (6) (7) -- -- 14 Rev. 3.00 Sep 14, 2005 page 713 of 910 REJ09B0258-0300 Appendix A Instruction Set No. of States*1 4 Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division) -- -- (8) (7) -- -- 16 DIVXS. W Rs, ERd W 4 ERd32 / Rs16 ERd32 -- -- (8) (7) -- -- (Ed: remainder, Rd: quotient) (signed division) 24 CMP.B #xx:8, Rd B 2 0-Rd8 Rd8 -- W 2 0-Rd16 Rd16 -- NEG.L ERd L 2 0-ERd32 ERd32 -- EXTU.W Rd W 2 0 (<bits 15 to 8> of Rd16) -- -- 0 EXTU.L ERd L 2 0 (<bits 31 to 16> of ERd32) -- -- 0 EXTS.W Rd W 2 (<bit 7> of Rd16) -- -- (<bits 15 to 8> of Rd16) EXTS.L ERd L 2 (<bit 15> of ERd32) (<bits 31 to 16> of ERd32) Normal B NEG.W Rd NEG.B Rd -- (2) ERd32-ERs32 -- -- 2 2 -- (2) 6 L -- (1) ERd32-#xx:32 CMP.L ERs, ERd Rd16-Rs16 2 2 L -- (1) 0 -- 2 W CMP.L #xx:32, ERd Rev. 3.00 Sep 14, 2005 page 714 of 910 REJ09B0258-0300 -- Rd16-#xx:16 2 0 -- 2 CMP.W Rs, Rd 2 Rd8-Rs8 C 0 -- 2 B W 4 6 -- V CMP.W #xx:16, Rd 2 Rd8-#xx:8 Z CMP.B Rs, Rd 2 H N I Operation -- Condition Code Advanced B @@aa DIVXS. B Rs, Rd @(d, PC) 22 @aa ERd32 / Rs16 ERd32 -- -- (6) (7) -- -- (Ed: remainder, Rd: quotient) (unsigned division) @(d, ERn) 2 @ERn W Rn DIVXU. W Rs, ERd #xx Mnemonic Operand Size @-ERn/@ERn+ Addressing Mode and Instruction Length (bytes) 0 -- 2 4 2 2 2 Appendix A Instruction Set 3. Logic instructions 2 W XOR.L #xx:32, ERd L 2 ERd32ERs32 ERd32 -- -- Rd8#xx:8 Rd8 -- -- Rd8Rs8 Rd8 -- -- Rd16#xx:16 Rd16 -- -- Rd16Rs16 Rd16 -- -- XOR.L ERs, ERd L 4 ERd32ERs32 ERd32 -- -- NOT.B Rd B 2 Rd8 Rd8 NOT.W Rd W 2 Rd16 Rd16 -- -- NOT.L ERd L 2 Rd32 Rd32 -- -- -- -- 0 -- 0 -- 0 -- 0 -- 0 -- Advanced Normal -- @@aa @(d, PC) @aa ERd32#xx:32 ERd32 -- -- 6 XOR.W Rs, Rd -- -- B W 4 Rd16Rs16 Rd16 4 2 XOR.W #xx:16, Rd -- -- ERd32#xx:32 ERd32 -- -- 6 XOR.B Rs, Rd -- -- Rd16#xx:16 Rd16 B 2 Rd8Rs8 Rd8 L XOR.B #xx:8, Rd 2 -- -- L OR.L ERs, ERd Rd8#xx:8 Rd8 W OR.L #xx:32, ERd ERd32ERs32 ERd32 -- -- OR.W Rs, Rd -- -- 0 -- B W 4 Rd16Rs16 Rd16 C 0 -- 4 2 OR.W #xx:16, Rd -- -- -- -- ERd32#xx:32 ERd32 -- -- 6 OR.B Rs, Rd Rd8Rs8 Rd8 Rd16#xx:16 Rd16 V B Z L OR.B #xx:8, Rd 2 I L AND.L ERs, ERd 2 H N -- -- W AND.L #xx:32, ERd Rd8#xx:8 Rd8 AND.W Rs, Rd Operation W 4 Condition Code B AND.W #xx:16, Rd No. of States*1 AND.B Rs, Rd @-ERn/@ERn+ 2 @(d, ERn) B @ERn #xx AND.B #xx:8, Rd Rn Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 2 0 -- 2 4 0 -- 2 0 -- 6 0 -- 4 0 -- 2 0 -- 2 0 -- 4 0 -- 2 0 -- 6 4 2 0 -- 2 4 0 -- 2 0 -- 6 0 -- 4 2 0 -- 2 2 Rev. 3.00 Sep 14, 2005 page 715 of 910 REJ09B0258-0300 Appendix A Instruction Set 4. Shift instructions B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.L ERd L 2 Rev. 3.00 Sep 14, 2005 page 716 of 910 REJ09B0258-0300 LSB -- -- -- -- -- -- C -- -- MSB LSB -- -- -- -- C MSB LSB -- -- -- -- ROTL.B Rd MSB 2 2 L W ROTXR.L ERd -- -- ROTXR.W Rd C -- -- 2 LSB 2 B MSB L ROTXR.B Rd -- -- 2 2 ROTXL.L ERd C 2 2 2 2 2 W -- -- 2 2 ROTXL.W Rd -- -- 2 2 2 LSB -- -- 2 B MSB -- -- 2 L ROTXL.B Rd C SHLR.L ERd 0 2 -- -- 2 W -- -- B SHLR.W Rd LSB SHLR.B Rd MSB 2 2 L 0 W SHLL.L ERd 0 -- -- SHLL.W Rd C -- -- 0 2 2 B LSB 0 0 L SHLL.B Rd MSB -- -- SHAR.L ERd -- -- C 0 2 -- -- 2 W -- -- 0 B SHAR.W Rd LSB SHAR.B Rd MSB 0 2 C 2 L V 0 W SHAL.L ERd 0 Z SHAL.W Rd C H N 0 I -- -- Operation 2 0 Normal Condition Code Advanced No. of States*1 -- @@aa @(d, PC) @aa @-ERn/@ERn+ @(d, ERn) @ERn B Rn SHAL.B Rd #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 2 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 Appendix A Instruction Set 5. Bit manipulation instructions B BCLR Rn, Rd B BCLR Rn, @ERd B BCLR Rn, @aa:8 B BNOT #xx:3, Rd B BNOT #xx:3, @ERd B BNOT #xx:3, @aa:8 B BNOT Rn, Rd B BNOT Rn, @ERd B BNOT Rn, @aa:8 B BTST #xx:3, Rd B BTST #xx:3, @ERd B BTST #xx:3, @aa:8 B BTST Rn, Rd B BTST Rn, @ERd B BTST Rn, @aa:8 B BLD #xx:3, Rd B 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 V C Advanced BCLR #xx:3, @aa:8 2 Z Normal B H N 2 (#xx:3 of @ERd) 1 -- -- -- -- -- -- 8 (#xx:3 of @aa:8) 1 -- -- -- -- -- -- 8 (Rn8 of Rd8) 1 -- -- -- -- -- -- 2 (Rn8 of @ERd) 1 -- -- -- -- -- -- 8 (Rn8 of @aa:8) 1 -- -- -- -- -- -- 8 (#xx:3 of Rd8) 0 -- -- -- -- -- -- 2 (#xx:3 of @ERd) 0 -- -- -- -- -- -- 8 (#xx:3 of @aa:8) 0 -- -- -- -- -- -- 8 (Rn8 of Rd8) 0 -- -- -- -- -- -- 2 (Rn8 of @ERd) 0 -- -- -- -- -- -- 8 (Rn8 of @aa:8) 0 -- -- -- -- -- -- 8 (#xx:3 of Rd8) (#xx:3 of Rd8) -- -- -- -- -- -- 2 (#xx:3 of @ERd) (#xx:3 of @ERd) -- -- -- -- -- -- 8 (#xx:3 of @aa:8) (#xx:3 of @aa:8) -- -- -- -- -- -- 8 (Rn8 of Rd8) (Rn8 of Rd8) -- -- -- -- -- -- 2 (Rn8 of @ERd) (Rn8 of @ERd) -- -- -- -- -- -- 8 (Rn8 of @aa:8) (Rn8 of @aa:8) -- -- -- -- -- -- 8 (#xx:3 of Rd8) Z -- -- -- (#xx:3 of @ERd) Z -- -- -- (#xx:3 of @aa:8) Z -- -- -- (Rn8 of @Rd8) Z -- -- -- (Rn8 of @ERd) Z -- -- -- (Rn8 of @aa:8) Z -- -- -- (#xx:3 of Rd8) C -- -- -- -- -- -- -- 2 -- -- 6 -- -- 6 -- -- 2 -- -- 6 -- -- 6 B BCLR #xx:3, @ERd 4 I -- -- -- -- -- -- BCLR #xx:3, Rd 4 Operation (#xx:3 of Rd8) 1 B Condition Code B BSET Rn, @aa:8 4 2 No. of States*1 -- BSET Rn, @ERd 4 @@aa B 2 @(d, PC) B BSET Rn, Rd @aa BSET #xx:3, @aa:8 @-ERn/@ERn+ B @(d, ERn) BSET #xx:3, @ERd @ERn B Rn BSET #xx:3, Rd #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 2 Rev. 3.00 Sep 14, 2005 page 717 of 910 REJ09B0258-0300 Appendix A Instruction Set B BIAND #xx:3, @ERd B 4 2 BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR #xx:3, Rd B BXOR #xx:3, @ERd B BXOR #xx:3, @aa:8 B BIXOR #xx:3, Rd B BIXOR #xx:3, @ERd B BIXOR #xx:3, @aa:8 B (#xx:3 of @ERd) C -- -- -- -- -- 6 (#xx:3 of @aa:8) C -- -- -- -- -- 6 C (#xx:3 of Rd8) -- -- -- -- -- -- 2 C (#xx:3 of @ERd24) -- -- -- -- -- -- 8 C (#xx:3 of @aa:8) -- -- -- -- -- -- 8 C (#xx:3 of Rd8) -- -- -- -- -- -- 2 C (#xx:3 of @ERd24) -- -- -- -- -- -- 8 C (#xx:3 of @aa:8) -- -- -- -- -- -- 8 C(#xx:3 of Rd8) C -- -- -- -- -- C(#xx:3 of @ERd24) C -- -- -- -- -- C(#xx:3 of @aa:8) C -- -- -- -- -- C (#xx:3 of Rd8) C -- -- -- -- -- 4 2 4 4 2 4 4 2 4 4 2 4 4 Rev. 3.00 Sep 14, 2005 page 718 of 910 REJ09B0258-0300 2 2 6 6 6 2 6 C (#xx:3 of @aa:8) C -- -- -- -- -- C(#xx:3 of Rd8) C -- -- -- -- -- C(#xx:3 of @ERd24) C -- -- -- -- -- 6 C(#xx:3 of @aa:8) C -- -- -- -- -- C (#xx:3 of Rd8) C -- -- -- -- -- 2 C (#xx:3 of @ERd24) C -- -- -- -- -- 6 C (#xx:3 of @aa:8) C -- -- -- -- -- C (#xx:3 of @ERd24) C -- -- -- -- -- 4 Advanced BIAND #xx:3, Rd 4 Normal B B BAND #xx:3, @aa:8 BAND #xx:3, @ERd 4 2 6 -- -- -- -- -- B -- -- -- -- -- (#xx:3 of Rd8) C B BAND #xx:3, Rd (#xx:3 of @aa:8) C BIST #xx:3, @aa:8 4 6 B Z BIST #xx:3, @ERd 4 2 H N B I B BIST #xx:3, Rd 4 C -- -- -- -- -- BST #xx:3, @aa:8 2 V (#xx:3 of @ERd) C B Operation B BST #xx:3, @ERd 4 Condition Code BST #xx:3, Rd 4 No. of States*1 -- B 4 2 @@aa B BILD #xx:3, @aa:8 4 @(d, PC) BILD #xx:3, @ERd @aa B @-ERn/@ERn+ B BILD #xx:3, Rd @(d, ERn) BLD #xx:3, @aa:8 @ERn B Rn BLD #xx:3, @ERd #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) C (#xx:3 of @aa:8) C -- -- -- -- -- C(#xx:3 of Rd8) C -- -- -- -- -- C(#xx:3 of @ERd24) C -- -- -- -- -- C(#xx:3 of @aa:8) C -- -- -- -- -- C (#xx:3 of Rd8) C -- -- -- -- -- C (#xx:3 of @ERd24) C -- -- -- -- -- 6 2 6 2 6 6 2 6 6 Appendix A Instruction Set 6. Branching instructions -- 2 BHI d:16 -- 4 BLS d:8 -- 2 BLS d:16 -- 4 BCC d:8 (BHS d:8) -- 2 BCC d:16 (BHS d:16) -- 4 BCS d:8 (BLO d:8) -- 2 BCS d:16 (BLO d:16) -- 4 BNE d:8 -- 2 BNE d:16 -- 4 BEQ d:8 -- 2 BEQ d:16 -- 4 BVC d:8 -- 2 BVC d:16 -- 4 BVS d:8 -- 2 BVS d:16 -- 4 BPL d:8 -- 2 BPL d:16 -- 4 BMI d:8 -- 2 BMI d:16 -- 4 BGE d:8 -- 2 BGE d:16 -- 4 BLT d:8 -- 2 BLT d:16 -- 4 BGT d:8 -- 2 BGT d:16 -- 4 If condition Always is true then PC PC+d else Never next; CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) =0 Condition Code I H N Z V C Advanced BHI d:8 Branch Operation Condition Normal 4 No. of States*1 -- 2 -- @@aa -- BRN d:16 (BF d:16) @(d, PC) BRN d:8 (BF d:8) @aa 4 @(d, ERn) 2 -- @ERn -- BRA d:16 (BT d:16) Rn BRA d:8 (BT d:8) #xx Mnemonic Operand Size @-ERn/@ERn+ Addressing Mode and Instruction Length (bytes) -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 Rev. 3.00 Sep 14, 2005 page 719 of 910 REJ09B0258-0300 Appendix A Instruction Set -- JMP @@aa:8 -- BSR d:8 -- BSR d:16 -- JSR @ERn -- JSR @aa:24 -- JSR @@aa:8 -- RTS -- Condition Code I H N Z V C Advanced JMP @aa:24 Branch Operation Condition Normal -- No. of States*1 -- JMP @ERn @@aa 4 @(d, PC) -- @aa BLE d:16 @(d, ERn) 2 @ERn -- Rn BLE d:8 #xx Mnemonic Operand Size @-ERn/@ERn+ Addressing Mode and Instruction Length (bytes) If condition Z (NV) = 1 -- -- -- -- -- -- is true then -- -- -- -- -- -- PC PC+d else next; 4 6 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- PC aa:24 -- -- -- -- -- -- PC @aa:8 2 PC @-SP PC PC+d:8 4 2 2 4 Rev. 3.00 Sep 14, 2005 page 720 of 910 REJ09B0258-0300 PC ERn 2 4 6 -- -- -- -- -- -- 8 10 -- -- -- -- -- -- 6 8 PC @-SP PC PC+d:16 -- -- -- -- -- -- 8 10 PC @-SP PC @ERn -- -- -- -- -- -- 6 8 PC @-SP PC @aa:24 -- -- -- -- -- -- 8 10 PC @-SP PC @aa:8 -- -- -- -- -- -- 8 12 8 10 2 PC @SP+ Appendix A Instruction Set 7. System control instructions -- Transition to powerdown state -- -- -- -- -- -- 2 LDC #xx:8, CCR B #xx:8 CCR B LDC @ERs, CCR W LDC @(d:16, ERs), CCR W 6 @(d:16, ERs) CCR 2 LDC Rs, CCR LDC @(d:24, ERs), CCR W 10 @(d:24, ERs) CCR 12 LDC @ERs+, CCR W @ERs CCR ERs32+2 ERs32 8 LDC @aa:16, CCR W 6 @aa:16 CCR LDC @aa:24, CCR W 8 @aa:24 CCR 8 10 STC CCR, Rd B CCR Rd8 -- -- -- -- -- -- 2 6 2 Rs8 CCR 2 @ERs CCR 4 4 Z V C Normal H N 2 6 8 STC CCR, @ERd W CCR @ERd -- -- -- -- -- -- STC CCR, @(d:16, ERd) W 6 CCR @(d:16, ERd) -- -- -- -- -- -- 8 STC CCR, @(d:24, ERd) W 10 CCR @(d:24, ERd) -- -- -- -- -- -- 12 STC CCR, @-ERd W ERd32-2 ERd32 CCR @ERd -- -- -- -- -- -- 8 STC CCR, @aa:16 W 6 CCR @aa:16 -- -- -- -- -- -- 8 8 10 2 I 1 -- -- -- -- -- 14 16 Operation -- Condition Code Advanced SLEEP @@aa 10 @(d, PC) CCR @SP+ PC @SP+ @aa -- @(d, ERn) RTE @ERn 2 PC @-SP CCR @-SP <vector> PC Rn -- #xx Mnemonic TRAPA #x:2 No. of States*1 Operand Size @-ERn/@ERn+ Addressing Mode and Instruction Length (bytes) 2 -- -- -- -- -- -- 2 4 CCR#xx:8 CCR ORC #xx:8, CCR B 2 CCR#xx:8 CCR XORC #xx:8, CCR B 2 CCR#xx:8 CCR NOP -- 2 PC PC+2 2 CCR @aa:24 B W ANDC #xx:8, CCR STC CCR, @aa:24 -- -- -- -- -- -- 4 2 2 Rev. 3.00 Sep 14, 2005 page 721 of 910 REJ09B0258-0300 Appendix A Instruction Set 8. Block transfer instructions Operation I H N Z V C -- -- -- -- -- -- Normal -- @@aa 4 if R4 0 repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next; @(d, PC) -- @aa EEPMOV. W @(d, ERn) -- -- -- -- -- -- 8+ 4 if R4L 0 repeat @R5 @R6 4n*2 R5+1 R5 R6+1 R6 R4L-1 R4L until R4L=0 else next; @ERn -- Rn EEPMOV. B #xx Mnemonic Condition Code Advanced No. of States*1 Operand Size @-ERn/@ERn+ Addressing Mode and Instruction Length (bytes) 8+ 4n*2 Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. For other cases see section A.3, Number of States Required for Execution. 2. n is the value set in register R4L or R4. (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) Retains its previous value when the result is zero; otherwise cleared to 0. (4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0. Rev. 3.00 Sep 14, 2005 page 722 of 910 REJ09B0258-0300 MULXU 5 STC Table A.2 (2) LDC 3 SUBX OR XOR AND MOV C D E F BILD BIST BLD BST TRAPA BNQ B BIAND BAND AND RTE BNE CMP BIXOR BXOR XOR BSR BCS A BIOR BOR OR RTS BCC MOV.B Table A.2 (2) LDC 7 ADDX BTST DIVXU BLS AND.B ANDC 6 9 BCLR MULXU BHI XOR.B XORC 5 ADD BNOT DIVXU BRN OR.B ORC 4 8 7 BSET BRA 6 2 1 Table A.2 Table A.2 Table A.2 Table A.2 (2) (2) (2) (2) NOP 4 3 2 1 0 0 MOV BVS 9 B JMP BPL BMI MOV Table A.2 Table A.2 (2) (2) Table A.2 Table A.2 (2) (2) A Table A.2 Table A.2 EEPMOV (2) (2) SUB ADD Table A.2 (2) BVC 8 BSR BGE C CMP MOV Instruction when most significant bit of BH is 1. Instruction when most significant bit of BH is 0. E JSR BGT SUBX ADDX Table A.2 (3) BLT D BLE Table A.2 (2) Table A.2 (2) F Table A.2 AL 1st byte 2nd byte AH AL BH BL A.2 AH Instruction code: Appendix A Instruction Set Operation Code Maps Operation Code Map (1) Rev. 3.00 Sep 14, 2005 page 723 of 910 REJ09B0258-0300 Rev. 3.00 Sep 14, 2005 page 724 of 910 REJ09B0258-0300 SUBS DAS BRA MOV MOV 1B 1F 58 79 7A 1 ADD ADD BRN NOT 17 DEC ROTXR 13 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 CMP CMP BHI 2 SUB SUB BLS NOT ROTXR ROTXL SHLR SHLL 3 4 OR OR BCC LDC/STC 1st byte 2nd byte AH AL BH BL XOR XOR BCS DEC EXTU INC 5 AND AND BNE 6 BEQ DEC EXTU INC 7 BVC SUBS NEG 9 BVS ROTR ROTL SHAR SHAL ADDS SLEEP 8 BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Table A.2 Table A.2 (3) (3) ADD SHAL B BGT E BLE DEC EXTS INC Table A.2 (3) F Table A.2 BH AH AL Instruction code: Appendix A Instruction Set Operation Code Map (2) DIVXS 3 BSET 7Faa7 *2 BNOT BNOT BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field. BSET 7Faa6 *2 BTST BCLR 7Eaa7 *2 BNOT BTST BSET 7Eaa6 *2 7Dr07 *1 7Dr06 *1 BTST BCLR MULXS 2 7Cr07 *1 BNOT DIVIXS 1 BTST BSET MULXS 0 7Cr06 *1 01F06 01D05 01C05 01406 CL BIOR BOR BIOR BOR OR 4 BIXOR BXOR BIXOR BXOR XOR 5 BIAND BAND BIAND BAND AND 6 7 BIST BILD BST BLD BIST BILD BST BLD 1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL 8 LDC STC 9 A LDC STC B C LDC STC D E LDC STC F Instruction when most significant bit of DH is 1. Instruction when most significant bit of DH is 0. Table A.2 AH ALBH BLCH Instruction code: Appendix A Instruction Set Operation Code Map (3) Rev. 3.00 Sep 14, 2005 page 725 of 910 REJ09B0258-0300 Appendix A Instruction Set A.3 Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states required per cycle according to the bus size. The number of states required for execution of an instruction can be calculated from these two tables as follows: Number of states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples of Calculation of Number of States Required for Execution Examples: Advanced mode, stack located in external address space, on-chip supporting modules accessed with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. BSET #0, @FFFFC7:8 From table A.4, I = L = 2 and J = K = M = N = 0 From table A.3, SI = 4 and SL = 3 Number of states = 2 x 4 + 2 x 3 = 14 JSR @@30 From table A.4, I = J = K = 2 and L = M = N = 0 From table A.3, SI = SJ = SK = 4 Number of states = 2 x 4 + 2 x 4 + 2 x 4 = 24 Rev. 3.00 Sep 14, 2005 page 726 of 910 REJ09B0258-0300 Appendix A Instruction Set Table A.3 Number of States per Cycle Access Conditions External Device On-Chip Supporting Module Execution State (Cycle) Instruction fetch On-Chip 8-Bit Memory Bus SI 2 6 8-Bit Bus 16-Bit Bus 16-Bit Bus 2-State Access 3-State Access 2-State Access 3-State Access 3 4 6 + 2m 2 3+m Branch address read SJ Stack operation SK Byte data access SL 3 2 3+m Word data access SM 6 4 6 + 2m Internal operation SN 1 Legend m: Number of wait states inserted into external device access Rev. 3.00 Sep 14, 2005 page 727 of 910 REJ09B0258-0300 Appendix A Instruction Set Table A.4 Number of Cycles per Instruction Instruction Mnemonic Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd 1 1 2 1 3 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd ADDX Rs, Rd 1 1 AND AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd 1 1 2 1 3 2 ANDC ANDC #xx:8, CCR 1 BAND BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 1 2 2 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Bcc Rev. 3.00 Sep 14, 2005 page 728 of 910 REJ09B0258-0300 1 1 Appendix A Instruction Set Instruction Mnemonic Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N Bcc BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 1 2 2 1 2 2 BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 1 2 2 1 1 BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 1 2 2 1 1 BIOR #xx:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 1 2 2 1 1 BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 1 2 2 2 2 BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 1 2 2 1 1 BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 1 2 2 1 1 BIAND BILD BIOR BIST BIXOR BLD 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 3.00 Sep 14, 2005 page 729 of 910 REJ09B0258-0300 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N Instruction Mnemonic BNOT BOR BSET BSR BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 1 2 2 1 2 2 BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 1 2 2 BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 1 2 2 1 2 2 BSR d:8 2 1 Advanced 2 2 Normal 2 1 2 Advanced 2 2 2 BSR d:16 BST Normal BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 1 2 2 BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 1 2 2 1 2 2 BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 1 2 2 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd 1 1 2 1 3 1 DAA DAA Rd 1 DAS DAS Rd 1 BTST BXOR Rev. 3.00 Sep 14, 2005 page 730 of 910 REJ09B0258-0300 2 2 2 2 1 1 2 2 2 2 2 2 1 1 1 1 1 1 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N Instruction Mnemonic DEC DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd 1 1 1 DIVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd 2 2 12 20 DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd 1 1 12 20 EEPMOV EEPMOV.B EEPMOV.W 2 2 EXTS EXTS.W Rd EXTS.L ERd 1 1 EXTU EXTU.W Rd EXTU.L ERd 1 1 INC INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd 1 1 1 JMP JMP @ERn 2 JMP @aa:24 2 JMP @@aa:8 Normal JSR JSR @ERn 2 2 1 2 Advanced 2 2 2 Normal 2 1 Advanced 2 2 JSR @aa:24 Normal 2 1 2 Advanced 2 2 2 JSR @@aa:8 Normal LDC 2n + 2*1 2n + 2*1 2 1 1 Advanced 2 2 2 LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR LDC @aa:16, CCR LDC @aa:24, CCR 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 Rev. 3.00 Sep 14, 2005 page 731 of 910 REJ09B0258-0300 Appendix A Instruction Set Instruction Mnemonic MOV Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16, ERs), Rd MOV.W @(d:24, ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16, ERd) MOV.W Rs, @(d:24, ERd) MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 3 1 2 3 5 2 3 4 2 3 5 2 3 4 Rev. 3.00 Sep 14, 2005 page 732 of 910 REJ09B0258-0300 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N Instruction Mnemonic MOVFPE 2 MOVFPE @aa:16, Rd* 2 1 2 MOVTPE MOVTPE Rs, @aa:16* 2 MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd 2 2 1 12 20 MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd 1 1 12 20 NEG NEG.B Rd NEG.W Rd NEG.L ERd 1 1 1 NOP NOP 1 NOT NOT.B Rd NOT.W Rd NOT.L ERd 1 1 1 OR OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd 1 1 2 1 3 2 ORC ORC #xx:8, CCR 1 POP POP.W Rn POP.L ERn 1 2 1 2 2 2 PUSH PUSH.W Rn PUSH.L ERn 1 2 1 2 2 2 ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd 1 1 1 ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd 1 1 1 ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd 1 1 1 ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd 1 1 1 RTE RTE 2 2 2 Rev. 3.00 Sep 14, 2005 page 733 of 910 REJ09B0258-0300 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N Instruction Mnemonic RTS RTS 2 1 2 Advanced 2 Normal 2 2 SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd 1 1 1 SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd 1 1 1 SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd 1 1 1 SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd 1 1 1 SLEEP SLEEP 1 STC STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd STC CCR, @aa:16 STC CCR, @aa:24 1 2 3 5 2 3 4 SUB SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd 1 2 1 3 1 SUBS SUBS #1/2/4, ERd 1 SUBX SUBX #xx:8, Rd SUBX Rs, Rd 1 1 TRAPA TRAPA #x:2 2 1 2 4 Advanced 2 2 2 4 Normal XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd 1 1 2 1 3 2 XORC XORC #xx:8, CCR 1 1 1 1 1 1 1 2 Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each. 2. Not available in the H8/3067 Group. Rev. 3.00 Sep 14, 2005 page 734 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Appendix B Internal I/O Registers B.1 Addresses (EMC = 1) Address (Low) Data Register Bus Width Bit 7 Name H'EE000 P1DDR 8 H'EE001 P2DDR 8 H'EE002 P3DDR H'EE003 P4DDR H'EE004 Bit Names Bit 1 Bit 0 Module Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2 8 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3 8 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4 P5DDR 8 -- -- P53DDR P52DDR P51DDR P50DDR Port 5 H'EE005 P6DDR 8 -- P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6 H'EE006 -- -- -- -- -- -- -- H'EE007 P8DDR 8 -- -- -- P84DDR P83DDR P82DDR P81DDR P80DDR Port 8 H'EE008 P9DDR 8 -- -- P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Port 9 H'EE009 PADDR 8 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Port A H'EE00A PBDDR 8 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Port B H'EE00B -- -- -- -- -- -- -- -- -- H'EE00C -- -- -- -- -- -- -- -- -- H'EE00D -- -- -- -- -- -- -- -- -- H'EE00E -- -- -- -- -- -- -- -- -- H'EE00F -- -- -- -- -- -- -- -- -- H'EE010 -- -- -- -- -- -- -- -- -- H'EE011 MDCR 8 -- -- -- -- -- MDS2 MDS1 MDS0 H'EE012 SYSCR 8 SSBY STS2 STS1 STS0 UE NMIEG SSOE RAME H'EE013 BRCR 8 A23E A22E A21E A20E -- -- -- BRLE Bus controller H'EE014 ISCR 8 -- -- IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC H'EE015 IER 8 -- -- IRQ5E IRQ2E IRQ1E IRQ0E Interrupt controller H'EE016 ISR 8 -- -- H'EE017 -- -- -- Bit 6 Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 -- IRQ4E IRQ3E IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F -- -- -- -- -- -- H'EE018 IPRA 8 IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 H'EE019 IPRB 8 IPRB7 IPRB6 IPRB5 -- IPRB3 IPRB2 IPRB1 -- H'EE01A DASTCR 8 -- -- -- -- -- -- -- DASTE H'EE01B DIVCR -- -- -- -- -- -- DIV1 DIV0 H'EE01C MSTCRH 8 PSTOP -- -- -- -- 8 System control D/A converter System MSTPH2 MSTPH1 MSTPH0 control H'EE01D MSTCRL 8 MSTPL7 -- MSTPL5 MSTPL4 MSTPL3 MSTPL2 -- MSTPL0 H'EE01E ADRCR 8 -- -- -- -- -- -- -- ADRCTL Bus controller H'EE01F CSCR 8 CS7E CS6E CS5E CS4E -- -- -- -- Rev. 3.00 Sep 14, 2005 page 735 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address (Low) Data Register Bus Width Bit 7 Name H'EE020 ABWCR 8 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 H'EE021 ASTCR 8 AST7 AST6 AST5 AST4 AST3 AST2 H'EE022 WCRH 8 W71 W70 W61 W60 W51 W50 W41 W40 H'EE023 WCRL 8 W31 W30 W21 W20 W11 W10 W01 W00 H'EE024 BCR 8 ICIS1 ICIS0 BROME BRSTS1 BRSTS0 -- RDEA WAITE -- Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 Module Name ABW1 ABW0 Bus controller AST1 AST0 Bit 1 H'EE025 -- -- -- -- -- -- -- -- H'EE026 DRCRA 8 DRAS2 DRAS1 DRAS0 -- BE RDM SRFMD RFSHE H'EE027 DRCRB 8 MXC1 MXC0 CSEL RCYCE -- TPC RCW RLW CMF CMIE CKS2 CKS1 CKS0 -- -- -- H'EE028 RTMCSR 8 H'EE029 RTCNT 8 H'EE02A RTCOR 8 H'EE02B Reserved area (access prohibited) DRAM Interface H'EE02C H'EE02D H'EE02E H'EE02F H'EE030 FLMCR1 8 FWE SWE ESU PSU EV PV E P H'EE031 FLMCR2 8 FLER -- -- -- -- -- -- -- H'EE032 EBR1 8 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 H'EE033 EBR2 8 -- -- EB13 EB12 EB11 EB10 EB9 EB8 H'EE034 Reserved area (access prohibited) P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P27PCR P20PCR -- Flash memory H'EE035 H'EE036 H'EE037 H'EE038 H'EE039 H'EE03A H'EE03B H'EE03C P2PCR 8 H'EE03D -- -- -- H'EE03E P4PCR 8 P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR Port 4 H'EE03F P5PCR 8 -- P51PCR P50PCR Port 5 -- -- -- -- Rev. 3.00 Sep 14, 2005 page 736 of 910 REJ09B0258-0300 -- -- -- -- P53PCR P52PCR Port 2 Appendix B Internal I/O Registers Address (Low) Data Register Bus Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'EE040 -- -- -- -- -- -- -- -- -- H'EE041 -- -- -- -- -- -- -- -- -- H'EE042 -- -- -- -- -- -- -- -- -- H'EE043 -- -- -- -- -- -- -- -- -- H'EE044 -- -- -- -- -- -- -- -- -- H'EE045 -- -- -- -- -- -- -- -- -- H'EE046 -- -- -- -- -- -- -- -- -- H'EE047 -- -- -- -- -- -- -- -- -- H'EE048 -- -- -- -- -- -- -- -- -- H'EE049 -- -- -- -- -- -- -- -- -- H'EE04A -- -- -- -- -- -- -- -- -- H'EE04B -- -- -- -- -- -- -- -- -- H'EE04C -- -- -- -- -- -- -- -- -- H'EE04D -- -- -- -- -- -- -- -- -- Bit Names H'EE04E -- -- -- -- -- -- -- -- -- H'EE04F -- -- -- -- -- -- -- -- -- H'EE050 -- -- -- -- -- -- -- -- -- H'EE051 -- -- -- -- -- -- -- -- -- H'EE052 -- -- -- -- -- -- -- -- -- H'EE053 -- -- -- -- -- -- -- -- -- H'EE054 -- -- -- -- -- -- -- -- -- H'EE055 -- -- -- -- -- -- -- -- -- H'EE056 -- -- -- -- -- -- -- -- -- H'EE057 -- -- -- -- -- -- -- -- -- H'EE058 -- -- -- -- -- -- -- -- -- H'EE059 -- -- -- -- -- -- -- -- -- H'EE05A -- -- -- -- -- -- -- -- -- H'EE05B -- -- -- -- -- -- -- -- -- H'EE05C -- -- -- -- -- -- -- -- -- H'EE05D -- -- -- -- -- -- -- -- -- H'EE05E -- -- -- -- -- -- -- -- -- H'EE05F -- -- -- -- -- -- -- -- -- Module Name Rev. 3.00 Sep 14, 2005 page 737 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address (Low) Data Register Bus Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'EE060 -- -- -- -- -- -- -- -- -- H'EE061 -- -- -- -- -- -- -- -- -- H'EE062 -- -- -- -- -- -- -- -- -- H'EE063 -- -- -- -- -- -- -- -- -- H'EE064 -- -- -- -- -- -- -- -- -- H'EE065 -- -- -- -- -- -- -- -- -- H'EE066 -- -- -- -- -- -- -- -- -- H'EE067 -- -- -- -- -- -- -- -- -- H'EE068 -- -- -- -- -- -- -- -- -- H'EE069 -- -- -- -- -- -- -- -- -- H'EE06A -- -- -- -- -- -- -- -- -- H'EE06B -- -- -- -- -- -- -- -- -- H'EE06C -- -- -- -- -- -- -- -- -- H'EE06D -- -- -- -- -- -- -- -- -- Bit Names H'EE06E -- -- -- -- -- -- -- -- -- H'EE06F -- -- -- -- -- -- -- -- -- H'EE070 -- -- -- -- -- -- -- -- -- H'EE071 -- -- -- -- -- -- -- -- -- H'EE072 -- -- -- -- -- -- -- -- -- H'EE073 -- -- -- -- -- -- -- -- -- H'EE074 Reserved area (access prohibited) -- -- RAMS RAM2 RAM1 RAM0 Module Name H'EE075 H'EE076 H'EE077 RAMCR *1 8 -- -- H'EE078 Reserved area (access prohibited) H'EE079 H'EE07A H'EE07B H'EE07C H'EE07D H'EE07E H'EE07F Rev. 3.00 Sep 14, 2005 page 738 of 910 REJ09B0258-0300 Flash memory*1 Appendix B Internal I/O Registers Data Bus Width Bit 7 Bit Names Address (Low) Register Name H'EE080 Reserved area (access prohibited) Flash memory*1 H'FFF20 MAR0AR 8 DMAC channel 0A H'FFF21 MAR0AE 8 H'FFF22 MAR0AH 8 H'FFF23 MAR0AL 8 H'FFF24 ETCR0AH 8 H'FFF25 ETCR0AL 8 H'FFF26 IOAR0A 8 H'FFF27 DTCR0A 8 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE081 H'FFF28 MAR0BR 8 H'FFF29 MAR0BE 8 H'FFF2A MAR0BH 8 H'FFF2B MAR0BL 8 H'FFF2C ETCR0BH 8 H'FFF2D ETCR0BL 8 H'FFF2E IOAR0B 8 H'FFF2F DTCR0B 8 H'FFF30 MAR1AR 8 H'FFF31 MAR1AE 8 H'FFF32 MAR1AH 8 H'FFF33 MAR1AL 8 H'FFF34 ETCR1AH 8 H'FFF35 ETCR1AL 8 H'FFF36 IOAR1A 8 H'FFF37 DTCR1A 8 H'FFF38 MAR1BR 8 H'FFF39 MAR1BE 8 H'FFF3A MAR1BH 8 H'FFF3B MAR1BL 8 H'FFF3C ETCR1BH 8 H'FFF3D ETCR1BL 8 H'FFF3E IOAR1B 8 H'FFF3F DTCR1B 8 DTE DTSZ DTID RPE DTIE DTS2 DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Full address mode DTS1 DTS0 Short address mode DMAC channel 0B DTE DTSZ DTID RPE DTME -- DAID DAIDE TMS DTIE DTS2 DTS1 DTS0 Short address mode DTS2B DTS1B DTS0B Full address mode DMAC channel 1A DTE DTSZ DTID RPE DTIE DTS2 DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Full address mode DTS1 DTS0 Short address mode DMAC channel 1B DTE DTSZ DTID RPE DTME -- DAID DAIDE TMS DTIE DTS2 DTS1 DTS0 Short address mode DTS2B DTS1B DTS0B Full address mode Rev. 3.00 Sep 14, 2005 page 739 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address (Low) Data Register Bus Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFF40 -- -- -- -- -- -- -- -- -- H'FFF41 -- -- -- -- -- -- -- -- -- H'FFF42 -- -- -- -- -- -- -- -- -- H'FFF43 -- -- -- -- -- -- -- -- -- H'FFF44 -- -- -- -- -- -- -- -- -- H'FFF45 -- -- -- -- -- -- -- -- -- H'FFF46 -- -- -- -- -- -- -- -- -- H'FFF47 -- -- -- -- -- -- -- -- -- H'FFF48 -- -- -- -- -- -- -- -- -- H'FFF49 -- -- -- -- -- -- -- -- -- H'FFF4A -- -- -- -- -- -- -- -- -- H'FFF4B -- -- -- -- -- -- -- -- -- H'FFF4C -- -- -- -- -- -- -- -- -- H'FFF4D -- -- -- -- -- -- -- -- -- H'FFF4E -- -- -- -- -- -- -- -- -- H'FFF4F -- -- -- -- -- -- -- -- -- H'FFF50 -- -- -- -- -- -- -- -- -- H'FFF51 -- -- -- -- -- -- -- -- -- H'FFF52 -- -- -- -- -- -- -- -- -- H'FFF53 -- -- -- -- -- -- -- -- -- H'FFF54 -- -- -- -- -- -- -- -- -- H'FFF55 -- -- -- -- -- -- -- -- -- H'FFF56 -- -- -- -- -- -- -- -- -- H'FFF57 -- -- -- -- -- -- -- -- -- H'FFF58 -- -- -- -- -- -- -- -- -- H'FFF59 -- -- -- -- -- -- -- -- -- H'FFF5A -- -- -- -- -- -- -- -- -- H'FFF5B -- -- -- -- -- -- -- -- -- H'FFF5C -- -- -- -- -- -- -- -- -- H'FFF5D -- -- -- -- -- -- -- -- -- H'FFF5E -- -- -- -- -- -- -- -- -- H'FFF5F -- -- -- -- -- -- -- -- -- Bit Names Rev. 3.00 Sep 14, 2005 page 740 of 910 REJ09B0258-0300 Module Name Appendix B Internal I/O Registers Address (Low) Data Register Bus Width Bit 7 Name Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFF60 TSTR 8 -- -- -- -- -- STR2 STR1 STR0 H'FFF61 TSNC 8 -- -- -- -- -- SYNC2 SYNC1 SYNC0 H'FFF62 TMDR 8 -- MDF FDIR -- -- PWM2 PWM1 PWM0 H'FFF63 TOLR 8 -- -- TOB2 TOA2 TOB1 TOA1 TOB0 TOA0 H'FFF64 TISRA 8 -- IMIEA2 IMIEA1 IMIEA0 -- IMFA2 IMFA1 IMFA0 H'FFF65 TISRB 8 -- IMIEB2 IMIEB1 IMIEB0 -- IMFB2 IMFB1 IMFB0 H'FFF66 TISRC 8 -- OVIE2 OVIE1 OVIE0 -- OVF2 OVF1 OVF0 H'FFF68 TCR0 8 -- CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FFF69 TIOR0 8 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 H'FFF6A TCNT0H 16 H'FFF6B TCNT0L Module Name 16-bit timer, (all channels) H'FFF67 H'FFF6C GRA0H H'FFF6D GRA0L 16 H'FFF6E GRB0H H'FFF6F GRB0L H'FFF70 TCR1 8 -- CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FFF71 TIOR1 8 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 H'FFF72 TCNT1H 16 H'FFF73 TCNT1L H'FFF74 GRA1H H'FFF75 GRA1L 16 GRB1H H'FFF77 GRB1L H'FFF78 TCR2 8 -- CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FFF79 TIOR2 8 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 H'FFF7A TCNT2H 16 H'FFF7B TCNT2L H'FFF7C GRA2H H'FFF7D GRA2L GRB2H H'FFF7F GRB2L 16-bit timer channel 1 16 H'FFF76 H'FFF7E 16-bit timer channel 0 16 16-bit timer channel 2 16 16 Rev. 3.00 Sep 14, 2005 page 741 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address (Low) Data Register Bus Width Bit 7 Name Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFF80 TCR0 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'FFF81 TCR1 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'FFF82 TCSR0 8 CMFB CMFA OVF ADTE OIS3 OIS2 OS1 OS0 H'FFF83 TCSR1 8 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0 H'FFF84 TCORA0 8 H'FFF85 TCORA1 8 H'FFF86 TCORB0 8 H'FFF8A -- -- -- -- -- -- -- -- -- H'FFF8B -- -- -- -- -- -- -- -- -- OVF WT/IT TME -- -- CKS2 CKS1 CKS0 -- -- -- -- -- -- -- -- H'FFF87 TCORB1 8 H'FFF88 TCNT0 8 H'FFF89 TCNT1 8 H'FFF8C TCSR*2 8 H'FFF8D TCNT*2 8 H'FFF8E -- H'FFF8F RSTCSR *2 8 WRST RSTOE -- -- -- -- -- -- H'FFF90 TCR2 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'FFF91 TCR3 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'FFF92 TCSR2 8 CMFB CMFA OVF -- OIS3 OIS2 OS1 OS0 H'FFF93 TCSR3 8 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0 H'FFF94 TCORA2 8 H'FFF95 TCORA3 8 H'FFF96 TCORB2 8 H'FFF9A -- -- -- -- -- -- -- -- -- H'FFF9B -- -- -- -- -- -- -- -- -- H'FFF97 TCORB3 8 H'FFF98 TCNT2 8 H'FFF99 TCNT3 8 H'FFF9C DADR0 8 H'FFF9D DADR1 8 H'FFF9E DACR 8 DAOE1 DAOE0 DAE -- -- -- -- -- H'FFF9F -- 8 -- -- -- -- -- -- -- -- Module Name 8-bit timer channels 0 and 1 WDT 8-bit timer channels 2 and 3 D/A converter Rev. 3.00 Sep 14, 2005 page 742 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Data Address Register Bus Width Bit 7 (Low) Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFFA0 TPMR 8 -- -- -- -- G3NOV G2NOV G1NOV G0NOV TPC H'FFFA1 TPCR 8 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Bit Names H'FFFA2 NDERB 8 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 H'FFFA3 NDERA 8 NDER7 NDER1 NDER0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 H'FFFA4 NDRB*3 8 H'FFFA5 NDRA*3 8 H'FFFA6 NDRB*3 8 H'FFFA7 NDRA*3 8 NDER6 NDER5 NDER4 NDER3 NDER2 NDER15 NDER14 NDER13 NDER12 -- -- -- -- NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 NDER7 NDER6 NDER5 NDER4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- NDER11 NDER10 NDER9 -- NDER8 -- -- -- -- -- -- -- -- -- -- -- -- NDER3 NDER2 NDER1 NDER0 C/A CHR PE O/E STOP MP CKS1 CKS0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER/ERS PER TEND MPB MPBT -- -- -- -- SDIR SINV -- SMIF H'FFFA8 H'FFFA9 H'FFFAA H'FFFAB H'FFFAC H'FFFAD H'FFFAE H'FFFAF H'FFFB0 SMR 8 H'FFFB1 BRR 8 H'FFFB2 SCR 8 H'FFFB3 TDR 8 H'FFFB4 SSR 8 H'FFFB5 RDR 8 H'FFFB6 SCMR 8 SCI channel 0 H'FFFB7 Reserved area (access prohibited) H'FFFB8 SMR 8 H'FFFB9 BRR 8 H'FFFBA SCR 8 H'FFFBB TDR 8 H'FFFBC SSR 8 H'FFFBD RDR 8 H'FFFBE SCMR 8 C/A CHR PE O/E STOP MP CKS1 CKS0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER/ERS PER TEND MPB MPBT -- -- -- -- SINV -- SMIF SDIR SCI channel 1 H'FFFBF Reserved area (access prohibited) Rev. 3.00 Sep 14, 2005 page 743 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address (Low) Data Register Bus Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFFC0 SMR 8 C/A CHR PE O/E STOP MP CKS1 CKS0 H'FFFC1 BRR 8 H'FFFC2 SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'FFFC3 TDR 8 H'FFFC4 SSR 8 TDRE RDRF ORER FER/ERS PER TEND MPB MPBT -- -- -- -- SDIR SINV -- SMIF -- Bit Names Module Name SCI channel 2 H'FFFC5 RDR 8 H'FFFC6 SCMR 8 H'FFFC7 Reserved area (access prohibited) H'FFFC8 -- -- -- -- -- -- -- -- H'FFFC9 -- -- -- -- -- -- -- -- -- H'FFFCA -- -- -- -- -- -- -- -- -- H'FFFCB -- -- -- -- -- -- -- -- -- H'FFFCC -- -- -- -- -- -- -- -- -- H'FFFCD -- -- -- -- -- -- -- -- -- H'FFFCE -- -- -- -- -- -- -- -- -- H'FFFCF -- -- -- -- -- -- -- -- -- H'FFFD0 P1DR 8 P17 P16 P15 P14 P13 P12 P11 P10 Port1 H'FFFD1 P2DR 8 P27 P26 P25 P24 P23 P22 P21 P20 Port2 H'FFFD2 P3DR 8 P37 P36 P35 P34 P33 P32 P31 P30 Port3 H'FFFD3 P4DR 8 P47 P46 P45 P44 P43 P42 P41 P40 Port4 H'FFFD4 P5DR 8 -- -- -- -- P53 P52 P51 P50 Port5 H'FFFD5 P6DR 8 P67 P66 P65 P64 P63 P62 P61 P60 Port6 H'FFFD6 P7DR 8 P77 P76 P75 P74 P73 P72 P71 P70 Port7 H'FFFD7 P8DR 8 -- -- -- P84 P83 P82 P81 P80 Port8 H'FFFD8 P9DR 8 -- -- P95 P94 P93 P92 P91 P90 Port9 H'FFFD9 PADR 8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PortA H'FFFDA PBDR 8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PortB H'FFFDB -- -- -- -- -- -- -- -- -- H'FFFDC -- -- -- -- -- -- -- -- -- H'FFFDD -- -- -- -- -- -- -- -- -- H'FFFDE -- -- -- -- -- -- -- -- -- H'FFFDF -- -- -- -- -- -- -- -- -- Rev. 3.00 Sep 14, 2005 page 744 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address (Low) Data Register Bus Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFFE0 ADDRAH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D converter H'FFFE1 ADDRAL 8 AD1 AD0 -- -- -- -- -- -- H'FFFE2 ADDRBH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'FFFE3 ADDRBL 8 AD1 AD0 -- -- -- -- -- -- H'FFFE4 ADDRCH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 Bit Names H'FFFE5 ADDRCL 8 AD1 AD0 -- -- -- -- -- -- H'FFFE6 ADDRDH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'FFFE7 ADDRDL 8 AD1 AD0 -- -- -- -- -- -- H'FFFE8 ADCSR 8 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 H'FFFE9 ADCR 8 TRGE -- -- -- -- -- -- -- Notes: 1. The RAMCR and FLMCR registers are used only in the flash memory and flash memory R versions, and are not provided in the mask ROM versions. 2. For write access to TCSR, TCNT, and RSTCSR, see section 12.2.4, Notes on Register Access. 3. The address depends on the output trigger setting. Legend WDT: Watchdog timer TPC: Programmable timing pattern controller SCI: Serial communication interface Rev. 3.00 Sep 14, 2005 page 745 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers B.2 Addresses (EMC = 0) Address Register (Low) Name Data Bus Width Bit 7 H'EE000 P1DDR 8 H'EE001 P2DDR 8 H'EE002 P3DDR H'EE003 Bit Names Bit 1 Bit 0 Module Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2 8 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3 P4DDR 8 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4 H'EE004 P5DDR 8 -- -- P53DDR P52DDR P51DDR P50DDR Port 5 H'EE005 P6DDR 8 -- P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6 H'EE006 -- -- -- -- -- -- -- -- H'EE007 P8DDR 8 -- -- -- P84DDR P83DDR P82DDR P81DDR P80DDR Port 8 H'EE008 P9DDR 8 -- -- P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Port 9 H'EE009 PADDR 8 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Port A H'EE00A PBDDR 8 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Port B Bit 6 Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 -- H'EE00B -- -- -- -- -- -- -- -- -- H'EE00C -- -- -- -- -- -- -- -- -- H'EE00D -- -- -- -- -- -- -- -- -- H'EE00E -- -- -- -- -- -- -- -- -- H'EE00F -- -- -- -- -- -- -- -- -- H'EE010 -- -- -- -- -- -- -- -- -- H'EE011 MDCR 8 -- -- -- -- -- MDS2 MDS1 MDS0 H'EE012 SYSCR 8 SSBY STS2 STS1 STS0 UE NMIEG SSOE RAME H'EE013 BRCR 8 A23E A22E A21E A20E -- -- -- BRLE Bus controller Interrupt controller H'EE014 ISCR 8 -- -- IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC H'EE015 IER 8 -- -- IRQ5E IRQ2E IRQ1E IRQ0E H'EE016 ISR 8 -- -- H'EE017 -- 8 -- -- IRQ4E IRQ3E IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F -- -- -- -- -- -- H'EE018 IPRA 8 IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 H'EE019 IPRB 8 IPRB7 IPRB6 IPRB5 -- IPRB3 IPRB2 IPRB1 -- H'EE01A DASTCR 8 -- -- -- -- -- -- -- DASTE H'EE01B DIVCR 8 -- -- -- -- -- -- H'EE01C MSTCRH 8 PSTOP -- -- -- -- System control D/A converter DIV1 DIV0 System MSTPH2 MSTPH1 MSTPH0 control H'EE01D MSTCRL 8 MSTPL7 -- MSTPL5 MSTPL4 MSTPL3 MSTPL2 -- MSTPL0 H'EE01E ADRCR 8 -- -- -- -- -- -- -- ADRCTL Bus controller H'EE01F 8 CS7E CS6E CS5E CS4E -- -- -- -- CSCR Rev. 3.00 Sep 14, 2005 page 746 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'EE020 ABWCR 8 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 H'EE021 ASTCR 8 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 H'EE022 WCRH 8 W71 W70 W61 W60 W51 W50 W41 W40 H'EE023 WCRL 8 W31 W30 W21 W20 W11 W10 W01 W00 H'EE024 BCR 8 ICIS1 ICIS0 BROME BRSTS1 BRSTS0 EMC RDEA WAITE H'EE025 (FLWCR) -- -- -- -- -- -- -- BE -- H'EE026 DRCRA 8 DRAS2 DRAS1 DRAS0 -- RDM SRFMD RFSHE H'EE027 DRCRB 8 MXC1 MXC0 CSEL RCYCE -- TPC RCW RLW CMF CMIE CKS2 CKS1 -- -- -- H'EE028 RTMCSR 8 H'EE029 RTCNT 8 H'EE02A RTCOR 8 H'EE02B -- 8 H'EE02C DCR0 8 H'EE02D DCR1 8 H'EE02E DCR2 8 H'EE02F DCR3 8 H'EE030 FLMCR1 8 FWE H'EE031 FLMCR2 8 FLER H'EE032 EBR1 8 H'EE033 EBR2 8 H'EE034 Reserved area (access prohibited) CKS0 Module Name Bus controller DRAM interface Bus controller SWE ESU PSU EV PV E P EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 -- -- EB13 EB12 EB11 EB10 EB9 EB8 P27PCR P20PCR Flash memory H'EE035 H'EE036 H'EE037 H'EE03C P2PCR 8 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR H'EE03D -- 8 -- -- -- H'EE03E P4PCR 8 P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR Port 4 H'EE03F 8 -- P51PCR P50PCR Port 5 P5PCR -- -- -- -- -- -- -- -- P53PCR P52PCR Port 2 Rev. 3.00 Sep 14, 2005 page 747 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'EE040 -- -- -- -- -- -- -- -- -- H'EE041 -- -- -- -- -- -- -- -- -- H'EE042 -- -- -- -- -- -- -- -- -- H'EE043 -- -- -- -- -- -- -- -- -- H'EE044 -- -- -- -- -- -- -- -- -- H'EE045 -- -- -- -- -- -- -- -- -- H'EE046 -- -- -- -- -- -- -- -- -- H'EE047 -- -- -- -- -- -- -- -- -- H'EE048 -- -- -- -- -- -- -- -- -- H'EE049 -- -- -- -- -- -- -- -- -- H'EE04A -- -- -- -- -- -- -- -- -- H'EE04B -- -- -- -- -- -- -- -- -- H'EE04C -- -- -- -- -- -- -- -- -- H'EE04D -- -- -- -- -- -- -- -- -- H'EE04E -- -- -- -- -- -- -- -- -- H'EE04F -- -- -- -- -- -- -- -- -- H'EE050 -- -- -- -- -- -- -- -- -- H'EE051 -- -- -- -- -- -- -- -- -- H'EE052 -- -- -- -- -- -- -- -- -- H'EE053 -- -- -- -- -- -- -- -- -- H'EE054 -- -- -- -- -- -- -- -- -- H'EE055 -- -- -- -- -- -- -- -- -- H'EE056 -- -- -- -- -- -- -- -- -- H'EE057 -- -- -- -- -- -- -- -- -- H'EE058 -- -- -- -- -- -- -- -- -- H'EE059 -- -- -- -- -- -- -- -- -- H'EE05A -- -- -- -- -- -- -- -- -- H'EE05B -- -- -- -- -- -- -- -- -- H'EE05C -- -- -- -- -- -- -- -- -- H'EE05D -- -- -- -- -- -- -- -- -- H'EE05E -- -- -- -- -- -- -- -- -- H'EE05F -- -- -- -- -- -- -- -- -- Rev. 3.00 Sep 14, 2005 page 748 of 910 REJ09B0258-0300 Module Name Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'EE060 -- -- -- -- -- -- -- -- -- H'EE061 -- -- -- -- -- -- -- -- -- H'EE062 -- -- -- -- -- -- -- -- -- H'EE063 -- -- -- -- -- -- -- -- -- H'EE064 -- -- -- -- -- -- -- -- -- H'EE065 -- -- -- -- -- -- -- -- -- H'EE066 -- -- -- -- -- -- -- -- -- H'EE067 -- -- -- -- -- -- -- -- -- H'EE068 -- -- -- -- -- -- -- -- -- H'EE069 -- -- -- -- -- -- -- -- -- H'EE06A -- -- -- -- -- -- -- -- -- H'EE06B -- -- -- -- -- -- -- -- -- H'EE06C -- -- -- -- -- -- -- -- -- H'EE06D -- -- -- -- -- -- -- -- -- H'EE06E -- -- -- -- -- -- -- -- -- H'EE06F -- -- -- -- -- -- -- -- -- H'EE070 Reserved area (access prohibited) -- -- RAMS RAM2 RAM1 RAM0 Module Name H'EE071 H'EE072 H'EE073 H'EE074 H'EE075 H'EE076 H'EE077 RAMCR *1 8 -- -- H'EE078 Reserved area (access prohibited) Flash memory*1 H'EE079 H'EE07A H'EE07B H'EE07C H'EE07D H'EE07E H'EE07F Rev. 3.00 Sep 14, 2005 page 749 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name OVF WT/IT TME -- -- CKS2 CKS1 CKS0 WDT H'EE090 TCSR*2 8 H'EE091 TCNT*2 8 Bit Names H'EE092 -- -- -- -- -- -- -- -- -- H'EE093 RSTCSR*2 8 WRST -- -- -- -- -- -- -- H'EE094 Reserved area (access prohibited) H'EE095 H'EE096 H'EE097 H'EE098 H'EE099 H'EE09A H'EE09B H'EE09C H'EE09D H'EE09E H'EE09F H'EE0A0 H'EE0A1 H'EE0A2 H'EE0A3 H'EE0A4 H'EE0A5 H'EE0A6 H'EE0A7 H'EE0A8 H'EE0A9 H'EE0AA H'EE0AB H'EE0AC H'EE0AD H'EE0AE H'EE0AF Rev. 3.00 Sep 14, 2005 page 750 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE0B0 Reserved area (access prohibited) H'EE0B1 H'EE0B2 H'EE0B3 H'EE0B4 H'EE0B5 H'EE0B6 H'EE0B7 H'EE0B8 H'EE0B9 H'EE0BA H'EE0BB H'EE0BC H'EE0BD H'EE0BE H'EE0BF H'EE0C0 H'EE0C1 H'EE0C2 H'EE0C3 H'EE0C4 H'EE0C5 H'EE0C6 H'EE0C7 H'EE0C8 H'EE0C9 H'EE0CA H'EE0CB H'EE0CC H'EE0CD H'EE0CE H'EE0CF Rev. 3.00 Sep 14, 2005 page 751 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit Names Bit 6 Bit 5 H'EE0D0 Reserved area (access prohibited) H'EE0D1 H'EE0D2 H'EE0D3 H'EE0D4 H'EE0D5 H'EE0D6 H'EE0D7 H'EE0D8 H'EE0D9 H'EE0DA H'EE0DB H'EE0DC H'EE0DD H'EE0DE H'EE0DF H'EE0E0 H'EE0E1 H'EE0E2 H'EE0E3 H'EE0E4 H'EE0E5 H'EE0E6 H'EE0E7 H'EE0E8 H'EE0E9 H'EE0EA H'EE0EB H'EE0EC H'EE0ED H'EE0EE H'EE0EF Rev. 3.00 Sep 14, 2005 page 752 of 910 REJ09B0258-0300 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Appendix B Internal I/O Registers Address Register (Low) Name H'EE0F0 Data Bus Width Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Reserved area (access prohibited) H'EE0F1 H'EE0F2 H'EE0F3 H'EE0F4 H'EE0F5 H'EE0F6 H'EE0F7 H'EE0F8 H'EE0F9 H'EE0FA H'EE0FB H'EE0FC H'EE0FD H'EE0FE H'EE0FF H'FFE00 -- -- -- -- -- -- -- -- -- H'FFE01 -- -- -- -- -- -- -- -- -- H'FFE02 -- -- -- -- -- -- -- -- -- H'FFE03 -- -- -- -- -- -- -- -- -- H'FFE04 -- -- -- -- -- -- -- -- -- H'FFE05 -- -- -- -- -- -- -- -- -- H'FFE06 -- -- -- -- -- -- -- -- -- H'FFE07 -- -- -- -- -- -- -- -- -- H'FFE08 -- -- -- -- -- -- -- -- -- H'FFE09 -- -- -- -- -- -- -- -- -- H'FFE0A -- -- -- -- -- -- -- -- -- H'FFE0B -- -- -- -- -- -- -- -- -- H'FFE0C -- -- -- -- -- -- -- -- -- H'FFE0D -- -- -- -- -- -- -- -- -- H'FFE0E -- -- -- -- -- -- -- -- -- H'FFE0F -- -- -- -- -- -- -- -- -- Rev. 3.00 Sep 14, 2005 page 753 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFE10 -- -- -- -- -- -- -- -- -- H'FFE11 -- -- -- -- -- -- -- -- -- H'FFE12 -- -- -- -- -- -- -- -- -- H'FFE13 -- -- -- -- -- -- -- -- -- H'FFE14 -- -- -- -- -- -- -- -- -- H'FFE15 -- -- -- -- -- -- -- -- -- H'FFE16 -- -- -- -- -- -- -- -- -- H'FFE17 -- -- -- -- -- -- -- -- -- H'FFE18 -- -- -- -- -- -- -- -- -- H'FFE19 -- -- -- -- -- -- -- -- -- H'FFE1A -- -- -- -- -- -- -- -- -- H'FFE1B -- -- -- -- -- -- -- -- -- H'FFE1C -- -- -- -- -- -- -- -- -- H'FFE1D -- -- -- -- -- -- -- -- -- H'FFE1E -- -- -- -- -- -- -- -- -- H'FFE1F -- -- -- -- -- -- -- -- -- H'FFE20 -- -- -- -- -- -- -- -- -- H'FFE21 -- -- -- -- -- -- -- -- -- H'FFE22 -- -- -- -- -- -- -- -- -- H'FFE23 -- -- -- -- -- -- -- -- -- H'FFE24 -- -- -- -- -- -- -- -- -- H'FFE25 -- -- -- -- -- -- -- -- -- H'FFE26 -- -- -- -- -- -- -- -- -- H'FFE27 -- -- -- -- -- -- -- -- -- H'FFE28 -- -- -- -- -- -- -- -- -- H'FFE29 -- -- -- -- -- -- -- -- -- H'FFE2A -- -- -- -- -- -- -- -- -- H'FFE2B -- -- -- -- -- -- -- -- -- H'FFE2C -- -- -- -- -- -- -- -- -- H'FFE2D -- -- -- -- -- -- -- -- -- H'FFE2E -- -- -- -- -- -- -- -- -- H'FFE2F -- -- -- -- -- -- -- -- -- Rev. 3.00 Sep 14, 2005 page 754 of 910 REJ09B0258-0300 Module Name Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFE30 -- -- -- -- -- -- -- -- -- H'FFE31 -- -- -- -- -- -- -- -- -- H'FFE32 -- -- -- -- -- -- -- -- -- H'FFE33 -- -- -- -- -- -- -- -- -- H'FFE34 -- -- -- -- -- -- -- -- -- H'FFE35 -- -- -- -- -- -- -- -- -- H'FFE36 -- -- -- -- -- -- -- -- -- H'FFE37 -- -- -- -- -- -- -- -- -- H'FFE38 -- -- -- -- -- -- -- -- -- H'FFE39 -- -- -- -- -- -- -- -- -- H'FFE3A -- -- -- -- -- -- -- -- -- H'FFE3B -- -- -- -- -- -- -- -- -- H'FFE3C -- -- -- -- -- -- -- -- -- H'FFE3D -- -- -- -- -- -- -- -- -- H'FFE3E -- -- -- -- -- -- -- -- -- H'FFE3F -- -- -- -- -- -- -- -- -- H'FFE40 -- -- -- -- -- -- -- -- -- H'FFE41 -- -- -- -- -- -- -- -- -- H'FFE42 -- -- -- -- -- -- -- -- -- H'FFE43 -- -- -- -- -- -- -- -- -- H'FFE44 -- -- -- -- -- -- -- -- -- H'FFE45 -- -- -- -- -- -- -- -- -- H'FFE46 -- -- -- -- -- -- -- -- -- H'FFE47 -- -- -- -- -- -- -- -- -- H'FFE48 -- -- -- -- -- -- -- -- -- H'FFE49 -- -- -- -- -- -- -- -- -- H'FFE4A -- -- -- -- -- -- -- -- -- H'FFE4B -- -- -- -- -- -- -- -- -- H'FFE4C -- -- -- -- -- -- -- -- -- H'FFE4D -- -- -- -- -- -- -- -- -- H'FFE4E -- -- -- -- -- -- -- -- -- H'FFE4F -- -- -- -- -- -- -- -- -- Module Name Rev. 3.00 Sep 14, 2005 page 755 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFE50 -- -- -- -- -- -- -- -- -- H'FFE51 -- -- -- -- -- -- -- -- -- H'FFE52 -- -- -- -- -- -- -- -- -- H'FFE53 -- -- -- -- -- -- -- -- -- H'FFE54 -- -- -- -- -- -- -- -- -- H'FFE55 -- -- -- -- -- -- -- -- -- H'FFE56 -- -- -- -- -- -- -- -- -- H'FFE57 -- -- -- -- -- -- -- -- -- H'FFE58 -- -- -- -- -- -- -- -- -- H'FFE59 -- -- -- -- -- -- -- -- -- H'FFE5A -- -- -- -- -- -- -- -- -- H'FFE5B -- -- -- -- -- -- -- -- -- H'FFE5C -- -- -- -- -- -- -- -- -- H'FFE5D -- -- -- -- -- -- -- -- -- H'FFE5E -- -- -- -- -- -- -- -- -- H'FFE5F -- -- -- -- -- -- -- -- -- H'FFE60 -- -- -- -- -- -- -- -- -- H'FFE61 -- -- -- -- -- -- -- -- -- H'FFE62 -- -- -- -- -- -- -- -- -- H'FFE63 -- -- -- -- -- -- -- -- -- H'FFE64 -- -- -- -- -- -- -- -- -- H'FFE65 -- -- -- -- -- -- -- -- -- H'FFE66 -- -- -- -- -- -- -- -- -- H'FFE67 -- -- -- -- -- -- -- -- -- H'FFE68 -- -- -- -- -- -- -- -- -- H'FFE69 -- -- -- -- -- -- -- -- -- H'FFE6A -- -- -- -- -- -- -- -- -- H'FFE6B -- -- -- -- -- -- -- -- -- H'FFE6C -- -- -- -- -- -- -- -- -- H'FFE6D -- -- -- -- -- -- -- -- -- H'FFE6E -- -- -- -- -- -- -- -- -- H'FFE6F -- -- -- -- -- -- -- -- -- Rev. 3.00 Sep 14, 2005 page 756 of 910 REJ09B0258-0300 Module Name Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFE70 -- -- -- -- -- -- -- -- -- H'FFE71 -- -- -- -- -- -- -- -- -- H'FFE72 -- -- -- -- -- -- -- -- -- H'FFE73 -- -- -- -- -- -- -- -- -- H'FFE74 -- -- -- -- -- -- -- -- -- H'FFE75 -- -- -- -- -- -- -- -- -- H'FFE76 -- -- -- -- -- -- -- -- -- H'FFE77 -- -- -- -- -- -- -- -- -- H'FFE78 -- -- -- -- -- -- -- -- -- H'FFE79 -- -- -- -- -- -- -- -- -- H'FFE7A -- -- -- -- -- -- -- -- -- H'FFE7B -- -- -- -- -- -- -- -- -- H'FFE7C -- -- -- -- -- -- -- -- -- H'FFE7D -- -- -- -- -- -- -- -- -- H'FFE7E -- -- -- -- -- -- -- -- -- H'FFE7F -- -- -- -- -- -- -- -- -- H'FFE80 MAR0AR 8 H'FFE81 MAR0AE 8 H'FFE82 MAR0AH 8 H'FFE83 MAR0AL 8 H'FFE84 ETCR0AH 8 H'FFE85 ETCR0AL 8 H'FFE86 IOAR0A 8 H'FFE87 DTCR0A 8 H'FFE88 MAR0BR 8 H'FFE89 MAR0BE 8 H'FFE8A MAR0BH 8 H'FFE8B MAR0BL 8 Module Name DMAC channel 0A DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Full address mode DMAC channel 0B H'FFE8C ETCR0BH 8 H'FFE8D ETCR0BL 8 H'FFE8E IOAR0B 8 H'FFE8F 8 DTCR0B DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode DTME -- DAID DAIDE TMS DTS2B DTS1B DTS0B Full address mode Rev. 3.00 Sep 14, 2005 page 757 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 H'FFE90 MAR1AR 8 H'FFE91 MAR1AE 8 H'FFE92 MAR1AH 8 H'FFE93 MAR1AL 8 H'FFE94 ETCR1AH 8 H'FFE95 ETCR1AL 8 H'FFE96 IOAR1A 8 H'FFE97 DTCR1A 8 H'FFE98 MAR1BR 8 H'FFE99 MAR1BE 8 H'FFE9A MAR1BH 8 H'FFE9B MAR1BL 8 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name DMAC channel 1A DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Full address mode DMAC channel 1B H'FFE9C ETCR1BH 8 H'FFE9D ETCR1BL 8 H'FFE9E IOAR1B 8 H'FFE9F 8 DTCR1B DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode DTME -- DAID DAIDE TMS DTS2B DTS1B DTS0B Full address mode 16-bit timer, (all channels) H'FFEA0 TSTR 8 -- -- -- -- -- STR2 STR1 STR0 H'FFEA1 TSNC 8 -- -- -- -- -- SYNC2 SYNC1 SYNC0 H'FFEA2 TMDR 8 -- MDF FDIR -- -- PWM2 PWM1 PWM0 H'FFEA3 TOLR 8 -- -- TOB2 TOA2 TOB1 TOA1 TOB0 TOA0 H'FFEA4 TISRA 8 -- IMIEA2 IMIEA1 IMIEA0 -- IMFA2 IMFA1 IMFA0 H'FFEA5 TISRB 8 -- IMIEB2 IMIEB1 IMIEB0 -- IMFB2 IMFB1 IMFB0 H'FFEA6 TISRC 8 -- OVIE2 OVIE1 OVIE0 -- OVF2 OVF1 OVF0 H'FFEA8 16TCR0 8 -- CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FFEA9 TIOR0 8 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 H'FFEA7 -- H'FFEAA 16TCNT0H 16 H'FFEAB 16TCNT0L H'FFEAC GRA0H 16 H'FFEAD GRA0L H'FFEAE GRB0H 16 H'FFEAF GRB0L Rev. 3.00 Sep 14, 2005 page 758 of 910 REJ09B0258-0300 16-bit timer channel 0 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit 6 Bit 5 H'FFEB0 16TCR1 8 -- CCLR1 H'FFEB1 TIOR1 8 -- IOB2 Bit Names Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 IOB1 IOB0 -- IOA2 IOA1 IOA0 Module Name 16-bit timer channel 1 H'FFEB2 16TCNT1H 16 H'FFEB3 16TCNT1L H'FFEB4 GRA1H 16 H'FFEB5 GRA1L H'FFEB6 GRB1H 16 H'FFEB7 GRB1L H'FFEB8 16TCR2 8 -- CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FFEB9 TIOR2 8 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 16-bit timer channel 2 H'FFEBA 16TCNT2H 16 H'FFEBB 16TCNT2L H'FFEBC GRA2H 16 H'FFEBD GRA2L H'FFEBE GRB2H 16 H'FFEBF GRB2L H'FFEC0 8TCR0 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'FFEC1 8TCR1 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'FFEC2 8TCSR0 8 CMFB CMFA OVF ADTE OIS3 OIS2 OS1 OS0 H'FFEC3 8TCSR1 8 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0 H'FFEC4 TCORA0 8 H'FFEC5 TCORA1 8 H'FFEC6 TCORB0 8 H'FFEC7 TCORB1 8 H'FFEC8 8TCNT0 8 H'FFEC9 8TCNT1 8 8-bit timer channels 0 and 1 H'FFECA Reserved area (access prohibited) H'FFECB H'FFECC H'FFECD H'FFECE H'FFECF Rev. 3.00 Sep 14, 2005 page 759 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFED0 8TCR2 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'FFED1 8TCR3 8 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Bit Names H'FFED2 8TCSR2 8 CMFB CMFA OVF -- OIS3 OIS2 OS1 OS0 H'FFED3 8TCSR3 8 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0 H'FFED4 TCORA2 8 H'FFED5 TCORA3 8 H'FFED6 TCORB2 8 H'FFED7 TCORB3 8 H'FFED8 8TCNT2 8 H'FFED9 8TCNT3 8 Module Name 8-bit timer channels 2 and 3 H'FFEDA Reserved area (access prohibited) H'FFEDB H'FFEDC H'FFEDD H'FFEDE H'FFEDF H'FFEE0 SMR 8 H'FFEE1 BRR 8 H'FFEE2 SCR 8 H'FFEE3 TDR 8 H'FFEE4 SSR 8 H'FFEE5 RDR 8 H'FFEE6 SCMR 8 H'FFEE7 -- H'FFEE8 SMR 8 H'FFEE9 BRR 8 H'FFEEA SCR 8 H'FFEEB TDR 8 H'FFEEC SSR 8 H'FFEED RDR 8 H'FFEEE SCMR 8 H'FFEEF -- C/A CHR PE O/E STOP MP CKS1 CKS0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER/ ERS PER TEND MPB MPBT -- -- -- -- SDIR SINV -- SMIF -- -- -- -- -- -- -- -- C/A CHR PE O/E STOP MP CKS1 CKS0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER/ ERS PER TEND MPB MPBT -- -- -- -- SDIR SINV -- SMIF -- -- -- -- -- -- -- -- Rev. 3.00 Sep 14, 2005 page 760 of 910 REJ09B0258-0300 SCI channel 0 SCI channel 1 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C/A CHR PE O/E STOP MP CKS1 CKS0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER/ ERS PER TEND MPB MPBT -- -- -- -- SDIR SINV -- SMIF -- -- -- -- -- -- -- -- -- -- -- -- G3NOV G2NOV G1NOV G0NOV H'FFEF0 SMR 8 H'FFEF1 BRR 8 H'FFEF2 SCR 8 H'FFEF3 TDR 8 H'FFEF4 SSR 8 H'FFEF5 RDR 8 H'FFEF6 SCMR 8 H'FFEF7 -- H'FFEF8 TPMR H'FFEF9 TPCR 8 Bit Names 8 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 H'FFEFA NDERB 8 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 H'FFEFB NDERA 8 NDER7 3 8 H'FFEFC NDRB* H'FFEFD NDRA*3 8 H'FFEFE NDRB*3 8 H'FFEFF NDRA*3 8 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 NDR8 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR15 NDR14 NDR13 NDR12 -- -- -- -- NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 NDR7 NDR6 NDR5 NDR4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- NDR11 NDR10 NDR9 NDR8 -- -- -- -- -- -- -- -- -- -- -- -- NDR3 NDR2 NDR1 NDR0 H'FFFE0 ADDRAH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'FFFE1 ADDRAL 8 AD1 AD0 -- -- -- -- -- -- H'FFFE2 ADDRBH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'FFFE3 ADDRBL 8 AD1 AD0 -- -- -- -- -- -- H'FFFE4 ADDRCH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'FFFE5 ADDRCL 8 AD1 AD0 -- -- -- -- -- -- H'FFFE6 ADDRDH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'FFFE7 ADDRDL 8 AD1 AD0 -- -- -- -- -- -- H'FFFE8 ADCSR 8 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 H'FFFE9 ADCR 8 TRGE -- -- -- -- -- -- -- Module Name SCI channel 2 A/D converter H'FFFEA Reserved area (access prohibited) H'FFFEB H'FFFEC DADR0 8 H'FFFED DADR1 8 H'FFFEE DACR 8 -- -- -- -- -- -- -- -- H'FFFEF -- 8 -- -- -- -- -- -- -- -- D/A converter Rev. 3.00 Sep 14, 2005 page 761 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers Address Register (Low) Name Data Bus Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFFF0 P1DR 8 P17 P16 P15 P14 P13 P12 P11 P10 Port1 H'FFFF1 P2DR 8 P27 P26 P25 P24 P23 P22 P21 P20 Port2 H'FFFF2 P3DR 8 P37 P36 P35 P34 P33 P32 P31 P30 Port3 H'FFFF3 P4DR 8 P47 P46 P45 P44 P43 P42 P41 P40 Port4 H'FFFF4 P5DR 8 -- -- -- -- P53 P52 P51 P50 Port5 H'FFFF5 P6DR 8 P67 P66 P65 P64 P63 P62 P61 P60 Port6 H'FFFF6 P7DR 8 P77 P76 P75 P74 P73 P72 P71 P70 Port7 H'FFFF7 P8DR 8 -- -- -- P84 P83 P82 P81 P80 Port8 H'FFFF8 P9DR 8 -- -- P95 P94 P93 P92 P91 P90 Port9 H'FFFF9 PADR 8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PortA H'FFFFA PBDR 8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PortB H'FFFFB -- -- -- -- -- -- -- -- -- H'FFFFC -- -- -- -- -- -- -- -- -- H'FFFFD -- -- -- -- -- -- -- -- -- H'FFFFE -- -- -- -- -- -- -- -- -- H'FFFFF -- -- -- -- -- -- -- -- -- Bit Names Notes: 1. The RAMCR and FLMCR registers are used only in the flash memory and flash memory R versions, and are not provided in the mask ROM versions. 2. For write access to TCSR, TCNT, and RSTCSR, see section 12.2.4, Notes on Register Access. 3. The address depends on the output trigger setting. Legend WDT: Watchdog timer TPC: Programmable timing pattern controller SCI: Serial communication interface Rev. 3.00 Sep 14, 2005 page 762 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers B.3 Functions Register abbreviation Address to which register is mapped* Register name TIER--Timer Interrupt Enable Register H' 90 Name of on-chip supporting module FRT Bit numbers Bit Initial bit values Initial value R/W: 6 5 ICIAE ICIBE ICICE 0 R/W 0 R/W 0 R/W OCIDE OCIAE OCIBE Read only W Write only 0 OVIE 1 R/W 1 R/W 0 R/W 0 R/W 1 Names of the bits. Dashes (--) indicate reserved bits. Timer overflow interrupt enable Possible types of access R 1 2 3 4 7 R/W Read and write 0 Interrupt requested by OVF flag is disabled 1 Interrupt requested by OVF flag is enabled Output compare interrupt B enable 0 Interrupt requested by OCFB flag is disabled 1 Interrupt requested by OCFB flag is enabled Full name of bit Output compare interrupt A enable 0 Interrupt requested by OCFA flag is disabled 1 Interrupt requested by OCFA flag is enabled Descriptions of bit settings Input capture interrupt D enable 0 Interrupt requested by ICFD flag is disabled 1 Interrupt requested by ICFD flag is enabled Note: * When the EMC bit in BCR is cleared to 0, addresses of some registers are changed. Rev. 3.00 Sep 14, 2005 page 763 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers P1DDR--Port 1 Data Direction Register Bit 7 6 H'EE000 5 4 3 Port 1 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Modes 1 to 4 Initial value Read/Write 1 1 1 1 1 1 1 1 Modes 5 to 7 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port 1 input/output select 0 Generic input 1 Generic output P2DDR--Port 2 Data Direction Register Bit 7 6 H'EE001 5 4 3 Port 2 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Modes 1 to 4 Initial value Read/Write 1 1 1 1 1 1 1 1 Modes 5 to 7 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port 2 input/output select Rev. 3.00 Sep 14, 2005 page 764 of 910 REJ09B0258-0300 0 Generic input 1 Generic output Appendix B Internal I/O Registers P3DDR--Port 3 Data Direction Register Bit 7 6 H'EE002 5 4 3 2 Port 3 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port 3 input/output select 0 Generic input 1 Generic output P4DDR--Port 4 Data Direction Register Bit 7 6 H'EE003 5 4 3 2 Port 4 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port 4 input/output select 0 Generic input 1 Generic output Rev. 3.00 Sep 14, 2005 page 765 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers P5DDR--Port 5 Data Direction Register Bit 7 6 H'EE004 5 4 Port 5 2 3 1 0 P53DDR P52DDR P51DDR P50DDR Modes 1 to 4 Initial value Read/Write 1 1 1 1 1 1 1 1 Modes 5 to 7 Initial value Read/Write 1 1 1 1 0 W 0 W 0 W 0 W Port 5 input/output select P6DDR--Port 6 Data Direction Register Bit 7 6 0 Generic input pin 1 Generic output pin H'EE005 5 4 3 2 Port 6 1 0 P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value Read/Write 1 0 W 0 W 0 W 0 W 0 W Port 6 input/output select Rev. 3.00 Sep 14, 2005 page 766 of 910 REJ09B0258-0300 0 Generic input 1 Generic output 0 W 0 W Appendix B Internal I/O Registers P8DDR--Port 8 Data Direction Register Bit 7 6 H'EE007 5 4 3 Port 8 2 1 0 P84DDR P83DDR P82DDR P81DDR P80DDR Modes 1 to 4 Initial value Read/Write 1 1 1 1 W 0 W 0 W 0 W 0 W Modes 5 to 7 Initial value Read/Write 1 1 1 0 W 0 W 0 W 0 W 0 W Port 8 input/output select 0 Generic input 1 Generic output Rev. 3.00 Sep 14, 2005 page 767 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers P9DDR--Port 9 Data Direction Register Bit 7 6 H'EE008 5 4 3 2 Port 9 1 0 P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Initial value Read/Write 1 1 0 W 0 W 0 W 0 W 0 W 0 W Port 9 input/output select 0 Generic input 1 Generic output PADDR--Port A Data Direction Register Bit 7 6 H'EE009 5 4 3 Port A 2 1 0 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Modes 3, 4 Initial value Read/Write 1 0 W 0 W 0 W 0 W 0 W 0 W 0 W Modes 1, 2, 5, 6, 7 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port A input/output select 0 Generic input 1 Generic output PBDDR--Port B Data Direction Register Bit 7 6 H'EE00A 5 4 3 2 Port B 1 0 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W Port B input/output select Rev. 3.00 Sep 14, 2005 page 768 of 910 REJ09B0258-0300 0 Generic input 1 Generic output 0 W 0 W Appendix B Internal I/O Registers MDCR--Mode Control Register Bit Initial value Read/Write 7 1 6 1 H'EE011 5 0 4 0 3 System control 2 1 0 MDS2 MDS1 MDS0 * 0 R * R * R Mode select 2 to 0 Bit 2 Bit 1 Bit 0 MD2 MD1 MD0 0 0 1 0 1 1 Operating Mode 0 1 Mode 1 0 Mode 2 1 Mode 3 0 Mode 4 1 Mode 5 0 Mode 6 1 Mode 7 Note: * Determined by the state of the mode pins (MD2 to MD0). Rev. 3.00 Sep 14, 2005 page 769 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers SYSCR--System Control Register Bit Initial value Read/Write H'EE012 System control 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 UE NMIEG SSOE RAME 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 1 R/W RAM enable 0 1 On-chip RAM is disabled On-chip RAM is enabled Software standby output port enable 0 1 In software standby mode, all address bus and bus control signals are highimpedance In software standby mode, address bus retains output state and bus control signals are fixed high NMI edge select An interrupt is requested at the falling edge of NMI 0 An interrupt is requested at the rising edge of NMI 1 User bit enable CCR bit 6 (UI) is used as an interrupt mask bit 0 CCR bit 6 (UI) is used as a user bit 1 Standby timer select 2 to 0 Bit 6 STS2 Bit 5 STS1 0 0 1 0 1 1 Bit 4 STS0 0 1 0 1 0 1 0 1 Standby Timer Waiting Time = 8,192 states Waiting Time = 16,384 states Waiting Time = 32,768 states Waiting Time = 65,536 states Waiting Time = 131,072 states Waiting Time = 26,2144 states Waiting Time = 1,024 states Illegal setting Software standby 0 1 SLEEP instruction causes transition to sleep mode SLEEP instruction causes transition to software standby mode Rev. 3.00 Sep 14, 2005 page 770 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers BRCR--Bus Release Control Register Bit H'EE013 7 6 5 4 3 A23E A22E A21E A20E Bus controller 2 1 0 BRLE Modes 1, 2, 6, 7 Initial value Read/Write 1 1 1 1 1 1 1 0 R/W Modes 3, 4 Initial value Read/Write 1 R/W 1 R/W 1 R/W 0 1 1 1 0 R/W Mode 5 Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 1 1 0 R/W Bus release enable Address 23 to 20 enable 0 Address output 1 Other input/output 0 1 ISCR--IRQ Sense Control Register Bit 7 6 5 H'EE014 4 3 2 The bus cannot be released to an external device The bus can be released to an external device Interrupt Controller 1 0 IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W IRQ5 to IRQ0 sense control 0 Interrupts are requested when IRQ5 to IRQ0 are low 1 Interrupts are requested by falling-edge input at IRQ5 to IRQ0 Rev. 3.00 Sep 14, 2005 page 771 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers IER--IRQ Enable Register Bit Initial value Read/Write H'EE015 7 6 0 R/W 0 R/W Interrupt Controller 5 4 3 2 1 0 IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W IRQ5 to IRQ0 enable 0 IRQ5 to IRQ0 interrupts are disabled 1 IRQ5 to IRQ0 interrupts are enabled ISR--IRQ Status Register Bit Initial value Read/Write H'EE016 6 7 0 0 Interrupt Controller 5 4 3 2 1 0 IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* IRQ5 to IRQ0 flags Bits 5 to 0 Setting and Clearing Conditions IRQ5F to IRQ0F [Clearing conditions] * Read IRQnF when IRQnF = 1, then write 0 in IRQnF. 0 * IRQnSC = 0, IRQn input is high, and interrupt exception handling is being carried out. * IRQnSC = 1 and IRQn interrupt exception handling is being carried out. [Setting conditions] 1 * IRQnSC = 0 and IRQn input is low. * IRQnSC = 1 and IRQn input changes from high to low. (n = 5 to 0) Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Sep 14, 2005 page 772 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers IPRA--Interrupt Priority Register A Interrupt Controller 7 6 5 4 3 2 1 0 IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Initial value Read/Write H'EE018 Priority level A7 to A0 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) * Interrupt sources controlled by each bit Bit IPRA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 IRQ0 IRQ1 IRQ2, IRQ4, WDT, 16-bit 16-bit 16-bit IRQ3 IRQ5 DRAM timer timer timer Interrupt source interface, channel 0 channel 1 channel 2 A/D converter IPRB--Interrupt Priority Register B Bit Initial value Read/Write H'EE019 7 6 5 IPRB7 IPRB6 IPRB5 0 R/W 0 R/W 0 R/W 4 0 R/W Interrupt Controller 3 2 1 IPRB3 IPRB2 IPRB1 0 R/W 0 R/W 0 R/W 0 0 R/W Priority level B7 to B5, B3 to B1 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) * Interrupt sources controlled by each bit Bit IPRB Bit 7 Bit 6 Bit 5 IPRB7 IPRB6 IPRB5 8-bit timer 8-bit timer Interrupt channels channels source 0 and 1 2 and 3 DMAC Bit 4 Bit 3 Bit 2 Bit 1 IPRB3 IPRB2 IPRB1 SCI SCI SCI Bit 0 channel 0 channel 1 channel 2 Rev. 3.00 Sep 14, 2005 page 773 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers DASTCR--D/A Standby Control Register Bit 7 6 5 H'EE01A 4 3 2 D/A 1 0 DASTE Initial value Read/Write 1 1 1 1 1 1 1 0 R/W D/A standby enable 0 D/A output is disabled in software standby mode 1 D/A output is enabled in software standby mode Rev. 3.00 Sep 14, 2005 page 774 of 910 REJ09B0258-0300 (Initial value) Appendix B Internal I/O Registers DIVCR--Division Control Register Bit Initial value Read/Write 7 1 6 1 5 1 H'EE01B 4 1 3 2 1 1 System control 1 0 DIV1 DIV0 0 R/W 0 R/W Divide 1 and 0 Bit 1 Bit 0 DIV1 DIV0 0 1 Frequency Division Ratio 0 1/1 1 1/2 0 1/4 1 1/8 (Initial value) Rev. 3.00 Sep 14, 2005 page 775 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers MSTCRH--Module Standby Control Register H 7 Bit 6 4 5 H'EE01C 3 PSTOP Initial value 0 Read/Write R/W 2 System control 1 0 MSTPH2 MSTPH1 MSTPH0 1 1 1 1 0 0 R/W R/W 0 R/W Module standby H2 to H0 Selection bits for placing modules in standby state. Reserved bits clock stop Enables or disables o clock output. MSTCRL--Module Standby Control Register L Bit 7 6 MSTPL7 5 4 H'EE01D System control 3 1 2 MSTPL5 MSTPL4 MSTPL3 MSTPL2 Initial value 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W MSTPL0 0 R/W Module standby L7, L5 to L2, L0 Selection bits for placing modules in standby state. Reserved bits Rev. 3.00 Sep 14, 2005 page 776 of 910 REJ09B0258-0300 0 0 R/W Appendix B Internal I/O Registers ADRCR--Address Control Register Bit H'EE01E Bus controller 7 6 5 4 3 2 1 0 ADRCTL Initial value 1 1 1 1 1 1 1 1 Read/Write R/W Reserved bits Address control Selects address update mode 1 or address update mode 2. Description ADRCTL 0 Address update mode 2 is selected 1 Address update mode 1 is selected (Initial value) Note: * This register is used only in the flash memory R version and mask ROM version. CSCR--Chip Select Control Register Bit Initial value Read/Write H'EE01F 7 6 5 4 CS7E CS6E CS5E CS4E 0 R/W 0 R/W 0 R/W 0 R/W Bus controller 3 2 1 0 1 1 1 1 Chip select 7 to 4 enable Bit n Description CSnE 0 Output of chip select signal CSn is disabled (Initial value) 1 Output of chip select signal CSn is enabled (n = 7 to 4) Rev. 3.00 Sep 14, 2005 page 777 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers ABWCR--Bus Width Control Register Bit Modes 1, 3, 5, 6, 7 Initial value Initial value Modes 2, 4 Read/Write H'EE020 Bus controller 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1 0 R/W 1 0 R/W 1 0 R/W 1 0 R/W 1 0 R/W 1 0 R/W 1 0 R/W 1 0 R/W Area 7 to 0 bus width control Bits 7 to 0 Bus Width of Access Area ABW7 to ABW0 0 Areas 7 to 0 are 16-bit access areas 1 Areas 7 to 0 are 8-bit access areas ASTCR--Access State Control Register Bit Initial value Read/Write H'EE021 Bus controller 7 6 5 4 3 2 1 0 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Area 7 to 0 access state control Bits 7 to 0 AST7 Number of States in Access Area to AST0 0 Areas 7 to 0 are two-state access areas 1 Areas 7 to 0 are three-state access areas Rev. 3.00 Sep 14, 2005 page 778 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers WCRH--Wait Control Register H Bit Initial value Read/Write H'EE022 7 6 5 4 3 2 1 0 W71 W70 W61 W60 W51 W50 W41 W40 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bus controller Area 4 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted 1 0 2 program wait states are inserted 1 3 program wait states are inserted Area 5 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted 1 0 2 program wait states are inserted 1 3 program wait states are inserted Area 6 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted 1 0 2 program wait states are inserted 1 3 program wait states are inserted Area 7 wait control 1 and 0 0 No program wait is inserted 0 1 1 program wait state is inserted 1 0 2 program wait states are inserted 1 3 program wait states are inserted Rev. 3.00 Sep 14, 2005 page 779 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers WCRL--Wait Control Register L Bit Initial value Read/Write H'EE023 Bus controller 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Area 0 wait control 1 and 0 0 1 0 No program wait is inserted 1 1 program wait state is inserted 0 2 program wait states are inserted 1 3 program wait states are inserted Area 1 wait control 1 and 0 0 1 0 No program wait is inserted 1 1 program wait state is inserted 0 2 program wait states are inserted 1 3 program wait states are inserted Area 2 wait control 1 and 0 0 1 0 No program wait is inserted 1 1 program wait state is inserted 0 2 program wait states are inserted 1 3 program wait states are inserted Area 3 wait control 1 and 0 0 1 0 No program wait is inserted 1 1 program wait state is inserted 0 2 program wait states are inserted 1 3 program wait states are inserted Rev. 3.00 Sep 14, 2005 page 780 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers BCR--Bus Control Register Bit Initial value Read/Write 7 6 ICIS1 ICIS0 1 R/W 1 R/W H'EE024 5 4 3 BROME BRSTS1 BRSTS0 0 R/W 0 R/W 0 R/W Bus controller 2 1 0 -- RDEA WAITE 1 -- 1 R/W 0 R/W Wait pin enable 0 WAIT pin wait input is disabled 1 WAIT pin wait input is enabled Area division unit select 0 1 Area divisions are as follows: Area 0: 2 MB Area 1: 2 MB Area 4: 1.93 MB Area 5: 4 kB Area 2: 8 MB Area 3: 2 MB Area 6: 23.75 kB Area 7: 22 B Areas 0 to 7 are the same size (2 MB) Burst cycle select 0 0 Max. 4 words in burst access 1 Max. 8 words in burst access Burst cycle select 1 0 Burst access cycle comprises 2 states 1 Burst access cycle comprises 3 states Burst ROM enable 0 Area 0 is a basic bus interface area 1 Area 0 is a burst ROM interface area Idle cycle insertion 0 0 No idle cycle is inserted in case of consecutive external read and write cycles 1 Idle cycle is inserted in case of consecutive external read and write cycles Idle cycle insertion 1 0 No idle cycle is inserted in case of consecutive external read cycles for different areas 1 Idle cycle is inserted in case of consecutive external read cycles for different areas Rev. 3.00 Sep 14, 2005 page 781 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers DRCRA--DRAM Control Register A Bit 7 6 H'EE026 5 4 3 DRAS2 DRAS1 DRAS0 Initial value 0 0 0 Read/Write R/W R/W R/W 2 BE 1 DRAM interface 1 0 RDM SRFMD RFSHE 0 0 0 0 R/W R/W R/W R/W Refresh pin enable 0 RFSH pin refresh signal output is disabled 1 RFSH pin refresh signal output is enabled Self-refresh mode DRAM self-refreshing is disabled in 0 software standby mode DRAM self-refreshing is enabled 1 in software standby mode RAS down mode 0 DRAM interface: RAS up mode selected 1 DRAM interface: RAS down mode selected Burst access enable 0 Burst disabled (always full access) 1 DRAM space access performed in fast page mode DRAM area select DRAS2 DRAS1 DRAS0 0 0 Area 5 Area 4 Area 3 0 Normal Normal Normal Normal 1 Normal Normal Normal DRAM space Area 2 (CS2) 1 0 Normal Normal 1 Normal Normal 0 Normal DRAM space DRAM space (CS3) 1 0 DRAM space DRAM space DRAM space (CS4) 1 0 1 (CS3) (CS2) DRAM space DRAM space DRAM space DRAM space (CS5) 1 (CS2) DRAM space(CS2)* (CS4) DRAM space(CS4)* (CS3) (CS2) DRAM space(CS2)* DRAM space(CS2)* Note: * A single CSn pin serves as a common RAS output pin for a number of areas. Unused CSn pins can be used as input/output ports. Rev. 3.00 Sep 14, 2005 page 782 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers DRCRB--DRAM Control Register B Bit 7 6 MXC1 MXC0 H'EE027 5 4 3 CSEL RCYCE Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W 1 2 1 0 TPC RCW RLW 0 0 0 R/W R/W R/W DRAM interface Refresh cycle wait control 0 Wait state (TRW) insertion is disabled 1 1 wait state (TRW) is inserted RAS-CAS wait 0 Wait state (Trw) insertion is disabled 1 1 wait state (Trw) is inserted TP cycle control 0 1-state precharge cycle is inserted 1 2-state precharge cycle is inserted Refresh cycle enable 0 Refresh cycles are disabled 1 DRAM refresh cycles are enabled CAS output pin select 0 PB4 and PB5 selected as UCAS and LCAS output pins 1 HWR and LWR selected as UCAS and LCAS output pins Multiplex control 1 and 0 MXC1 MXC0 0 0 Description Column address: 8 bits Compared address: Modes 1, 2 Modes 3, 4, 5 1 8-bit access space 16-bit access space 8-bit access space 16-bit access space Column address: 9 bits Compared address: Modes 1, 2 8-bit access space 16-bit access space 0 1 A19 to A9 A19 to A10 8-bit access space 16-bit access space A23 to A9 A23 to A10 Column address: 10 bits Compared address: Modes 1, 2 8-bit access space 16-bit access space Modes 3, 4, 5 8-bit access space 16-bit access space A19 to A10 A19 to A11 A23 to A10 A23 to A11 Modes 3, 4, 5 1 A19 to A8 A19 to A9 A23 to A8 A23 to A9 Illegal setting Rev. 3.00 Sep 14, 2005 page 783 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers RTMCSR--Refresh Timer Control/Status Register Bit H'EE028 7 6 5 4 3 CMF CMIE CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W DRAM interface 2 1 0 1 1 1 Refresh counter clock select CKS2 CKS1 0 0 1 1 0 1 Description CKS0 0 Count operation halted 1 /2 used as counter clock 0 /8 used as counter clock 1 /32 used as counter clock 0 /128 used as counter clock 1 /512 used as counter clock 0 /2048 used as counter clock 1 /4096 used as counter clock Compare match interrupt enable 0 The CMI interrupt requested by the CMF flag is disabled 1 The CMI interrupt requested by the CMF flag is enabled Compare match flag 0 [Clearing conditions] * Cleared by a reset and in standby mode * Cleared by reading CMF when CMF = 1, then writing 0 in CMF 1 [Setting condition] When RTCNT = RTCOR Note: * Only 0 can be written to clear the flag. Rev. 3.00 Sep 14, 2005 page 784 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers RTCNT--Refresh Timer Counter H'EE029 DRAM interface Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Incremented by internal clock selected by bits CKS2 to CKS0 in RTMCSR RTCOR--Refresh Time Constant Register H'EE02A DRAM interface Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W RTCNT compare match period Note: Only byte access can be used on this register. Rev. 3.00 Sep 14, 2005 page 785 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers FLMCR1--Flash Memory Control Register 1 H'EE030 Flash Memory 7 6 5 4 3 2 1 0 FWE SWE ESU PSU EV PV E P Bit Modes 1 to 4, and 6 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Modes 5 and 7 Initial value Read/Write 1/0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Program mode 0 Program mode cleared (Initial value) 1 Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase mode 0 Erase mode cleared (Initial value) 1 Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 Program-verify mode 0 Program-verify mode cleared (Initial value) 1 Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 Erase-verify mode 0 Erase-verify mode cleared (Initial value) 1 Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 Program setup 0 Program setup cleared (Initial value) 1 Program setup [Setting condition] When FWE = 1 and SWE = 1 Erase setup bit 0 Erase setup cleared (Initial value) 1 Erase setup [Setting condition] When FWE = 1 and SWE = 1 Software write enable bit 0 Write/erase disabled (Initial value) 1 Write/erase enabled [Setting condition] When FWE = 1 Flash write enable bit 0 When a low level is input to the FWE pin (hardware protection state) 1 When a high level is input to the FWE pin Note: This register is used only in the flash memory and flash memory R versions. Reading the corresponding address in a mask ROM version will always return 1s, and writes to this address are disabled. Fix the FWE pin low in mode 6. Rev. 3.00 Sep 14, 2005 page 786 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers FLMCR (FLMCR2)--Flash Memory Control Register 2 Bit H'EE031 Flash Memory 7 6 5 4 3 2 1 0 FLER -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R -- -- -- -- -- -- -- Flash memory error Reserved bits Note: Writes to FLMCR2 are prohibited. Rev. 3.00 Sep 14, 2005 page 787 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers EBR (EBR1)--Erase Block Register Bit H'EE032 Flash Memory 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Modes 1 to 4, and 6 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Modes 5 and 7 Initial value Read/Write 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Block 7 to 0 0 Block EB7 to EB0 is not selected (Initial value) 1 Block EB7 to EB0 is selected Note: When not erasing, clear EBR to H'00. Writes are invalid. A value of 1 cannot be set in this register in mode 6. Rev. 3.00 Sep 14, 2005 page 788 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers EBR (EBR2)--Erase Block Register 2 Bit H'EE033 Flash Memory 7 6 5 4 3 2 1 0 -- -- EB13 EB12 EB11 EB10 EB9 EB8 Modes 1 to 4, and 6 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Modes 5 and 7 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Block 13 to 8 0 Block EB13 to EB8 is not selected (Initial value) 1 Block EB13 to EB8 is selected Note: When not erasing, clear EBR to H'00. A value of 1 cannot be set in this register in mode 6. Rev. 3.00 Sep 14, 2005 page 789 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers P2PCR--Port 2 Input Pull-Up Control Register Bit 7 6 5 H'EE03C 4 3 2 Port 2 1 0 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port 2 input pull-up control 7 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P2DDR bit is cleared to 0 (designating generic input). Rev. 3.00 Sep 14, 2005 page 790 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers P4PCR--Port 4 Input Pull-Up Control Register Bit 7 6 5 H'EE03E 4 3 Port 4 2 1 0 P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port 4 input pull-up control 7 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P4DDR bit is cleared to 0 (designating generic input). P5PCR--Port 5 Input Pull-Up Control Register Bit 7 6 5 4 H'EE03F 3 2 Port 5 1 0 P53PCR P52PCR P51PCR P50PCR Initial value Read/Write 1 1 1 1 0 R/W 0 R/W 0 R/W 0 R/W Port 5 input pull-up control 3 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P5DDR bit is cleared to 0 (designating generic input). Rev. 3.00 Sep 14, 2005 page 791 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers RAM Control Register RAMCR Bit H'EE077 Flash Memory 7 6 5 4 3 2 1 0 -- -- -- -- RAMS RAM2 RAM1 RAM0 Modes 1 to 4 Initial value R/W 1 -- 1 -- 1 -- 1 -- 0 R 0 R 0 R 0 -- Modes 5 to 7 Initial value R/W 1 -- 1 -- 1 -- 1 -- 0 R/W* 0 R/W* 0 R/W* 0 R/W* Reserved bits RAM select, RAM2 to RAM0 Bit 3 Bit 2 Bit 1 Bit 0 RAMS RAM2 RAM1 RAM0 RAM Area RAM Emulation Status 0 0/1 0/1 0/1 H'FFE000 to H'FFEFFF Emulation 1 0 0 0 H'000000 to H'000FFF Mapping RAM 1 H'001000 to H'001FFF 0 H'002000 to H'002FFF 1 H'003000 to H'003FFF 0 H'004000 to H'004FFF 1 H'005000 to H'005FFF 0 H'006000 to H'006FFF 1 H'007000 to H'007FFF 1 1 0 1 Note: * In mode 6 (single-chip normal mode), flash memory emulation by RAM is not supported; these bits can be modified, but must not be set to 1. Note: This register is used only in the flash memory and flash memory R versions. Reading the corresponding address in a mask ROM version will always return 1s, and writes to this address are disabled. Rev. 3.00 Sep 14, 2005 page 792 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers MAR0A R/E/H/L--Memory Address Register 0A R/E/H/L Bit 31 30 29 28 27 26 25 24 Initial value Read/Write 1 1 1 1 1 1 1 1 23 H'FFF20 H'FFF21 H'FFF22 H'FFF23 22 21 Initial value Read/Write 19 18 17 16 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR0AR Bit 20 DMAC0 15 14 13 12 11 MAR0AE 10 9 8 7 6 5 Undetermined 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR0AH MAR0AL Source or destination address Rev. 3.00 Sep 14, 2005 page 793 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers ETCR0A H/L--Execute Transfer Count Register 0A H/L * H'FFF24 H'FFF25 DMAC0 Short address mode I/O mode and idle mode Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Repeat mode Bit Initial value Read/Write * 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ETCR0AH ETCR0AL Transfer counter Initial count Full address mode Normal mode 15 Bit Initial value Read/Write 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Block transfer mode Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Initial value Undetermined Undetermined Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ETCR0AH ETCR0AL Block size counter Initial block size Rev. 3.00 Sep 14, 2005 page 794 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers IOAR0A--I/O Address Register 0A Bit Initial value Read/Write H'FFF26 7 6 5 R/W R/W R/W 4 3 Undetermined R/W R/W DMAC0 2 1 0 R/W R/W R/W Short address mode : source or destination address Full address mode : not used Rev. 3.00 Sep 14, 2005 page 795 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers DTCR0A--Data Transfer Control Register 0A * H'FFF27 DMAC0 Short address mode Bit Initial value Read/Write 7 6 5 4 3 2 1 0 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 Data Transfer Activation Source Compare match/input capture A interrupt from 16-bit timer channel 0 Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 A/D converter conversion end interrupt SCI0 transmit-data-empty interrupt SCI0 receive-data-full interrupt Transfer in full address mode Transfer in full address mode Data transfer interrupt enable Interrupt requested by 0 DTE bit is disabled Interrupt requested by 1 DTE bit is enabled Repeat enable RPE DTIE Description 0 0 I/O mode 1 0 Repeat mode 1 1 Idle mode Data transfer increment/decrement 0 1 Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer If DTSZ = 1, MAR is incremented by 2 after each transfer Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer If DTSZ = 1, MAR is decremented by 2 after each transfer Data transfer size 0 1 Byte-size transfer Word-size transfer Data transfer enable 0 1 Data transfer is disabled Data transfer is enabled Rev. 3.00 Sep 14, 2005 page 796 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers DTCR0A--Data Transfer Control Register 0A (cont) * H'FFF27 DMAC0 Full address mode Bit Initial value Read/Write 7 6 5 4 3 2 1 0 DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data transfer select 0A 0 1 Normal mode Block transfer mode Data transfer select 2A and 1A Set both bits to 1 Data transfer interrupt enable 0 1 Interrupt requested by DTE bit is disabled Interrupt requested by DTE bit is enabled Source address increment/decrement (bit 5) Source address increment/decrement enable (bit 4) Bit 4 Bit 5 Increment/Decrement Enable SAID SAIDE 0 MARA is held fixed 0 Incremented: If DTSZ = 0, MARA is incremented by 1 after each transfer 1 If DTSZ = 1, MARA is incremented by 2 after each transfer 0 MARA is held fixed 1 Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer 1 If DTSZ = 1, MARA is decremented by 2 after each transfer Data transfer size 0 1 Byte-size transfer Word-size transfer Data transfer enable 0 1 Data transfer is disabled Data transfer is enabled Rev. 3.00 Sep 14, 2005 page 797 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers MAR0B R/E/H/L--Memory Address Register 0B R/E/H/L Bit 31 30 29 28 27 26 25 24 Initial value Read/Write 1 1 1 1 1 1 1 1 23 H'FFF28 H'FFF29 H'FFF2A H'FFF2B 22 21 Initial value Read/Write 19 18 17 16 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR0BR Bit 20 DMAC0 15 14 13 12 11 MAR0BE 10 9 8 7 6 5 Undetermined 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR0BH MAR0BL Source or destination address Rev. 3.00 Sep 14, 2005 page 798 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers ETCR0B H/L--Execute Transfer Count Register 0B H/L * H'FFF2C, H'FFF2D DMAC0 Short address mode I/O mode and idle mode Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Repeat mode Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Initial value Undetermined Undetermined Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ETCR0BH ETCR0BL Transfer counter Initial count * Full address mode Normal mode Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Not used Block transfer mode Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Block transfer counter Rev. 3.00 Sep 14, 2005 page 799 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers IOAR0B--I/O Address Register 0B Bit Initial value Read/Write H'FFF2E 7 6 5 R/W R/W R/W 4 3 Undetermined R/W R/W 2 1 0 R/W R/W R/W Short address mode : source or destination address Full address mode Rev. 3.00 Sep 14, 2005 page 800 of 910 REJ09B0258-0300 : not used DMAC0 Appendix B Internal I/O Registers DTCR0B--Data Transfer Control Register 0B * H'FFF2F DMAC0 Short address mode Bit Initial value Read/Write 7 6 5 4 3 2 1 0 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 Data Transfer Activation Source Compare match/input capture A interrupt from 16-bit timer channel 0 Compare match/input capture A interrupt from 16-bit timer channel 1 Compare match/input capture A interrupt from 16-bit timer channel 2 A/D converter conversion end interrupt SCI0 transmit-data-empty interrupt SCI0 receive-data-full interrupt Falling edge of DREQ input Low level of DREQ input Data transfer interrupt enable 0 1 Interrupt requested by DTE bit is disabled Interrupt requested by DTE bit is enabled Repeat enable Description RPE DTIE 0 0 I/O mode 1 0 Repeat mode 1 1 Idle mode Data transfer increment/decrement 0 1 Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer If DTSZ = 1, MAR is incremented by 2 after each transfer Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer If DTSZ = 1, MAR is decremented by 2 after each transfer Data transfer size 0 1 Byte-size transfer Word-size transfer Data transfer enable 0 1 Data transfer is disabled Data transfer is enabled Rev. 3.00 Sep 14, 2005 page 801 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers DTCR0B--Data Transfer Control Register 0B (cont) * H'FFF2F DMAC0 Full address mode 7 Bit 6 DTME Initial value Read/Write 0 R/W 0 R/W 5 4 3 2 1 0 DAID DAIDE TMS DTS2B DTS1B DTS0B 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data transfer select 2B to 0B Data transfer master enable 0 1 Bit 2 Bit 1 Bit 0 DTS2B DTS1B DTS0B Data transfer is disabled Data transfer is enabled Data Transfer Activation Source Normal Mode Block Transfer Mode Auto-request (burst mode) Compare match/input capture A interrupt from 16-bit timer channel 0 Not available Compare match/input capture A interrupt from 16-bit timer channel 1 0 Auto-request (cycle-steal mode) Compare match/input capture A interrupt from 16-bit timer channel 2 1 Not available 0 1 Not available Not available Falling edge input of DREQ Low level input at DREQ 0 0 1 0 1 0 1 1 0 1 A/D converter conversion end interrupt Not available Not available Falling edge input of DREQ Not available Transfer mode select 0 1 Destination is the block area in block transfer mode Source is the block area in block transfer mode Destination address increment/decrement (bit 5) Destination address increment/decrement enable (bit 4) Bit 5 Bit 4 Increment/Decrement Enable DAID DAIDE 0 MARB is held fixed 0 Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer 1 If DTSZ = 1, MARB is incremented by 2 after each transfer 0 MARB is held fixed 1 Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer 1 If DTSZ = 1, MARB is decremented by 2 after each transfer Rev. 3.00 Sep 14, 2005 page 802 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers MAR1A R/E/H/L--Memory Address Register 1A R/E/H/L Bit 31 30 29 28 27 26 25 24 Initial value Read/Write 1 1 1 1 1 1 1 1 23 H'FFF30 H'FFF31 H'FFF32 H'FFF33 22 21 Initial value Read/Write 19 18 17 16 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR1AR Bit 20 DMAC1 15 14 13 12 11 MAR1AE 10 9 8 7 6 5 4 Undetermined 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR1AH MAR1AL Note: Bit functions are the same as for DMAC0. ETCR1A H/L--Execute Transfer Count Register 1A H/L Bit Initial value Read/Write Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 H'FFF34 H'FFF35 6 5 4 3 DMAC1 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ETCR1AH ETCR1AL Note: Bit functions are the same as for DMAC0. Rev. 3.00 Sep 14, 2005 page 803 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers IOAR1A--I/O Address Register 1A Bit Initial value Read/Write H'FFF36 7 6 5 R/W R/W R/W 4 3 Undetermined R/W R/W DMAC1 2 1 0 R/W R/W R/W Note: Bit functions are the same as for DMAC0. DTCR1A--Data Transfer Control Register 1A * DMAC1 Short address mode Bit Initial value Read/Write * H'FFF37 7 6 5 4 3 2 1 0 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Full address mode Bit Initial value Read/Write Note: Bit functions are the same as for DMAC0. Rev. 3.00 Sep 14, 2005 page 804 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers MAR1B R/E/H/L--Memory Address Register 1B R/E/H/L Bit 31 30 29 28 27 26 25 24 Initial value Read/Write 1 1 1 1 1 1 1 1 23 H'FFF38 H'FFF39 H'FFF3A H'FFF3B 22 21 Initial value Read/Write 19 18 17 16 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W MAR1BR Bit 20 DMAC1 15 14 13 12 11 MAR1BE 10 9 8 7 6 5 4 Undetermined 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR1BH MAR1BL Note: Bit functions are the same as for DMAC0. ETCR1B H/L--Execute Transfer Count Register 1B H/L Bit Initial value Read/Write Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 H'FFF3C H'FFF3D 6 5 4 3 DMAC1 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ETCR1BH ETCR1BL Note: Bit functions are the same as for DMAC0. Rev. 3.00 Sep 14, 2005 page 805 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers IOAR1B--I/O Address Register 1B Bit Initial value Read/Write H'FFF3E 7 6 5 R/W R/W R/W 4 3 Undetermined R/W R/W DMAC1 2 1 0 R/W R/W R/W Note: Bit functions are the same as for DMAC0. DTCR1B--Data Transfer Control Register 1B * DMAC1 Short address mode Bit Initial value Read/Write * H'FFF3F 7 6 5 4 3 2 1 0 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 6 5 4 3 2 1 0 DAID DAIDE TMS DTS2B DTS1B DTS0B 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Full address mode Bit 7 DTME Initial value Read/Write 0 R/W 0 R/W Note: Bit functions are the same as for DMAC0. Rev. 3.00 Sep 14, 2005 page 806 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TSTR--Timer Start Register Bit H'FFF60 16-bit timer (all channels) 7 6 5 4 3 2 1 0 -- -- -- -- -- STR2 STR1 STR0 Initial value 1 1 1 1 1 0 0 0 Read/Write -- -- -- -- -- R/W R/W R/W Reserved bits Counter start 0 0 TCNT0 is halted 1 TCNT0 is counting (Initial value) Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting (Initial value) Counter start 2 0 TCNT2 is halted 1 TCNT2 is counting (Initial value) Rev. 3.00 Sep 14, 2005 page 807 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TSNC--Timer Synchro Register Bit H'FFF61 16-bit timer (all channels) 2 1 0 7 6 5 4 3 -- -- -- -- -- Initial value 1 1 1 1 1 0 0 0 Read/Write -- -- -- -- -- R/W R/W R/W SYNC2 SYNC1 SYNC0 Reserved bits Timer synchronization 0 0 Channel 0 timer counter (TCNT0) operates independently (TCNT0 presetting/clearing is unrelated to other channels) (Initial value) 1 Channel 0 operates synchronously TCNT0 synchronous presetting/synchronous clearing is possible Timer synchronization 1 0 Channel 1 timer counter (TCNT1) operates independently (TCNT1 presetting/clearing is unrelated to other channels) (Initial value) 1 Channel 1 operates synchronously TCNT1 synchronous presetting/synchronous clearing is possible Timer synchronization 2 0 Channel 2 timer counter (TCNT2) operates independently (TCNT2 presetting/clearing is unrelated to other channels) (Initial value) 1 Channel 2 operates synchronously TCNT2 synchronous presetting/synchronous clearing is possible Rev. 3.00 Sep 14, 2005 page 808 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TMDR--Timer Mode Register H'FFF62 16-bit timer (all channels) 7 6 5 4 3 2 1 0 -- MDF FDIR -- -- PWM2 PWM1 PWM0 Initial value 1 0 0 1 1 0 0 0 Read/Write -- R/W R/W -- -- R/W R/W R/W Bit PWM mode 0 0 Channel 0 operates normally (Initial value) 1 Channel 0 operates in PWM mode PWM mode 1 0 Channel 1 operates normally (Initial value) 1 Channel 1 operates in PWM mode PWM mode 2 0 Channel 2 operates normally (Initial value) 1 Channel 2 operates in PWM mode Flag direction 0 1 OVF is set to 1 in TISRC when TCNT2 overflows or underflows (Initial value) OVF is set to 1 in TISRC when TCNT2 overflows Phase counting mode flag 0 Channel 2 operates normally (Initial value) 1 Channel 2 operates in phase counting mode Rev. 3.00 Sep 14, 2005 page 809 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TOLR--Timer Output Level Setting Register H'FFF63 16-bit timer (all channels) 7 6 5 4 3 2 1 0 -- -- TOB2 TOA2 TOB1 TOA1 TOB0 TOA0 Initial value 1 1 0 0 0 0 0 0 Read/Write -- -- W W W W W W Bit Output level setting A0 0 TIOCA0 is 0 1 TIOCA0 is 1 (Initial value) Output level setting B0 0 TIOCB0 is 0 1 TIOCB0 is 1 (Initial value) Output level setting A1 0 TIOCA1 is 0 1 TIOCA1 is 1 (Initial value) Output level setting B1 0 TIOCB1 is 0 1 TIOCB1 is 1 (Initial value) Output level setting A2 0 TIOCA2 is 0 1 TIOCA2 is 1 (Initial value) Output level setting B2 0 TIOCB2 is 0 1 TIOCB2 is 1 Rev. 3.00 Sep 14, 2005 page 810 of 910 REJ09B0258-0300 (Initial value) Appendix B Internal I/O Registers TISRA--Timer Interrupt Status Register A Bit: 7 -- 6 H'FFF64 5 4 IMIEA2 IMIEA1 IMIEA0 3 16-bit timer (all channels) 2 1 0 -- IMFA2 IMFA1 IMFA0 0 0 0 R/(W)* R/(W)* R/(W)* Initial value: 1 0 0 0 1 Read/Write: -- R/W R/W R/W -- Input capture/compare match flag A0 [Clearing conditions] 0 (Initial value) Read IMFA0 when IMFA0=1, then write 0 in IMFA0 DMAC activated by IMIA0 interrupt. [Setting conditions] TCNT0=GRA0 when GRA0 functions as an output compare register. 1 TCNT0 value is transferred to GRA0 by an input capture signal when GRA0 functions as an input capture register. Input capture/compare match flag A1 [Clearing conditions] 0 (Initial value) Read IMFA1 when IMFA1=1, then write 0 in IMFA1 DMAC activated by IMIA1 interrupt. [Setting conditions] TCNT1=GRA1 when GRA1 functions as an output compare register. 1 TCNT1 value is transferred to GRA1 by an input capture signal when GRA1 functions as an input capture register. Input capture/compare match flag A2 [Clearing conditions] 0 (Initial value) Read IMFA2 when IMFA2=1, then write 0 in IMFA2 DMAC activated by IMIA2 interrupt. [Setting conditions] TCNT2=GRA2 when GRA2 functions as an output compare register. 1 TCNT2 value is transferred to GRA2 by an input capture signal when GRA2 functions as an input capture register. Input capture/compare match interrupt enable A0 0 IMIA0 interrupt requested by IMFA0 flag is disabled 1 Input capture/compare match interrupt enable A1 0 IMIA1 interrupt requested by IMFA1 flag is disabled 1 (Initial value) IMIA1 interrupt requested by IMFA1 is enabled Input capture/compare match interrupt enable A2 0 IMIA2 interrupt requested by IMFA2 flag is disabled 1 (Initial value) IMIA0 interrupt requested by IMFA0 is enabled (Initial value) IMIA2 interrupt requested by IMFA2 is enabled Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Sep 14, 2005 page 811 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TISRB--Timer Interrupt Status Register B Bit: 7 -- 6 H'FFF65 5 4 IMIEB2 IMIEB1 IMIEB0 3 16-bit timer (all channels) 2 1 0 -- IMFB2 IMFB1 IMFB0 0 0 0 R/(W)* R/(W)* R/(W)* Initial value: 1 0 0 0 1 Read/Write: -- R/W R/W R/W -- Input capture/compare match flag B0 0 [Clearing condition] (Initial value) Read IMFB0 when IMFB0=1, then write 0 in IMFB0. [Setting conditions] TCNT0=GRB0 when GRB0 functions as an output compare register. 1 TCNT0 value is transferred to GRB0 by an input capture signal when GRB0 functions as an input capture register. Input capture/compare match flag B1 0 [Clearing condition] (Initial value) Read IMFB1 when IMFB1=1, then write 0 in IMFB1. [Setting conditions] TCNT1=GRB1 when GRB1 functions as an output compare register. 1 TCNT1 value is transferred to GRB1 by an input capture signal when GRB1 functions as an input capture register. Input capture/compare match flag B2 0 [Clearing condition] (Initial value) Read IMFB2 when IMFB2=1, then write 0 in IMFB2. [Setting conditions] TCNT2=GRB2 when GRB2 functions as an output compare register. 1 TCNT2 value is transferred to GRB2 by an input capture signal when GRB2 functions as an input capture register. Input capture/compare match interrupt enable B0 0 IMIB0 interrupt requested by IMFB0 flag is disabled 1 Input capture/compare match interrupt enable B1 0 IMIB1 interrupt requested by IMFB1 flag is disabled 1 (Initial value) IMIB1 interrupt requested by IMFB1 is enabled Input capture/compare match interrupt enable B2 0 IMIB2 interrupt requested by IMFB2 flag is disabled 1 (Initial value) IMIB0 interrupt requested by IMFB0 is enabled IMIB2 interrupt requested by IMFB2 is enabled Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Sep 14, 2005 page 812 of 910 REJ09B0258-0300 (Initial value) Appendix B Internal I/O Registers TISRC--Timer Interrupt Status Register C 7 Bit: -- 6 5 H'FFF66 4 OVIE2 OVIE1 OVIE0 3 16-bit timer (all channels) 2 1 0 -- OVF2 OVF1 OVF0 0 0 0 R/(W)* R/(W)* R/(W)* Initial value: 1 0 0 0 1 Read/Write: -- R/W R/W R/W -- Overflow flag 0 0 1 [Clearing condition] (Initial value) Read OVF0 when OVF0 = 1, then write 0 in OVF0. [Setting condition] TCNT0 overflowed from H'FFFF to H'0000. Overflow flag 1 0 [Clearing condition] Read OVF1 when OVF1 = 1, then write 0 in OVF1. 1 [Setting condition] TCNT1 overflowed from H'FFFF to H'0000. (Initial value) Overflow flag 2 0 [Clearing condition] Read OVF2 when OVF2 = 1, then write 0 in OVF2. 1 [Setting condition] TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF. Overflow interrupt enable 0 OVI0 interrupt requested by OVF0 flag is disabled 0 1 (Initial value) OVI1 interrupt requested by OVF1 flag is enabled Overflow interrupt enable 2 OVI2 interrupt requested by OVF2 flag is disabled 0 1 (Initial value) OVI0 interrupt requested by OVF0 flag is enabled Overflow interrupt enable 1 OVI1 interrupt requested by OVF1 flag is disabled 0 1 (Initial value) (Initial value) OVI2 interrupt requested by OVF2 flag is enabled Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Sep 14, 2005 page 813 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCR0--Timer Control Register Bit Initial value Read/Write H'FFF68 7 -- 6 5 4 3 2 1 0 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Timer prescaler 2 to 0 Bit 1 Bit 0 Bit 2 TPSC2 TPSC1 0 1 0 1 1 Clock edge 1 and 0 Bit 4 Bit 3 CKEG1 CKEG0 0 0 1 0 1 -- Rising edges counted Falling edges counted Both edges counted 1 1 (Initial value) TCNT clear Sources CCLR0 0 1 0 Internal clock : Internal clock : / 2 Internal clock : / 4 Internal clock : / 8 External clock A : TCLKA input External clock B : TCLKB input External clock C : TCLKC input External clock D : TCLKD input 0 1 0 1 0 1 0 1 Counted Edges of External Clock Counter clear 1 and 0 Bit 6 Bit 5 0 TCNT Clock Source TPSC0 0 CCLR1 16-bit timer channel 0 (Initial value) TCNT is not cleared TCNT is cleared by GRA compare match or input capture TCNT is cleared by GRB compare match or input capture Synchronous clear : TCNT is cleared in synchronization with other synchronized timers Rev. 3.00 Sep 14, 2005 page 814 of 910 REJ09B0258-0300 (Initial value) Appendix B Internal I/O Registers TIOR0--Timer I/O Control Register 0 Bit: H'FFF69 16-bit timer channel 0 7 6 5 4 3 2 1 0 IOA0 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 Initial value: 1 0 0 0 1 0 0 0 Read/Write: -- R/W R/W R/W -- R/W R/W R/W I/O control A2 to A0 Bit 2 Bit 1 IOA2 IOA1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 1 GRA Functions GRA is an output compare register 1 0 I/O control B2 to B0 Bit 6 Bit 5 IOB2 IOB1 Bit 0 IOA0 0 1 0 Bit 4 IOB0 0 1 0 GRA is an input capture register (Initial value) 0 output at GRA compare match 1 output at GRA compare match Output toggles at GRA compare match (channel 2 only: 1 output) GRA captures rising edges of input GRA captures falling edges of input GRA captures both edges of input GRB Functions GRB is an output compare register 1 0 1 0 1 No output at compare match GRB is an input capture register No output at compare match (Initial value) 0 output at GRB compare match 1 output at GRB compare match Output toggles at GRB compare match (channel 2 only: 1 output) GRB captures rising edges of input GRB captures falling edges of input GRB captures both edges of input Rev. 3.00 Sep 14, 2005 page 815 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCNT0 H/L--Timer Counter 0 H/L Bit Initial value Read/Write 15 14 13 12 11 H'FFF6A, H'FFF6B 10 9 8 7 6 5 16-bit timer channel 0 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up - counter GRA0 H/L--General Register A0 H/L Bit Initial value Read/Write 15 14 13 12 11 H'FFF6C, H'FFF6D 10 9 8 7 6 5 16-bit timer channel 0 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register GRB0 H/L--General Register B0 H/L Bit Initial value Read/Write 15 14 13 12 11 H'FFF6E, H'FFF6F 10 9 8 7 6 5 16-bit timer channel 0 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register Rev. 3.00 Sep 14, 2005 page 816 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCR1 Timer Control Register 1 7 Bit H'FFF70 6 -- 5 4 16-bit timer channel 1 3 2 1 0 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value 1 0 0 0 0 0 0 0 Read/Write -- R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for 16-bit timer channel 0. TIOR1--Timer I/O Control Register 1 H'FFF71 16-bit timer channel 1 7 6 5 4 3 2 1 0 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 Initial value 1 0 0 0 1 0 0 0 Read/Write -- R/W R/W R/W -- R/W R/W R/W Bit Note: Bit functions are the same as for 16-bit timer channel 0. TCNT1 H/L--Timer Counter 1 H/L Bit Initial value Read/Write 15 14 13 12 11 H'FFF72, H'FFF73 10 9 8 7 6 5 16-bit timer channel 1 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for 16-bit timer channel 0. Rev. 3.00 Sep 14, 2005 page 817 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers GRA1 H/L--General Register A1 H/L Bit Initial value Read/Write 15 14 13 12 H'FFF74, H'FFF75 11 10 9 8 7 6 5 16-bit timer channel 1 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for 16-bit timer channel 0. GRB1 H/L--General Register B1 H/L Bit Initial value Read/Write 15 14 13 12 11 H'FFF76, H'FFF77 10 9 8 7 6 5 16-bit timer channel 1 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for 16-bit timer channel 0. TCR2 Timer Control Register 2 Bit 7 -- 6 H'FFF78 5 4 3 16-bit timer channel 2 2 1 0 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value 1 0 0 0 0 0 0 0 Read/Write -- R/W R/W R/W R/W R/W R/W R/W Notes: 1. Bit functions are the same as for 16-bit timer channel 0. 2. When phase counting mode is selected in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in TCR2 are ignored. Rev. 3.00 Sep 14, 2005 page 818 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TIOR2--Timer I/O Control Register 2 H'FFF79 16-bit timer channel 2 7 6 5 4 3 2 1 0 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 Initial value 1 0 0 0 1 0 0 0 Read/Write -- R/W R/W R/W -- R/W R/W R/W Bit Note: Bit functions are the same as for 16-bit timer channel 0. TCNT2 H/L--Timer Counter 2 H/L Bit Initial value Read/Write 15 14 13 12 11 H'FFF7A, H'FFF7B 10 9 8 GRA2 H/L--General Register A2 H/L Initial value Read/Write 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Phase counting mode : Other mode : Bit 7 16-bit timer channel 2 15 14 13 12 11 up / down counter up - counter H'FFF7C, H'FFF7D 10 9 8 7 6 5 16-bit timer channel 2 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for 16-bit timer channel 0. Rev. 3.00 Sep 14, 2005 page 819 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers GRB2 H/L--General Register B2 H/L Bit Initial value Read/Write 15 1 H'FFF7E, H'FFF7F 16-bit timer channel 2 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for 16-bit timer channel 0. Rev. 3.00 Sep 14, 2005 page 820 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCR0--Timer Control Register 0 TCR1--Timer Control Register 1 Bit Initial value Read/Write H'FFF80 H'FFF81 8-bit timer channel 0 8-bit timer channel 1 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Clock select 2 to 0 0 0 0 Clock input is disabled 1 Internal clock, counted on rising edge of /8 0 Internal clock, counted on rising edge of /64 1 Internal clock, counted on rising edge of /8192 0 Channel 0: Count on TCNT1 overflow signal* Channel 1: Count on TCNT0 compare match A* 1 External clock, counted on falling edge 0 External clock, counted on rising edge 1 External clock, counted on both rising and falling edges 1 0 1 1 Notes: * If the clock input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Counter clear 1 and 0 0 1 0 Clearing is disabled 1 Cleared by compare match A 0 Cleared by compare match B/input capture B 1 Cleared by input capture B Timer overflow interrupt enable 0 OVI interrupt requested by OVF is disabled 1 OVI interrupt requested by OVF is enabled Compare match interrupt enable A 0 CMIA interrupt requested by CMFA is disabled 1 CMIA interrupt requested by CMFA is enabled Compare match interrupt enable B 0 CMIB interrupt requested by CMFB is disabled 1 CMIB interrupt requested by CMFB is enabled Rev. 3.00 Sep 14, 2005 page 821 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCSR0--Timer Control/Status Register 0 Bit Initial value Read/Write H'FFF82 8-bit timer channel 0 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE OIS3 OIS2 OS1 OS0 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Output select A1 and A0 Bit 1 Bit 0 Description OS1 0 OS0 0 No change at compare match A 1 0 output at compare match A 0 1 output at compare match A 1 Output toggles at compare match A 1 Output/input capture edge select B3 and B2 ICE in Bit 3 Bit 2 TCSR1 OIS3 OIS2 0 0 No change at compare match B 1 0 output at compare match B 0 1 output at compare match B 1 1 0 0 1 1 1 Description 0 0 1 Output toggles at compare match B TCORB input capture on rising edge TCORB input capture on falling edge TCORB input capture on both rising and falling edges A/D trigger enable (TCSR0 only) TRGE* Bit 4 Description ADTE 0 0 1 A/D converter start requests by compare match A or an external trigger are disabled A/D converter start requests by compare match A or an external trigger are enabled A/D converter start requests by an external trigger are enabled A/D converter start requests by compare match A are enabled 0 1 Note: * TRGE is bit 7 of the A/D control register (ADCR). 1 Timer overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF. 1 [Setting condition] TCNT overflows from H'FF to H'00. Compare match flag A 0 [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA. 1 [Setting condition] TCNT = TCORA Compare match/input capture flag B 0 [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB. 1 [Setting conditions] TCNT = TCORB The TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register. Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Rev. 3.00 Sep 14, 2005 page 822 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCSR1--Timer Control/Status Register 1 Bit Initial value Read/Write H'FFF83 8-bit timer channel 1 7 6 5 4 3 2 1 0 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Output select A1 and A0 Bit 1 Bit 0 Description OS1 0 OS0 0 No change at compare match A 1 0 output at compare match A 0 1 output at compare match A 1 1 Output toggles at compare match A Output/input capture edge select B3 and B2 ICE in Bit 3 TCSR1 OIS3 0 0 Bit 2 0 No change at compare match B 1 0 output at compare match B 0 1 output at compare match B 1 Output toggles at compare match B 1 0 0 1 1 1 Description OIS2 0 1 TCORB input capture on rising edge TCORB input capture on falling edge TCORB input capture on both rising and falling edges Input capture enable 0 TCORB is a compare match register 1 TCORB is an input capture register Timer overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF. 1 [Setting condition] TCNT overflows from H'FF to H'00. Compare match/input capture flag A 0 [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA. 1 [Setting condition] TCNT = TCORA Compare match/input capture flag B 0 [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB. 1 [Setting conditions] TCNT = TCORB The TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register. Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Rev. 3.00 Sep 14, 2005 page 823 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCORA0--Time Constant Register A0 TCORA1--Time Constant Register A1 H'FFF84 H'FFF85 8-bit timer channel 0 8-bit timer channel 1 TCORA0 Bit Initial value Read/Write 15 1 TCORA1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0--Time Constant Register B0 TCORB1--Time Constant Register B1 H'FFF86 H'FFF87 8-bit timer channel 0 8-bit timer channel 1 TCORB0 Bit Initial value Read/Write 15 14 13 12 11 TCORB1 10 9 8 7 6 5 H'FFF88 H'FFF89 2 1 0 8-bit timer channel 0 8-bit timer channel 1 TCNT0 Initial value Read/Write 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0--Timer Counter 0 TCNT1--Timer Counter 1 Bit 4 15 14 13 12 11 TCNT1 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.00 Sep 14, 2005 page 824 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCSR--Timer Control/Status Register 7 6 5 OVF WT/IT TME 0 R/(W)* 0 R/W 0 R/W Bit Initial value Read/Write H'FFF8C 4 2 1 0 CKS2 CKS1 CKS0 0 R/W 0 R/W 0 R/W 3 1 1 WDT Clock select 2 to 0 CKS2 CKS1 CKS0 0 0 1 0 1 1 Description 0 /2 1 /32 0 /64 1 /128 0 /256 1 /512 0 /2048 1 /4096 Timer enable Timer disabled 0 * TCNT is initialized to H'00 and halted Timer enabled 1 * TCNT is counting Timer mode select 0 Interval timer: requests interval timer interrupts 1 Watchdog timer: generates a reset signal Overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] TCNT changes from H'FF to H'00 Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Sep 14, 2005 page 825 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCNT--Timer Counter Bit Initial value Read/Write H'FFF8D (read), H'FFF8C (write) WDT 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Count value RSTCSR--Reset Control/Status Register Bit Initial value Read/Write 7 6 WRST RSTOE 0 R/(W)* 0 R/W H'FFF8F (read), H'FFF8E (write) 5 4 3 2 1 0 1 1 1 1 1 1 Reset output enable 0 External output of reset signal is disabled 1 External output of reset signal is enabled Watchdog timer reset 0 [Clearing conditions] Reset signal at RES pin Read WRST when WRST = 1, then write 0 in WRST [Setting condition] 1 WDT TCNT overflow generates a reset signal Note: * Only 0 can be written in bit 7, to clear the flag. Rev. 3.00 Sep 14, 2005 page 826 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCR2--Timer Control Register 2 TCR3--Timer Control Register 3 Bit Initial value Read/Write H'FFF90 H'FFF91 8-bit timer channel 2 8-bit timer channel 3 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Clock select 2 to 0 CSK2 CSK1 CSK0 Clock input is disabled 1 Internal clock, counted on rising edge of /8 0 Internal clock, counted on rising edge of /64 1 Internal clock, counted on rising edge of /8192 0 Channel 2: Count on TCNT3 overflow signal* Channel 3: Count on TCNT2 compare match A* 1 External clock, counted on falling edge 0 External clock, counted on rising edge 1 External clock, counted on both rising and falling edges 0 0 1 0 1 Description 0 1 Note: * If the clock input of channel 2 is the TCNT3 overflow signal and that of channel 3 is the TCNT2 compare match signal, no incrementing clock is generated. Do not use this setting. Counter clear 1 and 0 0 1 0 Clearing is disabled 1 Cleared by compare match A 0 Cleared by compare match B/input capture B 1 Cleared by input capture B Timer overflow interrupt enable 0 OVI interrupt requested by OVF is disabled 1 OVI interrupt requested by OVF is enabled Compare match interrupt enable A 0 CMIA interrupt requested by CMFA is disabled 1 CMIA interrupt requested by CMFA is enabled Compare match interrupt enable B 0 CMIB interrupt requested by CMFB is disabled 1 CMIB interrupt requested by CMFB is enabled Rev. 3.00 Sep 14, 2005 page 827 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCSR2--Timer Control/Status Register 2 TCSR3--Timer Control/Status Register 3 TCSR2 Bit Initial value Read/Write TCSR3 Bit Initial value Read/Write 7 6 5 CMFB CMFA OVF 0 R/(W)* 0 R/(W)* 0 R/(W)* H'FFF92 H'FFF93 4 1 8-bit timer channel 2 8-bit timer channel 3 3 2 1 0 OIS3 OIS2 OS1 OS0 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 CMFB CMFA OVF ICE OIS3 OIS2 OS1 OS0 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Output select A1 and A0 Bit 1 Bit 0 Description OS1 OS0 0 0 No change at compare match A 1 0 output at compare match A 0 1 output at compare match A 1 Output toggles at compare match A 1 Output/input capture edge select B3 and B2 ICE in Bit 3 TCSR3 OIS3 0 0 Bit 3 0 No change at compare match B 1 0 output at compare match B 0 1 output at compare match B 1 1 0 0 1 1 Description OIS2 Output toggles at compare match B TCORB input capture on rising edge 1 TCORB input capture on falling edge 0 TCORB input capture on both rising and falling edges Input capture enable (TCSR3 only) 0 TCORB is a compare match register 1 TCORB is an input capture register Timer overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF. 1 [Setting condition] TCNT overflows from H'FF to H'00. Compare match/input capture flag A 0 1 [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA. [Setting condition] TCNT = TCORA Compare match/input capture flag B 0 [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB. 1 [Setting conditions] TCNT = TCORB The TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register. Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Rev. 3.00 Sep 14, 2005 page 828 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TCORA2--Time Constant Register A2 TCORA3--Time Constant Register A3 H'FFF94 H'FFF95 8-bit timer channel 2 8-bit timer channel 3 TCORA2 Bit Initial value Read/Write 15 1 TCORA3 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB2--Time Constant Register B2 TCORB3--Time Constant Register B3 H'FFF96 H'FFF97 8-bit timer channel 2 8-bit timer channel 3 TCORB2 Bit Initial value Read/Write 15 14 13 12 11 TCORB3 10 9 8 7 6 5 H'FFF98 H'FFF99 2 1 0 8-bit timer channel 2 8-bit timer channel 3 TCNT2 Initial value Read/Write 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT2--Timer Counter 2 TCNT3--Timer Counter 3 Bit 4 15 14 13 12 11 TCNT3 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.00 Sep 14, 2005 page 829 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers DADR0--D/A Data Register 0 Bit Initial value Read/Write H'FFF9C D/A 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W D/A conversion data DADR1--D/A Data Register 1 Bit Initial value Read/Write H'FFF9D D/A 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W D/A conversion data Rev. 3.00 Sep 14, 2005 page 830 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers DACR--D/A Control Register 7 6 5 DAOE1 DAOE0 DAE 0 R/W 0 R/W 0 R/W Bit Initial value Read/Write H'FFF9E D/A 4 3 2 1 0 1 1 1 1 1 D/A enable Bit 7 Bit 6 Bit 5 DAOE1 DAOE0 DAE 0 0 Description D/A conversion is disabled in channels 0 and 1 D/A conversion is enabled in channel 0 0 1 0 D/A conversion is disabled in channel 1 0 1 1 1 0 0 D/A conversion is enabled in channels 0 and 1 D/A conversion is disabled in channel 0 D/A conversion is enabled in channel 1 1 0 1 1 1 D/A conversion is enabled in channels 0 and 1 D/A conversion is enabled in channels 0 and 1 D/A output enable 0 0 DA0 analog output is disabled 1 Channel-0 D/A conversion and DA0 analog output are enabled D/A output enable 1 0 DA1 analog output is disabled 1 Channel-1 D/A conversion and DA1 analog output are enabled Rev. 3.00 Sep 14, 2005 page 831 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TPMR--TPC Output Mode Register Bit Initial value Read/Write 7 1 6 1 5 1 4 1 H'FFFA0 3 2 1 0 G3NOV G2NOV G1NOV G0NOV 0 R/W 0 R/W 0 R/W 0 R/W TPC Group 0 non-overlap 0 Normal TPC output in group 0. Output values change at compare match A in the selected 16-bit timer channel 1 Non-overlapping TPC output in group 0, controlled by compare match A and B in the selected 16-bit timer channel Group 1 non-overlap 0 Normal TPC output in group 1. Output values change at compare match A in the selected 16-bit timer channel 1 Non-overlapping TPC output in group 1, controlled by compare match A and B in the selected 16-bit timer channel Group 2 non-overlap 0 Normal TPC output in group 2. Output values change at compare match A in the selected 16-bit timer channel 1 Non-overlapping TPC output in group 2, controlled by compare match A and B in the selected 16-bit timer channel Group 3 non-overlap Rev. 3.00 Sep 14, 2005 page 832 of 910 REJ09B0258-0300 0 Normal TPC output in group 3. Output values change at compare match A in the selected 16-bit timer channel 1 Non-overlapping TPC output in group 3, controlled by compare match A and B in the selected 16-bit timer channel Appendix B Internal I/O Registers TPCR--TPC Output Control Register Bit Initial value Read/Write H'FFFA1 7 6 5 4 3 2 1 0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TPC Group 0 compare match select 1 and 0 Bit 1 Bit 0 16-Bit Timer Channel Selected as Output Trigger G0CMS1 G0CMS0 0 0 1 1 0 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit timer channel 2 Group 1 compare match select 1 and 0 Bit 3 Bit 2 G1CMS1 G1CMS0 0 0 1 1 0 1 16-Bit Timer Channel Selected as Output Trigger TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 1 TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit timer channel 2 Group 2 compare match select 1 and 0 Bit 5 Bit 4 16-Bit Timer Channel Selected as Output Trigger G2CMS1 G2CMS0 0 1 0 1 0 1 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 1 TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 2 Group 3 compare match select 1 and 0 Bit 7 Bit 6 G3CMS1 G3CMS0 0 1 0 1 0 1 16-Bit Timer Channel Selected as Output Trigger TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 1 TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 2 Rev. 3.00 Sep 14, 2005 page 833 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers NDERB--Next Data Enable Register B Bit Initial value Read/Write H'FFFA2 TPC 7 6 5 4 3 2 1 0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Next data enable 15 to 8 Bits 7 to 0 Description NDER15 to NDER8 0 TPC outputs TP15 to TP8 are disabled (NDR15 to NDR8 are not transferred to PB7 to PB0) 1 TPC outputs TP15 to TP8 are enabled (NDR15 to NDR8 are transferred to PB7 to PB0) NDERA--Next Data Enable Register A Bit Initial value Read/Write H'FFFA3 TPC 7 6 5 4 3 2 1 0 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Next data enable 7 to 0 Bits 7 to 0 Description NDER7 to NDER0 TPC outputs TP7 to TP0 are disabled 0 1 (NDR7 to NDR0 are not transferred to PA7 to PA0) TPC outputs TP7 to TP0 are enabled (NDR7 to NDR0 are transferred to PA7 to PA0) Rev. 3.00 Sep 14, 2005 page 834 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers NDRB--Next Data Register B * H'FFFA4/H'FFFA6 TPC Same trigger for TPC output groups 2 and 3 Address H'FFFA4 Bit Initial value Read/Write 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Store the next output data for TPC output group 3 Store the next output data for TPC output group 2 Address H'FFFA6 * Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 3 2 1 0 1 1 1 1 Different triggers for TPC output groups 2 and 3 Address H'FFFA4 7 6 5 4 NDR15 NDR14 NDR13 NDR12 0 R/W 0 R/W 0 R/W 0 R/W Bit Initial value Read/Write Store the next output data for TPC output group 3 Address H'FFFA6 Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 2 1 0 NDR11 NDR10 NDR9 NDR8 0 R/W 0 R/W 0 R/W 0 R/W Store the next output data for TPC output group 2 Rev. 3.00 Sep 14, 2005 page 835 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers NDRA--Next Data Register A * H'FFFA5/H'FFFA7 TPC Same trigger for TPC output groups 0 and 1 Address H'FFFA5 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Initial value Read/Write Store the next output data for TPC output group 1 Store the next output data for TPC output group 0 Address H'FFFA7 * Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 3 2 1 0 1 1 1 1 Different triggers for TPC output groups 0 and 1 Address H'FFFA5 7 6 5 4 NDR7 NDR6 NDR5 NDR4 0 R/W 0 R/W 0 R/W 0 R/W Bit Initial value Read/Write Store the next output data for TPC output group 1 Address H'FFFA7 Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 2 1 0 NDR3 NDR2 NDR1 NDR0 0 R/W 0 R/W 0 R/W 0 R/W Store the next output data for TPC output group 0 Rev. 3.00 Sep 14, 2005 page 836 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers SMR--Serial Mode Register SCI0 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Initial value Read/Write H'FFFB0 Clock select 1 and 0 Bit 1 Bit 0 CKS1 CKS0 0 1 Clock Source 0 clock 1 /4 clock 0 /16 clock 1 /64 clock Multiprocessor mode 0 1 Multiprocessor function disabled Multiprocessor format selected Stop bit length 0 One stop bit 1 Two stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit is not added or checked 1 Parity bit is added and checked Character length 0 8-bit data 1 7-bit data Communication mode (for serial communication interface) 0 Asynchronous mode 1 Synchronous mode GSM mode (for smart card interface) 0 TEND flag is set 12.5 etu* after start bit 1 TEND flag is set 11.0 etu* after start bit Note: * etu (Elementary time unit: the time for transfer of one bit) Rev. 3.00 Sep 14, 2005 page 837 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers BRR--Bit Rate Register Bit Initial value Read/Write H'FFFB1 SCI0 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Serial communication bit rate setting Rev. 3.00 Sep 14, 2005 page 838 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers SCR--Serial Control Register Bit Initial value Read/Write H'FFFB2 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Clock enable 1 and 0 (for serial communication interface) Bit 1 Bit 0 Description CKE1 CKE0 Internal clock, SCK pin Asynchronous mode available for generic I/O 0 Internal clock, SCK pin Synchronous mode used for serial clock output 0 Internal clock, SCK pin Asynchronous mode used for clock output 1 Internal clock, SCK pin Synchronous mode used for serial clock output External clock, SCK pin Asynchronous mode used for clock input 0 External clock, SCK pin Synchronous mode used for serial clock input 1 External clock, SCK pin Asynchronous mode used for clock input 1 External clock, SCK pin Synchronous mode used for serial clock input Receive enable 0 1 Receiving is disabled Receiving is enabled Transmit enable 0 Transmitting is disabled 1 Transmitting is enabled SCI0 Clock enable 1 and 0 (for smart card interface) SMR Bit 1 Bit 0 Description GM CKE1 CKE0 SCK pin available for generic I/O 0 0 0 SCK pin used for clock output 1 SCK pin output fixed low 0 0 SCK pin used for clock output 1 1 SCK pin output fixed high 0 1 SCK pin used for clock output 1 Transmit-end interrupt enable 0 1 Transmit-end interrupt requests (TEI) are disabled Transmit-end interrupt requests (TEI) are enabled Multiprocessor interrupt enable 0 1 Multiprocessor interrupts are disabled (normal receive operation) Multiprocessor interrupts are enabled Receive interrupt enable 0 1 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled Transmit interrupt enable 0 1 Transmit-data-empty interrupt request (TXI) is disabled Transmit-data-empty interrupt request (TXI) is enabled Rev. 3.00 Sep 14, 2005 page 839 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TDR--Transmit Data Register Bit Initial value Read/Write H'FFFB3 SCI0 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Serial transmit data Rev. 3.00 Sep 14, 2005 page 840 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers SSR--Serial Status Register 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER/ERS PER TEND MPB MPBT 1 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 1 R 0 R 0 R/W Bit Initial value Read/Write H'FFFB4 SCI0 Multiprocessor bit transfer 0 Multiprocessor bit value in transmit data is 0 1 Multiprocessor bit value in transmit data is 1 Multiprocessor bit 0 1 Multiprocessor bit value in receive data is 0 Multiprocessor bit value in receive data is 1 Transmit end (for serial communication interface) 0 [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE. The DMAC writes data in TDR. 1 [Setting conditions] Reset or transition to standby mode TE is cleared to 0 in SCR. TDRE is 1 when last bit of 1-byte serial character is transmitted. Transmit end (for smart card interface) 0 [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE. The DMAC writes data in TDR. 1 [Setting conditions] Reset or transition to standby mode TE is cleared to 0 in SCR and FER/ERS is cleared to 0. TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu* (when GM = 0) or 1.0 etu (when GM = 1) after 1-byte serial character is transmitted. Note: * etu (Elementary time unit: the time for transfer of one bit) Parity error 0 1 [Clearing conditions] Reset or transition to standby mode Read PER when PER = 1, then write 0 in PER. [Setting condition] Parity error (parity of receive data does not match parity setting of O/E bit in SMR) Framing error (for serial communication interface) 0 1 [Clearing conditions] Reset or transition to standby mode Read FER when FER = 1, then write 0 in FER. [Setting condition] Framing error (stop bit is 0) Error signal status (for smart card interface) 0 1 [Clearing conditions] Reset or transition to standby mode Read ERS when ERS = 1, then write 0 in ERS. [Setting condition] A low error signal is received. Overrun error 0 [Clearing conditions] Reset or transition to standby mode Read ORER when ORER = 1, then write 0 in ORER. 1 [Setting condition] Overrun error (reception of the next serial data ends when RDRF = 1) Receive data register full 0 1 [Clearing conditions] Reset or transition to standby mode Read RDRF when RDRF = 1, then write 0 in RDRF. The DMAC reads data from RDR. [Setting condition] Serial data is received normally and transferred from RSR to RDR. Transmit data register empty 0 1 [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE. The DMAC writes data in TDR. [Setting conditions] Reset or transition to standby mode TE is 0 in SCR. Data is transferred from TDR to TSR, enabling new data to be written in TDR Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Sep 14, 2005 page 841 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers RDR--Receive Data Register H'FFFB5 SCI0 Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Serial receive data SCMR--Smart Card Mode Register Bit Initial value Read/Write 7 1 6 1 5 1 H'FFFB6 4 1 3 2 SDIR SINV 1 0 R/W 0 R/W SCI0 0 SMIF 1 0 R/W Smart card interface mode select 0 Smart card interface function is disabled 1 Smart card interface function is enabled (Initial value) Smart card data invert Unmodified TDR contents are transmitted 0 1 (Initial value) Receive data is stored unmodified in RDR Inverted 1/0 logic levels of TDR contents are transmitted 1/0 logic levels of received data are inverted before storage in RDR Smart card data transfer direction TDR contents are transmitted LSB-first 0 1 Rev. 3.00 Sep 14, 2005 page 842 of 910 REJ09B0258-0300 Receive data is stored LSB-first in RDR TDR contents are transmitted MSB-first Receive data is stored MSB-first in RDR (Initial value) Appendix B Internal I/O Registers SMR--Serial Mode Register Bit Initial value Read/Write H'FFFB8 SCI1 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: Bit functions are the same as for SCI0. BRR--Bit Rate Register Bit Initial value Read/Write H'FFFB9 SCI1 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Note: Bit functions are the same as for SCI0. SCR--Serial Control Register Bit Initial value Read/Write H'FFFBA SCI1 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: Bit functions are the same as for SCI0. Rev. 3.00 Sep 14, 2005 page 843 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers TDR--Transmit Data Register Bit Initial value Read/Write H'FFFBB SCI1 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Note: Bit functions are the same as for SCI0. SSR--Serial Status Register Bit Initial value Read/Write H'FFFBC SCI1 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER/ERS PER TEND MPB MPBT 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 1 R 0 R 0 R/W Note: Bit functions are the same as for SCI0. * Only 0 can be written, to clear the flag. RDR--Receive Data Register H'FFFBD SCI1 Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: Bit functions are the same as for SCI0. Rev. 3.00 Sep 14, 2005 page 844 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers SCMR--Smart Card Mode Register Bit Initial value Read/Write 7 1 H'FFFBE 6 5 1 1 4 1 3 2 SDIR SINV 0 R/W 0 R/W SCI1 1 0 SMIF 1 0 R/W Note: Bit functions are the same as for SCI0. SMR--Serial Mode Register Bit Initial value Read/Write H'FFFC0 SCI2 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: Bit functions are the same as for SCI0. BRR--Bit Rate Register Bit Initial value Read/Write H'FFFC1 SCI2 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Note: Bit functions are the same as for SCI0. Rev. 3.00 Sep 14, 2005 page 845 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers SCR--Serial Control Register Bit Initial value Read/Write H'FFFC2 SCI2 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: Bit functions are the same as for SCI0. TDR--Transmit Data Register Bit Initial value Read/Write H'FFFC3 SCI2 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Note: Bit functions are the same as for SCI0. SSR--Serial Status Register Bit Initial value Read/Write H'FFFC4 SCI2 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER/ERS PER TEND MPB MPBT 1 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 1 R 0 R 0 R/W Note: Bit functions are the same as for SCI0. * Only 0 can be written, to clear the flag. Rev. 3.00 Sep 14, 2005 page 846 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers RDR--Receive Data Register H'FFFC5 SCI2 Bit 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: Bit functions are the same as for SCI0. SCMR--Smart Card Mode Register Bit Initial value Read/Write 7 1 6 H'FFFC6 5 1 4 1 1 3 2 SDIR SINV 0 R/W 0 R/W SCI2 1 0 SMIF 1 0 R/W Note: Bit functions are the same as for SCI0. P1DR--Port 1 Data Register Bit Initial value Read/Write H'FFFD0 Port 1 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data for port 1 pins Rev. 3.00 Sep 14, 2005 page 847 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers P2DR--Port 2 Data Register Bit Initial value Read/Write H'FFFD1 Port 2 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data for port 2 pins P3DR--Port 3 Data Register Bit Initial value Read/Write H'FFFD2 Port 3 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data for port 3 pins P4DR--Port 4 Data Register Bit Initial value Read/Write H'FFFD3 Port 4 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data for port 4 pins Rev. 3.00 Sep 14, 2005 page 848 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers P5DR--Port 5 Data Register Bit Initial value Read/Write 7 H'FFFD4 6 1 5 1 4 1 1 Port 5 3 2 1 0 P53 P52 P51 P50 0 R/W 0 R/W 0 R/W 0 R/W Data for port 5 pins P6DR--Port 6 Data Register Bit Initial value Read/Write H'FFFD5 Port 6 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data for port 6 pins P7DR--Port 7 Data Register Bit Initial value Read/Write H'FFFD6 Port 7 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 * R * R * R * R * R * R * R * R Data for port 7 pins Note: * Determined by pins P77 to P70. Rev. 3.00 Sep 14, 2005 page 849 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers P8DR--Port 8 Data Register Bit Initial value Read/Write 7 1 6 1 H'FFFD7 5 1 Port 8 4 3 2 1 0 P84 P83 P82 P81 P80 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data for port 8 pins P9DR--Port 9 Data Register Bit Initial value Read/Write 7 1 6 1 H'FFFD8 Port 9 5 4 3 2 1 0 P95 P94 P93 P92 P91 P90 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data for port 9 pins PADR--Port A Data Register Bit Initial value Read/Write H'FFFD9 Port A 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data for port A pins Rev. 3.00 Sep 14, 2005 page 850 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers PBDR--Port B Data Register Bit Initial value Read/Write H'FFFDA Port B 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Data for port B pins ADDRA H/L--A/D Data Register A H/L Bit 15 14 13 12 11 H'FFFE0, H'FFFE1 10 9 8 7 6 A/D 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ADDRAH ADDRAL A/D conversion data 10-bit data giving an A/D conversion result ADDRB H/L--A/D Data Register B H/L Bit 15 14 13 12 11 H'FFFE2, H'FFFE3 10 9 8 7 6 A/D 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R ADDRBH 0 R 0 R 0 R 0 R 0 R ADDRBL A/D conversion data 10-bit data giving an A/D conversion result Rev. 3.00 Sep 14, 2005 page 851 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers ADDRC H/L--A/D Data Register C H/L Bit 15 14 12 13 H'FFFE4, H'FFFE5 10 11 8 9 6 7 A/D 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ADDRCH ADDRCL A/D conversion data 10-bit data giving an A/D conversion result ADDRD H/L--A/D Data Register D H/L Bit 15 14 13 12 H'FFFE6, H'FFFE7 11 10 9 8 7 6 A/D 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ADDRDH ADDRDL A/D conversion data 10-bit data giving an A/D conversion result ADCR--A/D Control Register Bit 7 H'FFFE9 A/D 6 5 4 3 2 1 0 1 1 1 1 1 1 0 R/W TRGE Initial value Read/Write 0 R/W Trigger Enable 0 A/D conversion start by external trigger or 8-bit timer compare match is disabled 1 A/D conversion is started by falling edge of external trigger signal (ADTRG) or 8-bit timer compare match Rev. 3.00 Sep 14, 2005 page 852 of 910 REJ09B0258-0300 Appendix B Internal I/O Registers ADCSR--A/D Control/Status Register 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 0 R/(W)* 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Initial value Read/Write H'FFFE8 A/D Channel select 2 to 0 Clock select Conversion time = Group Selection Channel Selection Description 0 134 states (maximum) CH2 CH1 CH0 Single Mode Scan Mode AN0 0 AN0 Conversion time = 1 0 1 AN1 AN0, AN1 70 states (maximum) 0 0 AN2 AN0 to AN2 1 1 AN3 AN0 to AN3 0 AN4 AN4 0 Scan mode 1 AN5 AN4, AN5 1 Single mode 0 0 AN6 AN4 to AN6 1 1 Scan mode 1 AN7 AN4 to AN7 A/D start 0 A/D conversion is stopped Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends 1 Scan mode: A/D conversion starts and continues, cycling among the selected channels ADST is cleared to 0 by software, by a reset, or by a transition to standby mode A/D interrupt enable A/D end interrupt request is disabled 0 A/D end interrupt request is enabled 1 A/D end flag 0 1 [Clearing condition] Read ADF when ADF = 1, then write 0 in ADF The DMAC is activated by an ADI interrupt [Setting conditions] Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Sep 14, 2005 page 853 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams Port 1 Block Diagram SSOE Hardware standby External bus released Mode 6/7 Reset Mode 1 to 4 R Q P1 n DDR D C WP1D Reset Mode 6/7 R Q P1n C Mode 1 to 5 WP1 RP1 WP1D: Write to P1DDR WP1: Write to port 1 RP1: Read port 1 SSOE: Software standby output port enable n = 0 to 7 Figure C.1 Port 1 Block Diagram Rev. 3.00 Sep 14, 2005 page 854 of 910 REJ09B0258-0300 P1 nDR D Internal address bus Software standby Internal data bus (upper) C.1 Appendix C I/O Port Block Diagrams Port 2 Block Diagram Reset SSOE R Q P2 n PCR D C RP2P WP2P Mode 6/7 Hardware standby External bus released Internal address bus Software standby Internal data bus (upper) C.2 Reset Mode 1 to 4 R Q P2n DDR D C WP2D Reset Mode 6/7 R Q P2n P2 nDR D C Mode 1 to 5 WP2 RP2 WP2P: Write to P2PCR RP2P: Read P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2: Read port 2 SSOE: Software standby output port enable n = 0 to 7 Figure C.2 Port 2 Block Diagram Rev. 3.00 Sep 14, 2005 page 855 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Reset Hardware standby External bus released R Mode 6/7 Q Write to external address P3 n DDR D C WP3D Reset R Mode 6/7 Q P3n P3 nDR C Mode 1 to 5 WP3 RP3 Read external address WP3D: Write to P3DDR WP3: Write to port 3 RP3: Read port 3 n = 0 to 7 Figure C.3 Port 3 Block Diagram Rev. 3.00 Sep 14, 2005 page 856 of 910 REJ09B0258-0300 D Internal data bus (lower) Port 3 Block Diagram Internal data bus (upper) C.3 Appendix C I/O Port Block Diagrams C.4 Port 4 Block Diagram 8-bit bus 16-bit bus mode mode Mode 6/7 Mode 1 to 5 Q D P4 n PCR C RP4P WP4P Reset Hardware standby R Q Write to external address Internal data bus (lower) R Internal data bus (upper) Reset D P4 n DDR C External bus release WP4D Reset R Q P4n D P4n DR C WP4 RP4 Read external address WP4P: Write to P4PCR RP4P: Read P4PCR WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 n = 0 to 7 Figure C.4 Port 4 Block Diagram Rev. 3.00 Sep 14, 2005 page 857 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams C.5 Port 5 Block Diagram Software standby SSOE D P5 n PCR C RP5P WP5P Mode 6/7 Hardware standby External bus released Mode 1 to 4 Reset R Q P5 n DDR D C WP5D Reset Mode 6/7 R Q P5n P5n DR C Mode 1 to 5 WP5 RP5 WP5P: Write to P5PCR RP5P: Read P5PCR WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 SSOE: Software standby output port enable n = 0 to 3 Figure C.5 Port 5 Block Diagram Rev. 3.00 Sep 14, 2005 page 858 of 910 REJ09B0258-0300 D Internal address bus R Q Internal data bus (upper) Reset Appendix C I/O Port Block Diagrams C.6 Port 6 Block Diagrams R Hardware standby Q D P60 DDR C WP6D Mode 6/7 Reset Internal data bus Reset Bus controller WAIT input enable R P60 Q D P60 DR C WP6 RP6 Bus controller WAIT input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (a) Port 6 Block Diagram (Pin P60) Rev. 3.00 Sep 14, 2005 page 859 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams R Hardware standby Q D P6 1 DDR C Mode 6/7 WP6D Reset Internal data bus Reset Bus controller Bus release enable R P61 Q D P61 DR C WP6 RP6 BREQ input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (b) Port 6 Block Diagram (Pin P61) Rev. 3.00 Sep 14, 2005 page 860 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Hardware standby R Q D P6 2 DDR C WP6D Reset Internal data bus Reset R Q P62 D P62 DR C Mode 6/7 WP6 Bus controller Bus release enable BACK output RP6 WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (c) Port 6 Block Diagram (Pin P62) Rev. 3.00 Sep 14, 2005 page 861 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams SSOE Software standby Mode 6/7 Hardware standby External bus released R Q P6 3 DDR Mode 6/7 D C Internal data bus Reset WP6D Reset R Mode 6/7 P63 Q Mode 1 to 5 P6 3DR D C WP6 RP6 WP6D: WP6: RP6: SSOE: Write to P6DDR Write to port 6 Read port 6 Software standby output port enable Figure C.6 (d) Port 6 Block Diagram (Pin P63) Rev. 3.00 Sep 14, 2005 page 862 of 910 REJ09B0258-0300 Bus controller AS output Appendix C I/O Port Block Diagrams SSOE Software standby Mode 6/7 Hardware standby External bus released R Q P6 4 DDR Mode 6/7 D C Internal data bus Reset WP6D Reset R Mode 6/7 P64 Mode 1 to 5 Q P6 4DR D C Bus controller WE output enable WP6 RD output WE output RP6 WP6D: WP6: RP6: SSOE: Write to P6DDR Write to port 6 Read port 6 Software standby output port enable Figure C.6 (e) Port 6 Block Diagram (Pin P64) Rev. 3.00 Sep 14, 2005 page 863 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams SSOE Software standby Mode 6/7 Hardware standby External bus released R Q P6 n DDR Mode 6/7 D C Internal data bus Reset WP6D Reset R Mode 6/7 P6n Mode 1 to 5 Q P6 nDR D C WP6 Bus controller CAS output enable HWR output LWR output UCAS output LCAS output RP6 WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 SSOE: Software standby output port enable n = 5 and 6 Figure C.6 (f) Port 6 Block Diagram (Pins P65 and P66) Rev. 3.00 Sep 14, 2005 page 864 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Hardware standby Internal data bus output enable output P67 RP6 RP6: Read port 6 Figure C.6 (g) Port 6 Block Diagram (Pin P67) Rev. 3.00 Sep 14, 2005 page 865 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Port 7 Block Diagrams RP7 P7 n Internal data bus C.7 A/D converter Analog input Input enable Channel select signal RP7: Read port 7 n = 0 to 5 RP7 P7 n Internal data bus Figure C.7 (a) Port 7 Block Diagram (Pins P70 to P75) A/D converter Analog input Input enable Channel select signal D/A converter Output enable Analog output RP7: Read port 7 n = 6 and 7 Figure C.7 (b) Port 7 Block Diagram (Pins P76 and P77) Rev. 3.00 Sep 14, 2005 page 866 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Port 8 Block Diagrams Hardware standby SSOE Software standby External bus released Reset R Q D P8 0 DDR C WP8D Reset R Q P80 D P80 DR C Mode 6/7 WP8 Internal data bus C.8 Bus controller Self-refresh output enable RFSH output enable RFSH output RP8 Interrupt controller WP8D: WP8: RP8: SSOE: Write to P8DDR Write to port 8 Read port 8 Software standby output port enable IRQ 0 input Figure C.8 (a) Port 8 Block Diagram (Pin P80) Rev. 3.00 Sep 14, 2005 page 867 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams SSOE Software standby External bus release R Hardware standby Q D P8 1 DDR C WP8D Mode 6/7 Internal data bus Reset Reset R P8n Q Mode 1 to 5 D P81 DR C Bus controller WP8 CS3 output RAS3 output RAS3 output enable Area 3 DRAM connection enable RP8 Interrupt controller IRQ1 input WP8D: WP8: RP8: SSOE: Write to P8DDR Write to port 8 Read port 8 Software standby output port enable Figure C.8 (b) Port 8 Block Diagram (Pin P81) Rev. 3.00 Sep 14, 2005 page 868 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams SSOE Software standby External bus release R Hardware standby Q D P8 2 DDR C WP8D Internal data bus Reset Reset R Mode 6/7 P82 Q Mode 1 to 5 D P82 DR C Bus controller WP8 CS2 output RAS2 output RAS2 output enable RP8 Interrupt controller IRQ2 input WP8D: WP8: RP8: SSOE: Write to P8DDR Write to port 8 Read port 8 Software standby output port enable Figure C.8 (c) Port 8 Block Diagram (Pin P82) Rev. 3.00 Sep 14, 2005 page 869 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Software standby SSOE External bus release Reset R Q D P83DDR C Hardware standby Internal data bus Mode 6/7 Bus controller WP8D CS1 output Reset Mode 6/7 R Q D P83DR C P83 Mode 1 to 5 WP8 RP8 Interrupt controller IRQ3 input A/D converter ADTRG input WP8D: WP8: RP8: SSOE: Write to P8DDR Write to port 8 Read port 8 Software standby output port enable Figure C.8 (d) Port 8 Block Diagram (Pin P83) Rev. 3.00 Sep 14, 2005 page 870 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Reset Software standby SSOE External bus release S R Q D P8 4 DDR C Hardware standby WP8D Reset Internal data bus Mode 6/7 Mode 1 to 4 Bus controller CS 0 output R Mode 6/7 Q P84 Mode 1 to 5 D P84 DR C WP8 RP8 WP8D: WP8: RP8: SSOE: Write to P8DDR Write to port 8 Read port 8 Software standby output port enable Figure C.8 (e) Port 8 Block Diagram (Pin P84) Rev. 3.00 Sep 14, 2005 page 871 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams C.9 Port 9 Block Diagrams Reset Q D P9 0 DDR C WP9D Reset Internal data bus R Hardware standby R Q P90 D P90 DR C WP9 SCI Output enable Serial transmit data Guard time RP9 WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (a) Port 9 Block Diagram (Pin P90) Rev. 3.00 Sep 14, 2005 page 872 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Reset Hardware standby Q D P9 1 DDR C WP9D Reset Internal data bus R R Q P91 D P91 DR C WP9 SCI Output enable Serial transmit data Guard time RP9 WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (b) Port 9 Block Diagram (Pin P91) Rev. 3.00 Sep 14, 2005 page 873 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams R Q Hardware standby D P9 2 DDR C WP9D Reset Internal data bus Reset SCI Input enable R P9 Q 2 D P9 2 DR C WP9 RP9 Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (c) Port 9 Block Diagram (Pin P92) Rev. 3.00 Sep 14, 2005 page 874 of 910 REJ09B0258-0300 Reset Hardware standby R Q D P93DDR C WP9D Reset Internal data bus Appendix C I/O Port Block Diagrams SCI Input enable R Q D P93DR C P93 WP9 RP9 Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (d) Port 9 Block Diagram (Pin P93) Rev. 3.00 Sep 14, 2005 page 875 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams R Hardware standby Q D P9 4DDR C WP9D Reset Internal data bus Reset SCI Clock input enable R Q P9 4 D P9 4 DR C WP9 Clock output enable Clock output RP9 Clock input WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (e) Port 9 Block Diagram (Pin P94) Rev. 3.00 Sep 14, 2005 page 876 of 910 REJ09B0258-0300 Interrupt controller IRQ 4 input Reset Hardware standby R Q D P95DDR C WP9D Reset Internal data bus Appendix C I/O Port Block Diagrams SCI Clock input enable R Q D P95DR C P95 WP9 Clock output enable Clock output RP9 Clock input Interrupt controller IRQ5 input WP9D : Write to P9DDR WP9 : Write to port 9 RP9 : Read port 9 Figure C.9 (f) Port 9 Block Diagram (Pin P95) Rev. 3.00 Sep 14, 2005 page 877 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams C.10 Port A Block Diagrams Internal data bus Reset R Hardware standby Q D PA n DDR C WPAD Reset TPC output enable R Q PA n TPC D PA n DR C Next data WPA Output trigger DMA controller Output enable Transfer end output RPA WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 0 and 1 16-bit timer Counter clock input 8-bit timer Counter clock input Figure C.10 (a) Port A Block Diagram (Pins PA0, PA1) Rev. 3.00 Sep 14, 2005 page 878 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Internal data bus Reset R Hardware standby Q D PA n DDR C WPAD Reset TPC output enable R Q PA n TPC D PAn DR C Next data WPA Output trigger 16-bit timer Output enable Compare match output RPA Input capture Counter clock input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 2 and 3 8-bit timer Counter clock input Figure C.10 (b) Port A Block Diagram (Pins PA2, PA3) Rev. 3.00 Sep 14, 2005 page 879 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Software standby R Hardware standby Q D PAnDDR C WPAD Internal address bus Address output enable Mode 3/4 Reset Internal data bus SSOE Bus released TPC Reset TPC output enable R PA n Q D PAnDR Next data WPA C Output trigger 16-bit timer Output enable Compare match output PRA Input capture WPAD: Write to PADDR WPA: Write to port A RPA: Read port A SSOE: Software standby output port enable n = 4 to 7 Note: The PA7 address output enable setting is fixed at 1 in modes 3 and 4. Figure C.10 (c) Port A Block Diagram (Pins PA4 to PA7) Rev. 3.00 Sep 14, 2005 page 880 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Port B Block Diagrams Software standby SSOE Reset Internal data bus C.11 R Hardware standby Q D PB n DDR C Bus controller CS7 output WPBD Bus released CS output enable TPC Reset PB Mode 1 to 5 n TPC output enable R Q D PB n DR C Next data WPB Output trigger 8-bit timer Output enable Compare match output RPB WPBD: WPB: RPB: SSOE: Write to PBDDR Write to port B Read port B Software standby output port enable Figure C.11 (a) Port B Block Diagram (Pin PB0) Rev. 3.00 Sep 14, 2005 page 881 of 910 REJ09B0258-0300 Internal data bus Appendix C I/O Port Block Diagrams Software standby Reset SSOE Hardware R standby Q D PBnDDR C PB1 Bus released WPBD Mode 1 to 5 Reset Bus controller CS6 output CS output enable TPC TPC output enable R Q D PBnDR C Next data WPB Output trigger 8-bit timer Output enable Compare match output RPB TMO2 TMO3 input DMAC DREQ0 DREQ1 input WPBD: WPB: RPB: SSOE: Write to PBDDR Write to port B Read port B Software standby output port enable Figure C.11 (b) Port B Block Diagram (Pin PB1) Rev. 3.00 Sep 14, 2005 page 882 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams SSOE Software standby Internal data bus External bus release Reset Hardware standby R Q D PB2DDR C WPBD Bus controller RAS5 output enable Area 5 DRAM connection output enable RAS5 output Mode 6/7 PB2 CS5 output Reset CS5 output enable R Q D PB2DR C TPC TPC output enable Next data WPB Output trigger 8-bit timer Output enable Compare match output RPB WPBD: WPB: RPB: SSOE: Write to PBDDR Write to port B Read port B Software standby output port enable Figure C.11 (c) Port B Block Diagram (Pin PB2) Rev. 3.00 Sep 14, 2005 page 883 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams SSOE Software standby Internal data bus External bus release Reset Hardware standby R Q D PB2DDR C WPBD Bus controller RAS5 output enable Area 5 DRAM connection output enable RAS5 output Mode 6/7 PB3 CS5 output Reset CS5 output enable R Q D PB2DR C TPC TPC output enable Next data WPB Output trigger 8-bit timer Output enable Compare match output RPB TMIO3 input DMAC DREQ1 input WPBD: WPB: RPB: SSOE: Write to PBDDR Write to port B Read port B Software standby output port enable Figure C.11 (d) Port B Block Diagram (Pin PB3) Rev. 3.00 Sep 14, 2005 page 884 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Hardware standby External bus release SSOE Software standby Internal data bus Reset R Q D PB 4 DDR C TPC WPBD Reset TPC output enable R Q PB4 D PB 4 DR C Next data WPB Output trigger Bus controller Output enable CAS output RPB WPBD: WPB: RPB: SSOE: Write to PBDDR Write to port B Read port B Software standby output port enable Note: In modes 6 and 7, CAS output enable is fixed at 0. Figure C.11 (e) Port B Block Diagram (Pin PB4) Rev. 3.00 Sep 14, 2005 page 885 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Hardware standby Internal data bus External bus release Software standby SSOE Reset R Q D PB5DDR C SCI Clock input enable WPBD Reset TPC R Q PB5 TPC output enable D PB5DR C Next data WPB Output trigger Bus controller CAS output enable CAS output SCI Clock output enable Clock output RPB Clock input WPBD: WPB: RPB: SSOE: Note: In modes 6 and 7, CAS output enable is fixed at 0. Write to PBDDR Write to port B Read port B Software standby output port enable Figure C.11 (f) Port B Block Diagram (Pin PB5) Rev. 3.00 Sep 14, 2005 page 886 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Internal data bus Reset R Hardware standby Q PB 6 DDR D C WPBD TPC Reset TPC output enable R PB6 Q PB6 DR D Next data C WPB Output trigger SCI Output enable Serial transmit data Guard time RPB WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.11 (g) Port B Block Diagram (Pin PB6) Rev. 3.00 Sep 14, 2005 page 887 of 910 REJ09B0258-0300 Appendix C I/O Port Block Diagrams Internal data bus Reset R Hardware standby Q PB 7 DDR D C WPBD Reset TPC TPC output enable R PB7 Q PB7 DR SCI Input enable D Next data C WPB Output trigger RPB SCI Serial receive data WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.11 (h) Port B Block Diagram (Pin PB7) Rev. 3.00 Sep 14, 2005 page 888 of 910 REJ09B0258-0300 Appendix D Pin States Appendix D Pin States D.1 Port States in Each Mode Table D.1 Pin Name P17 to P10 P27 to P20 P37 to P30 P47 to P40 Port States Mode Hardware Standby Software Standby Reset Mode Mode Bus-Released Mode Program Execution Mode 1 to 4 L T (SSOE=0) T (SSOE=1) Keep T A7 to A0 5 T T (DDR = 0) Keep (DDR=1, SSOE=0) T (DDR=1, SSOE=1) Keep T (DDR=0) Input port (DDR=1) A7 to A0 6, 7 T T Keep -- I/O port 1 to 4 L T (SSOE = 0) T (SSOE = 1) Keep T A15 to A8 5 T T (DDR = 0) Keep (DDR=1,SSOE=0) T (DDR=1,SSOE=1) Keep T (DDR=0) Input port (DDR=1) A15 to A8 6, 7 T T Keep -- I/O port 1 to 5 T T T T D15 to D8 6, 7 T T Keep -- I/O port 1, 3, 5 T T Keep Keep I/O port 2, 4 T T T T D7 to D0 6, 7 T T Keep -- I/O port Rev. 3.00 Sep 14, 2005 page 889 of 910 REJ09B0258-0300 Appendix D Pin States Mode Hardware Standby Software Standby Reset Mode Mode Bus-Released Mode Program Execution Mode 1 to 4 L T (SSOE=0) T (SSOE=1) Keep T A19 to A16 5 T T (DDR=0) Keep (DDR=1, SSOE=0) T (DDR=1, SSOE=1) Keep T (DDR=0) Input port (DDR=1) A19 to A16 6, 7 T T Keep -- I/O port 1 to 5 T T Keep Keep WAIT 6, 7 T T Keep -- I/O port 1 to 5 T T (BRLE=0) Keep (BRLE=1) T T I/O port 6, 7 T T Keep -- I/O port 1 to 5 T T (BRLE=0) Keep (BRLE=1) H L (BRLE=0) I/O port (BRLE=1) 6, 7 T T Keep -- 1 to 5 H T (SSOE=0) T (SSOE=1) H T AS, RD, HWR, LWR 6, 7 T T Keep -- I/O port P67 1 to 7 Clock T output (PSTOP=0) H (PSTOP=1) Keep (PSTOP=0) (PSTOP=1) Keep (PSTOP=0) (PSTOP=1) Input port P77 to P70 1 to 7 T T T Input port Pin Name P53 to P50 P60 P61 P62 P66 to P63 T Rev. 3.00 Sep 14, 2005 page 890 of 910 REJ09B0258-0300 I/O port BREQ BACK I/O port Appendix D Pin States Pin Name Mode Hardware Standby Software Standby Reset Mode Mode P80 1 to 5 T T Bus-Released Mode Program Execution Mode When DRAM space is not selected*1 (RFSHE=0) Keep (RFSHE=1) Illegal setting When DRAM space is selected*2 (RFSHE=0) Keep (RFSHE=1, SRFMD=0, SSOE=0) T (RFSHE=1, SRFMD=0, SSOE=1) H (RFSHE=1, SRFMD=1) When DRAM space is selected*1 (RFSHE=0) Keep (RFSHE=1) Illegal setting When DRAM space is selected*2 (RFSHE=0) Keep (RFSHE=1) T (RFSHE=0) I/O port (RFSHE=1) RFSH RFSH P81 6, 7 T T Keep -- I/O port 1 to 5 T T When DRAM space is selected*3 (SSOE=0) T (SSOE=1) H When DRAM space is selected*4 Keep Otherwise*5 *1 (DDR=0) T (DDR=1, SSOE=0) T (DDR=1, SSOE=1) H When DRAM space is selected*3 T When DRAM space is selected*4 Keep Otherwise*1 (DDR=0) Keep (DDR=1) T When DRAM space is selected and RAS3 is output Keep -- 6, 7 T T RAS 3 When DRAM space is selected and RAS3 is not output I/O port Otherwise (DDR=0) Input port (DDR=1) CS 3 I/O port Rev. 3.00 Sep 14, 2005 page 891 of 910 REJ09B0258-0300 Appendix D Pin States Pin Name Mode Hardware Standby Software Standby Reset Mode Mode P82 1 to 5 T P83 P84 T Bus-Released Mode Program Execution Mode RAS2 output*2 (SSOE=0) T (SSOE=1) H Otherwise*1 (DDR=0) T (DDR=1, SSOE=0) T (DDR=1, SSOE=1) H RAS2 output*2 T Otherwise*1 (DDR=0) Keep (DDR=1) T RAS2 output RAS 2 Otherwise (DDR=0) I/O port (DDR=1) CS 2 6, 7 T T Keep -- I/O port 1 to 5 T T (DDR=0) T (DDR=1, SSOE=0) T (DDR=1, SSOE=1) H (DDR=0) Keep (DDR=1) T (DDR=0) Input port (DDR=1) CS 1 6, 7 T T Keep -- I/O port 1 to 4 H T (DDR=0) T (DDR=1, SSOE=0) T (DDR=1, SSOE=1) H (DDR = 0) Keep (DDR = 1) T (DDR = 0) Input port (DDR = 1) (DDR=0) T (DDR=1, SSOE=0) T (DDR=1, SSOE=1) H (DDR=0) Keep (DDR=1) T (DDR=0) Input port (DDR=1) 5 T T CS 0 CS 0 6, 7 T T Keep -- I/O port 1 to 7 T T Keep Keep I/O port PA3 to 1 to 7 PA0 T T Keep Keep I/O port PA6 to 1, 2, 6, T PA4 7 T Keep Keep I/O port P95 to P90 Rev. 3.00 Sep 14, 2005 page 892 of 910 REJ09B0258-0300 Appendix D Pin States Pin Name Mode Hardware Standby Software Standby Reset Mode Mode Bus-Released Mode Program Execution Mode PA6 to 3 to 5 PA4 T T Address output*5 (SSOE=0) T (SSOE=1) Keep Otherwise*6 Keep Address output*5 T Otherwise*6 Keep Address output A23 to A21 Otherwise I/O port PA7 1, 2 T T Keep Keep I/O port 3, 4 L T (SSOE=0) T (SSOE=1) Keep T A20 5 L T When A20E = 0 SSOE = 0 T SSOE = 1 Keep When A20E = 1 Keep When A20E = 0 T When A20E = 1 Keep When A20E = 0 A20 When A20E = 1 I/O port 6, 7 T T Keep -- I/O port T T CS output*7 (SSOE=0) T (SSOE=1) H Otherwise*8 Keep CS output*7 T Otherwise*8 Keep CS output 7 to 6 Otherwise I/O port T T Keep -- I/O port PB1 to 1 to 5 PB0 6, 7 PB2 1 to 5 6, 7 T T T T output*9 output*9 CS CS RAS5 (SSOE=0) T (SSOE=1) H CS output*10 (SSOE=0) T (SSOE=1) H Otherwise*11 Keep RAS5 T CS output*10 T Otherwise*11 Keep RAS5 output Keep -- I/O port RAS5 CS output CS5 Otherwise I/O port Rev. 3.00 Sep 14, 2005 page 893 of 910 REJ09B0258-0300 Appendix D Pin States Pin Name Mode Hardware Standby Software Standby Reset Mode Mode PB3 1 to 5 T 6, 7 PB5 to 1 to 5 PB4 6, 7 PB7 to 1 to 7 PB6 T T T Bus-Released Mode Program Execution Mode RAS4 output*12 (SSOE=0) T (SSOE=1) H CS output*13 (SSOE=0) T (SSOE=1) H Otherwise*14 Keep RAS4 output*12 T CS output*13 T Otherwise*14 Keep RAS4 output Keep -- I/O port output*15 output*15 RAS4 CS output CS4 Otherwise I/O port T T CAS (SSOE=0) T (SSOE=1) H Otherwise*16 Keep CAS T Otherwise*16 Keep CAS output , Otherwise I/O port T T Keep -- I/O port T T Keep Keep I/O port UCAS LCAS Legend H: High L: Low T: High-impedance state Keep: Input pins are in the high-impedance state; output pins maintain their previous state. DDR: Data direction register Notes: 1. When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all cleared to 0. 2. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is set to 1. 3. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is 010, 100, or 101. 4. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 010, 100, 101, or 000. 5. When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is cleared to 0. 6. When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is set to 1. 7. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to 1. Rev. 3.00 Sep 14, 2005 page 894 of 910 REJ09B0258-0300 Appendix D Pin States 8. 9. 10. 11. 12. 13. 14. 15. 16. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is cleared to 0. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is 101. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 101, and bit CS5E in CSCR (chip select control register) is set to 1. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 101, and bit CS5E in CSCR (chip select control register) is cleared to 0. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is 100, 101, or 110. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control register) is set to 1. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control register) is cleared to 0. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is set to 1, and bit CSEL in DRCRB (DRAM control register B) is cleared to 0. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is set to 1, and bit CSEL in DRCRB (DRAM control register B) is set to 1; or, when bits DRAS2, DRAS1, and DRAS0 are all cleared to 0. Rev. 3.00 Sep 14, 2005 page 895 of 910 REJ09B0258-0300 Appendix D Pin States D.2 Pin States at Reset Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, LWR, and CS0 go high, and D15 to D0 go to the high-impedance state. The address bus is initialized to the low output level 2.5 clock cycles after the low level of RES is sampled. Clock pin P67/ goes to the output state at the next rise of after RES goes low. Access to external memory T1 T2 T3 P67/ RES Internal reset signal A19 to A0 H'00000 CS0 AS, RD (read) HWR, LWR (write) D15 to D0 (write) High impedance I/O port, CS7 to CS1 High impedance Figure D.1 Reset during Memory Access (Modes 1 and 2) Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, LWR, and CS0 go high, and D15 to D0 go to the high-impedance state. The address bus is initialized to the low output level 2.5 clock cycles after the low level of RES is sampled. However, when PA4 to PA6 are used as address bus pins, or when P83 to P81 and PB0 Rev. 3.00 Sep 14, 2005 page 896 of 910 REJ09B0258-0300 Appendix D Pin States to PB3 are used as CS output pins, they go to the high-impedance state at the same time as RES goes low. Clock pin P67/ goes to the output state at the next rise of after RES goes low. Access to external memory T1 T2 T3 P67/ RES Internal reset signal A20 to A0 H'000000 CS0 AS, RD (read) HWR, LWR (write) D15 to D0 (write) High impedance I/O port, PA4/A23 to PA6/A21, CS7 to CS1 High impedance Figure D.2 Reset during Memory Access (Modes 3 and 4) Mode 5: Figure D.3 is a timing diagram for the case in which RES goes low during an external memory access in mode 5. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, and LWR go high, and the address bus and D15 to D0 go to the high-impedance state. Clock pin P67/ goes to the output state at the next rise of after RES goes low. Rev. 3.00 Sep 14, 2005 page 897 of 910 REJ09B0258-0300 Appendix D Pin States Access to external memory T1 T2 T3 P67/ RES Internal reset signal High impedance A23 to A0 AS, RD (read) HWR, LWR (write) D15 to D0 (write) High impedance I/O port, CS7 to CS1 High impedance Figure D.3 Reset during Memory Access (Mode 5) Modes 6 and 7: Figure D.4 is a timing diagram for the case in which RES goes low during an operation in mode 6 or 7. As soon as RES goes low, all ports are initialized to the input state. Clock pin P67/ goes to the output state at the next rise of after RES goes low. P67/ RES Internal reset signal High impedance I/O port Figure D.4 Reset during Operation (Modes 6 and 7) Rev. 3.00 Sep 14, 2005 page 898 of 910 REJ09B0258-0300 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode 1. To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns). STBY t1 10tcyc t2 0 ns RES 2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately 100 ns before STBY goes high. STBY t 100 ns tOSC RES Rev. 3.00 Sep 14, 2005 page 899 of 910 REJ09B0258-0300 Appendix D Pin States Appendix F Product Code Lineup Product Type Product Code Mark Code Package (Package Code) H8/3068F HD64F3068F HD64F3068F 100-pin QFP (FP-100B) HD64F3068TE HD64F3068TE 100-pin TQFP (TFP-100B) On-chip flash 5 V memory Rev. 3.00 Sep 14, 2005 page 900 of 910 REJ09B0258-0300 Appendix G Package Dimensions Appendix G Package Dimensions Figures G.1 show the FP-100B package dimensions of the H8/3067 Group. Figure G.2 shows the TFP-100B package dimensions. Figure G.3 shows the FP-100A package dimentions. JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HD *1 D 75 51 76 50 bp Reference Symbol Nom Max 14 D c c1 HE Dimension in Millimeters Min E 14 A2 2.70 *2 E b1 ZE Terminal cross section 1 2 5 16.0 16.3 15.7 16.0 16.3 0.00 0.12 0.25 bp 0.17 0.22 0.27 0.12 0.17 A1 bp x L e L1 x Detail F y 0.20 M 8 0 0.5 0.08 0.10 y 1.0 ZD 1.0 ZE L L1 0.22 0.15 c1 c F A2 A c *3 3.05 A1 b1 ZD e 15.7 HE A 26 100 HD 0.3 0.5 0.7 1.0 Figure G.1 Package Dimensions (FP-100B) Rev. 3.00 Sep 14, 2005 page 901 of 910 REJ09B0258-0300 Appendix G Package Dimensions JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g HD *1 D 75 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 51 76 50 bp Reference Symbol c c1 HE Dimension in Millimeters Min Nom D 14 E 14 Max *2 E b1 1.00 A2 Terminal cross section HD 15.8 16.0 HE 15.8 16.0 ZE 26 A1 0.00 0.10 0.20 bp 0.17 0.22 0.27 0.12 0.17 0.20 b1 ZD c c1 Index mark F A1 L L1 Detail F 0.15 y *3 bp x M e 0.5 0.08 x 0.10 y 1.00 ZD L L1 Figure G.2 Package Dimensions (TFP-100B) Rev. 3.00 Sep 14, 2005 page 902 of 910 REJ09B0258-0300 8 0 1.00 ZE e 0.22 c A2 25 A 1 16.2 1.20 A 100 16.2 0.4 0.5 1.0 0.6 Appendix H Comparison of H8/300H Series Product Specifications Appendix H Comparison of H8/300H Series Product Specifications H.1 Differences between H8/3068F and H8/3067 Group and H8/3062 Group, H8/3048 Group H8/3068F H8/3067 Group, H8/3062 Group H8/3048 Group Mode 5 16 Mbytes ROM enabled expanded mode 16 Mbytes ROM enabled expanded mode 1 Mbyte ROM enabled expanded mode Mode 6 64 kbytes single-chip mode 64 kbytes single-chip mode 16 Mbyte ROM enabled expanded mode Interrupt controller Internal interrupt sources 36 36 (H8/3067) 30 Bus controller Burst ROM interface Yes Item 1 2 3 4 Operating mode DRAM interface 27 (H8/3062) Yes (H8/3067) No No (H8/3062) Idle cycle insertion Yes function Yes No Wait mode 2 modes 2 modes 4 modes Wait state number setting Per area Per area Common to all areas Address output method Choice of address update fixed Fixed Choice of address update mode (mask ROM and flash memory R versions only) Connectable areas Area 2/3/4/5 Area 2/3/4/5 (H8/3067 only) Area 3 Precharge cycle insertion function Yes Yes (H8/3067 only) No Fast page mode Yes Yes (H8/3067 only) No Address shift amount 8 bit/9 bit/10 bit 8 bit/9 bit/10 bit (H8/3067 only) 8 bit/9 bit Rev. 3.00 Sep 14, 2005 page 903 of 910 REJ09B0258-0300 Appendix H Comparison of H8/300H Series Product Specifications 5 H8/3067 Group, H8/3062 Group H8/3048 Group 8-bit timers 16-bit timers 8-bit timers ITU 16 bits x 3 8 bits x 4 (16 bits x 2) 16 bits x 3 8 bits x 4 (16 bits x 2) 16 bits x 5 Pulse output 6 pins 4 pins (2 pins) 6 pins 4 pins (2 pins) 12 pins Input capture 6 2 6 2 10 External clock 4 systems (selectable) 4 systems (fixed) 4 systems (selectable) 4 systems (fixed) 4 systems (selectable) Internal clock , /2, /4, /8 /8, /64, /8192 , /2, /4, /8 /8, /64, /8192 , /2, /4, /8 Complementary PWM function No No No No Yes Resetsynchronous PWM function No No No No Yes Buffer operation No No No No Yes Output initialization function Yes No Yes No No PWM output 3 4 (2) 3 4 (2) 5 DMAC activation 3 channels No 3 channels (H8/3067 only) No 4 channels A/D conversion activation No Yes No Yes No Interrupt sources 3 sources x3 8 sources 3 sources x3 8 sources 3 sources x5 Item H8/3068F Timer functions 16-bit timers Number of channels 6 TPC Time base 3 kinds, 16-bit timer base 3 kinds, 16-bit timer base 4 kinds, ITU base 7 WDT Reset signal external output function No Yes (except products with on-chip flash memory) Yes 8 SCI Number of channels 3 channels 3 channels (H8/3067) 2 channels Smart card interface Supported on all channels 2 channels (H8/3062) Rev. 3.00 Sep 14, 2005 page 904 of 910 REJ09B0258-0300 Supported on all channels Supported on SCI0 only Appendix H Comparison of H8/300H Series Product Specifications Item H8/3068F H8/3067 Group, H8/3062 Group H8/3048 Group 9 A/D converter Conversion start trigger input External trigger/8-bit timer compare match External trigger/8-bit timer compare match External trigger 10 Pin control pin /input port multiplexing /input port multiplexing output only A20 in 16 MB ROM A20 / I/O port multiplexing enabled expanded mode A20 / I/O port multiplexing A20 output High-level output/highAddress bus, impedance selectable AS, RD, HWR, LWR, CS7-CS0, RFSH in software standby state High-level output/highimpedance selectable (RFSH: H8/3067 only) High-level output (except CS0) CS7-CS0 in busreleased state 11 Flash memory functions Low-level output (CS0) High-impedance High-impedance High-level output Program/erase voltage 12 V application unnecessary. Single-power-supply programming. 12 V application unnecessary. Single-power-supply programming. 12 V application from off-chip Block divisions 14 blocks 8 blocks 16 blocks Rev. 3.00 Sep 14, 2005 page 905 of 910 REJ09B0258-0300 Appendix H Comparison of H8/300H Series Product Specifications H.2 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) Table H.1 Pin Arrangement of Each Product (FP-100B, TFP-100B) Pin No. H8/3068F H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group 1 VCL VCC VCC/VCL VCC VCC 2 PB0/TP8/TMO0/ PB0/TP8/TMO0/ PB0/TP8/TMO0/ PB0/TP8/ TIOCA3 PB0/TP8/ TIOCA3 3 PB1/TP9/TMIO1/ DREQ0/CS6 PB1/TP9/TMIO1/ DREQ0/CS6 PB1/TP9/TMIO1/ PB1/TP9/ TIOCB3 PB1/TP9/ TIOCB3 4 PB2/TP10/TMO2/ PB2/TP10/TMO2/ PB2/TP10/TMO2/ CS5 PB2/TP10/ TIOCA4 PB2/TP10/ TIOCA4 5 PB3/TP11/TMIO3/ DREQ1/CS4 PB3/TP11/TMIO3/ DREQ1/CS4 PB3/TP11/TMIO3/ PB3/TP11/TIOCB4 PB3/TP11/TIOCB4 6 PB4/TP12/UCAS PB4/TP12/UCAS PB4/TP12 PB4/TP12/TOCXA4 PB4/TP12/TOCXA4 7 PB5/TP13/LCAS/ SCK2 PB5/TP13/LCAS/ SCK2 PB5/TP13 PB5/TP13/TOCXB4 PB5/TP13/TOCXB4 8 PB6/TP14/TxD2 PB6/TP14/TxD2 PB6/TP14 PB6/TP14/DREQ0/ PB6/TP14/DREQ0 9 PB7/TP15/RxD2 PB7/TP15/RxD2 PB7/TP15 PB7/TP15/DREQ1/ PB7/TP15/DREQ1/ 10 FWE RESO/FWE* RESO/FWE* ADTRG RESO/VPP* 11 Vss Vss Vss Vss Vss 12 P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 13 P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 14 P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 15 P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 16 P94/SCK0/IRQ4 P94/SCK0/IRQ4 P94/SCK0/IRQ4 P94/SCK0/IRQ4 P94/SCK0/IRQ4 17 P95/SCK1/IRQ5 P95/SCK1/IRQ5 P95/SCK1/IRQ5 P95/SCK1/IRQ5 P95/SCK1/IRQ5 18 P40/D0 P40/D0 P40/D0 P40/D0 P40/D0 19 P41/D1 P41/D1 P41/D1 P41/D1 P41/D1 20 P42/D2 P42/D2 P42/D2 P42/D2 P42/D2 21 P43/D3 P43/D3 P43/D3 P43/D3 P43/D3 22 Vss Vss Vss Vss Vss 23 P44/D4 P44/D4 P44/D4 P44/D4 P44/D4 24 P45/D5 P45/D5 P45/D5 P45/D5 P45/D5 25 P46/D6 P46/D6 P46/D6 P46/D6 P46/D6 26 P47/D7 P47/D7 P47/D7 P47/D7 P47/D7 CS7 CS5 CS7 CS5 Rev. 3.00 Sep 14, 2005 page 906 of 910 REJ09B0258-0300 CS7 CS6 CS4 CS7 ADTRG RESO Appendix H Comparison of H8/300H Series Product Specifications Pin No. H8/3068F H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group 27 P30/D8 P30/D8 P30/D8 P30/D8 P30/D8 28 P31/D9 P31/D9 P31/D9 P31/D9 P31/D9 29 P32/D10 P32/D10 P32/D10 P32/D10 P32/D10 30 P33/D11 P33/D11 P33/D11 P33/D11 P33/D11 31 P34/D12 P34/D12 P34/D12 P34/D12 P34/D12 32 P35/D13 P35/D13 P35/D13 P35/D13 P35/D13 33 P36/D14 P36/D14 P36/D14 P36/D14 P36/D14 34 P37/D15 P37/D15 P37/D15 P37/D15 P37/D15 35 Vcc Vcc Vcc Vcc Vcc 36 P10/A0 P10/A0 P10/A0 P10/A0 P10/A0 37 P11/A1 P11/A1 P11/A1 P11/A1 P11/A1 38 P12/A2 P12/A2 P12/A2 P12/A2 P12/A2 39 P13/A3 P13/A3 P13/A3 P13/A3 P13/A3 40 P14/A4 P14/A4 P14/A4 P14/A4 P14/A4 41 P15/A5 P15/A5 P15/A5 P15/A5 P15/A5 42 P16/A6 P16/A6 P16/A6 P16/A6 P16/A6 43 P17/A7 P17/A7 P17/A7 P17/A7 P17/A7 44 Vss Vss Vss Vss Vss 45 P20/A8 P20/A8 P20/A8 P20/A8 P20/A8 46 P21/A9 P21/A9 P21/A9 P21/A9 P21/A9 47 P22/A10 P22/A10 P22/A10 P22/A10 P22/A10 48 P23/A11 P23/A11 P23/A11 P23/A11 P23/A11 49 P24/A12 P24/A12 P24/A12 P24/A12 P24/A12 50 P25/A13 P25/A13 P25/A13 P25/A13 P25/A13 51 P26/A14 P26/A14 P26/A14 P26/A14 P26/A14 52 P27/A15 P27/A15 P27/A15 P27/A15 P27/A15 53 P50/A16 P50/A16 P50/A16 P50/A16 P50/A16 54 P51/A17 P51/A17 P51/A17 P51/A17 P51/A17 55 P52/A18 P52/A18 P52/A18 P52/A18 P52/A18 56 P53/A19 P53/A19 P53/A19 P53/A19 P53/A19 57 Vss Vss Vss Vss Vss 58 P60/WAIT P60/WAIT P60/WAIT P60/WAIT P60/WAIT 59 P61/BREQ P61/BREQ P61/BREQ P61/BREQ P61/BREQ 60 P62/BACK P62/BACK P62/BACK P62/BACK P62/BACK 61 P67/ P67/ P67/ Rev. 3.00 Sep 14, 2005 page 907 of 910 REJ09B0258-0300 Appendix H Comparison of H8/300H Series Product Specifications Pin No. H8/3068F H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group STBY RES STBY RES 63 STBY RES STBY RES STBY RES 64 NMI NMI NMI NMI NMI 65 Vss Vss Vss Vss Vss 66 EXTAL EXTAL EXTAL EXTAL EXTAL 62 67 XTAL XTAL XTAL XTAL XTAL 68 Vcc Vcc Vcc Vcc Vcc 69 P63/AS P63/AS P63/AS P63/AS P63/AS 70 P64/RD P64/RD P64/RD P64/RD P64/RD 71 P65/HWR P65/HWR P65/HWR P65/HWR P65/HWR 72 P66/LWR P66/LWR P66/LWR P66/LWR P66/LWR 73 MD0 MD0 MD0 MD0 MD0 74 MD1 MD1 MD1 MD1 MD1 75 MD2 MD2 MD2 MD2 MD2 76 AVcc AVcc AVcc AVcc AVcc 77 VREF VREF VREF VREF VREF 78 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 79 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 80 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 81 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 82 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 83 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 84 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 85 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 86 AVss AVss AVss AVss AVss 87 P80/RFSH/IRQ0 P80/RFSH/IRQ0 P80/IRQ0 P80/RFSH/IRQ0 P80/RFSH/IRQ0 88 P81/CS3/IRQ1 P81/CS3/IRQ1 P81/CS3/IRQ1 P81/CS3/IRQ1 P81/CS3/IRQ1 89 P82/CS2/IRQ2 P82/CS2/IRQ2 P82/CS2/IRQ2 P82/CS2/IRQ2 P82/CS2/IRQ2 90 P83/CS1/IRQ3/ P83/CS1/IRQ3/ P83/CS1/IRQ3 P83/CS1/IRQ3 91 ADTRG P84/CS0 P83/CS1/IRQ3/ P84/CS0 P84/CS0 92 Vss Vss Vss Vss Vss 93 PA0/TP0/TEND0/ TCLKA PA0/TP0/TEND0/ TCLKA PA0/TP0/TCLKA PA0/TP0/TEND0/ TCLKA PA0/TP0/TEND0/ TCLKA 94 PA1/TP1/TEND1/ TCLKB PA1/TP1/TEND1/ TCLKB PA1/TP1/TCLKB PA1/TP1/TEND1/ TCLKB PA1/TP1/TEND1/ TCLKB ADTRG P84/CS0 Rev. 3.00 Sep 14, 2005 page 908 of 910 REJ09B0258-0300 ADTRG P84/CS0 Appendix H Comparison of H8/300H Series Product Specifications Pin No. H8/3068F H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group 95 PA2/TP2/TIOCA0/ TCLKC PA2/TP2/TIOCA0/ TCLKC PA2/TP2/TIOCA0/ TCLKC PA2/TP2/TIOCA0/ TCLKC PA2/TP2/TIOCA0/ TCLKC 96 PA3/TP3/TIOCB0/ TCLKD PA3/TP3/TIOCB0/ TCLKD PA3/TP3/TIOCB0/ TCLKD PA3/TP3/TIOCB0/ TCLKD PA3/TP3/TIOCB0/ TCLKD 97 PA4/TP4/TIOCA1/ A23 PA4/TP4/TIOCA1/ A23 PA4/TP4/TIOCA1/ A23 PA4/TP4/TIOCA1/ CS6/A23 PA4/TP4/TIOCA1/ A23 98 PA5/TP5/TIOCB1/ A22 PA5/TP5/TIOCB1/ A22 PA5/TP5/TIOCB1/ A22 PA5/TP5/TIOCB1/ CS5/A22 PA5/TP5/TIOCB1/ A22 99 PA6/TP6/TIOCA2/ A21 PA6/TP6/TIOCA2/ A21 PA6/TP6/TIOCA2/ A21 PA6/TP6/TIOCA2/ CS4/A21 PA6/TP6/TIOCA2/ A21 100 PA7/TP7/TIOCB2/ A20 PA7/TP7/TIOCB2/ A20 PA7/TP7/TIOCB2/ A20 PA7/TP7/TIOCB2/ A20 PA7/TP7/TIOCB2/ A20 Note: * Functions as RESO in the mask ROM versions, and as FWE in the flash memory and flash memory R versions. Rev. 3.00 Sep 14, 2005 page 909 of 910 REJ09B0258-0300 Appendix H Comparison of H8/300H Series Product Specifications Rev. 3.00 Sep 14, 2005 page 910 of 910 REJ09B0258-0300 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/3068F-ZTAT Publication Date: 1st Edition, March, 2001 Rev.3.00, September 14, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. (c)2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> 2-796-3115, Fax: <82> 2-796-2145 Renesas Technology Malaysia Sdn. Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 3.0 H8/3068F-ZTATTM Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0258-0300