1
Single Port, PLC Differential Line Driver
ISL15100
The ISL15100 is a single port differential line driver developed
for Power Line Communication (PLC) applications. The device
is designed to drive heavy line loads while maintaining the
high level of linearity required in OFDM PLC modem links. With
15.5dBm of total transmit signal power into 100Ω line load,
the driver achieves -43dB average MTPR distortion across the
output spectrum up to 86MHz.
The ISL15100 has two bias current control pins (C0, C1) to
allow for four power settings (disable, low, medium, high). In
disable mode, the line driver outputs maintain a high
impedance in the presence of high receive signal amplitude,
so it doesn’t affect TDM receive signal integrity.
The ISL15100 is available in the thermally-enhanced 16 Ld
QFN and is specified for operation over the full -40°C to +85°C
ambient temperature range.
Features
• Single differential driver
• 100MHz Broadband PLC G.hn, EOC, HomePlug AV2
• Control pins for enable/disable and supply current selection
• High output impedance when disabled for TDM operation
• -43dBc average MTPR distortion at full line power
• Single +12V or bipolar ±6V nominal supplies
• High surge current handling capability
Applications
• Power Line Communication differential driver
• Pin compatible upgrade to ISL1571IRZ
Related Literature
•AN1325 “Choosing and Using Bypass Capacitors”
TABLE 1. ALTERNATE SOLUTIONS
PART #
NOMINAL ±VS
(V)
BANDWIDTH
(MHz) APPLICATIONS
ISL1571 ±6, +12 200 HomePlug AV1
FIGURE 1. TYPICAL APPLICATION CIRCUIT FIGURE 2. 50MHz PLC SPECTRUM
3.9
1k
+12V
+
-
AFE
1k
+
-
133
½ ISL15100
½ ISL15100 3.9
100
NOMINAL
LINE
1:2
TYPICAL DIFFEREN TIAL I/O LINE DRIVER
2.2n
Vcm
500
500
100n
100n
SUPPLY
DECOUPLING
NOT SHOWN
Rf
Rf
Rg Ω
Ω
Ω
FREQUENCY (MHz)
POWER (dBM)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130 2 7 12 17 22 27 32 37 42 47
September 19, 2013
FN8577.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL15100
2FN8577.0
September 19, 2013
Connection Diagram
Ordering Information
PART
NUMBER
(Notes 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL15100IRZ 151 00IRZ -40 to +85 16 Ld QFN L16.4x4H
ISL15100IRZ-T7 (Note 1) 151 00IRZ -40 to +85 16 Ld QFN L16.4x4H
ISL15100IRZ-T13 (Note 1) 151 00IRZ -40 to +85 16 Ld QFN L16.4x4H
ISL15100EVAL1Z Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL15100. For more information on MSL please see tech brief TB363.
+12V
+
-
+
-
1:2
INB-
INA-
OUTA
OUTB
INA+
INB+ BIAS
CURRENT
CONTROL
C0
C1
+
½ ISL15100
+6V 133
500mVp 11.8Vp
INTO
100
+
½ ISL15100
8.0Vp
3.9Ω
3.9Ω
PLINE
1kΩ
1kΩ
Ω
Txmn
CF = 15.4dB
PLINE = 16dBm
Av = 1 + 2 x 1000
133 = 16(V/V)
140Ω DIFFERENTIAL RECEIVER
PATH LOAD AT TXMN INPUT
Ω
500
Ω
500
FIGURE 3. TYPICAL DIFFERENTIAL AMPLIFIER I/O
ISL15100
3FN8577.0
September 19, 2013
Pin Configuration
ISL15100
(16 LD QFN)
TOP VIEW
1
3
4
15
NC
INA-
INA+
GND
OUTA
NC
VS+
OUTB
16 14 13
2
12
10
9
11
6578
NC
INB-
INB+
C1
NC
NC
VS-
C0
EP*
*EXPOSED THERMAL PAD CONNECTS TO MOST NEGATIVE SUPPLY
Pin Descriptions
PIN NUMBER PIN NAME FUNCTION
EP THERMAL PAD Connect to the Most Negative Supply
1 NC No Internal Connection
2 INA- Amplifier A Inverting Input
3 INA+ Amplifier A Non-Inverting Input
4GNDGround
5 NC No Internal Connection
6 NC No Internal Connection
7V
S- Negative Supply Voltage (-6V for split supplies, GND for single supply operation)
8 C0 Digital Control Pin
9 C1 Digital Control Pin
10 INB+ Amplifier B Non-Inverting Input
11 INB- Amplifier B Inverting Input
12 NC No Internal Connection
13 OUTB Amplifier B Output
14 VS+ Positive Supply Voltage (+6V for split supplies, +12V for single supply operation)
15 NC No Internal Connection
16 OUTA Amplifier A Output
C0, C1 Truth Table
C1 C0 FUNCTION
00High Bias Setting
0 1 Medium Bias Setting
1 0 Low Bias Setting
11Outputs Disabled (Power Down)
ISL15100
4FN8577.0
September 19, 2013
Absolute Maximum Ratings (TA = +25°C) Thermal Information
VS+ Voltage to VS- or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +13.3V
INA+, INB+ Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS+
C0, C1 Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VS+
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Continuous Output Current for Long Term Reliability. . . . . . . . . . . . . . . . 50mA
Latch-up (Tested per JESD78D, Class II) . . . . . . . . . . . . . . . . . . . . . . 100mA
ESD Rating
Human Body Model (Tested per JESD22-A114F). . . . . . . . . . . . . . . . . . 4kV
Charge Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . 1.5kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 300V
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
16 Ld QFN Package (Notes 4, 5) . . . . . . . . 53 16.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . -40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . - 40°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VS+ = +12V, VS- = GND = 0V, see Figure 3, Full Bias (C0 = C1 = 0V), TA = +25°C, unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNIT
DYNAMIC PERFORMANCE
-3dB Bandwidth BW Figure 3, 2VP-P differential output at pins 180 MHz
Slew Rate SR Differential VOUT (VOUTA - VOUTB) from -5V
to +5V (10VP-P)
1200 V/µs
Total Harmonic Distortion THD, Low Frequency,
Light Load
200kHz, differential 12VP-P, across ≥350Ω
differential load
-88 -67 dBc
THD, Low Frequency,
Heavy Load
200kHz, differential 12VP-P, across 29Ω
differential load
-72 -68 dBc
THD, High Frequency,
Light Load
4MHz, differential 12VP-P
, across ≥350Ω
differential load
-64 -58 dBc
THD, High Frequency,
Heavy Load
4MHz, differential 12VP-P
, across 29Ω
differential load
-51 -48 dBc
Avg. Multi-Tone Power Ratio MTPR 2MHz to 50MHz, 25kHz tone spacing,
PLINE = 15.5dBm, CF = 15dB
-43 dBc
Off State Multi-Tone Power Ratio MTPR-OFF 2MHz to 50MHz, 25kHz tone spacing,
PLINE = 15.5dBm, CF = 15dB
-55 dBc
Non-inverting Input Spot Voltage Noise Eni F > 1MHz, spot noise voltage on INA+ and
INB+ inputs separately
6nV/√Hz
Non-inverting Input Spot Current Noise Ini+ F > 1MHz, spot noise current on INA+ and
INB+ inputs separately
13 pA/√Hz
Inverting Input Spot Current Noise Ini- F > 1MHz, spot noise current on INA- and
INB- inputs separately
50 pA/√Hz
DC AND INPUT CHARACTERISTICS
Non-Inverting Input Bias Current IB+ Non-inverting inputs, INA+ and INB+, at
mid-supply voltage (Note 7)
-7 2 7 µA
Non-Inverting Input Bias Current
Mismatch
IB+DM Difference between the INA+ and INB+
bias currents
-0.5 0 0.5 µA
Inverting Input Bias Current IB- Inverting inputs, INA- and INB-, at mid
supply voltage (Note 7)
-90 -30 55 µA
ISL15100
5FN8577.0
September 19, 2013
Inverting Input Bias Current Mismatch IB-DM Difference between the INA- and INB- input
bias currents
-35 0 35 µA
Inverting Input Bias Current Common
Mode
IB-CM Average inverting input bias currents
(Note 7)
-90 -30 55 µA
Input Offset Voltage VIOA, VIOB Voltage difference from INA+ to INA- and
from INB+ to INB-
-85 0 85 mV
Input Offset Voltage Mismatch VIODM VIOA - VIOB -5 0 5 mV
Input Offset Voltage Common Mode VIOCM Average offset voltage across the two
inputs
-80 20 80 mV
Differential Mode Output Offset Voltage VOSDM Output referred total effect of all
differential DC error terms
-7.8 0 7.8 mV
Common Mode Output Offset Voltage VOSCM Output referred total effect of all common
mode DC errors
-105 40 145 mV
Input Headroom to Positive Supply (VS+) - VIN(MAX) INA+ and INB+ required margin to VS+
supply
3V
Input Headroom to Negative Supply VIN(MIN) - (VS-) INA+ and INB+ required margin to VS-
supply
3V
OUTPUT CHARACTERISTICS
Output Swing VO-OPEN VS = ±6V, Differential RLOAD ≥ 1kΩ, each
output pin voltage range
±4.85 ±5.0 V
VO-LOADED VS = ±6V, VO in linear region, Differential
RLOAD = 29Ω, each output pin voltage
range.
±4.6 V
VS = ±6V, VO driven into the rail, differential
RLOAD = 29Ω, each output pin voltage
range.
±4.2 ±4.7 V
Output Current IOLinear output current (not short circuit) ±300 ±400 mA
POWER SUPPLY
Bipolar Supply Range ±VSSymmetric supply, pin 4 at GND for logic
reference
±4 ±6 ±6.6 V
Single Supply Range VS+Single supply with V
S- and pin 4 at GND 8 12 13.2 V
Positive Supply Currents IS+ (Full bias) VO(DIFF) = 0V, C0 = C1 = 0V 27 32 37 mA
IS+ (Medium bias) VO(DIFF) = 0V, C0 = 3.3V, C1 = 0V 19 23 26 mA
IS+ (Low bias) VO(DIFF) = 0V, C0 = 0V, C1 = 3.3V 12 15 18 mA
IS+ (Power down) C0 = C1 = 3.3V 5.5 7 8.5 mA
C0, C1 Input High Current IINH, C0 or C1C0 = C1 = 3.3V (Note 7) -150 -90 -30 µA
C0, C1 Input Low Current IINL, C0 or C1C0 = C1 = 0V (Note 7) -1.5 1 1.5 µA
C0, C1 Logic High Voltage VINH Pin 4 at GND, logic reference pin 2 3.3 5.5 V
C0, C1 Logic Low Voltage VINL Pin 4 at GND, logic reference pin -0.3 0 0.8 V
NOTES:
6. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design.
7. Positive currents flow out of the pin.
Electrical Specifications VS+ = +12V, VS- = GND = 0V, see Figure 3, Full Bias (C0 = C1 = 0V), TA = +25°C, unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNIT
ISL15100
6FN8577.0
September 19, 2013
Applications Information
Product Description
The ISL15100 is a differential operational amplifier designed for
line driving in power line communications (PLC). It is a low
distortion, current mode feedback amplifier that draws
moderately low supply current. Due to the current feedback
architecture, the ISL15100 closed-loop -3dB bandwidth is
dependent on the value of the feedback resistor. The desired
bandwidth is selected by choosing the feedback resistor, RF, and
then the gain is set by picking the gain resistor, RG.
Feedback Resistor Values
The ISL15100 has been designed and specified with RF=1kΩ
for AV = +16. As is the case with all current feedback amplifiers,
wider bandwidth at the expense of slight peaking, can be
obtained by reducing the value of the feedback resistor.
Inversely, larger values of the feedback resistor will cause rolloff
to occur at a lower frequency.
Quiescent Current vs Temperature
The ISL15100 was designed to have the quiescent current
increase with temperature, which maintains good distortion
performance at high temperatures.
Supply Voltage Range
The ISL15100 operates with bipolar supply voltages from ±4.0V
to ±6.6V (±6.65V maximum). Optimum bandwidth, slew rate,
and video characteristics are obtained at higher supply voltages.
Single Supply Operation
If a single supply is desired, values from +8.0V to +13.2V (+13.3V
maximum) can be used as long as the input common mode
range is not exceeded. When using a single supply, be sure to
either:
1. DC bias the inputs at an appropriate common mode voltage
and AC-couple the signal.
2. Ensure the driving signal is within the common mode range of
the ISL15100.
Multi-Tone Power Ratio (MTPR)
G.hn PLC uses OFDM modulation to digitally encode data for
communication. A carrier spacing of 24.41kHz is used in power
lines, and 48.82kHz is used in phone lines.
In multi-tone signaling, linearity is shown in the MTPR
measurement. MTPR measures the difference in power of a
carrier tone vs. a missing tone.
Figure 4 shows ISL15100's MTPR performance for a narrow
frequency span.
Disable Linearity
Unlike DSL, communication in PLC systems is half duplex
meaning only one device can transmit at a time. When the line
driver is not transmitting, it is disabled and the receiver is
enabled. Figure 5 shows the shared transmit and receive signal
path of two ends. When Txa is transmitting, optimal MTPR is
achieved if Txb is removed. Since Txb cannot be removed, the
best MTPR occurs if the line driver is a very high impedance
when disabled.
RBM are resistors to limit fault currents, and to provide a driving
impedance to the transformer, thus setting its frequency span.
RBM is typically low in value (<10Ω).
-100
-90
-80
-70
-60
-50
-40
-30
1.50 1.52 1.54 1.56 1.58 1.60
TONE POWER (dBm)
FREQUENCY (MHz)
MTPR
FIGURE 4. PLC SIGNAL TONES WITH 25kHz SPACING
FIGURE 5. Tx AND Rx SIGNAL PATH. CASE1:[Txa: ON, Rxa: OFF, Txb: OFF, Rxb: ON]. CASE2:[Txa: OFF, Rxa: ON, Txb: ON, Rxb: OFF]
ISL15100
7FN8577.0
September 19, 2013
PC Board Design Recommendation
To minimize parasitic capacitance in the ISL15100 design,
consider laying out short output traces. Also, select low
capacitance protection devices, and use line transformers with
low interwinding capacitance in the signal path.
The supply decoupling capacitors must be close to the supply
pins to minimize parasitic inductance in the supply paths. High
frequency load currents are pulled through these capacitors, so
placement of the 0.1µF capacitors close to the supply pin(s)
improves dynamic performance. The higher value 4.7µF
capacitors provide low frequency decoupling, so they can be
placed farther from the supply pins.
The ISL15100’s thermal pad (EP) should be connected to VS-
(ground in single supply applications). For good thermal control,
include a thermal pad in the layout footprint, as shown in the
“Typical Recommended Land Pattern” on the “Package Outline
Drawing” page. Adding vias to this thermal pad helps dissipate
heat away from the package. The ISL15100 evaluation board
uses four 10mil (hole size) vias with 20mil diameter pads.
Thermal Resistance and Power Dissipation
Thermal resistance for junction to ambient, TJA, is +53°C/W. The
power dissipation at 12V supply is 600mW. The ambient
temperature allowed given the maximum junction temperature
of +150°C is:
TATJθJA Pd×–= (EQ. 1)
TA+150°C53°CW⁄()–∗600mW +118°C==
INA
OUTA OUTB
1 4
SW1:1
2 3
SW1:2
VS+
C2
0.1uf
C4
0.1uf
RSB
49.9
R11
10K
RFB
1k
RFA
1k
RSA
49.9
C1
4.7uF
C3
4.7uF
Rext3
22 2W
Rext4
56.2
Rext1
243
Rext2
243
+
+
NC
1
2
3
GND
4
NC
5
NC
6
VS-
7
C0
8
C1 9
10
11
NC 12
13
VS+ 14
NC 15
16
__
+
+U1
ISL15100IRZ
S/N=CMHZ5229B
INB
R1
0
R2
0
L2
L1
TP2
D4
OPEN
D3
OPEN
D1
OPEN
D2
OPEN
RGA
OPEN
RGB
OPEN
RLB
3.9 1/4 W
RLA
3.9 1/4 W
R4
0
RCG
133
R3
0
D5
4.3V ZENER DIODE
2.9V@ 300 uA
J1
VS+
J2
GND
J3
VS-
VS+
VS-
VS-
VS+ VS+
VS+
VS-
TP5
GND
TP4
GND
TP1
TP9
INA
TP10
INB
TP12
VS+
TP13
VS-
TP14
GND
R9
100
R10
100
FIGURE 6. ISL15100 EVALUATION BOARD
ISL15100
8
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8577.0
September 19, 2013
For additional products, see www.intersil.com/en/products.html
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE REVISION CHANGE
September 19 2013 FN8577.0 Initial Release.
ISL15100
9FN8577.0
September 19, 2013
Package Outline Drawing
L16.4x4H
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 1/12
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VI EW
SEE DETAIL "X"
0.30 ±0.05
BASE PLANE
PIN #1
5
8
( 3 . 6 TYP )
(12x0.65)
(16x0.30) 0 . 20 REF
+0.03/-0.02
C5
4
0.10 CM
INDEX AREA
(4X) 0.15
PIN 1
6
4.00
12
4.00
9
AB
4
0.65
12X
13
4X 1.95
16
1
6
C
SEATING PLANE
0.10 C
AB
16x 0.550±0.05
2.40
( 2.40)
0.90±0.10
(16x0.75)
2.40
INDEX AREA
