1. General description
The HEF4052B is a dual 4-channel analog multiplexer/demultiplexer with common
channel select logic. Each multiplexer/demultiplexer has four independent inputs/outputs
(nY0 to nY3) and a common input/o utput (nZ). Th e common chan nel select logic includes
two select inputs (S1 and S2) and an active LOW enable input (E). Both
multiplexers/demu ltipl exers contain four b idire ctional ana log switch es, each with one side
connected to an independent input/outpu t (nY0 to nY3) and the other side connected to a
common input/output (nZ). With E LOW, one of the four switches is selected
(low-impedance ON-state) by S1 and S2. With E HIGH, all switches are in the
high-impedance OFF-state, independe nt of S1 and S2. If break before make is needed,
then it is necessary to use the enable input.
VDD and VSS are the supply voltage connections for the digital control inputs (S1 and S2,
and E). The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (nY0 to nY3, and
nZ) can swing between VDD as a positive limit and VEE as a negative limit. VDD −VEE may
not exceed 15 V. Unused inputs must be connec te d to V DD, VSS, or anot he r inp u t. Fo r
operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically
ground). VEE and VSS are the supply voltage connections for the switches.
The HEF4052B is suitable for use over both the industrial (−40 °C to +85 °C) and
automotive (−40 °C to +125 °C) temperature ranges.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the automotive temperature range −40 °C to +125 °C
Complies with JEDEC standard JESD 13-B
3. Applications
Industrial and automotive
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
Rev. 07 — 26 March 2010 Product data sheet
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 2 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
4. Ordering information
5. Functional diagram
Ta ble 1. Ordering information
All types operate from
−
40
°
C to +125
°
C.
Type number Package
Name Description Version
HEF4052BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4052BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
HEF4052BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
Fig 1. Functional di agram
mnb042
1 - OF - 4
DECODER
LOGIC
LEVEL
CONVERSION
78
VEE
VSS
VDD
12
13
16
3
14
15
11
10
9
6
S1
S2
E
1
5
2
1Y0
1Z
2Z
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
4
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 3 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
Fig 2. Schematic diagram (on e sw itc h )
001aak60
4
nYn
nZ
VEE
VDD VDD
Fig 3. Logic symbol Fig 4. IEC logic symbol
001aak60
5
4
2
5
1
11
15
14
12
13
3
6
9
1Z
S1
S2
E
2Z
2Y3
2Y2
2Y1
2Y0
1Y3
1Y2
1Y1
1Y0
10
mnb041
11
15
14
12
4
2
5
91
10 0
6G4
MDX
0
3
4 ×
1
3
2
1
0
13
3
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 4 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
Fig 5. Logic diag ram
001aak634
LEVEL
CONVERTER
LEVEL
CONVERTER
LEVEL
CONVERTER
S1
S2
E
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
2Z
1Z
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 5 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 6. Pin configuration SOT38-4 and SOT109-1 Fig 7. Pin configu ration SOT338-1 and SOT403-1
001aag215
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
HEF4052B
2Y0 V
DD
2Y2 1Y2
2Z 1Y1
2Y3 1Z
2Y1 1Y0
E 1Y3
V
EE
S1
V
SS
S2
HEF4052B
2Y0 V
DD
2Y2 1Y2
2Z 1Y1
2Y3 1Z
2Y1 1Y0
E 1Y3
V
EE
S1
V
SS
S2
001aak606
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
E6 enable input (active LOW)
VEE 7 supply voltage
VSS 8 ground supply voltage
S1, S2 10, 9 select input
1Y0, 1Y1, 1Y2, 1Y3, 2Y0, 2Y1, 2Y2, 2Y3 12, 14, 15, 11, 1, 5, 2, 4 independent input or output
1Z, 2Z 13, 3 common output or input
VDD 16 supply voltage
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 6 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
7. Functional description
7.1 Function table
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
8. Limiting values
[1] To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional
switch must not exceed 0.4 V . If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there
is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE.
[2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
For SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 °C.
Table 3. Function table[1]
Input Channel on
ES2 S1
LLLnY0 to nZ
L L H nY1 to nZ
LHLnY2 to nZ
LHHnY3 to nZ
H X X switches off
Table 4. L imiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage −0.5 +18 V
VEE supply voltage referenced to VDD [1] −18 +0.5 V
IIK input clamping current pins Sn and E;
VI<−0.5 V or VI>V
DD + 0.5 V -±10 mA
VIinput voltage −0.5 VDD + 0.5 V
II/O input/output current - ±10 mA
IDD supply current - 50 mA
Tstg storage temperature −65 +150 °C
Tamb ambient temperature −40 +125 °C
Ptot total power dissipation Tamb = −40 °C to +125 °C[2]
DIP16 package - 750 mW
SO16 package - 500 mW
TSSOP16 package - 500 mW
P power dissipation per output - 100 mW
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 7 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage see Figure 8 3- 15V
VIinput voltage 0 - VDD V
Tamb ambient temperature in free air −40 - +125 °C
Δt/ΔV input transition rise and fall
rate VDD = 5 V - - 3.75 μs/V
VDD = 10 V - - 0.5 μs/V
VDD = 15 V - - 0.08 μs/V
Fig 8. Operating area as a function of the supply volt ages
VDD − VEE (V)
015510
001aac285
10
5
15
VDD − VSS
(V)
0
operating area
Table 6. Static characteristics
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °C Tamb = 125 °CUnit
Min Max Min Max Min Max Min Max
VIH HIGH-level
input voltage |IO| < 1 μA 5 V 3.5 - 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
VIL LOW-level
input voltage |IO| < 1 μA 5 V - 1.5 - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 - 4.0 V
IIinput leakage
current 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 μA
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 8 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
10.1 Test circuits
IS(OFF) OFF-state
leakage
current
Z port;
all channels OFF;
see Figure 9
15 V - - - 1000 - - - - nA
Y port;
per channel;
see Figure 10
15 V - - - 200 - - - - nA
IDD supply current IO = 0 A 5 V - 5 - 5 - 150 - 150 μA
10 V - 10 - 10 - 300 - 300 μA
15 V - 20 - 20 - 600 - 600 μA
CIinput
capacitance Sn, E inputs - - - - 7.5 - - - - pF
Table 6. Static characteristics …continued
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °C Tamb = 125 °CUnit
Min Max Min Max Min Max Min Max
Fig 9. Test circuit for measuring OFF-state leakage current Z port
I
S
001aak63
5
V
DD
VI
V
SS
= V
EE
S1 and S2
E
nZ
V
DD
or V
SS
V
DD
nYn
VO
Fig 10. Test circuit for measuring OFF-state leakage current nYn port
IS
001aak63
6
VSS
VO
switch
VSS = VEE
S1 and S2
E
nZ
nY0
VDD or VSS
VDD
nYn
1
2
VI
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 9 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
10.2 On resistance
10.2.1 On resistance waveform and test circuit
Table 7. ON resistance
Tamb = 25
°
C; ISW =200
μ
A; VSS = VEE = 0 V.
Symbol Parameter Conditions VDD − VEE Typ Max Unit
RON(peak) ON resistance (peak) VI = 0 V to VDD − VEE;
see Figure 11 and Figure 12 5 V 350 2500 Ω
10 V 80 245 Ω
15 V 60 175 Ω
RON(rail) ON resistance (rail) VI = 0 V; see Figure 11 and Figure 12 5 V 115 340 Ω
10 V 50 160 Ω
15 V 40 115 Ω
VI = VDD − VEE;
see Figure 11 and Figure 12 5 V 120 365 Ω
10 V 65 200 Ω
15 V 50 155 Ω
ΔRON ON resistance mismatch
between channel s VI = 0 V to VDD − VEE; see Figure 11 5 V 25 - Ω
10 V 10 - Ω
15 V 5 - Ω
RON =V
SW /I
SW.
Fig 11. Test circuit for measuring RON
V
001aak63
7
V
SS
VI
VSW
ISW
V
SS
= V
EE
S1 and S2
E
nZ
V
DD
or V
SS
V
DD
nYn
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 10 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
Fig 12. Typical RON as a function of input voltage
VI (V)
015510
001aae648
200
300
100
400
RON
(Ω)
0
VDD = 5 V
10 V
15 V
Table 8. Dynamic characteristics
Tamb = 25
°
C; VSS = VEE = 0 V; for test circuit see Figure 16.
Symbol Parameter Conditions VDD Typ Max Unit
tPHL HIGH to LOW propagation delay nYn, nZ to nZ, nYn; see Figure 13 5 V 1020ns
10 V 5 10 ns
15 V 5 10 ns
Sn to nYn, nZ; see Figure 14 5 V 150 305 ns
10 V 65 135 ns
15 V 50 100 ns
tPLH LOW to HIGH propagation delay Yn, nZ to nZ, nYn; see Figure 13 5 V 1020ns
10 V 5 10 ns
15 V 5 10 ns
Sn to nYn, nZ; see Figure 14 5 V 150 300 ns
10 V 75 150 ns
15 V 50 100 ns
tPHZ HIGH to OFF-state
propagation delay Eto nYn, nZ; see Figure 15 5 V 95 190 ns
10 V 90 180 ns
15 V 85 180 ns
tPZH OFF-state to HIGH
propagation delay Eto nYn, nZ; see Figure 15 5 V 130 260 ns
10 V 55 115 ns
15 V 4585ns
tPLZ LOW to OFF-state
propagation delay Eto nYn, nZ; see Figure 15 5 V 100 205 ns
10 V 90 180 ns
15 V 90 180 ns
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 11 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
11.1 Waveforms and test circuit
tPZL OFF-state to LOW
propagation delay Eto nYn, nZ; see Figure 15 5 V 120 240 ns
10 V 50 100 ns
15 V 3575ns
Table 8. Dynamic characteristics …continued
Tamb = 25
°
C; VSS = VEE = 0 V; for test circuit see Figure 16.
Symbol Parameter Conditions VDD Typ Max Unit
Measurement points are given in Table 9. Measurement points are given in Table 9.
Fig 13. nYn, nZ to nZ, nYn propagation delays Fig 14. Sn to nYn, nZ propagation delays
001aac29
0
nYn or nZ
input
nZ or nYn
output
t
PLH
t
PHL
V
DD
V
EE
V
M
V
M
V
O
V
EE
001aac29
1
switch ON
tPLH tPHL
switch OFF
VDD
VSS
VO
VEE
nYn or nZ
output
Sn input
switch OFF
10 %
90 %
VM
Measurement points are given in Table 9.
Fig 15. Enabl e and disable times
001aac29
2
t
PLZ
t
PHZ
switch OFF switch ONswitch ON
nYn or nZ output
LOW-to-OFF
OFF-to-LOW
nYn or nZ output
HIGH-to-OFF
OFF-to-HIGH
E input
V
O
V
O
V
EE
V
EE
V
DD
V
SS
V
M
t
PZL
t
PZH
90 %
90 %
10 %
10 %
Table 9. Mea surement points
Supply voltage Input Output
VDD VMVM
5 V to 15 V 0.5VDD 0.5VDD
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 12 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
[1] For nYn to nZ propagation delays use VEE. For Sn to nYn or nZ propagation delays use VDD.
Test data is given in Table 10.
Definitions:
DUT = Device Under Test.
RT= Termination resistance should be equal to output impedance Zo of the pulse generator.
CL= Load capacitance including test jig and probe.
RL= Load resistance.
Fig 16. Test circuit for measuring switching times
001aaj90
3
VIVO
RTCL
RLS1
DUT
PULSE
GENERATOR
tW
VM
VI
VI
VDD
VDD
VSS
VEE
open
0 V
negative
pulse
VI
0 V
positive
pulse
10 %
90 %
90 %
10 %
VM
VM
VM
tW
tf
tf
tr
tr
Table 10. Test data
Input Load S1 position
nYn, nZ Sn and E tr, tfVMCLRLtPHL[1] tPLH tPZH, tPHZ tPZL, tPLZ other
VDD or VEE VDD or VSS ≤ 20 ns 0.5VDD 50 pF 10 kΩVDD or VEE VEE VEE VDD VEE
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 13 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
11.2 Additional dynamic parameters
[1] fi is biased at 0.5 VDD; VI=0.5V
DD (p-p).
11.2.1 Test circuits
Table 11. Additional dynamic characte ristics
VSS = VEE = 0 V; Tamb = 25
°
C.
Symbol Parameter Conditions VDD Typ Max Unit
THD total harmonic distortion see Figure 17; RL=10kΩ; CL=15pF;
channel ON; VI=0.5V
DD (p-p);
fi=1kHz
5 V [1] 0.25 - %
10 V [1] 0.04 - %
15 V [1] 0.04 - %
f(−3dB) −3 dB frequency response see Figure 18; RL = 1 kΩ; CL = 5 pF;
channel ON; VI=0.5V
DD (p-p) 5 V [1] 13 - MHz
10 V [1] 40 - MHz
15 V [1] 70 - MHz
αiso isolation (OFF-state) see Figure 19; fi= 1 MHz; RL = 1 kΩ;
CL = 5 pF; channel OFF;
VI=0.5V
DD (p-p)
10 V [1] −50 - dB
Vct crosstalk voltage digital inputs to switch; see Figure 20;
RL = 10 kΩ; CL=15pF;
Eor Sn = VDD (square-wave)
10 V 50 - mV
Xtalk crosstalk between switches; see Figure 21;
fi= 1 MHz; RL=1 kΩ;
VI=0.5V
DD (p-p)
10 V [1] −50 - dB
Table 12. Dynamic power dissipation PD
PD can be calculated from the formulas shown; VEE = V SS =0 V; t
r = tf
≤
20 ns; Tamb = 25
°
C.
Symbol Parameter VDD Typical formula for PD (μW) where:
PDdynamic power
dissipation 5V P
D = 1300 × fi + Σ(fo × CL) × VDD2fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
Σ(CL × fo) = sum of the outputs.
10 V PD = 6100 × fi + Σ(fo × CL) × VDD2
15 V PD = 15600 × fi + Σ(fo × CL) × VDD2
Fig 17. Test circuit for measuring total harmonic
distortion Fig 18. Test circuit for measuring frequency response
D
001aak63
8
VSS
fi
RLCL
VSS = VEE
S1 and S2
E
nZ
VDD or VSS
VDD
nYn
dB
001aak63
9
VSS
fi
RLCL
VSS = VEE
S1 and S2
E
nZ
VDD or VSS
VDD
nYn
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 14 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
Fig 19. Test circuit for measuring isol ati on (OFF-state)
dB
001aak65
7
VSS
fi
RLCL
switch
VSS = VEE
S1 and S2
E
nZ
nY0
VDD or VSS
VDD
nYn
1
2
a. Test circuit
b. Input and output pulse definitions
Fig 20. Test circuit for measuring crosstalk voltage between digital inputs and switch
001aak658
VDD or VSS
0.5VDD
switch
VSS = VEE
S1 and S2
E
nZ
nY0
VDD
nYn
1
2
GV
RL
RL
CLVO
001aaj90
8
on
V
O
V
ct
off off
logic
input (Sn, E)
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 15 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
a. Switch closed condition b. Switch open condition
Fig 21. Test circuit for measuring crosstalk between switches
001aak65
9
VSS VO
RLRL
VSS = VEE
S1 and S2
E
nZ
nY0
VDD or VSS
VDD
nYn
VI
001aak66
0
VSS VI
RL
RL
VSS = VEE
S1 and S2
E
nZ
nY0
VDD or VSS
VDD
nYn
VO
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 16 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
12. Package outline
Fig 22. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05 0.2542.54 7.62 8.25
7.80
10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051
0.021
0.015
0.014
0.009
1.25
0.85
0.049
0.033
0.77
0.73
0.26
0.24
0.14
0.12 0.010.1 0.3 0.32
0.31
0.39
0.33 0.030.17 0.02 0.13
D
IP16: plastic dual in-line package; 16 leads (300 mil) SOT38
-4
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 17 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
Fig 23. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10
1.45
1.25 0.25 0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8 1.27 6.2
5.8
0.7
0.6
0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004
0.057
0.049 0.01 0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15 0.05
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
S
O16: plastic small outline package; 16 leads; body width 3.9 mm SOT109
-1
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 18 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
Fig 24. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3 0.65 6.6
6.2
0.4
0.3
0.40
0.06
8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403
-1
A
max.
1.1
pin 1 index
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 19 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
13. Revision history
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4052B_7 20100326 Product data sheet - HEF4052B_6
HEF4052B_6 20100308 Product data sheet - HEF4052B_5
Modifications: •Table 6 “Static characteristics”: Conditions VIL and VIH corrected.
HEF4052B_5 20091127 Product data sheet - HEF4052B_4
HEF4052B_4 20090924 Product data sheet - HEF4052B_CNV_3
HEF4052B_CNV_3 19950101 Product specification - HEF4052B_CNV_2
HEF4052B_CNV_2 19950101 Product specification - -
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 20 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict wit h the short data sheet, the
full data sheet shall pre va il.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
suitable for use in medica l, military, aircraft, space or life support equipmen t,
nor in applications where failure or malf unction of an NXP Semiconductor s
product can reasonably be expected to result in personal injury, death or
severe property or environment a l damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application /use or t he application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Appl ica tion plann ed. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and t he
product. NXP Semiconductors does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter m s and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from national authorities.
14.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
HEF4052B_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 26 March 2010 21 of 22
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 March 2010
Document identifier: HEF4052B_7
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 6
7.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Recommended operating conditions. . . . . . . . 7
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
10.2 On resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 9
10.2.1 On resistance waveform and test circuit. . . . . . 9
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
11.1 Waveforms and test circuit . . . . . . . . . . . . . . . 11
11.2 Additional dynamic parameters . . . . . . . . . . . 13
11.2.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15 Contact information. . . . . . . . . . . . . . . . . . . . . 21
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
