73S8024RN
Low-Cost Smart Card Interface
DATA SHEET
Rev. 2 1
19-5404; Rev 2; 6/12
DESCRIPTION
The 73S8024RN is a single smart card (ICC) interface IC
that can be controlled by a dedicated control bus. The
73S8024RN has been designed to provide full electrical
compliance with ISO 7816-3, EMV 4.0 (EMV2000) and
NDS specifications.
Interfacing with the system controller is done through a
control bus, composed of digital inputs to control the
interface, and one interrupt output to inform the system
controller of the card presence and faults.
The card clock can be generated by an on-chip oscillator
using an external crystal or by connection to a clock
signal.
The 73S8024RN incorporates an ISO 7816-3
activation/deactivation sequencer that controls the card
signals. Level-shifters drive the card signals with the
selected card voltage (3V or 5V), coming from an internal
Low Drop-Out (LDO) voltage regulator. This LDO
regulator is powered by a dedicated power supply input
VPC. Digital circuitry is separately powered by a digital
power supply VDD.
With its embedded LDO regulator, the 73S8024RN is a
cost effective solution for any application where a 5V
(typically -5% +10%) power supply is available.
Hardware support for auxiliary I/O lines, C4 / C8 contacts,
is provided*.
Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the protection
circuitry. The fault can be a card over-current, a VDD
(digital power supply)**, a VPC (regulator power supply), a
VCC (card power supply) or an over-heating fault.
The card over-current circuitry is a true current detection
function, as opposed to VCC voltage drop detection, as
usually implemented in ICC interface ICs.
The VDD voltage fault has a threshold voltage that can be
adjusted with an external resistor or resistor network. It
allows automated card deactivation at a customized VDD
voltage threshold value. It can be used, for instance, to
match the system controller operating voltage range.
APPLICATIONS
• Set-Top-Box Conditional Access and Pay-per-
View
• Point of Sales and Transaction Terminals
• Control Access and Identification
* Pins/functions not available on 20-pin QFN package.
** User VDD_FLT threshold configuration not available on
20-pin QFN package.
ADVANTAGES
• Traditional step-up converter is replaced by a LDO
regulator:
Greatly reduced power dissipation
Fewer external components are required
Better noise performance
High current capability (90mA supplied to the card)
• SO28 package is pin-to-pin compatible with
industry-standard TDA8004 and TDA8024
• Card clock STOP (high and low) mode
• Small format (4x4x0.85mm) 20QFN package option
• True card over-current detection
FEATURES
• Card Interface:
Complies with ISO 7816-3, EMV 4.0, and NDS
An LDO voltage regulator provides 3V / 5V to the
card from an external power supply input
Provides at least 90mA to the card
ISO 7816-3 Activation / Deactivation sequencer with
emergency automated deactivation on card removal
or fault detected by the protection circuitry
Protection includes 3 voltage supervisors that detect
voltage drops on VCC (card), VDD (digital)**, and VPC
(regulator) power supplies
The VDD voltage supervisor threshold value can be
externally adjusted**
Over-current detection 150mA max
Card clock stop high or low*
2 card detection inputs, 1 for each possible user
polarity
Auxiliary I/O lines, for C4 / C8 contact signals*
Card CLK clock frequency up to 20MHz
• System Controller Interface:
3 Digital inputs control the card activation /
deactivation, card reset and card voltage
4 Digital inputs control the card clock (division rate
and card clock stop modes)
1 Digital output, interrupt to the system controller,
allows the system controller to monitor the card
presence and faults.
Crystal oscillator or host clock, up to 27MHz
• Regulator Power Supply:
4.75V to 5.5V (EMV 4.0)
4.85V to 5.5V (NDS)
• Digital Interfacing: 2.7V to 5.5V
• ±6kV ESD Protection on the card interface
• Package: SO28, 20QFN or 32QFN
73S8024RN Data Sheet DS_8024RN_020
2 Rev. 2
FUNCTIONAL DIAGRAM
Pin numbers reference the 28SO package.
[Pin numbers] reference the 32QFN package.
{Pin numbers} reference the 20QFN package.
Figure 1: 73S8024RN Block Diagram
ICC I/O BUFFERS
DIGITAL POWER SUPPLY
VDD VOLTAGE SUPERVISOR
VOLTAGE REFERENCE
XTAL
OSC
CLOCK
GENERATION
DIGITAL
CIRCUITRY
&
FAULT LOGIC
V
DD
FAULT
V
CC
FAULT
V
PC
FAULT
Int_Clk
VDD VPC
VCC
RST
CLK
PRES
PRES
XTALIN
XTALOUT
CLKDIV1
CLKDIV2
GND
TEMP FAULT
CLKSTOP
{18} [29] 1
{19} [30] 2
{20} [31] 3
5 [2,9,16,25,32]
6
[4] 7
9 [6] {3}
10 [7] {4}
11 [8] {5}
12 [10]
13 [11]
14 [12] {6}
15 [13] {7}
17 [15] {9}
16 [14] {8}
21 [20] {12}
{11} [19] 20
{10} [18] 19
18 [17]
{17} [26] 26
{16} [24] 25
{15} [23] 24
{14} [22] 23
[28]
28
[27]
27
{13} [21] 22
ISO-7816
SEQUENCER
R-C
OSC.
LDO
REGULATOR
&
VOLTAGE
SUPERVISORS
ICC RESET
BUFFER
ICC CLOCK
BUFFER
OVER
TEMP
CLKLEV
I/O
AUX1
AUX2
I/OUC
AUX1UC
AUX2UC
GND
VDDF_ADJ
RSTIN
CMDVCC
5V/3V
OFF
[5] 8
GND
4 [1] {1}
NC
6 [3] {2}
I
CC
FAULT
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 3
Table of Contents
1 Pin Description ...............................................................................................................................5
2 System Controller Interface ...........................................................................................................7
3 Power Supply and Voltage Supervision ........................................................................................8
4 Card Power Supply ........................................................................................................................9
5 Over-Temperature Monitor.............................................................................................................9
6 On-Chip Oscillator and Card Clock ...............................................................................................9
7 Activation Sequence .................................................................................................................... 10
8 Deactivation Sequence ................................................................................................................ 12
9 OFF and Fault Detection .............................................................................................................. 13
10 I/O Circuitry and Timing ............................................................................................................... 13
11 Typical Application Schematic .................................................................................................... 15
12 Electrical Specification ................................................................................................................ 16
12.1 Absolute Maximum Ratings .................................................................................................... 16
12.2 Recommended Operating Conditions ..................................................................................... 16
12.3 Package Thermal Parameters ................................................................................................ 16
12.4 Smart Card Interface Requirements ........................................................................................ 17
12.5 Characteristics: Digital Signals................................................................................................ 19
12.6 DC Characteristics.................................................................................................................. 20
12.7 Voltage / Temperature Fault Detection Circuits ....................................................................... 20
13 Mechanical Drawing (20QFN) ...................................................................................................... 21
14 Package Pin Designation (20QFN)............................................................................................... 22
15 Mechanical Drawing (32QFN) ...................................................................................................... 23
16 Package Pin Designation (32QFN)............................................................................................... 24
17 Mechanical Drawing (SO) ............................................................................................................. 25
18 Package Pin Designation (SO) ..................................................................................................... 25
19 Ordering Information.................................................................................................................... 26
20 Related Documentation................................................................................................................ 26
21 Contact Information ..................................................................................................................... 26
Revision History ................................................................................................................................... 27
73S8024RN Data Sheet DS_8024RN_020
4 Rev. 2
Figures
Figure 1: 73S8024RN Block Diagram ...................................................................................................... 2
Figure 2: Activation Sequence – RSTIN Low When CMDVCC Goes Low .............................................. 10
Figure 3: Activation Sequence – RSTIN High When CMDVCCB Goes Low ........................................... 11
Figure 4: Deactivation Sequence ........................................................................................................... 12
Figure 5: Timing Diagram – Management of the Interrupt Line OFF ....................................................... 13
Figure 6: I/O and I/OUC State Diagram ................................................................................................. 14
Figure 7: I/O – I/OUC Delays Timing Diagram ....................................................................................... 14
Figure 8: 73S8024RN – Typical Application Schematic.......................................................................... 15
Figure 9: 20QFN Mechanical Drawing ................................................................................................... 21
Figure 10: 20QFN Pin Out ..................................................................................................................... 22
Figure 11: 32QFN Mechanical Drawing ................................................................................................. 23
Figure 12: 32QFN Pin Out ..................................................................................................................... 24
Tables
Table 1: Choice of VCC Pin Capacitor ....................................................................................................... 9
Table 2: Card Clock Frequency ............................................................................................................... 9
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 5
1 Pin Description
CARD INTERFACE
Name
Pin
28SO
Pin
20QFN
Pin
32QFN
Description
I/O
11
5
8
Card I/O: Data signal to/from card. Includes a pull-up
resistor to VCC.
AUX1
13
–
11
AUX1: Auxiliary data signal to/from card. Includes a
pull-up resistor to VCC.
AUX2
12
–
10
AUX2: Auxiliary data signal to/from card. Includes a
pull-up resistor to VCC.
RST
16
8
14
Card reset: provides reset (RST) signal to card.
CLK
15
7
13
Card clock: provides clock signal (CLK) to card. The rate
of this clock is determined by the external crystal
frequency or frequency of the external clock signal applied
on XTALIN and CLKDIV selections.
PRES
10
4
7
Card Presence switch: active high indicates card is
present. Should be tied to GND when not used, but it
Includes a high-impedance pull-down current source.
PRES
9
3
6
Card Presence switch: active low indicates card is
present. Should be tied to VDD when not used, but it
Includes a high-impedance pull-up current source.
VCC
17
9
15
Card power supply – logically controlled by sequencer,
output of LDO regulator. Requires an external filter
capacitor to the card GND.
GND
14
6
12
Card ground.
MISCELLANEOUS INPUTS AND OUTPUTS
Name
Pin
28SO
Pin
20QFN
Pin
32QFN
Description
XTALIN
24
15
23
Crystal oscillator input: can either be connected to crystal
or driven as a source for the card clock.
XTALOUT
25
16
24
Crystal oscillator output: connected to crystal. Left open
if XTALIN is being used as external clock input.
VDDF_ADJ
18
–
17
V
DD
fault threshold adjustment input: this pin can be used
to adjust the VDDF values (that controls deactivation of the
card). Must be left open if unused.
NC
5
–
2, 9,
16, 25,
32
Non-connected pin.
POWER SUPPLY AND GROUND
Name
Pin
28SO
Pin
20QFN
Pin
32QFN
Description
VDD
21
12
20
System interface supply voltage and supply voltage for
internal circuitry.
VPC
6
2
3
LDO regulator power supply source.
GND
4
1
1
LDO Regulator ground.
GND
22
13
21
Digital ground.
73S8024RN Data Sheet DS_8024RN_020
6 Rev. 2
MICROCONTROLLER INTERFACE
Name
Pin
28SO
Pin
20QFN
Pin
32QFN
Description
CMDVCC
19
10
18
Command VCC (negative assertion): Logic low on this pin
causes the LDO regulator to ramp the VCC supply to the
card and initiates a card activation sequence, if a card is
present.
5V/#V
3
20
31
5 volt / 3 volt card selection: Logic one selects 5 volts for
VCC and card interface, logic low selects 3 volt operation.
When the part is to be used with a single card voltage,
this pin should be tied to either GND or VDD. However, it
includes a high impedance pull-up resistor to default this
pin high (selection of 5V card) when not connected.
CLKSTOP
7
–
4
Stops the card clock signal during a card session when
set high (card clock STOP mode). Internal pull-down
resistor allows this pin to be left as an open circuit if the
clock STOP mode is not used.
CLKLVL
8
–
5
Sets the logic level of the card clock STOP mode when
the clock is de-activated by setting pin 7 high. Logic low
selects card STOP low. Logic high selects card STOP
high. Internal pull-down resistor allows this pin to be left
as an open circuit if the clock STOP mode is not used.
CLKDIV1
CLKDIV2
1
2
18
19
29
30
Sets the divide ratio from the XTAL oscillator (or external
clock input) to the card clock. These pins include
pull-down resistors.
CLKDIV1 CLKDIV2 CLOCK RATE
0 0 XTALIN/8
0 1 XTALIN/4
1 1 XTALIN/2
1 0 XTALIN
OFF
23
14
22
Interrupt signal to the processor. Active Low - Multi-
function indicating fault conditions and card presence.
Open drain output configuration. It includes an internal
21kΩ pull-up to VDD.
RSTIN
20
11
19
Reset Input: This signal is the reset command to the card.
I/OUC
26
17
26
System controller data I/O to/from the card. Includes a
pull-up resistor to VDD.
AUX1UC
27
–
27
System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to VDD.
AUX2UC
28
–
28
System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to VDD.
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 7
2 System Controller Interface
Three separated digital inputs allow direct control of the card interface from the host as follows:
• Pin CMDVCC: When low, starts an activation sequence.
• Pin RSTIN: controls the card Reset signal (when enabled by the sequencer).
• Pin 5V/#V: Defines the card voltage.
Card clock is controlled by four digital inputs:
• CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input clock
frequency (crystal or external clock).
• CLKSTOP (active high) allows card power down mode by stopping the card clock.
• CLKLEV defines the card clock level of the card power down mode.
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the
card presence only (Low = No card in the reader). When CMDVCC is set low (Card activation sequence
requested from the host), low level on OFF means a fault has been detected (e.g. card removal during
card session, or voltage fault, or thermal / over-current fault) that automatically initiates a deactivation
sequence.
73S8024RN Data Sheet DS_8024RN_020
8 Rev. 2
3 Power Supply and Voltage Supervision
The 73S8024RN smart card interface IC incorporates a LDO voltage regulator. The voltage output is
controlled by the digital input 5V/#V. This regulator is able to provide either 3V or 5V card voltage from
the power supply applied on the VPC pin.
Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage
range to interface with the system controller.
Three voltage supervisors constantly check the presence of the voltages VDD, VPC and VCC. A card
deactivation sequence is forced upon fault of any of these voltage supervisors. The two voltage
supervisors for VPC and VCC are linked so that a fault is generated to activate a deactivation sequence
when the voltage VPC becomes lower than VCC. It allows the 73S8024RN to operate at lower VPC voltage
when using 3V cards only. The voltage regulator can provide a current of at least 90mA on VCC that
comply easily with EMV 4.0 and NDS specifications. The VPC voltage supervisor threshold values are
defined from applicable standards (EMV and NDS). A third voltage supervisor monitors the VDD voltage.
It is used to initialize the ISO 7816-3 sequencer at power-on, and to deactivate the card at power-off or
upon fault. The voltage threshold of the VDD voltage supervisor is internally set by default to 2.3V
nominal. However, it may be desirable, in some applications, to modify this threshold value. The pin
VDDF_ADJ (pin 18 in the SO package, pin 17 in the 32QFN package, not supported in the 20QFN
package) is used to connect an external resistor REXT to ground to raise the VDD fault voltage to another
value VDDF. The resistor value is defined as follows:
REXT= 56kΩ /(VDDF - 2.33)
An alternative method (more accurate) of adjusting the VDD fault voltage is to use a resistive network of
R3 from the pin to supply and R1 from the pin to ground (see applications diagram). In order to set the
new threshold voltage, the equivalent resistance must be determined. This resistance value will be
designated Kx. Kx is defined as R1/(R1+R3). Kx is calculated as:
Kx = (2.789 / VTH) - 0.6125 where VTH is the desired new threshold voltage.
To determine the values of R1 and R3, use the following formulas.
R3 = 24000 / Kx R1 = R3*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7V is desired, solving for Kx gives:
Kx = (2.789 / 2.7) - 0.6125 = 0.42046.
Solving for R3 gives: R3 = 24000 / 0.42046 = 57080.
Solving for R1 gives: R1 = 57080 *(0.42046 / (1 – 0.42046)) = 41412.
Using standard 1 % resistor values gives R3 = 57.6KΩ and R1 = 42.4KΩ.
These values give an equivalent resistance of Kx = 0.4228, a 0.6% error.
If the 2.3V default threshold is used, this pin must be left unconnected. The 20QFN package has the VDD
fault threshold fixed at this default value.
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 9
4 Card Power Supply
The card power supply is internally provided by the LDO regulator, and controlled by the digital
ISO 7816-3 sequencer. Card voltage selection is carried out by the digital input 5V/#V.
Choice of the VCC Capacitor:
Depending on the applications, the requirements in terms of both VCC minimum voltage and transient
currents that the interface must be able to provide to the card are different. An external capacitor must be
connected between the VCC pin and to the card ground in order to guarantee stability of the LDO
regulator, and to handle the transient requirements. The type and value of this capacitor can be
optimized to meet the desired specification. Table 1 shows the recommended capacitors for each VPC
power supply configuration and applicable specification.
Table 1: Choice of VCC Pin Capacitor
Specification Requirements
System Requirements
Specification
Min VCC Voltage
Allowed During
Transient Current
Max
Transient
Current
Charge
Min V
PC
Power
Supply
Required
Capacitor
Type Capacitor Value
EMV 4.0
4.6V
30nA.s
4.75V
X5R/X7R
w/
ESR <
100mΩ
3.3 µF
ISO 7816-3
4.5V
20nA.s
4.75V
1 µF
NDS
4.6V
40nA.s
4.85V
1
µ
F
Note: Capacitor value for NDS implementation is also defined by the deactivation time requirement.
5 Over-Temperature Monitor
A built-in detector monitors die temperature. Upon an over-temperature condition, a card deactivation
sequence is initiated, and an error or fault condition is reported to the system controller.
6 On-Chip Oscillator and Card Clock
The 73S8024RN device has an on-chip oscillator that can generate the smart card clock using an
external crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency.
When the clock signal is available from another source, it can be connected to the pin XTALIN, and the
pin XTALOUT should be left unconnected.
The card clock frequency may be chosen between four different division rates, defined by digital inputs
CLKDIV 1 and CLKDIV 2, as per Table 2.
Table 2: Card Clock Frequency
CLKDIV1
CLKDIV2
CLK
0
0
⅛ XTALIN
0
1
¼ XTALIN
1
0
XTALIN
1
1
½ XTALIN
Card power down mode (card clock STOP) is supported and is controllable through the dedicated digital
inputs CLKSTOP and CLKLEV (not supported in the 20QFN package).
73S8024RN Data Sheet DS_8024RN_020
10 Rev. 2
7 Activation Sequence
The 73S8024RN smart card interface IC has an internal 10ms delay at power on reset or on the
application of VDD > VDDF. No activation is allowed at this time. The CMDVCC (edge triggered) must then
be set low to activate the card. In order to initiate activation, the card must be present; there can be no
over-temperature fault or no VDD fault.
The following steps show the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low while the RSTIN is low:
• CMDVCC is set low.
• Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation,
the voltage VCC to the card becomes valid during t1. If VCC does not become valid, the OFF goes low
to report a fault to the system controller, and the power VCC to the card is shut off.
• Turn I/O (AUX1, AUX2) to reception mode at the end of (t2).
• CLK is applied to the card at the end of (t3).
• RST is a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer will not
set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
I/O
CLK
RSTIN
t1t2t3t4
RST
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5µs, I/O goes to reception state
t3 = >0.5µs, CLK starts
t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 2: Activation Sequence – RSTIN Low When CMDVCC Goes Low
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 11
The following steps show the activation sequence and the timing of the card control signals when the
system controller pulls the CMDVCC low while the RSTIN is high:
• CMDVCC is set low.
• Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation,
the voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to
the system controller, and the power VCC to the card is shut down.
• Due to the fall of RSTIN at (t2), turn I/O (AUX1, AUX2) to reception mode.
• CLK is applied to the card at the end of (t3), after I/O is in reception mode.
• RST is to be a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer will
not set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
I/O
CLK
RSTIN
t1t2t3t4
RST
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5µs, I/O goes to reception state
t3 = > 0.5µs, CLK active
t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 3: Activation Sequence – RSTIN High When CMDVCCB Goes Low
73S8024RN Data Sheet DS_8024RN_020
12 Rev. 2
8 Deactivation Sequence
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in
the event of hardware faults. Hardware faults are over-current, overheating, VDD fault, VPC fault, VCC fault,
and card extraction during the session. To be noted that VPC and VCC faults are linked together so that a
fault is generated when VPC goes lower than VCC.
The following steps show the deactivation sequence and the timing of the card control signals when the
system controller sets the CMDVCC high or OFF goes low due to a fault or card removal:
• RST goes low at the end of t1.
• CLK is set low at the end of t2.
• I/O goes low at the end of t3. Out of reception mode.
• VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
RST
CLK
I/O
VCC
t
1
t
2
t
3
t
4
t
5
CMDVCC
-- OR --
OFF
t1 = > 0.5µs, timing by 1.5MHz internal Oscillator
t2 = > 7.5µs
t3 = > 0.5µs
t4 = > 0.5µs
t5 = depends on VCC filter capacitor.
For NDS application, CF=1µF makes t1 + t2 + t3 + t4 + t5 < 100µs
Figure 4: Deactivation Sequence
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 13
9 OFF and Fault Detection
There are two different cases that the system controller can monitor the OFF signal: to query regarding
the card presence outside card sessions, or for fault detection during card sessions.
Outside a card session: In this condition, CMDVCC is always high, OFF is low if the card is not present,
and high if the card is present. Because it is outside a card session, any fault detection will not act upon
the OFF signal. No deactivation is required during this time.
During a card session: CMDVCC is always low, and OFF falls low if the card is extracted or if any fault
detection is detected. At the same time that OFF is set low, the sequencer starts the deactivation
process.
The Figure 5 shows the timing diagram for the signals CMDVCC, PRES, and OFF during a card session
and outside the card session:
PRES
OFF
CMDVCC
VCC
outside card session within card session
OFF is low by
card extracted
OFF is low by
any fault
within card
session
Figure 5: Timing Diagram – Management of the Interrupt Line OFF
10 I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the
activation sequencer turns on the I/O reception state. See the Activation Sequence section for more
details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and AUX2UC are high after
power on reset.
Within a card session and when the I/O reception state is turn on, the first I/O line on which a falling edge
is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line
rising edge is detected then both I/O lines return to their neutral state.
Figure 6 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output.
The delay between the I/O signals is shown in Figure 7.
73S8024RN Data Sheet DS_8024RN_020
14 Rev. 2
Neutral
State
I/OUC
in
I/O
reception
I/OICC
in
No
Yes
No No
No
Yes
No
Yes
I/O
&
not I/OUC
I/OUC
&
not I/O
I/OUC I/O
yes
yes
Figure 6: I/O and I/OUC State Diagram
I/O
I/OUC
tI/O_HL tI/O_LH
tI/OUC_HL tI/OUC_LH
Delay from I/O to I/OUC: tI/O_HL = 100ns tI/O_LH = 25ns
Delay from I/OUC to I/O: tI/OUC_HL = 100ns tI/OUC_LH = 25ns
Figure 7: I/O – I/OUC Delays Timing Diagram
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 15
11 Typical Application Schematic
SO28
See NOTE 4
VDD
CLKSTOP_from_uC
Y1
CRYSTAL
C2
22pF
C1
NDS & ISO7816=1uF, EMV=3.3uF
See NOTE 5
RSTIN_from_uC
CLKDIV2_from_uC
CLK track should be routed
far from RST, I/O, C4 and
C8.
NOTES:
1) VDD = 2.7V to 5.5V DC.
2) VPC = 4.75V(EMV, ISO)/4.85(NDS) to 5.5V DC
3) Required if external clock from uP is used.
4) Required if crystal is used.
Y1, C2 and C3 must be removed if external clock is used.
5) Optional. Can be left open.
6)Internal pull-up allows it to be left open if unused.
7) R1 and R3 are external resistors that adjust the VDD
fault voltage. Can be left open.
I/OUC_to/from_uC
R1
Rext1
See NOTE 1
Card detection
switch is
normally closed
VPC
C6
100nF
VDD
External_clock_from uC
C4
100nF
C3
22pF
AUX1UC_to.from_uC See NOTE 5
C5
10uF
AUX2UC_to/from_uC
See NOTE 3
See NOTE 2
CLKLVL_from_uC
VDD
Low ESR (<100mohms) C1
should be placed near the SC
connecter contact
CLKDIV1_from_uC
CMDVCC_from_uC
73S8024RN
1
2
3
4
5
6
7
12
8
9
10
11
13
14 15
16
17
18
19
20
21
22
23
28
27
25
24
26
CLKDIV1
CLKDIV2
5V3V_
GND
NC
VPC
CLKSTOP
AUX2
CLKLVL
PRESB
PRES
I/O
AUX1
GND CLK
RST
VCC
VDDF_ADJ
CMDVCC_
RSTIN
VDD
GND
OFF_
AUX2UC
AUX1UC
XTALOUT
XTALIN
I/OUC
5V/3V_select_from_uC
OFF_interrupt_to_uC
R3
Rext2
- OR -
R2
20K
See note 7
Smart Card Connector
1
2
3
4
5
6
7
8
9
10
VCC
RST
CLK
C4
GND
VPP
I/O
C8
SW-1
SW-2
See NOTE 6
VDD
Figure 8: 73S8024RN – Typical Application Schematic
73S8024RN Data Sheet DS_8024RN_020
16 Rev. 2
12 Electrical Specification
12.1 Absolute Maximum Ratings
Operation outside these rating limits may cause permanent damage to the device. The smart card
interface pins are protected against short circuits to VCC, ground, and each other.
Parameter Rating
Supply Voltage VDD -0.5 to 6.0 VDC
Supply Voltage VPC -0.5 to 6.0 VDC
Input Voltage for Digital Inputs -0.3 to (VDD +0.5) VDC
Storage Temperature -60 to 150°C
Pin Voltage (except card interface) -0.3 to (VDD +0.5) VDC
Pin Voltage (card interface)
-0.3 to (VCC + 0.5) VDC
ESD Tolerance – Card interface pins +/- 6kV
ESD Tolerance – Other pins +/- 2kV
*Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground.
Note: Smart Card pins are protected against shorts between any combinations of Smart Card pins.
12.2 Recommended Operating Conditions
Parameter Rating
Supply Voltage VDD 2.7 to 5.5 VDC
Supply Voltage VPC 4.75 to 5.5 VDC
NDS Supply Voltage VPC 4.85 to 5.5 VDC
Ambient Operating Temperature -40°C to +85°C
Input Voltage for Digital Inputs 0V to VDD + 0.3V
12.3 Package Thermal Parameters
Package Rating
28 SO 44
°
C / W
32QFN 47 °C / W (with bottom pad soldered)
32QFN 78 °C / W (without bottom pad soldered)
20QFN 53 °C / W (with the bottom pad soldered)
20QFN 90 °C / W (without the bottom pad soldered)
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 17
12.4 Smart Card Interface Requirements
Symbol Parameter Condition Min Typ Max Unit
Card Power Supply (VCC) Regulator
General conditions, -40
°
C < T < 85
°
C, 4.75v < VPC < 5.5v, 2.7v < VDD < 5.5v
NDS conditions, 4.85v < VPC < 5.5v
VCC
Card supply voltage
including ripple and
noise
Inactive mode
-0.1
0.1
V
Inactive mode
ICC = 1mA
-0.1 0.4 V
Active mode; ICC <65mA; 5v
4.60
5.25
V
Active mode; I
CC
<65mA; 5v,
NDS condition
4.75 5.25 V
Active mode; ICC <90mA; 5v
4.55
5.25
V
Active mode; ICC <90mA; 3v
2.80
3.2
V
Active mode; single pulse of
100mA for 2µs; 5 volt, fixed load
= 25mA
4.6 5.25 V
Active mode; single pulse of
100mA for 2µs; 3v, fixed load =
25mA
2.76 3.2 V
Active mode; current pulses of
40nAs with peak |ICC | <200mA,
t <400ns; 5v
4.6 5.25 V
Active mode; current pulses of
40nAs with peak |ICC | <200mA,
t <400ns; 5v,
NDS condition
4.65 5.25 V
Active mode; current pulses of
40nAs with peak |ICC | <200mA,
t <400ns; 3v
2.76 3.2 V
VCCrip
VCC Ripple
fRIPPLE = 20K – 200MHz
350
mV
ICCmax Card supply output
current
Static load current, VCC>4.6
65
mA
Static load current, V
CC
>4.55 or
2.7 volts as selected
90 mA
ICCF
ICC fault current
90
150
mA
VSR - VSF
VCC slew rate -
CF = 3.3µF on VCC
0.02
0.050
0.08
V/µs
V
SRN
-
VSFN
VCC slew rate
C
F
= 1.0µF on V
CC
NDS applications
0.06 0.160 0.26 V/µs
CF
External filter capacitor
(VCC to GND)
C
F
should be ceramic with low
ESR (<100mΩ).
1 3.3 5 µF
CFNDS External filter capacitor
(VCC to GND)
NDS applications
CF should be ceramic with low ESR
(<100mΩ).
0.5 1.0 1.5 µF
73S8024RN Data Sheet DS_8024RN_020
18 Rev. 2
Symbol Parameter Condition Min Typ Max Unit
Interface Requirements –
Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,
AUX2UC.
ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC.
VOH Output level, high (I/O, AUX1,
AUX2)
IOH =0
0.9 VCC
VCC+0.1
V
IOH = -40µA
0.75 VCC
VCC+0.1
V
VOH Output level, high (I/OUC,
AUX1UC, AUX2UC)
IOH =0
0.9 VDD
VDD+0.1
V
IOH = -40µA
0.75 VDD
VDD+0.1
V
VOL
Output level, low
IOL=1mA
0.3
V
VIH
Input level, high (I/O, AUX1,
AUX2)
1.8 VCC+0.30 V
VIH
Input level, high (I/OUC,
AUX1UC, AUX2UC)
1.8
V
DD
+0.30 V
VIL
Input level, low
-0.3
0.8
V
VINACT Output voltage when outside
of session
IOL = 0
0.1
V
IOL = 1mA
0.3
V
ILEAK
Input leakage
VIH = VCC
10
µA
IIL
Input current, low
VIL = 0
0.65
mA
ISHORTL Short circuit output current
For output low,
shorted to VCC
through 33 ohms
15 mA
ISHORTH Short circuit output current
For output high,
shorted to ground
through 33 ohms
15 mA
tR, tF Output rise time, fall times
For I/O, AUX1,
AUX2, CL = 80pF,
10% to 90%.
For I/OUC,
AUX1UC, AUX2UC,
CL=50Pf, 10% to
90%.
100 ns
tIR, tIF
Input rise, fall times
1
µs
RPU Internal pull-up resistor
Output stable for
>200ns
8 11 14 kΩ
FDMAX
Maximum data rate
1
MHz
TFDIO
Delay, I/O to I/OUC, AUX1 to
AUX1UC, AUX2 to AUX2UC,
I/OUC to I/O, AUX1UC to
AUX1, AUX2UC to AUX2
(respectively falling edge to
falling edge and rising edge
to rising edge)
Edge from master to
slave, measured at
50%
60
100
200
ns
TRDIO 25 90 ns
CIN
Input capacitance
10
pF
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 19
Symbol Parameter Condition Min Typ Max Unit
Reset and Clock for card interface, RST, CLK
VOH
Output level, high
IOH =-200µA
0.9 VCC
VCC
V
VOL
Output level, low
IOL=200µA
0
0.3
V
VINACT Output voltage when outside
of session
IOL = 0
0.1
V
IOL = 1mA
0.3
V
IRST_LIM
Output current limit, RST
30
mA
ICLK_LIM
Output current limit, CLK
70
mA
CLKSR3V
CLK slew rate
Vcc = 3V
0.3
V/ns
CLKSR5V
CLK slew rate
Vcc = 5V
0.5
V/ns
tR, tF Output rise time, fall time
C
L
= 35pF for CLK,
10% to 90%
8 ns
C
L
= 200pF for RST,
10% to 90%
100 ns
δ Duty cycle for CLK
C
L
=35Pf,
FCLK ≤ 20MHz
45 55 %
12.5 Characteristics: Digital Signals
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Digital I/O Except for OSC I/O
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
0.7 VDD
VDD + 0.3
V
VOL
Output Low Voltage
IOL = 2mA
0.45
V
VOH
Output High Voltage
IOH = -1mA
VDD - 0.45
V
ROUT Pull-up resistor, OFF 16 21 24 kΩ
|IIL1|
Input Leakage Current
GND < VIN < VDD
-5
5
μA
Oscillator (XTALIN) I/O Parameters
VILXTAL
Input Low Voltage - XTALIN
-0.3
0.3 VDD
V
VIHXTAL
Input High Voltage - XTALIN
0.7 VDD
VDD+0.3
V
IILXTAL
Input Current -
XTALIN
GND < VIN < VDD -30 30 μA
fMAX
Max freq. Osc or external
clock
27 MHz
δin External input duty cycle limit
t
R/F
< 10% f
IN
,
45% < δCLK < 55%
48 52 %
73S8024RN Data Sheet DS_8024RN_020
20 Rev. 2
12.6 DC Characteristics
Symbol Parameter Condition Min Typ Max Unit
IDD Supply Current 2.7 7.0 mA
IPC Supply Current
V
CC
on, ICC=0
I/O, AUX1,
AUX2=high,
Clock not toggling
450 650 µA
IPCOFF
V
PC
supply current when
VCC = 0
CMDVCC High 345 550 µA
12.7 Voltage / Temperature Fault Detection Circuits
Symbol Parameter Condition Min Typ Max Unit
VDDF
V
DD
fault
(VDD Voltage supervisor
threshold)
No external resistor
on VDDF_ADJ pin 2.15 2.4 V
VPCF
V
PC
fault
(VPC Voltage supervisor
threshold)
V
PC
<V
CC
, a transient
event
VCC - 0.2
V
VCCF
V
CC
fault
(VCC Voltage supervisor
threshold)
VCC = 5v
4.20
4.55
V
VCC= 3v 2.5 2.7 V
TF
Die over temperature fault
115
145
°
C
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 21
13 Mechanical Drawing (20QFN)
20
1
2
4.0
4.0
2.0
2.0
TOP VIEW
0.85 NOM / 0.90 MAX
0.02 NOM / 0.05 MAX
0.20 REF
SEATING
PLANE
SIDE VIEW
PIN #1 ID
R 0.20
K
1920
2
1
0.50
0.18 / 0.30
0.35 / 0.45
2.50 / 2.70
1.25 / 1.35
2.50 / 2.70
1.25 / 1.35
0.20 MIN
0.20 MIN
0.18 / 0.30
BOTTOM VIEW
Figure 9: 20QFN Mechanical Drawing
73S8024RN Data Sheet DS_8024RN_020
22 Rev. 2
14 Package Pin Designation (20QFN)
Figure 10: 20QFN Pin Out
CAUTION: Use handling procedures necessary
for a static sensitive component
5
4
3
2
1
20
19
18
17
16
GND
VPC
PRES
PRES
I/O
XTALOUT
TERIDIAN
8024RN
5V/#V
CLKDIV2
CLKDIV1
I/OUC
6
7
8
9
10
CMDVCC
GND
CLK
RST
VCC
11
15
14
13
12
XTALIN
OFF
GND
VDD
RSTIN
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 23
15 Mechanical Drawing (32QFN)
2.5
5
2.5
5
TOP VIEW
1
2
3
Figure 11: 32QFN Mechanical Drawing
0.85 NOM.
/
0.9MAX.
0.00 / 0.005
0.20 REF.
SEATING
PLANE
SIDE VIEW
0.2 MIN.
0.35 / 0.45
1.5 / 1.6
3.0 / 3.2
0.18 / 0.3
BOTTOM VIEW
1
2
3
0.25
0.5
0.5
0.25
3.0 / 3.2
1.5 / 1.6
0.35 / 0.45
CHAMFERED
0.30
73S8024RN Data Sheet DS_8024RN_020
24 Rev. 2
16 Package Pin Designation (32QFN)
6
7
8
9
5
4
3
2
1
17
18
19
20
24
23
22
21
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
GND
NC
VPC
CLKSTOP
CLKLVL
PRES
PRES
I/O
XTALOUT
XTALIN
OFF
GND
VDD
RSTIN
CMDVCC
VDDF_ADJ
NC
AUX2
AUX1
GND
CLK
RST
VCC
NC
TERIDIAN
S8024RN
NC
NC
5V/#V
CLKDIV2
CLKDIV1
AUX2UC
AUX1UC
I/OUC
Figure 12: 32QFN Pin Out
CAUTION: Use handling procedures necessary
for a static sensitive component
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 25
17 Mechanical Drawing (SO)
Figure 13: 28 Lead SO
18 Package Pin Designation (SO)
(Top View)
TERIDIAN
73S8024RN
1
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
19
20
28
27
26
25
24
23
22
21
CLKDIV1
CLKDIV2
5V3V
GND
VPC
PRES
PRES
I/O
AUX2
AUX1
GND
AUX2UC
AUX1UC
I/OUC
XTALIN
XTALOUT
OFF
VDD
RSTIN
CMDVCC
VCC
RST
CLK
NC
CLKSTOP
CLKLVL
VDDF_ADJ
GND
Figure 14: 28SO 73S8024RN Pin Out
CAUTION: Use handling procedures necessary
for a static sensitive component
.335 (8.509)
.320 (8.128)
.420 (10.668)
.390 (9.906)
.050 TYP. (1.270)
.305 (7.747)
.285 (7.239)
.715 (18.161)
.695 (17.653)
.0115 (0.29)
.003 (0.076)
.016 nom (0.40)
.110 (2.790)
.092 (2.336)
PIN NO. 1
BEVEL
73S8024RN Data Sheet DS_8024RN_020
26 Rev. 2
19 Ordering Information
Part Description Order No. Packaging Mark
73S8024RN-SOL
28-pin Lead-Free SO 73S8024RN-IL/F 73S8024RN-IL
73S8024RN-SOL
28-pin Lead-Free SO Tape / Reel 73S8024RN-ILR/F 73S8024RN-IL
73S8024RN-32QFN
32-pin Lead-Free QF N 73S8024RN-IM/F S8024RN
73S8024RN-32QFN
32-pin Lead-Free QF N Tape / Reel 73S8024RN-IMR/F S8024RN
73S8024RN-20QFN
20-pin Lead-Free QF N 73S8024RN-20IM/F 8024RN
73S8024RN-20QFN
20-pin Lead-Free QF N Tape / Reel 73S8024RN-20IMR/F 8024RN
20 Related Documentation
The following 73S8024RN documents are available from Maxim:
73S8024RN Data Sheet (this document)
73S8024RN Combination 28SO/20QFN Demo Board User Guide
73S8024RN 28SO Demo Board User’s Guide
Achieving EMV Electrical Compliance with the TERIDIAN 73S8024RN
Dual Footprint Layout
73S8024RN vs NXP TDA8024T
Implementing the TERIDIAN 73S8024RN in NDS Applicatio ns
21 Contact Information
For more information about Maxim products or to check the availability of the 73S8024RN, contact
technical support at www.maxim-ic.com/support.
DS_8024RN_020 73S8024RN Data Sheet
Rev. 2 27
Revision History
Revision Date Description
1.1
5/18/2004
First publication.
1.2
11/5/2004
1.3 4/27/2005
Added 20QFN package option and ordering information. Updated 32 QFN
ordering information.
1.4
7/15/2005
1.5
8/23/2005
1.6 12/5/2007
Removes leaded package options, replaces 32QFN punched with SAWN
mechanical dimensions, update 28SO package dimensions.
1.7 1/17/2008
Changed dimension of bottom exposed pad on 32QFN mechanical package
figure.
1.8 1/19/2009
In Figure 1, modified the device block diagram to make pin 2 a no connect.
Also, changed the pin description.
In Figure 9, changed the mechanical drawing for the 20QFN package.
Added the NDS logo to page 1 and assigned document number.
Added the Related Documentation and the Contact Information sections.
1.9 5/27/2010
Changed dimension of bottom exposed pad on 32QFN mechanical package
figure.
2 6/12
Corrected the Order Numbers for the 73S8024RN-32QFN.
Added Maxim logo and Contact Information.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit
patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1 - 408-601-1000
2012 Maxim Integrated Products is a registered trademark of Maxim Integrated Products Inc.
