ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1986, Texas Instruments Incorporated
1
•8-Bit Resolution
•Easy Microprocessor Interface or Stand-
Alone Operation
•Operates Ratiometrically or With 5-V
Reference
•4- or 8-Channel Multiplexer Options With
Address Logic
•Shunt Regulator Allows Operation With
High-Voltage Supplies
•Input Range 0 to 5 V With Single 5-V
Supply
•Remote Operation With Serial Data Link
•Inputs and Outputs are Compatible With
TTL and MOS
•Conversion Time of 32 µs at
fclock = 250 kHz
•Designed to Be Interchangeable With
National Semiconductor ADC0834 and
ADC0838
DEVICE
TOTAL UNADJUSTED ERROR
DEVICE
A SUFFIX B SUFFIX
ADC0834 ±1 LSB ± 1/2 LSB
ADC0838 ±1 LSB ± 1/2 LSB
description
These devices are 8-bit successive- approxima-
tion analog-to-digital converters, each with an
input-configurable multichannel multi-
plexer and serial input/output. The serial input/
output is configured to interface with standard shift
registers or microprocessors. Detailed informa-
tion on interfacing with most popular microproces-
sors is readily available from the factory.
The ADC0834 (4-channel) and ADC0838
(8-channel) multiplexer is software configured
forsingle-ended or differential inputs as well as
pseudo-differential input assignments. The dif fer-
ential analog voltage input allows for common-
mode rejection or offset of the analog zero input
voltage value. In addition, the voltage reference
input can be adjusted to allow encoding any
smaller analog voltage span to the full 8 bits of
resolution.
The ADC0834AC, ADC0834BC, ADC0838AC, and ADC0838BC are characterized for operation from 0°C to
70°C. The ADC0834AI, ADC0834BI, ADC0838AI, and ADC0838BI are characterized for operation from –40°C
to 85°C.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
CS
CH0
CH1
CH2
CH3
DGTL GND
VCC
DI
CLK
SARS
DO
REF
ANLG GND
AD0834 . . . N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGTL GND
VCC
V+
CS
DI
CLK
SARS
DO
SE
REF
ANLG GND
ADC0838 . . . N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
CS
DI
CLK
SARS
DO
CH3
CH4
CH5
CH6
CH7
ADC0838 . . . FN PACKAGE
(TOP VIEW)
CH2
CH1
CH0
REF
SE V
V+
COM
DGTL GND
ANLG GND
CC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
CS
Circuits
To Internal
7 V
7 V
V +
SE
Only
5-Bit Shift Register
ODD\EVENSELECT0
EN
MUX
Analog
STARTSGL\DIFSELECT1
Circuits
To Internals
(see Note A)
DI
CLK
CS
R
D
CLK
ADC0838
ADC0838
ADC0834
CH7
CH5
CH6
COM
CH4
CH3
CH2
CH1
CH0
Comparator
SARS
CS
R
Start
S
CLK
CLK
Delay
Time SR
CS
DO
CS
CS
D
CLK
R
EOC
Register
Shift
9-Bit
R
CLK
First
LSB
Bit 1
Bits 0–7
First
MSB
Shot
One
Latch
and
Logic
SAR
R
CS
Bits 0–7
REF
Decoder
and
Ladder
EN
Flip-Flop
functional block diagram
NOTE A: For the ADC0834, DI is input directly to the D input of SELECT 1; SELECT 0 is forced to a high.
VCC
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
functional description
The ADC0834 and ADC0838 use a sample data comparator structure that converts differential analog inputs
by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single-ended), to an adjacent input (differential), or to a common terminal
(pseudo-differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative
(–) polarity. If the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial data link from the controlling
processor . A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor . This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer addressing sequence. The multiplexer
address is shifted into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single-ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs . For example, channel 0 and channel 1 may be selected as a differential pair . These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be
selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the ADC0838 can be used for a pseudo-differential input. In this mode, the voltage on
the common input is considered to be the negative differential input for all channel inputs. This voltage can be
any reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. On each low-to-high transition of the clock
input, the data on DI is clocked into the multiplexer address shift register . The first logic high on the input is the
start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of the clock
input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into
the start location of the multiplexer register, the input channel is selected and conversion starts. The SAR Status
output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift register is
disabled the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. The
data output DO comes out of the high-impedance state and provides a leading low for this one clock period of
multiplexer settling time. The SAR comparator compares successive outputs from the resistive ladder with the
incoming analog signal. The comparator output indicates whether the analog input is greater than or less than
the resistive ladder output. As the conversion proceeds, conversion data is simultaneously output from the DO
output pin, with the most significant bit (MSB) first.
After eight clock periods, the conversion is complete and the SARS output goes low.
The ADC0834 outputs the least-significant-bit-first data after the MSB-first data stream. If SE is held high on
the ADC0838, the value of the least significant bit (LSB) will remain on the data line. When SE is forced low,
the data is then clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored
in the 9-bit shift register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time
the output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low
transition followed by address information.
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
functional description (continued)
DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire.
This is possible because DI is only examined during the multiplexer addressing interval and DO is still in a
high-impedance state.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
sequence of operation
157
Select
CH Bit 1
1
Bit
tsu
Hi-Z
SARS
Don’t Care
176201267
MSBLSB
LSB-First Data
MSB-First Data
EvenDIF
Odd
+Sign
SGLBit
Start
MSB
Max
Settling
Time
DI
DO
CS
tsu
CLK
21201918141312123456 1011
t
conv
Hi-Z Hi-Z
ADC0834 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS CHANNEL NUMBER
SGL/DIF ODD/EVEN
L
L
H
H
L
H
L
H
O1
SELECT BIT 1
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
23
+
–
–
++
–
–
+
+
++
+
ADC0834
H = high level, L = low level, – or + = polarity of selected input pin
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
sequence of operation
SGL Odd Bit1
SE
LSB
MSB
LSB
765432101267
MSB
Time
MUX Settling
DO
LSB-Held LSB-First DataMSB-First Data
SE Used to Control LSB First Data
HI-Z
HI-Z
tconv
Dont Care
765432101267
MSB
LSB-First Data
MSB-First Data
MSB
Time
MUX Settling
HI-Z
DO
SE
SARS HI-Z
SELSEL+ Bit0
01
0
1EvenDIF
DI
Bit
Start
CS
Addressing
MUX
tSU
tsu
CLK
2726252423222120191817161514131211
8765432
1
ADC0838
Sign
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
ADC0838 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS SELECTED CHANNEL NUMBER
SGL/DIF
ODD/EVEN
SELECT 0 1 2 3 COM
SGL/DIF
ODD/EVEN
1 0 0 1 2 3 4 5 6 7
L L L L + –
L L L H +–
L L HL +–
L L HH +–
L H LL–+
L H LH –+
L H HL –+
L H HH –+
H L LL+ –
H L LH +–
HLHL+–
HLHH +–
HHLL+ –
HHLH +–
HHHL +–
HHHH +–
H = high level, L = low level, – or + = polarity of selected input
absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)
Supply voltage, VCC (see Notes 1 and 2) 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range: Logic –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog –0.3 V to VCC+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current: V+ input 15 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Any other input ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total input current for package ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: AC and BC suffixes 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AI and BI suffixes –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C. . . . . . . . . . . . . . . . . . . . .
NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal.
2. Internal zener diodes are connected from the VCC input to ground and from the V+ input to ground. The breakdown voltage of each
zener diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to VCC through a regular diode.
When the voltage regulator powers the converter, this zener and regular diode combination ensures that the VCC input (6.4 V) is less
than the zener breakdown voltage. A series resist or is recommended to limit current into the V+ input.
IOZ
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 6.3 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
fclock Clock frequency 10 400 kHz
Clock duty cycle (see Note 3) 40 60 %
twH(CS) Pulse duration, CS high 220 ns
tsu Setup time, CS low, SE low, or data valid before clock↑350 ns
thHold time, data valid after clock↑90 ns
TAO
p
erating free-air tem
p
erature
AC and BC suffixes 0 70 °
C
TAO erating
free
-
air
tem erature
AI and BI suffixes –40 85
°C
NOTE 3: The clock duty cycle range ensures proper operation at all clock frequencies. If a clock frequency is used outside the recommended
duty cycle range, the minimum pulse duration (high or low) is 1 µs.
electrical characteristics over recommended range of operating free-air temperature,
VCC = V+ = 5 V, fclock = 250 kHz (unless otherwise noted)
digital section
PARAMETER
TEST CONDITIONS†
AC, BC SUFFIX AI, BI SUFFIX
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VOH High levl out
p
ut voltage
VCC = 4.75 V, IOH = –360 µA2.8 2.4
V
V
OH
High
-
le
v
l
o
u
tp
u
t
v
oltage
VCC = 4.75 V, IOH = –10 µA4.6 4.5
V
VOL Low-levl output voltage VCC = 5.25 V, IOH = 1.6 mA 0.34 0.4 V
IIH High-level input current VIH = 5 V 0.005 1 0.005 1 µA
IIL Low-level input current VIL = 0 –0.005 –1 –0.005 –1 µA
IOH High-level output (source) current VOH = 0, TA = 25°C –6.5 –14 –6.5 –14 mA
IOL Low-level output (sink) current VOL = VCC,T
A
= 25°C 8 16 8 16 mA
High-impedance-state output VO = 5 V, TA = 25°C 0.01 3 0.01 3
µA
g
current (DO or SARS) VO = 0, TA = 25°C –0.01 –3 –0.01 –3 µ
A
CiInput capacitance 5 pF
CoOutput capacitance 5 pF
†All parameters are measured under open-loop conditions with zero common-mode input voltage (unless otherwise specified).
‡All typical values are at VCC = V+ = 5 V, TA = 25°C.
Standby input current (see Note 4) µAII(stdby)
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
electrical characteristics over recommended range of operating free-air temperature,
VCC = V + = 5 V, fclock = 250 kHz (unless otherwise noted) (continued)
analog and converter section
PARAMETER TEST CONDITIONS†MIN TYP‡MAX UNIT
–0.05
VICR Common-mode input voltage range See Note 3 to V
VCC+0.05
On-channel VI = 5 V 1
Off-channel VI = 0 –1
On-channel VI = 0 –1
Off–channel VI = 5 V 1
ri(REF) Input resistance to reference ladder 1.3 2.4 5.9 kΩ
total device PARAMETER TEST CONDITIONS†MIN TYP‡MAX UNIT
VZInternal zener diode breakdown voltage II = 15 mA at V+ pin, See Note 2 6.3 7 8.5 V
ICC Supply current 1 2.5 mA
†All parameters are measured under open-loop conditions with zero common-mode input voltage.
‡All typical values are at VCC = 5 V, V+ = 5 V, TA = 25°C.
NOTES: 4. Internal zener diodes are connected from the VCC input to ground and from the V+ input to ground. The breakdown voltage of each
zener diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to VCC through a regular diode.
When the voltage regulator powers the converter, this zener and regular diode combination ensures that the VCC input (6.4 V) is less
than the zener breakdown voltage. A series resistor is recommended to limit current into the V+ input.
5. If channel IN– is more positive than channel IN+, the digital output code will be 0000 0000. Connected to each analog input are two
on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC .Care must be taken during testing
at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause this input diode
to conduct and cause errors for analog input s that are near full-scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mV , the output code will be correct. T o achieve an absolute 0 V to 5 V input voltage range requires a minimum
VCC of 4.950 V for all variations of temperature and load.
6. Standby input currents are currents going into or out of the on or of f channels when the A/D converter is not performing conversion
and the clock is in a high or low steady-state condition.
PARAMETER UNITTEST CONDITIONS
ns
tdos
tconv
tpd CL = 100 pF ns
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
operating characteristics V + = 5 V, fclock = 250 kHz, tr = tf = 20 ns, TA = 25°C (unless otherwise noted)
AI, AC SUFFIX BI, BC SUFFIX
MIN TYP MAX MIN TYP MAX
Supply-voltage variation error VCC = 4.75 V to 5.25 V ±1/16 ±1/4 ±1/16 ±1/4 LSB
Total unadjusted error (see Note 6) Vref = 5 V,
TA = MIN to MAX ±1±1/2 LSB
Common-mode error Differential mode ±1/16 ±1/4 ±1/16 ±1/4 LSB
Change in zero-error from VCC = 5 V to internal
zener diode operation (see Note 2) II = 15 mA at V+ pin,
Vref = 5 V, VCC open 1 1 LSB
Propagation delay time, output MSB-first data 650 1500 650 1500
data after CLK↓, (see Note 7) LSB-first data 250 600 250 600
Output disable time, CL = 10 pF, RL = 10 kΩ125 250 125 250
DO or SARS after CS↑CL = 100 pF, RL = 2 kΩ500 500
Conversion time (multiplexer addressing
time not included) 8 8 clock
periods
†All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES:2. Internal zener diodes are connected from the VCC input to ground and from the V+ input to ground. The breakdown voltage of each zener
diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to VCC through a regular diode. When
the voltage regulator powers the converter , this zener and regular diode combination ensures that the VCC input (6.4 V) is less than
the zener breakdown voltage. A series resistor is recommended to limit current into the V+ input.
6. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
7. The most significant bit (MSB) data is output directly from the comparator and therefore requires additional delay to allow for comparator response
time.
PARAMETER MEASUREMENT INFORMATION
50%
tsu
thth
tsu
50%
VCC
GND
GND
GND
0.4 V0.4 V
2 V
2 V
DI
0.4 V
CS
CLK
VCC
VCC
Figure 1. Data Input Timing
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
PARAMETER MEASUREMENT INFORMATION
tsu
tpd
tpd
SE
CLK
DO
50%
50%
50%
50%
50%
GND
GND
GND
VCC
VCC
VCC
Figure 2. Data Output Timing
VOLTAGE WAVEFORMS
S2 closed
S1 open 10%
10%
90%
tr
VOLTAGE WAVEFORMS
S2 closed
S1 open
DO and SARS
tr
S1
S2
LOAD CIRCUIT
(see Note A)
CL
From Output
Under Test
Test
Point
CS
CS
tdis
90%
10%
90%
50% 50%
VCC
GND
GND
GND
GND
VCC
–VCC
VCC
VCC
RL
DO and SARS
tdis
NOTE A: CL includes probe and jig capacitance.
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11
TYPICAL CHARACTERISTICS
Vref – Reference Voltage – V
Linearity Error – LSB
Offset Error – LSB
Vref – Reference Voltage – V
VCC = 5 V
fclock = 250 kHz
TA = 25°C
54321
0
0.25
0.5
0.75
1
1.25
0
1.5
1010.10.01
VI(+) = VI(–) = 0 V
0
2
4
6
8
10
12
14
16
UNADJUSTED OFFSET ERROR
vs
REFERENCE VOLTAGE
LINEARITY ERROR
vs
REFERENCE VOLTAGE
Figure 4 Figure 5
Linearity Error – LSB
Linearity Error – LSB
fclock – Clock Frequency – kHzTA – Free-Air Tempertature – °C
25°C
85°C
Vref = 5 V
VCC = 5 V
600500400300200100
3
2.5
2
1.5
1
0.5
0
0
Vref = 5 V
fclock = 250 kHz
1007550250–25
0.5
0.45
0.4
0.35
0.3
–50
0.25
LINEARITY ERROR
vs
FREE-AIR TEMPERATURE
LINEARITY ERROR
vs
CLOCK FREQUENCY
–40°C
Figure 6 Figure 7
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
TYPICAL CHARACTERISTICS
fclock – Clock Frequency – kHzTA – Free-Air Temperature — °C
VCC = 5 V
TA = 25°C
1.5
1
0.5
5004003002001000
0
fclock = 250 kHz
CS = High
VCC = 5.5 V
VCC = 5 V
VCC = 4.5 V
1007550250–25
1.5
1
–50
0.5
– Supply Current – mA
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
CLOCK FREQUENCY
CC
I
– Supply Current – mA
CC
I
Figure 8 Figure 9
TA – Free-Air Temperature – °C
VCC = 5 V
IOL (VOL = 5 V)
–IOH (VOH = 0 V)
–IOH (VOH = 2.4 V)
IOL (VOL = 0.4 V)
20
25
15
10
5
1007550250–25–50
0
– Output Current – mA
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
IO
Figure 10
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
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Copyright 1998, Texas Instruments Incorporated
