2001 Microchip Technology Inc. DS21095H-page 1
FEATURES
• Single supply with operation down to 2.5V
• Comple tely implements DDC1/DDC2 inter-
face for monitor identification
• Low power CMOS technology
- 1 mA active current typical
-10 µA standby current typical at 5.5V
• 2-wire serial interface bus, I2C compatib le
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Factory programming (QTP) available
• 1,000,000 erase/write cycles ensured
• Data retention > 200 years
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24LC21 is a 128 x 8 bit
Electrically Erasable PROM. This device is designed
for use in applications requiring storage and serial
transmission of configuration and control information.
Two modes of operation have been implemented:
Transmit Only Mode and Bi-Directional Mode. Upon
power-up, the device will be in the Tra nsmit Only Mode,
sending a serial bit stream of the entire memory array
contents, clocked by the VCLK pin. A valid high to low
transiti on on the SCL pin will caus e the de vi ce to en ter
the Bi-Direc tional Mode, with byte selectabl e read/write
capability of the memory array . The 24LC21 is available
in a standard 8-pin PDIP and SOIC package in both
commercial and industrial temperature ranges.
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C t o +85°C
PACKAGE TYPES
BLOCK DIAGRAM
24LC21
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
24LC21
NC
NC
NC
VSS
1
2
3
4
8
7
5
5
VCC
VCLK
SCL
SDA
PDIP
SOIC
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
VCLK
SDA SCL
VCC
VSS
24LC21
1K 2.5V Dual Mode I2C™ Serial EEPROM
DDC is a trademark of the Video Electronics Standards Association.
I2C is a trademark of Philips Corporation.
24LC21
DS21095H-page 2 2001 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V
Storage temperature.....................................-65°C to +1 5 0 °C
Ambient temp. with power applied................-65°C to +1 2 5 °C
Soldering temperature of leads (10 seconds).............+300°C
ESD protection on all pins..................................................≥ 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1: PIN FUNCTION TABLE
Name Function
VSS Ground
SDA Serial Address/Data I/O
SCL Serial Clock (Bi-Directional Mode)
VCLK Serial Clock (Transmit-Only Mode)
VCC +2.5V to 5.5V Power Supply
NC No Conn ect ion
TABLE 1-2: DC CHARACTERISTICS
VCC = +2.5V to 5.5V
Commercial (C): TAMB = 0°C to +70°C
Industrial (I): TAMB = -40°C to +85°C
Parameter Symbol Min Max Units Conditions
SCL and SDA pins:
High level input voltage
Low level input voltage VIH
VIL .7 VCC
——
.3 VCC V
V—
—
Input levels on VCLK pin:
High level input voltage
Low level input voltage VIH
VIL 2.0
—.8
.2 VCC V
VVCC ≥ 2.7V (Note 1)
VCC < 2.7V (Note 1)
Hysteresis of Schmitt trigger inputs VHYS .05 VCC —V (Note 1)
Low level outp ut voltage VOL1—.4 V IOL = 3 mA, VCC = 2.5V (Note 1)
Low level outp ut voltage VOL2—.6 V IOL = 6 mA, VCC = 2.5V
Input leakage current ILI -10 10 µAVIN = .1V to VCC
Output lea kage curre nt ILO -10 10 µAVOUT = .1V to VCC
Pin capacitance (all inputs/outputs) CIN, COUT —10 pF VCC = 5.0V (Note1),
TAMB = 25°C, FCLK = 1 MHz
Operati ng current ICC Write
ICC Read —
—3
1mA
mA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS —
—30
100 µA
µAVCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
(Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: VLCK must be grounded.
2001 Microchip Technology Inc. DS21095H-page 3
24LC21
TABLE 1-3: AC CHARACTERISTICS
Parameter Symbol Standard Mode Vcc= 4.5 - 5.5V
Fast Mode Units Remarks
Min Max Min Max
Clock frequency FCLK —100 —400 kHz —
Clock high time THIGH 4000 —600 —ns —
Clock low time TLOW 4700 —1300 —ns —
SDA and SCL rise time TR—1000 —300 ns (Not e 1)
SDA and SCL fall time TF—300 —300 ns (Not e 1)
START condition hold time THD:STA 4000 —600 —ns After thi s period the first cloc k
puls e is generated
START condition setup
time TSU:STA 4700 —600 —ns Only relevant for repeated
START condition
Data input hold time THD:DAT 0—0—ns (Note 2)
Data input setup time TSU:DAT 250 —100 —ns —
STOP condition setup time TSU:STO 4000 —600 —ns —
Output valid from clock TAA —3500 —900 ns (Note 2)
Bus free time TBUF 4700 —1300 —ns Time the bus must be free
before a new transmission
can star t
Output fall time from VIH
min to VIL max TOF —250 20 + .1
CB250 ns (Note 1), CB ≤ 1 00 pF
Input filter spike suppres-
sion (SDA and SCL pins) TSP —50 —50 ns (Note 3)
Write cycle time TWR —10 —10 ms Byte or Page mode
Transmit-Only Mode Parameters
Output valid from VCLK TVAA —2000 —1000 ns —
VCLK high time TVHIGH 4000 —600 —ns —
VCLK low time TVLOW 4700 —1300 —ns —
Mode transition time TVHZ —500 —500 ns —
Transmit-Only power up
time TVPU 0—0—ns —
Endurance —1M —1M —cycles 25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specif ication f or standa rd operation .
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific applica-
tion, please consult the Total Endurance Model which can be obtained on our website: www.microchip.com
24LC21
DS21095H-page 4 2001 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LC 21 opera tes in two m odes, the T ransmit-O nly
Mode a nd th e Bi-Dire ction al Mo de. Th ere i s a separa te
two wire pr otocol to su pport ea ch mod e, each havin g a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-Only Mode
upon pow er-up. In t his mode , the devi ce transm its data
bits on the SDA pin in response to a clock signal on the
VCLK pin. The device will remain in this mode until a
valid high to low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bi-Directional Mode. The only
way to switch the device back to the Transmit-Only
Mode is to remove power from the device.
2.1 Transmit-Only Mode
The device will power up in the Transmit-Only Mode.
This mode supports a unidirectional two wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-Only Mode (see Initial-
ization Proc ed ure , be low) . In th is mo de, data is tran s-
mitted on the SDA pin in 8 bi t bytes, eac h follow ed by a
ninth, nul l bit (se e Figure 2-1). The clo ck sourc e for the
T ransm it-Only Mode is pro vided on t he VCLK pin, and a
data bit is output on the rising edge on this pin. The
eight bits in each byte are transmitted most significant
bit first. Each byte within the memory array will be out-
put in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bi-Directional Mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-Only Mode.
2.2 Initialization Procedure
After VCC has stabilized, the device will be in the T rans-
mit-Onl y Mode. Nine clock cycl es on the VCLK pin must
be give n to t he device f or it to p erform i nternal syn chro-
nization. During this period, the SDA pin will be in a
high impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the most significant bit of a byte. The
dev ice will power up at an indeterminate by te address.
(Figure 2-2).
FIGURE 2-1: TRANSMIT ONLY MODE
FIGURE 2-2: DEVICE INITIALIZATION
SCL
SDA
VCLK
TVAA TVAA
BIT 1 (LSB)
NULL BIT
BIT 1 (MSB) BIT 7
TVLOWTVHIGH
TVAA TVAA
BIT 8BIT 7HIGH IMPEDANCE FOR 9 CLOCK CYCLES
TVPU
12 891011
SCL
SDA
VCLK
VCC
2001 Microchip Technology Inc. DS21095H-page 5
24LC21
3.0 BI-DIRECTIONAL MODE
The 24LC21 can be switched into the Bi-Directional
Mode (see Figure 3-1) by applying a valid high to low
transition on the Bi-Directional Mode Clock (SCL).
When the device has been switched into the Bi-Direc-
tional Mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability . This mode supports a two wire bi-direc-
tional data transmission protocol. In this protocol, a
dev ice th at send s da ta on th e bu s is defin ed to b e t he
transmitter, and a device that receives data from the
bus is defin ed to be the rec eiver. Th e bus must be con-
trolled by a master device that generates the Bi-Direc-
tional Mode Clock (SCL), controls access to the bus
and genera tes the START and ST O P con diti ons, w hil e
the 24LC21 acts as the slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
3.1 Bi-Dir ection al Mod e Bus
Characteristics
The following bus protocol has been defined:
•Data transfer may be initiated only when the bus
is not busy.
•During data transfer, the data line must remain
stable w henev er the c lock l ine is HIG H. Cha nges
in the data line while the clock line is H IG H w i ll be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (se e Figur e 3-2).
3.1.1 BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
3.1.2 START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.1.3 STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1: MODE TRANSITION
FIGURE 3-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
VCLK
Bi-Directional Mode
TVHZ
Transmit Only Mode
(A) (B) (D) (D) (A)(C)
START
CONDITION ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL
SDA
24LC21
DS21095H-page 6 2001 Microchip Technology Inc.
3.1.4 DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
durat ion of the HIGH peri od of the clo ck sign al.
The data on the line must be changed during the LOW
period o f the c lock sign al. Th ere is one c lock pu lse p er
bit of data.
Each data transfer is initiated with a START condition
and term ina ted w ith a ST O P c ond iti on. The num ber of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight will be stored when doing a write operation.
When an ov erwrite does occur it will replace data in a
first in first out fashion.
3.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The mast er device mus t ge nera te a n ext ra c lock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line d uring th e ackn owledge clock pulse in such a
way t hat th e SDA line i s sta ble LO W dur ing th e HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave mus t leave the data l ine HIGH to enable
the master to generate the STOP condition.
Note: The 24LC21 does not generate any
acknowledge bits if an internal pro-
gramming cycle is in progress.
FIGURE 3-3: BUS TIMING START/STOP
FIGURE 3-4: BUS TIMING DATA
TSU:STA THD:STA
VHYS
TSU:STO
START STOP
SCL
SDA
TSU:STA
TF
TLOW
THIGH
TR
THD:DAT TSU:DAT TSU:STO
THD:STA TBUF
TAA
TAA
TSP
THD:STA
SCL
SDA
IN
SDA
OUT
24LC21
DS21095H-page 7 2001 Microchip Technology Inc.
3.1.6 SLAVE ADDRESS
After generating a START condition, the bus master
transmi ts the s lave addres s con sisting o f a 7- bit dev ice
code (1010) for the 24LC21, followed by three don’t
care bits.
The eighth bit of slave address determine s if the master
device wants to read or write to the 24LC21
(Figure 3-5).
The 24LC21 monitors the bus for its corresponding
slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
FIGURE 3-5: CONTROL BYTE
ALLOCATION
4.0 WRITE OPERATION
4.1 Byte Write
Following the start signal from the master, the slave
address (4 bits), th e don’t care bits (3 bits) and t he R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the nint h clock cycl e. Therefor e, the next byt e transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC21. After
receivi ng another acknowledge signal from the 24LC21
the mas ter device will trans mit the data w ord to be wr it-
ten into the addressed memory location. The 24LC21
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing t his time the 24L C21 will not generate a cknowledge
signals (Figure 4-1).
It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.
4.2 Page Write
The write control byte, word address and the first data
byte are tran smitt ed to th e 24LC21 in the sam e way as
in a byte write. But instead of generating a stop condi-
tion the master transmits up to eight data bytes to the
24LC21 which are temporarily stored in the on-chip
page buf fer and will be written into th e memory after the
master has transmitted a stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher or der five bit s of the word addres s remain s con-
stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
receive d data will be overwritte n. As with th e byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-3).
It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.
Operation Control Code Chip Select R/W
Read 1010 XXX 1
Write 1010 XXX 0
SLAVE ADDRESS
1010XXX
R/W A
START READ/WRITE
Note: Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses that
are intege r multip les of the page buffer
size (or ‘page size’) and end at
addresses t hat are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical
page boundary, the result is that the
data wraps around to the beginning of
the curre nt page (over writing data pre-
viously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for
the application software to prevent
page write operations that would
attempt to cross a page boundary.
24LC21
DS21095H-page 8 2001 Microchip Technology Inc.
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: BYTE WRITE
FIGURE 4-3: PAG E WRITE
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE WORD
ADDRESS DATA
A
C
K
A
C
K
A
C
K
VCLK
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE WORD
ADDRESS DATA
A
C
K
A
C
K
A
C
K
VCLK
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
TCONTROL
BYTE WORD
ADDRESS DATA (n) DATA (n + 15)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DATA (n + 1)
VCLK
24LC21
DS21095H-page 9 2001 Microchip Technology Inc.
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initi ated immediately . This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the d evice is s till busy wi th
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for the flow diagram.
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
6.0 WRITE PROTECTION
When usin g the 24LC21 in the Bi-Dire ctional Mode, the
VCLK pin operates as the write protect control pin. Set-
ting VCLK high allows normal write operations, while
setting VCLK low prevents writing to any location in the
array. Connecting the VCLK pin to VSS would allow the
24LC2 1 to o perate as a se rial R OM, although this con-
figuration would prevent using the device in the Trans-
mit-On ly Mo de.
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave a dd r es s i s set to ‘1’. There are th ree bas ic ty pe s
of read op erations: current add ress read, random rea d
and sequential read.
7.1 Current Address Read
The 24LC21 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next curren t address read opera tion would acces s data
from address n + 1. Upon receipt of the slave address
with R/W bit set to ‘1’, the 24LC21 issues an acknowl-
edge and t rans mits the eigh t bit data word. The m aster
will not acknowledge the transfer but does generate a
stop condition and the 24LC21 discontinues transmis-
sion (Figure 7-1).
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this typ e of re ad o peration, first the word address mus t
be set. This is done b y sending the word address to the
24LC21 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operatio n, but not bef ore the internal addre ss pointe r is
set. Then the master issues the control byte again but
with the R/W bit set to a ‘1’. The 24LC21 will then issue
an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does
generate a stop condition and the 24LC21 discontinues
transmission (Figure 7-2).
7.3 Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC21 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC21 to transmit the next sequentially
addressed 8-bit word (see Figure 7-3).
To provide sequential reads the 24LC21 contains an
internal address poin ter which is inc remented by o ne at
the com ple tio n o f each ope rati on. Thi s a ddre ss po int er
allows the entire memory contents to be serially read
during one operation.
7.4 Noise Protection
The 24LC21 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SCL an d SDA inpu ts have Schmitt trigg er and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
Send
Write Comman d
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Devic e
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
2001 Microchip Technology Inc. DS21095H-page 10
24LC21
FIGURE 7-1: CURRENT ADDRESS READ
FIGURE 7-2: RANDOM READ
FIGURE 7-3: SEQUENTIAL READ
SP
BUS ACT IV IT Y
MASTER
SDA LINE
BUS ACT IV IT Y
S
T
A
R
T
CONTROL
BYTE DATA (n)
A
C
K
N
O
A
C
K
S
T
O
P
S P
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE WORD
ADDRESS DATA (n)
A
C
K
A
C
K
N
O
A
C
K
CONTROL
BYTE
A
C
K
S
T
A
R
T
P
BUS AC TIVIT Y
MASTER
SDA LINE
BUS AC TIVIT Y
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA (n) DATA (n + 1) DATA (n + 2) DATA (n + X)
A
C
K
A
C
K
A
C
K
8.0 PIN DESCRIPTIONS
8.1 SDA
This pin is used to transfer addresses and data into and
out of the device, when the device is in the Bi-Direc-
tional Mode. In the Transmit-Only Mode, which only
allows data to be read from the device, data is also
transferred on the SDA pin. This pin is an open drain
termina l, therefore the SDA bus requires a pullup resis-
tor to VCC (typic al 10KΩ for 100 k Hz, 2KΩ for 40 0 kHz).
For normal data transfer in the Bi-Directional Mode,
SDA is allowed to change only during SCL low.
Changes during SCL high are reserved for indicating
the START and STOP conditions.
8.2 SCL
This pin is the clock input for the Bi-Directional Mode,
and is used to synchronize data transfer to and from th e
device. It is also used as the signaling input to switch
the device from the Transmit Only Mode to the Bi-Direc-
tional Mode. It must rema in high fo r the chip to continu e
operation in the Transmit Only Mode.
8.3 VCLK
This pin is the clock input for the Transmit Only Mode.
In the Transmit Only Mode, each bit is clocked out on
the rising edge of this signal. In the Bi-Directional
Mode, a high logic level is req uired on this pi n to enable
write capability.
24LC21
2001 Microchip Technology Inc. DS21095H-page 11
24LC21 Product Ide ntification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
Sales and Support
Package: P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
Temperature Blank = 0°C to +70°C
Range: I=-40°C to +85°C
Device: 24LC21 Dual Mode I2C Serial EEPROM
24LC21T Dual Mode I2C Serial EEPROM (Tape and Reel)
24LC21 -/P
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microc hip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Web Site (www.microchip. com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2001 Microchip Technology Inc. DS21095H-page 12
24LC21
NOTES:
24LC21
DS21095H-page 13 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. DS21095H-page 14
24LC21
NOTES:
24LC21
DS21095H-page 15 2001 Microchip Technology Inc.
“All rights reserved. Copyright © 2001, Microchip
Technology Incorporated, USA. Information contained
in this publication regard ing device ap plications and the
like is intended through suggestion only and may be
superse ded by updates . No repr esent ati on or warrant y
is given and no liability is assumed by Microchip
Technology Incorporated with respect to the accuracy
or use of such in formation, or infringement of patents or
other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized
except with express written approval by Microchi p. No
licenses are conveyed, implicitly or otherwise, under
any int ell ectual proper ty righ ts. The Mi cro chip log o an d
name are registered trademarks of Microchip
Technology Inc. in the U.S.A. and other countries. All
rights reserved. All ot her trademarks menti on ed h erei n
are the property of their respective companies. No
licenses are conveyed, implicitly or otherwise, under
any intellectual property rights.”
Trademarks
The Microchip name, logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, KEELOQ,
SEEVAL, MPLAB and The Emb edded Control
Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and
other countries.
Total Endurance, ICSP, In-Circuit Serial Programming,
FilterLab, MXDEV, microID, FlexROM, fuzzyLAB,
MPASM, MPLINK, MPLIB, PICDEM, ICEPIC,
Migratable Memory, FanSense, ECONOMONITOR,
SelectMode and microPort are trademarks of
Microchip Technology Incorporated in the U.S.A.
Serializ ed Q ui ck Term Programming (SQTP) is a
service mark of Microchip Technology Incorporated in
the U.S.A.
All other trademarks mentioned herein are property of
their respec tiv e com p a ni es.
© 2001, M icr oc hip Technology Inco rpo r ate d, Prin ted in
the U.S.A., All Rights Reserved.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and T empe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8- bi t MC Us , KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
update s. It i s your respo nsibilit y to en sure t hat you r app licatio n mee ts with y our sp ecifica tions. N o re presen tation or warra nty is given and n o liability is
assumed by M icroc hip Techno logy In corpor ated with respe ct to the a ccuracy or u se of such in format ion, or infringem ent of paten ts or other intel lectual
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec-
tual p roperty rights. The M icrochip logo an d name are reg istered tradema rks of Microchip Technolo gy Inc. in the U.S.A . and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21095H-page 16 2001 Microchip Technology Inc.
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 3/01 Printed on recycled paper.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://ww w.microchip .com
Rocky Mountain
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456
Atlanta
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640- 003 4 Fax: 770- 640 -03 07
Austin
Analog Product Sales
8303 MoPac Expressway North
Suite A-201
Austin, TX 78759
Tel: 512-345- 203 0 Fax: 512- 345 -60 85
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692- 384 8 Fax: 978- 692 -38 21
Boston
Analog Product Sales
Unit A-8-1 Millbrook Tarry Condominium
97 Lowell Road
Concord, MA 01742
Tel: 978-371- 640 0 Fax: 978- 371 -00 50
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 7500 1
Tel: 972-818- 742 3 Fax: 972- 818 -29 24
Dayton
Tw o Pres tige Pla ce, Su ite 130
Miamisburg, OH 45342
Tel: 937-291- 165 4 Fax: 937- 291 -91 75
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Los A n ge les
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263- 188 8 Fax: 949- 263 -13 38
Mountain View
Analog Product Sales
1300 Terra Bella Avenue
Mountain View, CA 94043-1836
Tel: 650-968- 924 1 Fax: 650- 967 -15 90
New York
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 212 1, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
China - Be ijing
Microchip Technology Beijing Office
Unit 915
New China Hong Kong Manhattan Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
China - Shanghai
Microchip Technology Shanghai Office
Room 701, Bldg. B
Far East In ternational Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Hong Kong
Microchip Asia Pacific
RM 2101, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
India
Microchip Technology Inc.
India Liaiso n Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku -Ku, Yok oha ma-shi
Kanaga wa, 222 -0 033 , Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
ASIA/PACIFIC (continued)
Korea
Microc hip Technolo gy Korea
168-1, You ng bo Bld g. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Ko re a
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Midd le Ro ad
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fax : 65-334-8 850
Taiwan
Microc hip Technolo gy Taiwan
11F -3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Et age
91300 Massy, France
Tel: 33-1-69-53- 63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Germany
Analog Product Sales
Lochhamer Strasse 13
D-82152 Martinsried, Germany
Tel: 49-89-895650-0 Fax: 49-89-895650-22
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berksh ire, E ngla nd RG 41 5TU
Tel: 44 1 18 921 5869 Fax: 44-118 921-5820
01/30/01
WORLDWIDE SALES AND SERVICE
