AD8313ARMZ-REEL7 - Analog Devices

0.1 GHz to 2.5 GHz 70 dB

Logarithmic Detector/Controller

AD8313

Rev. D

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infringements of patents or other rights of third parties that may result from its use.

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registered trademarks are the property of their respective owners.

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FEATURES

Wide bandwidth: 0.1 GHz to 2.5 GHz min

High dynamic range: 70 dB to ±3.0 dB

High accuracy: ±1.0 dB over 65 dB range (@ 1.9 GHz)

Fast response: 40 ns full-scale typical

Controller mode with error output

Scaling stable over supply and temperature

Wide supply range: 2.7 V to 5.5 V

Low power: 40 mW at 3 V

Power-down feature: 60 mW at 3 V

Complete and easy to use

APPLICATIONS

RF transmitter power amplifier setpoint control and

level monitoring

Logarithmic amplifier for RSSI measurement cellular

base stations, radio link, radar

FUNCTIONAL BLOCK DIAGRAM

++ +++

AD8313

VOUT

VSET

COMM

PWDN

GAIN

BIAS

BAND GAP

REFERENCE

SLOPE

CONTROL

INTERCEPT

CONTROL

EIGHT 8dB 3.5GHz AMPLIFIER STAGES

8dB 8dB

VPOS

INHI

INLO

VPOS

8dB8dB

NINE DETECTOR CELLS

INT

I→V

V→I

01085-C-001

Figure 1.

GENERAL DESCRIPTION

The AD8313 is a complete multistage demodulating logarithmic

amplifier that can accurately convert an RF signal at its differ-

ential input to an equivalent decibel-scaled value at its dc output.

The AD8313 maintains a high degree of log conformance for

signal frequencies from 0.1 GHz to 2.5 GHz and is useful over

the range of 10 MHz to 3.5 GHz. The nominal input dynamic

range is –65 dBm to 0 dBm (re: 50 Ω), and the sensitivity can be

increased by 6 dB or more with a narrow-band input impedance

matching network or a balun. Application is straightforward,

requiring only a single supply of 2.7 V to 5.5 V and the addition

of a suitable input and supply decoupling. Operating on a 3 V

supply, its 13.7 mA consumption (for TA = 25°C) is only 41 mW.

A power-down feature is provided; the input is taken high to

initiate a low current (20 µA) sleep mode, with a threshold at

half the supply voltage.

The AD8313 uses a cascade of eight amplifier/limiter cells, each

having a nominal gain of 8 dB and a −3 dB bandwidth of

3.5 GHz. This produces a total midband gain of 64 dB. At each

amplifier output, a detector (rectifier) cell is used to convert the

RF signal to baseband form; a ninth detector cell is placed

directly at the input of the AD8313. The current-mode outputs

of these cells are summed to generate a piecewise linear approxi-

mation to the logarithmic function. They are converted to a low

impedance voltage-mode output by a transresistance stage, which

also acts as a low-pass filter.

When used as a log amplifier, scaling is determined by a separate

feedback interface (a transconductance stage) that sets the slope

to approximately 18 mV/dB; used as a controller, this stage

accepts the setpoint input. The logarithmic intercept is positioned

to nearly −100 dBm, and the output runs from about 0.45 V dc

at −73 dBm input to 1.75 V dc at 0 dBm input. The scale and

intercept are supply- and temperature-stable.

The AD8313 is fabricated on Analog Devices’ advanced 25 GHz

silicon bipolar IC process and is available in an 8-lead MSOP

package. The operating temperature range is −40°C to +85°C.

An evaluation board is available.

INPUT AMPLITUDE (dBm)

2.0

–80

OUTPUT VOLTAGE (V DC)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0–70 –60 –50 –40 –30 –20 –10 0

FREQUENCY = 1.9GHz 5

–1

–2

–3

–

–5

OUTPUT ERROR (dB)

01085-C-002

Figure 2. Typical Logarithmic Response and Error vs. Input Amplitude

AD8313

Rev. D | Page 2 of 24

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Description............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 11

Interfaces.......................................................................................... 13

Power-Down Interface, PWDN ................................................ 13

Signal Inputs, INHI, INLO ........................................................ 13

Logarithmic/Error Output, VOUT .......................................... 13

Setpoint Interface, VSET............................................................ 14

Applications..................................................................................... 15

Basic Connections for Log (RSSI) Mode................................. 15

Operating in Controller Mode ................................................. 15

Input Coupling ........................................................................... 16

Narrow-Band LC Matching Example at 100 MHz ................ 16

Adjusting the Log Slope............................................................. 18

Increasing Output Current........................................................ 19

Effect of Waveform Type on Intercept..................................... 19

Evaluation Board ............................................................................ 20

Schematic and Layout................................................................ 20

General Operation ..................................................................... 20

Using the AD8009 Operational Amplifier .............................. 20

Var ying the L ogar ithm ic Slope ................................................. 20

Operating in Controller Mode ................................................. 20

RF Burst Response ..................................................................... 20

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

6/04—Data Sheet Changed from Rev. C to Rev. D

Updated Evaluation Board Section .............................................. 21

2/03—Data Sheet changed from Rev. B to Rev. C

TPCs and Figures Renumbered........................................Universal

Edits to SPECIFICATIONS............................................................. 2

Updated ESD CAUTION ................................................................ 4

Updated OUTLINE DIMENSIONS .............................................. 7

8/99—Data Sheet changed from Rev. A to Rev. B

5/99—Data Sheet changed from Rev. 0 to Rev. A

8/98—Revision 0: Initial Version

AD8313

Rev. D | Page 3 of 24

SPECIFICATIONS

TA = 25°C, VS = 5 V1, RL 10 kΩ, unless otherwise noted.

Table 1.

Parameter Conditions Min2Typ Max2Unit

SIGNAL INPUT INTERFACE

Specified Frequency Range 0.1 2.5 GHz

DC Common-Mode Voltage VPOS – 0.75 V

Input Bias Currents 10 µA

Input Impedance fRF < 100 MHz3 900||1.1 Ω||pF4

LOG (RSSI) MODE Sinusoidal, input termination configuration

shown in Figure 29

100 MHz5Nominal conditions

±3 dB Dynamic Range6 53.5 65 dB

Range Center −31.5 dBm

±1 dB Dynamic Range 56 dB

Slope 17 19 21 mV/dB

Intercept −96 −88 −80 dBm

2.7 V ≤ VS ≤ 5.5 V, −40°C ≤ T ≤ +85°C

±3 dB Dynamic Range 51 64 dB

Range Center −31 dBm

±1 dB Dynamic Range 55 dB

Slope 16 19 22 mV/dB

Intercept −99 −89 −75 dBm

Temperature Sensitivity PIN = −10 dBm −0.022 dB/°C

900 MHz5 Nominal conditions

±3 dB Dynamic Range 60 69 dB

Range Center −32.5 dBm

±1 dB Dynamic Range 62 dB

Slope 15.5 18 20.5 mV/dB

Intercept −105 −93 −81 dBm

2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C

±3 dB Dynamic Range 55.5 68.5 dB

Range Center –32.75 dBm

±1 dB Dynamic Range 61 dB

Slope 15 18 21 mV/dB

Intercept –110 –95 –80 dBm

Temperature Sensitivity PIN = –10 dBm –0.019 dB/°C

1.9 GHz7 Nominal conditions

±3 dB Dynamic Range 52 73 dB

Range Center –36.5 dBm

±1 dB Dynamic Range 62 dB

Slope 15 17.5 20.5 mV/dB

Intercept –115 –100 –85 dBm

2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C

±3 dB Dynamic Range 50 73 dB

Range Center –36.5 dBm

±1 dB Dynamic Range 60 dB

Slope 14 17.5 21.5 mV/dB

Intercept –125 –101 –78 dBm

Temperature Sensitivity PIN = –10 dBm –0.019 dB/°C

AD8313

Rev. D | Page 4 of 24

Parameter Conditions Min2Typ Max2Unit

2.5 GHz7Nominal conditions

±3 dB Dynamic Range 48 66 dB

Range Center –34 dBm

±1 dB Dynamic Range 46 dB

Slope 16 20 25 mV/dB

Intercept –111 –92 –72 dBm

2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C

±3 dB Dynamic Range 47 68 dB

Range Center –34.5 dBm

±1 dB Dynamic Range 46 dB

Slope 14.5 20 25 mV/dB

Intercept –128 –92 –56 dBm

Temperature Sensitivity PIN =–10 dBm –0.040 dB/°C

3.5 GHz5Nominal conditions

±3 dB Dynamic Range 43 dB

±1 dB Dynamic Range 35 dB

Slope 24 mV/dB

Intercept –65 dBm

CONTROL MODE

Controller Sensitivity f = 900 MHz 23 V/dB

Low Frequency Gain VSET to VOUT8 84 dB

Open-Loop Corner Frequency VSET to VOUT8 700 Hz

Open-Loop Slew Rate f = 900 MHz 2.5 V/µs

VSET Delay Time 150 ns

VOUT INTERFACE

Current Drive Capability

Source Current 400 µA

Sink Current 10 mA

Minimum Output Voltage Open-loop 50 mV

Maximum Output Voltage Open-loop VPOS – 0.1 V

Output Noise Spectral Density PIN = –60 dBm, fSPOT = 100 Hz 2.0 µV/√Hz

IN = –60 dBm, fSPOT = 10 MHz 1.3 µV/√Hz

Small Signal Response Time PIN = –60 dBm to –57 dBm, 10% to 90% 40 60 ns

Large Signal Response Time PIN = No signal to 0 dBm; settled to 0.5 dB 110 160 ns

VSET INTERFACE

Input Voltage Range 0 VPOS V

Input Impedance 18||1 kΩ||pF4

POWER-DOWN INTERFACE

PWDN Threshold VPOS/2 V

Power-Up Response Time Time delay following high to low transition

until device meets full specifications.

1.8 µs

PWDN Input Bias Current PWDN = 0 V 5 µA

PWDN = VS <1 µA

POWER SUPPLY

Operating Range 2.7 5.5 V

Powered-Up Current 13.7 15.5 mA

4.5 V ≤VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C 18.5 mA

2.7 V ≤VS ≤ 3.3 V, –40°C ≤ T ≤ +85°C 18.5 mA

Powered-Down Current 4.5 V ≤VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C 50 150 µA

2.7 V ≤VS ≤ 3.3 V, –40°C ≤ T ≤ +85°C 20 50 µA

AD8313

Rev. D | Page 5 of 24

1 Except where otherwise noted; performance at VS = 3 V is equivalent to 5 V operation.

2 Minimum and maximum specified limits on parameters that are guaranteed but not tested are 6 sigma values.

3 Input impedance shown over frequency range in Figure 26.

4 Double vertical bars (||) denote “in parallel with.”

5 Linear regression calculation for error curve taken from –40 dBm to –10 dBm for all parameters.

6 Dynamic range refers to range over which the linearity error remains within the stated bound.

7 Linear regression calculation for error curve taken from –60 dBm to –5 dBm for 3 dB dynamic range. All other regressions taken from –40 dBm to –10 dBm.

8 AC response shown in Figure 12.

AD8313

Rev. D | Page 6 of 24

ABSOLUTE MAXIMUM RATINGS

Table 2.

Supply Voltage VS5.5 V

VOUT, VSET, PWDN 0 V, VPOS

Input Power Differential (re: 50 Ω, 5.5 V) 25 dBm

Input Power Single-Ended (re: 50 Ω, 5.5 V) 19 dBm

Internal Power Dissipation 200 mW

θJA 200°C/W

Maximum Junction Temperature 125°C

Operating Temperature Range –40°C to +85°C

Storage Temperature Range –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

AD8313

Rev. D | Page 7 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTION

POS

INHI

INLO

POS

VOUT

VSET

COMM

PWDN

AD8313

TOP VIEW

(Not to Scale)

01085-C-003

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 4 VPOS Positive Supply Voltage (VPOS), 2.7 V to 5.5 V.

2 INHI Noninverting Input. This input should be ac-coupled.

3 INLO Inverting Input. This input should be ac-coupled.

5 PWDN Connect Pin to Ground for Normal Operating Mode. Connect this pin to the supply for power-down mode.

6 COMM Device Common.

7 VSET Setpoint Input for Operation in Controller Mode. To operate in RSSI mode, short VSET and VOUT.

8 VOUT Logarithmic/Error Output.

AD8313

Rev. D | Page 8 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = 5 V, RL input match shown in Figure 29, unless otherwise noted.

INPUT AMPLITUDE (dBm)

2.0

–70

OUT

(V)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0–60 –50 –40 –30 –20 –10 0 10

1.9GHz

2.5GHz

900MHz

100MHz

01085-C-004

Figure 4. VOUT vs. Input Amplitude

INPUT AMPLITUDE (dBm)

–6–70 10–60

ERROR (dB)

–50 –40 –30 –20 –10 0

–2

–4

900MHz

100MHz

900MHz

1.9GHz 2.5GHz

2.5GHz

1.9GHz

01085-C-005

Figure 5. Log Conformance vs. Input Amplitude

INPUT AMPLITUDE (dBm)

2.0

–70

OUT

(V)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0–60 –50 –40 –30 –20 –10 0 10

–1

–2

–3

–4

–5

ERROR (dB)

–40°C

+25°C

+85°C

SLOPE AND INTERCEPT NORMALIZED AT +25°C

AND APPLIED TO –40°C AND +85°C

01085-C-006

Figure 6. VOUT and Log Conformance vs. Input Amplitude at 100 MHz for

Multiple Temperatures

INPUT AMPLITUDE (dBm)

2.0

–70

VOUT (V)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0–60 –50 –40 –30 –20 –10 0 10

–1

–2

–3

–4

–5

ERROR (dB)

+25°C

+85°C

–40°C

SLOPE AND INTERCEPT NORMALIZED AT +25°C

AND APPLIED TO –40°C AND +85°C

01-85-C-007

Figure 7. VOUT and Log Conformance vs. Input Amplitude at 900 MHz for

Multiple Temperatures

INPUT AMPLITUDE (dBm)

2.0

–70

VOUT (V)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0–60 –50 –40 –30 –20 –10 0 10

–1

–2

–3

–4

–5

ERROR (dB)

–40°C

+25°C

+85°C

SLOPE AND INTERCEPT NORMALIZED AT +25°C

AND APPLIED TO –40°C AND +85°C

01085-C-008

Figure 8. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz for

Multiple Temperatures

INPUT AMPLITUDE (dBm)

2.0

–70

VOUT (V)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0–60 –50 –40 –30 –20 –10 0 10

–1

–2

–3

–4

–5

ERROR (dB)

–40°C

+25°C

+85°C

SLOPE AND INTERCEPT

NORMALIZED AT +25°C AND

APPLIED TO –40°C AND +85°C

01085-C-009

Figure 9. VOUT and Log Conformance vs. Input Amplitude at 2.5 GHz for

Multiple Temperatures

AD8313

Rev. D | Page 9 of 24

FREQUENCY (MHz)

16 0 2500500

SLOPE (mV/dB)

1000 1500 2000

–40°C

+25°C

+85°C

01085-C-010

Figure 10. VOUT Slope vs. Frequency for Multiple Temperatures

SUPPLY VOLTAGE (V)

2.5

SLOPE (mV/dB)

14 3.0 3.5 4.0 4.5 5.0 5.5 6.0

1.9GHz

2.5GHz

900MHz

100MHz

SPECIFIED OPERATING RANGE

01085-C-011

Figure 11. VOUT Slope vs. Supply Voltage

FREQUENCY (Hz)

VSET TO VOUT GAIN (dB)

100 1k 10k 100k

REF LEVEL = 92dB

SCALE: 10dB/DIV

01085-C-012

Figure 12. AC Response from VSET to VOUT

FREQUENCY (MHz)

–1100 2500500

INTERCEPT (dBm)

1000 1500 2000

–70

–80

–90

–100

+85°C

–40°C

+25°C

01085-C-013

Figure 13. VOUT Intercept vs. Frequency for Multiple Temperatures

SUPPLY VOLTAGE (V)

–70

2.5

INTERCEPT (dBm)

–75

–80

–85

–90

–95

–100

–105

–110 3.0 3.5 4.0 4.5 5.0 5.5 6.0

1.9GHz

2.5GHz

900MHz

100MHz

SPECIFIED OPERATING RANGE

01085-C-014

Figure 14. VOUT Intercept vs. Supply Voltage

FREQUENCY (Hz)

100

0.1

µV/ Hz

1k 10k 100k 1M 10M

2GHz RF INPUT

RF INPUT

–70dBm

–60dBm

–55dBm

–50dBm

–45dBm

–40dBm

–35dBm

–30dBm

01085-C-015

Figure 15. VOUT Noise Spectral Density

AD8313

Rev. D | Page 10 of 24

PWDN VOLTAGE (V)

100.00

SUPPLY CURRENT (mA)

10.00

1.00

0.10

0.01 21345

40µA

POS

= +3V V

POS

= +5V

20µA

13.7mA

01085-C-016

Figure 16. Typical Supply Current vs. PWDN Voltage

CH. 1 AND CH. 2: 1V/DIV CH. 3: 5V/DIV

HORIZONTAL: 1µs/DIV

OUT

= +5.5V

PWDN

CH. 1 GND

CH. 2 GND

CH. 3 GND

OUT

= +2.7V

01085-C-017

Figure 17. PWDN Response Time

CH. 1

CH. 1 GND

CH. 2 GND

CH. 2

CH. 1 AND CH. 2: 200mV/DIV AVERAGE: 50 SAMPLES

= +5.5V

= +2.7V

HORIZONTAL: 50ns/DIV

PULSED RF

100MHz, –45dBm

01085-C-019

Figure 18. Response Time, No Signal to –45 dBm

CH. 1 & CH. 2: 500mV/DIV AVERAGE: 50 SAMPLES

HORIZONTAL: 50ns/DIV

CH. 1 GND

CH. 2 GND PULSED RF

100MHz, 0dBm

CH. 1

CH. 2

= +5.5V

= +2.7V

01085-C-020

Figure 19. Response Time, No Signal to 0 dBm

________________________________________________________________________________________________________________________________

HP8648B

SIGNAL

GENERATOR

HP8112A

PULSE

GENERATOR

0.1µF

54.9Ω

0.01µF

10Ω

0.1µF

TEK

TDS784C

SCOPE

VPOS VOUT

INHI

INLO

VPOS PWDN

COMM

VSET

AD8313

TEK P6205

FET PROBE TRIG

0603 SIZE SURFACE

MOUNT COMPONENTS ON

A LOW LEAKAGE PC BOARD

EXT TRIG OUT

PIN = 0dBm

RF OUT

10MHz REF OUTPUT

01085-C-018

Figure 20. Test Setup for PWDN Response Time

0.1µF

54.9Ω

0.01µF

10Ω

0.1µF

TEK

TDS784C

SCOPE

VPOS VOUT

INHI

INLO

VPOS PWDN

COMM

VSET

AD8313

TEK P6205

FET PROBE TRIG

0603 SIZE SURFACE

MOUNT COMPONENTS ON

A LOW LEAKAGE PC BOARD

01085-C-021

TRIG

OUT

EXT TRIG

RF OUT

10MHz REF OUTPUT

–6dB

SPLITTER –6dB

HP8648B

SIGNAL

GENERATOR

PULSE

MODULATION

MODE

PULSE MODE IN OUT

HP8112A

PULSE

GENERATOR

Figure 21. Test Setup for RSSI Mode Pulse Response

AD8313

Rev. D | Page 11 of 24

CIRCUIT DESCRIPTION

The AD8313 is an 8-stage logarithmic amplifier, specifically

designed for use in RF measurement and power amplifier

control applications at frequencies up to 2.5 GHz. A block

diagram is shown in Figure 22. For a detailed description of

log amp theory and design principles, refer to the AD8307

data sheet.

++ +++

AD8313

VOUT

VSET

COMM

PWDN

GAIN

BIAS

BAND GAP

REFERENCE

SLOPE

CONTROL

INTERCEPT

CONTROL

EIGHT 8dB 3.5GHz AMPLIFIER STAGES

8dB 8dB

VPOS

INHI

INLO

VPOS

8dB8dB

NINE DETECTOR CELLS

INT

I→V

V→I

01085-C-001

Figure 22. Block Diagram

A fully differential design is used. Inputs INHI and INLO

(Pins 2 and 3) are internally biased to approximately 0.75 V

below the supply voltage, and present a low frequency impedance

of nominally 900 Ω in parallel with 1.1 pF. The noise spectral

density referred to the input is 0.6 nV/√Hz, equivalent to a

voltage of 35 V rms in a 3.5 GHz bandwidth, or a noise power of

−76 dBm re: 50 Ω. This sets the lower limit to the dynamic range;

the Applications section shows how to increase the sensitivity

by using a matching network or input transformer. However, the

low end accuracy of the AD8313 is enhanced by specially shaping

the demodulation transfer characteristic to partially compensate

for errors due to internal noise.

Each of the eight cascaded stages has a nominal voltage gain of

8 dB and a bandwidth of 3.5 GHz. Each stage is supported by

precision biasing cells that determine this gain and stabilize it

against supply and temperature variations. Since these stages are

direct-coupled and the dc gain is high, an offset compensation

loop is included. The first four stages and the biasing system are

powered from Pin 4, while the later stages and the output inter-

faces are powered from Pin 1. The biasing is controlled by a logic

interface PWDN (Pin 5); this is grounded for normal operation,

but may be taken high (to VS) to disable the chip. The threshold

is at VPOS/2 and the biasing functions are enabled and disabled

within 1.8 µs.

Each amplifier stage has a detector cell associated with its

output. These nonlinear cells perform an absolute value (full-

wave rectification) function on the differential voltages along

this backbone in a transconductance fashion; their outputs are

in current-mode form and are thus easily summed. A ninth

detector cell is added at the input of the AD8313. Since the

midrange response of each of these nine detector stages is

separated by 8 dB, the overall dynamic range is about 72 dB

(Figure 23). The upper end of this range is determined by the

capacity of the first detector cell, and occurs at approximately

0 dBm. The practical dynamic range is over 70 dB to the ±3 dB

error points. However, some erosion of this range can occur at

temperature and frequency extremes. Useful operation to over

3 GHz is possible, and the AD8313 remains serviceable at

10 MHz, needing only a small amount of additional ripple

filtering.

INPUT AMPLITUDE (dBm)

2.0

–80

OUT

(V)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0–70 –60 –50 –40 –30 –20 –10 0

–1

–2

–3

–4

–5

ERROR (dB)

–90

INTERCEPT = –100dBm

SLOPE = 18mV/dB

01085-c-023

Figure 23. Typical RSSI Response and Error vs. Input Power at 1.9 GHz

The fluctuating current output generated by the detector cells,

with a fundamental component at twice the signal frequency, is

filtered first by a low-pass section inside each cell, and then by

the output stage. The output stage converts these currents to a

voltage, VOUT, at VOUT (Pin 8), which can swing rail-to-rail. The

filter exhibits a 2-pole response with a corner at approximately

12 MHz and full-scale rise time (10% to 90%) of 40 ns. The

residual output ripple at an input frequency of 100 MHz has an

amplitude of under 1 mV. The output can drive a small resistive

load; it can source currents of up to 400 µA, and sink up to

10 mA. The output is stable with any capacitive load, though

settling time could be impaired. The low frequency incremental

output impedance is approximately 0.2 Ω.

In addition to its use as an RF power measurement device (that

is, as a logarithmic amplifier), the AD8313 may also be used in

controller applications by breaking the feedback path from

VOUT to VSET (Pin 7), which determines the slope of the

output (nominally 18 mV/dB). This pin becomes the setpoint

input in controller modes. In this mode, the voltage VOUT

remains close to ground (typically under 50 mV) until the

decibel equivalent of the voltage VSET is reached at the input,

when VOUT makes a rapid transition to a voltage close to VPOS

(see the Operating in Controller Mode section). The logarithmic

intercept is nominally positioned at −100 dBm (re: 50 Ω); this is

effective in both the log amp mode and the controller mode.

AD8313

Rev. D | Page 12 of 24

With Pins 7 and 8 connected (log amp mode), the output can be

stated as

)dBm100( += INSLOPEOUT PVV

where PIN is the input power stated in dBm when the source is

directly terminated in 50 Ω. However, the input impedance of

the AD8313 is much higher than 50 Ω, and the sensitivity of this

device may be increased by about 12 dB by using some type of

matching network (see below), which adds a voltage gain and

lowers the intercept by the same amount. Dependence on the ref-

erence impedance can be avoided by restating the expression as

)V2.2/(log20 µ×××= INSLOPEOUT VVV

where VIN is the rms value of a sinusoidal input appearing

across Pins 2 and 3; here, 2.2 µV corresponds to the intercept,

expressed in voltage terms. For detailed information on the

effect of signal waveform and metrics on the intercept

positioning for a log amp, refer to the AD8307 data sheet.

With Pins 7 and 8 disconnected (controller mode), the output

can be stated as

SETINSLOPESOUT VPVVV >→ )100/(logwhen

SETINSLOPEOUT VPVV <→ )100/(logwhen0

when the input is stated in terms of the power of a sinusoidal

signal across a net termination impedance of 50 Ω. The transition

zone between high and low states is very narrow since the output

stage behaves essentially as a fast integrator. The above equations

can be restated as

SETINSLOPESOUT VVVVV >µ→ )V2.2/(logwhen

SETINSLOPEOUT VVVV <µ→ )V2.2/(logwhen0

Another use of the separate VOUT and VSET pins is in raising

the load-driving current capability by including an external

NPN emitter follower. More complete information about usage

in these modes is provided in the Applications section.

AD8313

Rev. D | Page 13 of 24

INTERFACES

This section describes the signal and control interfaces and

their behavior. On-chip resistances and capacitances exhibit

variations of up to ±20%. These resistances are sometimes

temperature-dependent, and the capacitances may be voltage-

dependent.

POWER-DOWN INTERFACE, PWDN

The power-down threshold is accurately centered at the

midpoint of the supply as shown in Figure 24. If Pin 5 is left

unconnected or tied to the supply voltage (recommended), the

bias enable current is shut off, and the current drawn from the

supply is predominately through a nominal 300 kΩ chain

(20 µA at 3 V). When grounded, the bias system is turned on.

The threshold level is accurately at VPOS/2. When operating in

the device ON state, the input bias current at the PWDN pin is

approximately 5 µA for VPOS = 3 V.

PWDN

VPOS

75kΩ

OMM

150kΩ

50kΩ

150k

Ω

TO BIAS

ENABLE

01085-C-024

Figure 24. Power-Down Threshold Circuitry

SIGNAL INPUTS, INHI, INLO

The simplest low frequency ac model for this interface consists

of just a 900 Ω resistance, RIN, in shunt with a 1.1 pF input cap-

acitance, CIN, connected across INHI and INLO. Figure 25 shows

these distributed in the context of a more complete schematic.

The input bias voltage shown is for the enabled chip; when

disabled, it rises by a few hundred millivolts. If the input is

coupled via capacitors, this change may cause a low level signal

transient to be introduced, having a time constant formed by

these capacitors and RIN. For this reason, large coupling capacitors

should be well matched. This is not necessary when using the

small capacitors found in many impedance transforming

networks used at high frequencies.

1.25k

Ω

COMM

POS

INHI

INLO

POS

0.5pF

0.7pF

2.5k

Ω

2.5k

Ω

0.75V

(1ST DETECTOR)

250

Ω

1.4mA

125

Ω

125

Ω

1.25k

Ω

1.24V

GAIN BIAS

TO 2ND

STAGE

TO STAGES

1 TO 4

01085-C-025

Figure 25. Input Interface Simplified Schematic

For high frequency use, Figure 26 shows the input impedance

plotted on a Smith chart. This measured result of a typical

device includes a 191 mil 50 Ω trace and a 680 pF capacitor to

ground from the INLO pin.

1.1pF900Ω

1.9GHz

Frequency

100MHz

900MHz

1.9GHz

2.5GHz

650

+jX

–j400

–j135

–j65

–j43

2.5GHz

900MHz

100MHz

AD8313 MEASURED

01085-C-026

Figure 26. Typical Input Impedance

LOGARITHMIC/ERROR OUTPUT, VOUT

The rail-to-rail output interface is shown in Figure 27. VOUT can

run from within about 50 mV of ground, to within about 100 mV

of the supply voltage, and is short-circuit safe to either supply.

However, the sourcing load current, ISOURCE, is limited to that

which is provided by the PNP transistor, typically 400 µA.

Larger load currents can be provided by adding an external NPN

transistor (see the Applications section). The dc open-loop gain

of this amplifier is high, and it may be regarded as an integrator

having a capacitance of 2 pF (CINT) driven by the current-mode

signal generated by the summed outputs of the nine detector

stages, which is scaled approximately 4.0 µA/dB.

COMM

STAGE C

INT

LM 10mA

MAX

VOUT

BIAS I

SOURCE

400µA

VPOS

FROM

SETPOINT

SUMMED

DETECTOR

OUTPUTS

01085-C-027

Figure 27. Output Interface Circuitry

Thus, for midscale RF input of about 3 mV, which is some 40 dB

above the minimum detector output, this current is 160 µA, and

the output changes by 8 V/µs. When VOUT is connected to VSET,

the rise and fall times are approximately 40 ns (for RL ≥ 10 kΩ ).

The nominal slew rate is 2.5 V/µs. The HF compensation tech-

nique results in stable operation with a large capacitive load, CL,

though the positive-going slew rate is then limited by ISOURCE/CL

to 1 V/µs for CL = 400 pF.

AD8313

Rev. D | Page 14 of 24

SETPOINT INTERFACE, VSET

The setpoint interface is shown in Figure 28. The voltage, VSET, is

divided by a factor of 3 in a resistive attenuator of 18 kΩ total

resistance. The signal is converted to a current by the action of

the op amp and the resistor R3 (1.5 kΩ), which balances the

current generated by the summed output of the nine detector

cells at the input to the previous cell. The logarithmic slope is

nominally 3 µs × 4.0 µA/dB × 1.5 kΩ = 18 mV/dB.

VSET

VPOS

12kΩ

6kΩ

COMM

25µA

25µAFDBK

TO O/P

STAGE

1.5kΩ

01085-C-028

Figure 28. Setpoint Interface Circuitry

AD8313

Rev. D | Page 15 of 24

APPLICATIONS

BASIC CONNECTIONS FOR LOG (RSSI) MODE

Figure 29 shows the AD8313 connected in its basic measurement

mode. A power supply between 2.7 V and 5.5 V is required. The

power supply to each of the VPOS pins should be decoupled

with a 0.1 µF surface-mount ceramic capacitor and a 10 Ω series

resistor.

The PWDN pin is shown as grounded. The AD8313 may be

disabled by a logic high at this pin. When disabled, the chip

current is reduced to about 20 µA from its normal value of

13.7 mA. The logic threshold is at VPOS/2, and the enable

function occurs in about 1.8 µs. However, that additional

settling time is generally needed at low input levels. While the

input in this case is terminated with a simple 50 Ω broadband

resistive match, there are many ways in which the input termi-

nation can be accomplished. These are discussed in the Input

Coupling section.

VSET is connected to VOUT to establish a feedback path that

controls the overall scaling of the logarithmic amplifier. The

load resistance, RL, should not be lower than 5 kΩ so that the

full-scale output of 1.75 V can be generated with the limited

available current of 400 µA max.

As stated in the Absolute Maximum Ratings table, an externally

applied overvoltage on the VOUT pin, which is outside the

range 0 V to VPOS, is sufficient to cause permanent damage to

the device. If overvoltages are expected on the VOUT pin, a

series resistor, RPROT, should be included as shown. A 500 Ω

resistor is sufficient to protect against overvoltage up to ±5 V;

1000 Ω should be used if an overvoltage of up to ±15 V is

expected. Since the output stage is meant to drive loads of no

more than 400 μA, this resistor does not impact device perform-

ance for higher impedance drive applications (higher output

current applications are discussed in the Increasing Output

Current section).

0.1µF

53.6Ω

680pF

10Ω

0.1µF

VPOS VOUT

INHI

INLO

VPOS PWDN

COMM

VSET

AD8313

PROT

= 1MΩ

01085-C-029

Figure 29. Basic Connections for Log (RSSI) Mode

OPERATING IN CONTROLLER MODE

Figure 30 shows the basic connections for operation in controller

mode. The link between VOUT and VSET is broken and a set-

point is applied to VSET. Any difference between VSET and the

equivalent input power to the AD8313 drives VOUT either to the

supply rail or close to ground. If VSET is greater than the equivalent

input power, VOUT is driven toward ground, and vice versa.

0.1µF

10Ω

0.1µF

VPOS VOUT

INHI

INLO

VPOS PWDN

COMM

VSET

AD8313

PROT

01085-C-030

Figure 30. Basic Connections for Operation in the Controller Mode

This mode of operation is useful in applications where the output

power of an RF power amplifier (PA) is to be controlled by an

analog AGC loop (Figure 31). In this mode, a setpoint voltage,

proportional in dB to the desired output power, is applied to the

VSET pin. A sample of the output power from the PA, via a

directional coupler or other means, is fed to the input of the

AD8313.

SETPOINT

CONTROL DAC

RFIN VOUT

VSET

AD8313

DIRECTIONAL

COUPLER

POWER

AMPLIFIER RF IN

ENVELOPE OF

RANSMITTED

IGNAL

01085-C-031

Figure 31. Setpoint Controller Operation

VOUT is applied to the gain control terminal of the power

amplifier. The gain control transfer function of the power

amplifier should be an inverse relationship, that is, increasing

voltage decreases gain.

A positive input step on VSET (indicating a demand for increased

power from the PA) drives VOUT toward ground. This should be

arranged to increase the gain of the PA. The loop settles when

VOUT settles to a voltage that sets the input power to the AD8313

to the dB equivalent of VSET.

AD8313

Rev. D | Page 16 of 24

INPUT COUPLING

The signal can be coupled to the AD8313 in a variety of ways.

In all cases, there must not be a dc path from the input pins to

ground. Some of the possibilities include dual-input coupling

capacitors, a flux-linked transformer, a printed circuit balun,

direct drive from a directional coupler, or a narrow-band

impedance matching network.

Figure 32 shows a simple broadband resistive match. A

termination resistor of 53.6 Ω combines with the internal input

impedance of the AD8313 to give an overall resistive input

impedance of approximately 50 Ω. It is preferable to place the

termination resistor directly across the input pins, INHI to

INLO, where it lowers the possible deleterious effects of dc

offset voltages on the low end of the dynamic range. At low

frequencies, this may not be quite as beneficial, since it requires

larger coupling capacitors. The two 680 pF input coupling

capacitors set the high-pass corner frequency of the network at

9.4 MHz.

RMATCH

53.6Ω

680pF

CIN RIN

AD8313

50Ω

50ΩSOURCE

01085-C-032

Figure 32. A Simple Broadband Resistive Input Termination

The high-pass corner frequency can be set higher according to

the equation

502

3××π×

fdB

where:

C2C1 C2C1

C×

In high frequency applications, the use of a transformer, balun,

or matching network is advantageous. The impedance matching

characteristics of these networks provide what is essentially a

gain stage before the AD8313 that increases the device sensitivity.

This gain effect is explored in the following matching example.

Figure 33 and Figure 34 show device performance under these

three input conditions at 900 MHz and 1.9 GHz.

While the 900 MHz case clearly shows the effect of input

matching by realigning the intercept as expected, little

improvement is seen at 1.9 GHz. Clearly, if no improvement

in sensitivity is required, a simple 50 Ω termination may be

the best choice for a given design based on ease of use and

cost of components.

INPUT AMPLITUDE (dBm)

–80 –70 –60 –50 –40 –30 –20 –10

–1

–2

–3

ERROR (dB)

TERMINATED

DR = 66dB

–90 100

BALANCED

MATCHED

BALANCED

DR = 71dB

MATCHED

DR = 69dB

01085-C-033

Figure 33. Comparison of Terminated, Matched, and Balanced

Input Drive at 900 MHz

INPUT AMPLITUDE (dBm)

–80 –70 –60 –50 –40 –30 –20 –10 0

–1

–2

–3

ERROR (dB)

–90 10

TERMINATED

DR = 75dB

BALANCED

DR = 75dB

MATCHED

DR = 73dB

MATCHED

TERMINATED

01085-C-034

Figure 34. Comparison of Terminated, Matched, and Balanced

Input Drive at 1.9 GHz

NARROW-BAND LC MATCHING EXAMPLE

AT 100 MHz

While numerous software programs provide an easy way to

calculate the values of matching components, a clear under-

standing of the calculations involved is valuable. A low frequency

(100 MHz) value has been used for this example because of the

deleterious board effects at higher frequencies. RF layout

simulation software is useful when board design at higher

frequencies is required.

A narrow-band LC match can be implemented either as a

series-inductance/shunt-capacitance or as a series-capacitance/

shunt-inductance. However, the concurrent requirement that

the AD8313 inputs, INHI and INLO, be ac-coupled, makes a

series-capacitance/shunt-inductance type match more

appropriate (Figure 35).

AD8313

Rev. D | Page 17 of 24

LMATCH

CIN RIN

AD8313

50Ω

50ΩSOURCE

01085-C-035

Figure 35. Narrow-Band Reactive Match

Typically, the AD8313 needs to be matched to 50 Ω. The input

impedance of the AD8313 at 100 MHz can be read from the

Smith chart (Figure 26) and corresponds to a resistive input

impedance of 900 Ω in parallel with a capacitance of 1.1 pF.

To make the matching process simpler, the AD8313 input cap-

acitance, CIN, can be temporarily removed from the calculation

by adding a virtual shunt inductor (L2), which resonates away

CIN (Figure 36). This inductor is factored back into the calculation

later. This allows the main calculation to be based on a simple

resistive-to-resistive match, that is, 50 Ω to 900 Ω.

The resonant frequency is defined by the equation

CL2 ×

=ω 1

therefore,

H3.2

2µ=

MATCH

=(C1 × C2)

(C1 + C2)

AD8313

50Ω

50ΩSOURCE

01085-C-036

TEMPORARY

INDUCTANCE

MATCH

=(C1 × C2)

(C1 + C2)

Figure 36. Input Matching Example

With CIN and L2 temporarily out of the picture, the focus is now

on matching a 50 Ω source resistance to a (purely resistive) load

of 900 Ω and calculating values for CMATCH and L1. When

MATCH

INS CL1

RR =

the input looks purely resistive at a frequency given by

MHz100

×π

MATCH

0CL1

Solving for CMATCH gives

pF5.7

×= f

CINS

MATCH

Solving for L1 gives

nH6.337

L1 INS

Because L1 and L2 are parallel, they can be combined to give the

final value for LMATCH, that is,

nH294=

=L2L1 L2L1

LMATCH

C1 and C2 can be chosen in a number of ways. First, C2 can be

set to a large value, for example, 1000 pF, so that it appears as an

RF short. C1 would then be set equal to the calculated value of

CMATCH. Alternatively, C1 and C2 can each be set to twice CMATCH

so that the total series capacitance is equal to CMATCH. By making

C1 and C2 slightly unequal (that is, select C2 to be about 10%

less than C1) but keeping their series value the same, the ampli-

tude of the signals on INHI and INLO can be equalized so that

the AD8313 is driven in a more balanced manner. Any of the

options detailed above can be used provided that the combined

series value of C1 and C2, that is, C1 × C2/(C1 + C2) is equal to

CMATCH.

In all cases, the values of CMATCH and LMATCH must be chosen

from standard values. At this point, these values need now be

installed on the board and measured for performance at

100 MHz. Because of board and layout parasitics, the component

values from the preceding example had to be tuned to the final

values of CMATCH = 8.9 pF and LMATCH = 270 nH as shown in

Tabl e 4.

Assuming a lossless matching network and noting conservation

of power, the impedance transformation from RS to RIN (50 Ω to

900 Ω) has an associated voltage gain given by

dB6.12log20

dB =×= S

Gain

Because the AD8313 input responds to voltage and not to true

power, the voltage gain of the matching network increases the

effective input low-end power sensitivity by this amount. Thus,

in this case, the dynamic range is shifted downward, that is, the

12.6 dB voltage gain shifts the 0 dBm to −65 dBm input range

downward to −12.6 dBm to −77.6 dBm. However, because of

network losses, this gain is not be fully realized in practice.

Refer to Figure 33 and Figure 34 for an example of practical

attainable voltage gains.

Tabl e 4 shows recommended values for the inductor and cap-

acitors in Figure 35 for some selected RF frequencies in addition

to the associated theoretical voltage gain. These values for a

reactive match are optimal for the board layout detailed as

Figure 45.

AD8313

Rev. D | Page 18 of 24

As previously discussed, a modification of the board layout

produces networks that may not perform as specified. At 2.5 GHz,

a shunt inductor is sufficient to achieve proper matching. Con-

sequently, C1 and C2 are set sufficiently high that they appear as

RF shorts.

Table 4. Recommended Values for C1, C2, and

LMATCH in Figure 35

Freq.

(MHz)

CMATCH

(pF)

LMATCH

(nH)

Voltage

Gain(dB)

100 8.9 22 15 270 12.6

1000 270

900 1.5 3 3 8.2 9.0

1.5 1000 8.2

1900 1.5 3 3 2.2 6.2

1.5 1000 2.2

2500 Large 390 390 2.2 3.2

Figure 37 shows the voltage response of the 100 MHz matching

network. Note the high attenuation at lower frequencies typical

of a high-pass network.

FREQUENCY (MHz)

VOLTAGE GAIN (dB)

–5 100 200

01085-C-037

Figure 37. Voltage Response of 100 MHz Narrow-Band Matching Network

ADJUSTING THE LOG SLOPE

Figure 38 shows how the log slope can be adjusted to an exact

value. The idea is simple: the output at the VOUT pin is attenu-

ated by the variable resistor R2 working against the internal 18 kΩ

of input resistance at the VSET pin. When R2 is 0, the attenu-

ation it introduces is 0, and thus the slope is the basic 18 mV/dB.

Note that this value varies with frequency, (Figure 10). When R2

is set to its maximum value of 10 kΩ, the attenuation from

VOUT to VSET is the ratio 18/(18 + 10), and the slope is raised

to (28/18) × 18 mV, or 28 mV/dB. At about the midpoint, the

nominal scale is 23 mV/dB. Thus, a 70 dB input range changes

the output by 70 × 23 mV, or 1.6 V.

0.1µF

10Ω

10kΩ

0.1µF

+VS

VPOS VOUT

INHI

INLO

VPOS PWDN

COMM

VSET

AD8313

01085-C-038

18–30mV/dB

Figure 38. Adjusting the Log Slope

As stated, the unadjusted log slope varies with frequency from

17 mV/dB to 20 mV/dB, as shown in Figure 10. By placing a

resistor between VOUT and VSET, the slope can be adjusted to

a convenient 20 mV/dB as shown in Figure 39.

Table 5 shows the recommended values for this resistor, REXT.

Also shown are values for REXT, which increase the slope to

approximately 50 mV/dB. The corresponding voltage swings

for a −65 dBm to 0 dBm input range are also shown in Table 6.

0.1µF

10Ω

REXT

0.1µF

+VS

VPOS VOUT

INHI

INLO

VPOS PWDN

COMM

VSET

AD8313

01085-C-039

20mV/dB

Figure 39. Adjusting the Log Slope to a Fixed Value

Table 5. Values for R in Figure 39

EXT

Frequency

MHz

REXT

Slope

mV/dB

VOUT Swing for Pin

−65 dBm to 0 dBm – V

100 0.953 20 0.44 to 1.74

900 2.00 20 0.58 to 1.88

1900 2.55 20 0.70 to 2.00

2500 0 20 0.54 to 1.84

100 29.4 50 1.10 to 4.35

900 32.4 50.4 1.46 to 4.74

1900 33.2 49.8 1.74 to 4.98

2500 26.7 49.7 1.34 to 4.57

The value for REXT is calculated by

(

)

Ω×

−

=k18

SlopeOriginal SlopeOriginalSlopeNew

REXT

The value for the Original Slope, at a particular frequency, can

be read from Figure 10. The resulting output swing is calculated

by simply inserting the New Slope value and the intercept at that

frequency (Figure 10 and Figure 13) into the general equation

for the AD8313’s output voltage:

VOUT = Slope(PIN − Intercept)

AD8313

Rev. D | Page 19 of 24

INCREASING OUTPUT CURRENT

To drive a more substantial load, either a pull-up resistor or an

emitter-follower can be used.

In Figure 40, a 1 kΩ pull-up resistor is added at the output,

which provides the load current necessary to drive a 1 kΩ load

to 1.7 V for VS = 2.7 V. The pull-up resistor slightly lowers the

intercept and the slope. As a result, the transfer function of the

AD8313 is shifted upward (intercept shifts downward).

0.1µF

10Ω

0.1µF

VPOS VOUT

INHI

INLO

VPOS PWDN

COMM

VSET

AD8313

01085-C-040

1kΩ

= 1kΩ

20mV/dB

Figure 40. Increasing AD8313 Output Current Capability

In Figure 41, an emitter-follower provides the current gain,

when a 100 Ω load can readily be driven to full-scale output.

While a high ß transistor such as the BC848BLT1 (min ß = 200)

is recommended, a 2 kΩ pull-up resistor between VOUT and

+VS can provide additional base current to the transistor.

MIN

= 200

0.1µF

10Ω

0.1µF

VPOS VOUT

INHI

INLO

VPOS PWDN

COMM

VSET

AD8313

01085-C-041

100Ω

OUTPUT13kΩ

10kΩ

BC848BLT1

Figure 41. Output Current Drive Boost Connection

In addition to providing current gain, the resistor/potentiometer

combination between VSET and the emitter of the transistor

increases the log slope to as much as 45 mV/dB, at maximum

resistance. This gives an output voltage of 4 V for a 0 dBm input.

If no increase in the log slope is required, VSET can be connected

directly to the emitter of the transistor.

EFFECT OF WAVEFORM TYPE ON INTERCEPT

Although specified for input levels in dBm (dB relative to

1 mW), the AD8313 responds to voltage and not to power. A

direct consequence of this characteristic is that input signals of

equal rms power but differing crest factors produce different

results at the log amp’s output.

Different signal waveforms vary the effective value of the log

amp’s intercept upward or downward. Graphically, this looks

like a vertical shift in the log amp’s transfer function. The

device’s logarithmic slope, however, is in principle not affected.

For example, if the AD8313 is being fed alternately from a

continuous wave and from a single CDMA channel of the same

rms power, the AD8313 output voltage differs by the equivalent

of 3.55 dB (64 mV) over the complete dynamic range of the

device (the output for a CDMA input being lower).

Table 6 shows the correction factors that should be applied to

measure the rms signal strength of a various signal types. A

continuous wave input is used as a reference. To measure the

rms power of a square wave, for example, the mV equivalent of

the dB value given in the table (18 mV/dB × 3.01 dB) should be

subtracted from the output voltage of the AD8313.

Table 6. Shift in AD8313 Output for Signals with

Differing Crest Factors

Signal Type Correction Factor

(Add to Output Reading)

CW Sine Wave 0 dB

Square Wave or DC −3.01 dB

Triangular Wave +0.9 dB

GSM Channel (All Time Slots On) +0.55 dB

CDMA Channel +3.55 dB

PDC Channel (All Time Slots On) +0.58 dB

Gaussian Noise +2.51 dB

AD8313

Rev. D | Page 20 of 24

EVALUATION BOARD

SCHEMATIC AND LAYOUT

Figure 44 shows the schematic of the AD8313 evaluation board.

Note that uninstalled components are indicated as open. This

board contains the AD8313 as well as the AD8009 current-

feedback operational amplifier.

This is a 4-layer board (top and bottom signal layers, ground,

and power). The top layer silkscreen and layout are shown in

Figure 42 and Figure 43. A detailed drawing of the recommended

PCB footprint for the MSOP package and the pads for the

matching components are shown in Figure 45.

The vacant portions of the signal and power layers are filled out

with ground plane for general noise suppression. To ensure a low

impedance connection between the planes, there are multiple

through-hole connections to the RF ground plane. While the

ground planes on the power and signal planes are used as

general-purpose ground returns, any RF grounds related to the

input matching network (for example, C2) are returned directly

to the RF internal ground plane.

GENERAL OPERATION

The AD8313 should be powered by a single supply in the range

of 2.7 V to 5.5 V. The power supply to each AD8313 VPOS pin is

decoupled by a 10 Ω resistor and a 0.1 µF capacitor. The AD8009

can run on either single or dual supplies, +5 V to ±6 V. Both the

positive and negative supply traces are decoupled using a 0.1 µF

capacitor. Pads are provided for a series resistor or inductor to

provide additional supply filtering.

The two signal inputs are ac-coupled using 680 pF high quality

RF capacitors (C1, C2). A 53.6 Ω resistor across the differential

signal inputs (INHI, INLO) combines with the internal 900 Ω

input impedance to give a broadband input impedance of 50.6 Ω.

This termination is not optimal from a noise perspective due to

the Johnson noise of the 53.6 Ω resistor. Neither does it account

for the AD8313’s reactive input impedance nor for the decrease

over frequency of the resistive component of the input imped-

ance. However, it does allow evaluation of the AD8313 over its

complete frequency range without having to design multiple

matching networks.

For optimum performance, a narrow-band match can be

implemented by replacing the 53.6 Ω resistor (labeled L/R) with

an RF inductor and replacing the 680 pF capacitors with

appropriate values. The Narrow-Band LC Matching Example

at 100 MHz section includes a table of recommended values for

selected frequencies and explains the method of calculation.

Switch 1 is used to select between power-up and power-down

modes. Connecting the PWDN pin to ground enables normal

operation of the AD8313. In the opposite position, the PWDN

pin can be driven externally (SMA connector labeled ENBL) to

either device state, or it can be allowed to float to a disabled

device state.

The evaluation board comes with the AD8313 configured to

operate in RSSI/measurement mode. This mode is set by the

0 Ω resistor (R11), which shorts the VOUT and VSET pins to

each other. When using the AD8009, the AD8313 logarithmic

output appears on the SMA connector labeled VOUT. Using

only the AD8313, the log output can be measured at TP1 or the

SMA connector labeled VSET.

USING THE AD8009 OPERATIONAL AMPLIFIER

The AD8313 can supply only 400 µA at VOUT. It is also sensitive

to capacitive loading, which can cause inaccurate measurements,

especially in applications where the AD8313 is used to measure

the envelope of RF bursts.

The AD8009 alleviates both of these issues. It is an ultrahigh

speed current feedback amplifier capable of delivering over

175 mA of load current, with a slew rate of 5,500 V/µs, which

results in a rise time of 545 ps, making it ideal as a pulse amplifier.

The AD8009 is configured as a buffer amplifier with a gain of 1.

Other gain options can be implemented by installing the appro-

priate resistors at R10 and R12.

Various output filtering and loading options are available using

R5, R6, and C6. Note that some capacitive loads may cause the

AD8009 to become unstable. It is recommended that a 42.2 Ω

resistor be installed at R5 when driving a capacitive load. More

details can be found in the AD8009 data sheet.

VARYING THE LOGARITHMIC SLOPE

The slope of the AD8313 can be increased from its nominal

value of 18 mV/dB to a maximum of 40 mV/dB by removing

R11, the 0 Ω resistor, which shorts VSET to VOUT. VSET and

VOUT are now connected through the 20 kΩ potentiometer.

The AD8009 must be configured for a gain of 1 to accurately

vary the slope of the AD8313.

OPERATING IN CONTROLLER MODE

To put the AD8313 into controller mode, R7 and R11 should

be removed, breaking the link between VOUT and VSET. The

VSET pin can then be driven externally via the SMA connector

labeled VSET.

RF BURST RESPONSE

The VOUT pin of the AD8313 is very sensitive to capacitive

loading, as a result care must be taken when measuring the

device’s response to RF bursts. For best possible response time

measurements it is recommended that the AD8009 be used to

buffer the output from the AD8313. No connection should be

made to TP1, the added load will effect the response time.

AD8313

Rev. D | Page 21 of 24

001085-C-048

Figure 42. Layout of Signal Layer

01085-C-049

Figure 43. Signal Layer Silkscreen

AD8313

Rev. D | Page 22 of 24

VPS1

01085-C-046

10Ω

EXT ENABLE

SW1

10Ω1

INHI

INLO

VPOS PWDN

COMM

VSET

AD8313 8

INHI

VOUT

EXT VSET

AD8009

VPOS VOUT

0.1µF

680pF

0.1µF

0Ω

R12

301Ω

0Ω

R11

0Ω

0ΩR2

10Ω

L/R

53.6Ω

VNEG

VPS2

INLO

TP1

Z1 Z2

R10

OPEN

20kΩ

OPEN

0.1µF

Figure 44. Evaluation Board Schematic

Table 7. Evaluation Board Configuration Options

Component Function Default

VPS1, VPS2,

GND, VNEG

Supply Pins. VPS1 is the positive supply pin for the AD8313. VPS2 and VNEG are the

positive and negative supply pins for the AD8009. If the AD8009 is being operated

from a single supply, VNEG should be connected to GND. VPS1 and VPS2 are

independent. GND is shared by both devices.

Not Applicable

Z1 AD8313 Logarithmic Amplifier. If the AD8313 is used in measurement mode, it is not

necessary to power up the AD8009 op amp. The log output can be measured at TP1 or

at the SMA connector labeled VSET.

Installed

Z1 AD8009 Operational Amplifier. Installed

SW1 Device Enable. When in Position A, the PWDN pin is connected to ground and the

AD8313 is in normal operating mode. In Position B, the PWDN pin is connected to an

SMA connector labeled ENBL. A signal can be applied to this connector.

SW1 = A

R7, R8 Slope Adjust. The slope of the AD8313 can be increased from its nominal value of

18 mV/dB to a maximum of 40 mV/dB by removing R11, the 0 Ω resistor, which shorts

VSET to VOUT, and installing a 0 Ω resistor at R7. The 20 kΩ potentiometer at R8 can

then be used to change the slope.

R7 = 0 Ω (Size 0603)

R8 = installed

Operating in Controller Mode. To put the AD8313 into controller mode, R7 and R11

should be removed, breaking the link between VOUT and VSET. The VSET pin can then

be driven externally via the SMA connector labeled VSET.

L/R, C1, C2, R9 Input Interface. The 52.3 Ω resistor in position L/R, along with C1 and C2, create a

wideband 50 Ω input. Alternatively, the 52.3 Ω resistor can be replaced by an inductor

to form an input matching network. See Input Coupling section for more details.

Remove the 0 Ω resistor at R9 for differential drive applications.

L/R = 53.6 Ω (Size 0603)

C1 = C2 = 680 pF (Size 0603)

R9 = 0 Ω (Size 0603)

R10, R12 Op Amp Gain Adjust. The AD8009 is initially configured as a buffer; gain = 1. To increase

the gain of the op amp, modify the resistor values R10 and R12.

R10 = open (Size 0603)

R12 = 301 Ω (Size 0603)

R5, R6, C6 Op Amp Output Loading/Filtering. A variety of loading and filtering options are

available for the AD8009. The robust output of the op amp is capable of driving low

impedances such as 50 Ω or 75 Ω, configure R5 and R6 accordingly. See the AD8009

data sheet for more details.

R5 = 0 Ω (Size 0603)

R6 = open (Size 0603)

C6 = open (Size 0603)

R1, R2, R3, R4,

C3, C4, C5, C7

Supply Decoupling. R1 = R2 = 10 Ω (Size 0603)

R3 = R4 = 0 Ω (Size 0603)

C3 = C4 = 0.1 µF (Size 0603)

C5 = C7 = 0.1 µF (Size 0603)

AD8313

Rev. D | Page 23 of 24

48 54.4 90.6

27.5

75 50

41 22

48 51.7 91.3

126

TRACE WIDTH

15.4

NOT CRITICAL DIMENSIONS

UNIT = MILS

01085-C-047

Figure 45. Detail of PCB Footprint for Package and Pads for Matching Network

AD8313

Rev. D | Page 24 of 24

OUTLINE DIMENSIONS

0.80

0.60

0.40

8°

0°

4.90

BSC

PIN 1 0.65 BSC

3.00

BSC

SEATING

PLANE

0.15

0.00

0.38

0.22

1.10 MAX

3.00

BSC

COPLANARITY

0.10

0.23

0.08

COMPLIANT TO JEDEC STANDARDS MO-187AA

Figure 46 . 8-Lead MicroSOIC Package [MSOP]

(RM-08)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Descriptions Package Option Branding

AD8313ARM −40°C to +85°C 8-Lead MSOP RM-08 J1A

AD8313ARM-REEL −40°C to +85°C 13" Tape and Reel RM-08 J1A

AD8313ARM-REEL7 −40°C to +85°C 7" Tape and Reel RM-08 J1A

AD8313ARMZ1−40°C to +85°C 8-Lead MSOP

AD8313ARMZ-REEL71−40°C to +85°C 7" Tape and Reel

AD8313-EVAL Evaluation Board

1 Z = Pb-free part.

registered trademarks are the property of their respective owners.

C01085–0–6/04(D)