© 2001 Fairchild Semiconductor Corporation DS012464 www.fairchildsemi.com
May 1995
Revised April 2001
74LCX16543 Low Voltage 16-Bit Regist ered Transceiver with 5V Tolerant Inputs and Outputs
74LCX16543
Low Voltage 16-Bit Registered Transceive r
with 5V Tolerant Inputs and Outputs
General Description
The LCX16 543 con tain s sixteen no n-inver ting transceive rs
containing two sets of D-type registers for temporary stor-
age of data fl owin g i n eith er dir ecti o n. Each byte ha s sepa-
rate control inputs which can be shorted together for full
16-bit operation. Separate Latch Enable and Output
Enable inputs are provided for each register to permit inde-
pendent i nput an d output co ntrol in eith er dir ection of da ta
flow.
The LCX1 6543 is designed for low vo ltage (2.5V or 3 .3V)
VCC applications with capability of interfacing to a 5V signal
environment.
The LCX16543 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
5V tolerant inputs and outputs
2.3V–3.6V VCC specifications provided
5.2 ns tPD max (VCC = 3.3V), 20 µA ICC max
Power down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
±24 mA Output Drive (VCC = 3.0V)
Implements patented noise/EMI reduction circuitry
Latch-up per for man c e exce eds 500 mA
ESD performance :
Human Body Model > 2000V
Machine Model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull- up resist or: the min imum va lue or the
resisto r is det ermin ed by the current-so urc ing capability of th e driver.
Ordering Code:
Devices also available in Tape and R eel. Speci fy by appe nding the s uffix let t er X to the ordering code.
Connection Diagram Logic Symbol
Order Number Package Number Package Description
74LCX16543MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LCX16543MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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74LCX16543
Pin Descriptions
Data I/O Control Table
H = HIGH Voltage Le ve l
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn
Functional Description
The LCX 16543 contains six teen no n-inver ting tran sceive rs
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. The control pins may be shorted together to obtain
full 16-bit operation. The following description applies to
each byte. For data flow from A to B, for example, the
A-to-B Enable (CEABn) input must be LOW in order to
enter da ta from A0A15 or take data from B0B15, as indi-
cated in the Data I/O Control Table. With CEABn LOW, a
LOW signal on the A-to-B Latch Enable (LEABn) input
makes the A - to- B la tch es tr ans par ent ; a subsequ ent LOW-
to-HIGH transition of the LEABn sign al p u ts t h e A la t che s i n
the storage mode and their outputs no longer change with
the A inputs. With CEABn and OEABn both LOW, the
3-STATE B output buffers are active and reflect the data
present at the output o f the A latch es. Control o f data flo w
from B to A is similar, but using the CEBAn, LEBAn and
OEBAn inputs.
Pin Names Description
OEABnA-to-B Output Enable Input (Active LOW)
OEBAnB-to-A Output Enable Input (Active LOW)
CEABnA-to-B Enable Input (Active LOW)
CEBAnB-to-A Enable Input (Active LOW)
LEABnA-to-B Latch Enable In put (Active LOW)
LEBAnB-to-A Latch Enable In put (Active LOW)
A0A15 A-to-B Data Inputs or B-to-A 3-STATE Outputs
B0B15 B-to-A Data Inputs or A-to-B 3-STATE Outputs
Inpu ts Latc h St at us Outp ut Buf fe rs
CEABnLEABnOEABn(Byte n) (Byte n)
H X X Latched High Z
X H X Latched
L L X Transparent
XXH High Z
LXL Driving
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74LCX16543
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please not e t hat these diagram s are provided only fo r t he unders t anding of logic operations a nd should not be used to estim ate propagation delays.
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74LCX16543
Absolute Maximum Ratings(Note 2)
Recommended Operating Conditions (Note 4)
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recom-
mend ed Operating Co nditions ta ble will defi ne t he cond it ions for act ual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Unused (inputs or I/Os) must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol Parameter Value Conditions Units
VCC Supply Voltage 0.5 to +7.0 V
VIDC Input Voltage 0.5 to +7.0 V
VODC Output Voltage 0.5 to +7.0 Output in 3-STATE V
0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 3)
IIK DC Input Diode Current 50 VI < GND mA
IOK DC Output Diode Current 50 VO < GND mA
+50 VO > VCC
IODC Output Source/Sink Current ±50 mA
ICC DC Supply Current per Supply Pin ±100 mA
IGND DC Ground Cu rrent per Ground Pin ±100 mA
TSTG Storage Temperature 65 to +150 °C
Symbol Parameter Min Max Units
VCC Supply Voltage Operati ng 2.0 3.6 V
Data Retention 1.5 3.6
VIInput Voltage 0 5.5 V
VOOutput Voltage HIGH or LOW State 0 VCC V
3-STATE 0 5.5
IOH/IOL Output Current VCC = 3.0V 3.6V ±24 mAVCC = 2.7V 3.0V ±12
VCC = 2.3V 2.7V ±8
TAFree-Air Operating Temperature 40 85 °C
t/V Input Edge Rate, VIN = 0.8V2.0V, VCC = 3.0V 0 10 ns/V
Symbol Parameter Conditions VCC TA = 40°C to +85°CUnits
(V) Min Max
VIH HIGH Level Input V oltag e 2.3 2.7 1.7 V
2.7 3.6 2.0
VIL LOW Level Input Voltage 2.3 2.7 0.7 V
2.7 3.6 0.8
VOH HIGH Level Output Voltage IOH = 100 µA2.3 3.6 VCC 0.2
V
IOH = 8 mA 2.3 1.8
IOH = 12 mA 2.7 2.2
IOH = 18 mA 3.0 2.4
IOH = 24 mA 3.0 2.2
VOL LOW Level Output Voltage IOL = 100 µA2.3 3.6 0.2
V
IOL = 8 mA 2.3 0.6
IOL = 12 mA 2.7 0.4
IOL = 16 mA 3.0 0.4
IOL = 24 mA 3.0 0.55
IIInput Leakage Current 0 VI 5.5V 2.3 3.6 ±5.0 µA
IOZ 3-STATE I/O Leakage 0 VO 5.5V 2.3 3.6 ±5.0 µA
VI = VIH or VIL
IOFF Power-Off Leakage Current VI or VO = 5.5V 0 10 µA
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74LCX16543
DC Electrical Characteristics (Continued)
Note 5: Outputs in disabled or 3-STATE only.
AC Electrical Characteristics
Note 6: Skew is def ined as t he absolute va lue of the differenc e betwee n the ac tu al propa gation d elay for any two s eparate outpu ts of the same d evi ce. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (t OSLH). Param eter gu ar antee d by design .
Dynamic Switching Characteristics
Capacitance
Symbol Parameter Conditions VCC TA = 40°C to +85°CUnits
(V) Min Max
ICC Quiescent Supply Current VI = VCC or GND 2.3 3.6 20 µA
3.6V VI, VO 5.5V (Note 5) 2.3 3.6 ±20
ICC Increase in ICC per Input VIH = VCC 0.6V 2.3 3.6 500 µA
Symbol Parameter
TA = 40°C to +85°C, RL = 500
Units
VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V
CL = 50 pF CL = 50 pF CL = 30 pF
Min Max Min Max Min Max
tPHL Propagation Delay 1.5 5.2 1.5 6.0 1.5 6.2 ns
tPLH An to Bn or Bn to An1.55.21.56.01.56.2
tPHL Propagation Delay 1.5 6.5 1.5 7.5 1.5 7.8 ns
tPLH LEBAn to An or LEABn to Bn1.56.51.57.51.57.8
tPZL Output Enable Time
tPZH OEBAn or OEABn to An or Bn1.56.51.57.01.58.5 ns
CEBAn or CEABn to An or Bn1.56.51.57.01.58.5
tPLZ Output Disable Time
tPHZ OEBAn or OEABn to An or Bn1.56.51.57.01.57.8 ns
CEBAn or CEABn to An or Bn1.56.51.57.01.57.8
tSSetup Time, HIGH or LOW, 2.5 2.5 3.0 ns
Data to LEXXn
tHHold Time, HIGH or LOW, 1.5 1.5 2.0 ns
Data to LEXXn
tWPulse Width, Latch Enable, LOW 3.0 3.0 3.5 ns
tOSHL Output to Output Skew (Note 6) 1.0 ns
tOSLH 1.0
Symbol Parameter Conditions VCC TA = 25°CUnits
(V) Typical
VOLP Quiet Output Dynamic Peak VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V
CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6
VOLV Quiet Output Dynamic Valley VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V
CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6
Symbol Parameter Conditions Typical Units
CIN Input Capacitance VCC = Open, VI = 0V or VCC 7pF
CI/O Input/Output Capacitan ce VCC = 3.3V, VI = 0V or VCC 8pF
CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF
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74LCX16543
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL in cludes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay. Pulse Width and trec Waveforms
3-STATE Output Low Enable and
Disable Times for Logic
3-STATE Output High Enable and
Disable Ti mes for Logic
Setup Time, Hold Time and Recovery Time for Lo gic
trise and tfall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
Test Switch
tPLH, tPHL Open
tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH,tPHZ GND
Symbol VCC
3.3V ± 0.3V 2.7V 2.5V ± 0.2V
Vmi 1.5V 1.5V VCC/2
Vmo 1.5V 1.5V VCC/2
VxVOL + 0.3V VOL + 0.3V VOL + 0.15V
VyVOH 0.3V VOH 0.3V VOH 0.15V
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74LCX16543
Schematic Diagram Generic for LCX Family
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74LCX16543
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Packag e Num b er MS56A
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74LCX16543 Low Voltage 16-Bit Regist ered Transceiver with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 6.1mm Wide
Package Number MTD56
Fairchild does not assume an y respon sibility for use of any circuitry described, no circuit pat ent licenses ar e implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the l abe ling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A crit ical componen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife s upport
device or system, or to affect its safety or effectiveness.
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