Datasheet
R01DS0216EJ0110 Rev.1.10 Page 1 of 131
Mar 31, 2016
RX113 Group
Renesas MCUs
Features
■ 32-bit RX CPU core
32 MHz maximum operating frequency
Capable of 50 DMIPS when operating at 32 MHz
Accumulator handles 64-bit results (for a single in struction) from 32-
bit × 32-bit operations
Multiplication and division unit handles 32-bit × 32-bit ope rations
(multiplication instructions take one CPU clock cycle)
Fast interrupt
CISC Harvard architecture with five-stage pipeline
Variable-length instruction format, ultra-compact code
On-chip debugging circuit
■ Low power consumption functions
Operation from a single 1.8 to 3.6 V supply
Three low power consumption modes
Low power timer (LPT) that operates during the software standby
state
Supply current
High-speed operating mode: 0.11 mA/MHz
Software standby mode: 0.44 μA
Recovery time from software standby mode: 4.8 μs
■ On-chip flash memory for code, no wait states
Operation at 32 MHz, re ad cycle of 31.25 ns
No wait states for read ing at full CPU speed
128 to 512 Kbyte capacities
Programmable at 1.8 V
For instruct i ons and operands
■ On-chip data flash memory
8 Kbytes
1,000,000 Erase/Write cycles (typ.)
BGO (Background Operation)
■ On-chip SRAM, no wait states
32 and 64 Kbyte capaci t ie s
■ Data transfer controller (DTC)
Four transfer modes
Transfer can be set for each interrupt source.
■ Event link controller (ELC)
Module operati on can be initiated by event signals without going
through in te rrupts.
Link operation between modules is possible while the CPU is
sleeping.
■ Reset and power supply voltage management
Six types incl uding Power-On Reset (POR)
Low voltage detection (LVD) with voltage settings
■ Clock funct ions
External clock input frequency: Up to 20 MHz
Main clock oscillator frequency: 1 to 20 MHz
Sub-clo ck oscillator frequency: 32.768 kHz
PLL circuit input: 4 to 8 MHz
Low-speed on-chip oscillator: 4 MHz
High-speed on-chip oscillator: 32 MHz ±1% (20 to 85°C)
USB-dedicated PLL circuit: 6 and 8 MHz
IWDT-dedicated on-chip oscillator: 15 kHz
Generate a dedicated 32.768-kHz clock for the RTC
On-chip clock frequency accuracy measurement circuit (CAC)
■ Realtime clock (RTC)
30-second, leap year, and erro r adj u st ment functio ns
Calendar count mode or binary count mode selectable
Capable of initiating exit from software standby mode
■ Independent watchdog timer (IWDT)
15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
■ On-chip functions for IEC 60730 compliance
Clock frequency accuracy measurement circuit, IWDT, functions to
assist in RAM testing, etc.
■ Up to 12 channels for communication
USB: USB 2.0 host/function/On-The-Go (OTG) (one channel), full-
speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and
BC (Battery Charger) supported
SCI: Asynchronous mode, clock synchronous mode, smart card
interface (up to eight channels)
IrDA interface (one channel, in cooperation with SCI5)
I2C bus interface: Transfer at up to 400 kbps, capable of SMBus
operation (one channel)
RSPI: Up to 16 Mbps (one chan nel )
Serial sound interface (SSI) (one channel)
■ Up to 14 extended-function timers
16-bit MTU: Input capture/output compare, complementary PWM
output, phase counting mode
(six channels)
8-bit TMR (four channels)
16-bit CMT (four channels)
■ LCD controller/driver
Segment signal output × common signal output:
40 × 4, 36 × 8
On-chip voltage boost circuit, contrast adjustment, and 5-V panel
supported
Blinking function
■ 12-bit A/D conv ert er
Up to 17 channels
1.0 μs minimum conversion speed
Double trigger (data duplication) functio n for motor control
■ 12-bit D/A conv ert er
Two channels
■ Comparator B
Two channels
■ Capacitive touch sensing unit (CTSU)
Detection p i ns: 12 channels (for 100 p i ns only)
High-sensitive electrostatic capacitance detection using
self-capac itance and mutual capacitance methods
On-chip noise canceller that enables hig h tolerance to disturbance
noise
Also supports a mutu al capacitance method that allows touch
channels to be increased with low pin counts
■ Temperature sensor
■ General I/O ports
5-V tolerant, open drain, input pull-up
■ Multi-function pin controller (MPC)
Multiple I/O pins can be selected for peripheral f unctions.
■ Unique ID
32-byte ID code for the MCU
■ Operating temperature range
40 to 85C
40 to 105°C
PLQP0100KB-A 14 × 14 mm, 0.5 mm pitch
PLQP0064KB-A 10 × 10 mm, 0.5 mm pitch
PTLG0100JA-A 7 × 7 mm, 0.65 mm pitch
32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory,
USB 2.0 full-speed host/function/OTG, up to 12 comms channels, serial sound interface,
LCD controller/driver, capacitive touch sensing unit, 12-bit A/D, 12-bit D/A, RT C
R01DS0216EJ0110
Rev.1.10
Mar 31, 2016
R01DS0216EJ0110 Rev.1.10 Page 2 of 131
Mar 31, 2016
RX113 Group 1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specif ications, and Tabl e 1.2 gives a comparison of the functions of the products in different
packages.
Table 1.1 is for products with the greatest number of functions, so the number of periph eral m odul es and channels will
differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1 Outline of Specifications (1/3)
Classification Module/Function Description
CPU CPU Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Lit tle endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit
On-chip divider: 32-bit ÷ 32-bit → 32 bits
Barrel shifter: 32 bits
Memory ROM Capacity: 128 K /256 K /384 K /512 Kbytes
32 MHz, no-wait memory access
Programming/erasing method:
Serial programming (asyn ch r onous serial communication/USB communication), self-progra mming
RAM Capacity: 32 K /64 Kbytes
32 MHz, no-wait memory access
E2 DataFlash Capacity: 8 Kbytes
Number of erase/write cycles: 1,000,000 (typ)
MCU operating mode Single-chip mode
Clock Clock generation circuit Main clock oscillator, sub-clock oscillator, low-speed on- chip o scillato r, high -speed on- chip o scillato r,
PLL frequency synthesizer, USB-dedicated PLL freq uency synthesizer, and IWDT-dedicated on -chip
oscillator
Oscillation stop detection: Available
Clock frequency accuracy measurement circuit (CAC)
Independent settings for the system clo ck (ICLK), periphe ral module clock (PCLK), and FlashI F clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the PCLK: 32 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16 , 32,
64).
Resets RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
Voltage detection Voltage detection circuit
(LVDAa) When the voltage on VCC falls below the voltage detecti on level, a n internal re set or interna l interrupt
is generated.
Voltage detection circuit 1 is capable of selecting the detection voltage from 10 level s
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Low power
consumption Low power consumption
functions Module stop function
Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Function for lower operating
power consumption Operating power control modes
High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt Interrupt controller (ICUb) Interrupt vectors: 120
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 4 (NMI pin, volt age monitoring 1 interrupt, voltage monitoring 2 interrupt,
and IWDT interrupt)
16 levels specifiable for the order of priority
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RX113 Group 1. Overview
DMA Data transfer controller
(DTCa) Transfer modes: Normal transfer, repeat transfer, and bl ock transfer
Activation sources: Interrupts
Chain transfer function
I/O ports General I/O ports 100-pin /64-pin
I/O: 82/46
Input: 2/2
Pull-up resistors: 69/38
Open-drain outputs: 61/34
5-V tolerance: 4/4
Event link controller (ELC) Event signals of 44 types can be directly connected to the module
Operations of timer modules are selectable at event input
Capable of event link operation for port B
Multi-function pin controller ( MPC) Capable of selecting the input/output function from multiple pins
Timers Multi-function timer pulse
unit 2 (MTU2a) (16 bits × 6 channels) × 1 unit
Time bases for the six 16-bit ti mer channels can be provided via up to 16 pulse-input/ output lines and
three pulse-input lines
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
Input capture function
21 output compare/input captu re registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Capable of generating conversion sta r t triggers for the A/D converter
Port output enable 2
(POE2a) Controls the high-impedance state of the MTU’s waveform output pins
Compare match timer
(CMT) (16 bits × 2 channels) × 2 units
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Independent watchdog
timer (IWDTa) 14 bits × 1 channel
Count clock: Dedicated low-speed on-chi p oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
Realtime clock (RTCA) Clock source: Sub-clock
Calendar count mode or binary count mode selectable
Interrupts: Alarm interru pt, periodic interrupt, and carry interrupt
Low power timer (L PT) 16 bits × 1 channel
Clock source: Sub-clock, Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 2, 4, 8, 16, or 32
8-bit timer (TMR) (8 bits × 2 channels) × 2 units
Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK /64, PCLK/1024, and PCLK/8192)
and an external clock can be selected
Pulse output and PWM outp ut with any duty cycle are available
Two channels can be cascaded and used as a 16-bit timer
Communication
functions Serial communications
interfaces (SCIe, SCIf) 8 channels (channel 0, 1, 2, 5, 6, 8, and 9: SCIe, channel 12: SCIf)
Serial communications modes: Asynchronous, clock synchronous, and smart card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock ca n be input from MTU2 timers
Simple I2C
Simple SPI
Master/slave mode supported (SCIf only)
Start frame and information frame are included (SCIf only)
Start-bit detection in asynchronous mode: Low level or falling edge is selectable
IrDA interface (IRDA) 1 channel (SCI5 used)
Supports encoding/decoding of waveforms conforming to IrDA standard 1.0
I2C bus inter face (RIIC ) 1 channel
Communications formats:
I2C bus format/SMBus format
Master mode or slave mode selectable
Supports fa st m o de
Table 1.1 Outline of Specifications (2/3)
Classification Module/Function Description
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RX113 Group 1. Overview
Communication
functions
Serial peripheral interface
(RSPI) 1 channel
Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-
synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or
32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or receiv ed in a single transfer operation (with each frame
having up to 32 bits)
Double buffers for both transmission and reception
USB 2.0 host/function
module (USBc) USB Device Controller (UDC) and transceiver for USB 2.0 are incorporated.
Host/function module: 1 port
Compliant with USB version 2.0
Transfer speed: Full-speed (12 Mbps), low-speed (1.5 Mbps)
OTG (ON-The-Go) is supported.
Isochronous transfer is supported.
BC (Battery Charger) is supported.
Serial Sound Interface (SSI) 1 channel
Capable of duplex communications
Various serial audio fo rmats supported
Master/slave function supported
Programmable word clock or bit clock generation function
8/16/18/20/22/24/32-bit data formats suppor ted
On-chip 8-stage FIFO for transmission/reception
Supports WS continue mode in which the SSIWS signal is not stopped.
LCD controller/driver (LCDC) Internal volta ge boosting method , capacitor split method, a nd external resist ance division met hod are
switchable.
Segment signal output × common signal output : 40 × 4, 36 × 8
12-bit A/D converter (S12ADb) 1 unit (1 unit × 17 channels)
12-bit resolution
Minimum conversion time: 1.0 µs per channel when the ADCLK is operati ng at 32 MHz
Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
Double trigger mode (dupli cation of A/D conversion data)
A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), an external trigger signal, or ELC
Temperature sensor (TEMPSA) 1 channel
The voltage of the temperature is conve r ted into a digital value by the 12-bit A/D converter.
12-bit D/A converter (R12DAA) 2 channels
12-bit resolution
Output voltage: 0.35 to AVCC - 0.47 V
CRC calculator (CRC) CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1
Generation of CRC codes for use with LSB-first or MSB-first communicat i ons is selectable.
Comparator B (CMPBa) 2 channels
Function to compare the reference voltage and the analog input voltage
Window comparator operation or sta ndard comparator operation is selectable
Capacitive touch sensing unit (CTSU) Detection pin: 12 channels (for 100 pins only)
Data operation circuit (DOC) Comparison, addition, and subtraction of 16-bit data
Unique ID 32-byte ID code for the MCU
Power supply voltages/ Operating frequencies VCC = 1.8 to 2.4 V: 8 MHz, VCC = 2.4 to 2.7 V: 16 MHz, VCC = 2.7 to 3.6 V: 32 MHz
Supply current 3.6 mA at 32 MHz (typ.)
Operating temperature range D version: 40 to +85°C, G version: 40 to +105°C
Packages 100-pin LFQFP (PLQP0100KB- A) 14 × 14 mm, 0. 50 mm pi tch
100-pin TFLGA (PTLG0100JA-A) 7 × 7 mm, 0.65 mm pitch
64-pin LFQFP (PLQP0064KB-A ) 10 × 10 mm, 0.5 0 mm pitc h
On-chip debugging system E1 emulator (FINE interface)
Table 1.1 Outline of Specifications (3/3)
Classification Module/Function Description
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RX113 Group 1. Overview
Table 1.2 Comparison of Functions for Different Packages
Module/Functions
RX113 Group
100 Pins 64 Pins
Interrupts External interrupts NMI, IRQ0 to IRQ7
DMA Data transfer controller Supported
Timers Multi-function timer pulse unit 2 6 channels (MTU0 to MTU5)
Port output enable 2 Supported
Compare match timer 2 channels × 2 units
Realtime clock Supported
Low power timer 1 channel
8-bit timer 2 channels × 2 units
Independent watchdog timer Supported
Communication
functions Serial communications interfaces (SCIe)
[simple I2C, simple SPI] 7 channels
(SCI0, 1, 2, 5, 6, 8, 9) 5 channels
(SCI1, 5, 6, 8, 9)
IrDA interface 1 channel (SCI5)
Serial communications interface (SCIf)
[simple I2C, simple SPI] 1 channel (SCI12)
I2C bus interface 1 channel
Serial peripheral interface 1 channel
USB 2.0 host/function module (USBc) 1 channel
Serial sound interface 1 channel
12-bit A/D converter
(including high-precision channels) 17 channels
(9 channels) 11 channels
(3 channels)
Temperature sensor Supported
Comparator B 2 channels
12-bit D/A converter 2 channels
CRC calculator Supported
Event link controller Supported
Capacitive touch sensing unit 12 channels Not supported
LCD 40 SEG × 4 COM
36 SEG × 8 COM 20 SEG × 4 COM
16 SEG × 8 COM
Packages 100-pin LFQFP
100-pin TFLGA 64-pin LFQFP
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RX113 Group 1. Overview
1.2 List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no., memory capacity, and package
type.
Table 1.3 List of Products
Group Part No. Orderable Part No. Package ROM
Capacity RAM
Capacity E2
DataFlash
Maximum
Operating
Frequency Operating
Temperature
RX113 R5F51138ADFP R5F51138ADFP#3A PLQP0100KB-A
512 Kbytes
64 Kbytes
8 Kbytes 32MHz
40 to +85°C
R5F51138ADFM R5F51138ADFM#3A PLQP0064KB-A
R5F51138ADLJ R5F51138ADLJ#2A PTLG0100JA-A
R5F51137ADFP R5F51137ADFP#3A PLQP0100KB-A
384 KbytesR5F51137ADFM R5F51137ADFM#3A PLQP0064KB-A
R5F51137ADLJ R5F51137ADLJ#2A PTLG0100JA-A
R5F51136ADFP R5F51136ADFP#3A PLQP0100KB-A
256 Kbytes
32 Kbytes
R5F51136ADFM R5F51136ADFM#3A PLQP0064KB-A
R5F51136ADLJ R5F51136ADLJ#2A PTLG0100JA-A
R5F51135ADFP R5F51135ADFP#3A PLQP0100KB-A
128 KbytesR5F51135ADFM R5F51135ADFM#3A PLQP0064KB-A
R5F51135ADLJ R5F51135ADLJ#2A PTLG0100JA-A
R5F51138AGFP R5F51138AGFP#3A PLQP0100KB-A 512 Kbytes
64 Kbytes
40 to
+105°C
R5F51138AGFM R5F51138AGFM#3A PLQP0064KB-A
R5F51137AGFP R5F51137AGFP#3A PLQP0100KB-A 384 Kbytes
R5F51137AGFM R5F51137AGFM#3A PLQP0064KB-A
R5F51136AGFP R5F51136AGFP#3A PLQP0100KB-A 256 Kbytes
32 Kbytes
R5F51136AGFM R5F51136AGFM#3A PLQP0064KB-A
R5F51135AGFP R5F51135AGFP#3A PLQP0100KB-A 128 Kbytes
R5F51135AGFM R5F51135AGFM#3A PLQP0064KB-A
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RX113 Group 1. Overview
Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type
Type of memory
F: Flash memory version
Package type, number of pins, and pin pitch
FP: LFQFP/100/0.50
LJ: TFLGA/100/0.65
FM: LFQFP/64/0.50
ROM, RAM, and E2 DataFlash capacity
8: 512 Kbytes/64 Kbytes/8 Kbytes
7: 384 Kbytes/64 Kbytes/8 Kbytes
6: 256 Kbytes/32 Kbytes/8 Kbytes
5: 128 Kbytes/32 Kbytes/8 Kbytes
Group name
13: RX113 Group
Renesas MCU
Renesas semiconductor product
Series name
RX100 Series
D: Operating temperature (-40°C to +85°C)
G: Operating temperature (-4 0°C to +105°C)
R 5 F 5 1 D F MA831#3A
Packing, Terminal material (Pb-free)
#2: Tray/SnCu and others
#3: Tray/Sn (Tin) only
Production identification code
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Mar 31, 2016
RX113 Group 1. Overview
1.3 Block Diagram
Figure 1.2 shows a block diagram.
Figure 1.2 Block Diagram
ICUb: Interrupt controller
DTCa: Data transfer controller
TMR: 8-bit timer
IWDTa: Independent watchdog timer
ELC: Event link controller
CRC: CRC (cyclic redundancy check) calculator
SCIe/SCIf: Serial communications interface
RSPI: Serial peripheral interface
RIIC: I2C bus interface
MTU2a: Multi-function timer pulse unit 2
POE2a: Port output enable 2
SSI: Serial sound interface
CMT: Compare match timer
RTCc: Realtime clock
DOC: Data operation circuit
CAC: C lock frequency accuracy measurement circuit
CTSU: Capacitive touch sensing unit
Operand bus
Instruction bus
Internal main bus 1
Clock
generation
circuit
RX CPU
RAM
ROM
Port 0
Port 1
Port 3
Port 4
12-bit D/A converter × 2 channels
RIIC × 1 channel
DOC
SCIe × 7 channels
(including IrDA × 1 channel)
E2 DataFl ash
CRC
ELC
RTCc
MTU2a × 6 channels
12-bit A/D convert er × 17 channels
CMT × 2 channels (unit 0)
RSPI × 1 channel
Internal main bus 2
DTCa
ICUb
CAC
SCIf × 1 channel
Port 5
Port A
Port B
Port C
Port E
Port H
POE2a
IWDTa
SSI Port 2
Temperature sensor
Port J
USB 2.0 host/function module
Comparator B
LCD controller/driver
CTSU
Internal peripheral buses 1 to 6
CMT × 2 channels (unit 1)
TMR × 2 channels (unit 0)
TMR × 2 channels (unit 1)
Port 9
Port D
Port F
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RX113 Group 1. Overview
1.4 Pin Functions
Table 1.4 lists the pin functions.
Table 1.4 Pin Functions (1/4)
Classifications Pin Name I/O Description
Power supply VCC Input Power supply pin. Connect it to the system power supply.
VCL — Connect this pin to the VSS pin via the 4.7 μF smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the pin.
VSS Input Ground pin. Connect it to the system power supply (0 V).
VCC_USB Input Power supply pin for USB. Connect this pin to VCC.
VSS_USB Input Ground pin for USB. Connect this pin to VSS.
Analog power
supply AVCC0 Input Analog voltage supply pin for the 12-bit A/D converter and D/A converter.
Connect this pin to VCC when not using the 12-bit A/D converter and D/A
converter.
A VSS0 Input Analog ground pin for the 12-bit A/D converter and D/A converter. Connect
this pin to VSS when not using the 12-bit A/D converter and D/A converter.
VREFH0 Input Analog reference voltage supply pin for the 12-bit A/D converter.
VREFL0 Input Analog reference ground pin for the 12-bit A/D converter.
VREFH Input Analog reference voltage supply pin for the 12-bit D/A converter.
VREFL Input Analog reference ground pin for the 12-bit D/A converter.
Clock XTAL Output/
Input *1Pins for connecting a crystal. An external clock can be input through the
XTAL pin.
EXTAL Input
XCIN Input Input/output pins for the sub-clock oscillator. Connect a crystal between
XCIN and XCOUT.
XCOUT Output
CLKOUT Output Clock output pin.
Operating mode
control MD Input Pin for setting the operating mode. The signal levels on this pin must not
be changed during operation.
UB# Input Pin used for boot mode (USB interface).
UPSEL Input Pin used for boot mode (USB interface).
System control RES# Input Reset pin. This MCU enters the reset state when this signal goes low.
CAC CACREF Input Input pin for the clock frequency accuracy measurement circuit.
On-chip
emulator FINED I/O FINE interface pin.
LVD CMPA2 Input Detection target voltage pin for voltage detection 2.
Interrupts NMI Input Non-maskable interrupt request pin.
IRQ0 to IRQ7 Input Interrupt request pins.
Multi-function
timer pulse unit 2 MTIOC0A, MTIOC0B
MTIOC0C, MTIOC0D I/O The TGRA0 to TGRD0 input capture input/output compare output/PWM
output pins.
MTIOC1A, MTIOC1B I/O The TGRA1 and TGRB1 input capture input/output compare output/PWM
output pins.
MTIOC2A, MTIOC2B I/O The TGRA2 and TGRB2 input capture input/output compare output/PWM
output pins.
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D I/O The TGRA3 to TGRD3 input capture input/output compare output/PWM
output pins.
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D I/O The TGRA4 to TGRD4 input capture input/output compare output/PWM
output pins.
MTIC5U, MTIC5V, MTIC5W Input The TGRU5, TGRV5, and TGRW5 input capture input/external pulse input
pins.
MTCLKA, MTCLKB,
MTCLKC, MTCLKD Input Input pins for the external clock.
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RX113 Group 1. Overview
Port output
enable 2 POE0# to POE3#, POE8# Input Input pins for request signals to place the MTU pins in the high impedance
state.
Realtime clock RTCOUT Output Output pin for the 1-Hz/64-Hz clock.
8-bit timer TMO0 to TMO3 Output Compare match output pins.
TMCI0 to TMCI3 Input Input pins for the external clock to be input to the counter.
TMRI0 to TMRI3 Input Counter reset input pins.
Serial
communications
interface (SCIe)
Asynchronous mode/clock synchronous mode
SCK0, SCK1, SCK2, SCK5,
SCK6, SCK8, SCK9 I/O Input/output pins for the clock.
RXD0, RXD1, RXD2, RXD5,
RXD6, RXD8, RXD9 Input Input pins for received data.
TXD0, TXD1, TXD2, TXD5,
TXD6, TXD8, TXD9 Output Output pins for transmitted data.
CTS0#, CTS1#, CTS2#,
CTS5#, CTS6#, CTS8#,
CTS9#
Input Input pins for controlling the start of transmission and reception.
RTS0#, RTS1#, RTS2#,
RTS5#, RTS6#, RTS8#,
RTS9#
Output Output pins for controlling the start of transmission and reception.
Simple I2C mode
SSCL0, SSCL1, SSCL2,
SSCL5, SSCL6, SSCL8,
SSCL9
I/O Input/output pins for the I2C clock.
SSDA0, SSDA1, SSDA2,
SSDA5, SSDA6, SSDA8,
SSDA9
I/O Input/output pins for the I2C data.
Simple SPI mode
SCK0, SCK1, SCK2, SCK5,
SCK6, SCK8, SCK9 I/O Input/output pins for the clock.
SMISO0, SMISO1, SMISO2,
SMISO5, SMISO6, SMISO8,
SMISO9
I/O Input/output pins for slave transmit data.
SMOSI0, SMOSI1, SMOSI2,
SMOSI5, SMOSI6, SMOSI8,
SMOSI9
I/O Input/output pins for master transmit data.
SS0#, SS1#, SS2#, SS5#,
SS6#, SS8#, SS9# Input Chip-select input pins.
IrDA interface IRTXD5 Output Data output pin in the IrDA format.
IRRXD5 Input Data input pin in the IrDA format.
Table 1.4 Pin Functions (2/4)
Classifications Pin Name I/O Description
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RX113 Group 1. Overview
Serial
communications
interface (SCIf)
Asynchronous mode/clock synchronous mode
SCK12 I/O Input/output pin for the clock.
RXD12 Input Input pin for receiving data.
TXD12 Output Output pin for transmitting data.
CTS12# Input Input pin for controlling the start of transmission and reception.
RTS12# Output Output pin for controlling the start of transmission and reception.
Simple I2C mode
SSCL12 I/O Input/output pin for the I2C clock.
SSDA12 I/O Input/output pin for the I2C data.
Simple SPI mode
SCK12 I/O Input/output pin for the clock.
SMISO12 I/O Input/output pin for slave transmit data.
SMOSI12 I/O Input/output pin for master transmit data.
SS12# Input Chip-select input pin.
Extended serial mode
RXDX12 Input Input pin for data reception by SCIf.
TXDX12 Output Output pin for data transmission by SCIf.
SIOX12 I/O Input/output pin for data reception or transmission by SCIf.
I2C bus interface SCL0 I/O Input/output pin for I2C bus interface clocks. Bus can be directly driven by
the N-channel open drain output.
SDA0 I/O Input/output pin for I2C bus interface data. Bus can be directly driven by
the N-channel open drain output.
Serial peripheral
interface RSPCKA I/O Input/output pin for the RSPI clock.
MOSIA I/O Input/output pin for transmitting data from the RSPI master.
MISOA I/O Input/output pin for transmitting data from the RSPI slave.
SSLA0 I/O Input/output pin to select the slave for the RSPI.
SSLA1 to SSLA3 Output Output pins to select the slave for the RSPI.
Serial sound
interface SSISCK0 I/O SSI serial bit clock pin.
SSIWS I/O Word selection pin.
SSITXD0 Output Serial data output pin.
SSIRXD0 Input Serial data input pin.
AUDIO_MCLK Input Master clock pin for audio.
USB 2.0 host/
function module USB0_DP I/O D+ I/O pin of the USB on-chip transceiver.
USB0_DM I/O D- I/O pin of the USB on-chip transceiver.
USB0_VBUS Input USB cable connection monitor pin.
USB0_EXICEN Output Low-power control signal for the OTG chip.
USB0_VBUSEN Output VBUS (5 V) supply enable signal for the OTG chip.
USB0_OVRCURA,
USB0_OVRCURB Input External overcurrent detection pins.
USB0_ID Input Mini-AB connector ID input pin during operation in OTG mode.
12-bit A/D
converter AN000 to AN015, AN021 Input Input pins for the analog signals to be processed by the A/D converter.
ADTRG0# Input Input pin for the external trigger signals that start the A/D conversion.
12-bit D/A
converter DA0, DA1 Output Output pins for the analog signals to be processed by the D/A converter.
Table 1.4 Pin Functions (3/4)
Classifications Pin Name I/O Description
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RX113 Group 1. Overview
Note 1. For external clock input.
Comparator B CMPB0 Input Input pin for the analog signal to be processed by comparator B0.
CVREFB0 Input Analog reference voltage supply pin for comparator B0.
CMPB1 Input Input pin for the analog signal to be processed by comparator B1.
CVREFB1 Input Analog reference voltage supply pin for comparator B1.
CMPOB0 Output Output pin for comparator B0.
CMPOB1 Output Output pin for comparator B1.
LCD VL1, VL2, VL3, VL4 I/O Voltage pin for driving the LCD.
CAPH, CAPL I/O Capacitor connection pin for the LCD controller/driver .
COM0 to COM7 Output Common signal output pins for the LCD controller/driver.
SEG00 to SEG39 Output Segment signal output pins for the LCD controller/driver.
CTSU TS0 to TS11 Input Capacitive touch detection pins (touch pins).
TSCAP I/O Secondary power supply pin for the touch driver.
I/O ports P02, P04, P07 I/O 3-bit input/output pins.
P10 to P17 I/O 8-bit input/output pins.
P20 to P27 I/O 8-bit input/output pins.
P30 to P32, P35 I/O 4-bit input/output pins (P35 input pin).
P40 to P44, P46 I/O 6-bit input/output pins.
P50 to P56 I/O 7-bit input/output pins.
P90 to P92 I/O 3-bit input/output pins.
PA0 to PA7 I/O 8-bit input/output pins.
PB0 to PB7 I/O 8-bit input/output pins.
PC0 to PC7 I/O 8-bit input/output pins.
PD0 to PD4 I/O 5-bit input/output pins.
PE0 to PE7 I/O 8-bit input/output pins.
PF6, PF7 I/O 2-bit input/output pins.
PH7 Input 1-bit input pin.
PJ0, PJ2, PJ3, PJ6, PJ7 I/O 5-bit input/output pins.
Table 1.4 Pin Functions (4/4)
Classifications Pin Name I/O Description
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RX113 Group 1. Overview
1.5 Pin Assignments
Figure 1.3 to Figure 1. 5 show the pin assignments. Table 1.5 to Table 1.7 show the lists of pins and pin functions.
Figure 1.3 Pin Assignments of the 100-Pin LFQFP
PE2
PE1
PE0
PE7
PE6
PD4
PD3
PD2
PD1
PD0
P46
P90
P44
P43
PE3
PE4
PE5
PF6
PF7
PA0
PA1
PA2
PA3
PA4
PA5
PA7
PA6
VSS
PB0
VCC
PC2
PC3
PC4
PC5
PC6
PC7
P55
P50
P51
P52
P53
P56
P54
P10
P11
P12
P04
P26
P27
P30
P31
MD
RES#
XCOUT
RX113 Group
PLQP0100KB-A
(100-pin LFQFP)
(Top view)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
81
82
78
76
77
79
80
83
84
85
86
87
88
90
91
89
17
18
19
20
21
22
23
24
25
P32
PH7/XCIN
P35/NMI
XTAL
EXTAL
VCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
59
58
57
56
55
54
53
52
51
P42/VREFL
P41/VREFH
PJ7/VREFL0
PJ6/VREFH0
AVSS0
AVCC0
PJ2
P13
VSS_USB
USB0_DP
USB0_DM
VCC_USB
P14
P15
P16
P17
34
33
32
31
30
29
28
27
26
92
93
94
95
96
97
99
100
98
VCC
VSS
P22
P23
P21
P20
PJ3
P02
P25
P24
PJ0
P07
P40
P92
P91
Note: This figure indicates the power supply pins and I/ O port s.
For the pin configuration, see the table “List of Pins and Pin Functions (100-Pin LFQFP)”.
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Mar 31, 2016
RX113 Group 1. Overview
Figure 1.4 Pin Assignments of the 100-Pin TFLGA
P02
RX113 Group
PTLG0100JA-A
(100-pin TFLGA)
(Upper perspective view)
P25 PJ3 P22 P30/
CAPH XCOUT XCIN/
PH7 XTAL VCL VSS
P07 P04 P24 P23 P31/
CAPL P35/
NMI P14 EXTAL P17 VCC
AVCC0 PJ2 PJ6/
VREFH0 P21 P26 RES# P12 P15 P32 P16
AVSS0 PJ7/
VREFL0 P41/
VREFH PJ0 P20 P27 MD/
FINED P13 VCC_
USB USB0_
DM
P44 P90 P42/
VREFL P43 P40 P56 P10 P11 VSS_
USB USB0_
DP
P92 PD0 P91 P46 PA2 PB4 P50 P51 P52 P53
PD3 PD4 PD1 PF6 PA4 PA7 PB5 PC0 P55 P54
PE6 PE2 PD2 PF7 PA5 PB0 PB2 PC1 PC7 PC6
PB6PE7 PE1 PE5 PA1 PA3 PA6 PB1 PC4 PC5
PE0 PE3 PE4 PA0 VSS VCC PB3 PB7 PC2 PC3
ABCDEFGHJK
ABCDEFGHJK
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
Note: This figure indicates the power supply pins and I/O ports.
For the pin c onfiguration, see the table “List of Pins and Pin Functions (100-Pin TFLGA)”.
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RX113 Group 1. Overview
Figure 1.5 Pin Assignments of the 64-Pin LFQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
54
55
51
49
50
52
53
56
57
58
59
60
61
63
64
62
RX113 Group
PLQP0064KB-A
(64-pin LFQFP)
(Top view)
PE2
PE1
PE0
PE7
PE6
PD2
PD1
PD0
P42
P41
PJ7/VREFL0
P40
PJ6/VREFH0
AVSS0
AVCC0
PJ2
PE3
PE4
PE5
PA0
PA1
PA3
PA4
PA6
VSS
PB0
VCC
PB1
PB3
PB5
PB6/PC0
PB7/PC1
PC2
PC3
PC4
PC5
PC6
PC7
P54
P55
VSS_USB
USB0_DP
USB0_DM
VCC_USB
P14
P15
P16
P17
PJ0
P27
P26
P30
P31
MD
RES#
XCOUT
PH7/XCIN
P35/NMI
XTAL
EXTAL
VCL
VSS
VCC
P32
Note: This figure indicates the power supply pins and I/O ports.
For the pin configuration, see the table “List of Pins and Pin Functions (64-Pin LFQFP)”.
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RX113 Group 1. Overview
Table 1.5 List of Pins and Pin Functions (100-Pin LFQFP) (1/3)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC, TMR) Communication
(SCIe, SCIf, RSPI, RIIC, USB, SSI) LCD,
Touch Others
1 P04 MTIOC0A/POE2#/TMCI3 SCK6 TS1
2PJ0 DA0
3 P02 MTIOC0D/POE3#/TMRI3 RXD6/SMISO6/SSCL6 TS2
4 PJ3 MTIOC3C CTS6#/RTS6#/SS6# TS3
5 P25 MTIOC4C/MTCLKB TS4 ADTRG0#
6 P24 MTIOC4A/MTCLKA/
TMRI1 TS5
7 P23 MTIOC3D/MTCLKD CTS0#/RTS0#/SS0# TS6
8 P22 MTIOC3B/MTCLKC/
TMO0 SCK0 TS7
9 P21 MTIOC1B/TMCI0 RXD0/SMISO0/SSCL0 TS8
10 P20 MTIOC1A/TMRI0 TXD0/SMOSI0/SSDA0 TS9
11 P27 MTIOC2B/TMCI3 SCK12/SCK1/RXD6/SMISO6/
SSCL6 TS10 IRQ3/ADTRG0#/
CACREF/
CMPA2
12 P26 MTIOC2A/TMO1 TXD1/SMOSI1/SSDA1/
USB0_VBUSEN/TXD6/SMOSI6/
SSDA6
TSCAP
13 P30 MTIOC4B/POE8#/TMRI3 RXD1/SMISO1/SSCL1 CAPH IRQ0
14 P31 MTIOC4D/TMCI2 CTS1#/RTS1#/SS1# CAPL IRQ1
15 MD FINED
16 RES#
17 XCOUT
18 XCIN PH7
19 UPSEL P35 NMI
20 XTAL
21 EXTAL
22 VCL
23 VSS
24 VDD
25 P32 MTIOC0C/RTCOUT/
TMO3 TXD6/SMOSI6/SSDA6/CTS6#/
RTS6#/SS6# TS11 IRQ2
26 P17 MTIOC0C/MTIOC3A/
MTIOC3B/POE8#/TMO1 SCK1/MISOA/SDA0/RXD12/
RXDX12/SMISO12/SSCL12 IRQ7
27 P16 MTIOC3C/MTIOC3D/
RTCOUT/TMO2 TXD1/SMOSI1/SSDA1/MOSIA/
SCL0/USB0_VBUS/
USB0_VBUSEN/USB0_OVRCURB
IRQ6/ADTRG0#
28 P15 MTIOC0B/MTCLKB/
TMCI2 RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT/
CACREF
29 UB# P14 MTIOC0A/MTIOC3A/
MTCLKA/TMRI2 CTS1#/RTS1#/SS1#/SSLA0/
TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12/USB0_OVRCURA
IRQ4
30 VCC_USB
31 USB0_DM
32 USB0_DP
33 VSS_USB
34 P13 MTIOC0B/TMO3 CTS12#/RTS12#/SS12#/CTS0#/
RTS0#/SS0# SEG00 IRQ3
35 P12 TMCI1 SCK12/SCK0 SEG01 IRQ2
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RX113 Group 1. Overview
36 P11 MTIC5U/POE0# RXD12/RXDX12/SMISO12/
SSCL12/ RXD0/SMISO0/SSCL0 SEG02 IRQ7
37 P10 MTIC5V/POE1# TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12/TXD0/SMOSI0/SSDA0 SEG03 IRQ6
38 P56 MTIOC1A/MTIC5W/
POE2# TXD1/SMOSI1/SSDA1 SEG04 IRQ5
39 P53 MTIOC2B SSLA0/CTS2#/RTS2#/SS2# SEG05
40 P52 MISOA/RXD2/SMISO2/SSCL2 SEG06
41 P51 MTIOC4C RSPCKA/SCK2 SEG07
42 P50 MTIOC2A MOSIA/TXD2/SMOSI2/SSDA2 SEG08
43 P55 MTIOC4D/TMO3 VL1
44 P54 MTIOC4B/TMCI1 VL2
45 PC7 MTIOC3A/MTCLKB/
TMO2 TXD1/SMOSI1/SSDA1/MISOA/
TXD8/SMOSI8/SSDA8/
USB0_OVRCURB
VL3 CACREF
46 PC6 MTIOC3C/MTCLKA/
TMCI2 RXD1/SMISO1/SSCL1/MOSIA/
RXD8/SMISO8/SSCL8/
USB0_EXICEN
VL4
47 PC5 MTIOC3B/MTCLKD/
TMRI2 SCK1/RSPCKA/SCK8/USB0_ID COM0
48 PC4 MTIOC3D/MTCLKC/
POE0#/TMCI1 SSLA0/CTS8#/RTS8#/SS8#/SCK5/
USB0_VBUSEN/USB0_VBUS *1COM1 IRQ2/CLKOUT
49 PC3 MTIOC4D TXD5/SMOSI5/SSDA5/IRTXD5 COM2
50 PC2 MTIOC4B RXD5/SMOSI5/SSCL5/IRRXD5/
SSLA3 COM3
51 PC1 MTIOC3A SCK5/SSLA2 SEG09
52 PC0 MTIOC3C CTS5#/RTS5#/SS5#/SSLA1 SEG10
53 PB7 MTIOC3B TXD9/SMOSI9/SSDA9/SSITXD0 SEG11/
COM4
54 PB6 MTIOC3D RXD9/SMISO9/SSCL9/SSIRXD0 SEG12/
COM5
55 PB5 MTIOC1B/MTIOC2A/
POE1#/TMRI1 SCK9/SSISCK0 SEG13/
COM6
56 PB4 CTS9#/RTS9#/SS9# SEG14
57 PB3 MTIOC0A/MTIOC3B/
MTIOC4A/POE3#/TMO0 SCK6/AUDIO_MCLK/
USB0_OVRCURA SEG15/
COM7
58 PB2 CTS6#/RTS6#/SS6# SEG16
59 PB1 MTIOC0C/MTIOC4C/
TMCI0 TXD6/SMOSI6/SSDA6/SSIWS0 SEG17 IRQ4
60 VCC
61 PB0 MTIOC0C/MTIC5W/
RTCOUT SCL0/RSPCKA/RXD6/SMISO6/
SSCL6 IRQ2/ADTRG0#
62 VSS
63 PA6 MTIC5V/MTCLKB/
MTIOC2A/POE2#/TMCI3 CTS5#/RTS5#/SS5#/SDA0/MOSIA/
RXD8/SMISO8/SSCL8 IRQ3
64 PA7 TXD8/SMOSI8/SSDA8 SEG18
65 PA5 SCK8 SEG19
66 PA4 MTIOC2B/MTIC5U/
MTCLKA/TMRI0 TXD5/SMOSI5/SSDA5/IRTXD5/
SSLA0/CTS8#/RTS8#/SS8# SEG20 IRQ5/CVREFB1
67 PA3 MTIOC0D/MTIOC1B/
MTCLKD/POE0# RXD5/SMISO5/SSCL5/IRRXD5/
MISOA SEG21 IRQ6/CMPB1
Table 1.5 List of Pins and Pin Functions (100-Pin LFQFP) (2/3)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC, TMR) Communication
(SCIe, SCIf, RSPI, RIIC, USB, SSI) LCD,
Touch Others
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RX113 Group 1. Overview
Note 1. Not 5 V tolerant.
Note 2. The power source of the I/O buffer for these pins is AVCC0.
68 PA2 RXD5/SMISO5/SSCL5/IRRXD5/
SSLA3 SEG22
69 PA1 MTIOC0B/MTCLKC/
RTCOUT SCK5/SSLA2 SEG23
70 PA0 MTIOC4A SSLA1 SEG24 CACREF
71 PF7 MTIOC3A SEG25
72 PF6 MTIOC3C SEG26
73 PE5 MTIOC2B/MTIOC4C MISOA/TXD9/SMOSI9/SSDA9 SEG27 IRQ5/AN013/
CMPOB1
74 PE4 MTIOC1A/MTIOC3A/
MTIOC4D MOSIA/RXD9/SMISO9/SSCL9/
SSIWS0 SEG28 IRQ4/AN012
75 PE3 MTIOC0A/MTIOC1B/
MTIOC4B/POE8# CTS12#/RTS12#/SS12#/RSPCKA/
SCK9/AUDIO_MCLK SEG29 IRQ3/AN011
76 PE2 MTIOC4A RXD12/RXDX12/SMISO12/
SSCL12/SSIRXD0 SEG30 IRQ7/AN010/
CVREFB0
77 PE1 MTIOC4C TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12/SSITXD0 SEG31 IRQ1/AN009/
CMPB0
78 PE0 MTIOC2A/POE3# SCK12/CTS9#/RTS9#/SS9#/
SSISCK0 SEG32 IRQ0/AN008
79 PE7 SEG33 IRQ7/AN015/
CMPOB0
80 PE6 SEG34 IRQ6/AN014
81 PD4 POE3# SEG35 IRQ4
82 PD3 POE8# SEG36 IRQ3
83 PD2 MTIOC4D SEG37 IRQ2
84 PD1 MTIOC4B SEG38 IRQ1
85 PD0 SEG39 IRQ0
86 P92*2AN021
87 P91*2AN007
88 P46*2AN006
89 P90*2AN005
90 P44*2AN004
91 P43*2AN003
92 VREFL P42*2AN002
93 VREFH P41*2AN001
94 VREFL0 PJ7*2
95 P40*2AN000
96 VREFH0 PJ6*2
97 AVSS0
98 AVCC0
99 P07 TXD6/SMOSI6/SSDA6 TS0 ADTRG0#
100 PJ2 DA1
Table 1.5 List of Pins and Pin Functions (100-Pin LFQFP) (3/3)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC, TMR) Communication
(SCIe, SCIf, RSPI, RIIC, USB, SSI) LCD,
Touch Others
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RX113 Group 1. Overview
Table 1.6 List of Pins and Pin Functions (100-Pin TFLGA) (1/3)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC, TMR) Communication
(SCIe, SCIf, RSPI, RIIC, USB, SSI) LCD,
Touch Others
A1 P02 MTIOC0D/POE3#/TMRI3 RXD6/SMISO6/SSCL6 TS2
A2 P07 TXD6/SMOSI6/SSDA6 TS0 ADTRG0#
A3 AVCC0
A4 AVSS0
A5 P44*2AN004
A6 P92*2AN021
A7 PD3 POE8# SEG36 IRQ3
A8 PE6 SEG34 IRQ6/AN014
A9 PE7 SEG33 IRQ7/AN015/
CMPOB0
A10 PE0 MTIOC2A/POE3# SCK12/CTS9#/RTS9#/SS9#/
SSISCK0 SEG32 IRQ0/AN008
B1 P25 MTIOC4C/MTCLKB TS4 ADTRG0#
B2 P04 MTIOC0A/POE2#/TMCI3 SCK6 TS1
B3 PJ2 DA1
B4 VREFL0 PJ7*2
B5 P90*2AN005
B6 PD0 SEG39 IRQ0
B7 PD4 POE3# SEG35 IRQ4
B8 PE2 MTIOC4A RXD12/RXDX12/SMISO12/
SSCL12/SSIRXD0 SEG30 IRQ7/AN010/
CVREFB0
B9 PE1 MTIOC4C TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12/SSITXD0 SEG31 IRQ1/AN009/
CMPB0
B10 PE3 MTIOC0A/MTIOC1B/
MTIOC4B/POE8# CTS12#/RTS12#/SS12#/RSPCKA/
SCK9/AUDIO_MCLK SEG29 IRQ3/AN011
C1 PJ3 MTIOC3C CTS6#/RTS6#/SS6# TS3
C2 P24 MTIOC4A/MTCLKA/
TMRI1 TS5
C3 VREFH0 PJ6*2
C4 VREFH P41*2AN001
C5 VREFL P42*2AN002
C6 P91*2AN007
C7 PD1 MTIOC4B SEG38 IRQ1
C8 PD2 MTIOC4D SEG37 IRQ2
C9 PE5 MTIOC2B/MTIOC4C MISOA/TXD9/SMOSI9/SSDA9 SEG27 IRQ5/AN013/
CMPOB1
C10 PE4 MTIOC1A/MTIOC3A/
MTIOC4D MOSIA/RXD9/SMISO9/SSCL9/
SSIWS0 SEG28 IRQ4/AN012
D1 P22 MTIOC3B/MTCLKC/
TMO0 SCK0 TS7
D2 P23 MTIOC3D/MTCLKD CTS0#/RTS0#/SS0# TS6
D3 P21 MTIOC1B/TMCI0 RXD0/SMISO0/SSCL0 TS8
D4 PJ0 DA0
D5 P43*2AN003
D6 P46*2AN006
D7 PF6 MTIOC3C SEG26
D8 PF7 MTIOC3A SEG25
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RX113 Group 1. Overview
D9 PA1 MTIOC0B/MTCLKC/
RTCOUT SCK5/SSLA2 SEG23
D10 PA0 MTIOC4A SSLA1 SEG24 CACREF
E1 P30 MTIOC4B/POE8#/TMRI3 RXD1/SMISO1/SSCL1 CAPH IRQ0
E2 P31 MTIOC4D/TMCI2 CTS1#/RTS1#/SS1# CAPL IRQ1
E3 P26 MTIOC2A/TMO1 TXD1/SMOSI1/SSDA1/
USB0_VBUSEN/TXD6/SMOSI6/
SSDA6
TSCAP
E4 P20 MTIOC1A/TMRI0 TXD0/SMOSI0/SSDA0 TS9
E5 P40*2AN000
E6 PA2 RXD5/SMISO5/SSCL5/IRRXD5/
SSLA3 SEG22
E7 PA4 MTIOC2B/MTIC5U/
MTCLKA/TMRI0 TXD5/SMOSI5/SSDA5/IRTXD5/
SSLA0/CTS8#/RTS8#/SS8# SEG20 IRQ5/CVREFB1
E8 PA5 SCK8 SEG19
E9 PA3 MTIOC0D/MTIOC1B/
MTCLKD/POE0# RXD5/SMISO5/SSCL5/IRRXD5/
MISOA SEG21 IRQ6/CMPB1
E10 VSS
F1 XCOUT
F2 UPSEL P35 NMI
F3 RES#
F4 P27 MTIOC2B/TMCI3 SCK12/SCK1/RXD6/SMISO6/
SSCL6 TS10 IRQ3/
ADTRG0#/
CACREF/
CMPA2
F5 P56 MTIOC1A/MTIC5W/
POE2# TXD1/SMOSI1/SSDA1 SEG4 IRQ5
F6 PB4 CTS9#/RTS9#/SS9# SEG14
F7 PA7 TXD8/SMOSI8/SSDA8 SEG18
F8 PB0 MTIOC0C/MTIC5W/
RTCOUT SCL0/RSPCKA/RXD6/SMISO6/
SSCL6 IRQ2/ADTRG0#
F9 PA6 MTIC5V/MTCLKB/
MTIOC2A/POE2#/TMCI3 CTS5#/RTS5#/SS5#/SDA0/MOSIA/
RXD8/SMISO8/SSCL8 IRQ3
F10 VCC
G1 XCIN PH7
G2 UB# P14 MTIOC0A/MTIOC3A/
MTCLKA/TMRI2 CTS1#/RTS1#/SS1#/SSLA0/
TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12/USB0_OVRCURA
IRQ4
G3 P12 TMCI1 SCK12/SCK0 SEG01 IRQ2
G4 MD FINED
G5 P10 MTIC5V/POE1# TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12/TXD0/SMOSI0/SSDA0 SEG03 IRQ6
G6 P50 MTIOC2A MOSIA/TXD2/SMOSI2/SSDA2 SEG08
G7 PB5 MTIOC1B/MTIOC2A/
POE1#/TMRI1 SCK9/SSISCK0 SEG13/
COM6
G8 PB2 CTS6#/RTS6#/SS6# SEG16
G9 PB1 MTIOC0C/MTIOC4C/
TMCI0 TXD6/SMOSI6/SSDA6/SSIWS0 SEG17 IRQ4
G10 PB3 MTIOC0A/MTIOC3B/
MTIOC4A/POE3#/TMO0 SCK6/AUDIO_MCLK/
USB0_OVRCURA SEG15/
COM7
Table 1.6 List of Pins and Pin Functions (100-Pin TFLGA) (2/3)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC, TMR) Communication
(SCIe, SCIf, RSPI, RIIC, USB, SSI) LCD,
Touch Others
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Mar 31, 2016
RX113 Group 1. Overview
Note 1. Not 5 V tolerant.
Note 2. The power source of the I/O buffer for these pins is AVCC0.
H1 XTAL
H2 EXTAL
H3 P15 MTIOC0B/MTCLKB/
TMCI2 RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT/
CACREF
H4 P13 MTIOC0B/TMO3 CTS12#/RTS12#/SS12#/CTS0#/
RTS0#/SS0# SEG00 IRQ3
H5 P11 MTIC5U/POE0# RXD12/RXDX12/SMISO12/
SSCL12/RXD0/SMISO0/SSCL0 SEG02 IRQ7
H6 P51 MTIOC4C RSPCKA/SCK2 SEG07
H7 PC0 MTIOC3C CTS5#/RTS5#/SS5#/SSLA1 SEG10
H8 PC1 MTIOC3A SCK5/SSLA2 SEG09
H9 PB6 MTIOC3D RXD9/SMISO9/SSCL9/SSIRXD0 SEG12/
COM5
H10 PB7 MTIOC3B TXD9/SMOSI9/SSDA9/SSITXD0 SEG11/
COM4
J1 VCL
J2 P17 MTIOC0C/MTIOC3A/
MTIOC3B/POE8#/TMO1 SCK1/MISOA/SDA0/RXD12/
RXDX12/SMISO12/SSCL12 IRQ7
J3 P32 MTIOC0C/RTCOUT/
TMO3 TXD6/SMOSI6/SSDA6/CTS6#/
RTS6#/SS6# TS11 IRQ2
J4 VCC_USB
J5 VSS_USB
J6 P52 MISOA/RXD2/SMISO2/SSCL2 SEG06
J7 P55 MTIOC4D/TMO3 VL1
J8 PC7 MTIOC3A/MTCLKB/
TMO2 TXD1/SMOSI1/SSDA1/MISOA/
TXD8/SMOSI8/SSDA8/
USB0_OVRCURB
VL3 CACREF
J9 PC4 MTIOC3D/MTCLKC/
POE0#/TMCI1 SSLA0/CTS8#/RTS8#/SS8#/SCK5/
USB0_VBUSEN/USB0_VBUS *1COM1 IRQ2/CLKOUT
J10 PC2 MTIOC4B RXD5/SMOSI5/SSCL5/IRRXD5/
SSLA3 COM3
K1 VSS
K2 VDD
K3 P16 MTIOC3C/MTIOC3D/
RTCOUT/TMO2 TXD1/SMOSI1/SSDA1/MOSIA/
SCL0/USB0_VBUS/
USB0_VBUSEN/USB0_OVRCURB
IRQ6/ADTRG0#
K4 USB0_DM
K5 USB0_DP
K6 P53 MTIOC2B SSLA0/CTS2#/RTS2#/SS2# SEG05
K7 P54 MTIOC4B/TMCI1 VL2
K8 PC6 MTIOC3C/MTCLKA/
TMCI2 RXD1/SMISO1/SSCL1/MOSIA/
RXD8/SMISO8/SSCL8/
USB0_EXICEN
VL4
K9 PC5 MTIOC3B/MTCLKD/
TMRI2 SCK1/RSPCKA/SCK8/USB0_ID COM0
K10 PC3 MTIOC4D TXD5/SMOSI5/SSDA5/IRTXD5 COM2
Table 1.6 List of Pins and Pin Functions (100-Pin TFLGA) (3/3)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC, TMR) Communication
(SCIe, SCIf, RSPI, RIIC, USB, SSI) LCD,
Touch Others
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Mar 31, 2016
RX113 Group 1. Overview
Table 1.7 List of Pins an d Pin Functions (64-Pin LFQFP) (1/2)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC, TMR) Communication
(SCIe, SCIf, RSPI, RIIC, USB, SSI) LCD,
Touch Others
1PJ0 DA0
2 P27 MTIOC2B/TMCI3 SCK1/SCK12/RXD6/SMISO6/
SSCL6 IRQ3/CMPA2/
CACREF/
ADTRG0#
3 P26 MTIOC2A/TMO1 TXD1/SMOSI1/SSDA1/
USB0_VBUSEN/TXD6/SMOSI6/
SSDA6
4 P30 MTIOC4B/POE8#/TMRI3 RXD1/SMISO1/SSCL1 CAPH IRQ0
5 P31 MTIOC4D/TMCI2 CTS1#/RTS1#/SS1# CAPL IRQ1
6MD FINED
7RES#
8XCOUT
9XCIN PH7
10 UPSEL P35 NMI
11 XTAL
12 EXTAL
13 VCL
14 VSS
15 VCC
16 P32 MTIOC0C/RTCOUT/
TMO3 TXD6/SMOSI6/SSDA6/CTS6#/
RTS6#/SS6# IRQ2
17 P17 MTIOC0C/MTIOC3A/
MTIOC3B/POE8#/TMO1 SCK1/MISOA/SDA0/RXD12/
RXDX12/SMISO12/SSCL12 IRQ7
18 P16 MTIOC3C/MTIOC3D/
RTCOUT/TMO2 TXD1/SMOSI1/SSDA1/MOSIA/
SCL0/USB0_VBUS/
USB0_VBUSEN/USB0_OVRCURB
IRQ6/ADTRG0#
19 P15 MTIOC0B/MTCLKB/
TMCI2 RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT/
CACREF
20 UB# P14 MTIOC0A/MTIOC3A/
MTCLKA/TMRI2 CTS1#/RTS1#/SS1#/SSLA0/
TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12/USB0_OVRCURA
IRQ4
21 VCC_USB
22 USB0_DM
23 USB0_DP
24 VSS_USB
25 P55 MTIOC4D/TMO3 VL1
26 P54 MTIOC4B/TMCI1 VL2
27 PC7 MTIOC3A/MTCLKB/
TMO2 TXD1/SMOSI1/SSDA1/MISOA/
TXD8/SMOSI8/SSDA8/
USB0_OVRCURB
VL3 CACREF
28 PC6 MTIOC3C/MTCLKA/
TMCI2 RXD1/SMISO1/SSCL1/MOSIA/
RXD8/SMISO8/SSCL8/
USB0_EXICEN
VL4
29 PC5 MTIOC3B/MTCLKD/
TMRI2 SCK1/RSPCKA/SCK8/USB0_ID COM0
30 PC4 MTIOC3D/MTCLKC/
POE0#/TMCI1 SSLA0/CTS8#/RTS8#/SS8#/SCK5/
USB0_VBUSEN/USB0_VBUS *1COM1 IRQ2/CLKOUT
31 PC3 MTIOC4D TXD5/SMOSI5/SSDA5/IRTXD5 COM2
32 PC2 MTIOC4B RXD5/SMISO5/SSCL5/SSLA3/
IRRXD5 COM3
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RX113 Group 1. Overview
Note 1. Not 5 V tolerant.
Note 2. The power source of the I/O buffer for these pins is AVCC0.
33 PB7/
PC1 MTIOC3B TXD9/SMOSI9/SSDA9/SSITXD0 SEG11/
COM4
34 PB6/
PC0 MTIOC3D RXD9/SMOSI9/SSCL9/SSIRXD0 SEG12/
COM5
35 PB5 MTIOC2A/MTIOC1B/
POE1#/TMRI1 SCK9/SSISCK0 SEG13/
COM6
36 PB3 MTIOC0A/MTIOC3B/
MTIOC4A/POE3#/TMO0 SCK6/AUDIO_MCLK/
USB0_OVRCURA SEG15/
COM7
37 PB1 MTIOC0C/MTIOC4C/
TMCI0 TXD6/SMOSI6/SSDA6/SSIWS0 SEG17 IRQ4
38 VCC
39 PB0 MTIC5W/MTIOC0C/
RTCOUT SCL0/RSPCKA/RXD6/SMOSI6/
SSCL6 IRQ2/ADTRG0#
40 VSS
41 PA6 MTIC5V/MTCLKB/
MTIOC2A/POE2#/TMCI3 CTS5#/RTS5#/SS5#/SDA0/MOSIA IRQ3
42 PA4 MTIC5U/MTCLKA/
MTIOC2B/TMRI0 TXD5/SMOSI5/SSDA5/IRTXD5/
SSLA0 SEG20 IRQ5/CVREFB1
43 PA3 MTIOC0D/MTCLKD/
MTIOC1B/POE0# RXD5/SMISO5/SSCL5/IRRXD5/
MISOA SEG21 IRQ6/CMPB1
44 PA1 MTIOC0B/MTCLKC/
RTCOUT SCK5/SSLA2 SEG23
45 PA0 MTIOC4A SSLA1 SEG24 CACREF
46 PE5 MTIOC4C/MTIOC2B MISOA/TXD9/SMOSI9/SSDA9 SEG27 IRQ5/AN013/
CMPOB1
47 PE4 MTIOC4D/MTIOC1A/
MTIOC3A MOSIA/RXD9/SMISO9/SSCL9/
SSIWS0 SEG28 IRQ4/AN012
48 PE3 MTIOC0A/MTIOC1B/
MTIOC4B/POE8# CTS12#/RTS12#/SS12#/RSPCKA/
SCK9/AUDIO_MCLK SEG29 IRQ3/AN011
49 PE2 MTIOC4A RXD12/RXDX12/SMISO12/
SSCL12/RXDX12/SSIRXD0 SEG30 IRQ7/AN010/
CVREFB0
50 PE1 MTIOC4C TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12/SSITXD0 SEG31 IRQ1/AN009/
CMPB0
51 PE0 MTIOC2A/POE3# SCK12/CTS9#/RTS9#/SS6#/
SSISCK0 SEG32 IRQ0/AN008
52 PE7 SEG33 IRQ7/AN015/
CMPOB0
53 PE6 SEG34 IRQ6/AN014
54 PD2 MTIOC4D SEG37 IRQ2
55 PD1 MTIOC4B SEG38 IRQ1
56 PD0 SEG39 IRQ0
57 VREFL P42*2AN002
58 VREFH P41*2AN001
59 VREFL0 PJ7*2
60 P40*2AN000
61 VREFH0 PJ6*2
62 AVSS0
63 AVCC0
64 PJ2 DA1
Table 1.7 List of Pins an d Pin Functions (64-Pin LFQFP) (2/2)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC, TMR) Communication
(SCIe, SCIf, RSPI, RIIC, USB, SSI) LCD,
Touch Others
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RX113 Group 2. CPU
2. CPU
Figure 2.1 shows the register set of the CPU.
Figure 2.1 Register Set of the CPU
Note 1. The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according to
the value of the U bit in the PSW regis ter.
USP (User stack pointer)
ISP (Interrupt stack pointer)
INTB (Interrupt table register)
PC (Program counter)
PSW (Processor status word)
BPC (Backup PC)
BPSW (Backup PSW)
FINTV (Fast interrupt vector register)
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0 (SP)*1
General -purpose regist ers
Control registers
b31 b0
b31 b0
DSP instruct ion regist er
b63 b0
ACC (Accumulator)
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RX113 Group 2. CPU
2.1 Genera l-Purpose Registers (R0 to R15)
This CPU has 16 general-purpose registers (R0 to R15). R0 to R15 can be used as data registers or address registers.
R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the
interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor
status word (PSW).
2.2 Control Registers
(1) Interrupt Stack Pointer (ISP)/User Stack Pointer (USP)
The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP).
Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the
processor status word (PSW).
Set the ISP or USP to a multiple of 4, as this reduces the numbers of cycles required to execute interrupt sequences and
instructions entailing stack manipulation.
(2) Interrupt Table Register (INTB)
The interrupt table register (INTB) specifies the address where the relocatable vector table starts.
(3) Program Counter (PC)
The program counter (PC) indicates the address of the instruction being executed.
(4) Processor Status Word (PSW)
The processor status word (PSW) indicates the results of instruction execution or the state of the CPU.
(5) Backup PC (BPC)
The backup PC (BPC) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register.
(6) Backup PSW (BPSW)
The backup PSW (BPSW) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The
allocation of bits in the BPSW corresponds to that in the PSW.
(7) Fast Interrupt Vector Register (FINTV)
The fast in ter rupt vector register (FINTV) is provided to speed up response to interrupts.
The FINTV register specifies a branc h des tination address when a fast interrupt has been generated.
2.3 Register Associated with DSP Instructions
(1) Accumulator (ACC)
The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and
multiply-and-accumulate instructions; EMUL, EMULU, MUL, and RMPA, in which case the prior value in the
accumulator is modified by execution of the instruction.
Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO
instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively.
Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI
instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
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Mar 31, 2016
RX113 Group 3. Address Space
3. Address Space
3.1 Address Space
This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is,
linear access to an address space of up to 4 Gbytes is possible, and this contains program area.
Figure 3.1 shows the memory map.
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Mar 31, 2016
RX113 Group 3. Address Space
Figure 3.1 Memory Map
Reserved area*3
Reserved area*3
Reserved area*3
On-chip ROM (E2DataFlash)
(8 KB)
Reserved area*3
Single-chip mode*1
RAM*2
On-chip ROM (program ROM)*2
Peripheral I/O registers
Peripheral I/O registers
Peripheral I/O registers
0000 0000h
0001 0000h
0008 0000h
0010 0000h
0010 2000h
007F C000h
007F C500h
007F FC00h
0080 0000h
FFF8 0000h
FFFF FFFFh
Note 1. The address space in boot mode is the same as th e address space in single-chip mode.
Note 2. The capacity of ROM/RAM differs depending on the products.
Note: See Table 1.3, List of Products, for the product type name.
Note 3. Reserved areas should not be accessed.
ROM (bytes) RAM (bytes)
Capacity Address Capacity Address
512 K FFF8 0000h to FFFF FFFFh 64 K 0000 0000h to 0000 FFFFh
384 K FFFA 0000h to FFFF FFFFh
256 K FFFC 0000h to FFFF FFFFh 32 K 0000 0000h to 0000 7FFFh
128 K FFFE 0000h to FFFF FFFFh
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RX113 Group 4. I/O Regis ters
4. I/O Registers
This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as
shown below. Notes on writing to I/O registers are also given below.
(1) I/O register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified according to module symbols.
Numbers of cycles for access indicate numbers of cycles of the given base clock.
Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses
must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and
subsequent operations cannot be guaranteed.
(2) Notes on writing to I/O registers
While writing to an I/O register, the CPU starts executing subsequent instructions before the I/O register write access is
completed. This may cause the subsequent instructions to be executed before the write value is reflected in the operation.
The examples below show how subsequent instructions must be executed after a write access to an I/O register is
completed.
[Examples of cases requiring special care]
The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the
ICU (interrupt request enable bit) set to 0.
A WAIT instruction is executed immediately after the preprocessing for causing a tran sition to the low power
consumption state.
In the above cases, after writing to an I/O register, wait until the write operation is completed using the fo llowing
procedure and then execute the subsequent instruction.
(a) Write to an I/O register.
(b) Read the value in the I/O register and write it to a general register.
(c) Execute the operation using the value read.
(d) Execute the subsequent instruction .
Example of instructions
Byte-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.B #SFR_DATA, [R1]
CMP [R1].UB, R1
;; Next process
Word-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.W #SFR_DATA, [R1]
CMP [R1].W, R1
;; Next process
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RX113 Group 4. I/O Regis ters
Longword-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.L #SFR_DATA, [R1]
CMP [R1].L, R1
;; Next process
When executing an instruction after writing to multiple registers, only read the last I/O register written to and execute the
instruction using that value; it is not necessary to execute th e instruction using the values written to all the reg isters.
(3) Number of cycles necessary for accessing I/O registers
See Table 4.1 for details on the number of clock cycles necessary for accessing I/O registers.
The number of access cycles to I/O regist ers is obtained by following equation.*1
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
Number of divided clock synchronizati on cycles +
Number of bus cycles for internal peripheral buses 1 to 6
The number of bus cycles of internal peripheral buses 1 to 6 differs according to the register to be accessed.
When peripheral functions connected to internal peripheral buses 2 to 6 or regist ers for the external bus cont rol unit
(except for bus error related registers) are accessed, the number of divided clock synchronization cycles is added.
The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK
(or FCLK) or bus access timing.
In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the
sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will
be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of
access cycles shown in Tab l e 4.1.
When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the su bsequent bus access is started from the
ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described
on an ICLK basis.
Note 1. This applies to the number of cycles when the access from the CPU does not conflict with the bus access from
the different bus master (DTC).
(4) Notes on sleep mode and mode transitions
During sleep mode or mode transitions, do not write to the system control related registers (indicated by ‘SYSTEM’ in
the Module Symbol column in Table 4.1, List of I/O Registers (Address Order)).
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RX113 Group 4. I/O Regis ters
4.1 I/O Register Addresses (Address Order)
Table 4.1 List of I/O Registers (Address Order) (1/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
0008 0000h SYS TE M Mode Monitor Register MDMONR 16 16 3 ICLK
0008 0008h SYSTEM System Control Register 1 SYSCR1 16 16 3 ICLK
0008 000Ch SYSTEM Standby Control Register SBYCR 16 16 3 ICLK
0008 0010h SYSTEM Module Stop Control Register A MSTPCRA 32 32 3 ICLK
0008 0014h SYSTEM Module Stop Control Register B MSTPCRB 32 32 3 ICLK
0008 0018h SYSTEM Module Stop Control Register C MSTPCRC 32 32 3 ICLK
0008 001Ch SYSTEM Module Stop Control Register D MSTPCRD 32 32 3 ICLK
0008 0020h SYS TEM System Clock Control Register SCKCR 32 32 3 ICLK
0008 0026h SYSTEM System Clock Control Register 3 SCKCR3 16 16 3 ICLK
0008 0028h SYSTEM PLL Control Register PLLCR 16 16 3 ICLK
0008 002Ah SYSTEM PLL Control Register 2 PLLCR2 8 8 3 ICLK
0008 002Ch SYSTEM USB-dedicated PLL Control Register UPLLCR 16 16 3ICLK
0008 002Eh SYSTEM USB-dedicated PLL Control Register 2 UPLLCR2 8 8 3ICLK
0008 0032h SYSTEM Main Clock Oscillator Control Register MOSCCR 8 8 3 ICLK
0008 0033h SYSTEM Sub-Clock Oscillator Control Register SOSCCR 8 8 3 ICLK
0008 0034h SYSTEM Low-Speed On-Chip Oscillator Control Register LOCOCR 8 8 3 ICLK
0008 0035h SYSTEM IWDT-Dedicated On-Chip Oscillator Control Register ILOCOCR 8 8 3 ICLK
0008 0036h SYSTEM High-Speed On-Chip Oscillator Control Register HOCOCR 8 8 3 ICLK
0008 003Ch SYSTEM Oscillation Stabilization Flag Register OSCOVFSR 8 8 3 ICLK
0008 003Eh SYSTEM CLKOUT Output Control Register CKOCR 16 16 3 ICLK
0008 0040h SYSTEM Oscillation Stop Detection Control Register OSTDCR 8 8 3 ICLK
0008 0041h SYSTEM Oscillation Stop Detection Status Register OSTDSR 8 8 3 ICLK
0008 0050h SYSTEM LCD Source Clock Control Register LCDSCLKCR 8 8 3 ICLK
0008 0051h SYSTEM LCD Source Clock Contr o l Register 2 LCDSCLKCR2 8 8 3 ICLK
0008 00A0h SYSTEM Operating Power Contro l R egi ste r OPCCR 8 8 3 ICLK
0008 00A1h SYSTEM Sleep Mode Return Clock Source Switching Register RSTCKCR 8 8 3 ICLK
0008 00A2h SYSTEM Main Clock Oscillator Wait Control Register MOSCWTCR 8 8 3 ICLK
0008 00A5h SYSTEM High-Speed On-Chip Oscillator Wait Control Register HOCOWTCR 8 8 3 ICLK
0008 00AAh SYSTEM Sub Operating Power Control Register SOPCCR 8 8 3 ICLK
0008 00B0h LPT Low-power Timer Control Register 1 LPTCR1 8 8 3 ICLK
0008 00B1h LPT Low-power Timer Control Register 2 LPTCR2 8 8 3 ICLK
0008 00B2h LPT Low-power Timer Control Register 3 LPTCR3 8 8 3 ICLK
0008 00B4h LPT Low-Power Timer Cycle Setting Registe r LPTPRD 16 16 3 ICLK
0008 00B8h LPT Low-Power Timer Compare Register 0 LPCMR0 16 16 3 ICLK
0008 00BCh LPT Low-Power Timer Standby Wakeup Enable Register LPWUCR 16 16 3 ICLK
0008 00C0h SYSTEM Reset Status Register 2 RSTSR2 8 8 3 ICLK
0008 00C2h SYSTEM Software Re set R egister SWRR 16 16 3 ICLK
0008 00E0 h SYST EM Voltage Monitoring 1 Circuit Control Register 1 LVD1C R1 8 8 3 ICLK
0008 00E1h SYSTEM Voltage Monitoring 1 Circuit Status Register LVD1SR 8 8 3 ICLK
0008 00E2 h SYST EM Voltage Monitoring 2 Circuit Control Register 1 LVD2C R1 8 8 3 ICLK
0008 00E3h SYSTEM Voltage Monitoring 2 Circuit Status Register LVD2SR 8 8 3 ICLK
0008 03FEh SYSTEM Protect Register PRCR 16 16 3 ICLK
0008 1300h BSC Bus Error Status Clear Register BERCLR 8 8 2 ICLK
0008 1304h BSC Bus Error Monitoring Enable Register BEREN 8 8 2 ICLK
0008 1308h BSC Bus Error Status Register 1 BERSR1 8 8 2 ICLK
0008 130Ah BSC Bus Error Status Register 2 BERSR2 16 16 2 ICLK
0008 1310h BSC Bus Priority Contro l Re gi ste r BUSPRI 16 16 2 ICLK
0008 2400h DTC DTC Control Register DTCCR 8 8 2 ICLK
0008 2404h DTC DTC Vector Base Register DTCVBR 32 32 2 ICLK
0008 2408h DTC DTC Address Mode Register DTCADMOD 8 8 2 ICLK
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RX113 Group 4. I/O Regis ters
0008 240Ch DTC DTC Module Start Register DTCST 8 8 2 ICLK
0008 240Eh DTC DTC Status Register DTCSTS 16 16 2 ICLK
0008 7010h ICU Interrupt Request Register 016 IR016 8 8 2 ICLK
0008 701Bh ICU Interrupt Request Register 027 IR027 8 8 2 ICLK
0008 701Ch ICU Interrupt Request Register 028 IR028 8 8 2 ICLK
0008 701Dh ICU Interrupt Request Register 029 IR029 8 8 2 ICLK
0008 701Eh ICU Interrupt Request Register 030 IR030 8 8 2 ICLK
0008 701Fh ICU Interrupt Request Register 031 IR031 8 8 2 ICLK
0008 7020h ICU Interrupt Request Register 032 IR032 8 8 2 ICLK
0008 7021h ICU Interrupt Request Register 033 IR033 8 8 2 ICLK
0008 7022h ICU Interrupt Request Register 034 IR034 8 8 2 ICLK
0008 7024h ICU Interrupt Request Register 036 IR036 8 8 2 ICLK
0008 7025h ICU Interrupt Request Register 037 IR037 8 8 2 ICLK
0008 7026h ICU Interrupt Request Register 038 IR038 8 8 2 ICLK
0008 702Ch ICU Interrupt Request Register 044 IR044 8 8 2 ICLK
0008 702Dh ICU Interrupt Request Register 045 IR045 8 8 2 ICLK
0008 702Eh ICU Interrupt Request Register 046 IR046 8 8 2 ICLK
0008 702Fh ICU Interrupt Request Register 047 IR047 8 8 2 ICLK
0008 7039h ICU Interrupt Request Register 057 IR057 8 8 2 ICLK
0008 703Ah ICU Interrupt Request Register 058 IR058 8 8 2 ICLK
0008 703Bh ICU Interrupt Request Register 059 IR059 8 8 2 ICLK
0008 703Ch ICU Interrupt Request Register 060 IR060 8 8 2 ICLK
0008 703Dh ICU Interrupt Request Register 061 IR061 8 8 2 ICLK
0008 703Eh ICU Interrupt Request Register 062 IR062 8 8 2 ICLK
0008 703Fh ICU Interrupt Request Register 063 IR063 8 8 2 ICLK
0008 7040h ICU Interrupt Request Register 064 IR064 8 8 2 ICLK
0008 7041h ICU Interrupt Request Register 065 IR065 8 8 2 ICLK
0008 7042h ICU Interrupt Request Register 066 IR066 8 8 2 ICLK
0008 7043h ICU Interrupt Request Register 067 IR067 8 8 2 ICLK
0008 7044h ICU Interrupt Request Register 068 IR068 8 8 2 ICLK
0008 7045h ICU Interrupt Request Register 069 IR069 8 8 2 ICLK
0008 7046h ICU Interrupt Request Register 070 IR070 8 8 2 ICLK
0008 7047h ICU Interrupt Request Register 071 IR071 8 8 2 ICLK
0008 7058h ICU Interrupt Request Register 088 IR088 8 8 2 ICLK
0008 7059h ICU Interrupt Request Register 089 IR089 8 8 2 ICLK
0008 705Ah ICU Interrupt Request Register 090 IR090 8 8 2 ICLK
0008 705Ch ICU Interrupt Request Register 092 IR092 8 8 2 ICLK
0008 705Dh ICU Interrupt Request Register 093 IR093 8 8 2 ICLK
0008 7066h ICU Interrupt Request Register 102 IR102 8 8 2 ICLK
0008 7067h ICU Interrupt Request Register 103 IR103 8 8 2 ICLK
0008 706Ah ICU Interrupt Request Register 106 IR106 8 8 2 ICLK
0008 706Ch ICU Interrupt Request Register 108 IR108 8 8 2 ICLK
0008 706Dh ICU Interrupt Request Register 109 IR109 8 8 2 ICLK
0008 706Eh ICU Interrupt Request Register 110 IR110 8 8 2 ICLK
0008 7072h ICU Interrupt Request Register 114 IR114 8 8 2 ICLK
0008 7073h ICU Interrupt Request Register 115 IR115 8 8 2 ICLK
0008 7074h ICU Interrupt Request Register 116 IR116 8 8 2 ICLK
0008 7075h ICU Interrupt Request Register 117 IR117 8 8 2 ICLK
0008 7076h ICU Interrupt Request Register 118 IR118 8 8 2 ICLK
0008 7077h ICU Interrupt Request Register 119 IR119 8 8 2 ICLK
0008 7078h ICU Interrupt Request Register 120 IR120 8 8 2 ICLK
0008 7079h ICU Interrupt Request Register 121 IR121 8 8 2 ICLK
Table 4.1 List of I/O Registers (Address Order) (2/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
R01DS0216EJ0110 Rev.1.10 Page 32 of 131
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RX113 Group 4. I/O Regis ters
0008 707Ah ICU Interrupt Request Register 122 IR122 8 8 2 ICLK
0008 707Bh ICU Interrupt Request Register 123 IR123 8 8 2 ICLK
0008 707Ch ICU Interrupt Request Register 124 IR124 8 8 2 ICLK
0008 707Dh ICU Interrupt Request Register 125 IR125 8 8 2 ICLK
0008 707Eh ICU Interrupt Request Register 126 IR126 8 8 2 ICLK
0008 707Fh ICU Interrupt Request Register 127 IR127 8 8 2 ICLK
0008 7080h ICU Interrupt Request Register 128 IR128 8 8 2 ICLK
0008 7081h ICU Interrupt Request Register 129 IR129 8 8 2 ICLK
0008 7082h ICU Interrupt Request Register 130 IR130 8 8 2 ICLK
0008 7083h ICU Interrupt Request Register 131 IR131 8 8 2 ICLK
0008 7084h ICU Interrupt Request Register 132 IR132 8 8 2 ICLK
0008 7085h ICU Interrupt Request Register 133 IR133 8 8 2 ICLK
0008 7086h ICU Interrupt Request Register 134 IR134 8 8 2 ICLK
0008 7087h ICU Interrupt Request Register 135 IR135 8 8 2 ICLK
0008 7088h ICU Interrupt Request Register 136 IR136 8 8 2 ICLK
0008 7089h ICU Interrupt Request Register 137 IR137 8 8 2 ICLK
0008 708Ah ICU Interrupt Request Register 138 IR138 8 8 2 ICLK
0008 708Bh ICU Interrupt Request Register 139 IR139 8 8 2 ICLK
0008 708Ch ICU Interrupt Request Register 140 IR140 8 8 2 ICLK
0008 708Dh ICU Interrupt Request Register 141 IR141 8 8 2 ICLK
0008 70AAh ICU Interrupt Request Register 170 IR170 8 8 2 ICLK
0008 70ABh ICU Interrupt Request Register 171 IR171 8 8 2 ICLK
0008 70AEh ICU Interrupt Request Register 174 IR174 8 8 2 ICLK
0008 70AFh ICU Interrupt Request Register 175 IR175 8 8 2 ICLK
0008 70B0h ICU Interrupt Request Register 176 IR176 8 8 2 ICLK
0008 70B1h ICU Interrupt Request Register 177 IR177 8 8 2 ICLK
0008 70B2h ICU Interrupt Request Register 178 IR178 8 8 2 ICLK
0008 70B3h ICU Interrupt Request Register 179 IR179 8 8 2 ICLK
0008 70B4h ICU Interrupt Request Register 180 IR180 8 8 2 ICLK
0008 70B5h ICU Interrupt Request Register 181 IR181 8 8 2 ICLK
0008 70B6h ICU Interrupt Request Register 182 IR182 8 8 2 ICLK
0008 70B7h ICU Interrupt Request Register 183 IR183 8 8 2 ICLK
0008 70B8h ICU Interrupt Request Register 184 IR184 8 8 2 ICLK
0008 70B9h ICU Interrupt Request Register 185 IR185 8 8 2 ICLK
0008 70BAh ICU Interrupt Request Register 186 IR186 8 8 2 ICLK
0008 70BBh ICU Interrupt Request Register 187 IR187 8 8 2 ICLK
0008 70BCh ICU Interrupt Request Register 188 IR188 8 8 2 ICLK
0008 70BDh ICU Interrupt Request Register 189 IR189 8 8 2 ICLK
0008 70D6h ICU Interrupt Request Register 214 IR214 8 8 2 ICLK
0008 70D7h ICU Interrupt Request Register 215 IR215 8 8 2 ICLK
0008 70D8h ICU Interrupt Request Register 216 IR216 8 8 2 ICLK
0008 70D9h ICU Interrupt Request Register 217 IR217 8 8 2 ICLK
0008 70DAh ICU Interrupt Request Register 218 IR218 8 8 2 ICLK
0008 70DBh ICU Interrupt Request Register 219 IR219 8 8 2 ICLK
0008 70DCh ICU Interrupt Request Register 220 IR220 8 8 2 ICLK
0008 70DDh ICU Interrupt Request Register 221 IR221 8 8 2 ICLK
0008 70DEh ICU Interrupt Request Register 222 IR222 8 8 2 ICLK
0008 70DFh ICU Interrupt Request Register 223 IR223 8 8 2 ICLK
0008 70E0h ICU Interrupt Request Register 224 IR224 8 8 2 ICLK
0008 70E1h ICU Interrupt Request Register 225 IR225 8 8 2 ICLK
0008 70E2h ICU Interrupt Request Register 226 IR226 8 8 2 ICLK
0008 70E3h ICU Interrupt Request Register 227 IR227 8 8 2 ICLK
Table 4.1 List of I/O Registers (Address Order) (3/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 70E4h ICU Interrupt Request Register 228 IR228 8 8 2 ICLK
0008 70E5h ICU Interrupt Request Register 229 IR229 8 8 2 ICLK
0008 70E6h ICU Interrupt Request Register 230 IR230 8 8 2 ICLK
0008 70E7h ICU Interrupt Request Register 231 IR231 8 8 2 ICLK
0008 70E8h ICU Interrupt Request Register 232 IR232 8 8 2 ICLK
0008 70E9h ICU Interrupt Request Register 233 IR233 8 8 2 ICLK
0008 70EAh ICU Interrupt Request Register 234 IR234 8 8 2 ICLK
0008 70EBh ICU Interrupt Request Register 235 IR235 8 8 2 ICLK
0008 70ECh ICU Interrupt Request Register 236 IR236 8 8 2 ICLK
0008 70EDh ICU Interrupt Request Register 237 IR237 8 8 2 ICLK
0008 70EEh ICU Interrupt Request Register 238 IR238 8 8 2 ICLK
0008 70EFh ICU Interrupt Request Register 239 IR239 8 8 2 ICLK
0008 70F0h ICU Interrupt Request Register 240 IR240 8 8 2 ICLK
0008 70F1h ICU Interrupt Request Register 241 IR241 8 8 2 ICLK
0008 70F2h ICU Interrupt Request Register 242 IR242 8 8 2 ICLK
0008 70F3h ICU Interrupt Request Register 243 IR243 8 8 2 ICLK
0008 70F4h ICU Interrupt Request Register 244 IR244 8 8 2 ICLK
0008 70F5h ICU Interrupt Request Register 245 IR245 8 8 2 ICLK
0008 70F6h ICU Interrupt Request Register 246 IR246 8 8 2 ICLK
0008 70F7h ICU Interrupt Request Register 247 IR247 8 8 2 ICLK
0008 70F8h ICU Interrupt Request Register 248 IR248 8 8 2 ICLK
0008 70F9h ICU Interrupt Request Register 249 IR249 8 8 2 ICLK
0008 711Bh ICU DTC Activation Enable Register 027 DTCER027 8 8 2 ICLK
0008 711Ch ICU DTC Activation Enable Register 028 DTCER028 8 8 2 ICLK
0008 711Dh ICU DTC Activation Enable Register 029 DTCER029 8 8 2 ICLK
0008 711Eh ICU DTC Activation Enable Register 030 DTCER030 8 8 2 ICLK
0008 711Fh ICU DTC Activation Enable Register 031 DTCER031 8 8 2 ICLK
0008 7124h ICU DTC Activation Enable Register 036 DTCER036 8 8 2 ICLK
0008 7125h ICU DTC Activation Enable Register 037 DTCER037 8 8 2 ICLK
0008 712Dh ICU DTC Activation Enable Register 045 DTCER045 8 8 2 ICLK
0008 712Eh ICU DTC Activation Enable Register 046 DTCER046 8 8 2 ICLK
0008 713Ah ICU DTC Activation Enable Register 058 DTCER058 8 8 2 ICLK
0008 713Bh ICU DTC Activation Enable Register 059 DTCER059 8 8 2 ICLK
0008 713Ch ICU DTC Activation Enable Register 060 DTCER060 8 8 2 ICLK
0008 713Dh ICU DTC Activation Enable Register 061 DTCER061 8 8 2 ICLK
0008 7140h ICU DTC Activation Enable Register 064 DTCER064 8 8 2 ICLK
0008 7141h ICU DTC Activation Enable Register 065 DTCER065 8 8 2 ICLK
0008 7142h ICU DTC Activation Enable Register 066 DTCER066 8 8 2 ICLK
0008 7143h ICU DTC Activation Enable Register 067 DTCER067 8 8 2 ICLK
0008 7144h ICU DTC Activation Enable Register 068 DTCER068 8 8 2 ICLK
0008 7145h ICU DTC Activation Enable Register 069 DTCER069 8 8 2 ICLK
0008 7146h ICU DTC Activation Enable Register 070 DTCER070 8 8 2 ICLK
0008 7147h ICU DTC Activation Enable Register 071 DTCER071 8 8 2 ICLK
0008 7166h ICU DTC Activation Enable Register 102 DTCER102 8 8 2 ICLK
0008 7167h ICU DTC Activation Enable Register 103 DTCER103 8 8 2 ICLK
0008 716Ah ICU DTC Activation Enable Register 106 DTCER106 8 8 2 ICLK
0008 716Dh ICU DTC Activation Enable Register 109 DTCER109 8 8 2 ICLK
0008 716Eh ICU DTC Activation Enable Register 110 DTCER110 8 8 2 ICLK
0008 7172h ICU DTC Activation Enable Register 114 DTCER114 8 8 2 ICLK
0008 7173h ICU DTC Activation Enable Register 115 DTCER115 8 8 2 ICLK
0008 7174h ICU DTC Activation Enable Register 116 DTCER116 8 8 2 ICLK
0008 7175h ICU DTC Activation Enable Register 117 DTCER117 8 8 2 ICLK
Table 4.1 List of I/O Registers (Address Order) (4/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 7179h ICU DTC Activation Enable Register 121 DTCER121 8 8 2 ICLK
0008 717Ah ICU DTC Activation Enable Register 122 DTCER122 8 8 2 ICLK
0008 717Dh ICU DTC Activation Enable Register 125 DTCER125 8 8 2 ICLK
0008 717Eh ICU DTC Activation Enable Register 126 DTCER126 8 8 2 ICLK
0008 7181h ICU DTC Activation Enable Register 129 DTCER129 8 8 2 ICLK
0008 7182h ICU DTC Activation Enable Register 130 DTCER130 8 8 2 ICLK
0008 7183h ICU DTC Activation Enable Register 131 DTCER131 8 8 2 ICLK
0008 7184h ICU DTC Activation Enable Register 132 DTCER132 8 8 2 ICLK
0008 7186h ICU DTC Activation Enable Register 134 DTCER134 8 8 2 ICLK
0008 7187h ICU DTC Activation Enable Register 135 DTCER135 8 8 2 ICLK
0008 7188h ICU DTC Activation Enable Register 136 DTCER136 8 8 2 ICLK
0008 7189h ICU DTC Activation Enable Register 137 DTCER137 8 8 2 ICLK
0008 718Ah ICU DTC Activation Enable Register 138 DTCER138 8 8 2 ICLK
0008 718Bh ICU DTC Activation Enable Register 139 DTCER139 8 8 2 ICLK
0008 718Ch ICU DTC Activation Enable Register 140 DTCER140 8 8 2 ICLK
0008 718Dh ICU DTC Activation Enable Register 141 DTCER141 8 8 2 ICLK
0008 71AEh ICU DTC Activation Enable Register 174 DTCER174 8 8 2 ICLK
0008 71AFh ICU DTC Activation Enable Register 175 DTCER175 8 8 2 ICLK
0008 71B1h ICU DTC Activation Enable Register 177 DTCER177 8 8 2 ICLK
0008 71B2h ICU DTC Activation Enable Register 178 DTCER178 8 8 2 ICLK
0008 71B4h ICU DTC Activation Enable Register 180 DTCER180 8 8 2 ICLK
0008 71B5h ICU DTC Activation Enable Register 181 DTCER181 8 8 2 ICLK
0008 71B7h ICU DTC Activation Enable Register 183 DTCER183 8 8 2 ICLK
0008 71B8h ICU DTC Activation Enable Register 184 DTCER184 8 8 2 ICLK
0008 71BBh ICU DTC Activation Enable Register 187 DTCER187 8 8 2 ICLK
0008 71BCh ICU DTC Activation Enable Register 188 DTCER188 8 8 2 ICLK
0008 71D7h ICU DTC Activation Enable Register 215 DTCER215 8 8 2 ICLK
0008 71D8h ICU DTC Activation Enable Register 216 DTCER216 8 8 2 ICLK
0008 71DBh ICU DTC Activation Enable Register 219 DTCER219 8 8 2 ICLK
0008 71DCh ICU DTC Activation Enable Register 220 DTCER220 8 8 2 ICLK
0008 71DFh ICU DTC Activation Enable Register 223 DTCER223 8 8 2 ICLK
0008 71E0h ICU DTC Activation Enable Register 224 DTCER224 8 8 2 ICLK
0008 71E3h ICU DTC Activation Enable Register 227 DTCER227 8 8 2 ICLK
0008 71E4h ICU DTC Activation Enable Register 228 DTCER228 8 8 2 ICLK
0008 71E7h ICU DTC Activation Enable Register 231 DTCER231 8 8 2 ICLK
0008 71E8h ICU DTC Activation Enable Register 232 DTCER232 8 8 2 ICLK
0008 71EBh ICU DTC Activation Enable Register 235 DTCER235 8 8 2 ICLK
0008 71ECh ICU DTC Activation Enable Register 236 DTCER236 8 8 2 ICLK
0008 71EFh ICU DTC Activation Enable Register 239 DTCER239 8 8 2 ICLK
0008 71F0h ICU DTC Activation Enable Register 240 DTCER240 8 8 2 ICLK
0008 71F7h ICU DTC Activation Enable Register 247 DTCER247 8 8 2 ICLK
0008 71F8h ICU DTC Activation Enable Register 248 DTCER248 8 8 2 ICLK
0008 7202h ICU Interrupt Request En able Register 02 IER02 8 8 2 ICLK
0008 7203h ICU Interrupt Request En able Register 03 IER03 8 8 2 ICLK
0008 7204h ICU Interrupt Request En able Register 04 IER04 8 8 2 ICLK
0008 7205h ICU Interrupt Request En able Register 05 IER05 8 8 2 ICLK
0008 7207h ICU Interrupt Request En able Register 07 IER07 8 8 2 ICLK
0008 7208h ICU Interrupt Request En able Register 08 IER08 8 8 2 ICLK
0008 720Bh ICU Interrupt Request Enable Register 0B IER0B 8 8 2 ICLK
0008 720Ch ICU Interrupt Request Enable Register 0C IER0C 8 8 2 ICLK
0008 720Dh ICU Interrupt Request Enable Register 0D IER0D 8 8 2 ICLK
0008 720Eh ICU Interrupt Request Enable Register 0E IER0E 8 8 2 ICLK
Table 4.1 List of I/O Registers (Address Order) (5/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 720Fh ICU Interrupt Request Enable Register 0F IER0F 8 8 2 ICLK
0008 7210h ICU Interrupt Request En able Register 10 IER10 8 8 2 ICLK
0008 7211h ICU Interrupt Request Enable Register 11 IER11 8 8 2 ICLK
0008 7215h ICU Interrupt Request En able Register 15 IER15 8 8 2 ICLK
0008 7216h ICU Interrupt Request En able Register 16 IER16 8 8 2 ICLK
0008 7217h ICU Interrupt Request En able Register 17 IER17 8 8 2 ICLK
0008 721Ah ICU Interrupt Request Enable Register 1A IER1A 8 8 2 ICLK
0008 721Bh ICU Interrupt Request Enable Register 1B IER1B 8 8 2 ICLK
0008 721Ch ICU Interrupt Request Enable Register 1C IER1C 8 8 2 ICLK
0008 721Dh ICU Interrupt Request Enable Register 1D IER1D 8 8 2 ICLK
0008 721Eh ICU Interrupt Request Enable Register 1E IER1E 8 8 2 ICLK
0008 721Fh ICU Interrupt Request Enable Register 1F IER1F 8 8 2 ICLK
0008 72E0h ICU Software Interrupt Activation Register SWINTR 8 8 2 ICLK
0008 72F0h ICU Fast Interrupt Set Register FIR 16 16 2 ICLK
0008 7300h ICU Interrupt Source Priority Register 000 IPR000 8 8 2 ICLK
0008 7303h ICU Interrupt Source Priority Register 003 IPR003 8 8 2 ICLK
0008 7304h ICU Interrupt Source Priority Register 004 IPR004 8 8 2 ICLK
0008 7305h ICU Interrupt Source Priority Register 005 IPR005 8 8 2 ICLK
0008 7306h ICU Interrupt Source Priority Register 006 IPR006 8 8 2 ICLK
0008 7307h ICU Interrupt Source Priority Register 007 IPR007 8 8 2 ICLK
0008 7320h ICU Interrupt Source Priority Register 032 IPR032 8 8 2 ICLK
0008 7321h ICU Interrupt Source Priority Register 033 IPR033 8 8 2 ICLK
0008 7322h ICU Interrupt Source Priority Register 034 IPR034 8 8 2 ICLK
0008 7324h ICU Interrupt Source Priority Register 036 IPR036 8 8 2 ICLK
0008 7325h ICU Interrupt Source Priority Register 037 IPR037 8 8 2 ICLK
0008 7326h ICU Interrupt Source Priority Register 038 IPR038 8 8 2 ICLK
0008 732Ch ICU Interrupt Source Priority Register 044 IPR044 8 8 2 ICLK
0008 7339h ICU Interrupt Source Priority Register 057 IPR057 8 8 2 ICLK
0008 733Ah ICU Interrupt Source Priority Register 058 IPR058 8 8 2 ICLK
0008 733Bh ICU Interrupt Source Priority Register 059 IPR059 8 8 2 ICLK
0008 733Ch ICU Interrupt Source Priority Register 060 IPR060 8 8 2 ICLK
0008 733Fh ICU Interrupt Source Priority Register 063 IPR063 8 8 2 ICLK
0008 7340h ICU Interrupt Source Priority Register 064 IPR064 8 8 2 ICLK
0008 7341h ICU Interrupt Source Priority Register 065 IPR065 8 8 2 ICLK
0008 7342h ICU Interrupt Source Priority Register 066 IPR066 8 8 2 ICLK
0008 7343h ICU Interrupt Source Priority Register 067 IPR067 8 8 2 ICLK
0008 7344h ICU Interrupt Source Priority Register 068 IPR068 8 8 2 ICLK
0008 7345h ICU Interrupt Source Priority Register 069 IPR069 8 8 2 ICLK
0008 7346h ICU Interrupt Source Priority Register 070 IPR070 8 8 2 ICLK
0008 7347h ICU Interrupt Source Priority Register 071 IPR071 8 8 2 ICLK
0008 7358h ICU Interrupt Source Priority Register 088 IPR088 8 8 2 ICLK
0008 7359h ICU Interrupt Source Priority Register 089 IPR089 8 8 2 ICLK
0008 735Ah ICU Interrupt Source Priority Register 090 IPR090 8 8 2 ICLK
0008 735Ch ICU Interrupt Source Priority Register 092 IPR092 8 8 2 ICLK
0008 735Dh ICU Interrupt Source Priority Register 093 IPR093 8 8 2 ICLK
0008 7366h ICU Interrupt Source Priority Register 102 IPR102 8 8 2 ICLK
0008 7367h ICU Interrupt Source Priority Register 103 IPR103 8 8 2 ICLK
0008 736Ah ICU Interrupt Source Priority Register 106 IPR106 8 8 2 ICLK
0008 736Ch ICU Interrupt Source Priority Register 108 IPR108 8 8 2 ICLK
0008 7372h ICU Interrupt Source Priority Register 114 IPR114 8 8 2 ICLK
0008 7376h ICU Interrupt Source Priority Register 118 IPR118 8 8 2 ICLK
0008 7379h ICU Interrupt Source Priority Register 121 IPR121 8 8 2 ICLK
Table 4.1 List of I/O Registers (Address Order) (6/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 737Bh ICU Interrupt Source Priority Register 123 IPR123 8 8 2 ICLK
0008 737Dh ICU Interrupt Source Priority Register 125 IPR125 8 8 2 ICLK
0008 737Fh ICU Interrupt Source Priority Register 127 IPR127 8 8 2 ICLK
0008 7381h ICU Interrupt Source Priority Register 129 IPR129 8 8 2 ICLK
0008 7385h ICU Interrupt Source Priority Register 133 IPR133 8 8 2 ICLK
0008 7386h ICU Interrupt Source Priority Register 134 IPR134 8 8 2 ICLK
0008 738Ah ICU Interrupt Source Priority Register 138 IPR138 8 8 2 ICLK
0008 738Bh ICU Interrupt Source Priority Register 139 IPR139 8 8 2 ICLK
0008 73AAh ICU Interrupt Source Priority Register 170 IPR170 8 8 2 ICLK
0008 73ABh ICU Interrupt Source Priority Register 171 IPR171 8 8 2 ICLK
0008 73AEh ICU Interrupt Source Priority Register 174 IPR174 8 8 2 ICLK
0008 73B1h ICU Interrupt Source Priority Register 177 IPR177 8 8 2 ICLK
0008 73B4h ICU Interrupt Source Priority Register 180 IPR180 8 8 2 ICLK
0008 73B7h ICU Interrupt Source Priority Register 183 IPR183 8 8 2 ICLK
0008 73BAh ICU Interrupt Source Priority Register 186 IPR186 8 8 2 ICLK
0008 73D6h ICU Interrupt Source Priority Register 214 IPR214 8 8 2 ICLK
0008 73DAh ICU Interrupt Source Priority Register 218 IPR218 8 8 2 ICLK
0008 73DEh ICU Interrupt Source Priority Register 222 IPR222 8 8 2 ICLK
0008 73E2h ICU Interrupt Source Priority Register 226 IPR226 8 8 2 ICLK
0008 73E6h ICU Interrupt Source Priority Register 230 IPR230 8 8 2 ICLK
0008 73EAh ICU Interrupt Source Priority Register 234 IPR234 8 8 2 ICLK
0008 73EEh ICU Interrupt Source Priority Register 238 IPR238 8 8 2 ICLK
0008 73F2h ICU Interrupt Source Priority Register 242 IPR242 8 8 2 ICLK
0008 73F3h ICU Interrupt Source Priority Register 243 IPR243 8 8 2 ICLK
0008 73F4h ICU Interrupt Source Priority Register 244 IPR244 8 8 2 ICLK
0008 73F5h ICU Interrupt Source Priority Register 245 IPR245 8 8 2 ICLK
0008 73F6h ICU Interrupt Source Priority Register 246 IPR246 8 8 2 ICLK
0008 73F7h ICU Interrupt Source Priority Register 247 IPR247 8 8 2 ICLK
0008 73F8h ICU Interrupt Source Priority Register 248 IPR248 8 8 2 ICLK
0008 73F9h ICU Interrupt Source Priority Register 249 IPR249 8 8 2 ICLK
0008 7500h ICU IRQ Control Register 0 IRQCR0 8 8 2 ICLK
0008 7501h ICU IRQ Control Register 1 IRQCR1 8 8 2 ICLK
0008 7502h ICU IRQ Control Register 2 IRQCR2 8 8 2 ICLK
0008 7503h ICU IRQ Control Register 3 IRQCR3 8 8 2 ICLK
0008 7504h ICU IRQ Control Register 4 IRQCR4 8 8 2 ICLK
0008 7505h ICU IRQ Control Register 5 IRQCR5 8 8 2 ICLK
0008 7506h ICU IRQ Control Register 6 IRQCR6 8 8 2 ICLK
0008 7507h ICU IRQ Control Register 7 IRQCR7 8 8 2 ICLK
0008 7510 h ICU IRQ Pin Digital F ilter Enable Register 0 IRQFLTE0 8 8 2 ICL K
0008 7514h ICU IRQ Pin Digital Filter Setting Register 0 IRQFLTC0 16 16 2 ICLK
0008 7580h ICU Non-Maskable Interrupt Status Register NMISR 8 8 2 ICLK
0008 7581h ICU Non-Maskable Interrupt Enable Register NMIER 8 8 2 ICLK
0008 7582h ICU Non-Maskable Interrupt Status Clear Register NMICLR 8 8 2 ICLK
0008 7583h ICU NMI Pin Int errupt Contro l Register NMICR 8 8 2 ICLK
0008 7590h ICU NMI Pin Digital Filter Enable Register NMIFLTE 8 8 2 ICLK
0008 7594h ICU NMI Pin Digital Filter Setting Register NMIFLTC 8 8 2 ICLK
0008 8000 h CMT Compare Match Timer Start Register 0 CMSTR0 16 16 2 or 3 PCLKB
0008 8002h CMT0 Compare Match Timer Control Register CMCR 16 16 2 or 3 PCLKB
0008 8004h CMT0 Compare Match Timer Counter CMCNT 16 16 2 or 3 PCLKB
0008 8006h CMT0 Compare Match Timer Constant Register CMCOR 16 16 2 or 3 PCL KB
0008 8008h CMT1 Compare Match Timer Control Register CMCR 16 16 2 or 3 PCLKB
0008 800Ah CMT1 Compare Match Timer Counter CMCNT 16 16 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (7/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
R01DS0216EJ0110 Rev.1.10 Page 37 of 131
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RX113 Group 4. I/O Regis ters
0008 800Ch CMT1 Compare Match Timer Constant Register CMCOR 16 16 2 or 3 PCLKB
0008 8010 h CMT Compare Match Timer Start Register1 CMSTR1 16 16 2 or 3 PCLKB
0008 8012h CMT2 Compare Match Timer Control Register CMCR 16 16 2 or 3 PCLKB
0008 8014h CMT2 Compare Match Counter CMCNT 16 16 2 or 3 PCLKB
0008 8016h CMT2 Compare Match Constant Register CMCOR 16 16 2 or 3 PCLKB
0008 8018h CMT3 Compare Match Timer Control Register CMCR 16 16 2 or 3 PCLKB
0008 801Ah CMT3 Compare Ma tch Counter CMCNT 16 1 6 2 or 3 PCLKB
0008 801Ch CMT3 Compare Match Constant Register CMCOR 16 16 2 or 3 PCLKB
0008 8030h IWDT IWDT Refresh Register IWDTRR 8 8 2 or 3 PCLKB
0008 8032h IWDT IWDT Control Register IWDTCR 16 16 2 or 3 PCLKB
0008 8034h IWDT IWDT Status Register IWDTSR 16 16 2 or 3 PCLKB
0008 8036h IWDT IWDT Reset Control Register IWDTRCR 8 8 2 or 3 PCLKB
0008 8038h IWDT IWDT Count Stop Control Register IWDTCSTPR 8 8 2 or 3 PCLKB
0008 8040h R12DA D/A Data Register 0 DADR0 16 16 2 or 3 PCLKB
0008 8042h R12DA D/A Data Register 1 DADR1 16 16 2 or 3 PCLKB
0008 8044h R12DA D/A Control Register DACR 8 8 2 or 3 PCLKB
0008 8045h R12DA DADRm Format Select Register DADPR 8 8 2 or 3 PCLKB
0008 8046h R12DA D/A A/D Synchronous Start Control Register DAADSCR 8 8 2 or 3 PCLKB
0008 8047h R12DA D/A VREF Control Register DAVREFCR 8 8 2 or 3 PCLKB
0008 8200h TMR0 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8201h TMR1 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8202h TMR0 Timer Control/Status Register TCSR 8 8 2 or 3 PCLKB
0008 8203h TMR1 Timer Control/Status Register TCSR 8 8 2 or 3 PCLKB
0008 8204h TMR0 Time Constant Register A TCORA 8 8 2 or 3 PCLK B
0008 8205h TMR1 Time Constant Register A TCORA 8 8*12 or 3 PCLKB
0008 8206h TMR0 Time Constant Register B TCORB 8 8 2 or 3 PCLK B
0008 8207h TMR1 Time Constant Register B TCORB 8 8*12 or 3 PCLKB
0008 8208h TMR0 Timer Counter TCNT 8 8 2 or 3 PCLKB
0008 8209h TMR1 Timer Counter TCNT 8 8*12 or 3 PCLKB
0008 820Ah TMR0 Timer Counter Control Register TCCR 8 8 2 or 3 PCLKB
0008 820Bh TMR1 Timer Counter Control Register TCCR 8 8*12 or 3 PCLKB
0008 820Ch TMR0 Time Count Start Register TCSTR 8 8 2 or 3 PCLKB
0008 8210h TMR2 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8211h TMR3 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8212h TMR2 Timer Control/Status Register TCSR 8 8 2 or 3 PCLKB
0008 8213h TMR3 Timer Control/Status Register TCSR 8 8 2 or 3 PCLKB
0008 8214h TMR2 Time Constant Register A TCORA 8 8 2 or 3 PCLK B
0008 8215h TMR3 Time Constant Register A TCORA 8 8*12 or 3 PCLKB
0008 8216h TMR2 Time Constant Register B TCORB 8 8 2 or 3 PCLK B
0008 8217h TMR3 Time Constant Register B TCORB 8 8*12 or 3 PCLKB
0008 8218h TMR2 Timer Counter TCNT 8 8 2 or 3 PCLKB
0008 8219h TMR3 Timer Counter TCNT 8 8*12 or 3 PCLKB
0008 821Ah TMR2 Timer Control Register TCCR 8 8 2 or 3 PCLKB
0008 821Bh TMR3 Timer Control Register TCCR 8 8*12 or 3 PCLKB
0008 821Ch TMR2 Time Count Start Register TCSTR 8 8 2 or 3 PCLKB
0008 8280h CRC CRC Control Register CRCCR 8 8 2 or 3 PCLKB
0008 8281h CRC CRC Data Input Register CRCDIR 8 8 2 or 3 PCLKB
0008 8282h CRC CRC Data Output Register CRCDOR 16 16 2 or 3 PCLKB
0008 8300h RIIC0 I2C Bus Control Register 1 ICCR1 8 8 2 or 3 PCLKB
0008 8301h RIIC0 I2C Bus Control Register 2 ICCR2 8 8 2 or 3 PCLKB
0008 8302h RIIC0 I2C Bus Mode Register 1 ICMR1 8 8 2 or 3 PCLKB
0008 8303h RIIC0 I2C Bus Mode Register 2 ICMR2 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (8/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
R01DS0216EJ0110 Rev.1.10 Page 38 of 131
Mar 31, 2016
RX113 Group 4. I/O Regis ters
0008 8304h RIIC0 I2C Bus Mode Register 3 ICMR3 8 8 2 or 3 PCLKB
0008 8305h RIIC0 I2C Bus Function Enable Register ICFER 8 8 2 or 3 PCLKB
0008 8306h RIIC0 I2C Bus Status Enable Register ICSER 8 8 2 or 3 PCLKB
0008 8307h RIIC0 I2C Bus Interrupt Enable Register ICIER 8 8 2 or 3 PCLKB
0008 8308h RIIC0 I2C Bus Status Register 1 ICSR1 8 8 2 or 3 PCLKB
0008 8309h RIIC0 I2C Bus Status Register 2 ICSR2 8 8 2 or 3 PCLKB
0008 830A h RIIC0 Slave Ad dress Register L0 SARL0 8 8 2 or 3 PCLKB
0008 830Ah RIIC0 Timeout Internal Counter L TMOCNTL 8 8 2 or 3 PCLKB
0008 830Bh RIIC0 Slave Address Register U0 SARU0 8 8 2 or 3 PCLK B
0008 830Bh RIIC0 Timeout Internal Counter U TMOCNTU 8 8 *22 or 3 PCLKB
0008 830Ch RIIC0 Slave Addr ess Register L1 SARL1 8 8 2 or 3 PCLKB
0008 830Dh RIIC0 Slave Addres s Register U1 SARU1 8 8 2 or 3 PCLKB
0008 830E h RIIC0 Slave Ad dress Register L2 SARL2 8 8 2 or 3 PCLKB
0008 830Fh RIIC0 Slave Address Register U2 SARU2 8 8 2 or 3 PCLKB
0008 8310h RIIC0 I2C Bus Bit Rate Low-Level Register ICBRL 8 8 2 or 3 PCLKB
0008 8311h RIIC0 I2C Bus Bit Rate High-Level Register ICBRH 8 8 2 or 3 PCLKB
0008 8312h RIIC0 I2C Bus Transmit Data Register ICDRT 8 8 2 or 3 PCLKB
0008 8313h RIIC0 I2C Bus Receive Data Register ICDRR 8 8 2 or 3 PCLKB
0008 8380h RSPI0 RSPI Control Register SPCR 8 8 2 or 3 PCLKB
0008 8381h RSPI0 RSPI Slave Select Polarity Register SSLP 8 8 2 or 3 PCLKB
0008 8382h RSPI0 RSPI Pin Cont rol Register SPPCR 8 8 2 or 3 PCLKB
0008 8383h RSPI0 RSPI Status Register SPSR 8 8 2 or 3 PCLKB
0008 8384h RSPI0 RSPI Data Register SPDR 32 16, 32 2 or 3 PCLKB/2ICLK
0008 8388h RSPI0 RSPI Sequence Control Register SPSCR 8 8 2 or 3 PCLKB
0008 8389h RSPI0 RSPI Sequence Status Register SPSSR 8 8 2 or 3 PCLKB
0008 838Ah RSPI0 RSPI Bit Rate Register SPBR 8 8 2 or 3 PCLKB
0008 838Bh RSPI0 RSPI Data Control Register SPDCR 8 8 2 or 3 PCLKB
0008 838Ch RSPI0 RSPI Clock Delay Register SPCKD 8 8 2 or 3 PCLKB
0008 838Dh RSPI0 RSPI Sl ave Select Ne gation Delay Register SSLND 8 8 2 or 3 PCLK B
0008 838Eh RSPI0 RSPI Next-Access Delay Register SPND 8 8 2 or 3 PCLKB
0008 838Fh R SPI0 RSPI Control Register 2 SPCR2 8 8 2 or 3 PCLKB
0008 8390h RSPI0 RSPI Command Register 0 SPCMD0 16 16 2 or 3 PCLKB
0008 8392h RSPI0 RSPI Command Register 1 SPCMD1 16 16 2 or 3 PCLKB
0008 8394h RSPI0 RSPI Command Register 2 SPCMD2 16 16 2 or 3 PCLKB
0008 8396h RSPI0 RSPI Command Register 3 SPCMD3 16 16 2 or 3 PCLKB
0008 8398h RSPI0 RSPI Command Register 4 SPCMD4 16 16 2 or 3 PCLKB
0008 839Ah RSPI0 RSPI Command Register 5 SPCMD5 16 16 2 or 3 PCLKB
0008 839Ch RSPI0 RSPI Command Register 6 SPCMD6 16 16 2 or 3 PCLKB
0008 839Eh RSPI0 RSPI Command Register 7 SPCMD7 16 16 2 or 3 PCLKB
0008 8410h IRDA IrDA Control Register IRCR 8 8 2 or 3 PCLKB
0008 8600h MTU3 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8601h MTU4 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8602h MTU3 Timer Mode Register TMDR 8 8 2 or 3 PCLKB
0008 8603h MTU4 Timer Mode Register TMDR 8 8 2 or 3 PCLKB
0008 8604h MTU3 Timer I/O Control Register H TIORH 8 8 2 or 3 PCLKB
0008 8605h MTU3 Timer I/O Control Register L TIORL 8 8 2 or 3 PCLKB
0008 8606h MTU4 Timer I/O Control Register H TIORH 8 8 2 or 3 PCLKB
0008 8607h MTU4 Timer I/O Control Register L TIORL 8 8 2 or 3 PCLKB
0008 8608h MTU3 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 8609h MTU4 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 860Ah MTU Timer Output Master Enable Registe r TOER 8 8 2 or 3 PCLKB
0008 860Dh MTU Timer Gate Control Register TGCR 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (9/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 860Eh MTU Timer Output Control Registe r 1 TOCR1 8 8 2 or 3 PCLKB
0008 860Fh MTU Timer Output Control Regist er 2 TOCR2 8 8 2 or 3 PCLKB
0008 8610h MTU3 Timer Counter TCNT 16 16 2 or 3 PCLKB
0008 8612h MTU4 Timer Counter TCNT 16 16 2 or 3 PCLKB
0008 8614h MTU Timer Cycle Data Register TCDR 16 16 2 or 3 PCLKB
0008 8616h MTU Timer Dead Time Data Register TDDR 16 16 2 or 3 PCLKB
0008 8618h MTU3 Timer General Regis ter A TGRA 16 16 2 or 3 PCLKB
0008 861Ah MTU3 Timer General Register B TGRB 16 16 2 or 3 PCLKB
0008 861Ch MTU4 Timer General Reg i ster A TGRA 16 16 2 or 3 PCLKB
0008 861Eh MTU4 Timer General Register B TGRB 16 16 2 or 3 PCLKB
0008 8620h MTU Timer Subcounter TCNTS 16 16 2 or 3 PCLKB
0008 8622h MTU Timer Cycle Buffer Register TCBR 16 16 2 or 3 PCLKB
0008 8624h MTU3 Timer General Regis ter C T GRC 16 16 2 or 3 PCLKB
0008 8626h MTU3 Timer General Regis ter D T GRD 16 16 2 or 3 PCLKB
0008 8628h MTU4 Timer General Regis ter C T GRC 16 16 2 or 3 PCLKB
0008 862Ah MTU4 Timer General Register D TGRD 16 16 2 or 3 PCL KB
0008 862Ch MTU3 Timer Status Register TSR 8 8 2 or 3 PCLKB
0008 862Dh MTU4 Timer Status Register TSR 8 8 2 or 3 PCLKB
0008 8630h MTU Timer Interrupt Skipping Set Register TITCR 8 8 2 or 3 PCLKB
0008 8631h MTU Timer Interrupt Skipping Counter TITCNT 8 8 2 or 3 PCLKB
0008 8632h MTU Timer Buffer Transfer Set Register TBTER 8 8 2 or 3 PCLKB
0008 8634h MTU Timer Dead Time Enable Register TDER 8 8 2 or 3 PCLKB
0008 8636h MTU Timer Output Level Buffer Register TOLBR 8 8 2 or 3 PCLKB
0008 8638h MTU3 Timer Buffer Operation Transfer Mode Register TBTM 8 8 2 or 3 PCLKB
0008 8639h MTU4 Timer Buffer Operation Transfer Mode Register TBTM 8 8 2 or 3 PCLKB
0008 8640h MTU4 Timer A/D Converter Start Request Control Register TADCR 16 16 2 or 3 PCL KB
0008 8644h MTU4 Timer A/D Converter Start Request Cycle Set Register A TADCORA 16 16 2 or 3 PCLKB
0008 8646h MTU4 Timer A/D Converter Start Request Cycle Set Register B TADCORB 16 16 2 or 3 PCLKB
0008 8648h MTU4 Timer A/D Converter Start Request Cycle Set Buffer Register A TADCOBRA 16 16 2 or 3 PCLKB
0008 864Ah MTU4 Timer A/D Converter Start Request Cycle Set Buffer Register B TADCOBRB 16 16 2 or 3 PCLKB
0008 8660h MTU Timer Waveform Control Register TWCR 8 8, 16 2 or 3 PCLKB
0008 8680h MTU Timer Start Register TSTR 8 8, 16 2 or 3 PCLKB
0008 8681h MTU Timer Synchronous Register TSYR 8 8, 16 2 or 3 PCLKB
0008 8684h MTU Timer Read/Write Enable Register TRWER 8 8, 16 2 or 3 PCLKB
0008 8690h MTU0 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8691h MTU1 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8692h MTU2 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8693h MTU3 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8694h MTU4 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8695h MTU5 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8700h MTU0 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8701h MTU0 Timer Mode Register TMDR 8 8 2 or 3 PCLKB
0008 8702h MTU0 Timer I/O Control Register H TIORH 8 8 2 or 3 PCLKB
0008 8703h MTU0 Timer I/O Control Register L TIORL 8 8 2 or 3 PCLKB
0008 8704h MTU0 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 8705h MTU0 Timer Status Register TSR 8 8 2 or 3 PCLKB
0008 8706h MTU0 Timer Counter TCNT 16 16 2 or 3 PCLKB
0008 8708h MTU0 Timer General Regis ter A TGRA 16 16 2 or 3 PCLKB
0008 870Ah MTU0 Timer General Register B TGRB 16 16 2 or 3 PCLKB
0008 870Ch MTU0 Timer General Reg i ster C TGRC 16 16 2 or 3 PCLKB
0008 870Eh MTU0 Timer General Register D TGRD 16 16 2 or 3 PCL KB
0008 8720h MTU0 Timer General Regis ter E TGRE 16 16 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (10/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 8722h MTU0 Timer General Regis ter F TGRF 16 16 2 or 3 PCLKB
0008 8724h MTU0 Timer Interrupt Enable Register 2 TIER2 8 8 2 or 3 PCLKB
0008 8726h MTU0 Timer Buffer Operation Transfer Mode Register TBTM 8 8 2 or 3 PCLKB
0008 8780h MTU1 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8781h MTU1 Timer Mode Register TMDR 8 8 2 or 3 PCLKB
0008 8782h MTU1 Timer I/O Control Register TIOR 8 8 2 or 3 PCLKB
0008 8784h MTU1 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 8785h MTU1 Timer Status Register TSR 8 8 2 or 3 PCLKB
0008 8786h MTU1 Timer Counter TCNT 16 16 2 or 3 PCLKB
0008 8788h MTU1 Timer General Regis ter A TGRA 16 16 2 or 3 PCLKB
0008 878Ah MTU1 Timer General Register B TGRB 16 16 2 or 3 PCLKB
0008 8790h MTU1 Timer Input Capture Control Register TICCR 8 8 2 or 3 PCLKB
0008 8800h MTU2 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8801h MTU2 Timer Mode Register TMDR 8 8 2 or 3 PCLKB
0008 8802h MTU2 Timer I/O Control Register TIOR 8 8 2 or 3 PCLKB
0008 8804h MTU2 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 8805h MTU2 Timer Status Register TSR 8 8 2 or 3 PCLKB
0008 8806h MTU2 Timer Counter TCNT 16 16 2 or 3 PCLKB
0008 8808h MTU2 Timer General Regis ter A TGRA 16 16 2 or 3 PCLKB
0008 880Ah MTU2 Timer General Register B TGRB 16 16 2 or 3 PCLKB
0008 8880h MTU5 Timer Counter U TCNTU 16 16 2 or 3 PCLKB
0008 8882h MTU5 Timer General Regis ter U T GRU 16 16 2 or 3 PCLKB
0008 8884h M TU5 Timer Control Register U TCRU 8 8 2 or 3 PCLKB
0008 8886h MTU5 Timer I/O Control Register U TIORU 8 8 2 or 3 PCLKB
0008 8890h MTU5 Timer Counter V TCNTV 16 16 2 or 3 PCLKB
0008 8892h MTU5 Timer General Regis ter V TGRV 16 16 2 or 3 PCLKB
0008 8894h M TU5 Timer Control Register V TCRV 8 8 2 or 3 PCLKB
0008 8896h MTU5 Timer I/O Control Register V TIORV 8 8 2 or 3 PCLKB
0008 88A0h MTU5 Timer Counter W TCNTW 16 16 2 or 3 PCLKB
0008 88A2h MTU5 Timer General Register W TGRW 16 16 2 or 3 PCLKB
0008 88A4h MTU5 Timer Control Register W TCRW 8 8 2 or 3 PCLKB
0008 88A6h MTU5 Timer I/O Control Register W TIORW 8 8 2 or 3 PCLKB
0008 88B2h MTU5 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 88B4h MTU5 Timer Start Register TSTR 8 8 2 or 3 PCLKB
0008 88B6h MTU5 Timer Compare Match Clear Register TCNTCMPCLR 8 8 2 or 3 PCLKB
0008 8900h POE Input Level Control/Status Register 1 ICSR1 16 8, 16 2 or 3 PCLKB
0008 8902 h POE Output Level Control/Status Register 1 OCSR1 16 8, 16 2 or 3 PCLKB
0008 8908h POE Input Level Control/Status Register 2 ICSR2 16 8, 16 2 or 3 PCLKB
0008 890Ah POE Software Port Output Enable Register SPOER 8 8 2 or 3 PCLKB
0008 890Bh POE Port Output Enable Control Register 1 POECR1 8 8 2 or 3 PCLKB
0008 890Ch POE Port Output Enable Control Register 2 POECR2 8 8 2 or 3 PCLKB
0008 890Eh POE Input Level Control/Status Register 3 ICSR3 16 8, 16 2 or 3 PCLKB
0008 9000h S12A D A/D Control Register ADCSR 16 16 2 or 3 PCLKB
0008 9004h S12AD A/D Channel Select Register A ADANSA 16 16 2 or 3 PCLKB
0008 9006h S12AD A/D Channel Select Register A1 ADANSA1 16 16 2 or 3 PCLKB
0008 9008h S12AD A/D-Converted Value Addition Mode Select Register ADADS 16 16 2 or 3 PCLKB
0008 900Ah S12AD A/D-Converted Value Addition Mode Select Register 1 ADADS1 16 16 2 or 3 PCLKB
0008 900Ch S12AD A/D-Converted Value Addition Count Select Register ADADC 8 8 2 or 3 PCLKB
0008 900Eh S12AD A/D Control Extended Regi ster ADCER 16 16 2 or 3 PCLKB
0008 9010h S12AD A/D Start Trigger Select Register ADSTRGR 16 16 2 or 3 PCLKB
0008 9012h S12AD A/D Converted Extended Input Control Register ADEXICR 16 16 2 or 3 PCLKB
0008 9014h S12AD A/D Channel Select Register B ADANSB 16 16 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (11/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 9016h S12AD A/D Channel Select Register B1 ADANSB1 16 16 2 or 3 PCLKB
0008 9018h S12AD A/D Data Duplication Register ADDBLDR 16 16 2 or 3 PCLKB
0008 901Ah S12AD A/D Temperature Sensor Data Register ADTSDR 16 16 2 or 3 PCLKB
0008 901Ch S12AD A/D Internal Reference Voltage Data Register ADOCDR 16 16 2 or 3 PCLKB
0008 9020h S12AD A/D Data Register 0 A DDR0 16 16 2 or 3 PCLKB
0008 9022h S12AD A/D Data Register 1 A DDR1 16 16 2 or 3 PCLKB
0008 9024h S12AD A/D Data Register 2 A DDR2 16 16 2 or 3 PCLKB
0008 9026h S12AD A/D Data Register 3 A DDR3 16 16 2 or 3 PCLKB
0008 9028h S12AD A/D Data Register 4 A DDR4 16 16 2 or 3 PCLKB
0008 902Ah S12AD A/D Data Register 5 ADDR5 16 16 2 or 3 PCLKB
0008 902Ch S12AD A/D Data Register 6 ADDR6 16 16 2 or 3 PCL KB
0008 902Eh S12AD A/D Data Register 7 ADDR7 16 16 2 or 3 PCLKB
0008 9030h S12AD A/D Data Register 8 A DDR8 16 16 2 or 3 PCLKB
0008 9032h S12AD A/D Data Register 9 A DDR9 16 16 2 or 3 PCLKB
0008 9034h S12AD A/D Data Register 10 ADDR10 16 16 2 or 3 PCLK B
0008 9036h S12AD A/D Data Register 11 ADDR11 16 16 2 or 3 PCLKB
0008 9038h S12AD A/D Data Register 12 ADDR12 16 16 2 or 3 PCLK B
0008 903Ah S12AD A/D Da ta Register 13 ADDR13 16 16 2 or 3 PCLKB
0008 903Ch S12AD A/D Data Register 14 ADDR14 16 16 2 or 3 PCLKB
0008 903Eh S12AD A/D Da ta Register 15 ADDR15 16 16 2 or 3 PCLKB
0008 904Ah S12AD A/D Da ta Register 21 ADDR21 16 16 2 or 3 PCLKB
0008 9060h S12AD A/D Sampling State Register 0 ADSSTR0 8 8 2 or 3 PCLKB
0008 9061h S12AD A/D Sampling State Register L ADSSTRL 8 8 2 or 3 PCLKB
0008 9070h S12AD A/D Sampling State Register T ADSSTRT 8 8 2 or 3 PCLKB
0008 9071h S12AD A/D Sampling State Register O ADSSTRO 8 8 2 or 3 PCLKB
0008 9073h S12AD A/D Sampling State Register 1 ADSSTR1 8 8 2 or 3 PCLKB
0008 9074h S12AD A/D Sampling State Register 2 ADSSTR2 8 8 2 or 3 PCLKB
0008 9075h S12AD A/D Sampling State Register 3 ADSSTR3 8 8 2 or 3 PCLKB
0008 9076h S12AD A/D Sampling State Register 4 ADSSTR4 8 8 2 or 3 PCLKB
0008 9077h S12AD A/D Sampling State Register 5 ADSSTR5 8 8 2 or 3 PCLKB
0008 9078h S12AD A/D Sampling State Register 6 ADSSTR6 8 8 2 or 3 PCLKB
0008 9079h S12AD A/D Sampling State Register 7 ADSSTR7 8 8 2 or 3 PCLKB
0008 907Ch S12AD A/D High-Side Reference Voltage Control Register ADHVREFCNT 8 8 2 or 3 PCLKB
0008 9080h S12AD A/D Sampling State Register 21 ADSSTR21 8 8 2 or 3 PCLKB
0008 A000h SCI0 Serial Mode Register SMR 8 8 2 or 3 PCLKB
0008 A001h SCI0 Bit Rate Register BRR 8 8 2 or 3 PCLKB
0008 A002h SCI0 Serial Control Register SCR 8 8 2 or 3 PCLKB
0008 A003h SCI0 Transmit Data Register TDR 8 8 2 or 3 PCLKB
0008 A004h SCI0 Serial Status Register SSR 8 8 2 or 3 PCLKB
0008 A005h SCI0 Receive Data Register RDR 8 8 2 or 3 PCLKB
0008 A006h SCI0 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB
0008 A007h SCI0 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB
0008 A008h SCI0 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB
0008 A009h SCI0 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB
0008 A00Ah SCI0 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCL KB
0008 A00Bh SCI0 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCL KB
0008 A00Ch SCI0 I2C Status Register SISR 8 8 2 or 3 PCLKB
0008 A00Dh SCI0 SPI Mode Register SPMR 8 8 2 or 3 PCLKB
0008 A020h SCI1 Serial Mode Register SMR 8 8 2 or 3 PCLKB
0008 A021h SCI1 Bit Rate Register BRR 8 8 2 or 3 PCLKB
0008 A022h SCI1 Serial Control Register SCR 8 8 2 or 3 PCLKB
0008 A023h SCI1 Transmit Data Register TDR 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (12/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 A024h SCI1 Serial Status Register SSR 8 8 2 or 3 PCLKB
0008 A025h SCI1 Receive Data Register RDR 8 8 2 or 3 PCLKB
0008 A026h SCI1 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB
0008 A027h SCI1 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB
0008 A028h SCI1 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB
0008 A029h SCI1 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB
0008 A02Ah SCI1 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCL KB
0008 A02Bh SCI1 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCL KB
0008 A02Ch SCI1 I2C Status Register SISR 8 8 2 or 3 PCLKB
0008 A02Dh SCI1 SPI Mode Register SPMR 8 8 2 or 3 PCLKB
0008 A040h SCI2 Serial Mode Register SMR 8 8 2 or 3 PCLKB
0008 A041h SCI2 Bit Rate Register BRR 8 8 2 or 3 PCLKB
0008 A042h SCI2 Serial Control Register SCR 8 8 2 or 3 PCLKB
0008 A043h SCI2 Transmit Data Register TDR 8 8 2 or 3 PCLKB
0008 A044h SCI2 Serial Status Register SSR 8 8 2 or 3 PCLKB
0008 A045h SCI2 Receive Data Register RDR 8 8 2 or 3 PCLKB
0008 A046h SCI2 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB
0008 A047h SCI2 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB
0008 A048h SCI2 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB
0008 A049h SCI2 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB
0008 A04Ah SCI2 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCL KB
0008 A04Bh SCI2 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCL KB
0008 A04Ch SCI2 I2C Status Register SISR 8 8 2 or 3 PCLKB
0008 A04Dh SCI2 SPI Mode Register SPMR 8 8 2 or 3 PCLKB
0008 A0A0h SCI5 Serial Mode Register SMR 8 8 2 or 3 PCLKB
0008 A0A1h SCI5 Bit Rate Register BRR 8 8 2 or 3 PCLKB
0008 A0A2h SCI5 Serial Control Register SCR 8 8 2 or 3 PCL KB
0008 A0A3h SCI5 Transmit Data Register TDR 8 8 2 or 3 PCLKB
0008 A0A4h SCI5 Serial Status Register SSR 8 8 2 or 3 PCLKB
0008 A0A5h SCI5 Receive Data Register RDR 8 8 2 or 3 PCLKB
0008 A0A6h SCI5 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB
0008 A0A7h SCI5 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB
0008 A0A8h SCI5 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB
0008 A0A9h SCI5 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB
0008 A0AAh SCI5 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCLKB
0008 A0ABh SCI5 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCLKB
0008 A0ACh SCI5 I2C Status Register SISR 8 8 2 or 3 PCLKB
0008 A0ADh SCI5 SPI Mode Register SPMR 8 8 2 or 3 PCLKB
0008 A0C0h SCI6 Serial Mode Register SMR 8 8 2 or 3 PCLKB
0008 A0C1h SCI6 Bit Rate Register BRR 8 8 2 or 3 PCLKB
0008 A0C2h SCI6 Serial Control Register SCR 8 8 2 or 3 PCLK B
0008 A0C3h SCI6 Transmit Data Register TDR 8 8 2 or 3 PCLKB
0008 A0C4h SCI6 Serial Status Register SSR 8 8 2 or 3 PCLKB
0008 A0C5h SCI6 Receive Data Register RDR 8 8 2 or 3 PCLKB
0008 A0C6h SCI6 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB
0008 A0C7h SCI6 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB
0008 A0C8h SCI6 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB
0008 A0C9h SCI6 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB
0008 A0CAh SCI6 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCLKB
0008 A0CBh SCI6 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCLKB
0008 A0CCh SCI6 I2C Status Register SISR 8 8 2 or 3 PCLKB
0008 A0CDh SCI6 SPI Mode Register SPMR 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (13/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 A100h SCI8 Serial Mode Register SMR 8 8 2 or 3 PCLKB
0008 A101h SCI8 Bit Rate Register BRR 8 8 2 or 3 PCLKB
0008 A102h SCI8 Serial Control Register SCR 8 8 2 or 3 PCLKB
0008 A103h SCI8 Transmit Data Register TDR 8 8 2 or 3 PCLKB
0008 A104h SCI8 Serial Status Register SSR 8 8 2 or 3 PCLKB
0008 A105h SCI8 Receive Data Register RDR 8 8 2 or 3 PCLKB
0008 A106h SCI8 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB
0008 A107h SCI8 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB
0008 A108h SCI8 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB
0008 A109h SCI8 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB
0008 A10Ah SCI8 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCL KB
0008 A10Bh SCI8 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCL KB
0008 A10Ch SCI8 I2C Status Register SISR 8 8 2 or 3 PCLKB
0008 A10Dh SCI8 SPI Mode Register SPMR 8 8 2 or 3 PCLKB
0008 A120h SCI9 Serial Mode Register SMR 8 8 2 or 3 PCLKB
0008 A121h SCI9 Bit Rate Register BRR 8 8 2 or 3 PCLKB
0008 A122h SCI9 Serial Control Register SCR 8 8 2 or 3 PCLKB
0008 A123h SCI9 Transmit Data Register TDR 8 8 2 or 3 PCLKB
0008 A124h SCI9 Serial Status Register SSR 8 8 2 or 3 PCLKB
0008 A125h SCI9 Receive Data Register RDR 8 8 2 or 3 PCLKB
0008 A126h SCI9 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB
0008 A127h SCI9 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB
0008 A128h SCI9 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB
0008 A129h SCI9 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB
0008 A12Ah SCI9 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCL KB
0008 A12Bh SCI9 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCL KB
0008 A12Ch SCI9 I2C Status Register SISR 8 8 2 or 3 PCLKB
0008 A12Dh SCI9 SPI Mode Register SPMR 8 8 2 or 3 PCLKB
0008 A500h SSI0 Control Register SSICR 32 32 2 or 3 PCLKB
0008 A504h SSI0 Status Register SSISR 32 32 2 or 3 PCLKB
0008 A510h SSI0 FIFO Control Register SSIFCR 32 32 2 or 3 PCLKB
0008 A514h SSI0 FIFO Status Register SSIFSR 32 32 2 or 3 PCLKB
0008 A518h SSI0 Transmit FIFO Data Register SSIFTDR 32 32 2 or 3 PCLKB
0008 A51Ch SSI0 Receive FIFO Data Register SSIFRDR 32 32 2 or 3 PCLKB
0008 A520h SSI0 TDM Mode Register SSITDMR 32 32 2 or 3 PCLKB
0008 B000h CAC CAC Control Register 0 CACR0 8 8 2 or 3 PCLKB
0008 B001h CAC CAC Control Register 1 CACR1 8 8 2 or 3 PCLKB
0008 B002h CAC CAC Control Register 2 CACR2 8 8 2 or 3 PCLKB
0008 B003h CAC CAC Interrupt Requ est Ena bl e Re gi ste r CAICR 8 8 2 or 3 PCLKB
0008 B004h CAC CAC Status Register CASTR 8 8 2 or 3 PCLKB
0008 B006h CAC CAC Upper-Limit Value Setting Register CAULVR 16 16 2 or 3 PCLKB
0008 B008h CAC CAC Lower-Limit Value Setting Register CALLVR 16 16 2 or 3 PCLKB
0008 B00Ah CAC CAC Counter Buffer Register CACNTBR 16 16 2 or 3 PCLKB
0008 B080h DOC DOC Control Register DOCR 8 8 2 or 3 PCLKB
0008 B082h DOC DOC Data Input Register DODIR 16 16 2 or 3 PCLKB
0008 B084h DOC DOC Data Setting Register DODSR 16 16 2 or 3 PCLK B
0008 B100h ELC Event Link Control Register ELCR 8 8 2 or 3 PCLKB
0008 B102h ELC Event Link Setting Register 1 ELSR1 8 8 2 or 3 PCLKB
0008 B103h ELC Event Link Setting Register 2 ELSR2 8 8 2 or 3 PCLKB
0008 B104h ELC Event Link Setting Register 3 ELSR3 8 8 2 or 3 PCLKB
0008 B105h ELC Event Link Setting Register 4 ELSR4 8 8 2 or 3 PCLKB
0008 B108h ELC Event Link Setting Register 7 ELSR7 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (14/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 B10Bh ELC Event Link Setting Register 10 ELSR10 8 8 2 or 3 PCLKB
0008 B10Dh ELC Event Link Setting Register 12 ELSR12 8 8 2 or 3 PCLKB
0008 B10Fh ELC Event Link Setting Register 14 ELSR14 8 8 2 or 3 PCLKB
0008 B110h ELC Event Link Setting Register 15 ELSR15 8 8 2 or 3 PCLKB
0008 B112h ELC Event Link Setting Register 17 ELSR17 8 8 2 or 3 PCLKB
0008 B113h ELC Event Link Setting Register 18 ELSR18 8 8 2 or 3 PCLKB
0008 B114h ELC Event Link Setting Register 19 ELSR19 8 8 2 or 3 PCLKB
0008 B115h ELC Event Link Setting Register 20 ELSR20 8 8 2 or 3 PCLKB
0008 B117h ELC Event Link Setting Register 22 ELSR22 8 8 2 or 3 PCLKB
0008 B119h ELC Event Link Setting Register 24 ELSR24 8 8 2 or 3 PCLKB
0008 B11Ah ELC Event Link Setting Register 25 ELSR25 8 8 2 or 3 PCLKB
0008 B11Fh ELC Event Link Option Setting Register A ELOPA 8 8 2 or 3 PCLKB
0008 B120h ELC Event Link Option Setting Register B ELOPB 8 8 2 or 3 PCLKB
0008 B121h ELC Event Link Option Setting Register C ELOPC 8 8 2 or 3 PCLKB
0008 B122h ELC Event Link Option Setting Register D ELOPD 8 8 2 or 3 PCLKB
0008 B123h ELC Port Group Setting Register 1 PGR1 8 8 2 or 3 PCLKB
0008 B125h ELC Port Group Control Register 1 PGC1 8 8 2 or 3 PCLKB
0008 B127h ELC Port Buffer Register 1 PDBF1 8 8 2 or 3 PCLKB
0008 B129h ELC Event Link Port Setting Register 0 PEL0 8 8 2 or 3 PCLKB
0008 B12Ah ELC Event Link Port Setting Register 1 PEL1 8 8 2 or 3 PCLKB
0008 B12Dh ELC Event Link Software Event Generation Register ELSEGR 8 8 2 or 3 PCLKB
0008 B300h SCI12 Serial Mode Register SMR 8 8 2 or 3 PCLKB
0008 B301h SCI12 Bit Rate Register BRR 8 8 2 or 3 PCLKB
0008 B302h SCI12 Serial Control Register SCR 8 8 2 or 3 PCLKB
0008 B303h SCI12 Transmit Data Register TDR 8 8 2 or 3 PCLKB
0008 B304h SCI12 Serial Status Register SSR 8 8 2 or 3 PCLKB
0008 B305h SCI12 Receive Data Register RDR 8 8 2 or 3 PCLKB
0008 B306h SCI12 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB
0008 B307h SCI12 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB
0008 B308h SCI12 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB
0008 B309h SCI12 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCL KB
0008 B30Ah SCI12 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCLKB
0008 B30Bh SCI12 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCLKB
0008 B30Ch SCI12 I2C Status Register SISR 8 8 2 or 3 PCLKB
0008 B30Dh SCI12 SPI Mode Register SPMR 8 8 2 or 3 PCLKB
0008 B320h SCI12 Extended Serial Mode Enable Register ESMER 8 8 2 or 3 PCLKB
0008 B321h SCI12 Control Register 0 CR0 8 8 2 or 3 PCLKB
0008 B322h SCI12 Control Register 1 CR1 8 8 2 or 3 PCLKB
0008 B323h SCI12 Control Register 2 CR2 8 8 2 or 3 PCLKB
0008 B324h SCI12 Control Register 3 CR3 8 8 2 or 3 PCLKB
0008 B325h SCI12 Port Control Register PCR 8 8 2 or 3 PCLKB
0008 B326h SCI12 Interrupt Control Register ICR 8 8 2 or 3 PCLKB
0008 B327h SCI12 Status Register STR 8 8 2 or 3 PCLKB
0008 B328h SCI12 Status Clear Register STCR 8 8 2 or 3 PCLKB
0008 B329h SCI12 Control Field 0 Data Register CF0DR 8 8 2 or 3 PCLKB
0008 B32Ah SCI12 Control Field 0 Compare Enable Register CF0CR 8 8 2 or 3 PCLKB
0008 B32Bh SCI12 Control Field 0 Receive Data Register CF0RR 8 8 2 or 3 PCLKB
0008 B32Ch SCI12 Primary Control Field 1 Data Register PCF1DR 8 8 2 or 3 PCLKB
0008 B32Dh SCI12 Secondary Control Field 1 Data Register SCF1DR 8 8 2 or 3 PCLKB
0008 B32Eh SCI12 Control Field 1 Compare Enable Register CF1CR 8 8 2 or 3 PCLKB
0008 B32Fh SCI12 Control Field 1 Receive Data Register CF1RR 8 8 2 or 3 PCLKB
0008 B330h SCI12 Timer Control Register TCR 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (15/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 B331h SCI12 Timer Mode Register TMR 8 8 2 or 3 PCLKB
0008 B332h SCI12 Timer Prescaler Register TPRE 8 8 2 or 3 PCLKB
0008 B333h SCI12 Timer Count Register TCNT 8 8 2 or 3 PCLKB
0008 C000h PORT0 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C001h PORT1 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C002h PORT2 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C003h PORT3 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C004h PORT4 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C005h PORT5 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C009h PORT9 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C00Ah PORTA Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C00Bh PORTB Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C00Ch PORTC Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C00Dh PORTD Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C00Eh PORTE Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C00Fh PORTF Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C012h PORTJ Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C020h PORT0 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C021h PORT1 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C022h PORT2 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C023h PORT3 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C024h PORT4 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C025h PORT5 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C029h PORT9 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C02Ah PORTA Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C02Bh PORTB Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C02Ch PORTC Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C02Dh PORTD Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C02Eh PORTE Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C02Fh PORTF Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C032h PORTJ Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C040h PORT0 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C041h PORT1 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C042h PORT2 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C043h PORT3 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C044h PORT4 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C045h PORT5 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C049h PORT9 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C04Ah PORTA Port Input Data Register PI DR 8 8 3 or 4 PCLKB cycles
when reading,
2 or 3 PCLKB cycles
when writing
Table 4.1 List of I/O Registers (Address Order) (16/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 C04Bh PORTB Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when reading,
2 or 3 PCLKB cycles
when writing
0008 C04Ch PORTC Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C04Dh PORTD Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C04Eh PORTE Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when reading,
2 or 3 PCLKB cycles
when writing
0008 C04Fh PORTF Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C051h PORTH Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C052h PORTJ Port Input Data Register PIDR 8 8 3 or 4 PCL KB cycle s
when reading,
2 or 3 PCLKB cycles
when writing
0008 C060h PORT0 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C061h PORT1 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C062h PORT2 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C063h PORT3 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C064h PORT4 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C065h PORT5 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C069h PORT9 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C06Ah PORTA Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C06Bh PORTB Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C06Ch PORTC Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C06Dh PORTD Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C06Eh PORTE Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C06Fh PORTF Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C071h PORTH Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C072h PORTJ Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C080h PORT0 Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C081h PORT0 Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C082h PORT1 Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C083h PORT1 Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C084h PORT2 Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C085h PORT2 Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C086h PORT3 Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C08Ah PORT5 Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C08Bh PORT5 Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C094h PORTA Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C095h PORTA Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C096h PORTB Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C097h PORTB Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C098h PORTC Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C099h PORTC Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C09Ch PORTE Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C09Dh PORTE Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C0A4h PORTJ Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C0C0h PORT0 Pull-Up Control Register PCR 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (17/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 C0C1h PORT1 Pull-Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C0C2h PORT2 Pull-Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C0C3h PORT3 Pull-Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C0C5h PORT5 Pull-Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C0CAh PORTA Pull-Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C0CBh PORTB Pull- Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C0CCh PORTC Pull-Up Contro l Register PCR 8 8 2 or 3 PCLKB
0008 C0CDh PORTD Pull-Up Contro l Register PCR 8 8 2 or 3 PCLKB
0008 C0CEh PORTE Pull- Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C0CFh PORTF Pull-Up Co ntrol Register PCR 8 8 2 or 3 PCLKB
0008 C0D2h PORTJ Pull-Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C11Fh M PC Write-Protect Register PWPR 8 8 2 or 3 PCLKB
0008 C121h PORT Port Switching Register A PSRA 8 8 2 or 3 PCLKB
0008 C142h MPC P02 Pin Function Control Register P02PFS 8 8 2 or 3 PCLKB
0008 C144h MPC P04 Pin Function Control Register P04PFS 8 8 2 or 3 PCLKB
0008 C147h MPC P07 Pin Function Control Register P07PFS 8 8 2 or 3 PCLKB
0008 C148h MPC P10 Pin Function Control Register P10PFS 8 8 2 or 3 PCLKB
0008 C149h MPC P11 Pin Function Control Register P11PFS 8 8 2 or 3 PCLKB
0008 C14Ah MPC P12 Pin Function Control Register P12PFS 8 8 2 or 3 PCLKB
0008 C14Bh MPC P13 Pin Function Control Register P13PFS 8 8 2 or 3 PCLKB
0008 C14Ch MPC P14 Pin Function Control Register P14PFS 8 8 2 or 3 PCLKB
0008 C14Dh MPC P15 Pin Function Control Register P15PFS 8 8 2 or 3 PCLKB
0008 C14Eh MPC P16 Pin Function Control Register P16PFS 8 8 2 or 3 PCLKB
0008 C14Fh MPC P17 Pin Function Control Register P17PFS 8 8 2 or 3 PCLKB
0008 C150h MPC P20 Pin Function Control Register P20PFS 8 8 2 or 3 PCLKB
0008 C151h MPC P21 Pin Function Control Register P21PFS 8 8 2 or 3 PCLKB
0008 C152h MPC P22 Pin Function Control Register P22PFS 8 8 2 or 3 PCLKB
0008 C153h MPC P23 Pin Function Control Register P23PFS 8 8 2 or 3 PCLKB
0008 C154h MPC P24 Pin Function Control Register P24PFS 8 8 2 or 3 PCLKB
0008 C155h MPC P25 Pin Function Control Register P25PFS 8 8 2 or 3 PCLKB
0008 C156h MPC P26 Pin Function Control Register P26PFS 8 8 2 or 3 PCLKB
0008 C157h MPC P27 Pin Function Control Register P27PFS 8 8 2 or 3 PCLKB
0008 C158h MPC P30 Pin Function Control Register P30PFS 8 8 2 or 3 PCLKB
0008 C159h MPC P31 Pin Function Control Register P31PFS 8 8 2 or 3 PCLKB
0008 C15Ah MPC P32 Pin Function Control Register P32PFS 8 8 2 or 3 PCLKB
0008 C160h MPC P40 Pin Function Control Register P40PFS 8 8 2 or 3 PCLKB
0008 C161h MPC P41 Pin Function Control Register P41PFS 8 8 2 or 3 PCLKB
0008 C162h MPC P42 Pin Function Control Register P42PFS 8 8 2 or 3 PCLKB
0008 C163h MPC P43 Pin Function Control Register P43PFS 8 8 2 or 3 PCLKB
0008 C164h MPC P44 Pin Function Control Register P44PFS 8 8 2 or 3 PCLKB
0008 C166h MPC P46 Pin Function Control Register P46PFS 8 8 2 or 3 PCLKB
0008 C168h MPC P50 Pin Function Control Register P50PFS 8 8 2 or 3 PCLKB
0008 C169h MPC P51 Pin Function Control Register P51PFS 8 8 2 or 3 PCLKB
0008 C16Ah MPC P52 Pin Function Control Register P52PFS 8 8 2 or 3 PCLKB
0008 C16Bh MPC P53 Pin Function Control Register P53PFS 8 8 2 or 3 PCLKB
0008 C16Ch MPC P54 Pin Function Control Register P54PFS 8 8 2 or 3 PCLKB
0008 C16Dh MPC P55 Pin Function Control Register P55PFS 8 8 2 or 3 PCLKB
0008 C16Eh MPC P56 Pin Function Control Register P56PFS 8 8 2 or 3 PCLKB
0008 C188h MPC P90 Pin Function Control Register P90PFS 8 8 2 or 3 PCLKB
0008 C189h MPC P91 Pin Function Control Register P91PFS 8 8 2 or 3 PCLKB
0008 C18Ah MPC P92 Pin Function Control Register P92PFS 8 8 2 or 3 PCLKB
0008 C190h MPC PA0 Pin Function Control Register PA0PFS 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (18/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 C191h MPC PA1 Pin Function Control Register PA1PFS 8 8 2 or 3 PCLKB
0008 C192h MPC PA2 Pin Function Control Register PA2PFS 8 8 2 or 3 PCLKB
0008 C193h MPC PA3 Pin Function Control Register PA3PFS 8 8 2 or 3 PCLKB
0008 C194h MPC PA4 Pin Function Control Register PA4PFS 8 8 2 or 3 PCLKB
0008 C195h MPC PA5 Pin Function Control Register PA5PFS 8 8 2 or 3 PCLKB
0008 C196h MPC PA6 Pin Function Control Register PA6PFS 8 8 2 or 3 PCLKB
0008 C197h MPC PA7 Pin Function Control Register PA7PFS 8 8 2 or 3 PCLKB
0008 C198h MPC PB0 Pin Function Control Register PB0PFS 8 8 2 or 3 PCLKB
0008 C199h MPC PB1 Pin Function Control Register PB1PFS 8 8 2 or 3 PCLKB
0008 C19Ah MPC PB2 Pin Function Control Register PB2PFS 8 8 2 or 3 PCLKB
0008 C19Bh MPC PB3 Pin Function Control Register PB3PFS 8 8 2 or 3 PCLKB
0008 C19Ch MPC PB4 Pin Function Control Register PB4PFS 8 8 2 or 3 PCLKB
0008 C19Dh MPC PB5 Pin Function Control Register PB5PFS 8 8 2 or 3 PCLKB
0008 C19Eh MPC PB6 Pin Function Control Register PB6PFS 8 8 2 or 3 PCLKB
0008 C19Fh MPC PB7 Pin Function Control Register PB7PFS 8 8 2 or 3 PCLKB
0008 C1A0h MPC PC0 Pin Function Control Register PC0PFS 8 8 2 or 3 PCLKB
0008 C1A1h MPC PC1 Pin Function Control Register PC1PFS 8 8 2 or 3 PCLKB
0008 C1A2h MPC PC2 Pin Function Control Register PC2PFS 8 8 2 or 3 PCLKB
0008 C1A3h MPC PC3 Pin Function Control Register PC3PFS 8 8 2 or 3 PCLKB
0008 C1A4h MPC PC4 Pin Function Control Register PC4PFS 8 8 2 or 3 PCLKB
0008 C1A5h MPC PC5 Pin Function Control Register PC5PFS 8 8 2 or 3 PCLKB
0008 C1A6h MPC PC6 Pin Function Control Register PC6PFS 8 8 2 or 3 PCLKB
0008 C1A7h MPC PC7 Pin Function Control Register PC7PFS 8 8 2 or 3 PCLKB
0008 C1A8h MPC PD0 Pin Function Control Register PD0PFS 8 8 2 or 3 PCLKB
0008 C1A9h MPC PD1 Pin Function Control Register PD1PFS 8 8 2 or 3 PCLKB
0008 C1AAh MPC PD2 Pin Fu nction Contr ol Register PD2PFS 8 8 2 or 3 PCLKB
0008 C1ABh MPC PD3 Pin Fu nction Contr ol Register PD3PFS 8 8 2 or 3 PCLKB
0008 C1ACh MPC PD4 Pin Functio n Control Register PD4PFS 8 8 2 or 3 PCLKB
0008 C1B0h MPC PE0 Pin Function Control Register PE0PFS 8 8 2 or 3 PCLKB
0008 C1B1h MPC PE1 Pin Function Control Register PE1PFS 8 8 2 or 3 PCLKB
0008 C1B2h MPC PE2 Pin Function Control Register PE2PFS 8 8 2 or 3 PCLKB
0008 C1B3h MPC PE3 Pin Function Control Register PE3PFS 8 8 2 or 3 PCLKB
0008 C1B4h MPC PE4 Pin Function Control Register PE4PFS 8 8 2 or 3 PCLKB
0008 C1B5h MPC PE5 Pin Function Control Register PE5PFS 8 8 2 or 3 PCLKB
0008 C1B6h MPC PE6 Pin Function Control Register PE6PFS 8 8 2 or 3 PCLKB
0008 C1B7h MPC PE7 Pin Function Control Register PE7PFS 8 8 2 or 3 PCLKB
0008 C1BE h MPC PF6 Pin F unction Control Register PF6PFS 8 8 2 or 3 PCLKB
0008 C1BFh MPC PF7 Pin Function Control Register PF7PFS 8 8 2 or 3 PCLKB
0008 C1D0h MPC PJ0 Pin Function Control Register PJ0PFS 8 8 2 or 3 PCLKB
0008 C1D2h MPC PJ2 Pin Function Control Register PJ2PFS 8 8 2 or 3 PCLKB
0008 C1D3h MPC PJ3 Pin Function Control Register PJ3PFS 8 8 2 or 3 PCLKB
0008 C1D6h MPC PJ6 Pin Function Control Register PJ6PFS 8 8 2 or 3 PCLKB
0008 C1D7h MPC PJ7 Pin Function Control Register PJ7PFS 8 8 2 or 3 PCLKB
0008 C290h SYSTEM Reset Status Register 0 RSTSR0 8 8 4 or 5 PCLKB
0008 C291h SYSTEM Reset Status Register 1 RSTSR1 8 8 4 or 5 PCLKB
0008 C293h SYSTEM Main Clock Oscillator Forced Oscillation Control Register MOFCR 8 8 4 or 5 PCLK B
0008 C297h SYSTEM Voltage Monitoring Circuit Control Register LVCMPCR 8 8 4 or 5 PCLKB
0008 C298h SYSTEM Voltage Detection Level Select Register LVDLVLR 8 8 4 or 5 PCLKB
0008 C29Ah SYSTEM Voltage Monitoring 1 Circuit Control Register 0 LVD1CR0 8 8 4 or 5 PCLKB
0008 C29Bh SYSTEM Voltage Monitoring 2 Circuit Control Register 0 LVD2CR0 8 8 4 or 5 PCLKB
0008 C400h RTC 64-Hz Counter R64CNT 8 8 2 or 3 PCLKB
0008 C402h RTC Second Counter RSECCNT 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (19/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
0008 C402h RTC Binary Counter 0 BCNT0 8 8 2 or 3 PCLKB
0008 C404h RTC Minute Counter RMINCNT 8 8 2 or 3 PCLKB
0008 C404h RTC Binary Counter 1 BCNT1 8 8 2 or 3 PCLKB
0008 C406h RTC Hour Counter RHRCNT 8 8 2 or 3 PCLKB
0008 C406h RTC Binary Counter 2 BCNT2 8 8 2 or 3 PCLKB
0008 C408h RTC Day-Of-Week Counter RWKCNT 8 8 2 or 3 PCLKB
0008 C408h RTC Binary Counter 3 BCNT3 8 8 2 or 3 PCLKB
0008 C40Ah RTC Date Counter RDAYCNT 8 8 2 or 3 PCLKB
0008 C40Ch RTC Month Counter RMONCNT 8 8 2 or 3 PCLKB
0008 C40Eh RTC Year Counter RYRCNT 16 16 2 or 3 PCLKB
0008 C410h RTC Second Alarm Register RSECAR 8 8 2 or 3 PCLKB
0008 C410h RTC Binary Counter 0 Alarm Register BCNT0AR 8 8 2 or 3 PCLKB
0008 C412h RTC Minute Alarm Register RMINAR 8 8 2 or 3 PCLKB
0008 C412h RTC Binary Counter 1 Alarm Register BCNT1AR 8 8 2 or 3 PCLKB
0008 C414h RTC Hour Alarm Registe r RHRAR 8 8 2 or 3 PCLKB
0008 C414h RTC Binary Counter 2 Alarm Register BCNT2AR 8 8 2 or 3 PCLKB
0008 C416h RTC Day-of-Week Alarm Register RWKAR 8 8 2 or 3 PCLKB
0008 C416h RTC Binary Counter 3 Alarm Register BCNT3AR 8 8 2 or 3 PCLKB
0008 C418h RTC Date Alarm Register RDAYAR 8 8 2 or 3 PCLKB
0008 C418h RTC Binary Counter 0 Alarm Enable Register BCNT0AER 8 8 2 or 3 PCLKB
0008 C41Ah RTC Month Alarm Register RMONAR 8 8 2 or 3 PCLKB
0008 C41Ah RTC Binary Counter 1 Alarm Enable Register BCNT1AER 8 8 2 or 3 PCLKB
0008 C41Ch RTC Year Alarm Register RYRAR 16 16 2 or 3 PCLKB
0008 C41Ch RTC Binary Counter 2 Alarm Enable Register BCNT2AER 16 16 2 or 3 PCLKB
0008 C41Eh RTC Year Alarm Enable Register RYRAREN 8 8 2 or 3 PCLKB
0008 C41Eh RTC Binary Counter 3 Alarm Enable Register BCNT3AER 8 8 2 or 3 PCLKB
0008 C422h RTC RTC Control Register 1 RCR1 8 8 2 or 3 PCLKB
0008 C424h RTC RTC Control Register 2 RCR2 8 8 2 or 3 PCLKB
0008 C426h RTC RTC Control Register 3 RCR3 8 8 2 or 3 PCLKB
0008 C42Eh RTC Time Error Adjustment Register RADJ 8 8 2 or 3 PCLKB
0008 C580h CMPB Comparator B Control Register 1 CPBCNT1 8 8 2 or 3 PCLKB
0008 C581h CMPB Comparator B Control Register 2 CPBCNT2 8 8 2 or 3 PCLKB
0008 C582h CMPB Comparator B Flag Register CPBFLG 8 8 2 or 3 PCLKB
0008 C583h CMPB Comparator B Interrupt Control Register CPBINT 8 8 2 or 3 PCLKB
0008 C584h CMPB Comparator B Filter Select Register CPBF 8 8 2 or 3 PCLKB
0008 C585h CMPB Comparator B Mode Select Register CPBMD 8 8 2 or 3 PCLKB
0008 C586h CMPB Comparator B Reference Input Voltage Select Register CPBREF 8 8 2 or 3 PCLKB
0008 C587h CMPB Comparator B Output Control Register CPBOCR 8 8 2 or 3 PCLKB
000A 0000h USB0 System Configuration Control Register SYSCFG 16 16 3 or 4 PCLKB
000A 0004h USB0 System Configuration Status Register 0 SYSSTS0 16 16 9 PCLK or more
000A 0008 h USB0 Device State Control Regist er 0 DVSTCTR0 16 16 9 PCLK or more
000A 0014 h USB0 CFIFO Port Register CFIFO 16 16 3 or 4 PCLKB
000A 0018h USB0 D0FIFO Port Register D0FIFO 16 16 3 or 4 PCLKB
000A 001Ch USB 0 D1FIFO P ort Register D1FIFO 16 16 3 or 4 PCLKB
000A 0020h USB0 CFIFO Port Select Register CFIFOSEL 16 16 3 or 4 PCLKB
000A 0028h USB0 D0FIFO P ort Select Register D0FIFOSEL 16 16 3 or 4 PCLKB
000A 002Ch USB 0 D1FIFO P ort Select Register D1FIFOSEL 16 16 3 or 4 PCLK B
000A 0022h USB0 CFIFO Port Control Register CFIFOCTR 16 16 3 or 4 PCLKB
000A 002Ah USB0 D0FIFO Port Control Register D0FIFOCTR 16 16 3 or 4 PCLKB
000A 002Eh USB0 D1FIFO Port Control Register D1FIFOCTR 16 16 3 or 4 PCLKB
000A 0030h USB0 Interrupt Enable Register 0 INTENB0 16 16 9 PCLKB or more
000A 0032h USB0 Interrupt Enable Register 1 INTENB1 16 16 9 PCLKB or more
Table 4.1 List of I/O Registers (Address Order) (20/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
000A 0036h USB0 BRDY Interrupt Enable Register BRDYENB 16 16 9 PCLKB or more
000A 0038h USB0 NRDY Interrupt Enable Register NRDYENB 16 16 9 PCLK B or more
000A 003Ah USB0 BEMP Interrupt Enable Register BEMPENB 16 16 9 PCLKB or more
000A 003Ch USB0 SOF Output Configuration Register SOFCFG 16 16 9 PCLKB or more
000A 0040h USB0 Interrupt Status Register 0 INTSTS0 16 16 9 PCLKB or more
000A 0042h USB0 Interrupt Status Register 1 INTSTS1 16 16 9 PCLKB or more
000A 0046h USB0 BRDY Interrupt Status Register BRDYSTS 16 16 9 PCLKB or more
000A 0048h USB0 NRDY Interrupt Status Register NRDYSTS 16 16 9 PCLKB or mor e
000A 004Ah USB0 BEMP Interrupt Status Register BEMPSTS 16 16 9 PCLKB or more
000A 004Ch USB0 Frame Number Register FRMNUM 16 16 9 PCLKB or more
000A 0054h USB0 USB Request Type Register USBREQ 16 16 9 PCLKB or more
000A 0056h USB0 USB Request Value Register USBVAL 16 16 9 PCLKB or more
000A 0058h USB0 USB Request Index Register USBINDX 16 16 9 PCLKB or more
000A 005Ah USB0 USB Request Length Register USBLENG 16 16 9 PCLKB or more
000A 005Ch USB0 DCP Configuration Register DCPCFG 16 16 9 PCLKB or more
000A 005Eh USB0 DCP Maximum Packet Size Register DCPMAXP 16 16 9 PCLKB or more
000A 0060h USB0 DCP Contr o l Register DCPCTR 16 16 9 PCLKB or more
000A 0064h USB0 Pipe Window Select Register PIPESEL 16 16 9 PCLKB or more
000A 0068h USB0 Pipe Configuration Register PIPECFG 16 16 9 PCLKB or more
000A 006Ch USB0 Pipe Maximum Packet Size Register PIPEMAXP 16 16 9 PCLKB or more
000A 006Eh USB0 Pipe Cycle Control Register PIPEPERI 16 16 9 PCLKB or more
000A 0070h USB0 PIPE1 Control Register PIPE1CTR 16 16 9 PCLKB or more
000A 0072h USB0 PIPE2 Control Register PIPE2CTR 16 16 9 PCLKB or more
000A 0074h USB0 PIPE3 Control Register PIPE3CTR 16 16 9 PCLKB or more
000A 0076h USB0 PIPE4 Control Register PIPE4CTR 16 16 9 PCLKB or more
000A 0078h USB0 PIPE5 Control Register PIPE5CTR 16 16 9 PCLKB or more
000A 007Ah USB0 PIPE6 Control Register PIPE6CTR 16 16 9 PCLKB or more
000A 007Ch USB0 PIPE7 Control Register PIPE7CTR 16 16 9 PCLKB or more
000A 007Eh USB0 PIPE8 Control Register PIPE8CTR 16 16 9 PCLKB or more
000A 0080h USB0 PIPE9 Control Register PIPE9CTR 16 16 9 PCLKB or more
000A 0090h USB0 PIPE1 Transaction Counter Enable Register PIPE1TRE 16 16 9 PCLKB or more
000A 0092h USB0 PIPE1 Transaction Counter Register PIPE1TRN 16 16 9 PCLKB or more
000A 0094h USB0 PIPE2 Transaction Counter Enable Register PIPE2TRE 16 16 9 PCLKB or more
000A 0096h USB0 PIPE2 Transaction Counter Register PIPE2TRN 16 16 9 PCLKB or more
000A 0098h USB0 PIPE3 Transaction Counter Enable Register PIPE3TRE 16 16 9 PCLKB or more
000A 009Ah USB0 PIPE3 Transaction Counter Register PIPE3TRN 16 16 9 PCLKB or more
000A 009Ch USB0 PIPE4 Transaction Counter Enable Register PIPE4TRE 16 16 9 PCLKB or more
000A 009Eh USB0 PIPE4 Transaction Counter Register PIPE4TRN 16 16 9 PCLKB or more
000A 00A0h USB0 PIPE5 Transaction Counter Enable Register PIPE5TRE 16 16 9 PCLKB or more
000A 00A2h USB0 PIPE5 Transaction Counter Register PIPE5TRN 16 16 9 PCLKB or more
000A 00B0h USB0 BC Control Register 0 USBBCCTRL0 16 16 9 PCLKB or more
000A 00CCh USB0 USB Module Control Register USBMC 16 16 9 PCLKB or more
000A 00D0h USB0 Device Address 0 Configuration Register DEVADD0 16 16 9 PCLKB or more
000A 00D2h USB0 Device Address 1 Configuration Register DEVADD1 16 16 9 PCLKB or more
000A 00D4h USB0 Device Address 2 Configuration Register DEVADD2 16 16 9 PCLKB or more
000A 00D6h USB0 Device Address 3 Configuration Register DEVADD3 16 16 9 PCLKB or more
000A 00D8h USB0 Device Address 4 Configuration Register DEVADD4 16 16 9 PCLKB or more
000A 00DAh USB0 Device Address 5 Configuration Register DEVADD5 16 16 9 PCLKB or more
000A 0800h LCDC LCD mode register 0 LCDM0 8 8 1 or 2 PCLKB
000A 0801h LCDC LCD mode register 1 LCDM1 8 8 1 or 2 PCLKB
000A 0802h LCDC LCD Clock Control Register 0 LCDC0 8 8 1 or 2 PCLKB
000A 0803h LCDC LCD Boost Level Control Register VLCD 8 8 1 or 2 PCLKB
Table 4.1 List of I/O Registers (Address Order) (21/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
000A 0840h LCDC LCD Display Data Register 00 SEG00 8 8 1 or 2 PCLKB
000A 0841h LCDC LCD Display Data Register 01 SEG01 8 8 1 or 2 PCLKB
000A 0842h LCDC LCD Display Data Register 02 SEG02 8 8 1 or 2 PCLKB
000A 0843h LCDC LCD Display Data Register 03 SEG03 8 8 1 or 2 PCLKB
000A 0844h LCDC LCD Display Data Register 04 SEG04 8 8 1 or 2 PCLKB
000A 0845h LCDC LCD Display Data Register 05 SEG05 8 8 1 or 2 PCLKB
000A 0846h LCDC LCD Display Data Register 06 SEG06 8 8 1 or 2 PCLKB
000A 0847h LCDC LCD Display Data Register 07 SEG07 8 8 1 or 2 PCLKB
000A 0848h LCDC LCD Display Data Register 08 SEG08 8 8 1 or 2 PCLKB
000A 0849h LCDC LCD Display Data Register 09 SEG09 8 8 1 or 2 PCLKB
000A 084Ah LCDC LCD Display Data Register 10 SEG10 8 8 1 or 2 PCLKB
000A 084Bh LCDC LCD Display Data Register 11 SEG11 8 8 1 or 2 PCLKB
000A 084Ch LCDC LCD Display Data Register 12 SEG12 8 8 1 or 2 PCLKB
000A 084Dh LCDC LCD Display Data Register 13 SEG13 8 8 1 or 2 PCLKB
000A 084Eh LCDC LCD Display Data Register 14 SEG14 8 8 1 or 2 PCLKB
000A 084Fh LCDC LCD Display Data Register 15 SEG15 8 8 1 or 2 PCLKB
000A 0850h LCDC LCD Display Data Register 16 SEG16 8 8 1 or 2 PCLKB
000A 0851h LCDC LCD Display Data Register 17 SEG17 8 8 1 or 2 PCLKB
000A 0852h LCDC LCD Display Data Register 18 SEG18 8 8 1 or 2 PCLKB
000A 0853h LCDC LCD Display Data Register 19 SEG19 8 8 1 or 2 PCLKB
000A 0854h LCDC LCD Display Data Register 20 SEG20 8 8 1 or 2 PCLKB
000A 0855h LCDC LCD Display Data Register 21 SEG21 8 8 1 or 2 PCLKB
000A 0856h LCDC LCD Display Data Register 22 SEG22 8 8 1 or 2 PCLKB
000A 0857h LCDC LCD Display Data Register 23 SEG23 8 8 1 or 2 PCLKB
000A 0858h LCDC LCD Display Data Register 24 SEG24 8 8 1 or 2 PCLKB
000A 0859h LCDC LCD Display Data Register 25 SEG25 8 8 1 or 2 PCLKB
000A 085Ah LCDC LCD Display Data Register 26 SEG26 8 8 1 or 2 PCLKB
000A 085Bh LCDC LCD Display Data Register 27 SEG27 8 8 1 or 2 PCLKB
000A 085Ch LCDC LCD Display Data Register 28 SEG28 8 8 1 or 2 PCLKB
000A 085Dh LCDC LCD Display Data Register 29 SEG29 8 8 1 or 2 PCLKB
000A 085Eh LCDC LCD Display Data Register 30 SEG30 8 8 1 or 2 PCLKB
000A 085Fh LCDC LCD Display Data Register 31 SEG31 8 8 1 or 2 PCLKB
000A 0860h LCDC LCD Display Data Register 32 SEG32 8 8 1 or 2 PCLKB
000A 0861h LCDC LCD Display Data Register 33 SEG33 8 8 1 or 2 PCLKB
000A 0862h LCDC LCD Display Data Register 34 SEG34 8 8 1 or 2 PCLKB
000A 0863h LCDC LCD Display Data Register 35 SEG35 8 8 1 or 2 PCLKB
000A 0864h LCDC LCD Display Data Register 36 SEG36 8 8 1 or 2 PCLKB
000A 0865h LCDC LCD Display Data Register 37 SEG37 8 8 1 or 2 PCLKB
000A 0866h LCDC LCD Display Data Register 38 SEG38 8 8 1 or 2 PCLKB
000A 0867h LCDC LCD Display Data Register 39 SEG39 8 8 1 or 2 PCLKB
000A 0900h CTSU CTSU Control Reg i ster 0 CTSUCR0 8 8 1 or 2 PCLKB
000A 0901h CTSU CTSU Control Reg i ster 1 CTSUCR1 8 8 1 or 2 PCLKB
000A 0902 h CTSU CTS U Synchronous Noise Reduction Setting Register CTSUSDPRS 8 8 1 or 2 PCLKB
000A 0903h CTSU CTSU Sensor Stabilization Wait Time Register CTSUSST 8 8 1 or 2 PCLKB
000A 0904h CTSU CTSU Measurement Channel Register 0 CTSUMCH0 8 8 1 or 2 PCLKB
000A 0905h CTSU CTSU Measurement Channel Register 1 CTSUMCH1 8 8 1 or 2 PCLKB
000A 0906h CTSU CTSU Channel Enable Control Register 0 CTSUCHAC0 8 8 1 or 2 PCLKB
000A 0907h CTSU CTSU Channel Enable Control Register 1 CTSUCHAC1 8 8 1 or 2 PCLKB
000A 090Bh CTSU CTSU Channel Transmit/Receive Control Register 0 CTSUCHTRC0 8 8 1 or 2 PCLKB
000A 090Ch CTSU CTSU Channel Transmit/Receive Control Register 1 CTSUCHTRC1 8 8 1 or 2 PCLKB
000A 0910h CTSU CTSU High-Pass Noise Reduction Con trol Register CTSUDCLKC 8 8 1 or 2 PCLKB
000A 0911h CTSU CTSU Status Register CTSUST 8 8 1 or 2 PCLKB
Table 4.1 List of I/O Registers (Address Order) (22/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 4. I/O Regis ters
Note 1. Odd addresses cannot be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMR0
or TMR2 register. Table 22.4 lists register allocation for 16-bit access in the User’s Manual: Hardware.
Note 2. Odd addresses cannot be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the
TMOCNTL register. Table 30.6 lists register allocation for 16-bit access in the User’s Manual: Hardware.
000A 0912h CTSU CTSU High-Pass Noise Spectrum Diffusion Control Register CTS USSC 16 16 1 or 2 PCLKB
000A 0914h CTSU CTSU Sensor Offset Register 0 CTSUSO0 16 16 1 or 2 PCLKB
000A 0916h CTSU CTSU Sensor Offset Register 1 CTSUSO1 16 16 1 or 2 PCLKB
000A 0918h CTSU CTSU Sensor Count er CTSUSC 16 16 1 or 2 PCLKB
000A 091Ah CTSU CTSU Reference Counter CTSURC 16 16 1 or 2 PCLKB
000A 091Ch CTSU CTSU Error Status Register CTSUERRS 16 16 1 or 2 PCLKB
007F C090h FLASH E2 DataFlash Control Register DFLCTL 8 8 2 or 3 FCLK
007F C0ACh TEMPS Temperature Senso r Calibration Data Register TSCDRL 8 8 1 or 2 PCLKB
007F C0ADh TEMPS Temperature Senso r Calibration Data Register TSCDRH 8 8 1 or 2 PCLKB
007F C0B0h FLASH Flash Start-Up Setting Monitor Register FSCMR 16 16 2 or 3 FCLK
007F C0B2h FLASH Flash Access Window Start Address Monitor FAWSMR 16 16 2 or 3 FCLK
007F C0B4h FLASH Flash Access Window End Address Monitor Register FAWEMR 16 16 2 or 3 FCLK
007F C0B6h FLASH Flash Initial Setting Register FISR 8 8 2 or 3 FCLK
007F C0B7h FLASH Flash Extra Area Control Register FEXCR 8 8 2 or 3 FCLK
007F C0B8h FLASH Flash Error Address Monitor Register L FEAML 16 16 2 or 3 FCLK
007F C0BAh FLASH Flash Error Address Monitor Register H FEAMH 8 8 2 or 3 FCLK
007F C0C0h FLASH Protection Unlock Register FPR 8 8 2 or 3 FCLK
007F C0C1h FLASH Protection Unlock Status Register FPSR 8 8 2 or 3 FCLK
007F C0C2h FLASH Flash Read Buffer Register L FRBL 16 16 2 or 3 FCLK
007F C0C4h FLASH Flash Read Buffer Register H FRBH 16 16 2 or 3 FCLK
007F FF80h FLASH Flash P/E Mode Control Register FPMCR 8 8 2 or 3 FCLK
007F FF81h FLASH Flash Area Select Register FASR 8 8 2 or 3 FCLK
007F FF82h FLASH Flash Processing Start Address Register L FSARL 16 16 2 or 3 FCLK
007F FF84h FLASH Flash Processing Start Address Register H FSARH 8 8 2 or 3 FCLK
007F FF85h FLASH Flash Control Register FCR 8 8 2 or 3 FCLK
007F FF86h FLASH Flash Processing End Address Register L FEARL 16 16 2 or 3 FCLK
007F FF88h FLASH Flash Processing End Address Register H FEARH 8 8 2 or 3 FCLK
007F FF89h FLASH Flash Reset Register FRESETR 8 8 2 or 3 FCLK
007F FF8Ah FLASH Flash Status Register 0 FSTATR0 8 8 2 or 3 FCLK
007F FF8Bh FLASH Flash Status Register 1 FSTATR1 8 8 2 or 3 FCLK
007F FF8Ch FLASH Flash Write Buffer Register L FWBL 16 16 2 or 3 FCLK
007F FF8Eh FLASH Flash Write Buffer Register H FWBH 16 16 2 or 3 FCLK
007F FFB2h FLASH Flash P/E Mode Entry Register FENTRYR 16 1 6 2 or 3 FCLK
Table 4.1 List of I/O Registers (Address Order) (23/23)
Address Module
Symbol Register Name Register
Symbol Number of
Bits Access
Size Number of Access
States
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RX113 Group 5. Electrical Characteristics
5. Electrical Characteristics
5.1 Absolute Maximum Ratings
Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded.
To preclude any malfuncti ons due to n oise in terferenc e, insert c ap acit ors of high f requency ch aracteristi cs between the VCC and
VSS pins, between the AVCC0 and AVSS0 pins, between the VCC_USB and VSS_USB pins, between the VREFH0 and
VREFL0 pins, and between the VREFH and VREFL pins. Place capacitors of about 0.1 μF as close as possible to every power
supply pin and use the shortest and heaviest possible traces. Also, connect capacitors as stabilization capacitance.
Connect the VCL pin to a VSS pin via a 4.7 µF capacitor. The capacitor must be placed close to the pin, refer to section 5.15.1,
Connecting VCL Capacitor and Bypass Capacitors.
Do not input sign als or an I/O pull-up power supply to ports other than 5-V tolerant ports while the device is not powered. The
current injection that results from input of such a signal or I/O pull-up may cause malfunction and the abnormal current that
passes in the device at this time may cause degradation of internal elements.
If input voltage (within the specified range from -0.3 to + 6.5V) is applied to 5-V tolerant ports, it will not cause problems such as
damage to the MCU.
Note 1. Ports P16, P17, PA6, and PB0 are 5 V tolerant.
Note 2. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, refer to Table 1.3, List of
Products.
Table 5.1 Absolute Maximum Ratings
Conditions: VSS = AVSS0 = VREFL0 = VREFL = VSS_USB = 0 V
Item Symbol Value Unit
Power supply voltage VCC, VCC_USB –0.3 to +4.6 V
Input voltage Ports for 5 V tolerant*1Vin –0.3 to +6.5 V
Ports P40 to P44, P46,
ports P90 to P92,
ports PJ6, PJ7
Vin –0.3 to AVCC0 +0.3 V
Ports other than above Vin –0.3 to VCC +0.3 V
Reference power supply voltage VREFH0 –0.3 to AVCC0 +0.3 V
VREFH
Analog power supply voltage AVCC0 –0.3 to +4.6 V
Analog input voltage VAN –0.3 to AVCC0 + 0.3
(when AN000 to AN007 and AN021 used)
–0.3 to VCC + 0.3
(when AN008 to AN015 used)
V
LCD voltage VL1 voltage VL1 –0.3 to +2.8 V
VL2 voltage VL2 –0.3 to +6.5
VL3 voltage VL3 –0.3 to +6.5
VL4 voltage VL4 –0.3 to +6.5
Operating temperature*2Topr –40 to +85
–40 to +105 °C
Storage temperature Tstg –55 to +125 °C
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RX113 Group 5. Electrical Characteristics
Note 1. AVCC0 and VCC can be set individually within the operating range, but there are the following restrictions for the voltage
applied to the PJ0 and PJ2 pins, VCC, and AVCC0.
When 12-bit D/A converter used: Voltage applied to port J0 and J2 pins (D/A output voltage) ≤ VCC
When general ports selected: VCC ≤ AVCC0
Note 2. For details, refer to section 36.8.11, Voltage Range of Analog Power Supply Pins in the User’s Manual: Hardware.
Note 3. Sequence of Powering on AVCC0 and VCC
When powering on AVCC0 and VCC, power them on at the same time or VCC first.
Table 5.2 Recommended Operating Conditions
Item Symbol Conditions Min. Typ. Max. Unit
Power supply voltages VCC*1, *3 When USB not used 1.8 — 3.6 V
When USB used 3.0 — 3.6
VSS — 0 —
USB power supply voltages VCC_USB — VCC — V
VSS_USB — 0 —
Analog power supply voltages AVCC0*1 to *3 1.8 — 3.6 V
AVSS0 — 0 —
VREFH0 1.8 — AVCC0
VREFL0 — 0 —
VREFH 1.8 — AVCC0
VREFL — 0 —
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RX113 Group 5. Electrical Characteristics
5.2 DC Characteristics
Note 1. There are restrictions on AVCC0 and VCC depending on the usage conditions for the 12-bit D/A converter and I/O ports.
When using ports PJ0 and PJ2 multiplexed with DA0 and DA1 as general I/O ports, make sure that VCC ≤ AVCC0.
Table 5.3 DC Characteri st ics (1 )
Conditions: 2.7 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test
Conditions
Schmitt trigger
input voltage RIIC input pin
(except for SMBus, 5 V tolerant) VIH VCC × 0.7 — 5.8 V
Ports P16, P17, port PA6, port
PB0 (5 V tolerant) VCC × 0.8 — 5.8
Ports P02, P04, P07,
ports P10 to P15,
ports P20 to P27,
ports P30 to P32, P35,
ports P50 to P56,
ports PA0 to PA5, PA7,
ports PB1 to PB7,
ports PC0 to PC7,
ports PD0 to PD4,
ports PE0 to PE7,
ports PF6, PF7,
port PH7,
ports PJ0*1, PJ2*1, PJ3,
RES#
VCC × 0.8 — VCC + 0.3
RIIC input pin (except for SMBus) VIL –0.3 — VCC × 0.3
Other than RIIC input pin –0.3 — VCC × 0.2
RIIC input pin (except for SMBus) ∆VTVCC × 0.05 — —
Other than RIIC input pin VCC × 0.1 — —
Input voltage
(except for
Schmitt trigger
input pins)
MD VIH VCC × 0.9 — VCC + 0.3 V
XTAL (external clock input) VCC × 0.8 — VCC + 0.3
Ports P40 to P44, P46,
ports P90 to P92,
ports PJ6, PJ7
AVCC0 × 0.7 — AVCC0 + 0.3
RIIC input pin (SMBus) 2.1 — VCC + 0.3
MD VIL –0.3 — VCC × 0.1
XTAL (external clock input) –0.3 — VCC × 0.2
Ports P40 to P44, P46,
ports P90 to P92,
ports PJ6, PJ7
–0.3 — AVCC0 × 0.3
RIIC input pin (SMBus) –0.3 — 0.8
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RX113 Group 5. Electrical Characteristics
Note 1. There are restrictions on AVCC0 and VCC depending on the usage conditions for the 12-bit D/A converter and I/O ports.
When using ports PJ0 and PJ2 multiplexed with DA0 and DA1 as general I/O ports, make sure that VCC ≤ AVCC0.
Table 5.4 DC Characteri st ics (2 )
Conditions: 1.8 V ≤ VCC = VCC_USB < 2.7 V, 1.8 V ≤ AVCC0 < 2.7 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test
Conditions
Schmitt trigger
input voltage Ports P16, P17, port PA6, port
PB0 (5 V tolerant) VIH VCC × 0.8 — 5.8 V
Ports P02, P04, P07,
ports P10 to P15,
ports P20 to P27,
ports P30 to P32, P35,
ports P50 to P56,
ports PA0 to PA5, PA7
ports PB1 to PB7,
ports PC0 to PC7,
ports PD0 to PD4,
ports PE0 to PE7,
ports PF6, PF7,
port PH7,
ports PJ0*1, PJ2*1, PJ3,
RES#
VCC × 0.8 — VCC + 0.3
All pins VIL –0.3 — VCC × 0.2
All pins ∆VTVCC × 0.01 — —
Input voltage
(except for
Schmitt trigger
input pins)
MD VIH VCC × 0.9 — VCC + 0.3 V
XTAL (external clock input) VCC × 0.8 — VCC + 0.3
Ports P40 to P44, P46,
ports P90 to P92,
ports PJ6, PJ7
AVCC0 × 0.7 — AVCC0 + 0.3
MD VIL –0.3 — VCC × 0.1
XTAL (external clock input) –0.3 — VCC × 0.2
Ports P40 to P44, P46,
ports P90 to P92,
ports PJ6, PJ7
–0.3 — AVCC0 × 0.3
Table 5.5 DC Characteri st ics (3 )
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Input leakage
current RES#, MD, port P35,
port PH7 Iin——1.0µAV
in = 0 V, VCC
Three-state
leakage current
(off-state)
Ports for 5 V tolerant ITSI——1.0µAV
in = 0 V, 5.8 V
Pins other than above — — 1.0 Vin = 0 V, VCC
Input capacitance All input pins
(except for port P16, port P35,
USB0_DM, USB0_DP)
Cin — — 15 pF Vin = 0 V
Frequency: 1 MHz
Ta = 25°C
Port P16, port P35, USB0_DM,
USB0_DP ——30
Table 5.6 DC Characteri st ics (4 )
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Input pull-up
resistor All ports
(except for ports P35, PH7) RU10 20 100 kΩVin = 0 V
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RX113 Group 5. Electrical Characteristics
Table 5.7 DC Characteri st ics (5 ) (1/2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Typ
*4Max Unit Test
Conditions
Supply
current*1High-speed
operating
mode
Normal
operating
mode
No peripheral
operation*2ICLK = 32 MHz ICC 3.6 — mA
ICLK = 16 MHz 2.4 —
ICLK = 8 MHz 1.8 —
All peripheral operation:
Normal*3ICLK = 32 MHz 14.0 —
ICLK = 16 MHz 7.9 —
ICLK = 8 MHz 4.9 —
All peripheral operation:
Max.*3ICLK = 32 MHz — 30.0
Sleep mode No peripheral
operation*2ICLK = 32 MHz 1.9 —
ICLK = 16 MHz 1.5 —
ICLK = 8 MHz 1.3 —
All peripheral operation:
Normal*3ICLK = 32 MHz 8.2 —
ICLK = 16 MHz 4.8 —
ICLK = 8 MHz 3.1 —
Deep sleep
mode No peripheral
operation*2ICLK = 32 MHz 1.1 —
ICLK = 16 MHz 0.95 —
ICLK = 8 MHz 0.86 —
All peripheral operation:
Normal*3ICLK = 32 MHz 6.4 —
ICLK = 16 MHz 3.8 —
ICLK = 8 MHz 2.4 —
Increase during flash rewrite*52.5 —
Middle-speed
operating
modes
Normal
operating
mode
No peripheral
operation*6ICLK = 12 MHz ICC 2.1 — mA
ICLK = 8 MHz 1.4 —
ICLK = 1 MHz 0.77 —
All peripheral operation:
Normal*7ICLK = 12 MHz 6.3 —
ICLK = 8 MHz 4.6 —
ICLK = 1 MHz 1.6 —
All peripheral
operation: Max.*7ICLK = 12 MHz — 14.2
Sleep mode No peripheral
operation*6ICLK = 12 MHz 1.4 —
ICLK = 8 MHz 0.90 —
ICLK = 1 MHz 0.68 —
All peripheral operation:
Normal*7ICLK = 12 MHz 3.9 —
ICLK = 8 MHz 2.9 —
ICLK = 1 MHz 1.4 —
Deep sleep
mode No peripheral
operation*6ICLK = 12 MHz 1.1 —
ICLK = 8 MHz 0.63 —
ICLK = 1 MHz 0.55 —
All peripheral operation:
Normal*7ICLK = 12 MHz 3.3 —
ICLK = 8 MHz 2.4 —
ICLK = 1 MHz 1.2 —
Increase during flash rewrite*52.5 —
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RX113 Group 5. Electrical Characteristics
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOSs are in the off state.
Note 2. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is PLL. FCLK and
PCLK are set to divided by 64.
Note 3. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is PLL. FCLK and PCLK
are set to the same frequency as ICLK.
Note 4. Values when VCC = 3.3 V.
Note 5. This is the increase for programming or erasure of the ROM or E2 DataFlash during program execution.
Note 6. Clock supply to the peripheral functions is stopped. The clock source is PLL when ICLK = 12 MHz, and HOCO otherwise. FCLK
and PCLK are set to divided by 64.
Note 7. Clocks are supplied to the peripheral functions. The clock source is PLL when ICLK = 12 MHz, and HOCO otherwise. FCLK and
PCLK are set to the same frequency as ICLK.
Note 8. Clock supply to the peripheral functions is stopped. The clock source is the sub-clock oscillator. FCLK and PCLK are set to
divided by 64.
Note 9. Clocks are supplied to the peripheral functions. The clock source is the sub-clock oscillator. FCLK and PCLK are set to the
same frequency as ICLK.
Note 10. Values when the MSTPCRA.MSTPA17 bit (12-bit A/D converter module stop bit) is set to “transition to the module stop state is
made”.
Supply
current*1Low-speed
operating
mode
Normal
operating
mode
No peripheral
operation*8ICLK = 32.768 kHz ICC 4.3 — μA
All peripheral operation:
Normal*9, *10 ICLK = 32.768 kHz 15.0 —
All peripheral operation:
Max.*9, *10 ICLK = 32.768kHz — 62
Sleep mode No peripheral
operation*8ICLK = 32.768 kHz 2.3 —
All peripheral operation:
Normal*9ICLK = 32.768 kHz 8.6 —
Deep sleep
mode No peripheral
operation*8ICLK = 32.768 kHz 1.7 —
All peripheral operation:
Normal*9ICLK = 32.768 kHz 7.0 —
Table 5.7 DC Characteri st ics (5 ) (2/2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Typ
*4Max Unit Test
Conditions
R01DS0216EJ0110 Rev.1.10 Page 59 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.1 Voltage Dependency in High-Speed Operating Mode (Refer ence Data)
Figure 5.2 Voltage Dependency in Middle-Speed Operating Mode (Reference Data)
0
5
10
15
20
25
1.52.02.53.03.54.0
Note 1. All peripheral operation is normal. This does not include BGO operation. Average value of the
tested middle samples during product evaluation.
Note 2. All peripheral operation is maximum. This does not include BGO operation. Average value of the
tested upper-limit samples during product evaluation.
VCC (V)
ICC (mA)
Ta = 85/105°C, ICLK = 32 MHz*2
Ta = 25°C, ICLK = 32 MHz*1
Ta = 25°C, ICLK = 16 MHz*1
Ta = 25°C, ICLK = 8 MHz*1
Ta = 85/105°C, ICLK = 16 MHz*2
Ta = 85/105°C, ICLK = 8 MHz*2
0
2
4
6
8
10
12
1.5 2.0 2.5 3.0 3.5 4.0
Ta = 85/105°C, ICLK = 12 MHz*2
Ta = 25°C, ICLK = 8 MHz*1
Ta = 85/105°C, ICLK = 8 MHz*2
Ta = 85/105°C, ICLK = 1 MHz*2
Ta = 25°C, ICLK = 1 MHz*1
Ta = 25°C, ICLK = 12 MHz*1
Note 1. All peripheral operation is normal. This does not include BGO operation. Average value of the
tested middle samples during product evaluation.
Note 2. All peripheral operation is maximum. This does not include BGO operation. Average value of the
tested upper-limit samples during product evaluation.
VCC (V)
ICC (mA)
R01DS0216EJ0110 Rev.1.10 Page 60 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.3 Voltage Dependency in Low-Speed Operating Mode (Reference Data)
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOSs are in the off state.
Note 2. The IWDT and LVD are stopped.
Note 3. VCC = 3.3 V.
Note 4. Includes the oscillation circuit.
Table 5.8 DC Characteri st ics (6 )
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Typ.*3Max. Unit Test Conditions
Supply
current*1Software standby
mode*2Ta = 25°C ICC 0.44 0.98 μA
Ta = 55°C 0.80 3.47
Ta = 85°C 2.7 12.0
Ta = 105°C 6.17 42.7
Increment for RTC operation*40.31 — RCR3.RTCDV[2:0] = 010b
1.09 — RCR3.RTCDV[2:0] = 100b
Increment for LPT operation 0.37 — LPTCR1.LPCNTCKSEL set to IWDT
dedicated on-chip oscillator
Increment for IWDT operation 0.37 —
0
10
20
30
40
50
60
1.5 2.0 2.5 3.0 3.5 4.0
Ta = 105°C, ICLK = 32 kHz*2
Ta = 25°C, ICLK = 32 kHz*1
Ta = 85°C , ICLK = 32 kHz*2
Note 1. A ll peripheral operation is normal. Average value of the tested middle samples during product
evaluation.
Note 2. All peripheral operation is maximum. Average value of the tested upper-limit samples during
product evaluation.
VCC (V)
ICC (µA)
R01DS0216EJ0110 Rev.1.10 Page 61 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.4 Voltage Dependency in Software Standby Mode (Reference Data)
Figure 5.5 Temperature Dependency in Software Stand by Mode (Reference Data)
Note 1. Average value of the tested middle samples during product evaluat ion.
Note 2. Average value of the tested upper-limit samples during product evaluation.
0.1
1
10
100
1.5 2 2.5 3 3.5 4
Ta = 105°C*2
Ta = 85°C*2
Ta = 105°C*1
Ta = 85°C*1
Ta = 55°C*2
Ta = 55°C*1
Ta = 25°C*2
Ta = 25°C*1
Note 1. Average v alu e of the tested middle samples during product evaluation.
Note 2. Average value of the tested upper-limit samples during produc t evaluation.
0.1
1
10
100
–40 –20 0 20 40 60 80 100 120
*2
*1
R01DS0216EJ0110 Rev.1.10 Page 62 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Note 1. Total power dissipated by the entire chip (including output currents).
Note 2. Please contact Renesas Electronics sales office for derating under Ta = +85°C to 105°C. Derating is the systematic reduction of
load for the sake of improved reliability.
Table 5.9 DC Characteri st ics (7 )
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V
Item Symbol Typ. Max. Unit Test Conditions
Permissible total consumption power*1Pd — 300 mW D version (Ta = -40 to 85°C)
— 105 G version (Ta = -40 to 105°C)*2
Table 5.10 DC Characteristics (8) (1/2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ.*7Max. Unit Test
Conditions
Analog power
supply current During A/D conversion (at high-speed conversion) IAVCC —0.71.2mA
During D/A conversion (per channel) — 0.4 0.8
Waiting for A/D and D/A conversion (all units) — — 0.4 μA
Reference
power supply
current
During A/D conversion (at high-speed conversion) IREFH0 —2552μA
Waiting for A/D conversion (all units) — — 60 nA
During D/A conversion IREFH — 50 100 μA
Waiting for D/A conversion (all units) — — 100 nA
LDV1, 2 Per channel ILVD —0.15—μA
Temperature
sensor*6—I
TEMP —75—μA
Comparator B
operating
current*6
Window mode ICMP*4— 12.5 — μA
Comparator high-speed mode — 6.5 — μA
Comparator low-speed mode — 1.7 — μA
LCD operating
current*6External resistance division method*8
fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD1*5—0.04—μA
Internal voltage boosting method (VLCD.VLCD = 04)
fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD2*5—0.85—μA
Internal voltage boosting method (VLCD.VLCD = 12)
fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD2*5—1.55—μA
Capacitor split method
fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD3*5—0.20—μA
R01DS0216EJ0110 Rev.1.10 Page 63 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Note 1. Current consumed only by the USB module.
Note 2. Includes the current supplied from the pull-up resistor of the USB0_DP pin to the pull-down resistor of the host device, in
addition to the current consumed by this MCU during the suspended state.
Note 3. Current consumed by the power supplies (VCC and VCC_USB).
Note 4. Current consumed only by the comparator B module.
Note 5. Current consumed only by the LCD module. Current when the LCD panel is not connected.
Note 6. Current consumed by the power supply (VCC).
Note 7. When VCC = AVCC0 = VCC_USB = 3.3 V.
Note 8. It does not include the current that flows through external divider resistors.
Note: When powering on AVCC0 and VCC, power them on at the same time or VCC first.
Note 1. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b.
Note 2. When OFS1.(STUPLVD1REN, FASTSTUP) = 10b.
Note 3. When OFS1.STUPLVD1REN = 0.
Note 4. Turn on the power supply voltage according to the normal startup rising gradient because the register settings set by OFS1 are
not read in boot mode.
USB operating
current*3During USB communication operation under the
following settings and conditions
Host controller operation is set to full-speed mode
Bulk OUT transfer (64 bytes) × 1,
bulk IN transfer (64 bytes) × 1
Connect peripheral devices via a 1-meter USB
cable from the USB port.
IUSBH*1—4.3
(VCC)
0.9
(VCC_USB)*3
—mA
During USB communication operation under the
following settings and conditions
Function controller operation is set to full-speed
mode
Bulk OUT transfer (64 bytes) × 1,
bulk IN transfer (64 bytes) × 1
Connect the host device via a 1-meter USB cable
from the USB port.
IUSBF*1—3.6
(VCC)
1.1
(VCC_USB)*3
—mA
During suspended state under the following setting
and conditions
Function controller operation is set to full-speed
mode (pull up the USB0_DP pin)
Software standby mode
Connect the host device via a 1-meter USB cable
from the USB port.
ISUSP*2—0.35
(VCC)
170
(VCC_USB)*3
—μA
CTSU
operating
current
During measurement (CPU is in sleep mode)
Base clock: 2 MHz
Pin capacity: 50 pF
ICTSU —150—μA
Table 5.11 DC Characteristics (9)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
RAM standby voltage VRAM 1.8 — — V
Table 5.12 DC Characteristics (10)
Conditions: 0 V ≤ VCC = VCC_USB ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Power-on VCC
rising gradient At normal startup*1SrVCC 0.02 — 20 ms/V
During fast startup time*20.02 — 2
Voltage monitoring 1 reset enabled at startup
*3, *40.02 — —
Table 5.10 DC Characteristics (8) (2/2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ.*7Max. Unit Test
Conditions
R01DS0216EJ0110 Rev.1.10 Page 64 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.6 Ripple Waveform
Table 5.13 DC Characteristics (11)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and
lower limit (1.8 V).
When VCC change exceeds VCC ±10%, the allowable voltage change rising/falling gradient dt/dVCC must be met.
Item Symbol Min. Typ. Max. Unit Test Conditions
Allowable ripple frequency fr (VCC) — — 10 kHz Figure 5.6
Vr (VCC) ≤ VCC × 0.2
— — 1 MHz Figure 5.6
Vr (VCC) ≤ VCC × 0.08
— — 10 MHz Figure 5.6
Vr (VCC) ≤ VCC × 0.06
Allowable voltage change rising/
falling gradient dt/dVCC 1.0 — — ms/V When VCC change exceeds VCC ±10%
Vr(VCC)
VCC
1/fr(VCC)
R01DS0216EJ0110 Rev.1.10 Page 65 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Note: The recommended capacitance is 4.7 μF. Variations in connected capacitors should be within the above range.
Note: Do not exceed the permissible total supply current.
Table 5.14 DC Characteristics (12)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Permissible error of VCL pin external capacitance CVCL 1.4 4.7 7.0 μF
Table 5.15 Permissible Output Currents (1)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V,
Ta = –40 to +85°C (D version)
Item Symbol Max. Unit
Permissible output low current
(average value per pin) Ports P40 to P44, P46, ports P90 to P92, ports PJ6, PJ7 IOL 0.4 mA
Ports other than above 8.0
Permissible output low current
(maximum value per pin) Ports P40 to P44, P46, ports P90 to P92, ports PJ6, PJ7 0.4
Ports other than above 8.0
Permissible output low current Total of ports P40 to P44, P46, ports P90 to P92, ports PJ6,
PJ7 IOL 2.4
Total of ports P02, P04, P07, P20 to P27, P30, P 31, PJ0, PJ2,
PJ3 30
Total of ports P10 to P17, port P32, ports P50 to P56,
ports PB0 to PB7, ports PC0 to PC7 30
Total of ports PA0 to PA7, ports PD0 to PD4, ports PE0 to
PE7, ports PF6, PF7 30
Total of all output pins 60
Permissible output high current
(average value per pin) Ports P40 to P44, P46, ports P90 to P92, ports PJ6, PJ7 IOH –0.1
Ports other than above –4.0
Permissible output high current
(maximum value per pin) Ports P40 to P44, P46, ports P90 to P92, ports PJ6, PJ7 –0.1
Ports other than above –4.0
Permissible output high current Total of ports P40 to P44, P46, ports P90 to P92, ports PJ6,
PJ7 IOH –0.6
Total of ports P02, P04, P07, P20 to P27, P30, P 31, PJ0, PJ2,
PJ3 –10
Total of ports P10 to P17, port P32, ports P50 to P56,
ports PB0 to PB7, ports PC0 to PC7 –15
Total of ports PA0 to PA7, ports PD0 to PD4, ports PE0 to
PE7, ports PF6, PF7 –15
Total of all output pins –40
R01DS0216EJ0110 Rev.1.10 Page 66 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Note: Do not exceed the permissible total supply current.
Table 5.16 Permissible Output Currents (2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V,
Ta = –40 to +105°C (G version)
Item Symbol Max. Unit
Permissible output low current
(average value per pin) Ports P40 to P44, P46, ports P90 to P92, ports PJ6, PJ7 IOL 0.4 mA
Ports other than above 8.0
Permissible output low current
(maximum value per pin) Ports P40 to P44, P46, ports P90 to P92, ports PJ6, PJ7 0.4
Ports other than above 8.0
Permissible output low current Total of ports P40 to P44, P46, ports P90 to P92, ports PJ6,
PJ7 IOL 1.6
Total of ports P02, P04, P07, P20 to P27, P30, P 31, PJ0, PJ2,
PJ3 20
Total of ports P10 to P17, port P32, ports P50 to P56
ports PB0 to PB7, ports PC0 to PC7 20
Total of ports PA0 to PA7, ports PD0 to PD4, ports PE0 to
PE7, ports PF6, PF7 20
Total of all output pins 40
Permissible output high current
(average value per pin) Ports P40 to P44, P46, ports P90 to P92, ports PJ6, PJ7 IOH –0.1
Ports other than above –4.0
Permissible output high current
(maximum value per pin) Ports P40 to P44, P46, ports P90 to P92, ports PJ6, PJ7 –0.1
Ports other than above –4.0
Permissible output high current Total of ports P40 to P44, P46, ports P90 to P92, ports PJ6,
PJ7 IOH –0.6
Total of ports P02, P04, P07, P20 to P27, P30, P 31, PJ0, PJ2,
PJ3 –10
Total of ports P10 to P17, port P32, ports P50 to P56,
ports PB0 to PB7, ports PC0 to PC7 –15
Total of ports PA0 to PA7, ports PD0 to PD4, ports PE0 to
PE7, ports PF6, PF7 –15
Total of all output pins –40
R01DS0216EJ0110 Rev.1.10 Page 67 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Note 1. There are restrictions on AVCC0 and VCC depending on the usage conditions for the 12-bit D/A converter and I/O ports.
When using ports PJ0 and PJ2 multiplexed with DA0 and DA1 as general I/O ports, make sure that VCC ≤ AVCC0.
Note 1. There are restrictions on AVCC0 and VCC depending on the usage conditions for the 12-bit D/A converter and I/O ports.
When using ports PJ0 and PJ2 multiplexed with DA0 and DA1 as general I/O ports, make sure that VCC ≤ AVCC0.
Table 5.17 Output Values of Voltage (1)
Conditions: 2.7 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Max. Unit Test Conditions
Low-level
output
voltage
All output ports
(except for RIIC, ports P40 to P44, P46, ports
P90 to P92, ports PJ6, PJ7)
VOL —0.6VI
OL = 3.0 mA
—0.4 I
OL = 1.5 mA
Ports P40 to P44, P46, ports P90 to P92,
ports PJ6, PJ7 —0.4 I
OL = 0.4 mA
RIIC pins Standard mode — 0.4 IOL = 3.0 mA
Fast mode — 0.6 IOL = 6.0 mA
High-level
output
voltage
All output ports (except for ports P40 to P44,
P46, ports P90 to P92, ports PJ6, PJ7)*1VOH VCC – 0.5 — V IOH = –2.0 mA
Ports P40 to P44, P46, ports P90 to P92,
ports PJ6, PJ7 AVCC0 – 0.5 — IOH = –0.1 mA
Table 5.18 Output Values of Voltage (2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 2.7 V, 1.8 V ≤ AVCC0 ≤ 2.7 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Max. Unit Test Conditions
Low-level
output
voltage
All output ports (except for ports P40 to P44,
P46, ports P90 to P92, ports PJ6, PJ7) VOL —0.6VI
OL = 1.5 mA
Ports P40 to P44, P46, ports P90 to P92,
ports PJ6, PJ7 —0.4 I
OL = 0.4 mA
High-level
output
voltage
All output ports (except for ports P40 to P44,
P46, ports P90 to P92, ports PJ6, PJ7)*1VOH VCC – 0.5 — V IOH = –1.0 mA
Ports P40 to P44, P46, ports P90 to P92,
ports PJ6, PJ7 AVCC0 – 0.5 — IOH = –0.1 mA
R01DS0216EJ0110 Rev.1.10 Page 68 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
5.2.1 Standard I/O Pin Output Characteristics (1)
Figure 5.7 to Figure 5.10 show the characteristics of general ports (except for the RIIC output pin, ports P40 to P44,
P46, ports P90 to P92, port s PJ6, PJ7).
Figure 5.7 VOH/VOL and IOH/IOL Voltage Characteristics of General Ports (Except for RIIC Output
Pin, Ports P40 to P44, P46, Ports P90 to P92, Ports PJ6, PJ7) at Ta = 25°C (Reference
Data)
–30
–20
–10
0
10
20
30
40
0 0.5 1 1.5 2 2.5 3 3.5
VOH/VOL [V]
IOH/IOL vs VOH/VOL
VCC = 3.3 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 2.7 V
VCC = 1.8 V
VCC = 1.8 V
IOH/IOL [mA]
R01DS0216EJ0110 Rev.1.10 Page 69 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.8 VOH/VOL and IOH/IOL Temperature Characteristics of General Ports (Except for RIIC
Output Pin, Ports P40 to P44, P46, Ports P90 to P92, Ports PJ6, PJ7) at VCC = 1.8 V
(Reference Data)
Figure 5.9 VOH/VOL and IOH/IOL Temperature Characteristics of General Ports (Except for RIIC
Output Pin, Ports P40 to P44, P46, Ports P90 to P92, Ports PJ6, PJ7) at VCC = 2.7 V
(Reference Data)
–6
–4
–2
0
2
4
6
8
10
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VOH/VOL [V]
IOH/IOL vs VOH/VOL
Ta = –40°C
Ta = –40°C
Ta = 25°C
Ta = 25°C
Ta = 105°C
Ta = 105°C
IOH/IOL [mA]
IOH/IOL [mA]
–20
–15
–10
–5
0
5
10
15
20
25
30
0 0.5 1 1.5 2 2.5 3
VOH/VOL [V]
IOH/IOL vs VOH/VOL
Ta= –40°C
Ta= –40°C
Ta = 25°C
Ta = 25°C
Ta = 105°C
Ta = 105°C
R01DS0216EJ0110 Rev.1.10 Page 70 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.10 VOH/VOL and IOH/IOL Temperature Characteristics of General Ports (Except for RIIC
Output Pin, Ports P40 to P44, P46, Ports P90 to P92, Ports PJ6, PJ7) at VCC = 3.3 V
(Reference Data)
–30
–20
–10
0
10
20
30
40
50
0 0.5 1 1.5 2 2.5 3 3.5 4
VOH/VOL [V]
IOH/IOL vs VOH/VOL
Ta = –40°C
Ta = –40°C
Ta = 25°C
Ta = 25°C
Ta = 105°C
Ta = 105°C
IOH/IOL [mA]
R01DS0216EJ0110 Rev.1.10 Page 71 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
5.2.2 Standard I/O Pin Output Characteristics (2)
Figure 5.11 to Figure 5.13 show the characteristics of the RIIC output pin.
Figure 5.11 VOL and IOL Voltage Characteristics of RIIC Output Pin at Ta = 25°C (Reference Data)
Figure 5.12 VOL and IOL Temperature Characteristics of RIIC Out put Pin at VCC = 2.7 V (Reference
Data)
0
5
10
15
20
25
30
35
40
00.511.522.53 3.5
VOH/VOL [V]
IOL vs VOL
VCC = 3.3 V
VCC = 2.7 V
IOL [mA]
0
5
10
15
20
25
30
0 0.5 1 1.5 2 2.5 3
VOL [V]
IOL vs VOL
Ta = –40°C
Ta = 25°C
Ta = 105°C
IOL [mA]
R01DS0216EJ0110 Rev.1.10 Page 72 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.13 VOL and IOL Temperature Characteristics of RIIC Out put Pin at VCC = 3.3 V (Reference
Data)
0
5
10
15
20
25
30
35
40
45
50
0 0.5 1 1.5 2 2.5 3 3.5 4
VOL [V]
IOL vs VOL
Ta = –40°C
Ta = 25°C
Ta = 105°C
IOL [mA]
R01DS0216EJ0110 Rev.1.10 Page 73 of 131
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RX113 Group 5. Electrical Characteristics
5.2.3 Standard I/O Pin Output Characteristics (3)
Figure 5.14 to Figure 5.17 show the characteristics of ports P40 to P44, P46, ports P90 to P92, ports PJ6, PJ7.
Figure 5.14 VOH/VOL and IOH/IOL Voltage Characteristics of Ports P40 to P44, P46, Ports P90 to P92,
Ports PJ6, PJ7 at Ta = 25°C (Reference Data)
Figure 5.15 VOH/VOL and IOH/IOL Temperatu re Ch aracterist ics o f Ports P40 to P4 4, P46, Ports P90 to
P92, Ports PJ6, PJ7 at VCC = 1.8 V (Reference Data)
–4
–2
0
2
4
6
8
10
12
14
0 0.5 1 1.5 2 2.5 3 3.5
VOH/VOL [V]
IOH/IOL vs VOH/VOL
VCC = 3.3 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 2.7 V
VCC = 1.8 V
VCC = 1.8 V
IOH/IOL [mA]
–1
–1
0
1
1
2
2
3
3
4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VOH/VOL [V]
IOH/IOL vs VOH/VOL
Ta = –40 ° C
Ta = –40°C
Ta = 25°C
Ta = 25°C
Ta = 105°C
Ta = 105°C
IOH/IOL [mA]
R01DS0216EJ0110 Rev.1.10 Page 74 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.16 VOH/VOL and IOH/IOL Temperatu re Ch aracterist ics o f Ports P40 to P4 4, P46, Ports P90 to
P92, Ports PJ6, PJ7 at VCC = 2.7 V (Reference Data)
Figure 5.17 VOH/VOL and IOH/IOL Temperatu re Ch aracterist ics o f Ports P40 to P4 4, P46, Ports P90 to
P92, Ports PJ6, PJ7 at VCC = 3.3 V (Reference Data)
–4
–2
0
2
4
6
8
10
0 0.5 1 1.5 2 2.5 3
VOH/VOL [V]
IOH/IOL vs VOH/VOL
Ta = –40°C
Ta = –40°C
Ta = 25°C
Ta = 25°C
Ta = 105°C
Ta = 105°C
IOH/IOL [mA]
–4
–2
0
2
4
6
8
10
12
14
16
0 0.5 1 1.5 2 2.5 3 3.5 4
VOH/VOL [V]
IOH/IOL vs VOH/VOL
Ta = –40 ° C
Ta = –40°C
Ta = 25°C
Ta = 25°C
Ta = 105° C
Ta = 105° C
IOH/IOL [mA]
R01DS0216EJ0110 Rev.1.10 Page 75 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
5.3 AC Characteristics
5.3.1 Clock Timing
Note 1. The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the A/D converter is in use.
Note 4. The VCC_USB range is 3.0 to 3.6 V when the USB clock is in use.
Note 1. The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of FCLK should be ±3.5%.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the A/D converter is in use.
Note 4. The VCC_USB range is 3.0 to 3.6 V when the USB clock is in use.
Note 1. Programming and erasing the flash memory is impossible.
Note 2. The A/D converter cannot be used.
Table 5.19 Operation Frequency Value (High-Speed Operating Mode)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol VCC Unit
1.8 to 2.4 V 2.4 to 2.7 V 2.7 to 3.6 V When USB
in Use*4
Maximum
operating
frequency
System clock (ICLK) fmax 8163232MHz
FlashIF clock (FCLK)*1, *28163232
Peripheral module clock (PCLKB) 8 16 32 32
Peripheral module clock (PCLKD)*38163232
USB clock (UCLK) fusb ———48
Table 5.20 Operation Frequency Valu e (Middle-Speed Operating Mode)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol VCC Unit
1.8 to 2.4 V 2.4 to 2.7 V 2.7 to 3.6 V When USB
in Use*4
Maximum
operating
frequency
System clock (ICLK) fmax 8121212MHz
FlashIF clock (FCLK)*1, *28121212
Peripheral module clock (PCLKB) 8 12 12 12
Peripheral module clock (PCLKD)*38121212
USB clock (UCLK) fusb ———48
Table 5.21 Operation Frequency Valu e (Low-Speed Operating Mode)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol VCC Unit
1.8 to 2.4 V 2.4 to 2.7 V 2.7 to 3.6 V
Maximum
operating
frequency
System clock (ICLK) fmax 32.768 kHz
FlashIF clock (FCLK)*132.768
Peripheral module clock (PCLKB) 32.768
Peripheral module clock (PCLKD)*232.768
R01DS0216EJ0110 Rev.1.10 Page 76 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Note 1. Time until the clock can be used after the main clock oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the
external clock is stable.
Note 2. Reference values when an 8-MHz resonator is used.
When specifying the main clock oscillator stabilization time, set the MOSCWTCR register with a stabilization time value that is
equal to or greater than the resonator-manufacturer-recommended value.
After changing the setting of the MOSCCR.MOSTP bit so that the main clock oscillator operates, read the OSCOVFSR.MOOVF
flag to confirm that is has become 1, and then start using the main clock.
Note 3. The VCC range should be 2.4 to 3.6 V when the PLL is used.
Note 4. After changing the setting of the SOSCCR.SOSTP bit or RCR3.RTCEN bit so that the sub-clock oscillator operates, only start
using the sub-clock after the sub-clock oscillation stabilization wait time that is equal to or greater than the
oscillator-manufacturer-recommended value has elapsed.
Reference value when a 32.768-kHz resonator is used.
Note 5. The VCC range should be 3.0 to 3.6 V when the USBPLL is used.
Note 6. The input frequency can be set to 6 or 8 MHz only and the oscillation frequency can be set to 48 MHz only.
Note 7. Only 32.768 kHz can be used.
Table 5.22 Clock Timing
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
XTAL external clock input cycle time tXcyc 50 — — ns Figure 5.18
XTAL external clock input high pulse width tXH 20 — — ns
XTAL external clock input low pulse width tXL 20 — — ns
XTAL external clock rising time tXr —— 5 ns
XTAL external clock falling time tXf —— 5 ns
XTAL external clock input wait time*1tEXWT 0.5 — — μs
Main clock oscillator oscillation
frequency 2.4 ≤ VCC ≤ 3.6 fMAIN 1—20MHz
1.8 ≤ VCC < 2.4 1 — 8
Main clock oscillation stabilization time (crystal)*2tMAINOSC — 3 — ms Figure 5.19
Main clock oscillation stabilization time (ceramic
resonator)*2tMAINOSC —50—μs
LOCO clock oscillation frequency fLOCO 3.44 4.0 4.56 MHz
LOCO clock oscillation stabilization time tLOCO ——0.5μs Figure 5.20
IWDT-dedicated clock oscillation frequency fILOCO 12.75 15 17.25 kHz
IWDT-dedicated clock oscillation stabilization time tILOCO ——50μs Figure 5.21
HOCO clock oscillation frequency fHOCO 31.52 32 32.48 MHz Ta = –40 to 85°C
31.68 32 32.32 Ta = –20 to 85°C
31.36 32 32.64 Ta = –40 to 105°C
HOCO clock oscillation stabilization time tHOCO ——56μs Figure 5.23
PLL input frequency*3fPLLIN 4—8MHz
PLL circuit oscillation frequency*3fPLL 32 — 48 MHz
PLL clock oscillation stabilization time tPLL ——50μs Figure 5.24
PLL free-running oscillation frequency fPLLFR —8—MHz
USBPLL input frequency*5fPLLIN —6, 8*
6—MHz
USBPLL circuit oscillation frequency*5fPLL — 48*6—MHz
USBPLL clock oscillation stabilization time tPLL ——50μs Figure 5.24
Sub-clock oscillator oscillation frequency*7fSUB — 32.768 — kHz
Sub-clock oscillation stabilization time*4tSUBOSC — 0.5 — s Figure 5.25
R01DS0216EJ0110 Rev.1.10 Page 77 of 131
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RX113 Group 5. Electrical Characteristics
Figure 5.18 XTAL External Clock Input Timing
Figure 5.19 Main Clock Oscillation Start Timing
Figure 5.20 LOCO Clock Oscillation Start Timing
Figure 5.21 I WDT -Dedicated Cloc k Os c ill at io n Sta rt Timing
tXH
tXcyc
XTAL external clock input VCC × 0.5
tXL
tXr tXf
Main clock oscillator output
MOSCCR.MOSTP
tMAINOSC
LOCO clock oscillator output
LOCOCR.LCSTP
tLOCO
IWDT-dedicated clock oscillator output
ILOCOCR.ILCSTP
tILOCO
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RX113 Group 5. Electrical Characteristics
Figure 5.22 HOCO Clock Oscillation Start Timing (After Reset is Canceled by Setting
OFS1.HOCOEN Bit to 0)
Figure 5.23 HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting HOCOCR.HCSTP
Bit)
Figure 5.24 PLL Clock Oscillation Start Timing (PLL is Operated after Main Clock Oscillation Has
Settled)
Figure 5.25 Sub-Clock Oscillation Start Timing
RES#
Internal reset
HOCO clock
OFS1.HOCOEN
tRESWT
HOCO clock
HOCOCR.HCSTP
tHOCO
PLLCR2.PLLEN
PLL clock
MOSCCR.MOSTP
tMAINOSC
Main clock oscillator output
tPLL
Sub-cl ock osci llator out put
SOSCCR.SOSTP
tSUBOSC
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Mar 31, 2016
RX113 Group 5. Electrical Characteristics
5.3.2 Reset Timing
Note 1. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b.
Note 2. When OFS1.(STUPLVD1REN, FASTSTUP) ≠ 11b.
Note 3. When IWDTCR.CKS[3:0] = 0000b.
Figure 5.26 Reset Input Timing at Power-On
Figure 5.27 Reset Input Timing (1)
Figure 5.28 Reset Input Timing (2)
Table 5.23 Reset Timing
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test
Conditions
RES# pulse width At power-on tRESWP 3 — — ms Figure 5.26
Other than above tRESW 30 — — μs Figure 5.27
Wait time after RES#
cancellation
(at power-on)
At normal startup*1tRESWT — 8.5 — ms Figure 5.26
During fast startup time*2tRESWT — 560 — μs
Wait time after RES# cancellation
(during powered-on state) tRESWT —114— μs Figure 5.27
Independent watchdog timer reset period tRESWIW —1—IWDT
clock cycle Figure 5.28
Software reset period tRESWSW —1—ICLK cycle
Wait time after independent watchdog timer reset cancellation*3tRESW2 — 300 — μs
Wait time after software reset cancellation tRESW2 — 168 — μs
VCC
RES#
tRESWP
Internal reset
tRESWT
RES#
Internal reset
tRESWT
tRESW
Independent watchdog timer reset
Software reset
Internal reset
tRESWT2
tRESWIW, tRESWSW
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Mar 31, 2016
RX113 Group 5. Electrical Characteristics
5.3.3 Timing of Recovery from Low Power Consumption Modes
Note: When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1.
Note 1. The recovery time varies depending on the state of each oscillator when the WAIT instruction is executed. The recovery time
when multiple oscillators are operating varies depending on the operating state of the oscillators that are not selected as the
system clock source. This applies when only the oscillator listed in each item is operating and the other oscillators are stopped.
Note 2. When the frequency of the crystal is 20 MHz.
When the main clock oscillator wait control register (MOSCWTCR) is set to 04h.
Note 3. When the frequency of PLL is 32 MHz.
When the main clock oscillator wait control register (MOSCWTCR) is set to 04h.
Note 4. When the frequency of the external clock is 20 MHz.
When the main clock oscillator wait control register (MOSCWTCR) is set to 00h.
Note 5. When the frequency of PLL is 32 MHz.
When the main clock oscillator wait control register (MOSCWTCR) is set to 00h.
Note 6. When the frequency of HOCO is 32 MHz.
When the high-speed clock oscillator wait control register (HOCOWTCR) is set to 05h.
Note: When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1.
Note 1. The recovery time varies depending on the state of each oscillator when the WAIT instruction is executed. The recovery time
when multiple oscillators are operating varies depending on the operating state of the oscillators that are not selected as the
system clock source. This applies when only the oscillator listed in each item is operating and the other oscillators are stopped.
Note 2. When the frequency of the crystal is 12 MHz.
When the main clock oscillator wait control register (MOSCWTCR) is set to 04h.
Note 3. When the frequency of PLL is 12 MHz.
When the main clock oscillator wait control register (MOSCWTCR) is set to 04h.
Note 4. When the frequency of the external clock is 12 MHz.
When the main clock oscillator wait control register (MOSCWTCR) is set to 00h.
Note 5. When the frequency of PLL is 12 MHz.
When the main clock oscillator wait control register (MOSCWTCR) is set to 00h.
Table 5.24 Timing of Recovery from Low Power Consumption Modes (1)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test
Conditions
Recovery time
from software
standby
mode*1
High-speed
mode Crystal
connected to
main clock
oscillator
Main clock oscillator
operating*2tSBYMC — 2 3 ms Figure 5.29
Main clock oscillator and PLL
circuit operating*3tSBYPC —2 3ms
External clock
input to main
clock oscillator
Main clock oscillator
operating*4tSBYEX —3550μs
Main clock oscillator and PLL
circuit operating*5tSBYPE —7095μs
Sub-clock oscillator operating tSBYSC — 650 800 μs
HOCO clock oscillator operating*6tSBYHO —4055μs
LOCO clock oscillator operating tSBYLO —4055μs
Table 5.25 Timing of Recovery from Low Power Consumption Modes (2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test
Conditions
Recovery time
from software
standby
mode*1
Middle-speed
mode Crystal
connected to
main clock
oscillator
Main clock oscillator
operating*2tSBYMC — 2 3 ms Figure 5.29
Main clock oscillator and PLL
circuit operating*3tSBYPC —2 3ms
External clock
input to main
clock oscillator
Main clock oscillator
operating*4tSBYEX —3 4μs
Main clock oscillator and PLL
circuit operating*5tSBYPE —6585μs
Sub-clock oscillator operating tSBYSC — 600 750 μs
HOCO clock oscillator operating*6tSBYHO —4050μs
LOCO clock oscillator operating tSBYLO —4.8 7 μs
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RX113 Group 5. Electrical Characteristics
Note 6. When the frequency of HOCO is 8 MHz.
When the high-speed clock oscillator wait control register (HOCOWTCR) is set to 05h.
Note: When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1.
Note 1. The sub-clock continues oscillating in software standby mode during low-speed mode.
Figure 5.29 Software Standby Mode Recovery Timin g
Table 5.26 Timing of Recovery from Low Power Consumption Modes (3)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test
Conditions
Recovery time
from software
standby mode*1
Low-speed
mode Sub-clock oscillator operating tSBYSC — 600 750 μs Figure 5.29
Oscillator
ICLK
IRQ
Software st a ndby mode
tSBYMC, tSBYPC, tSBYEX,
tSBYPE, tSBYHO, tSBYLO
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RX113 Group 5. Electrical Characteristics
Note: When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1.
Note 1. Oscillators continue oscillating in deep sleep mode.
Note 2. When the frequency of the system clock is 32 MHz.
Note 3. When the frequency of the system clock is 12 MHz.
Note 4. When the frequency of the system clock is 32.768 kHz.
Figure 5.30 Deep Sleep Mode Recovery Timing
Note: When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1.
Table 5.27 Timing of Recovery from Low Power Consumption Modes (4)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Recovery time from deep
sleep mode*1High-speed mode*2tDSLP —23.5μs
Middle-speed mode*3tDSLP —3 4μs
Low-speed mode*4tDSLP — 400 500 μs
Table 5.28 Timing of Recovery from Low Power Consumption Modes (5)
Operating Mode Transition Time
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Mode before Transition Mode after Transition ICLK Frequency Transition Time Unit
Min. Typ. Max.
High-speed operating mode Middle-speed operating mode 8 MHz — 10 — μs
Middle-speed operating mode High-speed operating mode 8 MHz — 37.5 — μs
Low-speed operating mode Middle-speed operating mode,
high-speed operating mode 32.768 kHz — 213.62 — μs
Middle-speed operating mode,
high-speed operating mode Low-speed operating mode 32.768 kHz — 183.11 — μs
Oscillator
ICLK
IRQ
Deep sleep mode
tDSLP
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RX113 Group 5. Electrical Characteristics
5.3.4 Control Signal Timing
Note: 200 ns minimum in software standby mode.
Note 1. tPcyc indicates the cycle of PCLKB.
Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).
Figure 5.31 NMI Interrupt Input Timing
Figure 5.32 IRQ Interrupt Input Timing
Table 5.29 Control Signal Timing
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
NMI pulse
width tNMIW 200 — — ns NMI digital filter disabled
(NMIFLTE.NFLTEN = 0) tPcyc × 2 ≤ 200 ns
tPcyc × 2*1—— t
Pcyc × 2 > 200 ns
200 — — NMI digital filter enabled
(NMIFLTE.NFLTEN = 1) tNMICK × 3 ≤ 200 ns
tNMICK × 3.5*2—— t
NMICK × 3 > 200 ns
IRQ pulse
width tIRQW 200 — — ns IRQ digital filter disabled
(IRQFLTE0.FLTENi = 0) tPcyc × 2 ≤ 200 ns
tPcyc × 2*1—— t
Pcyc × 2 > 200 ns
200 — — IRQ digital filter enabled
(IRQFLTE0.FLTENi = 1) tIRQCK × 3 ≤ 200 ns
tIRQCK × 3.5*3—— t
IRQCK × 3 > 200 ns
NMI
tNMIW
IRQ
tIRQW
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RX113 Group 5. Electrical Characteristics
5.3.5 Timing of On-Chip Peripheral Modules
Note 1. tPcyc: PCLK cycle
Note 2. tcac: CAC count clock source cycle
Note 3. When the LOCO is selected as the clock output source (CKOCR.CKOSEL[2:0] bits = 000b), set the clock output division ratio
selection to divided by 2 (CKOCR.CKODIV[2:0] bits = 001b).
Note 4. When the XTAL external clock input or an oscillator is used with divided by 1 (CKOCR.CKOSEL[2:0] bits = 010b and
CKOCR.CKODIV[2:0] bits = 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%.
Table 5.30 Timing of On-Chip Peripheral Modules (1)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Max. Unit*1Test
Conditions
I/O ports Input data pulse width tPRW 1.5 — tPcyc Figure 5.33
MTU2 Input capture input pulse width Single-edge setting tTICW 1.5 — tPcyc Figure 5.34
Both-edge setting 2.5 —
Timer clock pulse width Single-edge setting tTCKWH,
tTCKWL
1.5 — tPcyc Figure 5.35
Both-edge setting 2.5 —
Phase counting mode 2.5 —
POE POE# input pulse width tPOEW 1.5 — tPcyc Figure 5.36
TMR Timer clock pulse width Asynchronous tTMCWH,
tTMCWL
1.5 — tPcyc Figure 5.37
Clock synchronous 2.5 —
SCI Input clock cycle Asynchronous tScyc 4—t
Pcyc Figure 5.38
Clock synchronous 6 —
Input clock pulse width tSCKW 0.4 0.6 tScyc
Input clock rise time tSCKr —20ns
Input clock fall time tSCKf —20ns
Output clock cycle Asynchronous tScyc 16 — tPcyc Figure 5.39
C = 30 pF
Clock synchronous 4 —
Output clock pulse width tSCKW 0.4 0.6 tScyc
Output clock rise time tSCKr —20ns
Output clock fall time tSCKf —20ns
Transmit data delay
time (master) Clock synchronous tTXD —40ns
Transmit data delay
time (slave) Clock
synchronous 2.7 V or above — 65 ns
1.8 V or above — 100 ns
Receive data setup
time (master) Clock
synchronous 2.7 V or above tRXS 65 — ns
1.8 V or above 90 — ns
Receive data setup
time (slave) Clock synchronous 40 — ns
Receive data hold
time Clock synchronous tRXH 40 — ns
A/D converter Trigger input pulse width tTRGW 1.5 — tPcyc Figure 5.40
CAC CACREF input pulse width tPcyc ≤ tcac*2tCACREF 4.5 tcac + 3 tPcyc —ns
tPcyc > tcac*25 tcac + 6.5 tPcyc
CLKOUT CLKOUT pin output cycle*4VCC = 2.7 V or above tCcyc 125 — ns Figure 5.41
VCC = 1.8 V or above 250
CLKOUT pin high pulse width*3VCC = 2.7 V or above tCH 35 — ns
VCC = 1.8 V or above 70
CLKOUT pin low pulse width*3VCC = 2.7 V or above tCL 35 — ns
VCC = 1.8 V or above 70
CLKOUT pin output rise time VCC = 2.7 V or above tCr —15ns
VCC = 1.8 V or above 30
CLKOUT pin output fall time VCC = 2.7 V or above tCf —15ns
VCC = 1.8 V or above 30
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RX113 Group 5. Electrical Characteristics
Note 1. tPcyc: PCLK cycle
Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)
Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)
Table 5.31 Timing of On-Chip Peripheral Modules (2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V,
Ta = –40 to +105°C, C = 30 pF
Item Symbol Min. Max. Unit Test
Conditions
RSPI RSPCK clock cycle Master tSPcyc 2 4096 tPcyc*1Figure 5.42
Slave 8 4096
RSPCK clock
high pulse width Master tSPCKWH (tSPcyc – tSPCKr –
tSPCKf)/2 – 3 —ns
Slave (tSPcyc – tSPCKr –
tSPCKf)/2 —
RSPCK clock
low pulse width Master tSPCKWL (tSPcyc – tSPCKr–
tSPCKf)/2 – 3 —ns
Slave (tSPcyc – tSPCKr –
tSPCKf)/2 —
RSPCK clock
rise/fall time Output 2.7 V or above tSPCKr,
tSPCKf
—10ns
1.8 V or above —15
Input —1μs
Data input setup time Master 2.7 V or above tSU 10 — ns Figure 5.43
to
Figure 5.48
1.8 V or above 30 —
Slave 25 – tPcyc —
Data input hold time Master RSPCK set to a division
ratio othe r than PCLKB
divided by 2
tHtPcyc —ns
RSPCK set to PCLKB
divided by 2 tHF 0—
Slave tH20 + 2 × tPcyc —
SSL setup time Master tLEAD –30 + N*2 ×
tSPcyc
—ns
Slave 2—t
Pcyc
SSL hold time Master tLAG –30 + N*3 ×
tSPcyc
—ns
Slave 2—t
Pcyc
Data output delay time Master 2.7 V or above tOD —14ns
1.8 V or above —30
Slave 2.7 V or above —3 × t
Pcyc + 65
1.8 V or above —3 × t
Pcyc +105
Data output hold time Master 2.7 V or above tOH 0—ns
1.8 V or above –20 —
Slave 0—
Successive
transmissi on delay
time
Master tTD tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 ×
tPcyc
ns
Slave 4 × tPcyc —
MOSI and MISO rise/
fall time Output 2.7 V or above tDr, tDf —10ns
1.8 V or above —20
Input —1μs
SSL rise/fall time Output tSSLr,
tSSLf
—20ns
Input —1μs
Slave access t ime 2.7 V or above tSA —6t
Pcyc Figure 5.47,
Figure 5.48
1.8 V or above —7
Slave output release time 2. 7 V or above tREL —5t
Pcyc
1.8 V or above —6
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RX113 Group 5. Electrical Characteristics
Note 1. tPcyc: PCLK cycle
Table 5.32 Timing of On-Chip Peripheral Modules (3)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V,
Ta = –40 to +105°C, C = 30 pF
Item Symbol Min. Max. Unit*1Test
Conditions
Simple
SPI SCK clock cycle output (master) tSPcyc 4 65536 tPcyc Figure 5.42
SCK clock cycle input (slave) 6 65536 tPcyc
SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc
SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc
SCK clock rise/fall time tSPCKr, tSPCKf —20ns
Data input setup time (master) 2.7 V or above tSU 65 — ns Figure 5.43,
Figure 5.45
1.8 V or above 95 —
Data input setup time (slave) 40 —
Data input hold time tH40 — ns
SS input setup time tLEAD 3—t
SPcyc
SS input hold time tLAG 3—t
SPcyc
Data output delay time (master) tOD —40ns
Data output delay time (slave) 2.7 V or above — 65
1.8 V or above — 100
Data output hold time (master) 2.7 V or above tOH –10 — ns
1.8 V or above –20 —
Data output hold time (slave) –10 —
Data rise/fall time tDr, tDf —20ns
SS input rise/fall time tSSLr, tSSLf —20ns
Slave access time tSA —6t
Pcyc Figure 5.47,
Figure 5.48
Slave output release time tREL —6t
Pcyc
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RX113 Group 5. Electrical Characteristics
Note: tIICcyc: RIIC internal reference count clock (IICφ) cycle
Note 1. The value in parentheses is used when the ICMR3.NF[1:0] bits are set to 11b while a digital filter is enabled with the ICFER.NFE
bit = 1.
Note 2. The minimum tsr and tsf specifications for fast mode are not set.
Table 5.33 Timing of On-Chip Peripheral Modules (4)
Conditions: 2.7 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz,
Ta = –40 to +105°C
Item Symbol Min.*1Max. Unit Test
Conditions
RIIC
(S tandard mode,
SMBus)
SCL0 input cycle time tSCL 6 (12) × tIICcyc + 1300 — ns Figure 5.49
SCL0 input high pulse width tSCLH 3 (6) × tIICcyc + 300 — ns
SCL0 input low pulse width tSCLL 3 (6) × tIICcyc + 300 — ns
SCL0, SDA0 input rise time tSr — 1000 ns
SCL0, SDA0 input fall time tSf — 300 ns
SCL0, SDA0 input spike pulse removal
time tSP 0 1 (4) × tIICcyc ns
SDA0 input bus free time tBUF 3 (6) × tIICcyc + 300 — ns
START condition input hold time tSTAH tIICcyc + 300 — ns
Repeated START condition input setup
time tSTAS 1000 — ns
STOP condition input setup time tSTOS 1000 — ns
Data input setup time tSDAS tIICcyc + 50 — ns
Data input hold time tSDAH 0—ns
SCL0, SDA0 capacitive load Cb— 400 pF
RIIC
(Fast mode) SCL0 input cycle time tSCL 6 (12) × tIICcyc + 600 — ns Figure 5.49
SCL0 input high pulse width tSCLH 3 (6) × tIICcyc + 300 — ns
SCL0 input low pulse width tSCLL 3 (6) × tIICcyc + 300 — ns
SCL0, SDA0 input rise time tSr —*2300 ns
SCL0, SDA0 input fall time tSf —*2300 ns
SCL0, SDA0 input spike pulse removal
time tSP 0 1 (4) × tIICcyc ns
SDA0 input bus free time tBUF 3 (6) × tIICcyc + 300 — ns
START condition input hold time tSTAH tIICcyc + 300 — ns
Repeated START condition input setup
time tSTAS 300 — ns
STOP condition input setup time tSTOS 300 — ns
Data input setup time tSDAS tIICcyc + 50 — ns
Data input hold time tSDAH 0—ns
SCL0, SDA0 capacitive load Cb— 400 pF
R01DS0216EJ0110 Rev.1.10 Page 88 of 131
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RX113 Group 5. Electrical Characteristics
Note: tPcyc: PCLK cycle
Note 1. This applies when the SMR.CKS[1:0] bits = 00b and the SNFR.NFCS[2:0] bits = 010b while the SNFR.NFE bit = 1 and the
digital filter is enabled.
Table 5.34 Timing of On-Chip Peripheral Modules (5)
Conditions: 2.7 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz,
Ta = –40 to +105°C
Item Symbol Min. Max. Unit Test
Conditions
Simple I2C
(Standard mode) SDA0 input rise time tSr — 1000 ns Figure 5.49
SDA0 input fall time tSf — 300 ns
SDA0 input spike pulse removal time tSP 04 × t
pcyc*1ns
Data input setup time tSDAS 250 — ns
Data input hold time tSDAH 0—ns
SCL0, SDA0 capacitive load Cb— 400 pF
Simple I2C
(Fast mode) SCL0, SDA0 input rise time tSr — 300 ns Figure 5.49
SCL0, SDA0 input fall time tSf — 300 ns
SCL0, SDA0 input spike pulse removal time tSP 04 × t
pcyc*1ns
Data input setup time tSDAS 100 — ns
Data input hold time tSDAH 0—ns
SCL0, SDA0 capacitive load Cb— 400 pF
Table 5.35 Timing of On-Chip Peripheral Modules (6)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz,
Ta = –40 to +105°C
Item Symbol Min. Max. Unit Test
Conditions
SSI AUDIO_MCLK input
frequency 2.7 V or above tAUDIO 125MHz
1.8 V or above 1 4
Output clock cycle tO250 — ns Figure 5.50
Input clock cycle tI250 — ns
Clock high pulse width tHC 0.4 0.6 to, ti
Clock low pulse width tLC 0.4 0.6 to, ti
Clock rise time tRC —20ns
Data delay time 2.7 V or above tDTR — 65 ns Figure 5.51
Figure 5.52
1.8 V or above — 105
Setup time 2.7 V or above tSR 65 — ns
1.8 V or above 90 —
Hold time tHTR 40 — ns
WS changing edge SSIDATA output delay tDTRW — 105 ns Figure 5.53
R01DS0216EJ0110 Rev.1.10 Page 89 of 131
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RX113 Group 5. Electrical Characteristics
Figure 5.33 I/O Port Input Timing
Figure 5.34 MTU2 Input/Output Timing
Figure 5.35 MTU2 Clock Input Timing
Figure 5.36 POE# Input Timing
Port
PCLK
tPRW
Output
compare output
Input capture
input
PCLK
tTICW
MTCLKA to MTCLKD
PCLK
tTCKWL tTCKWH
POEn# input
PCLK
tPOEW
R01DS0216EJ0110 Rev.1.10 Page 90 of 131
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RX113 Group 5. Electrical Characteristics
Figure 5.37 TMR Clock Input Timing
Figure 5.38 SCK Clock Input Timing
Figure 5.39 SCI Input/Output Timing: Clock Synchronous Mode
PCLK
TMCI0 to TMCI3
tTMCWL tTMCWH
tSCKW tSCKr tSCKf
tScyc
SCKn
n = 0, 1, 2 , 5, 6, 8, 9 , 12
tTXD
tRXS tRXH
TXDn
RXDn
SCKn
n = 0, 1, 2, 5, 6, 8, 9, 12
R01DS0216EJ0110 Rev.1.10 Page 91 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.40 A/D Converter External Trigger Input Timing
Figure 5.41 CLKOUT Output Timing
Figure 5.42 RSPI Clock Timing and Simple SPI Clock Timing
ADTRG0#
PCLK
tTRGW
tCf
tCH
tCcyc
tCr
tCL
CLKOUT pin output
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF
SCKn
Master select output
SCKn
Slave select input
n = 0, 1, 2, 5, 6, 8, 9, 12
tSPCKWH
VOH VOH
VOL VOL
VOH VOH
tSPCKWL
tSPCKr tSPCKf
VOL
tSPcyc
tSPCKWH
VIH VIH
VIL VIL
VIH VIH
tSPCKWL
tSPCKr tSPCKf
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × V C C
RSPCKA
Master select output
RSPCKA
Slave select input
Simple SPIRSPI
R01DS0216EJ0110 Rev.1.10 Page 92 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.43 RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Set to Division Ratio Other Than
Divided by 2) and Simple SPI Timing (Master, CKPH = 1)
Figure 5.44 RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Set to Divided by 2)
tDr, tDf
tSU tH
tLEAD
tTD
tLAG tSSLr, tSSLf
tOH tOD
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LS B OUT IDLE MSB O UT
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
SMISOn
input
SMOSIn
output
n = 0, 1, 2, 5, 6, 8, 9, 12
Simple SPIRSPI
SSLA0 to
SSLA3
output
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
MISOA
input
MOSIA
output
SSLA0 to
SSLA3
output
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
MISOA
input
MOSIA
output
LSB IN
tDr, tDf
tSU tHF
tLEAD
tTD
tLAG tSSLr, tSSLf
tOH tOD
MSB IN
MSB OUT DATA LSB O U T IDL E MSB O UT
MSB IN DATA
tHF
R01DS0216EJ0110 Rev.1.10 Page 93 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.45 RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Set to Division Ratio Other Than
Divided by 2) and Simple SPI Timing (Master, CKPH = 0)
Figure 5.46 RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Set to Divided by 2)
SSLA0 to
SSLA3
output
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
MISOA
input
MOSIA
output
RSPI Simple SPI
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
SMISOn
input
SMOSIn
output
tDr, tDf
tSU tH
tLEAD
tTD
tLAG tSSLr, tSSLf
tOH
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
tOD
n = 0, 1, 2, 5, 6, 8, 9, 12
tDr, tDf
tHF
tLEAD
tTD
tLAG tSSLr, tSSLf
tOH
DATA MSB IN
MSB OUT DATA LSB OUT I DLE MSB OUT
tOD
SSLA0 to
SSLA3
output
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
MISOA
input
MOSIA
output
MSB IN LSB IN
tSU tH
R01DS0216EJ0110 Rev.1.10 Page 94 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.47 RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 1)
Figure 5.48 RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH = 0)
tDr, tDf
tSU tH
tLEAD
tTD
tLAG
tSA
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT MSB IN MSB OUT
tOH tOD tREL
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
SMISOn
output
SMOSIn
input
n = 0, 1, 2, 5, 6, 8, 9, 12
Simple SPIRSPI
SSLA0
input
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
MISOA
output
MOSIA
input
SSn#
input
tDr, tDf
tSA tOH
tLEAD
tTD
tLAG
tH
LSB OUT
(Last data) DATA MSB OUT
MSB IN DATA LSB IN MSB IN
LSB OUT
tSU
tOD tREL
MSB OUT
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
SMISOn
output
SMOSIn
input
n = 0, 1, 2, 5, 6, 8, 9, 12
Simple SPIRSPI
SSLA0
input
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
MISOA
output
MOSIA
input
SSn#
input
R01DS0216EJ0110 Rev.1.10 Page 95 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.49 R IIC Bus In te rfa ce In put/Output Timing and Simple I2C Bus Interface Input/Output
Timing
Figure 5.50 Clock Input/Output Timing
Figure 5.51 Transmission/Reception Timing (Synchronized with SSISCKn Rising Edge)
Test conditions
VIH = VCC × 0.7, VIL = VCC × 0.3
SDA0
SCL0
VIH
VIL
tSTAH tSCLH
tSCLL
P*1 S*1
tSf tSr
tSCL tSDAH
tSDAS
tSTAS tSP tSTOS
P*1
tBUF
Sr*1
Note 1. S, P, and Sr indicate the following conditi ons, respectively.
S: START condition
P: STOP condition
Sr: Repeated START condition
SSISCKn
tHC
tLC
tRC
tI, tO
tSR tHTR
tDTR
SSISCKn
(input or output )
SSIWSn, SSIDATAn,
SS IRXD n (input)
SSIWSn, SSIDATAn,
SSITXD n (output)
R01DS0216EJ0110 Rev.1.10 Page 96 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.52 Transmission/Reception Timing (Synchronized with SSISCKn Falling Edge)
Figure 5.53 SSIDATA Output Delay After SSIWSn Changing Edge
tSR tHTR
tDTR
SSISCKn
(input or output)
SSIWSn, SSIDATAn,
SSIRXDn (input)
SSIWSn, SSIDATAn,
SSITXDn (output)
tDTRW
SSIWSn (input)
SSIDAT An (ou t put)
Note. Timing to output the MSB bit during slave transmission from SSIWSn
when DEL = 1 and SDT A = 0 or DEL = 1 , SDTA = 1, and SWL[2:0] = DWL[2:0]
R01DS0216EJ0110 Rev.1.10 Page 97 of 131
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RX113 Group 5. Electrical Characteristics
5.4 USB Characteristics
Figure 5.54 USB0_DP and USB0_DM Output Timing
Table 5.36 USB Characteristics (USB0_DP and USB0_DM Pin Characteristics)
Conditions: 3.0 V ≤ VCC = VCC_USB ≤ 3.6 V, 3.0 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Max. Unit Test Conditions
Input
characteristics Input high level voltage VIH 2.0 — V
Input low level voltage VIL —0.8V
Differential input sensitivity VDI 0.2 — V | USB0_DP – USB0_DM |
Differential common mode
range VCM 0.8 2.5 V
Output
characteristics Output high level voltage VOH 2.8 VCC_USB V IOH = –200 μA
Output low level voltage VOL 0.0 0.3 V IOL = 2 mA
Cross-over voltage VCRS 1.3 2.0 V Figure 5.54
Figure 5.55
Rise time FS tr420ns
LS 75 300
Fall time FS tf420ns
LS 75 300
Rise/fall time ratio FS tr/tf90 111.11 % tr/tf
LS 80 125
Output resistance ZDRV 28 44 Ω(Adjusting the resistance
of external elements is
not necessary.)
VBUS
characteristics VBUS input voltage VIH VCC × 0.8 — V
VIL —VCC × 0.2V
VBUS (P16) input leakage
current | IVBUSIN |— 10μA USB0_VBUS = 5.5 V
Pull-up,
pull-down Pull-down resistor RPD 14.25 24.80 kΩ
Pull-up resistor RPUI 0.9 1.575 kΩDuring idle state
RPUA 1.425 3.09 kΩDuring reception
Battery Charging
Specification
Ver 1.2
USB0_DP sink current IDP_SINK 25 175 μA
USB0_DM sink current IDM_SINK 25 175 μA
DCD source current IDP_SRC 713μA
Data detection voltage VDAT_REF 0.25 0.4 V
USB0_DP source current VDP_SRC 0.5 0.7 V Output current = 250 μA
USB0_DM source current VDM_SRC 0.5 0.7 V Output current = 250 μA
USB0_DP,
USB0_DM
tf
tr
90% 10%10% 90%
VCRS
R01DS0216EJ0110 Rev.1.10 Page 98 of 131
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RX113 Group 5. Electrical Characteristics
Figure 5.55 Test Circuit
Observation point
50 pF
50 pF
USB0_DP
USB0_DM
Full- speed ( FS)
Observation point
200 pF to
600 pF
USB0_DP
USB0_DM
200 pF to
600 pF 3.6 V
Observation point
Low-speed (LS)
1.5 k
R01DS0216EJ0110 Rev.1.10 Page 99 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
5.5 A/D Conversion Characteristics
Note: The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not
include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling
states is indicated.
Note 2. The value in parentheses indicates the sampling time.
Table 5.37 A/D Conversion Characteristics (1)
Conditions: 2.7 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = VREF L0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Min. Typ. Max. Unit Test Conditions
Frequency 4 — 32 MHz
Resolution — — 12 Bit
Conversion time*1
(Operation at
PCLKD = 32 MHz)
Permissible signal
source impedance
(Max.) = 0.3 kΩ
1.031
(0.313)*2——μs High-precision channel
ADCSR.ADHSC bit = 1
ADSSTRn.SST[7:0] bits = 09h
1.375
(0.641)*2——μs Normal-precision channel
ADCSR.ADHSC bit = 1
ADSSTRn.SST[7:0] bits = 14h
Analog input effective range 0 — VREFH0 V
Offset error — ±0.5 ±4.5 LSB High-precision channel
PJ6PFS.ASEL bit = 1
PJ7PFS.ASEL bit = 1
±6.0 LSB Other than above
Full-scale error — ±0.75 ±4.5 LSB High-precision channel
PJ6PFS.ASEL bit = 1
PJ7PFS.ASEL bit = 1
±6.0 LSB Other than above
Quantization error — ±0.5 — LSB
Absolute accuracy — ±1.25 ±5.0 LSB High-precision channel
PJ6PFS.ASEL bit = 1
PJ7PFS.ASEL bit = 1
±8.0 LSB Other than above
DNL differential nonlinearity error — ±1.0 — LSB
INL integral nonlinearity error — ±1.0 ±3.0 LSB
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RX113 Group 5. Electrical Characteristics
Figure 5.56 AVCC0 to AVREFH0 Voltage Range
1.0 2.0 3.0 4.0 5.0 AVCC0
1.0
2.0
3.0
4.0
5.0
AVREFH0
1.8
1.8
2.7
3.6
2.4
2.4 2.7 3.6
Characteristics listed in
Table 5.37
A/D Conversion
Characteristics (1)
Characteristics listed in
Table 5.38
A/D Conversion
Characteristics (2)
Characteristics listed in
Table 5.39
A/D Conversion
Characteristics (3)
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RX113 Group 5. Electrical Characteristics
Note: The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not
include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling
states is indicated.
Note 2. The value in parentheses indicates the sampling time.
Note: The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not
include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling
states is indicated.
Note 2. The value in parentheses indicates the sampling time.
Table 5.38 A/D Conversion Characteristics (2)
Conditions: 2.4 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.4 V ≤ AVCC0 ≤ 3.6 V, 2.4 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = VREF L0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Min. Typ. Max. Unit Test Conditions
Frequency 4 — 16 MHz
Resolution — — 12 Bit
Conversion time*1
(Operation at
PCLKD = 16 MHz)
Permissible signal
source impedance
(Max.) = 1.0 kΩ
2.062
(0.625)*2——μs High-precision channel
ADCSR.ADHSC bit = 1
ADSSTRn.SST[7:0] bits = 09h
2.750
(1.313)*2——μs Normal-precision channel
ADCSR.ADHSC bit = 1
ADSSTRn.SST[7:0] bits = 14h
Analog input effective range 0 — VREFH0 V
Offset error — ±0.5 ±6.0 LSB
Full-scale erro r — ±1.25 ±6.0 LSB
Quantization error — ±0.5 — LSB
Absolute accuracy — ±3.0 ±8.0 LSB
DNL differential nonlinearity error — ±1.0 — LSB
INL integral nonlinearity error — ±1.5 ±3.0 LSB
Table 5.39 A/D Conversion Characteristics (3)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, 1.8 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = VREF L0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Min. Typ. Max. Unit Test Conditions
Frequency 1 — 8 MHz
Resolution — — 12 Bit
Conversion time*1
(Operation at
PCLKD = 8 MHz)
Permissible signal
source impedance
(Max.) = 5.0 kΩ
4.875
(1.250)*2——μs High-precision channel
ADCSR.ADHSC bit = 0
ADSSTRn.SST[7:0] bits = 09h
6.250
(2.625)*2——μs Normal-precision channel
ADCSR.ADHSC bit = 0
ADSSTRn.SST[7:0] bits = 14h
Analog input effective range 0 — VREFH0 V
Offset error — ±0.5 ±24.0 LSB
Full-scale error — ±1.25 ±24.0 LSB
Quantization error — ±0.5 — LSB
Absolute accuracy — ±2.75 ±32.0 LSB
DNL differential nonlinearity error — ±1.0 — LSB
INL integral nonlinearity error — ±1.25 ±12.0 LSB
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RX113 Group 5. Electrical Characteristics
Note: The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not
include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling
states is indicated.
Note 2. The value in parentheses indicates the sampling time.
Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V.
Note 2. The A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the A/D converter.
Table 5.40 A/D Conversion Characteristics (4)
Conditions: 2.0 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.0 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V,
ADHVREFCNT.OCSVSEL = 1 (internal reference voltage selected as high-side reference voltage),
PJ7PFS.ASEL = 0 (AVSS0 pin selected as low-side reference power supply ground pin)
Ta = –40 to +105°C
Item Min. Typ. Max. Unit Test Conditions
Frequency 1 — 2 MHz
Resolution — — 12 Bit
Internal reference voltage 1.36 1.43 1.50 V
Conversion time*1
(Operation at
PCLKD = 2 MHz)
Permissible signal
source impedance
(Max.) = 5.0 kΩ
16
(1.5)*2——μs High-precision channel
ADCSR.ADHSC bit = 0
ADSSTRn.SST[7:0] bits = 02h
17.5
(3.0)*2— — Normal-precision channel
ADCSR.ADHSC bit = 0
ADSSTRn.SST[7:0] bits = 05h
Analog input effective range 0 — Internal
reference
voltage
V
Offset error — — ±24.0 LSB
DNL differential nonlinearity error — ±16.0 — LSB
INL integral nonlinearity error — ±16.0 ±32.0 LSB
Table 5.41 A/D Converter Channel Classification
Classification Channel Conditions Remarks
High-precision channel AN000 to AN007, AN021 AVCC0 = 1.8 to 3.6 V Pins AN000 to AN007 and AN021
cannot be used as digital outputs
when the A/D converter is in use.
Normal-precision channel AN008 to AN015
Internal reference voltage input channel Internal reference voltage AVCC0 = 2.0 to 3.6 V
Temperature sensor input channel Temperature sensor output AVCC0 = 2.0 to 3.6 V
Table 5.42 A/D Internal Reference Voltage Characteristics
Conditions: 2.0 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.0 V ≤ AVCC0 ≤ 3.6 V*1, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Min. Typ. Max. Unit Test Conditions
Internal reference voltage input channel*21.36 1.43 1.50 V
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RX113 Group 5. Electrical Characteristics
Figure 5.57 Illustration of A/D Converter Charact eristic Terms
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of analog
input voltage (1-LSB width), that can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and if reference
voltage (VREFH0 = 3.072 V), then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, 1.5 mV, ... are used as analog
input voltages.
If analog input voltage is 6 mV, absolute accuracy = ±5 LSB means that the actual A/D conversion result is in the range
of 003h to 00Dh though an output code, 008h, can be expected from the theoretical A/D conversion characteristi cs.
Integral nonlinearity error (INL)
Integral nonl inearity error is the maximum deviatio n between the ideal line when the measured offset and full-scale
errors are zeroed, and the actual output code.
Integral nonlinearity
error (INL)
Actual A/D conversion
characteristic
Ideal A/D conversion
characteristic
Analog input voltage
Offset error
Absolute accuracy
Differential nonlinea rity error (DNL)
Full-scale error
FFFh
000h
0
Ideal line of actual A/D
conversion characteristic
1-LSB width fo r ideal A/D
conversion characteristic
Differential nonlin eari ty error (DNL)
1-LSB width for ideal A/D
conversion characteristic
VREFH0
(full-scale)
A/D converter
output code
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RX113 Group 5. Electrical Characteristics
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics
and the width of the actual output code.
Offset error
Offs et error is the dif ference between a transiti on poi nt of the ideal fi rst output code and the actual first output code.
Full-scale error
Full-scale error is the difference between a transition point of the ideal last output code and the actual last outpu t code.
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RX113 Group 5. Electrical Characteristics
5.6 D/A Conversion Characteristics
Note 1. There are restrictions on AVCC0 and VCC depending on the usage conditions for the 12-bit D/A converter and I/O ports.
When using ports J0 and J2 as DA0 and DA1 output, make sure that VCC ≥ D/A output voltage.
Note 1. There are restrictions on AVCC0 and VCC depending on the usage conditions for the 12-bit D/A converter and I/O ports.
When using ports J0 and J2 as DA0 and DA1 output, make sure that VCC ≥ D/A output voltage.
Table 5.43 D/A Conversion Characteristics (1)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, 1.8 V ≤ VREFH ≤ AVCC0, VSS = AVSS0 = VREF L =
VSS_USB = 0 V, T a = –40 to +105°C
Reference voltage = VREFH and VREFL selected
Item Min. Typ. Max. Unit Test Conditions
Resolution — — 12 Bit
Resistive load 30 — — kΩ
Capacitive load — — 50 pF
Output voltage range*10.35 — VREFH V VREFH ≤
AVCC0 - 0.47 V
0.35 — AVCC0 - 0.47 V VREFH >
AVCC0 - 0.47 V
DNL differential nonlinearity error — ±0.5 ±1.0 LSB
INL integral nonlinearity error — ±2.0 ±8.0 LSB
Offset error — — ±20 mV
Full-scale error — — ±20 mV
Output resistance — 75 — Ω
Conversion time — — 30 μs
Table 5.44 D/A Conversion Characteristics (2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 = VREFH ≤ 3.6 V, VSS = AVSS0 = VREFL = VSS_USB = 0 V,
Ta = –40 to +105°C
Reference voltage = AVCC0 and AVSS0 selected
Item Min. Typ. Max. Unit Test Conditions
Resolution — — 12 Bit
Resistive load 30 — — kΩ
Capacitive load — — 50 pF
Output voltage range*10.35 — AVCC0 - 0.47 V
DNL differential nonlinearity error — ±0.5 ±2.0 LSB
INL integral nonlinearity error — ±2.0 ±8.0 LSB
Offset error — — ±30 mV
Full-scale error — — ±30 mV
Output resistance — 75 — Ω
Conversion time — — 30 μs
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RX113 Group 5. Electrical Characteristics
Table 5.45 D/A Conversion Characteristics (3)
Conditions: 2.0 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.0 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Reference voltage = internal reference voltage selected
Item Min. Typ. Max. Unit Test Conditions
Resolution — — 12 Bit
Internal reference voltage (Vbgr) 1.36 1.43 1.50 V
Resistive load 30 — — kΩ
Capacitive load — — 50 pF
Output voltage range 0.35 — Vbgr V
DNL differential nonlinearity error — ±2.0 ±16.0 LSB
INL integral nonlinearity error — ±8.0 ±16.0 LSB
Offset error — — ±30 mV
Output resistance — 75 — Ω
Conversion time — — 30 μs
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RX113 Group 5. Electrical Characteristics
Figure 5.58 Illustration of D/A Converter Charact eristic Terms
Integral nonlinearity error (INL)
Integral nonl inearity error is the maximum deviatio n between the ideal output voltage based on the ideal conversion
characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion
characteristics and the width of the actual output voltage.
Offset error
Offs et error is the dif ference between the highest actua l out put voltage that falls below the lower ou tput limit and the
ideal output voltage based on the input code.
Full-scale error
Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the
ideal output voltage based on the input code.
000h D/A converter input code FFFh
Output analog voltage
Upper output limit
Lower output limit
Offset error
Ideal output voltage
1-LSB width for ideal D/A conversion
characteristic
Differential nonlinearity error
(DNL)
Actual D/A conversion characteristic
*1
Integral nonlinearity error (INL)
Full-scale error Gain error
Offset error
Ideal output volt age
Note 1. Ideal D/A conversion output voltage that is adjust ed so that of fset and full scale errors are zeroed.
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RX113 Group 5. Electrical Characteristics
5.7 Temperature Sensor Characteristics
5.8 Comparator Characteristics
Table 5.46 Temperature Sensor Characteristics
Conditions: 2.0 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.0 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Relative accuracy ――±1.5 ―°C 2.4 V or above
―±2.0 ―Below 2.4 V
Temperature slope ――–3.65 ―mV/°C
Output voltage (25°C) ――1.05 ―V VCC = 3.3 V
Temperature sensor start time tSTART ―― 5μs
Sampling time ―5――μs
Table 5.47 Comparator Characteristics
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
CVREFB0 or CVREFB1 input reference voltage VREF 0 — VCC - 1.4 V
CMPB0 or CMPB1 input voltage VI –0.3 — VCC + 0.3 V
Offset Comparator high-speed mode — — — 50 mV
Comparator high-speed mode
Window function enabled —— — 60mV
Comparator low-speed mode — — — 40 mV
Comparator
output delay time Comparator high-speed mode Td — — 1.2 μsVCC = 3 V,
input slew rate
≥ 50 mV/us
Comparator high-speed mode
Window function enabled Tdw — — 2 μs
Comparator low-speed mode Td — — 5 μs
High-side reference voltage
(comparator high-speed mode, window function
enabled)
VRFH — 0.76 VCC — V
Low-side reference voltage
(comparator high-speed mode, window function
enabled)
VRFL — 0.24 VCC — V
Operation stabilization wait time Tcmp 100 — — μs
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RX113 Group 5. Electrical Characteristics
Figure 5.59 Comparator Output Delay Time in Comparator High-Speed Mode and Low-Speed Mode
Figure 5.60 Comparator Output Delay Time in High-Speed Mode with Window Function Enabled
CMPB
CMPOB
td td
CVREFB = 0 V
CMPB
CMPOB
tdw tdw
Internal vrh = V C C * 0.76
CMPB
CMPOB
tdw tdw
Internal vrh = V C C * 0.24
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RX113 Group 5. Electrical Characteristics
5.9 LCD Characteristics
5.9.1 External Resistance Division Method
(1) Static Display Mode
(2) 1/2 Bias Method, 1/4 Bias Method
(3) 1/3 Bias Method
Table 5.48 LCD Characteristics
Conditions: 2.0 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.0 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
LCD drive voltage VL4 2.0 ―VCC V
Table 5.49 LCD Characteristics
Conditions: 2.7 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
LCD drive voltage VL4 2.7 ―VCC V
Table 5.50 LCD Characteristics
Conditions: 2.5 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.5V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
LCD drive voltage VL4 2.5 ―VCC V
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RX113 Group 5. Electrical Characteristics
5.9.2 Internal Voltage Boosting Method
(1) 1/3 Bias Method
Note 1. This is the required wait time from when the r eference voltage is specified by the VLCD register (or when the internal voltage
boosting method is selected (LCDM0.MDSET1 and MDSET0 = 01b) if the default reference voltage value is used) until voltage
boosting starts (VLCON = 1).
Note 2. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
Table 5.51 Internal Voltage Boosting Method
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test
Conditions
External capacitance connected between CAPH and CAPL pins C1 0.33 0.47 0.61 μF
External capacitor connected to VL1 pin C2 0.33 0.47 0.61 μF
External capacitor connected to VL2 pin C3 0.33 0.47 0.61 μF
External capacitor connected to VL3 pin C4 0.33 0.47 0.61 μF
External capacitor connected to VL4 pin C5 0.33 0.47 0.61 μF
Table 5.52 Internal Voltage Boosting Method LCD Characteristics
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Conditions Min. Typ. Max. Unit Test
Conditions
LCD output voltage
variation range VL1 C1 to C4
connected VLCD = 04h 0.9 1.0 1.08 V
VLCD = 05h 0.95 1.05 1.13 V
VLCD = 06h 1 1.1 1.18 V
VLCD = 07h 1.05 1.15 1.23 V
VLCD = 08h 1.1 1.2 1.28 V
VLCD = 09h 1.15 1.25 1.33 V
VLCD = 0Ah 1.2 1.3 1.38 V
VLCD = 0Bh 1.25 1.35 1.43 V
VLCD = 0Ch 1.3 1.4 1.48 V
VLCD = 0Dh 1.35 1.45 1.53 V
VLCD = 0Eh 1.4 1.5 1.58 V
VLCD = 0Fh 1.45 1.55 1.63 V
VLCD = 10h 1.5 1.6 1.68 V
VLCD = 11h 1.55 1.65 1.73 V
VLCD = 12h 1.6 1.70 1.78 V
VLCD = 13h 1.65 1.75 1.83 V
Doubler output voltage VL2 C1 to C3, C5 connected 2VL1 - 0.10 2VL1 2VL1 V
Tripler output voltage VL3 C1 to C5 connected 3VL1 - 0.15 3VL1 3VL1 V
Reference voltage
setup time*1tVL1S 5——ms
LCD output voltage
variation range*2tVLWT C1 to C4 connected 500 — — ms
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RX113 Group 5. Electrical Characteristics
(2) 1/4 Bias Method
Note 1. This is the required wait time from when the r eference voltage is specified by the VLCD register (or when the internal voltage
boosting method is selected (LCDM0.MDSET1 and MDSET0 = 01b) if the default reference voltage value is used) until voltage
boosting starts (VLCON = 1).
Note 2. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
Table 5.53 Internal Voltage Boosting Method LCD Characteristics
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Conditions Min. Typ. Max. Unit Test
Conditions
LCD output voltage
variation range VL1 C1 to C4
connected VLCD = 04h 0.9 1.0 1.08 V
VLCD = 05h 0.95 1.05 1.13 V
VLCD = 06h 1 1.1 1.18 V
VLCD = 07h 1.05 1.15 1.23 V
VLCD = 08h 1.1 1.2 1.28 V
VLCD = 09h 1.15 1.25 1.33 V
VLCD = 0Ah 1.2 1.3 1.38 V
Doubler output voltage VL2 C1 to C5 connected 2VL1 - 0.08 2VL1 2VL1 V
Tripler output voltage VL3 C1 to C5 connected 3VL1 - 0.12 3VL1 3VL1 V
Quadruply output voltage VL4 C1 to C5 connected 4VL1 - 0.16 4VL1 4VL1 V
Reference voltage setup
time*1tVL1S 5——ms
Voltage boost wait time*2tVLWT C1 to C5 connected 500 — — ms
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RX113 Group 5. Electrical Characteristics
5.9.3 Capacitor Split Method
(1) 1/3 Bias Method
Note 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).
Figure 5.61 LCD Refe renc e Vo lta g e Set up T ime , Voltage Boosting Wait Time, and Capacitor Split
Wait Time
Table 5.54 Capacitor Split Method
Conditions: 2.2 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.2 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test
Conditions
External capacitance connected between CAPH and CAPL pins C1 0.33 0.47 0.61 μF
External capacitor connected to VL1 pin C2 0.33 0.47 0.61 μF
External capacitor connected to VL2 pin C3 0.33 0.47 0.61 μF
External capacitor connected to VL3 pin C4 0.33 0.47 0.61 μF
External capacitor connected to VL4 pin C5 0.33 0.47 0.61 μF
Table 5.55 Capacitor Split Method LCD Character istics
Conditions: 2.2 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.2 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Conditions Min. Typ. Max. Unit Test
Conditions
VL4 voltage*1VL4 C1 to C4 connected — VCC — V
VL2 voltage*1VL2 C1 to C4 connected 2/3VL4-0.07 2/3VL4 2/3VL4+0.07 V
VL1 voltage**1VL1 C1 to C4 connected 1/3VL4-0.08 2/3VL4 2/3VL4+0.08 V
Capacitor split wait time*1tWAIT 100 — — ms
00b 01b or 10b
tVL1S
tVLWT, tWAIT
MDSET1,
MDSET0
VLCON
LCDON
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RX113 Group 5. Electrical Characteristics
5.10 CTSU Characteristics
Table 5.56 CTSU Characteristics
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test
Conditions
External capacitance connected to TSCAP pin Ctscap 91011nF
TS pin capacitive load Cbase — — 50 pF
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RX113 Group 5. Electrical Characteristics
5.11 Power-On Reset Circuit and Voltage Detection Circuit Characteristics
Note: These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD2), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
Note 1. n in the symbol Vdet1_n denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.
Note: These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD1), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
Note 1. n in the symbol Vdet2_n denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 2. Vdet2_3 selection can be used only when the CMPA2 pin input voltage is selected and cannot be used when the power supply
voltage (VCC) is selected.
Note 3. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b.
Note 4. When OFS1.(STUPLVD1REN, FASTSTUP) ≠ 11b.
Note 5. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,
Vdet1, and Vdet2 for the POR/LVD.
Table 5.57 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (1)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Voltage detection level Power-on reset (POR) VPOR 1.35 1.50 1.65 V Fig ur e 5.62, Figure 5.63
Voltage detection circuit
(LVD1)*1Vdet1_4 3.00 3.10 3.20 V F igure 5.64
At falling edge VC C
Vdet1_5 2.91 3.00 3.09
Vdet1_6 2.81 2.90 2.99
Vdet1_7 2.70 2.79 2.88
Vdet1_8 2.60 2.68 2.76
Vdet1_9 2.50 2.58 2.66
Vdet1_A 2.40 2.48 2.56
Vdet1_B 1.99 2.06 2.13
Vdet1_C 1.90 1.96 2.02
Vdet1_D 1.80 1.86 1.92
Table 5.58 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Voltage detection
level Voltage detection circuit
(LVD2)*1Vdet2_0 2.71 2.90 3.09 V Figure 5.65
At falling edge VCC
Vdet2_1 2.43 2.60 2.77
Vdet2_2 1.87 2.00 2.13
Vdet2_3*21.69 1.80 1.91
W a it time after
power-on reset
cancellation
At normal startup*3tPOR ―9.1 ―ms Figure 5.63
During fast startup time*4tPOR ―1.6 ―
Wait time after voltage
monitoring 1 reset
cancellation
Power-on voltage monitoring
1 reset disabled*3tLVD1 ―568 ―μsFigure 5.64
Power-on voltage monitoring
1 reset enab led*4―100 ―
Wait time after voltage monitoring 2 reset cancellation tLVD2 ―100 ―μsFigure 5.65
Response delay time tdet ――350 μsFigure 5.62
Minimum VCC down time*5tVOFF 350 ――μsFigure 5.62, VCC = 1.0 V or above
Power-on reset enable time tW (PO R) 1――ms Figure 5.63, VCC = below 1.0 V
LVD operation stabilization time (after LVD is enabled) Td (E-A) ――300 μsFigure 5.64, Figure 5.65
Hysteresis width (LVD1 and LVD2) VLVH ―70 ―mV Vdet1_4 selecte d
―60 ―Vdet1_5 to 9, LVD2 selected
―50 ―When select ion is from among Vdet1_A to B.
―40 ―When selection is from among Vdet1_C to D.
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RX113 Group 5. Electrical Characteristics
Figure 5.62 Voltage Detection Reset Timing
Figure 5.63 Power-On Reset Timing
Internal reset signal
(active-low)
VCC tVOFF
tPOR
tdet
VPOR
tdet
1.0 V
Internal reset signal
(active-low)
VCC
tPOR
VPOR
1.0 V
tw(POR)
*1
tdet
Note 1. tw(por) is the time required for a power-on reset to be enabled while the external power VCC is being held below the
valid voltage (1.0 V).
When VCC turns on, maintain tw(por) for 1.0 ms or more.
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RX113 Group 5. Electrical Characteristics
Figure 5.64 Voltage Detection Circuit Timing (Vdet1)
Figure 5.65 Voltage Detection Circuit Timing (Vdet2)
tVOFF
Vdet1
VCC
tdet
tdet
tLVD1
Td(E-A)
LVD1E
LVD1
Comparator output
LVD1CMPE
LVD1MON
Internal reset signal
(active-low)
When LVD1RN = L
When LVD1RN = H
VLVH
tLVD1
tVOFF
Vdet2
VCC
tdet
tdet
tLVD2
Td(E-A)
LVD2E
LVD2
Comparator output
LVD2CMPE
LVD2MON
Internal reset signal
(active-low)
When LVD2RN = L
When LVD2RN = H
VLVH
tLVD2
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RX113 Group 5. Electrical Characteristics
5.12 Oscillation Stop Detection Timing
Figure 5.66 Oscillation Stop Detection Timing
Table 5.59 Oscillation Stop Detection Circuit Characteristics
Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Detection time tdr — — 1 ms Figure 5.66
tdr
Main clock or PLL clock
OSTDSR.OSTDF
LOCO clock
ICLK
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RX113 Group 5. Electrical Characteristics
5.13 ROM (Flash Memory for Code Storage) Characteristics
Note 1. Definition of reprogram/erase cycle: The reprogram/erase cycle is the number of erasing for each block. When the reprogram/
erase cycle is n times (n = 1000), erasing can be performed n times for each block. For instance, when 4-byte programming is
performed 256 times for different addresses in 1-Kbyte block and then the entire block is erased, the reprogram/erase cycle is
counted as one. However, programming the same address for several times as one erasing is not enabled (overwriting is
prohibited).
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided from Renesas Electronics.
Note 3. This result is obtained from reliability testing.
Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software.
Note: The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note: The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source.
Table 5.60 ROM (Flash Memory for Code Storage) Characteristics (1)
Item Symbol Min. Typ. Max. Unit Conditions
Reprogramming/erasure cycle*1NPEC 1000 — — Times
Data hold time After 1000 times of NPEC tDRP 20*2, *3— — Year Ta = +85°C
Table 5.61 ROM (Flash Memory for Code Storage) Characteristics (2)
High-speed operating mode Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V
Temperature range for the programming/erasure operation: Ta = –40 to +105°C
Item Symbol FCLK = 1 MHz FCLK = 32 MHz Unit
Min. Typ. Max. Min. Typ. Max.
Programming time 4-byte tP4 — 103 931 — 52 489 μs
Erasure time 1-Kbyte tE1K — 8.23 267 — 5.48 214 ms
256-Kbyte tE256K — 407 925 — 39 457 ms
Blank check time 4-byte tBC4 — — 48 — — 15.9 μs
1-Kbyte tBC1K — — 1.58 — — 0.127 ms
Erase operation forcible stop time tSED — — 21.6 — — 12.8 μs
Start-up area switching setting time tSAS — 12.6 543 — 6.16 432 ms
Access window time tAWS — 12.6 543 — 6.16 432 ms
ROM mode transition wait time 1 tDIS 2——2——μs
ROM mode transition wait time 2 tMS 5——5——μs
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RX113 Group 5. Electrical Characteristics
Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software.
Note: The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note: The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source.
Table 5.62 ROM (Flash Memory for Code Storage) Characteristics (3)
Middle-speed operating mode Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V
Temperature range for the programming/erasure operation: Ta = –40 to +85°C
Item Symbol FCLK = 1 MHz FCLK = 8 MHz Unit
Min. Typ. Max. Min. Typ. Max.
Programming time 4-byte tP4 — 143 1330 — 96.8 932 μs
Erasure time 1-Kbyte tE1K — 8.3 269 — 5.85 219 ms
256-Kbyte tE256K — 407 928 — 93 520 ms
Blank check time 4-byte tBC4 ——78—— 50 μs
1-Kbyte tBC1K — — 1.61 — — 0.369 ms
Erase operation forcible stop time tSED — — 33.6 — — 25.6 μs
Start-up area switching setting time tSAS — 13.2 549 — 7.6 445 ms
Access window time tAWS — 13.2 549 — 7.6 445 ms
ROM mode transition wait time 1 tDIS 2——2— — μs
ROM mode transition wait time 2 tMS 3——3— — μs
R01DS0216EJ0110 Rev.1.10 Page 121 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
5.14 E2 DataFlash Characteristics
Note 1. The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 100000),
erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1000 times for different
addresses in 1-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided from Renesas Electronics.
Note 3. These results are obtained from reliability testing.
Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software.
Note: The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note: The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source.
Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software.
Note: The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note: The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source.
Table 5.63 E2 DataFlash Characteristics (1)
Item Symbol Min. Typ. Max. Unit Conditions
Reprogramming/erasure cycle*1NDPEC 100000 1000000 — Times
Data hold time After 10000 times of NDPEC tDDRP 20*2, *3— — Year Ta = +85°C
After 100000 times of NDPEC 5*2, *3— — Year
After 1000000 times of NDPEC —1*
2, *3— Year Ta = +25°C
Table 5.64 E2 DataFlash Characteristics (2)
: high-speed operating mode
Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V
Temperature range for the programming/erasure operation: Ta = –40 to +105°C
Item Symbol FCLK = 1 MHz FCLK = 32 MHz Unit
Min. Typ. Max. Min. Typ. Max.
Programming time 1-byte tDP1 — 86 761 — 40.5 374 μs
Erasure time 1-Kbyte tDE1K — 17.4 456 — 6.15 228 ms
8-Kbyte tDE8K — 60.4 499 — 9.3 231 ms
Blank check time 1-byte tDBC1 — — 48 — — 15.9 μs
1-Kbyte tDBC1K — — 1.58 — — 0.127 ms
Erase operation forcible stop time tDSED — — 21.5 — — 12.8 μs
DataFlash STOP recovery time tDSTOP 5——5——μs
Table 5.65 E2 DataFlash Characteristics (3)
: middle-speed operating mode
Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB= 0 V
Temperature range for the programming/erasure operation: Ta = –40 to +85°C
Item Symbol FCLK = 1 MHz FCLK = 8 MHz Unit
Min. Typ. Max. Min. Typ. Max.
Programming time 1-byte tDP1 — 126 1160 — 85.4 818 μs
Erasure time 1-Kbyte tDE1K — 17.5 457 — 7.76 259 ms
8-Kbyte tDE8K — 60.5 500 — 16.7 267.6 ms
Blank check time 1-byte tDBC1 — — 78 — — 50 μs
1-Kbyte tDBC1K — — 1.61 — — 0.369 ms
Erase operation forcible stop time tDSED — — 33.5 — — 25.5 μs
DataFlash STOP recovery time tDSTOP 720 — — 720 — — ns
R01DS0216EJ0110 Rev.1.10 Page 122 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
5.15 Usage Notes
5.15.1 Connecting VCL Capacitor and Bypass Capacitors
This MCU integrates an internal voltage-down circuit, which is used for lowering the power supply voltage in the
internal MCU to adjust automatically to the op tim um level. A 4.7-μF capacitor needs to be connected between this
internal voltage-down power su ppl y (VCL pin) and VSS pin. Figure 5.67 to Figure 5.68 shows how to connect
external capacitors. Place an external capacitor close to the pins. Do not apply the power supply voltage to the VCL pin.
Insert a multilayer ceramic capacitor as a bypass capacitor between each pair of the power supply pins. Implement a
bypass capacitor to the MCU power supply pi ns as close as possible. Use a recommended value of 0.1 μF as the
capacitance of the capacitors. For the capacitors related to crystal oscillation, see section 9, Clock Generation Circuit
in the User’s Manual: Hardware. For the capacitors related to analog modules, also see section 36, 12-Bit A/D
Converter (S12ADb) in the User’s Manual: Hardware.
For notes on designing the printed circuit board, see the descriptions of the application note "Hardware Design Guide"
(R01AN1411EJ). The latest vers i on c an be downloaded from Renesas Electronics Website.
R01DS0216EJ0110 Rev.1.10 Page 123 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.67 Connectin g Cap acitors (100-pin LFQFP)
RX113 Group
PLQP0100KB-A
(100-pin LFQFP)
(Top view)
VSS
VCC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
81
82
78
76
77
79
80
83
84
85
86
87
88
90
91
89
17
18
19
20
21
22
23
24
25
VCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
59
58
57
56
55
54
53
52
51
AVSS0
AVCC0
VSS_USB
VCC_USB
34
33
32
31
30
29
28
27
26
92
93
94
95
96
97
99
100
98
VCC
VSS
Bypass
capacitor
0.1 µF
Bypass
capacitor
0.1 µF
Bypass
capacitor
0.1 µF
Bypass
capacitor
0.1 µF
Bypass
capacitor
4.7 µF
Note. Do not apply the power supply voltage to the VCL pin.
Use a 4.7-µF multilayer ceram ic f or the V CL pin and place it close t o the pin.
A recommended value is shown for the capacitance of the bypass capacitors.
R01DS0216EJ0110 Rev.1.10 Page 124 of 131
Mar 31, 2016
RX113 Group 5. Electrical Characteristics
Figure 5.68 Connecting Cap acitors (64 Pins)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
54
55
51
49
50
52
53
56
57
58
59
60
61
63
64
62
RX113 Group
PLQP0064KB-A
(64-pin LFQFP)
(Top view)
AVSS0
AVCC0
VSS
VCC
VSS_USB
VCC_USB
VSS
VCC
Bypass
capacitor
0.1 µF
Note. Do not apply the power supply voltage to the VCL pin.
Use a 4.7-µF multilayer ceramic for the VCL pin and place it close to the pin.
A recommended value is shown for the capacitance of the bypass capacitors.
Bypass
capacitor
0.1 µF
Bypass
capacitor
0.1 µF
VCL
Bypass
capacitor
0.1 µF
Bypass
capacitor
4.7 µF
R01DS0216EJ0110 Rev.1.10 Page 125 of 131
Mar 31, 2016
RX113 Group Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Information on the latest version of the pa ck age dimensions or mountings has been displayed in “Pack a ges” on Renesas
Electronics Corporation website.
Figure A 100-Pin LFQFP (PLQP0100KB-A)
Terminal cross section
b
1
c
1
b
p
c
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Index mark
x
125
26
50
51
75
76
100
F
*1
*3
*2
Z
E
Z
D
E
D
H
D
H
E
b
p
Detail F
L
1
A
2
A
1
L
A
c
L1
ZE
ZD
c1
b1
bp
A1
HE
HD
y0.08
e0.5
c
0° 8°
x
L0.35 0.5 0.65
0.05 0.1 0.15
A1.7
15.8 16.0 16.2
15.8 16.0 16.2
A21.4
E13.9 14.0 14.1
D13.9 14.0 14.1
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.15 0.20 0.25
0.09 0.145 0.20
0.08
1.0
1.0
0.18
0.125
1.0
Previous CodeJEITA Package Code RENESAS Code
PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6gP-LFQFP100-14x14-0.50
e
yS
S
R01DS0216EJ0110 Rev.1.10 Page 126 of 131
Mar 31, 2016
RX113 Group Appendix 1. Package Dimensions
Figure B 100-Pin TFLGA (PTLG0100JA-A)
P-TFLGA100-7x7-0.65 0.1g
MASS[Typ.]
100F0GPTLG0100JA-A
RENESAS CodeJEITA Package Code Previous Code
0.15v
0.20w
0.08
0.4850.4350.385
MaxNomMin
Dimension in Millimeters
Symbol
Reference
7.0D
7.0E
1.05A
x
0.65
e
0.10y
b1
b0.31 0.35 0.39
0.575ZD
ZE0.575
Index mark
B
w
S
wA
S
A
H
G
F
E
D
C
B
12345678
yS
S
A
v
×4
(Laser mark)
Index mark
J
K
910
D
E
e
e
AZD
ZE
B
φ b
φ b1
φ×MS AB
φ×MS AB
R01DS0216EJ0110 Rev.1.10 Page 127 of 131
Mar 31, 2016
RX113 Group Appendix 1. Package Dimensions
Figure C 64-Pin LFQFP (PLQP0064KB-A)
Terminal cross section
b
1
c
1
b
p
c
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Index mark
*3
17
32
64
49
116
3348
F
*1
*2
x
b
p
H
E
E
H
D
D
Z
D
Z
E
Detail F
A
c
A
2
A
1
L
1
L
P-LFQFP64-10x10-0.50 0.3g
MASS[Typ.]
64P6Q-A / FP-64K / FP-64KVPLQP0064KB-A
RENESAS CodeJEITA Package Code Previous Code
1.0
0.125
0.18
1.25
1.25
0.08
0.20
0.145
0.09
0.250.200.15
MaxNomMin
Dimension in Millimeters
Symbol
Reference
10.110.0
9.9
D
10.110.0
9.9
E
1.4
A2
12.212.011.8
12.212.011.8
1.7
A
0.15
0.1
0.05
0.65
0.5
0.35
L
x
8°0°
c
0.5
e
0.08
y
HD
HE
A1
bp
b1
c1
ZD
ZE
L1
e
yS
S
R01DS0216EJ0110 Rev.1.10 Page 128 of 131
Mar 31, 2016
RX113 Group REVISION HISTORY
Classifications
- Items with Technical Up date docu ment num ber: Changes according to the corresponding issued Technical Update
- Items without Technical Update document number: Minor changes that do not require Technical Update to be issued
REVISION HISTORY RX113 Group Datasheet
Rev. Date Description Classification
Page Summary
1.02 Dec 01, 2014 — First edition, issued
1.10 Mar 31, 2016 1. Overview
16 to 23 Table 1.5 to 1.7 Note 2 regarding I/O power source is AVCC0 for the ports
(P4, P9, PJ6, and P7), added
5. Electrical Characteristics
53 Table 5.1 Absolute Maximum Ratings, Analog power supply voltage added TN-RX*-A149A/E
54 Table 5.2 Recommended Operating Conditions, VREFH0 / VREFH / A V CC0
/ VREFL added TN-RX*-A149A/E
60 Table 5.8 DC Characteristics (6), Increment for LPT operatio n and Increment
for IWDT operation added TN-RX*-A149A/E
62 Table 5.9 DC Characteristics (7) added TN-RX*-A136A/E
62, 63 Table 5.10 DC Characteristics (8), LDV1,2 and CTSU operating current
added TN-RX*-A149A/E
65, 66 Table 5.15 Permissible Output Currents is divided into D version and G
version TN-RX*-A136A/E
105 Table 5.43 D/A Conversion Characteristics (1), Output voltage range added
119 Table 5.61 ROM (Flash Memory for Code S torage) Characteristics (2),
Erasure time - 256-Kbyte added TN-RX*-A132A/E
120 Table 5.62 ROM (Flash Memory for Code S torage) Characteristics (3),
Temperature range for the programming/erasure operation changed
and Erasure time - 256-Kbyte added
TN-RX*-A132A/E
121 Table 5.64 E2 DataFlash Characteristics (2), Low speed FCLK changed
and Erasure time - 8-Kbyte added TN-RX*-A132A/E
121 Table 5.65 E2 DataFlash Characteristics (3),
Temperature range for the programming/erasure operation changed,
Low speed FCLK changed
and Erasure time - 8-Kbyte added
TN-RX*-A132A/E
122 to 124 5.15 Usage Notes added
REVISION HISTORY
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, et c., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction.
If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up o r pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequat e. When it is dry, a humidifier should b e used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive m aterial. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a
wrist strap. Semicon ductor devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and exter nal interface, as a rule, s witch on the external power supply after s witching on the in ternal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. T he correct power on/off sequence must be j udged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device an d accord ing to related specifications governing the device.
General Precauti ons in the Han dling of Micr oprocessing Unit and Mi c r ocontroller Unit Produc t s
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas.
For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well
as any technical updates that have been issued for the products.
1. Handling of Unused Pins
Handle unused pins in accordance with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Po wer-on
The state of the product is undef in ed at the moment when po wer is supp lied.
The states of internal circuits in the LSI are indeterminate and the states of register settings and
pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins
are not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
When the clock signal is generated with an external resonator (or from an external oscillator)
during a reset, ensure that the reset line is only released after full stabilization of the clock signal.
Moreover, when switching to a clock signal produced with an external resonator (or by an external
oscillator) while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to a product with a different part number, confirm
that the change will not lead to problems.
The characteristics of Microprocessing unit or Microcontroller unit products in the same group but
having a different part number may differ in terms of the internal memory capacity, layout pattern,
and other factors, which can affect the ranges of electrical characteristics, such as characteristic
values, operating margins, immunity to noise, and amount of radiated noise. When changing to a
product with a different part number, implement a system-evaluation test for the given product.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
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third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HAL II Stage, Indiranagar, Bangalore, India
Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
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