Triple, 200 mA, Low Noise,
High PSRR Voltage Regulator
Data Sheet ADP322/ADP323
Rev. A
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FEATURES
Fixed (ADP322) and adjustable output (ADP323) options
Bias voltage range (VBIAS): 2.5 V to 5.5 V
LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V
Three 200 mA low dropout voltage regulators (LDOs)
16-lead, 3 mm × 3 mm LFCSP
Initial accuracy: ±1%
Stable with 1 μF ceramic output capacitors
No noise bypass capacitor required
3 independent logic controlled enables
Overcurrent and thermal protection
Key specifications
High PSRR
76 dB PSRR up to 1 kHz
70 dB PSRR at 10 kHz
60 dB PSRR at 100 kHz
40 dB PSRR at 1 MHz
Low output noise
29 μV rms typical output noise at VOUT = 1.2 V
55 μV rms typical output noise at VOUT = 2.8 V
Excellent transient response
Low dropout voltage: 110 mV at 200 mA load
85 μA typical ground current at no load, all LDOs enabled
100 μs fast turn-on circuit
Guaranteed 200 mA output current per regulator
−40°C to +125°C junction temperature
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Portable medical devices
Post dc-to-dc regulation
TYPICAL APPLICATION CIRCUITS
ADP322
VBIAS
VOUT1
GND
VBIAS
1µF
OFF
ON
EN1
OFF
ON
EN2
OFF
ON
EN3
+
1µF
+
LDO 1
EN LD1
VBIAS
VBIAS
VOUT2
1µF
+
LDO 2
EN LD2
VOUT3
1µF
+
LDO 3
EN LD3
2.5V T
O
5.5V
VIN1/VIN2
VIN3
1µF
+
1.8V T
O
5.5V
1.8V T
O
5.5V
1µF
+
09288-001
Figure 1. Typical Application Circuit for ADP322
ADP323
VBIAS
VOUT1
GND
VBIAS
1µF
OFF
ON
EN1
OFF
ON
EN2
OFF
ON
EN3
+
1µF
+
LDO 1
EN LD1
VBIAS
VBIAS
VOUT2
1µF
+
LDO 2
EN LD2
VOUT3
FB1
FB2
FB3 1µF
+
LDO 3
EN LD3
2.5V TO
5.5V
VIN1/VIN2
VIN3
1µF
+
1.8V TO
5.5V
1.8V TO
5.5V
1µF
+
09288-053
Figure 2. Typical Application Circuit for ADP323
GENERAL DESCRIPTION
The ADP322/ADP323 200 mA triple output LDOs combine high
PSRR, low noise, low quiescent current, and low dropout voltage
to extend the battery life of portable devices and are ideally
suited for wireless applications with demanding performance
and board space requirements.
The ADP322/ADP323 PSRR is greater than 60 dB for frequencies
as high as 100 kHz while operating with a low headroom voltage.
The ADP322/ADP323 offer much lower noise performance
than competing LDOs without the need for a noise bypass
capacitor.
The ADP322/ADP323 are available in a miniature 16-lead,
3 mm × 3 mm LFCSP package and are stable with tiny 1 µF
±30% ceramic output capacitors providing the smallest possible
board area for a wide variety of portable power needs.
The ADP322 is available in output voltage combinations ranging
from 0.8 V to 3.3 V and offers overcurrent and thermal protection
to prevent damage in adverse conditions. The APDP323
adjustable triple LDO can be configured for any output voltage
between 0.5 V and 5 V with two resistors for each output.
ADP322/ADP323 Data Sheet
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Typical Application Circuits............................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Input and Output Capacitor, Recommended Specifications.. 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 15
Applications Information.............................................................. 16
Capacitor Selection .................................................................... 16
Undervoltage Lockout ............................................................... 17
Enable Feature ............................................................................ 17
Current-Limit and Thermal Overload Protection................. 18
Thermal Considerations............................................................ 18
Printed Circuit Board Layout Considerations ....................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
9/11—Rev.0 to Rev. A
Added Figure 2, Renumbered Sequentially .................................. 1
Changes to Theory of Operation Section.................................... 15
Added Figure 45, Renumbered Sequentially .............................. 15
Changes to Ordering Guide .......................................................... 21
9/10—Revision 0: Initial Version
Data Sheet ADP322/ADP323
Rev. A | Page 3 of 24
SPECIFICATIONS
VIN1/VIN2 = VIN3 = (VOUT + 0.5 V) or 1.8 V (whichever is greater), VBIAS = 2.5 V, EN1, EN2, EN3 = VBIAS, IOUT1 = IOUT2 = IOUT3 = 10 mA,
CIN = COUT1 = COUT2 = COUT3 = 1 µF, and TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
VOLTAGE RANGE
Input Bias Voltage Range VBIAS T
J = −40°C to +125°C 2.5 5.5 V
Input LDO Voltage Range VIN1/VIN2/VIN3 T
J = −40°C to +125°C 1.8 5.5 V
CURRENT
Ground Current with All
Regulators On
IGND I
OUT = 0 μA 85 μA
I
OUT = 0 μA, TJ = −40°C to +125°C 160 μA
I
OUT = 10 mA 120 μA
I
OUT = 10 mA, TJ = −40°C to +125°C 220 μA
I
OUT = 200 mA 250 μA
I
OUT = 200 mA, TJ = −40°C to +125°C 380 μA
Bias Voltage Input Current IBIAS 66 μA
T
J = −40°C to +125°C 140 μA
Shutdown Current IGND-SD EN1 = EN2 = EN3 = GND 0.1 μA
EN1 = EN2 = EN3 = GND, TJ = −40°C to +125°C 2.5 μA
FEEDBACK INPUT CURRENT FBIN 0.01 μA
VOLTAGE ACCURACY
Output Voltage Accuracy
(ADP322)
VOUT −1 +1 %
100 μA < IOUT < 200 mA, VIN = (VOUT + 0.5 V) to 5.5 V,
TJ = −40°C to +125°C
−2 +2 %
Feedback Voltage Accuracy
(ADP323)1
VFB 0.495 0.5 0.505 V
100 μA < IOUT < 200 mA, VIN = (VOUT + 0.5 V) to 5.5 V,
TJ = −40°C to +125°C
0.490 0.510 V
LINE REGULATION ∆VOUT/∆VIN V
IN = (VOUT + 0.5 V) to 5.5 V 0.01 %/ V
V
IN = (VOUT + 0.5 V) to 5.5 V, TJ = −40°C to +125°C −0.03 +0.03 %/ V
LOAD REGULATION2 ∆VOUT/∆IOUT I
OUT = 1 mA to 200 mA 0.001 %/mA
I
OUT = 1 mA to 200 mA, TJ = −40°C to +125°C 0.005 %/mA
DROPOUT VOLTAGE3 V
DROPOUT VOUT = 3.3 V mV
IOUT = 10 mA 6 mV
I
OUT = 10 mA, TJ = −40°C to +125°C 9 mV
I
OUT = 200 mA 110 mV
I
OUT = 200 mA, TJ = −40°C to +125°C 170 mV
START-UP TIME4 T
START-UP V
OUT = 3.3 V, all VOUT initially off, enable any LDO 240 μs
V
OUT = 0.8 V 100 μs
VOUT = 3.3 V, one VOUT initially on, enable second or
third LDO
160 μs
V
OUT = 0.8 V 20 μs
CURRENT LIMIT THRESHOLD5 I
LIMIT 250 360 600 mA
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD T
J rising 155 °C
Thermal Shutdown Hysteresis TSSD-HYS 15 °C
ADP322/ADP323 Data Sheet
Rev. A | Page 4 of 24
Parameter Symbol Conditions Min Typ Max Unit
EN INPUT
EN Input Logic High VIH 2.5 V ≤ VBIAS ≤ 5.5 V 1.2 V
EN Input Logic Low VIL 2.5 V ≤ VBIAS ≤ 5.5 V 0.4 V
EN Input Leakage Current VI-LEAKAGE EN1 = EN2 = EN3 = VIN or GND 0.1 μA
EN1 = EN2 = EN3 = VIN or GND,
TJ = −40°C to +125°C
1 μA
UNDERVOLTAGE LOCKOUT UVLO
Input Bias Voltage (VBIAS)
Rising
UVLORISE 2.45 V
Input Bias Voltage (VBIAS)
Falling
UVLOFALL 2.0 V
Hysteresis UVLOHYS 180 mV
OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V 63 μV rms
10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.8 V 55 μV rms
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 2.5 V 50 μV rms
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.2 V 29 μV rms
POWER SUPPLY REJECTION RATIO PSRR VIN = 1.8 V, VOUT = 0.8 V, IOUT = 100 mA
100 Hz 70 dB
1 kHz 70 dB
10 kHz 70 dB
100 kHz 60 dB
1 MHz 40 dB
V
IN = 3.8 V, VOUT = 2.8 V, IOUT = 100 mA
100 Hz 68 dB
1 kHz 62 dB
10 kHz 68 dB
100 kHz 60 dB
1 MHz 40 dB
1 Accuracy when VOUTx is connected directly to FBx. When the VOUTx voltage is set by external feedback resistors, the absolute accuracy in adjust mode depends on
the tolerances of the resistors used.
2 Based on an end-point calculation using 1 mA and 200 mA loads.
3 The dropout voltage specification applies only to output voltages greater than 1.8 V. Dropout voltage is defined as the input-to-output voltage differential when the
input voltage is set to the nominal output voltage.
4 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 90% of its nominal value.
5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, that is, 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE1 C
MIN TA = −40°C to +125°C 0.70 μF
CAPACITOR ESR RESR T
A = −40°C to +125°C 0.001 1 Ω
1 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with LDOs.
Data Sheet ADP322/ADP323
Rev. A | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN1/VIN2, VIN3, VBIAS to GND –0.3 V to +6.5 V
VOUT1, VOUT2, FB1, FB2 to GND –0.3 V to VIN1/VIN2
VOUT3, FB3 to GND –0.3 V to VIN3
EN1, EN2, EN3 to GND –0.3 V to +6.5 V
Storage Temperature Range –65°C to +150°C
Operating Junction Temperature Range –40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP322/ADP323 triple LDO can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that the junction temperature
(TJ) is within the specified temperature limits. In applications
with high power dissipation and poor thermal resistance, the
maximum ambient temperature may have to be derated. In
applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits.
The junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA). Maximum junction temperature (TJ) is calculated
from the ambient temperature (TA) and power dissipation (PD)
using the following formula:
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 inch × 3 inch
circuit board. See JEDEC JESD 51-9 for detailed information
on the board construction. For additional information, see the
AN-617 Application Note, MicroCSP™ Wafer Level Chip Scale
Package.
ΨJB is the junction to board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing through
multiple thermal paths rather than a single path as in thermal
resistance, θJB. Therefore, ΨJB thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make ΨJB more useful in real-world applications.
Maximum junction temperature (TJ) is calculated from the board
temperature (TB) and power dissipation (PD) using the following
formula:
TJ = TB + (PD × ΨJB)
See JEDEC JESD51-8 and JESD51-12 for more detailed inform-
ation about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4.
Package Type θJA Ψ
JB Unit
16-Lead, 3 mm × 3 mm LFCSP 49.5 25.2 °C/W
ESD CAUTION
ADP322/ADP323 Data Sheet
Rev. A | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
12
11
10
1
3
4
GND
NC
VIN3
9NC
EN1
VIN1/VIN2
2
VBIAS
NC
6
VOUT2
5
VOUT1
7
NC
8
VOUT3
16 EN2
15 EN3
14 NC
13 NC
TOP VIEW
(Not to Scale)
ADP322
NOTES
1. NC = NO CONNE
C
T.
2
. CONNECT EXPOSED PAD TO GROUND PLANE.
09288-002
Figure 3. ADP322 Pin Configuration
Table 5. ADP322 Pin Function Descriptions
Pin No. Mnemonic Description
1 EN1 Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For
automatic startup, connect EN1 to VBIAS.
2 VBIAS Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 μF or greater capacitor.
3 VIN1/VIN2
Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 μF or
greater capacitor.
4 NC Not connected internally.
5 VOUT1 Regulated Output Voltage 1. Connect a 1 μF or greater output capacitor between VOUT1 and GND.
6 VOUT2 Regulated Output Voltage 2. Connect a 1 μF or greater output capacitor between VOUT2 and GND.
7 NC Not connected internally.
8 VOUT3 Regulated Output Voltage 3. Connect a 1 μF or greater output capacitor between VOUT3 and GND.
9 NC Not connected internally.
10 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 μF or greater capacitor.
11 NC Not connected internally.
12 GND Ground Pin.
13 NC Not connected internally.
14 NC Not connected internally.
15 EN3 Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For
automatic startup, connect EN3 to VBIAS.
16 EN2 Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For
automatic startup, connect EN2 to VBIAS.
EP Exposed pad for enhanced thermal performance. Connect to copper ground plane.
Data Sheet ADP322/ADP323
Rev. A | Page 7 of 24
12
11
10
1
3
4
GND
NC
VIN3
9FB3
EN1
VIN1/VIN2
2
VBIAS
FB1
6
VOUT2
5
VOUT1
7
FB2
8
VOUT3
16 EN2
15 EN3
14 NC
13 NC
TOP VIEW
(Not to Scale)
ADP323
NOTES
1. NC = NO CONNE
C
T.
2
. CONNECT EXPOSED PAD TO GROUND PLANE.
09288-054
Figure 4. ADP323 Pin Configuration
Table 6. ADP323 Pin Function Descriptions
Pin No. Mnemonic Description
1 EN1 Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For
automatic startup, connect EN1 to VBIAS.
2 VBIAS Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 μF or greater capacitor.
3 VIN1/VIN2
Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 μF or
greater capacitor.
4 FB1 Connect the midpoint of the voltage divider from VOUT1 to GND to set VOUT1.
5 VOUT1 Regulated Output Voltage 1. Connect a 1 μF or greater output capacitor between VOUT1 and GND.
6 VOUT2 Regulated Output Voltage 2. Connect a 1 μF or greater output capacitor between VOUT2 and GND.
7 FB2 Connect the midpoint of the voltage divider from VOUT2 to GND to set VOUT2.
8 VOUT3 Regulated Output Voltage 3. Connect a 1 μF or greater output capacitor between VOUT3 and GND.
9 FB3 Connect the midpoint of the voltage divider from VOUT3 to GND to set VOUT3.
10 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 μF or greater capacitor.
11 NC Not connected internally.
12 GND Ground Pin.
13 NC Not connected internally.
14 NC Not connected internally.
15 EN3 Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For
automatic startup, connect EN3 to VBIAS.
16 EN2 Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For
automatic startup, connect EN2 to VBIAS.
EP Exposed pad for enhanced thermal performance. Connect to copper ground plane.
ADP322/ADP323 Data Sheet
Rev. A | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
VIN1/VIN2 = VIN3 =VBIAS = 4 V, VOUT1 = 3.3 V, VOUT2 = 1.8 V, VOUT3 = 1.5 V, IOUT = 10 mA, CIN = COUT1 = COUT2 = COUT3 = 1 µF, VENX is the
enable voltage, TA = 25°C, unless otherwise noted.
3.27
3.28
3.29
3.30
3.31
3.32
3.33
–40–52585125
T
J
(°C)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-003
Figure 5. Output Voltage vs. Junction Temperature
3.300
3.305
3.310
3.315
3.320
1 10 100 1000
ILOAD (mA)
VOUT (V)
09288-004
Figure 6. Output Voltage vs. Load Current
3.300
3.305
3.310
3.315
3.320
3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
V
IN
(V)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-005
Figure 7. Output Voltage vs. Input Voltage
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
–40 –5 25 85 125
T
J
(°C)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-006
Figure 8. Output Voltage vs. Junction Temperature
1.800
1.805
1.810
1.815
1.820
1 10 100 1000
I
LOAD
(mA)
V
OUT
(V)
09288-007
Figure 9. Output Voltage vs. Load Current
1.800
1.805
1.810
1.815
1.820
2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
V
IN
(V)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-008
Figure 10. Output Voltage vs. Input Voltage
Data Sheet ADP322/ADP323
Rev. A | Page 9 of 24
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
–40 –5 25 85 125
T
J
(°C)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-009
Figure 11. Output Voltage vs. Junction Temperature
1.500
1.502
1.504
1.506
1.508
1.510
1 10 100 1000
I
LOAD
(mA)
V
OUT
(V)
09288-010
Figure 12. Output Voltage vs. Load Current
1.500
1.502
1.504
1.506
1.508
1.510
1.80 2.20 2.60 3.00 3.40 3.80 4.20 4.60 5.00 5.40
V
IN
(V)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-011
Figure 13. Output Voltage vs. Input Voltage
0
20
40
60
80
100
120
140
–40 –5 25 85 125
T
J
(°C)
GROUND CURRENT (µA)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-012
Figure 14. Ground Current vs. Junction Temperature, Single Output Loaded
0
20
40
60
80
100
120
1 10 100 1000
I
LOAD
(mA)
GROUND CURRENT (µA)
09288-013
Figure 15. Ground Current vs. Load Current, Single Output Loaded
0
20
40
60
80
100
120
1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4
V
IN
(V)
GROUND CURRENT (µA)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-014
Figure 16. Ground Current vs. Input Voltage, Single Output Loaded
ADP322/ADP323 Data Sheet
Rev. A | Page 10 of 24
0
50
100
150
200
250
300
350
–40 –5 25 85 125
T
J
(°C)
GROUND CURRENT (µA)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-015
Figure 17. Ground Current vs. Junction Temperature,
All Outputs Loaded Equally
0
50
100
150
200
250
300
1 10 100 1000
TOTAL LOAD CURRENT (mA)
GROUND CURRENT (µA)
09288-016
Figure 18. Ground Current vs. Load Current, All Outputs Loaded Equally
0
50
100
150
200
250
300
1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
V
IN
(V)
GROUND CURRENT (µA)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-017
Figure 19. Ground Current vs. Input Voltage, All Outputs Loaded Equally
–40 –5 25 85 125
T
J
(°C)
BIAS CURRENT (µA)
0
20
40
60
80
100
120
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-018
Figure 20. Bias Current vs. Junction Temperature, Single Output Loaded
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
ILOAD (mA)
BIAS CURRENT (µA)
09288-019
Figure 21. Bias Current vs. Load Current, Single Output Loaded
64
66
68
70
72
74
76
2.52.93.33.74.14.54.95.3
VIN (V)
BIAS CURRENT (µA)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-020
Figure 22. Bias Current vs. Input Voltage, Single Output Loaded
Data Sheet ADP322/ADP323
Rev. A | Page 11 of 24
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
3.6
3.8
4.2
4.4
4.8
5.5
09288-021
Figure 23. Shutdown Current vs. Temperature at Various Input Voltages
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
LOAD (mA)
DROPOUT (mV)
09288-022
Figure 24. Dropout Voltage vs. Load Current and Output Voltage,
VOUT1 = 3.3 V
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50
V
IN
(V)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-023
Figure 25. Output Voltage vs. Input Voltage (in Dropout),
VOUT1 = 3.3 V
0
50
100
150
200
250
300
350
3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50
V
IN
(V)
GROUND CURRENT (µA)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-024
Figure 26. Ground Current vs. Input Voltage (in Dropout), VOUT1 = 3.3 V
0
50
100
150
200
250
300
1 10 100 1000
LOAD (mA)
DROPOUT (mV)
09288-025
Figure 27. Dropout Voltage vs. Load Current and Output Voltage,
VOUT2 = 1.8 V
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.70 1.80 1.90 2.00 2.10
V
IN
(V)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09288-026
Figure 28. Output Voltage vs. Input Voltage (in Dropout),
VOUT2 = 1.8 V
ADP322/ADP323 Data Sheet
Rev. A | Page 12 of 24
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
0
20
40
60
80
100
120
140
160
1.70 1.80 1.90 2.00 2.10
VIN (V)
GROUND CURRENT (µA)
09288-027
Figure 29. Ground Current vs. Input Voltage (in Dropout), VOUT2 = 1.8 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
200mA
100mA
10mA
1mA
V
RIPPLE
= 50mV
V
IN
= 2.8V
V
OUT
= 1.8V
C
OUT
= 1µF
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
09288-028
Figure 30. Power Supply Rejection Ratio vs. Frequency, 1.8 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
200mA
100mA
10mA
1mA
V
RIPPLE
= 50mV
V
IN
= 4.3V
V
OUT
= 3.3V
C
OUT
= 1µF
09288-029
Figure 31. Power Supply Rejection Ratio vs. Frequency, 3.3 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
200mA
100mA
10mA
1mA
V
RIPPLE
= 50mV
V
IN
= 2.5V
V
OUT
= 1.5V
C
OUT
= 1µF
09288-030
Figure 32. Power Supply Rejection Ratio vs. Frequency, 1.5 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (Hz)
PSRR (dB)
1.8V/200mA
1.8V/100mA
1.8V/10mA
1.2V/200mA
1.2V/100mA
1.2V/10mA
V
RIPPLE
= 50mV
1V HEADROOM
1.8V PSRR
1.2 XTALK
10 100 1k 10k 100k 1M 10M
09288-031
Figure 33. Power Supply Rejection Ratio vs. Frequency,
Channel-to-Channel Crosstalk
0.01
0.1
1
10
10 100 1k 10k 100k
NOISE SPECTR
A
L DENSITY (nV/
√
Hz)
3.3V
1.8V
1.5V
FREQUENCY (Hz)
09288-032
Figure 34. Output Noise Spectral Density vs. Frequency, VIN = 5 V,
ILOAD = 10 mA
Data Sheet ADP322/ADP323
Rev. A | Page 13 of 24
0
10
20
30
40
50
60
70
0.001 0.01 0.1 1 10 100 1000
LOAD CURRENT (mA)
NOISE (µV rms)
3.3V
1.8V
1.5V
09288-033
Figure 35. Output Noise vs. Load Current and Output Voltage, VIN = 5 V
CH1 100mA CH2 50mV
CH3 10mV CH4 10mV
M40µs A CH1 44mA
1
2
3
4
T 9.8%
BWBW
BW
BW
Ω
I
LOAD1
V
OUT1
V
OUT2
V
OUT3
09288-034
Figure 36. Load Transient Response,
ILOAD1 = 1 mA to 200 mA, ILOAD2 = ILOAD3 = 1 mA,
CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3
1
2
T 10.2%
CH1 200mA M40µs A CH1 124mA
BW
BW
ΩCH2 50mV
I
LOAD1
V
OUT1
09288-035
Figure 37. Load Transient Response,
ILOAD1 = 1 mA to 200 mA, COUT1 = 1 μF,
CH1 = ILOAD1, CH2 = VOUT1
CH2
1
2
T 10.4%
CH1 200mA 50mV M40µs A CH1 84mA
BW
BW
Ω
I
LOAD2
V
OUT2
09288-036
Figure 38. Load Transient Response, ILOAD2 = 1 mA to 200 mA, COUT2 = 1 μF,
CH1 = ILOAD2, CH2 = VOUT2
CH1 200mA CH2 50mV M40µs A CH1 124mA
1
2
T 10.2%
BW
BW
Ω
I
LOAD3
V
OUT3
09288-037
Figure 39. Load Transient Response,
ILOAD3 = 1 mA to 200 mA, COUT3 = 1 μF,
CH1 = ILOAD3, CH2 = VOUT3
CH3 10mV
BW
1
4
3
2
T 15%
CH1 1V CH2 10mV M1µs A CH1 4.62V
BW
CH4 10mV
BW
BW
V
IN
V
OUT1
V
OUT2
V
OUT3
09288-038
Figure 40. Line Transient Response,
VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =100 mA,
CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3
ADP322/ADP323 Data Sheet
Rev. A | Page 14 of 24
CH2
1
4
3
2
T 12%
CH1 1V 10mV M2µs A CH1 4.58V
BW
CH4 10mV
BW
CH3 10mV
BW
BW
V
IN
V
OUT1
V
OUT2
V
OUT3
09288-039
Figure 41. Line Transient Response,
VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =1 mA,
CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3
CH3
CH2
500mV
BW
1
2
T 10.2%
CH1 1V 500mV M100µs A CH1 540mV
BW
CH4 500mV
BW
BW
V
ENx
V
OUT1
V
OUT2
V
OUT3
09288-040
Figure 42. Turn-On Response, ILOAD1 = ILOAD2 = ILOAD3 =100 mA,
CH1 = VENx (the Enable Voltage), CH2 = VOUT1, CH3 = VOUT2,
CH4 = VOUT3
Data Sheet ADP322/ADP323
Rev. A | Page 15 of 24
THEORY OF OPERATION
The ADP322/ADP323 triple LDO are low quiescent current, low
dropout linear regulators that operate from 1.8 V to 5.5 V on
VIN1/VIN2 and VIN3 and provide up to 200 mA of current from
each output. Drawing a low 250 A quiescent current (typical) at
full load makes the ADP322/ADP323 ideal for battery-operated
portable equipment. Shutdown current consumption is typically
100 nA. Optimized for use with small 1 µF ceramic capacitors,
the ADP322/ADP323 provide excellent transient performance.
Internally, the ADP322 consists of a reference, three error ampli-
fiers, three feedback voltage dividers, and three PMOS pass
transistors. Output current is delivered via the PMOS pass device,
which is controlled by the error amplifier. The error amplifier
compares the reference voltage with the feedback voltage from the
output and amplifies the difference. If the feedback voltage is lower
than the reference voltage, the gate of the PMOS device is pulled
lower, allowing more current to flow and increasing the output vol-
tage. If the feedback voltage is higher than the reference voltage, the
gate of the PMOS device is pulled higher, allowing less current
to flow and decreasing the output voltage.
0.5V
REF
OVERCURRENT
V
OUT1
V
OUT2
V
OUT3
VIN1/VIN2
GND
EN1
VBIAS
VIN3
EN3
EN2
0.5V
REF
OVERCURRENT
0.5V
REF
OVERCURRENT
INTERNAL BIAS
VOLTAGES/CURRENTS,
UVLO AND THERMAL
PROTECT
SHUTDOWN
VOUT1
SHUTDOWN
VOUT2
SHUTDOWN
VOUT3
09288-041
+
–
+
–
+
–
Figure 43. ADP322 Internal Block Diagram
The ADP323 differs from the ADP322 except in that the output
voltage dividers are internally disconnected and the feedback
inputs of the error amplifiers are brought out for each output.
0.5V
REF
OVERCURRENT
VOUT1
VOUT2
VOUT3
FB1
FB2
FB3
VIN1/VIN2
GND
EN1
VBIAS
VIN3
EN3
EN2
0.5V
REF
OVERCURRENT
0.5V
REF
OVERCURRENT
INTERNAL BIAS
VOLTAGES/CURRENTS,
UVLO AND THERMAL
PROTECT
SHUTDOWN
VOUT1
SHUTDOWN
VOUT2
SHUTDOWN
VOUT3
0
9288-055
+
–
+
–
+
–
Figure 44. ADP323 Internal Block Diagram
The output voltage can be set using the following formulas:
VOUT = 0.5 V(1 + R1/R2) + (FBIN)(R1)
VOUT2 = 0.5 V(1 + R3/R4) + (FBIN)(R3)
VOUT3 = 0.5 V(1 + R5/R6) + (FBIN)(R5)
The value of R1, R3, R5 should be less than 200 k to minimize
errors in the output voltage caused by the FBx pin input
current. For example, when R1 and R2 each equal 200 k, the
output voltage is 1.0 V. The output voltage error introduced by
the FBx pin input current is 2 mV or 0.20%, assuming a typical
FBx pin input current of 10 nA at 25°C.
The ADP322 is available in multiple output voltage options
ranging from 0.8 V to 3.3 V.
The ADP322/ADP323 use the EN1/EN2 and EN3 pins to
enable and disable the VOUT1/VOUT2/VOUT3 pins under
normal operating conditions. When the EN1/EN2 and EN3
pins are high, VOUT1/VOUT2/VOUT3 turn on; when the
EN1/EN2 and EN3 pins are low, VOUT1/VOUT2/VOUT3 turn
off. For automatic startup, the EN1/EN2 and EN3 pins can be
tied to VBIAS.
0
9288-145
ADP323
VBIAS
VOUT1
GND
VBIAS
1µF
OFF
ON
EN1
OFF
ON
EN2
OFF
ON
EN3
+
1µF
+
LDO 1
EN LD1
VBIAS
VBIAS
VOUT2
1µF
+
LDO 2
EN LD2
VOUT3
1µF
+
LDO 3
EN LD3
2
.5
V
TO
5.5V
VIN1/VIN2
VIN3
1µF
+
1.8
V
TO
5.5V
1.8
V
TO
5.5V
1µF
+
FB1
R2
R1
FB2
R4
R3
FB3
R6
R5
Figure 45. ADP323 Application Circuit Diagram
ADP322/ADP323 Data Sheet
Rev. A | Page 16 of 24
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP322/ADP323 are designed for operation with small,
space-saving ceramic capacitors, but the parts function with
most commonly used capacitors as long as care is taken with
the effective series resistance (ESR) value. The ESR of the
output capacitor affects the stability of the LDO control loop.
A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less is
recommended to ensure the stability of the ADP322/ADP323.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP322/ADP323 to large
changes in the load current. Figure 46 shows the transient
response for an output capacitance value of 1 µF.
CH1 100mA ΩCH2 50mV
CH4 10mVCH3 10mV
M40µs A CH1 44mA
1
2
3
4
T 9.8%
I
LOAD1
V
OUT1
V
OUT2
V
OUT3
09288-042
BWBW
BW
BW
Figure 46. Output Transient Response,
ILOAD1 = 1 mA to 200 mA, ILOAD2 = 1 mA, ILOAD3 = 1 mA,
CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN1/VIN2, VIN3, and
VBIAS to GND reduces the circuit sensitivity to the PCB layout,
especially when long input traces or high source impedance is
encountered. If an output capacitance greater than 1 µF is
required, the input capacitor should be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitor can be used with the ADP322/
ADP323, as long as the capacitor meets the minimum capacit-
ance and maximum ESR requirements. Ceramic capacitors are
manufactured with a variety of dielectrics, each with a different
behavior over temperature and applied voltage. Capacitors must
have an adequate dielectric to ensure the minimum capacitance
over the necessary temperature range and dc bias conditions.
X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are
recommended. Y5V and Z5U dielectrics are not recommended
due to their poor temperature and dc bias characteristics.
Figure 47 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or with a higher
voltage rating exhibits better stability. The temperature variation
of the X5R dielectric is about ±15% over the −40°C to +85°C
temperature range and is not a function of the package or
voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
0
024681
VOLTAGE (V)
CAPACITANCE (µF)
0
09288-043
Figure 47. Capacitance vs. Voltage Bias Characteristic
Data Sheet ADP322/ADP323
Rev. A | Page 17 of 24
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, compo-
nent tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, TEMPCO over −40°C to +85°C is assumed
to be 15% for an X5R dielectric. TOL is assumed to be 10%,
and CBIAS is 0.94 F at 1.8 V (from the graph in Figure 47).
Substituting these values into Equation 1 yields
CEFF = 0.94 F × (1 − 0.15) × (1 − 0.1) = 0.719 F
Therefore, the capacitor chosen in this example meets the mini-
mum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
To guarantee the performance of the ADP322/ADP323 triple
LDO, it is imperative that the effects of dc bias, temperature,
and tolerances on the behavior of the capacitors be evaluated
for each application.
UNDERVOLTAGE LOCKOUT
The ADP322/ADP323 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage bias, VBIAS, is less than approximately 2.2 V. This
ensures that the inputs of the ADP322/ADP323 and the output
behave in a predictable manner during power-up.
ENABLE FEATURE
The ADP322/ADP323 use the ENx pins to enable and disable
the VOUTx pins under normal operating conditions. Figure 48
shows that, when a rising voltage on ENx crosses the active
threshold, VOUTx turns on. When a falling voltage on ENx
crosses the inactive threshold, VOUTx turns off.
ENABLE VOLTAGE (V)
V
OUT
(V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.4 0.60.5 0.7 0.90.8 1.0 1.1 1.2
VOUT
@ 4.5V
IN
09288-044
Figure 48. Typical ENx Pin Operation
As shown in Figure 48, the ENx pin has built-in hysteresis. This
prevents on/off oscillations that can occur due to noise on the
ENx pin as it passes through the threshold points.
The active/inactive thresholds of the ENx pin are derived
from the VBIAS voltage. Therefore, these thresholds vary with
changing input voltage. Figure 49 shows typical ENx active/
inactive thresholds when the input voltage varies from 2.5 V
to 5.5 V (note that VENx is the enable voltage).
INPUT VOLTAGE (V)
ENABLE THRESHOLDS
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
ENx
RISE V
ENx
FALL
09288-045
Figure 49. Typical ENx Pins Thresholds vs. Input Voltage
The ADP322/ADP323 use an internal soft start to limit the
inrush current when the output is enabled. The start-up time
for the 2.8 V option is approximately 220 µs from the time the
ENx active threshold is crossed to when the output reaches 90%
of its final value. The start-up time is somewhat dependent on
the output voltage setting and increases slightly as the output
voltage increases.
CH3
CH2
500mV
BW
1
2
T 10.2%
CH1 1V 500mV M100µs A CH1 540mV
BW
CH4 500mV
BW
BW
V
ENx
V
OUT1
V
OUT2
V
OUT3
09288-046
Figure 50. Typical Start-Up Time,ILOAD1 = ILOAD2 = ILOAD3 = 100 mA,
CH1 = VENx (the Enable Voltage), CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3
ADP322/ADP323 Data Sheet
Rev. A | Page 18 of 24
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP322/ADP323 are protected against damage due to
excessive power dissipation by current and thermal overload
protection circuits. The ADP322/ADP323 are designed to
current limit when the output load reaches 300 mA (typical).
When the output load exceeds 300 mA, the output voltage is
reduced to maintain a constant current limit.
Thermal overload protection is built in, which limits the
junction temperature to a maximum of 155°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature starts to
rise above 155°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
140°C, the output is turned on again and the output current
is restored to its nominal value.
Consider the case where a hard short from VOUTx to GND
occurs. At first, the ADP322/ADP323 limits current so that only
300 mA is conducted into the short. If self-heating of the junction
is great enough to cause its temperature to rise above 155°C,
thermal shutdown activates, turning off the output and
reducing the output current to zero. As the junction tempera-
ture cools and drops below 140°C, the output turns on and
conducts 300 mA into the short, again causing the junction
temperature to rise above 155°C. This thermal oscillation
between 140°C and 155°C causes a current oscillation between
0 mA and 300 mA that continues as long as the short remains
at the output.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so that junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
In most applications, the ADP322/ADP323 do not dissipate a
lot of heat due to high efficiency. However, in applications with
a high ambient temperature and high supply voltage to output
voltage differential, the heat dissipated in the package is large
enough that it can cause the junction temperature of the die to
exceed the maximum junction temperature of 125°C.
When the junction temperature exceeds 155°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature decreases below 140°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the tempera-
ture rise of the package due to the power dissipation, as shown
in Equation 2.
To guarantee reliable operation, the junction temperature of
the ADP322/ADP323 must not exceed 125°C. To ensure that
the junction temperature stays below this maximum value, the
user must be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient tem-
perature, power dissipation in the power device, and thermal
resistances between the junction and ambient air (θJA). The θJA
number is dependent on the package assembly compounds used
and the amount of copper to which the GND pins of the package
are soldered on the PCB. Table 7 shows typical θJA values for the
ADP322/ADP323 for various PCB copper sizes.
Table 7. Typical θJA Values
Copper Size (mm2) ADP322/ADP323 Triple LDO (°C/W)
JEDEC1 49.5
100 83.7
500 68.5
1000 64.7
1 Device soldered to JEDEC standard board.
The junction temperature of the ADP322/ADP323 can be
calculated from the following equation:
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = Σ[(VIN − VOUT) × ILOAD] + Σ(VIN × IGND) (3)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
Power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to
TJ = TA + {Σ[(VIN − VOUT) × ILOAD] × θJA} (4)
As shown in Equation 4, for a given ambient temperature,
input-to-output voltage differential, and continuous load
current, there exists a minimum copper size requirement
for the PCB to ensure that the junction temperature does not
rise above 125°C. Figure 51 to Figure 54 show junction
temperature calculations for different ambient temperatures,
total power dissipation, and areas of PCB copper.
In cases where the board temperature is known, the thermal
characterization parameter, ΨJB, can be used to estimate the
junction temperature rise. TJ is calculated from TB and PD using
the formula
TJ = TB + (PD × ΨJB) (5)
The typical ΨJB value for the 16-lead, 3 mm × 3 mm LFCSP is
25.2°C/W.
Data Sheet ADP322/ADP323
Rev. A | Page 19 of 24
0
20
40
60
80
100
120
140
0 0.2 0.4 0.6 0.8 1.0 1.2
TOTAL POWER DISSIPATION (W)
JUNCTION TEMPER
A
TURE, T
J
(°C)
1000mm
2
500mm
2
100mm
2
50mm
2
JEDEC
T
J
MAX
09288-047
Figure 51. Junction Temperature vs. Total Power Dissipation, TA = 25°C
0
20
40
60
80
100
120
140
00.20.40.6
0.8 1.0 1.2
TOTAL POWER DISSIPATION (W)
JUNCTION TEMPE
TURE, TJ (°C)
1000mm2
500mm2
100mm2
50mm2
JEDEC
TJ MAX
09288-048
Figure 52. Junction Temperature vs. Total Power Dissipation, TA = 50°C
0
20
40
60
80
100
120
140
0 0.2 0.4 0.6 0.8 1.0 1.2
TOTAL POWER DISSIPATION (W)
JUNCTION TEMPER
A
TURE, T
J
(°C)
1000mm
2
500mm
2
100mm
2
50mm
2
JEDEC
T
J
MAX
09288-049
Figure 53. Junction Temperature vs. Total Power Dissipation, TA = 85°C
0
20
40
60
80
100
120
140
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
TOTAL POWER DISSIPATION (W)
JUNCTION TEMPER
A
TURE, T
J
(°C)
T
B
= 25°C
T
B
= 50°C
T
B
= 85°C
T
J
MAX
09288-050
Figure 54. Junction Temperature vs. Total Power Dissipation and
Board Temperature
ADP322/ADP323 Data Sheet
Rev. A | Page 20 of 24
09288-051
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP322/ADP323. However, as can be seen from Table 7 , a
point of diminishing returns is eventually reached, beyond
which an increase in the copper size does not yield significant
heat dissipation benefits.
Place the input capacitor as close as possible to the VINx and
GND pins. Place the output capacitors as close as possible to
the VOUTx and GND pins. Use 0402 or 0603 size capacitors
and resistors to achieve the smallest possible footprint solution
on boards where area is limited.
Figure 55. Example of PCB Layout, Top Side
09288-052
Figure 56. Example of PCB Layout, Bottom Side
Data Sheet ADP322/ADP323
Rev. A | Page 21 of 24
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.25
0.20
1.65
1.50 SQ
1.45
091609-A
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN1
INDICATOR
0.50
0.40
0.30
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS MO-229.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very, Very Thin Quad
(CP-16-27)
Dimensions shown in millimeters
ORDERING GUIDE
Output Voltage (V)2
Model1
Temperature
Range VOUT1 VOUT2 VOUT3 Package Description
Package
Option Branding
ADP322ACPZ-115-R7 −40°C to +125°C 3.3 V 2.8 V 1.8 V 16-Lead LFCSP_WQ CP-16-27 LGU
ADP322ACPZ-135-R7 −40°C to +125°C 3.3 V 2.5 V 1.8 V 16-Lead LFCSP_WQ CP-16-27 LGT
ADP322ACPZ-145-R7 −40°C to +125°C 3.3 V 2.5 V 1.2 V 16-Lead LFCSP_WQ CP-16-27 LJC
ADP322ACPZ-155-R7 −40°C to +125°C 3.3 V 1.8 V 1.5 V 16-Lead LFCSP_WQ CP-16-27 LGS
ADP322ACPZ-165-R7 −40°C to +125°C 3.3 V 1.8 V 1.2V 16-Lead LFCSP_WQ CP-16-27 LLX
ADP322ACPZ-175-R7 −40°C to +125°C 2.8 V 1.8 V 1.2 V 16-Lead LFCSP_WQ CP-16-27 LGR
ADP322ACPZ-189-R7 −40°C to +125°C 2.5 V 1.8 V 1.2 V 16-Lead LFCSP_WQ CP-16-27 LJD
ADP323ACPZ-R7 −40°C to +125°C Adjustable Adjustable Adjustable 16-Lead LFCSP_WQ CP-16-27 LGQ
ADP322CP-EVALZ Evaluation board
ADP323CP-EVALZ Evaluation board
ADP322CPZ-REDYKIT Evaluation board kit
1 Z = RoHS Compliant Part.
2 For additional voltage options, contact a local sales or distribution representative.
ADP322/ADP323 Data Sheet
Rev. A | Page 22 of 24
NOTES
Data Sheet ADP322/ADP323
Rev. A | Page 23 of 24
NOTES
ADP322/ADP323 Data Sheet
Rev. A | Page 24 of 24
NOTES
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D09288-0-9/11(A)