FEATURES TYPICAL APPLICATION CIRCUITS ADP322 2.5V TO VBIAS 5.5V + 1.8V TO VIN1/VIN2 5.5V + 1F 1F EN1 LDO 1 VOUT1 ON + EN LD1 OFF 1F VBIAS EN2 LDO 2 ON VOUT2 + EN LD2 OFF 1F VBIAS 1.8V TO VIN3 5.5V + 1F EN3 LDO 3 ON OFF VOUT3 + EN LD3 1F GND Figure 1. Typical Application Circuit for ADP322 ADP323 2.5V TO VBIAS 5.5V + 1.8V TO VIN1/VIN2 5.5V + VBIAS 1F 1F EN1 LDO 1 ON VOUT1 FB1 + EN LD1 OFF 1F VBIAS EN2 ON LDO 2 VOUT2 FB2 + EN LD2 OFF APPLICATIONS Mobile phones Digital cameras and audio devices Portable and battery-powered equipment Portable medical devices Post dc-to-dc regulation VBIAS 09288-001 Fixed (ADP322) and adjustable output (ADP323) options Bias voltage range (VBIAS): 2.5 V to 5.5 V LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V Three 200 mA low dropout voltage regulators (LDOs) 16-lead, 3 mm x 3 mm LFCSP Initial accuracy: 1% Stable with 1 F ceramic output capacitors No noise bypass capacitor required 3 independent logic controlled enables Overcurrent and thermal protection Key specifications High PSRR 76 dB PSRR up to 1 kHz 70 dB PSRR at 10 kHz 60 dB PSRR at 100 kHz 40 dB PSRR at 1 MHz Low output noise 29 V rms typical output noise at VOUT = 1.2 V 55 V rms typical output noise at VOUT = 2.8 V Excellent transient response Low dropout voltage: 110 mV at 200 mA load 85 A typical ground current at no load, all LDOs enabled 100 s fast turn-on circuit Guaranteed 200 mA output current per regulator -40C to +125C junction temperature 1F VBIAS 1.8V TO VIN3 5.5V + 1F EN3 ON OFF LDO 3 VOUT3 FB3 EN LD3 GND + 1F 09288-053 Data Sheet Triple, 200 mA, Low Noise, High PSRR Voltage Regulator ADP322/ADP323 Figure 2. Typical Application Circuit for ADP323 GENERAL DESCRIPTION The ADP322/ADP323 200 mA triple output LDOs combine high PSRR, low noise, low quiescent current, and low dropout voltage to extend the battery life of portable devices and are ideally suited for wireless applications with demanding performance and board space requirements. The ADP322/ADP323 PSRR is greater than 60 dB for frequencies as high as 100 kHz while operating with a low headroom voltage. The ADP322/ADP323 offer much lower noise performance than competing LDOs without the need for a noise bypass capacitor. The ADP322/ADP323 are available in a miniature 16-lead, 3 mm x 3 mm LFCSP package and are stable with tiny 1 F 30% ceramic output capacitors providing the smallest possible board area for a wide variety of portable power needs. The ADP322 is available in output voltage combinations ranging from 0.8 V to 3.3 V and offers overcurrent and thermal protection to prevent damage in adverse conditions. The APDP323 adjustable triple LDO can be configured for any output voltage between 0.5 V and 5 V with two resistors for each output. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010-2011 Analog Devices, Inc. All rights reserved. ADP322/ADP323 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications....................................................................................... 1 Applications Information .............................................................. 16 Typical Application Circuits............................................................ 1 Capacitor Selection .................................................................... 16 General Description ......................................................................... 1 Undervoltage Lockout ............................................................... 17 Revision History ............................................................................... 2 Enable Feature ............................................................................ 17 Specifications..................................................................................... 3 Current-Limit and Thermal Overload Protection................. 18 Input and Output Capacitor, Recommended Specifications.. 4 Thermal Considerations............................................................ 18 Absolute Maximum Ratings............................................................ 5 Printed Circuit Board Layout Considerations ....................... 20 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 21 ESD Caution.................................................................................. 5 Ordering Guide .......................................................................... 21 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 9/10--Revision 0: Initial Version 9/11--Rev.0 to Rev. A Added Figure 2, Renumbered Sequentially .................................. 1 Changes to Theory of Operation Section.................................... 15 Added Figure 45, Renumbered Sequentially .............................. 15 Changes to Ordering Guide .......................................................... 21 Rev. A | Page 2 of 24 Data Sheet ADP322/ADP323 SPECIFICATIONS VIN1/VIN2 = VIN3 = (VOUT + 0.5 V) or 1.8 V (whichever is greater), VBIAS = 2.5 V, EN1, EN2, EN3 = VBIAS, IOUT1 = IOUT2 = IOUT3 = 10 mA, CIN = COUT1 = COUT2 = COUT3 = 1 F, and TA = 25C, unless otherwise noted. Table 1. Parameter VOLTAGE RANGE Input Bias Voltage Range Input LDO Voltage Range CURRENT Ground Current with All Regulators On Symbol Conditions Min VBIAS VIN1/VIN2/VIN3 TJ = -40C to +125C TJ = -40C to +125C 2.5 1.8 IGND IOUT = 0 A IBIAS Shutdown Current IGND-SD FEEDBACK INPUT CURRENT VOLTAGE ACCURACY Output Voltage Accuracy (ADP322) LINE REGULATION LOAD REGULATION 2 DROPOUT VOLTAGE 3 START-UP TIME 4 TSTART-UP CURRENT LIMIT THRESHOLD 5 THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis ILIMIT TSSD TSSD-HYS A 220 250 380 140 0.1 2.5 0.01 100 A < IOUT < 200 mA, VIN = (VOUT + 0.5 V) to 5.5 V, TJ = -40C to +125C VIN = (VOUT + 0.5 V) to 5.5 V VIN = (VOUT + 0.5 V) to 5.5 V, TJ = -40C to +125C IOUT = 1 mA to 200 mA IOUT = 1 mA to 200 mA, TJ = -40C to +125C VOUT = 3.3 V IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C VOUT = 3.3 V, all VOUT initially off, enable any LDO VOUT = 0.8 V VOUT = 3.3 V, one VOUT initially on, enable second or third LDO VOUT = 0.8 V +1 % -2 +2 % 0.505 V 0.510 V 0.5 0.490 0.01 -0.03 +0.03 0.001 0.005 6 9 110 170 240 100 160 250 TJ rising 20 360 155 15 Rev. A | Page 3 of 24 A A A A A A A A A A -1 0.495 VFB VDROPOUT V V 160 TJ = -40C to +125C EN1 = EN2 = EN3 = GND EN1 = EN2 = EN3 = GND, TJ = -40C to +125C VOUT VOUT/IOUT 5.5 5.5 120 FBIN VOUT/VIN Unit 66 100 A < IOUT < 200 mA, VIN = (VOUT + 0.5 V) to 5.5 V, TJ = -40C to +125C Feedback Voltage Accuracy (ADP323) 1 Max 85 IOUT = 0 A, TJ = -40C to +125C IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C Bias Voltage Input Current Typ 600 %/ V %/ V %/mA %/mA mV mV mV mV mV s s s s mA C C ADP322/ADP323 Parameter EN INPUT EN Input Logic High EN Input Logic Low EN Input Leakage Current Data Sheet Symbol Conditions Min VIH VIL VI-LEAKAGE 2.5 V VBIAS 5.5 V 2.5 V VBIAS 5.5 V EN1 = EN2 = EN3 = VIN or GND EN1 = EN2 = EN3 = VIN or GND, TJ = -40C to +125C 1.2 UNDERVOLTAGE LOCKOUT Input Bias Voltage (VBIAS) Rising Input Bias Voltage (VBIAS) Falling Hysteresis OUTPUT NOISE UVLOHYS OUTNOISE POWER SUPPLY REJECTION RATIO PSRR Typ 1 2.45 V 0.1 2.0 10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V 10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.8 V 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 2.5 V 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.2 V VIN = 1.8 V, VOUT = 0.8 V, IOUT = 100 mA 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz VIN = 3.8 V, VOUT = 2.8 V, IOUT = 100 mA 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz Unit V V A A 0.4 UVLO UVLORISE UVLOFALL Max V 180 63 55 50 29 mV V rms V rms V rms V rms 70 70 70 60 40 dB dB dB dB dB 68 62 68 60 40 dB dB dB dB dB 1 Accuracy when VOUTx is connected directly to FBx. When the VOUTx voltage is set by external feedback resistors, the absolute accuracy in adjust mode depends on the tolerances of the resistors used. Based on an end-point calculation using 1 mA and 200 mA loads. 3 The dropout voltage specification applies only to output voltages greater than 1.8 V. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. 4 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 90% of its nominal value. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, that is, 2.7 V. 2 INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter MINIMUM INPUT AND OUTPUT CAPACITANCE 1 CAPACITOR ESR 1 Symbol CMIN RESR Conditions TA = -40C to +125C TA = -40C to +125C Min 0.70 0.001 Typ Max 1 Unit F The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with LDOs. Rev. A | Page 4 of 24 Data Sheet ADP322/ADP323 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN1/VIN2, VIN3, VBIAS to GND VOUT1, VOUT2, FB1, FB2 to GND VOUT3, FB3 to GND EN1, EN2, EN3 to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating -0.3 V to +6.5 V -0.3 V to VIN1/VIN2 -0.3 V to VIN3 -0.3 V to +6.5 V -65C to +150C -40C to +125C JEDEC J-STD-020 Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP322/ADP323 triple LDO can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature (TJ) is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (JA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the following formula: TJ = TA + (PD x JA) Junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of JA are based on a 4-layer, 4 inch x 3 inch circuit board. See JEDEC JESD 51-9 for detailed information on the board construction. For additional information, see the AN-617 Application Note, MicroCSPTM Wafer Level Chip Scale Package. JB is the junction to board thermal characterization parameter with units of C/W. JB of the package is based on modeling and calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, JB. Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package, factors that make JB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula: TJ = TB + (PD x JB) See JEDEC JESD51-8 and JESD51-12 for more detailed information about JB. THERMAL RESISTANCE JA and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Package Type 16-Lead, 3 mm x 3 mm LFCSP ESD CAUTION Rev. A | Page 5 of 24 JA 49.5 JB 25.2 Unit C/W ADP322/ADP323 Data Sheet 13 NC 14 NC 16 EN2 15 EN3 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EN1 1 12 GND 11 NC ADP322 VIN1/VIN2 3 10 VIN3 NC 4 NC 7 NC VOUT3 8 VOUT2 6 VOUT1 5 9 TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO GROUND PLANE. 09288-002 VBIAS 2 Figure 3. ADP322 Pin Configuration Table 5. ADP322 Pin Function Descriptions Pin No. 1 Mnemonic EN1 2 3 VBIAS VIN1/VIN2 4 5 6 7 8 9 10 11 12 13 14 15 NC VOUT1 VOUT2 NC VOUT3 NC VIN3 NC GND NC NC EN3 16 EN2 EP Description Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For automatic startup, connect EN1 to VBIAS. Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 F or greater capacitor. Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 F or greater capacitor. Not connected internally. Regulated Output Voltage 1. Connect a 1 F or greater output capacitor between VOUT1 and GND. Regulated Output Voltage 2. Connect a 1 F or greater output capacitor between VOUT2 and GND. Not connected internally. Regulated Output Voltage 3. Connect a 1 F or greater output capacitor between VOUT3 and GND. Not connected internally. Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 F or greater capacitor. Not connected internally. Ground Pin. Not connected internally. Not connected internally. Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For automatic startup, connect EN3 to VBIAS. Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For automatic startup, connect EN2 to VBIAS. Exposed pad for enhanced thermal performance. Connect to copper ground plane. Rev. A | Page 6 of 24 13 NC 14 NC 16 EN2 ADP322/ADP323 15 EN3 Data Sheet EN1 1 12 GND 11 NC ADP323 VIN1/VIN2 3 10 VIN3 FB1 4 FB2 7 FB3 VOUT3 8 VOUT2 6 VOUT1 5 9 TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO GROUND PLANE. 09288-054 VBIAS 2 Figure 4. ADP323 Pin Configuration Table 6. ADP323 Pin Function Descriptions Pin No. 1 Mnemonic EN1 2 3 VBIAS VIN1/VIN2 4 5 6 7 8 9 10 11 12 13 14 15 FB1 VOUT1 VOUT2 FB2 VOUT3 FB3 VIN3 NC GND NC NC EN3 16 EN2 EP Description Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For automatic startup, connect EN1 to VBIAS. Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 F or greater capacitor. Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 F or greater capacitor. Connect the midpoint of the voltage divider from VOUT1 to GND to set VOUT1. Regulated Output Voltage 1. Connect a 1 F or greater output capacitor between VOUT1 and GND. Regulated Output Voltage 2. Connect a 1 F or greater output capacitor between VOUT2 and GND. Connect the midpoint of the voltage divider from VOUT2 to GND to set VOUT2. Regulated Output Voltage 3. Connect a 1 F or greater output capacitor between VOUT3 and GND. Connect the midpoint of the voltage divider from VOUT3 to GND to set VOUT3. Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 F or greater capacitor. Not connected internally. Ground Pin. Not connected internally. Not connected internally. Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For automatic startup, connect EN3 to VBIAS. Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For automatic startup, connect EN2 to VBIAS. Exposed pad for enhanced thermal performance. Connect to copper ground plane. Rev. A | Page 7 of 24 ADP322/ADP323 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VIN1/VIN2 = VIN3 =VBIAS = 4 V, VOUT1 = 3.3 V, VOUT2 = 1.8 V, VOUT3 = 1.5 V, IOUT = 10 mA, CIN = COUT1 = COUT2 = COUT3 = 1 F, VENX is the enable voltage, TA = 25C, unless otherwise noted. 1.820 3.33 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 3.32 1.810 3.31 1.805 VOUT (V) VOUT (V) LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 1.815 3.30 1.800 1.795 3.29 1.790 3.28 1.785 -5 25 85 125 1.780 TJ (C) 1.820 3.315 1.815 VOUT (V) 85 125 3.310 1.810 10 100 1000 ILOAD (mA) 1.800 09288-004 1 1 1000 Figure 9. Output Voltage vs. Load Current 3.320 1.820 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA VOUT (V) 1.815 3.310 3.305 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 1.810 1.805 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 VIN (V) 5.4 09288-005 3.300 3.6 100 ILOAD (mA) Figure 6. Output Voltage vs. Load Current 3.315 10 09288-007 1.805 3.305 Figure 7. Output Voltage vs. Input Voltage 1.800 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 VIN (V) Figure 10. Output Voltage vs. Input Voltage Rev. A | Page 8 of 24 5.3 09288-008 VOUT (V) 25 Figure 8. Output Voltage vs. Junction Temperature 3.320 VOUT (V) -5 TJ (C) Figure 5. Output Voltage vs. Junction Temperature 3.300 -40 09288-006 -40 09288-003 3.27 Data Sheet ADP322/ADP323 1.520 140 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 1.500 1.495 1.490 80 60 40 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 20 1.485 -40 -5 25 85 125 0 09288-009 1.480 TJ (C) Figure 11. Output Voltage vs. Junction Temperature -40 -5 25 85 125 TJ (C) Figure 14. Ground Current vs. Junction Temperature, Single Output Loaded 1.510 120 100 GROUND CURRENT (A) 1.508 VOUT (V) 1.506 1.504 80 60 40 1.502 20 10 100 1000 ILOAD (mA) 0 Figure 12. Output Voltage vs. Load Current GROUND CURRENT (A) 100 VOUT (V) 1.504 1.502 80 60 40 20 3.00 3.40 3.80 4.20 4.60 5.00 VIN (V) 5.40 0 1.8 09288-011 2.60 1000 120 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 2.20 100 Figure 15. Ground Current vs. Load Current, Single Output Loaded 1.506 1.500 1.80 10 ILOAD (mA) 1.510 1.508 1 09288-013 1 09288-010 1.500 100 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 2.2 2.6 3.0 3.4 3.8 VIN (V) 4.2 4.6 5.0 5.4 09288-014 VOUT (V) 1.505 09288-012 1.510 120 GROUND CURRENT (A) 1.515 Figure 16. Ground Current vs. Input Voltage, Single Output Loaded Figure 13. Output Voltage vs. Input Voltage Rev. A | Page 9 of 24 ADP322/ADP323 Data Sheet 350 120 100 200 150 100 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 50 0 -40 -5 25 85 125 80 60 40 TJ (C) LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 20 0 -40 -5 25 85 125 09288-018 BIAS CURRENT (A) 250 09288-015 GROUND CURRENT (A) 300 TJ (C) Figure 20. Bias Current vs. Junction Temperature, Single Output Loaded Figure 17. Ground Current vs. Junction Temperature, All Outputs Loaded Equally 100 300 90 80 BIAS CURRENT (A) GROUND CURRENT (A) 250 200 150 100 70 60 50 40 30 20 50 10 100 1000 TOTAL LOAD CURRENT (mA) 0 250 74 BIAS CURRENT (A) 76 150 100 0 1.7 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 2.1 2.5 2.9 1000 72 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 70 68 66 3.3 3.7 VIN (V) 4.1 4.5 4.9 5.3 09288-017 50 100 Figure 21. Bias Current vs. Load Current, Single Output Loaded 300 200 10 ILOAD (mA) Figure 18. Ground Current vs. Load Current, All Outputs Loaded Equally GROUND CURRENT (A) 1 Figure 19. Ground Current vs. Input Voltage, All Outputs Loaded Equally Rev. A | Page 10 of 24 64 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 VIN (V) Figure 22. Bias Current vs. Input Voltage, Single Output Loaded 09288-020 1 09288-016 0 09288-019 10 Data Sheet ADP322/ADP323 0.9 300 0.6 0.5 0.4 0.3 250 200 150 100 0.2 50 0.1 -25 0 25 50 75 100 125 TEMPERATURE (C) 0 3.10 09288-021 0 -50 Figure 23. Shutdown Current vs. Temperature at Various Input Voltages LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 VIN (V) 09288-024 0.7 GROUND CURRENT (A) SHUTDOWN CURRENT (A) 0.8 350 3.6 3.8 4.2 4.4 4.8 5.5 Figure 26. Ground Current vs. Input Voltage (in Dropout), VOUT1 = 3.3 V 100 300 90 250 80 200 DROPOUT (mV) DROPOUT (mV) 70 60 50 40 150 100 30 20 50 1 10 100 1000 LOAD (mA) 0 09288-022 3.25 1000 1.85 1.80 1.75 3.20 VOUT (V) 1.70 3.15 1.65 3.10 1.60 3.05 1.55 3.00 1.50 2.95 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 VIN (V) 09288-023 VOUT (V) 100 Figure 27. Dropout Voltage vs. Load Current and Output Voltage, VOUT2 = 1.8 V LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 3.30 10 LOAD (mA) Figure 24. Dropout Voltage vs. Load Current and Output Voltage, VOUT1 = 3.3 V 3.35 1 Figure 25. Output Voltage vs. Input Voltage (in Dropout), VOUT1 = 3.3 V 1.45 1.70 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 1.80 1.90 2.00 2.10 VIN (V) Figure 28. Output Voltage vs. Input Voltage (in Dropout), VOUT2 = 1.8 V Rev. A | Page 11 of 24 09288-026 0 09288-025 10 ADP322/ADP323 Data Sheet 160 0 120 -30 PSRR (dB) 100 80 60 -50 -60 -70 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 1.80 -90 1.90 2.00 -100 2.10 VIN (V) -10 -20 0 -20 -30 -40 -40 PSRR (dB) -30 -60 -80 -80 -90 -100 10 -100 10 10k 100k 1M 10M 09288-028 -90 FREQUENCY (Hz) -20 200mA 100mA 10mA 1mA VRIPPLE = 50mV 1V HEADROOM 1.8V PSRR 1.2 XTALK 100 1k 10k 100k 1M 10M Figure 33. Power Supply Rejection Ratio vs. Frequency, Channel-to-Channel Crosstalk 10 VRIPPLE = 50mV VIN = 4.3V VOUT = 3.3V COUT = 1F NOISE SPECTRAL DENSITY (nV/Hz) 0 10M FREQUENCY (Hz) Figure 30. Power Supply Rejection Ratio vs. Frequency, 1.8 V -10 1M -60 -70 1k 100k -50 -70 100 10k 1.8V/200mA 1.8V/100mA 1.8V/10mA 1.2V/200mA 1.2V/100mA 1.2V/10mA -10 -50 1k Figure 32. Power Supply Rejection Ratio vs. Frequency, 1.5 V VRIPPLE = 50mV VIN = 2.8V VOUT = 1.8V COUT = 1F 200mA 100mA 10mA 1mA 100 FREQUENCY (Hz) Figure 29. Ground Current vs. Input Voltage (in Dropout), VOUT2 = 1.8 V 0 10 09288-030 0 1.70 -80 09288-031 40 20 -30 -40 -50 -60 -70 -80 3.3V 1.8V 1.5V 1 0.1 -100 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 09288-029 -90 0.01 10 100 1k 10k 100k FREQUENCY (Hz) Figure 34. Output Noise Spectral Density vs. Frequency, VIN = 5 V, ILOAD = 10 mA Figure 31. Power Supply Rejection Ratio vs. Frequency, 3.3 V Rev. A | Page 12 of 24 09288-032 PSRR (dB) -40 09288-027 GROUND CURRENT (A) 140 PSRR (dB) 200mA 100mA 10mA 1mA VRIPPLE = 50mV -10 VIN = 2.5V VOUT = 1.5V -20 COUT = 1F Data Sheet 70 60 ADP322/ADP323 3.3V 1.8V 1.5V ILOAD2 1 NOISE (V rms) 50 40 30 VOUT2 2 20 0.01 0.1 1 10 100 1000 LOAD CURRENT (mA) Figure 35. Output Noise vs. Load Current and Output Voltage, VIN = 5 V CH1 200mA 09288-033 0 0.001 B W B W M40s A CH1 84mA T 10.4% Figure 38. Load Transient Response, ILOAD2 = 1 mA to 200 mA, COUT2 = 1 F, CH1 = ILOAD2, CH2 = VOUT2 ILOAD1 ILOAD3 1 2 CH2 50mV 09288-036 10 1 VOUT1 VOUT3 2 VOUT2 3 CH1 100mA CH3 10mV B W B W CH2 50mV CH4 10mV B W B W M40s A CH1 T 9.8% 44mA CH1 200mA B W CH2 50mV B W M40s A CH1 T 10.2% Figure 36. Load Transient Response, ILOAD1 = 1 mA to 200 mA, ILOAD2 = ILOAD3 = 1 mA, CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3 Figure 39. Load Transient Response, ILOAD3 = 1 mA to 200 mA, COUT3 = 1 F, CH1 = ILOAD3, CH2 = VOUT3 ILOAD1 VIN 124mA 09288-037 VOUT3 09288-034 1 1 VOUT1 2 VOUT1 2 VOUT2 3 VOUT3 CH1 200mA B W CH2 50mV B W M40s A CH1 T 10.2% 124mA 09288-035 4 CH1 1V CH3 10mV B W B W CH2 10mV CH4 10mV B W B W M1s A CH1 4.62V T 15% Figure 40. Line Transient Response, VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =100 mA, CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3 Figure 37. Load Transient Response, ILOAD1 = 1 mA to 200 mA, COUT1 = 1 F, CH1 = ILOAD1, CH2 = VOUT1 Rev. A | Page 13 of 24 09288-038 4 ADP322/ADP323 Data Sheet VENx VIN VOUT1 1 1 VOUT1 2 VOUT2 VOUT3 VOUT2 3 VOUT3 4 B W B W CH2 10mV CH4 10mV B W B W M2s A CH1 4.58V T 12% CH1 1V CH3 500mV Figure 41. Line Transient Response, VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =1 mA, CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3 B W B W CH2 500mV CH4 500mV B W B W M100s A CH1 540mV T 10.2% Figure 42. Turn-On Response, ILOAD1 = ILOAD2 = ILOAD3 =100 mA, CH1 = VENx (the Enable Voltage), CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3 Rev. A | Page 14 of 24 09288-040 CH1 1V CH3 10mV 09288-039 2 Data Sheet ADP322/ADP323 THEORY OF OPERATION The ADP322/ADP323 triple LDO are low quiescent current, low dropout linear regulators that operate from 1.8 V to 5.5 V on VIN1/VIN2 and VIN3 and provide up to 200 mA of current from each output. Drawing a low 250 A quiescent current (typical) at full load makes the ADP322/ADP323 ideal for battery-operated portable equipment. Shutdown current consumption is typically 100 nA. Optimized for use with small 1 F ceramic capacitors, the ADP322/ADP323 provide excellent transient performance. Internally, the ADP322 consists of a reference, three error amplifiers, three feedback voltage dividers, and three PMOS pass transistors. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to flow and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to flow and decreasing the output voltage. VOUT1 VIN1/VIN2 VBIAS INTERNAL BIAS VOLTAGES/CURRENTS, UVLO AND THERMAL PROTECT EN1 SHUTDOWN VOUT1 EN2 SHUTDOWN VOUT2 EN3 OVERCURRENT VOUT2 = 0.5 V(1 + R3/R4) + (FBIN)(R3) VOUT3 = 0.5 V(1 + R5/R6) + (FBIN)(R5) The value of R1, R3, R5 should be less than 200 k to minimize errors in the output voltage caused by the FBx pin input current. For example, when R1 and R2 each equal 200 k, the output voltage is 1.0 V. The output voltage error introduced by the FBx pin input current is 2 mV or 0.20%, assuming a typical FBx pin input current of 10 nA at 25C. The ADP322 is available in multiple output voltage options ranging from 0.8 V to 3.3 V. The ADP322/ADP323 use the EN1/EN2 and EN3 pins to enable and disable the VOUT1/VOUT2/VOUT3 pins under normal operating conditions. When the EN1/EN2 and EN3 pins are high, VOUT1/VOUT2/VOUT3 turn on; when the EN1/EN2 and EN3 pins are low, VOUT1/VOUT2/VOUT3 turn off. For automatic startup, the EN1/EN2 and EN3 pins can be tied to VBIAS. ADP323 VOUT2 SHUTDOWN VOUT3 VOUT = 0.5 V(1 + R1/R2) + (FBIN)(R1) + - 0.5V REF OVERCURRENT The output voltage can be set using the following formulas: 2.5V TO 5.5V 1.8V TO 5.5V + - VBIAS + 1F VIN1/VIN2 + 0.5V REF VIN3 VBIAS 1F EN1 VOUT1 LDO 1 ON EN LD1 OFF FB1 + 1F R2 VBIAS VOUT3 R1 VOUT2 OVERCURRENT + - EN2 09288-041 0.5V REF Figure 43. ADP322 Internal Block Diagram ON LDO 2 EN LD2 OFF FB2 The ADP323 differs from the ADP322 except in that the output voltage dividers are internally disconnected and the feedback inputs of the error amplifiers are brought out for each output. VIN3 + 1F EN3 ON OFF INTERNAL BIAS VOLTAGES/CURRENTS, UVLO AND THERMAL PROTECT EN1 SHUTDOWN VOUT1 EN2 SHUTDOWN VOUT2 EN3 SHUTDOWN VOUT3 OVERCURRENT + FB1 - 0.5V REF VOUT2 OVERCURRENT + - FB2 0.5V REF VIN3 VOUT3 GND OVERCURRENT + - 0.5V REF FB3 09288-055 VBIAS Figure 44. ADP323 Internal Block Diagram Rev. A | Page 15 of 24 1F VOUT3 LDO 3 EN LD3 FB3 R5 R6 GND Figure 45. ADP323 Application Circuit Diagram VOUT1 VIN1/VIN2 + R4 VBIAS 1.8V TO 5.5V R3 + 1F 09288-145 GND ADP322/ADP323 Data Sheet APPLICATIONS INFORMATION CAPACITOR SELECTION Input Bypass Capacitor Output Capacitor Connecting a 1 F capacitor from VIN1/VIN2, VIN3, and VBIAS to GND reduces the circuit sensitivity to the PCB layout, especially when long input traces or high source impedance is encountered. If an output capacitance greater than 1 F is required, the input capacitor should be increased to match it. The ADP322/ADP323 are designed for operation with small, space-saving ceramic capacitors, but the parts function with most commonly used capacitors as long as care is taken with the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 0.70 F capacitance with an ESR of 1 or less is recommended to ensure the stability of the ADP322/ADP323. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP322/ADP323 to large changes in the load current. Figure 46 shows the transient response for an output capacitance value of 1 F. ILOAD1 1 Figure 47 depicts the capacitance vs. voltage bias characteristic of a 0402 1 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or with a higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about 15% over the -40C to +85C temperature range and is not a function of the package or voltage rating. VOUT2 CH1 100mA BW CH2 50mV B CH3 10mV W CH4 10mV B W B W M40s T 9.8% A CH1 44mA Figure 46. Output Transient Response, ILOAD1 = 1 mA to 200 mA, ILOAD2 = 1 mA, ILOAD3 = 1 mA, CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3 1.2 09288-042 VOUT3 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 VOLTAGE (V) 8 Figure 47. Capacitance vs. Voltage Bias Characteristic Rev. A | Page 16 of 24 10 09288-043 VOUT1 3 4 Any good quality ceramic capacitor can be used with the ADP322/ ADP323, as long as the capacitor meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics. CAPACITANCE (F) 2 Input and Output Capacitor Properties Data Sheet ADP322/ADP323 Use Equation 1 to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) As shown in Figure 48, the ENx pin has built-in hysteresis. This prevents on/off oscillations that can occur due to noise on the ENx pin as it passes through the threshold points. (1) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. The active/inactive thresholds of the ENx pin are derived from the VBIAS voltage. Therefore, these thresholds vary with changing input voltage. Figure 49 shows typical ENx active/ inactive thresholds when the input voltage varies from 2.5 V to 5.5 V (note that VENx is the enable voltage). 1.00 In this example, TEMPCO over -40C to +85C is assumed to be 15% for an X5R dielectric. TOL is assumed to be 10%, and CBIAS is 0.94 F at 1.8 V (from the graph in Figure 47). 0.95 CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. 0.85 0.80 VENx RISE 0.75 VENx FALL 0.70 0.65 0.60 To guarantee the performance of the ADP322/ADP323 triple LDO, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 0.55 0.50 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) 09288-045 Substituting these values into Equation 1 yields ENABLE THRESHOLDS 0.90 Figure 49. Typical ENx Pins Thresholds vs. Input Voltage UNDERVOLTAGE LOCKOUT The ADP322/ADP323 have an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage bias, VBIAS, is less than approximately 2.2 V. This ensures that the inputs of the ADP322/ADP323 and the output behave in a predictable manner during power-up. ENABLE FEATURE The ADP322/ADP323 use an internal soft start to limit the inrush current when the output is enabled. The start-up time for the 2.8 V option is approximately 220 s from the time the ENx active threshold is crossed to when the output reaches 90% of its final value. The start-up time is somewhat dependent on the output voltage setting and increases slightly as the output voltage increases. The ADP322/ADP323 use the ENx pins to enable and disable the VOUTx pins under normal operating conditions. Figure 48 shows that, when a rising voltage on ENx crosses the active threshold, VOUTx turns on. When a falling voltage on ENx crosses the inactive threshold, VOUTx turns off. VENx VOUT1 1 VOUT2 1.4 VOUT @ 4.5VIN 1.2 VOUT3 1.0 2 CH1 1V CH3 500mV 0.4 CH2 500mV CH4 500mV B W B W M100s A CH1 T 10.2% 540mV Figure 50. Typical Start-Up Time,ILOAD1 = ILOAD2 = ILOAD3 = 100 mA, CH1 = VENx (the Enable Voltage), CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3 0.2 0 0.4 B W B W 09288-046 0.6 0.5 0.6 0.7 0.8 0.9 1.0 ENABLE VOLTAGE (V) 1.1 1.2 09288-044 VOUT (V) 0.8 Figure 48. Typical ENx Pin Operation Rev. A | Page 17 of 24 ADP322/ADP323 Data Sheet CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION The ADP322/ADP323 are protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP322/ADP323 are designed to current limit when the output load reaches 300 mA (typical). When the output load exceeds 300 mA, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is built in, which limits the junction temperature to a maximum of 155C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 155C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 140C, the output is turned on again and the output current is restored to its nominal value. Consider the case where a hard short from VOUTx to GND occurs. At first, the ADP322/ADP323 limits current so that only 300 mA is conducted into the short. If self-heating of the junction is great enough to cause its temperature to rise above 155C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 140C, the output turns on and conducts 300 mA into the short, again causing the junction temperature to rise above 155C. This thermal oscillation between 140C and 155C causes a current oscillation between 0 mA and 300 mA that continues as long as the short remains at the output. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125C. THERMAL CONSIDERATIONS In most applications, the ADP322/ADP323 do not dissipate a lot of heat due to high efficiency. However, in applications with a high ambient temperature and high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125C. When the junction temperature exceeds 155C, the converter enters thermal shutdown. It recovers only after the junction temperature decreases below 140C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2. To guarantee reliable operation, the junction temperature of the ADP322/ADP323 must not exceed 125C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (JA). The JA number is dependent on the package assembly compounds used and the amount of copper to which the GND pins of the package are soldered on the PCB. Table 7 shows typical JA values for the ADP322/ADP323 for various PCB copper sizes. Table 7. Typical JA Values Copper Size (mm2) JEDEC1 100 500 1000 1 ADP322/ADP323 Triple LDO (C/W) 49.5 83.7 68.5 64.7 Device soldered to JEDEC standard board. The junction temperature of the ADP322/ADP323 can be calculated from the following equation: TJ = TA + (PD x JA) (2) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN - VOUT) x ILOAD] + (VIN x IGND) (3) where: ILOAD is the load current. IGND is the ground current. VIN and VOUT are input and output voltages, respectively. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to TJ = TA + {[(VIN - VOUT) x ILOAD] x JA} (4) As shown in Equation 4, for a given ambient temperature, input-to-output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 125C. Figure 51 to Figure 54 show junction temperature calculations for different ambient temperatures, total power dissipation, and areas of PCB copper. In cases where the board temperature is known, the thermal characterization parameter, JB, can be used to estimate the junction temperature rise. TJ is calculated from TB and PD using the formula TJ = TB + (PD x JB) The typical JB value for the 16-lead, 3 mm x 3 mm LFCSP is 25.2C/W. Rev. A | Page 18 of 24 (5) ADP322/ADP323 140 120 120 JUNCTION TEMPERATURE, TJ (C) 140 60 40 1000mm 2 500mm 2 100mm 2 50mm 2 JEDEC TJ MAX 20 0 0 0.2 0.4 0.6 0.8 1.0 1.2 TOTAL POWER DISSIPATION (W) Figure 51. Junction Temperature vs. Total Power Dissipation, TA = 25C 60 40 120 JUNCTION TEMPERATURE, TJ (C) 120 60 40 1000mm 2 500mm 2 100mm 2 50mm 2 JEDEC TJ MAX 20 0 0 0.2 0.4 0.6 0.8 TOTAL POWER DISSIPATION (W) 1.0 1.2 0.2 0.4 0.6 0.8 1.0 1.2 Figure 53. Junction Temperature vs. Total Power Dissipation, TA = 85C 140 80 0 TOTAL POWER DISSIPATION (W) 140 100 1000mm 2 500mm 2 100mm 2 50mm 2 JEDEC TJ MAX 20 0 09288-048 JUNCTION TEMPERATURE, TJ (C) 80 09288-049 80 100 Figure 52. Junction Temperature vs. Total Power Dissipation, TA = 50C Rev. A | Page 19 of 24 100 80 60 40 TB = 25C TB = 50C TB = 85C TJ MAX 20 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 TOTAL POWER DISSIPATION (W) Figure 54. Junction Temperature vs. Total Power Dissipation and Board Temperature 09288-050 100 09288-047 JUNCTION TEMPERATURE, TJ (C) Data Sheet ADP322/ADP323 Data Sheet PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP322/ADP323. However, as can be seen from Table 7, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. 09288-051 Place the input capacitor as close as possible to the VINx and GND pins. Place the output capacitors as close as possible to the VOUTx and GND pins. Use 0402 or 0603 size capacitors and resistors to achieve the smallest possible footprint solution on boards where area is limited. 09288-052 Figure 55. Example of PCB Layout, Top Side Figure 56. Example of PCB Layout, Bottom Side Rev. A | Page 20 of 24 Data Sheet ADP322/ADP323 OUTLINE DIMENSIONS PIN 1 INDICATOR 3.10 3.00 SQ 2.90 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 16 13 1 12 1.65 1.50 SQ 1.45 EXPOSED PAD 9 0.80 0.75 0.70 SEATING PLANE 4 5 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 091609-A TOP VIEW 0.50 0.40 0.30 COMPLIANT TO JEDEC STANDARDS MO-229. Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm x 3 mm Body, Very, Very Thin Quad (CP-16-27) Dimensions shown in millimeters ORDERING GUIDE 1 Model ADP322ACPZ-115-R7 ADP322ACPZ-135-R7 ADP322ACPZ-145-R7 ADP322ACPZ-155-R7 ADP322ACPZ-165-R7 ADP322ACPZ-175-R7 ADP322ACPZ-189-R7 ADP323ACPZ-R7 ADP322CP-EVALZ ADP323CP-EVALZ ADP322CPZ-REDYKIT 1 2 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Output Voltage (V) 2 VOUT1 VOUT2 VOUT3 3.3 V 2.8 V 1.8 V 3.3 V 2.5 V 1.8 V 3.3 V 2.5 V 1.2 V 3.3 V 1.8 V 1.5 V 3.3 V 1.8 V 1.2V 2.8 V 1.8 V 1.2 V 2.5 V 1.8 V 1.2 V Adjustable Adjustable Adjustable Z = RoHS Compliant Part. For additional voltage options, contact a local sales or distribution representative. Rev. A | Page 21 of 24 Package Description 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ Evaluation board Evaluation board Evaluation board kit Package Option CP-16-27 CP-16-27 CP-16-27 CP-16-27 CP-16-27 CP-16-27 CP-16-27 CP-16-27 Branding LGU LGT LJC LGS LLX LGR LJD LGQ ADP322/ADP323 Data Sheet NOTES Rev. A | Page 22 of 24 Data Sheet ADP322/ADP323 NOTES Rev. A | Page 23 of 24 ADP322/ADP323 Data Sheet NOTES (c)2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09288-0-9/11(A) Rev. A | Page 24 of 24