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November 2012

FL6300A • Rev. 1.0.2

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

FL6300A

Quasi-Resonant Current Mode PWM Controller for Lighting

Features

 High-Voltage Startup

 Quasi-Resonant Operation

 Cycle-by-Cycle Current Limiting

 Peak-Current-Mode Control

 Leading-Edge Blanking (LEB)

 Internal Minimum tOFF

 Internal 5 ms Soft-Start

 Over-Power Compensation

 GATE Output Maximum Voltage

 Auto-Recovery Over-Current Protection (FB Pin)

 Auto-Recovery Open-Loop Protection (FB Pin)

 Latch Protection VDD Pin and Output Voltage (DET

Pin) OVP

 Frequency Operation Below 100 kHz

Applications

 General LED Lighting

 Industrial, Commercial, and Residential Fixtures

 Outdoor Lighting: Street, Roadway, Parking,

Construction, and Ornamental LED Lighting Fixtures

Description

The FL6300A lighting power controller includes a highly

integrated PWM controller and provides several features

to enhance the performance of flyback converters in

medium- to high-power lumens applications.

The FL6300A is applied on quasi-resonant flyback

converters, where maximum operating frequency is

limited to below 100 kHz. A built-in HV startup circuit

can provide more startup current to reduce the startup

time of the controller. Once the VDD voltage exceeds the

turn-on threshold voltage, the HV startup function is

disabled to reduce power consumption. An internal

valley voltage detector ensures that the power system

operates at quasi-resonant operation over a wide-range

of line voltage and load conditions, as well as reducing

switching loss to minimize switching voltage on the drain

of the power MOSFET.

To minimize standby power consumption and improve

light-load efficiency, a proprietary Green-Mode function

provides off-time modulation to decrease switching

frequency and perform extended valley voltage

switching to keep to a minimum switching pulse. The

operating frequency is limited by minimum tOFF time,

which is 38 µs to 8 µs.

FL6300A also provides many protection functions.

Pulse-by-pulse current limiting ensures the fixed-peak

current-limit level, even when a short circuit occurs.

Once an open-circuit failure occurs in the feedback loop,

the internal protection circuit disables PWM output

immediately. When VDD drops below the turn-off

threshold voltage, the controller disables PWM output.

The gate output is clamped at 18 V to protect the power

MOSFET from high gate-source voltage conditions. The

minimum tOFF time limit prevents the system frequency

from being too high. When over-voltage protection

(OVP) is triggered by DET or when internal over-

temperature protection (OTP) is triggered, the power

system enters Latch Mode until AC power is removed.

Ordering Information

Part Number Operating

Temperature Range Package Packing Method

FL6300AMY -40°C to +125°C 8-Lead, Small Outline Package (SOP) Tape & Reel

FL6300A • Rev. 1.0.2 2

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

Application Diagram

Figure 1. Typical Application Circuit for Flyback Converter

Internal Block Diagram

SOFT-START

5ms

0.3V

Latched

TWO STEPS

UVLO

16V/10V/8V

VDD

DET

GATE

CS 5

8 6

18V

VREF

4.2V 27V

OVER-POWER

COMPENSATION

LEB

tOFF_MIN

BLANKING S/H

VALLEY

DETECTOR

0.3V

2.5V

Latched

tOFF_OUT

2.1ms 30µs

STARTER

TIMER

52ms

PWM

Current Limit

IDET

VDET

GND

INTERNAL

OTP Latched

OVP

IHV

INTERNAL

BIAS

FB OLP

VDET

IDET

DET OVP

Figure 2. Functional Block Diagram

Marking Information

Figure 3. Marking Diagram

: Fairchild Logo

Z: Plant Code

X: Year Code

Y: Week Code

TT: Die Run Code

T: Package Type (M = SOP)

P: Y = Green Package

M: Manufacture Flow Code

FL6300A • Rev. 1.0.2 3

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

Pin Configuration

GND

DET

CS VDD

GATE

Figure 4. Pin Assignments

Pin Definitions

Pin # Name Description

1 DET

This pin is connected to an auxiliary winding of the transformer via resistors of the divider for the

following purposes:

- Generates a zero-current detection (ZCD) signal once the secondary-side switching current

falls to zero.

- Produces an offset voltage to compensate the threshold voltage of the peak current limit to

provide a constant power limit. The offset is generated in accordance with the input voltage

when PWM signal is enabled.

- Detects the valley voltage of the switching waveform to achieve the valley voltage switching

and minimize the switching losses.

A voltage comparator and a 2.5 V reference voltage develop an output OVP protection. The

ratio of the divider determines what output voltage to stop gate, as an optical coupler and

secondary shunt regulator are used.

2 FB

The feedback pin should to be connected to the output of the error amplifier for achieving the

voltage control loop. The FB pin should be connected to the output of the optical coupler if the

error amplifier is equipped at the secondary-side of the power converter.

For primary-side control applications, FB is applied to connect a RC network to the ground for

feedback-loop compensation.

The input impedance of this pin is a 5 k equivalent resistance. A one-third (1/3) attenuator

connected between the FB and the PWM circuit is used for the loop-gain attenuation. FL6300A

performs an open-loop protection (OLP) once the FB voltage is higher than a threshold voltage

(around 4.2 V) for more than 55ms.

3 CS

Input to the comparator of the over-current protection. A resistor senses the switching current

and the resulting voltage is applied to this pin for the cycle-by-cycle current limit.

4 GND

The power ground and signal ground. A 0.1 µF decoupling capacitor placed between VDD and

GND is recommended.

5 GATE

Totem-pole output generates the PWM signal to drive the external power MOSFET. The

clamped gate output voltage is 18 V.

6 VDD Power supply. The threshold voltages for startup and turn-off are 16 V and 10 V, respectively.

The startup current is less than 20 µA and the operating current is lower than 4.5 mA.

7 NC No connect

8 HV High-voltage startup

FL6300A • Rev. 1.0.2 4

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VVDD DC Supply Voltage 30 V

VHV HV 500 V

VH GATE -0.3 25.0 V

VL V

FB, VCS, VDET -0.3 7.0 V

PD Power Dissipation 400 mW

TJ Operating Junction Temperature +150 °C

TSTG Storage Temperature Range -55 +150 °C

TL Lead Temperature (Soldering 10 Seconds) +270 °C

ESD Human Body Model, JEDEC:JESD22-A114 3.0 KV

Charged Device Model, JEDEC:JESD22-C101 1.5

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

2. All voltage values, except differential voltages, are given with respect to GND pin.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

TA Operating Ambient Temperature -40 +125 °C

FL6300A • Rev. 1.0.2 5

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

Electrical Characteristics

Unless otherwise specified, VDD=10~25 V, TA=-40°C~125°C (TA=TJ).

Symbol Parameter Conditions Min. Typ. Max. Unit

VDD Section

VOP Continuously Operating Voltage 25 V

VDD-ON Turn-On Threshold Voltage 15 16 17 V

VDD-PWM-OFF PWM Off Threshold Voltage 9 10 11 V

VDD-OFF Turn-Off Threshold Voltage 7 8 9 V

IDD-ST Startup Current VDD=VDD-ON -0.16 V

GATE Open 10 20 µA

IDD-OP Operating Current VDD=15 V, fS=60 kHz,

CL=2 nF 4.5 5.5 mA

IDD-GREEN Green-Mode Operating Supply Current

(Average)

VDD=15 V, fS=2 kHz,

CL=2 nF 3.5 mA

IDD-PWM-OFF Operating Current at PWM-Off Phase VDD=VDD-PWM-OFF-0.5 V 70 80 90 µA

VDD-OVP V

DD Over-Voltage Protection (Latch-Off) 26 27 28 V

tVDD-OVP V

DD OVP Debounce Time 100 150 200 µs

IDD-LATCH V

DD OVP Latch-Up Holding Current VDD=5 V 42 µA

HV Startup Current Source Section

VHV-MIN Minimum Startup Voltage on Pin HV 50 V

IHV Supply Current Drawn from Pin HV VAC=90 V (VDC=120 V)

VDD=0 V 1.5 4.0 mA

IHV-LC Leakage Current After Startup HV=500 V,

VDD=VDD-OFF +1 V 1 20 µA

Feedback Input Section

AV Input-Voltage to Current Sense Attenuation AV=VCS/VFB,

0<VCS<0.9 1/2.75 1/3.00 1/3.25 V/V

ZFB Input Impedance 3 5 7 KΩ

IOZ Bias Current FB=VOZ 1.2 2.0 mA

VOZ Zero Duty Cycle Input Voltage 0.8 1.0 1.2 V

VFB-OLP Open-Loop Protection Threshold Voltage 3.9 4.2 4.5 V

tD-OLP Debounce Time for Open-Loop/Overload

Protection 46 52 62 ms

tSS Internal Soft-Start Time 5 ms

Continued on the following page...

FL6300A • Rev. 1.0.2 6

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

Electrical Characteristics (Continued)

Unless otherwise specified, VDD=10~25 V, TA=-40°C ~125°C (TA=TJ).

Symbol Parameter Conditions Min. Typ. Max. Unit

DET Pin OVP and Valley Detection Section

VDET-OVP Comparator Reference Voltage 2.45 2.50 2.55 V

Av Open-Loop Gain(3) 60 dB

Bw Gain Bandwidth(3) 1 MHz

VV-HIGH Output High Voltage 4.5 V

VV-LOW Output Low Voltage 0.5 V

tDET-OVP Output OVP (Latched) Debounce Time 100 150 200 µs

IDET-SOURCE Maximum Source Current VDET=0 V 1 mA

VDET-HIGH Upper Clamp Voltage IDET=-1 mA 5 V

VDET-LOW Lower Clamp Voltage IDET=1 mA 0.1 0.3 V

tVALLEY-DELAY Delay Time from Valley Signal Detected to

Output Turn-On(3) 200 ns

tOFF-BNK Leading-Edge-Blanking Time for DET

when PWM MOS Turns Off(3) 4 µs

tTIME-OUT Time-Out After tOFF-MIN 9 µs

Oscillator Section

tON-MAX Maximum On-Time 38 45 54 µs

tOFF-MIN Minimum Off-Time VFB≧VN, 8 µs

VFB=VG 38

VN Beginning of Green-On Mode at FB

Voltage Level 1.95 2.10 2.25 V

VG Beginning of Green-Off Mode at FB

Voltage Level 1.0 1.2 1.4 V

VFBG Green-Off Mode VFB Hysteresis Voltage 0.05 0.10 0.20 V

tSTARTER Start Timer (Time-Out Timer) VFB<VG 1.8 2.1 2.4 ms

VFB>VFB-OLP 25 30 45 µs

Output Section

VOL Output Voltage Low VDD=15 V,

IO=150 mA 1.5 V

VOH Output Voltage High VDD=12 V,

IO=150 mA 7.5 V

tR Rising Time 145 200 ns

tF Falling Time 55 120 ns

VCLAMP Gate Output Clamping Voltage 16.7 18.0 19.3 V

Continued on the following page…

FL6300A • Rev. 1.0.2 7

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

Electrical Characteristics (Continued)

Unless otherwise specified, VDD=10~25 V, TA=-40°C ~125°C (TA=TJ).

Symbol Parameter Conditions Min. Typ. Max. Unit

Current Sense Section

tPD Delay to Output 20 150 200 ns

VLIMIT Limit Voltage on CS Pin for Over-Power

Compensation

IDET < 74.41 µA 0.82 0.85 0.88 V

IDET=550 µA 0.380 0.415 0.450

VSLOPE Slope Compensation(3) tON=45 µs 0.3 V

tON=0 µs 0.1

tBNK Leading-Edge-Blanking Time

(MOS Turns ON) 525 625 725 ns

VCS-H VCS Clamped High Voltage once CS Pin

Floating CS Pin Floating 4.5 5.0 V

tCS-H Delay Time Once CS Pin Floating CS Pin Floating 150 µs

Internal Over-Temperature Protection Section

TOTP Internal Threshold Temperature for OTP(3) +140 °C

TOTP-HYST Hysteresis Temperature for Internal OTP(3) +15 °C

Note:

3. This parameter, although guaranteed by design, is not tested in production.

FL6300A • Rev. 1.0.2 8

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

Typical Performance Characteristics

Graphs are normalized at TA=25°C.

Figure 5. Turn-On Threshold Voltage Figure 6. PWM-Off Threshold Voltage

Figure 7. Turn-Off Threshold Voltage Figure 8. Startup Current

Figure 9. Operating Current Figure 10. Supply Current Drawn From HV Pin

Figure 11. Leakage Current

fter Startup Figure 12. Lower Clamp

oltage

15.0

15.5

16.0

16.5

17.0

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(

DD-ON

(V)

9.00

9.20

9.40

9.60

9.80

10.00

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(°C)

DD-PWM-OFF

(V)

7.5

7.6

7.7

7.8

7.9

8.0

8.1

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(oC)

VDD-OFF(V)

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(°C)

DD-ST

(µA)

3.00

3.30

3.60

3.90

4.20

4.50

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(°C)

DD-OP

(mA)

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(°C)

(mA)

0.25

0.26

0.27

0.28

0.29

0.30

0.31

0.32

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(°C)

HV-LC

(µA)

0.10

0.15

0.20

0.25

0.30

0.35

0.40

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(

DET-LOW

(V)

FL6300A • Rev. 1.0.2 9

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

Typical Performance Characteristics (Continued)

These characteristic graphs are normalized at TA = 25°C.

Figure 13. Comparator Reference Voltage Figure 14. Minimum Of

Time (VFB>VN)

Figure 15. Minimum Of

Time (VFB=VG) Figure 16. Start Timer (VFB<VG)

2.48

2.49

2.50

2.51

2.52

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(

DET-OVP

(V)

7.50

7.80

8.10

8.40

8.70

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(°C)

off-min

(µs)

32.0

34.0

36.0

38.0

40.0

42.0

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(

OFF-M IN

(μs)

1.90

2.00

2.10

2.20

2.30

2.40

2.50

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(°C)

STARTER

(ms)

FL6300A • Rev. 1.0.2 10

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

Operation Description

The FL6300A PWM controller integrates features to

enhance the performance of flyback converters. An

internal valley voltage detector ensures Quasi-Resonant

(QR) operation across a wide range of line voltage.

Startup Current

For startup, the HV pin is connected to the line input or

bulk capacitor through an external diode and resistor,

RHV, which are recommended as 1N4007 and 100 k.

Typical startup current drawn from the HV pin is 1.2 mA

and it charges the hold-up capacitor through the diode

and resistor. When the VDD voltage level reaches VDD-ON,

the startup current switches off. At this point, the VDD

capacitor only supplies the FL6300A to maintain VDD until

the auxiliary winding of the main transformer provides

the operating current.

Valley Detection

The DET pin is connected to an auxiliary winding of the

transformer via resistors of the divider to generate a

valley signal once the secondary-side switching current

discharges to zero. It detects the valley voltage of the

switching waveform to achieve the valley voltage

switching. This ensures QR operation, minimizes

switching losses, and reduces EMI. Figure 17 shows

divider resistors RDET and RA. RDET is recommended as

150 k to 220 k to achieve valley voltage switching.

When VAUX (in Figure 17) is negative, the DET pin

voltage is clamped to 0.3 V.

Figure 17. Valley Detect Section

The internal timer (minimum tOFF) prevents gate

retriggering within 8 µs after the gate signal going-LOW

transition. The minimum tOFF limit prevents system

frequency being too high. Figure 18 shows a typical drain

voltage waveform with first valley switching.

Figure 18. First Valley Switching

Green-Mode Operation

The proprietary green mode provides off-time modulation

to linearly decrease the switching frequency under light-

load conditions. VFB, which is derived from the voltage

feedback loop, is taken as the reference. In Figure 19,

once VFB is lower than VN, tOFF-MIN increases linearly with

lower VFB. The valley voltage detection signal does not

start until tOFF-MIN finishes. Therefore, the valley-detect

circuit is active until tOFF-MIN finishes, which decreases the

switching frequency and provides extended valley

voltage switching. However, in very light-load condition, it

might fail to detect the valley voltage after the tOFF-MIN

expires. Under this condition, an internal tTIME-OUT signal

initiates a new cycle after a 9 μs delay. Figure 20 and

Figure 21 show the two conditions.

Figure 19. VFB vs. tOFF-MIN Curve

Figure 20. QR Operation in Extended Valley Voltage

Detection Mode

Figure 21. Internal tTIME-OUT Initiates New Cycle After

Failure to Detect Valley Voltage

OFF-M IN

1.2V 2.1V

2.1ms

38/13μs

8/3μs

FL6300A • Rev. 1.0.2 11

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

Current Sensing and PWM Current Limiting

Peak-current-mode control is utilized to regulate output

voltage and provide pulse-by-pulse current limiting. The

switch current is detected by a sense resistor into the CS

pin. The PWM duty cycle is determined by this current-

sense signal and VFB. When the voltage on CS reaches

around VLIMIT=(VFB-1.2)/3, the switch cycle is terminated

immediately. VLIMIT is internally clamped to a variable

voltage around 0.85 V for output power limit.

Leading-Edge Blanking (LEB)

Each time the power MOFFET switches on, a turn-on

spike occurs on the sense resistor. To avoid premature

termination of the switching pulse, lead-edge blanking time

is built in. During the blanking period, the current limit

comparator is disabled; it cannot switch off the gate driver.

Under-Voltage Lockout (UVLO)

The turn-on, PWM-off, and turn-off thresholds are

fixed internally at 16 V / 10 V / 8 V, respectively.

During startup, the startup capacitor must be charged

to 16 V through the startup resistor to enable the IC.

The hold-up capacitor continues to supply VDD until

energy can be delivered from the auxiliary winding of

the main transformer. VDD must not drop below 10 V

during this startup process. This UVLO hysteresis

window ensures that hold-up capacitor is adequate to

supply VDD during startup.

Gate Output

The BiCMOS output stage is a fast totem-pole gate

driver. Cross conduction has been avoided to minimize

heat dissipation, increase efficiency, and enhance

reliability. The output driver is clamped by an internal

18 V Zener diode to protect power MOSFET transistors

against undesired over-voltage gate signals.

Over-Power Compensation

To compensate for the variation of a wide AC input

range, the DET pin produces an offset voltage to

compensate the threshold voltage of the peak current

limit for a constant-power limit. The offset is generated

in accordance with the input voltage when PWM signal

is enabled. This results in a lower current limit at high-

line inputs than low-line inputs. At fixed-load condition,

the CS limit is higher when the value of RDET is higher.

RDET also affects the H/L line constant power limit.

VDD RDET

VAUX

VIN

DET 1

GATE

GND

Figure 22. H/L Line Constant Power Limit

Compensated by DET Pin

VDD Over-Voltage Protection

VDD over-voltage protection prevents damage due to

abnormal conditions. Once the VDD voltage is over the

VDD over-voltage protection voltage (VDD-OVP) and lasts

for tVDDOVP, the PWM pulse is disabled until the VDD

voltage drops below the UVLO, then starts again.

Output Over-Voltage Protection

The output over-voltage protection works by the

sampling voltage, as shown in Figure 23, after switch-

off sequence. A 4 μs blanking time ignores the leakage

inductance ringing. A voltage comparator and a 2.5 V

reference voltage develop an output OVP protection.

The ratio of the divider determines the sampling voltage

of the stop gate, as an optical coupler and secondary

shunt regulator are used. If the DET pin OVP is

triggered, the power system enters latch-mode until AC

power is removed.

Figure 23. Voltage Sampled After 4 μs

Blanking Time After Switch-Off Sequence

Short-Circuit and Open-Loop Protection

The FB voltage increases every time the output of the

power supply is shorted or overloaded. If the FB voltage

remains higher than a built-in threshold for longer than

tD-OLP, PWM output is turned off. As PWM output is

turned-off, the supply voltage VDD begins decreasing.

When VDD goes below the PWM-off threshold of 10 V,

VDD decreases to 8 V, then the controller is totally shut

down. VDD is charged up to the turn-on threshold voltage

of 16 V through the startup resistor until PWM output is

restarted. This protection feature continues as long as

the overloading condition persists. This prevents the

power supply from overheating due to overloading.

FL6300A • Rev. 1.0.2 12

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

Physical Dimensions

Figure 24. 8-Pin Small Outline Package (SOP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the mo st recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

8°

0°

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

LAND PATTERN RECOMMENDATION

SEATING PLANE

0.10 C

GAGE PLANE

x 45°

DETAIL A

SCALE: 2:1

PIN ONE

INDICATOR

MBA0.25

5.60

0.65

1.75

1.27

6.20

5.80

3.81

4.00

3.80

5.00

4.80

(0.33)

1.27

0.51

0.33

0.25

0.10

1.75 MAX

0.25

0.19

0.36

0.50

0.25

R0.10

0.90

0.406 (1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

FL6300A • Rev. 1.0.2 13

FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting

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