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FL6300A Quasi-Resonant Current Mode PWM Controller for Lighting Features Description High-Voltage Startup Quasi-Resonant Operation Cycle-by-Cycle Current Limiting Peak-Current-Mode Control Leading-Edge Blanking (LEB) Internal Minimum tOFF Internal 5 ms Soft-Start Over-Power Compensation GATE Output Maximum Voltage Auto-Recovery Over-Current Protection (FB Pin) Auto-Recovery Open-Loop Protection (FB Pin) Latch Protection VDD Pin and Output Voltage (DET The FL6300A lighting power controller includes a highly integrated PWM controller and provides several features to enhance the performance of flyback converters in medium- to high-power lumens applications. Pin) OVP Frequency Operation Below 100 kHz Applications General LED Lighting Industrial, Commercial, and Residential Fixtures Outdoor Lighting: Street, Roadway, Parking, Construction, and Ornamental LED Lighting Fixtures The FL6300A is applied on quasi-resonant flyback converters, where maximum operating frequency is limited to below 100 kHz. A built-in HV startup circuit can provide more startup current to reduce the startup time of the controller. Once the VDD voltage exceeds the turn-on threshold voltage, the HV startup function is disabled to reduce power consumption. An internal valley voltage detector ensures that the power system operates at quasi-resonant operation over a wide-range of line voltage and load conditions, as well as reducing switching loss to minimize switching voltage on the drain of the power MOSFET. To minimize standby power consumption and improve light-load efficiency, a proprietary Green-Mode function provides off-time modulation to decrease switching frequency and perform extended valley voltage switching to keep to a minimum switching pulse. The operating frequency is limited by minimum tOFF time, which is 38 s to 8 s. FL6300A also provides many protection functions. Pulse-by-pulse current limiting ensures the fixed-peak current-limit level, even when a short circuit occurs. Once an open-circuit failure occurs in the feedback loop, the internal protection circuit disables PWM output immediately. When VDD drops below the turn-off threshold voltage, the controller disables PWM output. The gate output is clamped at 18 V to protect the power MOSFET from high gate-source voltage conditions. The minimum tOFF time limit prevents the system frequency from being too high. When over-voltage protection (OVP) is triggered by DET or when internal overtemperature protection (OTP) is triggered, the power system enters Latch Mode until AC power is removed. Ordering Information Part Number Operating Temperature Range Package Packing Method FL6300AMY -40C to +125C 8-Lead, Small Outline Package (SOP) Tape & Reel (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 www.fairchildsemi.com FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting November 2012 Figure 1. Typical Application Circuit for Flyback Converter Internal Block Diagram HV VDD 8 6 IHV INTERNAL BIAS OVP TIMER 52ms 4.2V VREF VDD 30s 2R SOFT-START 5ms 2 Latched 27V STARTER 2.1ms FB FB OLP TWO STEPS UVLO 16V/10V/8V 1R S CS 3 Q PWM Current Limit LEB OVER-POWER COMPENSATION VALLEY DETECTOR VDET tOFF_MIN BLANKING S/H tOFF_OUT 7 NC VDET 2.5V Latched INTERNAL OTP DET 1 5V IDET 5 GATE DET OVP IDET 0.3V tOFF_MIN 18V R FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting Application Diagram Latched 4 GND 0.3V Figure 2. Functional Block Diagram Marking Information : Fairchild Logo Z: Plant Code X: Year Code Y: Week Code TT: Die Run Code T: Package Type (M = SOP) P: Y = Green Package M: Manufacture Flow Code Figure 3. Marking Diagram (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 www.fairchildsemi.com 2 DET 1 8 HV FB 2 7 NC CS 3 6 VDD GND 4 5 GATE Figure 4. Pin Assignments Pin Definitions Pin # Name Description DET This pin is connected to an auxiliary winding of the transformer via resistors of the divider for the following purposes: - Generates a zero-current detection (ZCD) signal once the secondary-side switching current falls to zero. - Produces an offset voltage to compensate the threshold voltage of the peak current limit to provide a constant power limit. The offset is generated in accordance with the input voltage when PWM signal is enabled. - Detects the valley voltage of the switching waveform to achieve the valley voltage switching and minimize the switching losses. A voltage comparator and a 2.5 V reference voltage develop an output OVP protection. The ratio of the divider determines what output voltage to stop gate, as an optical coupler and secondary shunt regulator are used. 2 FB The feedback pin should to be connected to the output of the error amplifier for achieving the voltage control loop. The FB pin should be connected to the output of the optical coupler if the error amplifier is equipped at the secondary-side of the power converter. For primary-side control applications, FB is applied to connect a RC network to the ground for feedback-loop compensation. The input impedance of this pin is a 5 k equivalent resistance. A one-third (1/3) attenuator connected between the FB and the PWM circuit is used for the loop-gain attenuation. FL6300A performs an open-loop protection (OLP) once the FB voltage is higher than a threshold voltage (around 4.2 V) for more than 55ms. 3 CS Input to the comparator of the over-current protection. A resistor senses the switching current and the resulting voltage is applied to this pin for the cycle-by-cycle current limit. 4 GND The power ground and signal ground. A 0.1 F decoupling capacitor placed between VDD and GND is recommended. 5 GATE Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 18 V. 6 VDD Power supply. The threshold voltages for startup and turn-off are 16 V and 10 V, respectively. The startup current is less than 20 A and the operating current is lower than 4.5 mA. 7 NC No connect 8 HV High-voltage startup 1 (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting Pin Configuration www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit 30 V VVDD DC Supply Voltage VHV HV 500 V VH GATE -0.3 25.0 V VL VFB, VCS, VDET -0.3 7.0 V PD Power Dissipation 400 mW TJ Operating Junction Temperature +150 C +150 C +270 C TSTG TL ESD Storage Temperature Range -55 Lead Temperature (Soldering 10 Seconds) Human Body Model, JEDEC:JESD22-A114 3.0 Charged Device Model, JEDEC:JESD22-C101 1.5 KV Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 Min. Max. Unit -40 +125 C FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting Absolute Maximum Ratings www.fairchildsemi.com 4 Unless otherwise specified, VDD=10~25 V, TA=-40C~125C (TA=TJ). Symbol Parameter Conditions Min. Typ. Max. Unit 25 V VDD Section VOP Continuously Operating Voltage VDD-ON Turn-On Threshold Voltage 15 16 17 V VDD-PWM-OFF PWM Off Threshold Voltage 9 10 11 V VDD-OFF Turn-Off Threshold Voltage 7 8 9 V IDD-ST Startup Current VDD=VDD-ON -0.16 V GATE Open 10 20 A IDD-OP Operating Current VDD=15 V, fS=60 kHz, CL=2 nF 4.5 5.5 mA IDD-GREEN Green-Mode Operating Supply Current (Average) VDD=15 V, fS=2 kHz, CL=2 nF 3.5 mA IDD-PWM-OFF Operating Current at PWM-Off Phase VDD=VDD-PWM-OFF-0.5 V 70 80 90 A VDD-OVP VDD Over-Voltage Protection (Latch-Off) 26 27 28 V tVDD-OVP VDD OVP Debounce Time 100 150 200 s IDD-LATCH VDD OVP Latch-Up Holding Current VDD=5 V 42 A HV Startup Current Source Section VHV-MIN Minimum Startup Voltage on Pin HV IHV Supply Current Drawn from Pin HV VAC=90 V (VDC=120 V) VDD=0 V Leakage Current After Startup HV=500 V, VDD=VDD-OFF +1 V IHV-LC 50 V 4.0 mA 1 20 A 1/2.75 1/3.00 1/3.25 V/V 3 5 7 K 1.2 2.0 mA 1.5 Feedback Input Section AV=VCS/VFB, 0<VCS<0.9 AV Input-Voltage to Current Sense Attenuation ZFB Input Impedance IOZ Bias Current VOZ Zero Duty Cycle Input Voltage 0.8 1.0 1.2 V VFB-OLP Open-Loop Protection Threshold Voltage 3.9 4.2 4.5 V tD-OLP Debounce Time for Open-Loop/Overload Protection 46 52 62 ms tSS FB=VOZ Internal Soft-Start Time 5 FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting Electrical Characteristics ms Continued on the following page... (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 www.fairchildsemi.com 5 Unless otherwise specified, VDD=10~25 V, TA=-40C ~125C (TA=TJ). Symbol Parameter Conditions Min. Typ. Max. Unit 2.45 2.50 2.55 V DET Pin OVP and Valley Detection Section VDET-OVP Av Bw Comparator Reference Voltage (3) Open-Loop Gain (3) Gain Bandwidth VV-HIGH Output High Voltage VV-LOW Output Low Voltage tDET-OVP Output OVP (Latched) Debounce Time IDET-SOURCE 60 dB 1 MHz 4.5 100 V 150 0.5 V 200 s Maximum Source Current VDET=0 V 1 mA VDET-HIGH Upper Clamp Voltage IDET=-1 mA 5 V VDET-LOW Lower Clamp Voltage IDET=1 mA tVALLEY-DELAY 0.1 Delay Time from Valley Signal Detected to Output Turn-On(3) 0.3 V 200 ns tOFF-BNK Leading-Edge-Blanking Time for DET when PWM MOS Turns Off(3) 4 s tTIME-OUT Time-Out After tOFF-MIN 9 s Oscillator Section tON-MAX Maximum On-Time tOFF-MIN Minimum Off-Time 38 45 VFBVN, 8 VFB=VG 38 54 s s VN Beginning of Green-On Mode at FB Voltage Level 1.95 2.10 2.25 V VG Beginning of Green-Off Mode at FB Voltage Level 1.0 1.2 1.4 V VFBG tSTARTER Green-Off Mode VFB Hysteresis Voltage Start Timer (Time-Out Timer) 0.05 0.10 0.20 V VFB<VG 1.8 2.1 2.4 ms VFB>VFB-OLP 25 30 45 s 1.5 V FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting Electrical Characteristics (Continued) Output Section VOL Output Voltage Low VDD=15 V, IO=150 mA VOH Output Voltage High VDD=12 V, IO=150 mA 7.5 V tR Rising Time 145 200 ns tF Falling Time 55 120 ns 18.0 19.3 V VCLAMP Gate Output Clamping Voltage 16.7 Continued on the following page... (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 www.fairchildsemi.com 6 Unless otherwise specified, VDD=10~25 V, TA=-40C ~125C (TA=TJ). Symbol Parameter Conditions Min. Typ. Max. Unit 20 150 200 ns Current Sense Section tPD Delay to Output VLIMIT Limit Voltage on CS Pin for Over-Power Compensation VSLOPE Slope Compensation(3) tBNK IDET < 74.41 A 0.82 0.85 0.88 IDET=550 A 0.380 0.415 0.450 tON=45 s 0.3 tON=0 s 0.1 Leading-Edge-Blanking Time (MOS Turns ON) 525 VCS-H VCS Clamped High Voltage once CS Pin Floating CS Pin Floating tCS-H Delay Time Once CS Pin Floating CS Pin Floating 625 4.5 V V 725 ns 5.0 V 150 s Internal Over-Temperature Protection Section TOTP Internal Threshold Temperature for OTP(3) +140 C TOTP-HYST Hysteresis Temperature for Internal OTP(3) +15 C Note: 3. This parameter, although guaranteed by design, is not tested in production. (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting Electrical Characteristics (Continued) www.fairchildsemi.com 7 Graphs are normalized at TA=25C. 10.00 17.0 9.80 V DD-P WM -O FF (V) V D D -ON (V) 16.5 16.0 9.60 9.40 15.5 9.20 15.0 -40 -25 -10 5 9.00 20 35 50 65 80 95 110 125 -40 Temperature(oC) -10 5 20 35 50 65 Temperature(C) 80 95 110 125 Figure 6. PWM-Off Threshold Voltage 8.1 18 8.0 16 7.9 14 IDD-ST(A) VDD-OFF (V) Figure 5. Turn-On Threshold Voltage -25 7.8 12 7.7 10 7.6 8 7.5 6 -40 -25 -10 5 -40 20 35 50 65 80 95 110 125 -25 -10 5 20 o Temperature( C) 35 50 65 80 95 110 125 Temperature(C) Figure 7. Turn-Off Threshold Voltage Figure 8. Startup Current 4.0 4.50 3.5 4.20 I HV(mA) IDD-O P (m A) 3.0 3.90 3.60 2.5 2.0 1.5 3.30 1.0 3.00 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -25 -10 5 20 Figure 9. Operating Current 50 65 80 95 110 125 Figure 10. Supply Current Drawn From HV Pin 0.32 0.40 0.31 0.35 0.30 0.30 V DET-LOW (V) 0.29 0.28 0.25 0.27 0.20 0.26 0.15 0.25 -40 -25 -10 35 Temperature(C) Temperature(C) IHV-LC(A) FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting Typical Performance Characteristics 5 0.10 20 35 50 65 80 95 110 125 -40 -25 -10 Temperature(C) 20 35 50 65 80 95 110 125 Temperature(oC) Figure 11. Leakage Current After Startup (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 5 Figure 12. Lower Clamp Voltage www.fairchildsemi.com 8 These characteristic graphs are normalized at TA = 25C. 8.70 2.52 8.40 toff-min(s) V DET -OVP(V) 2.51 2.50 2.49 8.10 7.80 2.48 -40 -25 -10 5 20 35 50 65 80 95 110 125 7.50 -40 -25 -10 Temperature(oC) 35 50 65 80 95 110 125 Figure 14. Minimum Off Time (VFB>VN) 42.0 2.50 40.0 2.40 tSTARTER(ms) t OF F -M IN(s) 20 Temperature(C) Figure 13. Comparator Reference Voltage 38.0 36.0 34.0 2.30 2.20 2.10 2.00 1.90 32.0 -40 -25 -10 5 5 20 35 50 65 -40 -25 -10 5 80 95 110 125 Temperature( C) Figure 15. Minimum Off Time (VFB=VG) (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 20 35 50 65 80 95 110 125 Temperature(C) o Figure 16. Start Timer (VFB<VG) FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting Typical Performance Characteristics (Continued) www.fairchildsemi.com 9 The FL6300A PWM controller integrates features to enhance the performance of flyback converters. An internal valley voltage detector ensures Quasi-Resonant (QR) operation across a wide range of line voltage. Green-Mode Operation The proprietary green mode provides off-time modulation to linearly decrease the switching frequency under lightload conditions. VFB, which is derived from the voltage feedback loop, is taken as the reference. In Figure 19, once VFB is lower than VN, tOFF-MIN increases linearly with lower VFB. The valley voltage detection signal does not start until tOFF-MIN finishes. Therefore, the valley-detect circuit is active until tOFF-MIN finishes, which decreases the switching frequency and provides extended valley voltage switching. However, in very light-load condition, it might fail to detect the valley voltage after the tOFF-MIN expires. Under this condition, an internal tTIME-OUT signal initiates a new cycle after a 9 s delay. Figure 20 and Figure 21 show the two conditions. Startup Current For startup, the HV pin is connected to the line input or bulk capacitor through an external diode and resistor, RHV, which are recommended as 1N4007 and 100 k. Typical startup current drawn from the HV pin is 1.2 mA and it charges the hold-up capacitor through the diode and resistor. When the VDD voltage level reaches VDD-ON, the startup current switches off. At this point, the VDD capacitor only supplies the FL6300A to maintain VDD until the auxiliary winding of the main transformer provides the operating current. Valley Detection tO F F -M I N 2 .1 m s The DET pin is connected to an auxiliary winding of the transformer via resistors of the divider to generate a valley signal once the secondary-side switching current discharges to zero. It detects the valley voltage of the switching waveform to achieve the valley voltage switching. This ensures QR operation, minimizes switching losses, and reduces EMI. Figure 17 shows divider resistors RDET and RA. RDET is recommended as 150 k to 220 k to achieve valley voltage switching. When VAUX (in Figure 17) is negative, the DET pin voltage is clamped to 0.3 V. 38/13 s 8 /3 s 1 .2 V VFB 2 .1 V Figure 19. VFB vs. tOFF-MIN Curve FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting Operation Description Figure 17. Valley Detect Section The internal timer (minimum tOFF) prevents gate retriggering within 8 s after the gate signal going-LOW transition. The minimum tOFF limit prevents system frequency being too high. Figure 18 shows a typical drain voltage waveform with first valley switching. Figure 20. QR Operation in Extended Valley Voltage Detection Mode Figure 18. First Valley Switching (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 Figure 21. Internal tTIME-OUT Initiates New Cycle After Failure to Detect Valley Voltage www.fairchildsemi.com 10 VDD Over-Voltage Protection Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the CS pin. The PWM duty cycle is determined by this currentsense signal and VFB. When the voltage on CS reaches around VLIMIT=(VFB-1.2)/3, the switch cycle is terminated immediately. VLIMIT is internally clamped to a variable voltage around 0.85 V for output power limit. VDD over-voltage protection prevents damage due to abnormal conditions. Once the VDD voltage is over the VDD over-voltage protection voltage (VDD-OVP) and lasts for tVDDOVP, the PWM pulse is disabled until the VDD voltage drops below the UVLO, then starts again. Output Over-Voltage Protection The output over-voltage protection works by the sampling voltage, as shown in Figure 23, after switchoff sequence. A 4 s blanking time ignores the leakage inductance ringing. A voltage comparator and a 2.5 V reference voltage develop an output OVP protection. The ratio of the divider determines the sampling voltage of the stop gate, as an optical coupler and secondary shunt regulator are used. If the DET pin OVP is triggered, the power system enters latch-mode until AC power is removed. Leading-Edge Blanking (LEB) Each time the power MOFFET switches on, a turn-on spike occurs on the sense resistor. To avoid premature termination of the switching pulse, lead-edge blanking time is built in. During the blanking period, the current limit comparator is disabled; it cannot switch off the gate driver. Under-Voltage Lockout (UVLO) The turn-on, PWM-off, and turn-off thresholds are fixed internally at 16 V / 10 V / 8 V, respectively. During startup, the startup capacitor must be charged to 16 V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD until energy can be delivered from the auxiliary winding of the main transformer. V DD must not drop below 10 V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup. Gate Output The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18 V Zener diode to protect power MOSFET transistors against undesired over-voltage gate signals. Figure 23. Voltage Sampled After 4 s Blanking Time After Switch-Off Sequence Short-Circuit and Open-Loop Protection Over-Power Compensation The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned-off, the supply voltage VDD begins decreasing. To compensate for the variation of a wide AC input range, the DET pin produces an offset voltage to compensate the threshold voltage of the peak current limit for a constant-power limit. The offset is generated in accordance with the input voltage when PWM signal is enabled. This results in a lower current limit at highline inputs than low-line inputs. At fixed-load condition, the CS limit is higher when the value of RDET is higher. RDET also affects the H/L line constant power limit. VAUX 6 When VDD goes below the PWM-off threshold of 10 V, VDD decreases to 8 V, then the controller is totally shut down. VDD is charged up to the turn-on threshold voltage of 16 V through the startup resistor until PWM output is restarted. This protection feature continues as long as the overloading condition persists. This prevents the power supply from overheating due to overloading. VIN RDET VDD FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting Current Sensing and PWM Current Limiting DET 1 RA GATE 5 ON CS 3 RS GND 4 Figure 22. H/L Line Constant Power Limit Compensated by DET Pin (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 www.fairchildsemi.com 11 5.00 4.80 A 0.65 3.81 8 5 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX 0.25 0.19 C 0.10 0.51 0.33 0.50 x 45 0.25 R0.10 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting Physical Dimensions OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8 0 0.90 0.406 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 24. 8-Pin Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 www.fairchildsemi.com 12 FL6300A -- Quasi-Resonant Current Mode PWM Controller for Lighting (c) 2010 Fairchild Semiconductor Corporation FL6300A * Rev. 1.0.2 www.fairchildsemi.com 13 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. "Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. 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