LTC2962/LTC2963/LTC2964
1
Rev 0
For more information www.analog.com
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents including 6967591, 7239251, 7119714.
TYPICAL APPLICATION
FEATURES DESCRIPTION
±0.5% Accurate Quad
Configurable Supervisor
The LT C
®
2962 series of configurable power supply moni-
tors can supervise systems with up to four supply volt-
ages. One of 16 preset or adjustable voltage monitor
thresholds per channel can be selected using external 1%
resistors connected to the programming (PG) inputs. The
preset voltage thresholds are accurate to ±0.5% over tem-
perature. Positive (+ADJ) and negative (–ADJ) adjustable
inputs with a 0.5V threshold allow undervoltage, negative
voltage and overvoltage monitoring.
The watchdog (LTC2963 only) and reset timeout periods
are adjustable using external capacitors. Accurate volt-
age thresholds and comparator glitch immunity ensure
reliable reset operation without false triggering. The RST
output is guaranteed to be in the correct state for V
CC
input voltage down to 1V.
The flexibility of the LTC2962 family provides the ability
to monitor a wide variety of power supply combinations,
including multiple supplies of the same voltage, with
±0.5% accuracy.
APPLICATIONS
n Simultaneously Monitor Four Power Supplies
n ±0.5% Threshold Accuracy Over Temperature
n Selectable –4% and –6% Thresholds per Supply:
5V, 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 1V and ±ADJ
n Adjustable Reset (RST) Timeout
n Overvoltage and Negative Voltage Monitoring
n Push-Pull or Open-Drain RST Output
n Margin Pin RDIS for Reset Disable
n H-Grade Temperature Range
n LTC2963
Non-Windowed (–1) Watchdog
Adjustable Watchdog Timer
Watchdog Status Output WDO
Selectable Initial Watchdog Timeout
n LTC2964
Individual Comparator Open-drain Outputs
n 16-Lead 3mm × 3mm QFN (LTC2962)
n 20-Lead 3mm × 4mm QFN (LTC2963, LTC2964)
n High Reliability Systems
n Network, Telecom and Server Systems
n Automotive Control Systems
Typical Distribution of Monitor
Threshold Error
LTC2962
R5
30.1k
296234 TA01a
PG1
REF
R4
20k
VCC
PG2
R3
20k
0 TO 5
1% CONFIGURATION
RESISTORS PG3
MR
RDIS
R2
20k PG4 MANUAL
RESET
56ms RESET TIMEOUT
GND
2.5V
3.3V
1.8V
1.5V
SYSTEM
LOGIC
2.5V
3.3V
1.8V
1.5V
DC/DC
R1
60.4k CRT
47nF
V1 V2 V3 V4 DVCC
RT
0.1µF 0.1µF
RST
494 PARTS ( 31616 TRESHOLDS )
THRESHOLD ERROR (%)
–0.2
–0.15
–0.1
–0.05
0
0.05
0.1
0.15
0.2
0
5
PERCENTAGE OF THRESHOLDS (%)
296234 TA01b
Document Feedback
LTC2962/LTC2963/LTC2964
2
Rev 0
For more information www.analog.com
ABSOLUTE MAXIMUM RATINGS
V1 - V4, MR, RDIS, WDI, DVCC, VCC ............ –0.3V to 6V
PG1 - PG4, REF ......................................... –0.3V to 1.5V
OUT1 - OUT4 ................................................ –0.3V to 6V
RT, WT, WDS ................................–0.3V to (VCC + 0.3V)
RST, WDO (DVCC ≥ 1.6V) ........... –0.3V to (DVCC + 0.3V)
RST, WDO (DVCC = GND) ............................. –0.3V to 6V
Reference Load Current (IREF) ............................... ±1mA
(Notes 1, 2)
ORDER INFORMATION
TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2962CUD#PBF LTC2962CUD#TRPBF LGZZ 16-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C
LTC2962IUD#PBF LTC2962IUD#TRPBF LGZZ 16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C
LTC2962HUD#PBF LTC2962HUD#TRPBF LGZZ 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C
LTC2963CUDC-1#PBF LTC2963CUDC-1#TRPBF LHBC 20-Lead (3mm × 4mm) Plastic QFN 0°C to 70°C
LTC2963IUDC-1#PBF LTC2963IUDC-1#TRPBF LHBC 20-Lead (3mm × 4mm) Plastic QFN –40°C to 85°C
LTC2963HUDC-1#PBF LTC2963HUDC-1#TRPBF LHBC 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LTC2964CUDC#PBF LTC2964CUDC#TRPBF LHBB 20-Lead (3mm × 4mm) Plastic QFN 0°C to 70°C
LTC2964IUDC#PBF LTC2964IUDC#TRPBF LHBB 20-Lead (3mm × 4mm) Plastic QFN –40°C to 85°C
LTC2964HUDC#PBF LTC2964HUDC#TRPBF LHBB 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
LTC2962 LTC2963 LTC2964
16 15 14
17
13
5678
TOP VIEW
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
9
10
11
12
4
3
2
1
RDIS
MR
DV
CC
VCC
REF
PG1
PG2
PG3
V1
V2
V3
V4
RST
GND
RT
PG4
TJMAX = 125°C, JA = 68°C/W, JC = 7.5°C/W
EXPOSED PAD (PIN 17) PCB GND CONNECTION OPTIONAL
20 19 18 17
7 8
TOP VIEW
21
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
9 10
6
5
4
3
2
1
11
12
13
14
15
16
RDIS
MR
DV
CC
VCC
RST
GND
REF
PG1
PG2
PG3
PG4
RT
V1
V2
V3
V4
WD0
WDI
WDS
WT
TJMAX = 125°C, JA = 52°C/W, JC = 6.8°C/W
EXPOSED PAD (PIN 21) PCB GND CONNECTION OPTIONAL
20 19 18 17
7 8
TOP VIEW
21
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
9 10
6
5
4
3
2
1
11
12
13
14
15
16
RDIS
MR
DV
CC
VCC
RST
GND
REF
PG1
PG2
PG3
PG4
RT
V1
V2
V3
V4
OUT1
OUT2
OUT3
OUT4
TJMAX = 125°C, JA = 52°C/W, JC = 6.8°C/W
EXPOSED PAD (PIN 21) PCB GND CONNECTION OPTIONAL
PIN CONFIGURATION
RST, WDO, OUT1 - OUT4 Currents ....................... ±10mA
Operating Temperature Range
C-Grade ................................................... 0°C to 70°C
I-Grade.................................................–40°C to 85°C
H-Grade ............................................. –40°C to 125°C
Storage Temperature Range ......................–65 to 150°C
LTC2962/LTC2963/LTC2964
3
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, DVCC = 0V, MR = RDIS = VCC, unless otherwise specified.
(Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Operating Range l2.25 5.5 V
Guaranteed RST Output Low VCC Rising l1 V
VCCMINC Minimum Required for Configuration VCC Rising l2.2 V
IVCC VCC Input Supply Current l80 140 210 µA
DVCC Operating Range l1.6 5.5 V
DVCC Input Supply Current IRST = 0, IWDO = 0 l25 500 nA
VRT50 5V, –4% Reset Threshold
5V, –6% Reset Threshold
l
l
4.775
4.675
4.8
4.7
4.825
4.725
V
V
VRT33 3.3V, –4% Reset Threshold
3.3V, –6% Reset Threshold
l
l
3.152
3.087
3.168
3.102
3.185
3.119
V
V
VRT25 2.5V, –4% Reset Threshold
2.5V, –6% Reset Threshold
l
l
2.388
2.338
2.4
2.35
2.413
2.363
V
V
VRT18 1.8V, –4% Reset Threshold
1.8V, –6% Reset Threshold
l
l
1.719
1.683
1.728
1.692
1.737
1.701
V
V
VRT15 1.5V, –4% Reset Threshold
1.5V, –6% Reset Threshold
l
l
1.433
1.403
1.44
1.41
1.448
1.418
V
V
VRT12 1.2V, –4% Reset Threshold
1.2V, –6% Reset Threshold
l
l
1.146
1.122
1.152
1.128
1.158
1.134
V
V
VRT10 1.0V, –4% Reset Threshold
1.0V, –6% Reset Threshold
l
l
0.955
0.935
0.96
0.94
0.965
0.945
V
V
VRTA ±ADJ Reset Threshold l497.5 500 502.5 mV
VREF Reference Voltage VCC = 2.25V to 5.5V, IREF = ±1mA,
CREF ≤ 1000pF
l1.183 1.195 1.207 V
VPG PG1 to PG4 Configuration Voltage Range VCC > VCCMINC l0 VREF V
IMON Monitor Input Current for V1 - V4 ±ADJ Modes (Vn = 0.5V) l±15 nA
RMON Monitor Input Resistance for V1 - V4 All Modes Except ±ADJ 0.8 1.2 1.6 MΩ
tUV Comparator Propagation Delay to RST
or OUTn Falling Edge
Overdrive = 10% l20 40 µs
RT and WT Pull-Up Current V = GND l–1.5 –2 –2.5 µA
RT and WT Pull-Down Current V = 1.3V l1.5 2 2.5 µA
tRST Reset Timeout Period CRT = 1500pF
VRT = VCC
l
l
12
160
18
200
24
240
ms
ms
Internal Timer Select Level (WT and RT) lVCC – 0.1 V
VCC-Detect Current in Internal Timer Mode (WT and RT) V = VCC l1 2 µA
LTC2963 Watchdog
tWDU Watchdog Upper Timeout Period CWT = 1500pF
WT Tied to VCC
l
l
100
1.3
150
1.6
200
2
ms
s
tWD(INIT) Initial Watchdog Timeout Period WDS = Logic Low
WDS = Open
WDS = Logic High
l
l
l
tWDU
8 • tWDU
64 • tWDU
VWDS WDS Input Level
(VCC = 2.25 to 5.5V)
Logic Low
Open
Logic High
l
l
l
0.7
VCC – 0.3
1.3
0.4
VCC – 0.7
V
V
V
LTC2962/LTC2963/LTC2964
4
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
Note 3: The RST and WDO pins are push-pull outputs that swing to DVCC
when DVCC is greater than 1.6V.
Note 4: The output pins, OUT1 - OUT4, have internal pull-ups to VCC of
typically 6µA. However, external pull-up resistors may be used when faster
rise times are required or for VOH voltages greater than VCC.
IWDS WDS Input Current VWDS = GND
VWDS = VCC
l
l
–4 –2.6
2.6
4
µA
µA
IWDS(HZ) Allowable WDS Leakage in Open State l±1 µA
tWDI,MAX Rise/Fall Time of WDI Edge 2 µs
tWP WDI Input Pulse Width VCC = 2.25V to 5.5V l2 µs
tWD WDI to WDO Propagation Delay l0.5 µs
Logic I/O
VOL Voltage Output Low RST, WDO (Note 3)
RST Only
ISINK = 3mA, VCC = 2.25V to 5.5V l40 150 mV
ISINK = 100µA, VCC = 1.1V l10 60 mV
Voltage Output Low OUTn (LTC2964, Note 4) ISINK = 5mA, VCC = 2.25V to 5.5V l50 300 mV
VOH Voltage Output High RST, WDO (Note 3) ISOURCE = –200µA; DVCC = 3.3V l0.7 • DVCC V
Voltage Output High, OUTn (LTC2964, Note 4) ISOURCE = –1µA lVCC – 1 V
IOH RST, WDO Output Voltage High Leakage V = 5.5V, VCC = 5.5V or
VCC = GND
l100 nA
IOPU RST, WDO and OUTn Internal Pull-Up Current V = GND l–4 –6 -10 µA
VIL RDIS, MR and WDI Input Level Low VCC = 2.25 to 5.5V l0.4 V
VIH RDIS, MR and WDI Input Level High VCC = 2.25 to 5.5V l1.6 V
IIL RDIS, MR and WDI Internal Pull-up Current V = GND l–16 –10 –4 µA
tMP MR Input Pulse Width l150 ns
tMD MR Input Propagation Delay MR Falling to RST Falling l0.1 1 µs
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, DVCC = 0V, MR = RDIS = VCC, unless otherwise specified.
(Note 2)
LTC2962/LTC2963/LTC2964
5
Rev 0
For more information www.analog.com
Vn Monitor Timing
RST
Vn
VRTX
tUV tRST
296234 TD01
TIMING DIAGRAMS
Reset and Watchdog Timing (LTC2963)
Vn
296234 TD02
RST
WDI
tRST tRST tRST
tRST
tRST tWD(INIT)
WDO
tWD(INIT) tWD(INIT) tWDU
tRST
tRST
POWER-ON RESET FOLLOWED BY
RESET CAUSED BY UNDERVOLTAGE
EVENT.
WATCHDOG OUTPUT SET HIGH,
WATCHDOG INPUT = DON’T CARE.
WATCHDOG INPUT NOT TOGGLED, INITIAL
WATCHDOG TIMER EXPIRES, WATCHDOG OUTPUT
PULLS LOW. RESET OUTPUT PULLS LOW FOR ONE
RESET TIMEOUT PERIOD.
WATCHDOG INPUT REMAINS UNTOGGLED,
WATCHDOG OUTPUT REMAINS LOW, RESET
OUTPUT PULLS LOW AGAIN AFTER ONE INITIAL
WATCHDOG TIMEOUT PERIOD. WATCHDOG
OUTPUT CLEARED BY UNDERVOLTAGE EVENT.
WATCHDOG INPUT TOGGLED, INITIAL
WATCHDOG TIMER CLEARED.
WATCHDOG INPUT NOT TOGGLED,
WATCHDOG TIMER EXPIRES,
WATCHDOG OUTPUT PULLS LOW.
RESET OUTPUT PULLS LOW.
WATCHDOG OUTPUT NOT CLEARED
BY WATCHDOG INPUT DURING RESET
TIMEOUT. AFTER RESET COMPLETED,
WATCHDOG INPUT CLEARS
WATCHDOG OUTPUT.
WATCHDOG INPUT NOT
TOGGLED, INITIAL WATCHDOG
TIMER EXPIRES, WATCHDOG
OUTPUT PULLS LOW. RESET
OUTPUT PULLS LOW.
WATCHDOG OUTPUT LOW
TIME SHORTENED BY
UNDERVOLTAGE EVENT
DURING RESET TIMEOUT.
LTC2962/LTC2963/LTC2964
6
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Normalized Threshold Error vs
Temperature
Vn Input Current vs Voltage:
±ADJ Mode
Vn Input Current vs Voltage:
All Modes Except ±ADJ
IVCC vs VCC (LTC2962) IVCC vs VCC (LTC2963) IVCC vs VCC (LTC2964)
VREF vs VCC VREF vs Temperature VREF vs IREF
ONE CHANNEL, 16 MODES, VCC = 3.3V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–0.2
–0.15
–0.1
–0.05
0
0.05
0.1
0.15
0.2
THRESHOLD ERROR (%)
296234 G01
V
CC
= 3.3V
T
A
= –40°C
T
A
= 25°C
T
A
= 125°C
V
n
(mV)
450
475
500
525
550
–5
–4
–3
–2
–1
0
1
2
3
4
5
IV
n
(nA)
296234 G02
V
CC
= 3.3V
T
A
= –40°C
T
A
= 125°C
V
n
(V)
0
1
2
3
4
5
0
1
2
3
4
5
IV
n
(µA)
296234 G03
T
A
= –40°C
T
A
= 25°C
T
A
= 125°C
V
CC
(V)
2
3
4
5
6
1.1930
1.1935
1.1940
1.1945
V
REF
(V)
296234 G07
V
CC
= 2.25V
V
CC
= 3.3V
V
CC
= 5.5V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
1.1930
1.1935
1.1940
1.1945
V
REF
(V)
296234 G08
V
CC
= 2.25V
V
CC
= 3.3V
V
CC
= 5.5V
I
REF
(mA)
–1
–0.5
0
0.5
1
1.1935
1.1936
1.1937
1.1938
1.1939
1.1940
V
REF
(V)
296234 G09
T
A
= –40°C
T
A
= 25°C
T
A
= 125°C
V
CC
(V)
2
2.5
3
3.5
4
4.5
5
5.5
6
100
105
110
115
120
125
130
135
140
I
VCC
(µA)
296234 G04
T
A
= –40°C
T
A
= 25°C
T
A
= 125°C
V
CC
(V)
2
2.5
3
3.5
4
4.5
5
5.5
6
120
125
130
135
140
145
150
155
160
296234 G05
I
VCC
(µA)
T
A
= –40°C
T
A
= 25°C
T
A
= 125°C
V
CC
(V)
2
2.5
3
3.5
4
4.5
5
5.5
6
100
105
110
115
120
125
130
135
140
296234 G06
I
VCC
(µA)
LTC2962/LTC2963/LTC2964
7
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Reset Timeout Period vs
Capacitance
Reset Timeout Period vs
Temperature
Reset Timeout Period vs
Temperature
Watchdog Timeout Period vs
Capacitance
Watchdog Timeout Period vs
Temperature
Watchdog Timeout Period vs
Temperature
Transient Duration vs Comparator
Overdrive
RST, WDO, OUTn VOL vs
Pull-Down Current
RT CAPACITANCE, C
RT
(nF)
0.001
0.01
0.1
1
10
100
1000
0.0001
0.001
0.01
0.1
1
10
RESET TIMEOUT PERIOD, t
RST
(s)
296234 G10
C
RT
= 1.5nF
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
17.6
17.7
17.8
17.9
18.0
18.1
18.2
18.3
18.4
RESET TIMEOUT PERIOD, t
RST
(ms)
296234 G11
V
RT
= V
CC
, INTERNAL TIMER
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
199.6
199.7
199.8
199.9
200.0
200.1
200.2
200.3
200.4
RESET TIMEOUT PERIOD, t
RST
(ms)
296234 G12
WT CAPACITANCE, C
WT
(nF)
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
WATCHDOG TIMEOUT PERIOD, t
WD
(s)
296234 G13
V
WT
= V
CC
, INTERNAL TIMER
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
1.62
1.63
1.64
1.65
1.66
1.67
1.68
1.69
1.70
WATCHDOG TIMEOUT PERIOD, t
WD
(s)
296234 G15
RESET OCCURS ABOVE CURVE
T
A
= 25°C
V
CC
= 2.25V
V
CC
= 5.5V
COMPARATOR OVERDRIVE (% OF V
RTX
)
0.1
1
10
100
0.01
0.1
1
TYPICAL TRANSIENT DURATION (ms)
296234 G16
V
CC
= 2.25V, NO EXTERNAL PULL–UP
T
A
= –40°C
T
A
= 25°C
T
A
= 125°C
I
RST
, I
WDO
, I
OUT
n
(mA)
0
2
4
6
8
10
0
0.1
0.2
0.3
0.4
0.5
V
RST
, V
WDO
, V
OUT
n
(V)
296234 G17
C
WT
= 1.5nF
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
145
146
147
148
149
150
WATCHDOG TIMEOUT PERIOD, t
WD
(ms)
296234 G14
Output Logic Low, ISINK vs VCC
RST, WDO, OUTn
V
OL
= 0.2V
V
OL
= 0.4V
V
CC
(V)
0
1
2
3
4
5
6
0
10
20
30
40
50
I
SINK
(mA)
296234 G18
LTC2962/LTC2963/LTC2964
8
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
RST, WDO VOH vs Source Current
MR, RDIS, WDI Input vs
Temperature IWDS vs Temperature
V
CC
= DV
CC
= 3.3V
T
A
= –40°C
T
A
= 25°C
T
A
= 125°C
I
SOURCE
(mA)
0
–0.3
–0.6
–0.9
–1.2
–1.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
(V)
296234 G19
2.25V ≤ V
CC
≤ 5.5V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0.80
0.85
0.90
0.95
1.00
THRESHOLD (V)
296234 G20
WDS = V
CC
= 3.3V
WDS = GND
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
2.5
2.6
2.7
2.8
2.9
3.0
–3.0
–2.9
–2.8
–2.7
–2.6
–2.5
I
WDS
(µA)
I
WDS
(µA)
296234 G21
PIN FUNCTIONS
DVCC: Digital Logic Supply. DVCC is used for setting the
logic swing at the RST and WDO (LTC2963 only) outputs.
Tying DVCC to a voltage greater than 1.6V allows the RST
and WDO to act as active push-pull outputs. When DVCC
is applied above 1.6V, a 0.1µF (or greater) bypass capaci-
tor is recommended. Ground the DVCC pin to configure
the RST and WDO as open drain outputs. Do not leave
DVCC open.
Exposed Pad: Exposed pad internally connected to
ground. PCB connection is optional.
GND: Device Ground.
MR: Manual Reset Input. A logic low on this input pulls
RST low. When MR returns high, RST returns high after
the configured reset timeout assuming all four Vn inputs
are above their respective thresholds. The manual reset
input is pulled up to VCC by an internal 10µA current
source. Drive the input with a mechanical switch or logic
signal. Leave the input open or tied to VCC if unused.
OUT1 - OUT4 (LTC2964 only): Individual Comparator
Outputs. These four pins are real-time open drain logic
outputs of the monitor comparators. Each output is
released when the corresponding input is above its reset
threshold, and pulls low when its input is below the reset
threshold (except in –ADJ mode). A weak internal 6µA
pulls these pins up to VCC. Connect an external pull up
resistor to an external logic supply to ensure that the out-
put high of each pin is above VIH of the external detector
and/or for faster rise times. Leave open if unused.
PG1 - PG4: Threshold Select Inputs. Connect an external
1% resistive divider between REF and GND to select one
of sixteen possible voltage thresholds for each channel.
Do not add capacitance to PG1 through PG4 inputs. See
the Monitor Configuration section for more information.
Connect to REF if unused.
RDIS: Reset Disable Input. Pulling this input to GND pre-
vents the RST output from being pulled low. This function
allows supply margining without issuing a reset com-
mand to the processor. A weak internal 10µA pull-up to
VCC allows this pin to be left open for normal operation.
REF: Buffered Reference Voltage Output. A 1.195V nomi-
nal reference is used for the mode selection voltage and
for level shifting in negative adjustable applications. The
buffered reference can source and sink up to 1mA. The
reference can drive a bypass capacitor of up to 1000pF
without oscillation.
LTC2962/LTC2963/LTC2964
9
Rev 0
For more information www.analog.com
PIN FUNCTIONS
RST: Reset Output. An internal 6µA current pulls this open
drain output to VCC. Pulls low when any voltage monitor
input is below the reset threshold and held low for the
configured reset delay time after all voltage inputs are
above their threshold. Leave open if unused.
RT: Reset Timeout Capacitor Input. Attach an external
capacitor (CRT) to GND to set a reset timeout of 12ms/nF.
Tie RT to VCC to activate the internal 200ms reset timeout.
V1 - V4: Voltage Monitor Inputs. Select from 5V, 3.3V,
2.5V, 1.8V, 1.5V, 1.2V, 1V or ±ADJ monitor thresholds as
determined by the threshold selection inputs PG1 - PG4.
See Applications Information for details. Connect to VCC
and set to +ADJ mode if unused.
V
CC
: Power Supply Input. V
CC
powers the part. Bypass
this input to ground with a 0.1µF (or greater) capacitor.
All status outputs are weakly pulled up to VCC.
WDI (LTC2963 only): Watchdog Input. It controls the
operation of the watchdog timer. While RST is high, a
valid WDI transition during the watchdog timeout period
is required to inhibit WDO and RST from pulling low and
initiating a watchdog reset. In LTC2963, both rising and
falling edges are valid WDI inputs. A capacitor attached to
WT sets the watchdog timeout period. A valid WDI edge
clears the internal counter driven by a clock signal based
on CWT, preventing WDO from going low. Once the watch-
dog timer expires and WDO is latched low, WDI must
transition between low and high logic levels to clear WDO.
See the Watchdog Timer section for more information.
WDO (LTC2963 only): Watchdog Output. Open drain out-
put weakly pulled to VCC. The watchdog timer is enabled
when RST is high. The WDO output pulls low if the watch-
dog timer expires, and it remains low until the next valid
WDI transition during the watchdog timer period or if a
channel undervoltage condition occurs. A watchdog fail-
ure also triggers a reset event, and the RST output pulls
low. Leave open if unused. See the Watchdog Timer sec-
tion for more information.
WDS (LTC2963 only): Initial watchdog timeout select
input. A three-state input controls the duration of the ini-
tial watchdog timeout immediately following any reset
event. Extending the timeout for the first period gives
extra time for the system logic to initialize before generat-
ing watchdog input pulses. A logic low sets the timeout
to its nominal time period (equal to the watchdog upper
timeout). Leaving the WDS input open sets the timeout to
eight times the watchdog upper timeout, while a logic high
selects sixty-four times the watchdog upper timeout. See
the Initial Watchdog Timeout discussion for more details.
WT (LTC2963 only): Watchdog Timeout Capacitor Input.
Attach a capacitor CWT between WT and GND to set a
watchdog timeout period of 100ms/nF. Leaving WT open
generates a minimum timeout period of approximately
2ms, which may vary depending on parasitic capacitance
on the pin. Tie WT to GND in order to disable the watch-
dog function. Tie WT to VCC to activate the internal 1.6s
watchdog timer.
LTC2962/LTC2963/LTC2964
10
Rev 0
For more information www.analog.com
BLOCK DIAGRAM
CHANNEL 4
CHANNEL 3
CHANNEL 2
–
+
4
*
4
0.5V 0.18V
VCC VCC
GND
PG1
PG2
PG3
PG4
V1
V2
V3
V4
WT
WDI
REF ×1
BUFFER
BANDGAP
REFERENCE
ADJUSTABLE
RESET TIME-OUT
200ms RESET
TIME-OUT
LTC2964
OPTION
LTC2963
OPTION VCC
10µA
CHANNEL 1
A/D
+
–
CHANNEL 4
CHANNEL 3
CHANNEL 2
6µA
CHANNEL 1
VCC
+
–
VCC
0.1V
I
O
OUT1
2962 BD
*REVERSE POLARITY FOR –ADJ MODE
OUT2
OUT3
OUT4
RT
DVCC
6µA
VCC
RST
1.6s WATCHDOG
TIME-OUT
TIMING
CONTROL
WDS 3-STATE
INPUT
ADJUSTABLE
WATCHDOG
TIME-OUT
6µA
VCC
DVCC
WDO
MR
10µA
VCC
RDIS
10µA
VCC
+
–
VCC
–
+
O
I
–
+
LTC2962/LTC2963/LTC2964
11
Rev 0
For more information www.analog.com
OPERATION
The LTC2962 family monitors up to four power supplies
(or channels) with industry leading ±0.5% accuracy over
a wide temperature range. While primarily intended for
monitoring undervoltage (UV) events, the LTC2962 family
has a mode allowing for overvoltage (OV) monitoring. In
typical operation, if any of the monitored supplies fall below
a predetermined threshold, the reset output, RST, pulls
low immediately. When all four supplies rise above their
threshold (or below, in the case of –ADJ mode), the reset
output is released after a timeout period. The reset timeout
can be a fixed 200ms or it can be adjusted using an external
capacitor. The reset output is held low during power-up,
power-down and brownout conditions on any channel.
±ADJ modes and fourteen UV thresholds can be con-
figured for each channel individually. Each of the four
program (PG) inputs select one of sixteen voltage monitor
thresholds for each input respectively. During power-up,
a 4-bit ADC converts the voltage on each PG input. The
resultant digital value is decoded into one of the sixteen
threshold options (see Table 1). This technique allows
for 1% standard resistors to be used to configure the PG
inputs while maintaining tight ±0.5% accuracy for each
threshold. 65,536 different threshold combinations can
be selected with the LTC2962 family, including the ability
to monitor the same voltage on more than one channel.
The +ADJ and –ADJ modes compare the channel inputs
to 0.5V. With an external resistive divider, +ADJ can be
used to monitor any voltage greater than 0.5V. –ADJ can
be used as an overvoltage monitor for positive supplies
or an undervoltage monitor for negative supplies.
The reset disable function, RDIS, eases system voltage
margining by forcing RST high. During normal operation,
RST will go low when the monitored voltage (e.g. V1, V2,
etc.) falls below its threshold (or above, in the case of –
ADJ mode). By disabling the reset function with RDIS, a
microprocessor voltage limit can be tested through mar-
gining without issuing a system reset. In addition to being
able to ignore valid reset outputs, a manual reset can also
be commanded with the MR input. This input has an inter-
nal pull-up and debounce circuitry making it well suited
for a pushbutton input. When MR goes low, RST pulls low
immediately. When MR goes high, RST is released after
the configured reset timeout delay – assuming that all four
monitored voltages are above their configured threshold.
With DV
CC
grounded, RST is an open-drain output weakly
pulled up internally to VCC by 6µA through a Schottky
diode. However, if DVCC is externally connected to a volt-
age greater than 1.6V, then RST will be driven as an active
push-pull output to DVCC.
LTC2963 Watchdog Functionality
In addition to the common LTC2962 family functionality
discussed above, the LTC2963 offers a watchdog func-
tion. In the LTC2963, the WDI input must receive an edge
(rising or falling) at least as often as the configured watch-
dog upper timeout period. This time can be fixed to 1.6s
by connecting WT to VCC or it can be adjusted using an
external capacitor on WT. If WDI does not receive a signal
quickly enough, then WDO (watchdog status) and RST
outputs will both pull low. RST returns high after a single
reset timeout period. Like the RST output, the WDO output
has a weak internal pull-up to VCC, but can be used as an
active push-pull if DVCC is greater than 1.6V. The details
of WDO functionality can be found in the Watchdog Timer
section.
Following a reset event, the microprocessor under super-
vision may require more time than usual to send valid
watchdog edge transitions. The 3-state WDS input pro-
vides a way to choose three different initial watchdog
timeout periods immediately following a reset.
LTC2964 Individual Outputs
The LTC2964 provides individual comparator outputs for
each voltage input. These outputs could serve as a status
indicator, e.g. power good, or be part of a power supply
sequencer circuit. OUT1 through OUT4 provide the out-
puts of each of the four channel comparators without the
adjustable reset timeout delay.
LTC2962/LTC2963/LTC2964
12
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Threshold Accuracy
The LTC2962 family features outstanding accuracy. To
better understand the importance and implication of the
monitor accuracy, we provide the following example.
Consider a system device whose operation requires 1V
± 4.5% tolerance. In other words, to guarantee proper
operation, the manufacturer states that the voltage pre-
sented to the device remain between 0.955V and 1.045V.
In an ideal world, the power supply providing voltage to
this device could vary over that entire range, and an ideal
undervoltage supervisor for the supply would generate a
reset at exactly 0.955V. However, no supervisor is per-
fect. The actual reset threshold of a supervisor varies
over a specified range; the LTC2962 family varies ±0.5%
around its nominal threshold voltage over temperature
(see Figure 1).
Figure 1. Threshold Diagram
Furthermore, the power supply must be guaranteed to
provide a voltage greater than 0.965V to avoid a false or
nuisance reset.
An extremely accurate supervisor, like the LTC2962 family,
has reduced monitor threshold spread, which increases
system voltage margin and reduces the probability of
system malfunction. By providing increased system mar-
gin the demands of the power supply are relaxed. For
example, with a ±1% supervisor, the nominal supervi-
sor threshold would need to be increased from –4% to
–3.5%, and the lower limit of the power supply tolerance
would be at –2.5%, 0.975V as opposed to 0.965V. In
other words, the power supply would need to be more
precise by 1%. Because of the accuracy of the LTC2962
family, it may be possible to use a smaller capacitor or a
smaller inductor in the power supply. The system may be
more tolerant of transient excursions. The additional mar-
gin may even allow a lower nominal supply voltage, which
can dramatically reduce power consumption. Hence, the
best-in-class ±0.5% accuracy of the LTC2962 family pro-
vides many benefits.
Power-Up
Upon initial application of voltage, V
CC
will power the drive
circuits for the RST output. This ensures that the RST out-
put will be low as soon as VCC reaches 1V. The RST out-
put remains low until the part is configured. See Monitor
Configuration for details about configuration. After config-
uration, if any one of the supply monitor inputs falls below
(or rises above, in –ADJ mode) its configured threshold,
RST will continue to remain low. Once all monitor inputs
rise above their thresholds, an internal timer is started
and RST is released after the configured delay time, tRST.
Monitor Configuration
Configure the monitor threshold for each channel input
by placing the recommended resistive divider from REF
to GND and connect the tap point to the appropriate PG
input, as shown in Figure 2. Table 1 specifies optimum
VPG/VREF ratios when configuring with a resistive divider
or a ratiometric DAC.
As one may want to share the resistive divider for all four
PG inputs, the following procedure is recommended.
REGION OF POTENTIAL MALFUNCTION
MINIMAL
RELIABLE
SYSTEM
VOLTAGE
SYSTEM
VOLTAGE
MARGIN
NOMINAL
SUPPLY
VOLTAGE
–3.5%
–4.0%
–4.5%
0.965V
±0.5%
THRESHOLD
BAND
0.960V
0.955V
ALLOWED
SUPPLY TOLERANCE
IDEAL
SUPERVISOR
THRESHOLD
1.0V
296234 F01
The monitor reset threshold range and the power supply
tolerance range should not overlap. This prevents false or
nuisance resets when the power supply is actually within
its specified tolerance range.
The LTC2962 family has ±0.5% reset threshold accuracy,
so a system load requiring ±4.5% tolerance requires the
supervisor threshold to be set 4% below the nominal sup-
ply voltage. Using the 1V system described, the nominal
–4% monitor threshold would be 0.96V. The monitor
threshold is guaranteed to be between 0.955V and 0.965V
over temperature. The powered system must work reliably
down to the low end of the threshold range, 0.955V, or
risk malfunction before a reset signal is properly issued.
LTC2962/LTC2963/LTC2964
13
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
First, create a resistive divider between REF and GND
composed of fifteen ideal 10k resistors. For a specific
input threshold combination, locate the optimal tap point
for each PG input following the ratio provided in Table 1.
Second, merge all resistors between any two adjacent tap
points into one single resistor and choose the standard
value using Table 2. Note the actual resistors in Table 2
are standard 1% values. Despite the difference between
the actual and the calculated resistance value as well as
the 1% tolerance, the LTC2962 family is guaranteed to
select the proper configuration.
Table 1. Voltage Configuration Table
SUPPLY VOLTAGE OPTIMAL RATIO VPG/VREF
+ADJ 1
5.0V, –4% 14/15
5.0V, –6% 13/15
3.3V, –4% 12/15
3.3V, –6% 11/15
2.5V, –4% 10/15
2.5V, –6% 9/15
1.8V, –4% 8/15
1.8V, –6% 7/15
1.5V, –4% 6/15
1.5V, –6% 5/15
1.2V, –4% 4/15
1.2V, –6% 3/15
1.0V, –4% 2/15
1.0V, –6% 1/15
–ADJ 0
Figure 3 shows an example of choosing PG resistors
using the above procedure. In the example, the V1 moni-
tor threshold is 5V –4% (4.8V), V2 is 3.3V –6% (3.102V),
V3 is 1.2V –4% (1.152V) and V4 is set to –ADJ mode,
respectively.
When a DAC is used to drive the PG inputs, the LTC2962
family is guaranteed to operate properly for bias voltage
within ±1.5% of VREF relative to the optimal value.
During power-up, once VCC reaches VCCMINC (2.2V max),
the LTC2962 family enters a configuration period of
approximately 500µs during which the voltage on each
of the four PG inputs are sampled and the monitor is
configured to the desired threshold. Immediately after
configuration, the comparators are enabled and supply
monitoring will begin. Note once the part is configured,
it cannot be reconfigured without powering down. Do not
add capacitance to the PG inputs. It is always benefi-
cial to Kelvin connect the resistive divider ground to the
LTC2962 family GND.
Table 2. Recommended 1% Resistors for Programming
CALCULATED RESISTOR VALUE
(kΩ)
ACTUAL RESISTOR VALUE
(kΩ)
10 10
20 20
30 30.1
40 40.2
50 49.9
60 60.4
70 69.8
80 80.6
90 90.9
100 100
110 110
120 121
130 130
140 140
Figure 2. Monitor Configuration
Figure 3. Programming (PG) Pin Bias Example
LTC2962
FAMILY
REF
R2
1%
296234 F02
PGn
GND R1
1%
RX4
10k
1%
REF
296234 F03
RX3
30.1k
1%
RX2
69.8k
1%
RX1
40.2k
1%
PG1
PG2
PG3
PG4
STEP 1: IDEAL LADDER
STEP 2: CHOOSE ACTUAL
RESISTORS
R14
10k
REF
R13
10k
R3
10k
R12
10k
PG1
5V
–4%
PG4
–ADJ
PG3
1.2V
–4%
PG2
3.3V
–4%
R8
10k
R9
10k
R10
10k
R11
10k
R7
10k
R6
10k
R5
10k
R4
10k
R1
10k
R2
10k
R3
10k
LTC2962/LTC2963/LTC2964
14
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure 4. Setting the Positive Adjustable (+ADJ) Threshold
Figure 5. Setting the Negative Adjustable (–ADJ) Threshold
Supply Monitoring – Fixed Thresholds
With the exception of the +ADJ and –ADJ modes, the
remaining fourteen configuration settings for each chan-
nel set a fixed monitor threshold for that channel. In these
settings, the input impedance of each of the four channel
voltage inputs (V1 ~ V4) is a fixed 1.2MΩ to ground. As
shown in the block diagram, the 4-bit programming ADC
selects an attenuation factor between the channel voltage
input and the channel comparator input corresponding to
the configured fixed monitor threshold. These settings
require the fewest external components and provide the
ability to monitor any of the preselected thresholds with
±0.5% accuracy using, at most, five external 1% PG
resistors.
Supply Monitoring – Adjustable Thresholds
In the two Adjustable modes (+ADJ and –ADJ), the chan-
nel voltage inputs become high impedance. Normally
these modes require the use of an additional external
resistive divider, but provide the ability to monitor any
supply voltage threshold.
In positive adjustable (+ADJ) mode, the comparator refer-
ence input (inverting) is set to 0.5V as shown in Figure 4.
An external resistive divider connected between the posi-
tive voltage being sensed and ground is connected to the
channel voltage input (V1 ~ V4). Calculate the channel
threshold voltage from:
VTH = 0.5V • 1+
R4
R3
⎛
⎝
⎜⎞
⎠
⎟
In the negative adjustable (–ADJ) mode, the comparator
polarity is reversed as shown in Figure 5. The internal 0.5V
reference is connected to the non-inverting comparator
input. An external resistive divider connected between
the negative voltage being sensed and the REF output is
connected to the channel voltage input (V1 ~ V4). VREF
provides the necessary level shift required to operate the
comparator. Calculate the negative threshold voltage from:
VTH = 0.5V • 1+
R3
R4
⎛
⎝
⎜⎞
⎠
⎟– V
REF •
R3
R4
where VREF = 1.195V Nominal
LTC2962
FAMILY
R4
296234 F04
Vn
R3
0.5V
V
SUPPLY
+
–
+
–
LTC2962
FAMILY
R4
296234 F05
Vn
REF
R3
0.5V
V
SUPPLY +
–
+
–
In a negative adjustable application, the minimum value
for R4 is limited by the sourcing capability of REF (1mA).
With no other load on REF, R4 (minimum) is:
R4(min)=
1.195V – 0.5V
1mA
=695
Ω
Tables 3 and 4 offer suggested 0.1% resistor values for
various adjustable applications.
Table 3. Suggested 0.1% Resistor Values for +ADJ Inputs
(Figure 4)
VSUPPLY (V) VTH (V) R4 (kΩ) R3 (kΩ)
12 11.25 2150 100
10 9.4 1780 100
8 7.5 1400 100
7.5 7 1300 100
6 5.6 1020 100
LTC2962/LTC2963/LTC2964
15
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Table 4. Suggested 0.1% Resistor Values for –ADJ Inputs
(Figure 5)
VSUPPLY (V) VTH (V) R3 (kΩ) R4 (kΩ)
–2 –1.866 412 121
–5 –4.721 909 121
–5.2 –4.847 931 121
–10 –9.494 1740 121
–12 –11.28 2050 121
Supply Monitoring – Overvoltage Thresholds
Because the comparator polarity is reversed for the –ADJ
mode, this mode can also be used for overvoltage moni-
toring. Implementing undervoltage and overvoltage (UV/
OV) monitoring of a single supply is as simple as dedicat-
ing two channels in ±ADJ mode as shown in Figure 6. The
threshold voltages are:
VOVTH = 0.5 • 1+ R5+R4
R3
⎛
⎝
⎜⎞
⎠
⎟
V
UVTH = 0.5 • 1+
R5
R4+R3
⎛
⎝
⎜⎞
⎠
⎟
configuration (V
CCMINC
, guaranteed to be below 2.2V),
then the device may reconfigure when VCC rises above
VCCMINC.
Selecting the Reset Timing Capacitor
The reset timeout period is adjustable in order to accom-
modate a variety of applications. The reset timeout period,
t
RST
, is adjusted by connecting a capacitor, C
RT
, between RT
and ground. The value of this capacitor is determined by:
CRT = tRST • 83 [pF/ms]
A graph of reset timeout period as a function of the
RT capacitor can be found in the Typical Performance
Characteristics section.
Leaving RT open generates a minimum reset timeout
period of approximately 250µs. Maximum reset time-
out period is limited by the largest available low leakage
capacitor. The accuracy of the timeout period is affected
by capacitor tolerance, temperature coefficienct and leak-
age (the nominal RT charging current is 2µA). A low leak-
age ceramic capacitor is recommended.
Connect RT to VCC generates a fixed reset timeout of
approximately 200ms.
Glitch Immunity
In any supervisor application, noise on the monitored
DC voltage could cause spurious undesirable resets. Two
techniques are used to combat the spurious resets with-
out sacrificing threshold accuracy. First, the reset time-
out period helps prevent high-frequency supply variation
whose frequency is above 1/tRST from appearing at the
output RST.
When the voltage input goes below the threshold, the RST
output goes low. When it recovers beyond the thresh-
old, the reset timer starts (assuming it is not disabled by
RDIS), and RST does not go high until the timeout com-
pletes. If the monitored supply becomes invalid during
the timeout period, the timer resets. The timer will restart
when the supply becomes valid again.
While the reset timeout is useful at preventing RST tog-
gling in most cases, it is not effective at preventing nui-
sance resets due to short glitches (due to load transients
Figure 6. 3-Resistor Positive UV/OV Monitoring Configuration
(V1 in +ADJ, V2 in –ADJ)
LTC2962
FAMILY
R5
296234 F06
V1
R4 0.5V
V
SUPPLY
+
–
+
–
V2
R3
0.5V
+
–
+
–
Power-Down
On power-down, once any of the monitor inputs drop
below its threshold, RST is held at a logic low. A logic
low of 0.4V is guaranteed until VCC drops below 1V.
If VCC drops below the minimum voltage required for
LTC2962/LTC2963/LTC2964
16
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
or other effects) on a valid supply. Hysteresis is tradition-
ally used to solve this problem, but it causes additional
error in the threshold voltage. In order to reduce sensitiv-
ity to these short glitches without introducing hysteresis,
the LTC2962 family low-pass filters the output of the first
stage in the comparator. This filter integrates the output
of the comparator before pulling the reset output low,
dramatically reducing the effect of instantaneous glitches
or noise. Only a transient with sufficient magnitude and
duration at the input of the comparator will trigger the out-
put logic. The Typical Performance Characteristics section
shows a graph of the Transient Duration vs Comparator
Overdrive. Unlike some other supply monitors, LTC2962
family transient duration is not sensitive to supply voltage
V
CC
and thus leads to better predictability. The combi-
nation of the reset timeout and anti-glitch circuitry pre-
vents spurious changes in output state without sacrificing
threshold accuracy.
Watchdog Timer (LTC2963)
Watchdog circuitry is used to ensure that the system
is functioning properly by continuously monitoring
microprocessor activity. The microprocessor is required
to change the logic state of the WDI input periodically
to clear the watchdog timer. The CWT timing capacitor
adjusts the watchdog timeout period depending on the
application and microprocessor requirements. If the soft-
ware malfunctions and the state of WDI does not change
properly, the watchdog times out and the WDO output is
latched low. Simultaneously, RST is pulled low to reset
the microprocessor. While RST is low, the WDI input does
not affect RST or WDO. The system therefore resets for
at least tRST.
After the configured reset timeout period, tRST, RST goes
back high and the microprocessor can poll the state of
the WDO output to determine if the reset was caused by
a voltage-based comparator event or by a watchdog fault.
Following the rising edge of RST, if WDO output is high,
then the reset was caused by a voltage-based compara-
tor event. If WDO output is low, then the system reset
was caused by a watchdog fault. The rising edge of RST
resets the watchdog timer, and the microprocessor can
then issue a valid WDI input to clear the WDO latch. Please
see the Initial Watchdog Timeout section for details on a
valid WDI input following a reset. If the microprocessor
fails to issue a valid WDI, the watchdog will timeout and
behave as described above with the exception that the
WDO output will already be low. Note manual reset has the
same effect on watchdog function as comparator event.
The RST and WDO outputs should not be tied together to
generate the master reset signal since a watchdog timeout
forces RST low together with WDO and the master reset
signal will remain low indefinitely.
LTC2963 provides traditional watchdog functionality
with a constraint on the lower bound of the WDI input
frequency.
Selecting the Watchdog Timing Capacitor
The watchdog timeout period is adjustable and can be
optimized for software execution. The watchdog upper
timeout, tWDU, can be adjusted by connecting a capacitor,
CWT, between WT and ground. Given a specified watchdog
timeout period, the capacitor is determined by:
CWT = tWDU • 10 [pF/ms]
The accuracy of the timeout period will be affected by
capacitor leakage (the nominal charging current is 2μA)
and capacitor tolerance. A low leakage ceramic capacitor is
recommended. Leaving WT open will generate a minimum
watchdog timeout of approximately 2ms. Connecting WT
to VCC generates a fixed watchdog timeout of 1.6s.
Initial Watchdog Timeout
Following a reset event, the microprocessor under super-
vision may require more time than usual to send valid
watchdog edge transitions. In order for the microproces-
sor to have sufficient setup time to issue valid WDI inputs
and avoid an unnecessary reset, the LTC2963 offers flex-
ible adjustability for the initial watchdog timeout using the
WDS input. The 3-state WDS input provides three differ-
ent initial watchdog timeout periods immediately follow-
ing a reset. Connecting the WDS input to ground sets the
initial watchdog timeout, tWD(INIT) equal to the watchdog
LTC2962/LTC2963/LTC2964
17
Rev 0
For more information www.analog.com
to reduce mechanical stress. A thicker and smaller board
is stiffer and less prone to bend. Finally, use stress relief,
such as flexible standoffs, when mounting the board.
To prevent interference, try to place the LTC2962 close
to the device it monitors. For best accuracy, connect the
channel voltage inputs (V1 ~ V4) directly to the supply
pin of the device it monitors. This avoids possible voltage
drop between the output of the power supply and the input
supply of the device under supervision.
Careful attention to grounding is also important, especially
when LTC2962 is sinking significant current through logic
outputs or the REF output. The return load current can
produce ground potential differences between LTC2962
and the device under supervision. This voltage difference
may manifest as threshold hysteresis. Use a star ground
connection and minimize the ground metal resistance,
especially for applications where multiple devices are
monitored. Figure 7 gives an example of the optimal lay-
out practice for good voltage monitoring.
APPLICATIONS INFORMATION
upper timeout, tWDU. Leaving WDS open sets the initial
watchdog timeout to eight times the upper timeout, while
connecting WDS to VCC sets it to sixty-four times the
upper timeout.
Table 6. Initial Watchdog Timeout Options with WDS
WDS
INITIAL WATCHDOG TIMEOUT
tWD(INIT)
GND tWDU
Open 8 • tWDU
VCC 64 • tWDU
The rising edge of the RST output resets the watchdog
timer and starts the initial watchdog timeout, tWD(INIT),
and is the upper limit for a valid WDI input immediately
following a rising edge of the RST output. If there is no
valid WDI edge before tWD(INIT) expires, a typical watch-
dog fault occurs as described above in the Watchdog
Timer section. When the initial watchdog timer is properly
cleared by a valid WDI edge, the LTC2963 starts using the
normal watchdog timer limits (tWDU for LTC2963).
PCB Layout
The LTC2962 family is a precision device whose compara-
tor thresholds are factory trimmed to ±0.5% accuracy as
shown in the Typical Performance Characteristics sec-
tion. The mechanical stress caused by soldering parts to a
printed circuit board may cause the threshold to shift and
the temperature coefficient to change. While every situa-
tion is different, expected errors due to these effects are
likely to be on the order of 0.05%. To reduce the effects
of stress-related shifts, mount the device near the short
edge of a printed circuit board or in a corner. In addition,
slots can be cut into the board on two sides of the device
Figure 7. Kelvin Connection for Good Voltage Monitoring
LTC2962
FAMILY
296234 F07
Vn
VDD
0.5V
+
–
+
–
GND
GND
DEVICE
(µP, FPGA, ETC.)
KELVIN CONNECT
MINIMIZE RESISTANCE OF METAL
GND
STAR
POWER
SUPPLY
VOUT
LTC2962/LTC2963/LTC2964
18
Rev 0
For more information www.analog.com
PACKAGE DESCRIPTION
3.00 ±0.10
(4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.45 ±0.05
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.45 ± 0.10
(4-SIDES)
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
1
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
15 16
2
0.50 BSC
0.200 REF
2.10 ±0.05
3.50 ±0.05
0.70 ±0.05
0.00 – 0.05
(UD16) QFN 0904
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691 Rev Ø)
LTC2962/LTC2963/LTC2964
19
Rev 0
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PACKAGE DESCRIPTION
3.00 ±0.10 1.50 REF
4.00 ±0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
19 20
1
2
BOTTOM VIEW—EXPOSED PAD
2.50 REF
0.75 ±0.05
R = 0.115
TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UDC20) QFN 1106 REV Ø
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
2.50 REF
3.10 ±0.05
4.50 ±0.05
1.50 REF
2.10 ±0.05
3.50
±0.05
PACKAGE OUTLINE
R = 0.05 TYP
1.65 ±0.10
2.65 ±0.10
1.65 ±0.05
2.65 ±0.05
0.50 BSC
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
LTC2962/LTC2963/LTC2964
20
Rev 0
D17154-0-8/18(0)
www.analog.com
ANALOG DEVICES, INC. 2018
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
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Supervisor with Power-Up Sequence Function
LTC2964
30.1k
1%
296234 TA02
PG1
REF
OUT1
OUT2
OUT3
OUT4
20k
1%
VCC
PG2
20k
1% PG3
MR
RDIS
20k
1% PG4
tRST 56ms RESET TIMEOUT
GND
2.5V
3.3V
1.8V
1.5V
SYSTEM
LOGIC
2.5V
3.3V
1.8V
1.5V
EN4 EN3 EN2
DC/DC
CONVERTER
60.4k
1%
47nF
V1 V2 V3 V4 DVCC
RT
RST
0.1µF 0.1µF