LTC2962/LTC2963/LTC2964 0.5% Accurate Quad Configurable Supervisor FEATURES DESCRIPTION Simultaneously Monitor Four Power Supplies nn 0.5% Threshold Accuracy Over Temperature nn Selectable -4% and -6% Thresholds per Supply: 5V, 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 1V and ADJ nn Adjustable Reset (RST) Timeout nn Overvoltage and Negative Voltage Monitoring nn Push-Pull or Open-Drain RST Output nn Margin Pin RDIS for Reset Disable nn H-Grade Temperature Range nn LTC2963 Non-Windowed (-1) Watchdog Adjustable Watchdog Timer Watchdog Status Output WDO Selectable Initial Watchdog Timeout nn LTC2964 Individual Comparator Open-drain Outputs nn 16-Lead 3mm x 3mm QFN (LTC2962) nn 20-Lead 3mm x 4mm QFN (LTC2963, LTC2964) The LTC(R)2962 series of configurable power supply monitors can supervise systems with up to four supply voltages. One of 16 preset or adjustable voltage monitor thresholds per channel can be selected using external 1% resistors connected to the programming (PG) inputs. The preset voltage thresholds are accurate to 0.5% over temperature. Positive (+ADJ) and negative (-ADJ) adjustable inputs with a 0.5V threshold allow undervoltage, negative voltage and overvoltage monitoring. nn The watchdog (LTC2963 only) and reset timeout periods are adjustable using external capacitors. Accurate voltage thresholds and comparator glitch immunity ensure reliable reset operation without false triggering. The RST output is guaranteed to be in the correct state for VCC input voltage down to 1V. The flexibility of the LTC2962 family provides the ability to monitor a wide variety of power supply combinations, including multiple supplies of the same voltage, with 0.5% accuracy. APPLICATIONS All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents including 6967591, 7239251, 7119714. High Reliability Systems nn Network, Telecom and Server Systems nn Automotive Control Systems nn TYPICAL APPLICATION 0.1F 0.1F VCC V1 R5 30.1k R4 20k 0 TO 5 1% CONFIGURATION RESISTORS Typical Distribution of Monitor Threshold Error 3.3V 2.5V 1.8V 1.5V R3 20k R2 20k R1 60.4k V2 V3 V4 DVCC SYSTEM LOGIC REF RST PG1 RDIS LTC2962 PG2 56ms RESET TIMEOUT PG3 MR PG4 GND MANUAL RESET RT CRT 47nF 50 PERCENTAGE OF THRESHOLDS (%) 3.3V 2.5V 1.8V 1.5V DC/DC 45 494 PARTS ( 31616 TRESHOLDS ) 40 35 30 25 20 15 10 5 0 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 THRESHOLD ERROR (%) 296234 TA01b 296234 TA01a Rev 0 Document Feedback For more information www.analog.com 1 LTC2962/LTC2963/LTC2964 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) V1 - V4, MR, RDIS, WDI, DVCC, VCC............. -0.3V to 6V PG1 - PG4, REF.......................................... -0.3V to 1.5V OUT1 - OUT4................................................. -0.3V to 6V RT, WT, WDS.................................-0.3V to (VCC + 0.3V) RST, WDO (DVCC 1.6V)............ -0.3V to (DVCC + 0.3V) RST, WDO (DVCC = GND).............................. -0.3V to 6V Reference Load Current (IREF)................................ 1mA RST, WDO, OUT1 - OUT4 Currents........................ 10mA Operating Temperature Range C-Grade.................................................... 0C to 70C I-Grade.................................................-40C to 85C H-Grade.............................................. -40C to 125C Storage Temperature Range.......................-65 to 150C PIN CONFIGURATION PG4 UD PACKAGE 16-LEAD (3mm x 3mm) PLASTIC QFN TJMAX = 125C, JA = 68C/W, JC = 7.5C/W EXPOSED PAD (PIN 17) PCB GND CONNECTION OPTIONAL V4 V3 V1 V4 V3 V2 12 PG4 GND 6 11 RT GND 6 7 8 12 PG4 11 RT 7 9 10 UDC PACKAGE 20-LEAD (3mm x 4mm) PLASTIC QFN TJMAX = 125C, JA = 52C/W, JC = 6.8C/W EXPOSED PAD (PIN 21) PCB GND CONNECTION OPTIONAL 13 PG3 8 9 10 OUT4 RT RST 5 RST 5 VCC 4 14 PG2 21 OUT3 RST 13 PG3 VCC 4 21 OUT2 8 14 PG2 DVCC 3 OUT1 7 GND 9 PG3 6 15 PG1 DVCC 3 WT 10 PG2 5 15 PG1 MR 2 WDS 11 PG1 VCC 4 16 REF MR 2 WDI DVCC 3 16 REF WD0 12 REF 17 20 19 18 17 RDIS 1 RDIS 1 16 15 14 13 MR 2 TOP VIEW 20 19 18 17 V4 V3 V2 V1 TOP VIEW RDIS 1 LTC2964 TOP VIEW V2 LTC2963 V1 LTC2962 UDC PACKAGE 20-LEAD (3mm x 4mm) PLASTIC QFN TJMAX = 125C, JA = 52C/W, JC = 6.8C/W EXPOSED PAD (PIN 21) PCB GND CONNECTION OPTIONAL ORDER INFORMATION TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2962CUD#PBF LTC2962CUD#TRPBF LGZZ 16-Lead (3mm x 3mm) Plastic QFN 0C to 70C LTC2962IUD#PBF LTC2962IUD#TRPBF LGZZ 16-Lead (3mm x 3mm) Plastic QFN -40C to 85C LTC2962HUD#PBF LTC2962HUD#TRPBF LGZZ 16-Lead (3mm x 3mm) Plastic QFN -40C to 125C LTC2963CUDC-1#PBF LTC2963CUDC-1#TRPBF LHBC 20-Lead (3mm x 4mm) Plastic QFN 0C to 70C LTC2963IUDC-1#PBF LTC2963IUDC-1#TRPBF LHBC 20-Lead (3mm x 4mm) Plastic QFN -40C to 85C LTC2963HUDC-1#PBF LTC2963HUDC-1#TRPBF LHBC 20-Lead (3mm x 4mm) Plastic QFN -40C to 125C LTC2964CUDC#PBF LTC2964CUDC#TRPBF LHBB 20-Lead (3mm x 4mm) Plastic QFN 0C to 70C LTC2964IUDC#PBF LTC2964IUDC#TRPBF LHBB 20-Lead (3mm x 4mm) Plastic QFN -40C to 85C LTC2964HUDC#PBF LTC2964HUDC#TRPBF LHBB 20-Lead (3mm x 4mm) Plastic QFN -40C to 125C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev 0 2 For more information www.analog.com LTC2962/LTC2963/LTC2964 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V, DVCC = 0V, MR = RDIS = VCC, unless otherwise specified. (Note 2) SYMBOL PARAMETER CONDITIONS VCC Operating Range MIN l TYP 2.25 MAX UNITS 5.5 V Guaranteed RST Output Low VCC Rising l 1 V VCCMINC Minimum Required for Configuration VCC Rising l 2.2 V IVCC VCC Input Supply Current l 80 140 210 A DVCC Operating Range l 1.6 5.5 V 25 500 nA DVCC Input Supply Current IRST = 0, IWDO = 0 l VRT50 5V, -4% Reset Threshold 5V, -6% Reset Threshold l l 4.775 4.675 4.8 4.7 4.825 4.725 V V VRT33 3.3V, -4% Reset Threshold 3.3V, -6% Reset Threshold l l 3.152 3.087 3.168 3.102 3.185 3.119 V V VRT25 2.5V, -4% Reset Threshold 2.5V, -6% Reset Threshold l l 2.388 2.338 2.4 2.35 2.413 2.363 V V VRT18 1.8V, -4% Reset Threshold 1.8V, -6% Reset Threshold l l 1.719 1.683 1.728 1.692 1.737 1.701 V V VRT15 1.5V, -4% Reset Threshold 1.5V, -6% Reset Threshold l l 1.433 1.403 1.44 1.41 1.448 1.418 V V VRT12 1.2V, -4% Reset Threshold 1.2V, -6% Reset Threshold l l 1.146 1.122 1.152 1.128 1.158 1.134 V V VRT10 1.0V, -4% Reset Threshold 1.0V, -6% Reset Threshold l l 0.955 0.935 0.96 0.94 0.965 0.945 V V VRTA ADJ Reset Threshold l 497.5 500 502.5 mV VREF Reference Voltage VCC = 2.25V to 5.5V, IREF = 1mA, l CREF 1000pF 1.183 1.195 1.207 V VPG PG1 to PG4 Configuration Voltage Range VCC > VCCMINC l VREF V IMON Monitor Input Current for V1 - V4 ADJ Modes (Vn = 0.5V) l 15 nA RMON Monitor Input Resistance for V1 - V4 All Modes Except ADJ 1.2 1.6 M tUV Comparator Propagation Delay to RST or OUTn Falling Edge Overdrive = 10% l 20 40 s RT and WT Pull-Up Current V = GND l -1.5 -2 -2.5 A RT and WT Pull-Down Current V = 1.3V l 1.5 2 2.5 A Reset Timeout Period CRT = 1500pF VRT = VCC l l 12 160 18 200 24 240 ms ms Internal Timer Select Level (WT and RT) l VCC - 0.1 VCC-Detect Current in Internal Timer Mode (WT and RT) V = VCC l 1 2 A 150 1.6 200 2 ms s tRST 0 0.8 V LTC2963 Watchdog tWDU Watchdog Upper Timeout Period CWT = 1500pF WT Tied to VCC l l tWD(INIT) Initial Watchdog Timeout Period WDS = Logic Low WDS = Open WDS = Logic High l l l VWDS WDS Input Level (VCC = 2.25 to 5.5V) Logic Low Open Logic High l l l 100 1.3 tWDU 8 * tWDU 64 * tWDU 0.7 VCC - 0.3 1.3 0.4 VCC - 0.7 V V V Rev 0 For more information www.analog.com 3 LTC2962/LTC2963/LTC2964 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V, DVCC = 0V, MR = RDIS = VCC, unless otherwise specified. (Note 2) IWDS WDS Input Current IWDS(HZ) Allowable WDS Leakage in Open State tWDI,MAX Rise/Fall Time of WDI Edge tWP WDI Input Pulse Width tWD WDI to WDO Propagation Delay VWDS = GND VWDS = VCC l l -4 -2.6 2.6 l VCC = 2.25V to 5.5V l 4 A A 1 A 2 s 2 s l 0.5 s 150 mV Logic I/O Voltage Output Low RST, WDO (Note 3) ISINK = 3mA, VCC = 2.25V to 5.5V l 40 RST Only ISINK = 100A, VCC = 1.1V l 10 60 mV Voltage Output Low OUTn (LTC2964, Note 4) ISINK = 5mA, VCC = 2.25V to 5.5V l 50 300 mV Voltage Output High RST, WDO (Note 3) ISOURCE = -200A; DVCC = 3.3V l 0.7 * DVCC V Voltage Output High, OUTn (LTC2964, Note 4) ISOURCE = -1A l VCC - 1 V IOH RST, WDO Output Voltage High Leakage V = 5.5V, VCC = 5.5V or VCC = GND l IOPU RST, WDO and OUTn Internal Pull-Up Current V = GND l -4 VIL RDIS, MR and WDI Input Level Low VCC = 2.25 to 5.5V l 0.4 VIH RDIS, MR and WDI Input Level High VCC = 2.25 to 5.5V l IIL RDIS, MR and WDI Internal Pull-up Current V = GND l -16 tMP MR Input Pulse Width l 150 tMD MR Input Propagation Delay VOL VOH MR Falling to RST Falling Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. l 100 nA -10 A 1.6 V -10 -4 A 0.1 1 s -6 V ns Note 3: The RST and WDO pins are push-pull outputs that swing to DVCC when DVCC is greater than 1.6V. Note 4: The output pins, OUT1 - OUT4, have internal pull-ups to VCC of typically 6A. However, external pull-up resistors may be used when faster rise times are required or for VOH voltages greater than VCC. Rev 0 4 For more information www.analog.com LTC2962/LTC2963/LTC2964 TIMING DIAGRAMS Vn Monitor Timing Vn VRTX tRST tUV RST 296234 TD01 Reset and Watchdog Timing (LTC2963) Vn RST tRST tRST tRST tWD(INIT) tRST tWD(INIT) WDO tRST tRST tWD(INIT) tRST tWDU WDI POWER-ON RESET FOLLOWED BY RESET CAUSED BY UNDERVOLTAGE EVENT. WATCHDOG OUTPUT SET HIGH, WATCHDOG INPUT = DON'T CARE. WATCHDOG INPUT NOT TOGGLED, INITIAL WATCHDOG TIMER EXPIRES, WATCHDOG OUTPUT PULLS LOW. RESET OUTPUT PULLS LOW FOR ONE RESET TIMEOUT PERIOD. WATCHDOG INPUT REMAINS UNTOGGLED, WATCHDOG OUTPUT REMAINS LOW, RESET OUTPUT PULLS LOW AGAIN AFTER ONE INITIAL WATCHDOG TIMEOUT PERIOD. WATCHDOG OUTPUT CLEARED BY UNDERVOLTAGE EVENT. WATCHDOG INPUT NOT TOGGLED, INITIAL WATCHDOG TIMER EXPIRES, WATCHDOG OUTPUT PULLS LOW. RESET OUTPUT PULLS LOW. WATCHDOG OUTPUT LOW TIME SHORTENED BY UNDERVOLTAGE EVENT DURING RESET TIMEOUT. WATCHDOG INPUT TOGGLED, INITIAL WATCHDOG TIMER CLEARED. WATCHDOG INPUT NOT TOGGLED, WATCHDOG TIMER EXPIRES, WATCHDOG OUTPUT PULLS LOW. RESET OUTPUT PULLS LOW. WATCHDOG OUTPUT NOT CLEARED BY WATCHDOG INPUT DURING RESET TIMEOUT. AFTER RESET COMPLETED, WATCHDOG INPUT CLEARS WATCHDOG OUTPUT. 296234 TD02 Rev 0 For more information www.analog.com 5 LTC2962/LTC2963/LTC2964 TYPICAL PERFORMANCE CHARACTERISTICS Normalized Threshold Error vs Temperature 0.2 5 ONE CHANNEL, 16 MODES, VCC = 3.3V 0.15 5 VCC = 3.3V 3 0.1 4 2 0 -0.05 1 IVn (A) 0.05 0 -1 -3 -0.15 2 -25 0 25 50 75 TEMPERATURE (C) 100 -5 450 125 475 500 Vn (mV) 296234 G01 IVCC vs VCC (LTC2962) 160 TA = -40C TA = 25C TA = 125C 130 IVCC (A) 120 115 130 145 140 135 115 125 105 3.5 4 4.5 5 VCC (V) 1.1945 5.5 120 6 2 2.5 3 3.5 4 4.5 5 VCC (V) 296234 G04 VREF vs VCC 1.1945 5.5 100 6 2 2.5 3 3.5 296234 G05 VREF vs Temperature 1.1940 VCC = 2.25V VCC = 3.3V VCC = 5.5V TA = -40C TA = 25C TA = 125C 4 4.5 VCC (V) 5.5 6 296234 G06 VREF vs IREF 1.1939 VREF (V) VREF (V) 1.1935 1.1938 1.1937 1.1935 1.1936 1.1930 5 1.1940 VREF (V) 1.1940 5 296234 G03 120 105 3 4 125 110 2.5 3 TA = -40C TA = 25C TA = 125C 135 130 2 2 IVCC vs VCC (LTC2964) 140 110 100 1 Vn (V) TA = -40C TA = 25C TA = 125C 150 0 296234 G02 IVCC vs VCC (LTC2963) 155 125 0 550 IVCC (A) 135 525 TA = -40C TA = 125C 1 TA = -40C TA = 25C TA = 125C -4 -0.2 -50 IVCC (A) 3 -2 -0.1 140 Vn Input Current vs Voltage: All Modes Except ADJ VCC = 3.3V 4 IVn (nA) THRESHOLD ERROR (%) Vn Input Current vs Voltage: ADJ Mode 2 3 4 VCC (V) 5 6 296234 G07 1.1930 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 296234 G08 1.1935 VCC = 2.25V VCC = 3.3V VCC = 5.5V -1 -0.5 0 IREF (mA) 0.5 1 296234 G09 Rev 0 6 For more information www.analog.com LTC2962/LTC2963/LTC2964 TYPICAL PERFORMANCE CHARACTERISTICS Reset Timeout Period vs Capacitance Reset Timeout Period vs Temperature 18.4 1 0.1 0.01 0.001 0.0001 0.001 0.01 0.1 1 10 100 RT CAPACITANCE, CRT (nF) 1000 200.4 CRT = 1.5nF 18.3 RESET TIMEOUT PERIOD, tRST (ms) RESET TIMEOUT PERIOD, tRST (ms) 18.2 18.1 18.0 17.9 17.8 17.7 17.6 -50 -25 0 25 50 75 TEMPERATURE (C) 100 Watchdog Timeout Period vs Capacitance 200.1 200.0 199.9 199.8 199.7 199.6 -50 1.70 0.01 0.001 0.001 0.01 0.1 1 10 WT CAPACITANCE, CWT (nF) 100 CWT = 1.5nF WATCHDOG TIMEOUT PERIOD, tWD (s) WATCHDOG TIMEOUT PERIOD, tWD (ms) 0.1 149 148 147 146 145 -50 -25 0 25 50 75 TEMPERATURE (C) 296234 G13 100 125 1.68 1.67 1.66 1.65 1.64 1.63 1.62 -50 0.01 0.1 50 296234 G16 100 VRST, VWDO, VOUTn (V) 0.3 0.2 0 125 VOL = 0.2V VOL = 0.4V 40 TA = -40C TA = 25C TA = 125C 0.1 1 10 100 COMPARATOR OVERDRIVE (% OF VRTX) 0 25 50 75 TEMPERATURE (C) Output Logic Low, ISINK vs VCC RST, WDO, OUTn VCC = 2.25V, NO EXTERNAL PULL-UP 0.4 VCC = 2.25V VCC = 5.5V -25 296234 G15 0.5 TA = 25C 125 VWT = VCC, INTERNAL TIMER 1.69 RST, WDO, OUTn VOL vs Pull-Down Current 1 0.1 100 296234 G14 Transient Duration vs Comparator Overdrive RESET OCCURS ABOVE CURVE 0 25 50 75 TEMPERATURE (C) Watchdog Timeout Period vs Temperature 150 1 -25 296234 G12 Watchdog Timeout Period vs Temperature 10 WATCHDOG TIMEOUT PERIOD, tWD (s) 200.2 296234 G11 296234 G10 TYPICAL TRANSIENT DURATION (ms) 125 VRT = VCC, INTERNAL TIMER 200.3 ISINK (mA) RESET TIMEOUT PERIOD, tRST (s) 10 Reset Timeout Period vs Temperature 30 20 10 0 2 4 6 8 IRST, IWDO, IOUTn (mA) 10 296234 G17 0 0 1 2 3 VCC (V) 4 5 6 296234 G18 Rev 0 For more information www.analog.com 7 LTC2962/LTC2963/LTC2964 TYPICAL PERFORMANCE CHARACTERISTICS 1.00 2.25V VCC 5.5V TA = -40C TA = 25C TA = 125C 2.5 1.5 1.0 0.90 0.85 0.5 0 0 -0.3 -0.6 -0.9 ISOURCE (mA) -1.2 -1.5 296234 G19 0.80 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 296234 G20 -2.5 WDS = VCC = 3.3V WDS = GND -2.6 2.8 -2.7 2.7 -2.8 2.6 -2.9 2.5 -50 -25 0 25 50 75 TEMPERATURE (C) 100 IWDS (A) 2.0 IWDS vs Temperature 2.9 0.95 IWDS (A) 3.0 VOH (V) 3.0 VCC = DVCC = 3.3V THRESHOLD (V) 3.5 MR, RDIS, WDI Input vs Temperature RST, WDO VOH vs Source Current -3.0 125 296234 G21 PIN FUNCTIONS DVCC: Digital Logic Supply. DVCC is used for setting the logic swing at the RST and WDO (LTC2963 only) outputs. Tying DVCC to a voltage greater than 1.6V allows the RST and WDO to act as active push-pull outputs. When DVCC is applied above 1.6V, a 0.1F (or greater) bypass capacitor is recommended. Ground the DVCC pin to configure the RST and WDO as open drain outputs. Do not leave DVCC open. Exposed Pad: Exposed pad internally connected to ground. PCB connection is optional. GND: Device Ground. MR: Manual Reset Input. A logic low on this input pulls RST low. When MR returns high, RST returns high after the configured reset timeout assuming all four Vn inputs are above their respective thresholds. The manual reset input is pulled up to VCC by an internal 10A current source. Drive the input with a mechanical switch or logic signal. Leave the input open or tied to VCC if unused. OUT1 - OUT4 (LTC2964 only): Individual Comparator Outputs. These four pins are real-time open drain logic outputs of the monitor comparators. Each output is released when the corresponding input is above its reset threshold, and pulls low when its input is below the reset threshold (except in -ADJ mode). A weak internal 6A pulls these pins up to VCC. Connect an external pull up resistor to an external logic supply to ensure that the output high of each pin is above VIH of the external detector and/or for faster rise times. Leave open if unused. PG1 - PG4: Threshold Select Inputs. Connect an external 1% resistive divider between REF and GND to select one of sixteen possible voltage thresholds for each channel. Do not add capacitance to PG1 through PG4 inputs. See the Monitor Configuration section for more information. Connect to REF if unused. RDIS: Reset Disable Input. Pulling this input to GND prevents the RST output from being pulled low. This function allows supply margining without issuing a reset command to the processor. A weak internal 10A pull-up to VCC allows this pin to be left open for normal operation. REF: Buffered Reference Voltage Output. A 1.195V nominal reference is used for the mode selection voltage and for level shifting in negative adjustable applications. The buffered reference can source and sink up to 1mA. The reference can drive a bypass capacitor of up to 1000pF without oscillation. Rev 0 8 For more information www.analog.com LTC2962/LTC2963/LTC2964 PIN FUNCTIONS RST: Reset Output. An internal 6A current pulls this open drain output to VCC. Pulls low when any voltage monitor input is below the reset threshold and held low for the configured reset delay time after all voltage inputs are above their threshold. Leave open if unused. RT: Reset Timeout Capacitor Input. Attach an external capacitor (CRT) to GND to set a reset timeout of 12ms/nF. Tie RT to VCC to activate the internal 200ms reset timeout. V1 - V4: Voltage Monitor Inputs. Select from 5V, 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 1V or ADJ monitor thresholds as determined by the threshold selection inputs PG1 - PG4. See Applications Information for details. Connect to VCC and set to +ADJ mode if unused. VCC: Power Supply Input. VCC powers the part. Bypass this input to ground with a 0.1F (or greater) capacitor. All status outputs are weakly pulled up to VCC. WDI (LTC2963 only): Watchdog Input. It controls the operation of the watchdog timer. While RST is high, a valid WDI transition during the watchdog timeout period is required to inhibit WDO and RST from pulling low and initiating a watchdog reset. In LTC2963, both rising and falling edges are valid WDI inputs. A capacitor attached to WT sets the watchdog timeout period. A valid WDI edge clears the internal counter driven by a clock signal based on CWT, preventing WDO from going low. Once the watchdog timer expires and WDO is latched low, WDI must transition between low and high logic levels to clear WDO. See the Watchdog Timer section for more information. WDO (LTC2963 only): Watchdog Output. Open drain output weakly pulled to VCC. The watchdog timer is enabled when RST is high. The WDO output pulls low if the watchdog timer expires, and it remains low until the next valid WDI transition during the watchdog timer period or if a channel undervoltage condition occurs. A watchdog failure also triggers a reset event, and the RST output pulls low. Leave open if unused. See the Watchdog Timer section for more information. WDS (LTC2963 only): Initial watchdog timeout select input. A three-state input controls the duration of the initial watchdog timeout immediately following any reset event. Extending the timeout for the first period gives extra time for the system logic to initialize before generating watchdog input pulses. A logic low sets the timeout to its nominal time period (equal to the watchdog upper timeout). Leaving the WDS input open sets the timeout to eight times the watchdog upper timeout, while a logic high selects sixty-four times the watchdog upper timeout. See the Initial Watchdog Timeout discussion for more details. WT (LTC2963 only): Watchdog Timeout Capacitor Input. Attach a capacitor CWT between WT and GND to set a watchdog timeout period of 100ms/nF. Leaving WT open generates a minimum timeout period of approximately 2ms, which may vary depending on parasitic capacitance on the pin. Tie WT to GND in order to disable the watchdog function. Tie WT to VCC to activate the internal 1.6s watchdog timer. Rev 0 For more information www.analog.com 9 LTC2962/LTC2963/LTC2964 BLOCK DIAGRAM VCC VCC LTC2964 OPTION GND VCC BUFFER REF 6A BANDGAP REFERENCE x1 OUT1 PG1 OUT2 A/D 4 PG2 OUT3 PG3 OUT4 PG4 CHANNEL 1 CHANNEL 2 V1 * V2 CHANNEL 3 - CHANNEL 4 4 V3 + V4 0.5V VCC + - 0.18V + - RT CHANNEL 1 DVCC + - CHANNEL 2 CHANNEL 3 VCC CHANNEL 4 VCC 6A 10A MR VCC ADJUSTABLE RESET TIME-OUT O 200ms RESET TIME-OUT I RST 10A RDIS LTC2963 OPTION V CC DVCC 10A ADJUSTABLE WATCHDOG TIME-OUT 6A I WDO O VCC 3-STATE INPUT + WDS TIMING CONTROL 1.6s WATCHDOG TIME-OUT - WDI VCC + - 0.1V WT 2962 BD *REVERSE POLARITY FOR -ADJ MODE Rev 0 10 For more information www.analog.com LTC2962/LTC2963/LTC2964 OPERATION The LTC2962 family monitors up to four power supplies (or channels) with industry leading 0.5% accuracy over a wide temperature range. While primarily intended for monitoring undervoltage (UV) events, the LTC2962 family has a mode allowing for overvoltage (OV) monitoring. In typical operation, if any of the monitored supplies fall below a predetermined threshold, the reset output, RST, pulls low immediately. When all four supplies rise above their threshold (or below, in the case of -ADJ mode), the reset output is released after a timeout period. The reset timeout can be a fixed 200ms or it can be adjusted using an external capacitor. The reset output is held low during power-up, power-down and brownout conditions on any channel. ADJ modes and fourteen UV thresholds can be configured for each channel individually. Each of the four program (PG) inputs select one of sixteen voltage monitor thresholds for each input respectively. During power-up, a 4-bit ADC converts the voltage on each PG input. The resultant digital value is decoded into one of the sixteen threshold options (see Table 1). This technique allows for 1% standard resistors to be used to configure the PG inputs while maintaining tight 0.5% accuracy for each threshold. 65,536 different threshold combinations can be selected with the LTC2962 family, including the ability to monitor the same voltage on more than one channel. The +ADJ and -ADJ modes compare the channel inputs to 0.5V. With an external resistive divider, +ADJ can be used to monitor any voltage greater than 0.5V. -ADJ can be used as an overvoltage monitor for positive supplies or an undervoltage monitor for negative supplies. The reset disable function, RDIS, eases system voltage margining by forcing RST high. During normal operation, RST will go low when the monitored voltage (e.g. V1, V2, etc.) falls below its threshold (or above, in the case of - ADJ mode). By disabling the reset function with RDIS, a microprocessor voltage limit can be tested through margining without issuing a system reset. In addition to being able to ignore valid reset outputs, a manual reset can also be commanded with the MR input. This input has an internal pull-up and debounce circuitry making it well suited for a pushbutton input. When MR goes low, RST pulls low immediately. When MR goes high, RST is released after the configured reset timeout delay - assuming that all four monitored voltages are above their configured threshold. With DVCC grounded, RST is an open-drain output weakly pulled up internally to VCC by 6A through a Schottky diode. However, if DVCC is externally connected to a voltage greater than 1.6V, then RST will be driven as an active push-pull output to DVCC. LTC2963 Watchdog Functionality In addition to the common LTC2962 family functionality discussed above, the LTC2963 offers a watchdog function. In the LTC2963, the WDI input must receive an edge (rising or falling) at least as often as the configured watchdog upper timeout period. This time can be fixed to 1.6s by connecting WT to VCC or it can be adjusted using an external capacitor on WT. If WDI does not receive a signal quickly enough, then WDO (watchdog status) and RST outputs will both pull low. RST returns high after a single reset timeout period. Like the RST output, the WDO output has a weak internal pull-up to VCC, but can be used as an active push-pull if DVCC is greater than 1.6V. The details of WDO functionality can be found in the Watchdog Timer section. Following a reset event, the microprocessor under supervision may require more time than usual to send valid watchdog edge transitions. The 3-state WDS input provides a way to choose three different initial watchdog timeout periods immediately following a reset. LTC2964 Individual Outputs The LTC2964 provides individual comparator outputs for each voltage input. These outputs could serve as a status indicator, e.g. power good, or be part of a power supply sequencer circuit. OUT1 through OUT4 provide the outputs of each of the four channel comparators without the adjustable reset timeout delay. Rev 0 For more information www.analog.com 11 LTC2962/LTC2963/LTC2964 APPLICATIONS INFORMATION Threshold Accuracy The LTC2962 family features outstanding accuracy. To better understand the importance and implication of the monitor accuracy, we provide the following example. Consider a system device whose operation requires 1V 4.5% tolerance. In other words, to guarantee proper operation, the manufacturer states that the voltage presented to the device remain between 0.955V and 1.045V. In an ideal world, the power supply providing voltage to this device could vary over that entire range, and an ideal undervoltage supervisor for the supply would generate a reset at exactly 0.955V. However, no supervisor is perfect. The actual reset threshold of a supervisor varies over a specified range; the LTC2962 family varies 0.5% around its nominal threshold voltage over temperature (see Figure 1). NOMINAL SUPPLY 1.0V VOLTAGE ALLOWED SUPPLY TOLERANCE MINIMAL RELIABLE SYSTEM VOLTAGE 0.5% THRESHOLD BAND IDEAL SUPERVISOR THRESHOLD 0.965V 0.960V 0.955V SYSTEM VOLTAGE MARGIN -3.5% -4.0% -4.5% REGION OF POTENTIAL MALFUNCTION 296234 F01 Figure 1. Threshold Diagram The monitor reset threshold range and the power supply tolerance range should not overlap. This prevents false or nuisance resets when the power supply is actually within its specified tolerance range. The LTC2962 family has 0.5% reset threshold accuracy, so a system load requiring 4.5% tolerance requires the supervisor threshold to be set 4% below the nominal supply voltage. Using the 1V system described, the nominal -4% monitor threshold would be 0.96V. The monitor threshold is guaranteed to be between 0.955V and 0.965V over temperature. The powered system must work reliably down to the low end of the threshold range, 0.955V, or risk malfunction before a reset signal is properly issued. Furthermore, the power supply must be guaranteed to provide a voltage greater than 0.965V to avoid a false or nuisance reset. An extremely accurate supervisor, like the LTC2962 family, has reduced monitor threshold spread, which increases system voltage margin and reduces the probability of system malfunction. By providing increased system margin the demands of the power supply are relaxed. For example, with a 1% supervisor, the nominal supervisor threshold would need to be increased from -4% to -3.5%, and the lower limit of the power supply tolerance would be at -2.5%, 0.975V as opposed to 0.965V. In other words, the power supply would need to be more precise by 1%. Because of the accuracy of the LTC2962 family, it may be possible to use a smaller capacitor or a smaller inductor in the power supply. The system may be more tolerant of transient excursions. The additional margin may even allow a lower nominal supply voltage, which can dramatically reduce power consumption. Hence, the best-in-class 0.5% accuracy of the LTC2962 family provides many benefits. Power-Up Upon initial application of voltage, VCC will power the drive circuits for the RST output. This ensures that the RST output will be low as soon as VCC reaches 1V. The RST output remains low until the part is configured. See Monitor Configuration for details about configuration. After configuration, if any one of the supply monitor inputs falls below (or rises above, in -ADJ mode) its configured threshold, RST will continue to remain low. Once all monitor inputs rise above their thresholds, an internal timer is started and RST is released after the configured delay time, tRST. Monitor Configuration Configure the monitor threshold for each channel input by placing the recommended resistive divider from REF to GND and connect the tap point to the appropriate PG input, as shown in Figure 2. Table 1 specifies optimum VPG/VREF ratios when configuring with a resistive divider or a ratiometric DAC. As one may want to share the resistive divider for all four PG inputs, the following procedure is recommended. Rev 0 12 For more information www.analog.com LTC2962/LTC2963/LTC2964 APPLICATIONS INFORMATION LTC2962 FAMILY REF REF R2 1% PG1 5V -4% PGn GND R1 1% 296234 F02 Figure 2. Monitor Configuration First, create a resistive divider between REF and GND composed of fifteen ideal 10k resistors. For a specific input threshold combination, locate the optimal tap point for each PG input following the ratio provided in Table 1. Second, merge all resistors between any two adjacent tap points into one single resistor and choose the standard value using Table 2. Note the actual resistors in Table 2 are standard 1% values. Despite the difference between the actual and the calculated resistance value as well as the 1% tolerance, the LTC2962 family is guaranteed to select the proper configuration. Table 1. Voltage Configuration Table SUPPLY VOLTAGE OPTIMAL RATIO VPG/VREF +ADJ 1 5.0V, -4% 14/15 5.0V, -6% 13/15 3.3V, -4% 12/15 3.3V, -6% 11/15 2.5V, -4% 10/15 2.5V, -6% 9/15 1.8V, -4% 8/15 1.8V, -6% 7/15 1.5V, -4% 6/15 1.5V, -6% 5/15 1.2V, -4% 4/15 1.2V, -6% 3/15 1.0V, -4% 2/15 1.0V, -6% 1/15 -ADJ 0 PG2 3.3V -4% REF R14 10k R8 10k R7 10k R13 10k R9 10k R6 10k R1 10k R3 10k R10 10k R5 10k R2 10k R12 10k R11 10k R4 10k PG3 1.2V -4% STEP 1: IDEAL LADDER 296234 F03 PG4 -ADJ PG1 PG2 PG3 R3 10k PG4 RX4 10k 1% RX3 30.1k 1% RX2 69.8k 1% RX1 40.2k 1% STEP 2: CHOOSE ACTUAL RESISTORS Figure 3. Programming (PG) Pin Bias Example When a DAC is used to drive the PG inputs, the LTC2962 family is guaranteed to operate properly for bias voltage within 1.5% of VREF relative to the optimal value. During power-up, once VCC reaches VCCMINC (2.2V max), the LTC2962 family enters a configuration period of approximately 500s during which the voltage on each of the four PG inputs are sampled and the monitor is configured to the desired threshold. Immediately after configuration, the comparators are enabled and supply monitoring will begin. Note once the part is configured, it cannot be reconfigured without powering down. Do not add capacitance to the PG inputs. It is always beneficial to Kelvin connect the resistive divider ground to the LTC2962 family GND. Table 2. Recommended 1% Resistors for Programming CALCULATED RESISTOR VALUE (k) ACTUAL RESISTOR VALUE (k) 10 10 Figure 3 shows an example of choosing PG resistors using the above procedure. In the example, the V1 monitor threshold is 5V -4% (4.8V), V2 is 3.3V -6% (3.102V), V3 is 1.2V -4% (1.152V) and V4 is set to -ADJ mode, respectively. 20 20 30 30.1 40 40.2 50 49.9 60 60.4 70 69.8 80 80.6 90 90.9 100 100 110 110 120 121 130 130 140 140 Rev 0 For more information www.analog.com 13 LTC2962/LTC2963/LTC2964 APPLICATIONS INFORMATION Supply Monitoring - Fixed Thresholds With the exception of the +ADJ and -ADJ modes, the remaining fourteen configuration settings for each channel set a fixed monitor threshold for that channel. In these settings, the input impedance of each of the four channel voltage inputs (V1 ~ V4) is a fixed 1.2M to ground. As shown in the block diagram, the 4-bit programming ADC selects an attenuation factor between the channel voltage input and the channel comparator input corresponding to the configured fixed monitor threshold. These settings require the fewest external components and provide the ability to monitor any of the preselected thresholds with 0.5% accuracy using, at most, five external 1% PG resistors. In the negative adjustable (-ADJ) mode, the comparator polarity is reversed as shown in Figure 5. The internal 0.5V reference is connected to the non-inverting comparator input. An external resistive divider connected between the negative voltage being sensed and the REF output is connected to the channel voltage input (V1 ~ V4). VREF provides the necessary level shift required to operate the comparator. Calculate the negative threshold voltage from: R3 R3 VTH = 0.5V * 1+ - VREF * R4 R4 where VREF = 1.195V Nominal R4 Supply Monitoring - Adjustable Thresholds In the two Adjustable modes (+ADJ and -ADJ), the channel voltage inputs become high impedance. Normally these modes require the use of an additional external resistive divider, but provide the ability to monitor any supply voltage threshold. In positive adjustable (+ADJ) mode, the comparator reference input (inverting) is set to 0.5V as shown in Figure 4. An external resistive divider connected between the positive voltage being sensed and ground is connected to the channel voltage input (V1 ~ V4). Calculate the channel threshold voltage from: R4 VTH = 0.5V * 1+ R3 Vn R3 + - VSUPPLY - + 0.5V 296234 F05 Figure 5. Setting the Negative Adjustable (-ADJ) Threshold In a negative adjustable application, the minimum value for R4 is limited by the sourcing capability of REF (1mA). With no other load on REF, R4 (minimum) is: R4(min)= 1.195V - 0.5V = 695 1mA Tables 3 and 4 offer suggested 0.1% resistor values for various adjustable applications. VSUPPLY R4 LTC2962 FAMILY REF Table 3. Suggested 0.1% Resistor Values for +ADJ Inputs (Figure 4) LTC2962 FAMILY Vn R3 + - + - 0.5V 296234 F04 VSUPPLY (V) VTH (V) R4 (k) R3 (k) 12 11.25 2150 100 10 9.4 1780 100 8 7.5 1400 100 7.5 7 1300 100 6 5.6 1020 100 Figure 4. Setting the Positive Adjustable (+ADJ) Threshold Rev 0 14 For more information www.analog.com LTC2962/LTC2963/LTC2964 APPLICATIONS INFORMATION Table 4. Suggested 0.1% Resistor Values for -ADJ Inputs (Figure 5) VSUPPLY (V) VTH (V) R3 (k) R4 (k) -2 -1.866 412 121 -5 -4.721 909 121 -5.2 -4.847 931 121 -10 -9.494 1740 121 -12 -11.28 2050 121 Supply Monitoring - Overvoltage Thresholds Because the comparator polarity is reversed for the -ADJ mode, this mode can also be used for overvoltage monitoring. Implementing undervoltage and overvoltage (UV/ OV) monitoring of a single supply is as simple as dedicating two channels in ADJ mode as shown in Figure 6. The threshold voltages are: R5+R4 VOVTH = 0.5 * 1+ R3 R5 VUVTH = 0.5 * 1+ R4+R3 R4 LTC2962 FAMILY V1 + - V2 R3 + - Selecting the Reset Timing Capacitor The reset timeout period is adjustable in order to accommodate a variety of applications. The reset timeout period, tRST, is adjusted by connecting a capacitor, CRT, between RT and ground. The value of this capacitor is determined by: CRT = tRST * 83 [pF/ms] A graph of reset timeout period as a function of the RT capacitor can be found in the Typical Performance Characteristics section. Leaving RT open generates a minimum reset timeout period of approximately 250s. Maximum reset timeout period is limited by the largest available low leakage capacitor. The accuracy of the timeout period is affected by capacitor tolerance, temperature coefficienct and leakage (the nominal RT charging current is 2A). A low leakage ceramic capacitor is recommended. Connect RT to VCC generates a fixed reset timeout of approximately 200ms. VSUPPLY R5 configuration (VCCMINC, guaranteed to be below 2.2V), then the device may reconfigure when VCC rises above VCCMINC. Glitch Immunity + - In any supervisor application, noise on the monitored DC voltage could cause spurious undesirable resets. Two techniques are used to combat the spurious resets without sacrificing threshold accuracy. First, the reset timeout period helps prevent high-frequency supply variation whose frequency is above 1/tRST from appearing at the output RST. 0.5V - + 0.5V 296234 F06 Figure 6. 3-Resistor Positive UV/OV Monitoring Configuration (V1 in +ADJ, V2 in -ADJ) Power-Down On power-down, once any of the monitor inputs drop below its threshold, RST is held at a logic low. A logic low of 0.4V is guaranteed until VCC drops below 1V. If VCC drops below the minimum voltage required for When the voltage input goes below the threshold, the RST output goes low. When it recovers beyond the threshold, the reset timer starts (assuming it is not disabled by RDIS), and RST does not go high until the timeout completes. If the monitored supply becomes invalid during the timeout period, the timer resets. The timer will restart when the supply becomes valid again. While the reset timeout is useful at preventing RST toggling in most cases, it is not effective at preventing nuisance resets due to short glitches (due to load transients Rev 0 For more information www.analog.com 15 LTC2962/LTC2963/LTC2964 APPLICATIONS INFORMATION or other effects) on a valid supply. Hysteresis is traditionally used to solve this problem, but it causes additional error in the threshold voltage. In order to reduce sensitivity to these short glitches without introducing hysteresis, the LTC2962 family low-pass filters the output of the first stage in the comparator. This filter integrates the output of the comparator before pulling the reset output low, dramatically reducing the effect of instantaneous glitches or noise. Only a transient with sufficient magnitude and duration at the input of the comparator will trigger the output logic. The Typical Performance Characteristics section shows a graph of the Transient Duration vs Comparator Overdrive. Unlike some other supply monitors, LTC2962 family transient duration is not sensitive to supply voltage VCC and thus leads to better predictability. The combination of the reset timeout and anti-glitch circuitry prevents spurious changes in output state without sacrificing threshold accuracy. Watchdog Timer (LTC2963) Watchdog circuitry is used to ensure that the system is functioning properly by continuously monitoring microprocessor activity. The microprocessor is required to change the logic state of the WDI input periodically to clear the watchdog timer. The CWT timing capacitor adjusts the watchdog timeout period depending on the application and microprocessor requirements. If the software malfunctions and the state of WDI does not change properly, the watchdog times out and the WDO output is latched low. Simultaneously, RST is pulled low to reset the microprocessor. While RST is low, the WDI input does not affect RST or WDO. The system therefore resets for at least tRST. After the configured reset timeout period, tRST, RST goes back high and the microprocessor can poll the state of the WDO output to determine if the reset was caused by a voltage-based comparator event or by a watchdog fault. Following the rising edge of RST, if WDO output is high, then the reset was caused by a voltage-based comparator event. If WDO output is low, then the system reset was caused by a watchdog fault. The rising edge of RST resets the watchdog timer, and the microprocessor can then issue a valid WDI input to clear the WDO latch. Please see the Initial Watchdog Timeout section for details on a valid WDI input following a reset. If the microprocessor fails to issue a valid WDI, the watchdog will timeout and behave as described above with the exception that the WDO output will already be low. Note manual reset has the same effect on watchdog function as comparator event. The RST and WDO outputs should not be tied together to generate the master reset signal since a watchdog timeout forces RST low together with WDO and the master reset signal will remain low indefinitely. LTC2963 provides traditional watchdog functionality with a constraint on the lower bound of the WDI input frequency. Selecting the Watchdog Timing Capacitor The watchdog timeout period is adjustable and can be optimized for software execution. The watchdog upper timeout, tWDU, can be adjusted by connecting a capacitor, CWT, between WT and ground. Given a specified watchdog timeout period, the capacitor is determined by: CWT = tWDU * 10 [pF/ms] The accuracy of the timeout period will be affected by capacitor leakage (the nominal charging current is 2A) and capacitor tolerance. A low leakage ceramic capacitor is recommended. Leaving WT open will generate a minimum watchdog timeout of approximately 2ms. Connecting WT to VCC generates a fixed watchdog timeout of 1.6s. Initial Watchdog Timeout Following a reset event, the microprocessor under supervision may require more time than usual to send valid watchdog edge transitions. In order for the microprocessor to have sufficient setup time to issue valid WDI inputs and avoid an unnecessary reset, the LTC2963 offers flexible adjustability for the initial watchdog timeout using the WDS input. The 3-state WDS input provides three different initial watchdog timeout periods immediately following a reset. Connecting the WDS input to ground sets the initial watchdog timeout, tWD(INIT) equal to the watchdog Rev 0 16 For more information www.analog.com LTC2962/LTC2963/LTC2964 APPLICATIONS INFORMATION upper timeout, tWDU. Leaving WDS open sets the initial watchdog timeout to eight times the upper timeout, while connecting WDS to VCC sets it to sixty-four times the upper timeout. Table 6. Initial Watchdog Timeout Options with WDS WDS INITIAL WATCHDOG TIMEOUT tWD(INIT) GND tWDU Open 8 * tWDU VCC 64 * tWDU The rising edge of the RST output resets the watchdog timer and starts the initial watchdog timeout, tWD(INIT), and is the upper limit for a valid WDI input immediately following a rising edge of the RST output. If there is no valid WDI edge before tWD(INIT) expires, a typical watchdog fault occurs as described above in the Watchdog Timer section. When the initial watchdog timer is properly cleared by a valid WDI edge, the LTC2963 starts using the normal watchdog timer limits (tWDU for LTC2963). to reduce mechanical stress. A thicker and smaller board is stiffer and less prone to bend. Finally, use stress relief, such as flexible standoffs, when mounting the board. To prevent interference, try to place the LTC2962 close to the device it monitors. For best accuracy, connect the channel voltage inputs (V1 ~ V4) directly to the supply pin of the device it monitors. This avoids possible voltage drop between the output of the power supply and the input supply of the device under supervision. Careful attention to grounding is also important, especially when LTC2962 is sinking significant current through logic outputs or the REF output. The return load current can produce ground potential differences between LTC2962 and the device under supervision. This voltage difference may manifest as threshold hysteresis. Use a star ground connection and minimize the ground metal resistance, especially for applications where multiple devices are monitored. Figure 7 gives an example of the optimal layout practice for good voltage monitoring. PCB Layout KELVIN CONNECT The LTC2962 family is a precision device whose comparator thresholds are factory trimmed to 0.5% accuracy as shown in the Typical Performance Characteristics section. The mechanical stress caused by soldering parts to a printed circuit board may cause the threshold to shift and the temperature coefficient to change. While every situation is different, expected errors due to these effects are likely to be on the order of 0.05%. To reduce the effects of stress-related shifts, mount the device near the short edge of a printed circuit board or in a corner. In addition, slots can be cut into the board on two sides of the device VOUT POWER SUPPLY GND VDD STAR Vn DEVICE (P, FPGA, ETC.) GND + - + - LTC2962 FAMILY 0.5V GND MINIMIZE RESISTANCE OF METAL 296234 F07 Figure 7. Kelvin Connection for Good Voltage Monitoring Rev 0 For more information www.analog.com 17 LTC2962/LTC2963/LTC2964 PACKAGE DESCRIPTION UD Package 16-Lead Plastic QFN (3mm x 3mm) (Reference LTC DWG # 05-08-1691 Rev O) 0.70 0.05 3.50 0.05 1.45 0.05 2.10 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 0.10 (4 SIDES) BOTTOM VIEW--EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 0.25 x 45 CHAMFER R = 0.115 TYP 0.75 0.05 15 PIN 1 TOP MARK (NOTE 6) 16 0.40 0.10 1 1.45 0.10 (4-SIDES) 2 (UD16) QFN 0904 0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC Rev 0 18 For more information www.analog.com LTC2962/LTC2963/LTC2964 PACKAGE DESCRIPTION UDC Package 20-Lead Plastic QFN (3mm x 4mm) (Reference LTC DWG # 05-08-1742 Rev O) 0.70 0.05 3.50 0.05 2.10 0.05 1.50 REF 2.65 0.05 1.65 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.50 REF 3.10 0.05 4.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 0.10 0.75 0.05 1.50 REF 19 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.25 x 45 CHAMFER 20 0.40 0.10 1 PIN 1 TOP MARK (NOTE 6) 4.00 0.10 2 2.65 0.10 2.50 REF 1.65 0.10 (UDC20) QFN 1106 REV O 0.200 REF 0.00 - 0.05 R = 0.115 TYP 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license isFor granted implication orwww.analog.com otherwise under any patent or patent rights of Analog Devices. morebyinformation 19 LTC2962/LTC2963/LTC2964 TYPICAL APPLICATION Supervisor with Power-Up Sequence Function 3.3V 2.5V DC/DC CONVERTER 1.8V 1.5V 3.3V 2.5V 1.8V 1.5V EN4 EN3 EN2 0.1F VCC V1 V2 V3 V4 DVCC 0.1F OUT1 SYSTEM LOGIC OUT2 OUT3 OUT4 30.1k 1% 20k 1% 20k 1% 20k 1% 60.4k 1% REF LTC2964 RST PG1 RDIS PG2 tRST 56ms RESET TIMEOUT PG3 MR PG4 GND RT 47nF 296234 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2900/LTC2902 Programmable Quad Supply Monitor Adjustable Reset and Watchdog Timer, 10-Lead MSOP and DFN Packages LTC2903-1 6-Lead SOT-23 Package Precision Quad Supply Monitor LTC2904/LTC2907 Three-State Programmable Precision Dual Supply Monitor 8-Lead SOT-23 and DFN Packages LTC2908 Precision Six Supply Monitor (Four Fixed and Two Adjustable) 8-Lead TSOT-23 and DFN Packages LTC2909 Precision Triple/Dual Input UV, OV and Negative Voltage Monitor Shunt Regulated VCC Pin, Adjustable Threshold and Reset, 8-Lead SOT-23 and DFN Packages LTC2910 Precision Octal Positive/Negative Voltage Supply Monitor 16-Lead SSOP and 5mm x 3mm DFN Packages, H-Grade Temperature Range LTC2912/LTC2914 Single/Dual/Quad UV and OV Voltage Monitors Separate VCC Pin, Adjustable Reset Timer, H-Grade Temperature Range LTC2915/LTC2918 Single Supply Monitor with 27 Pin-Selectable Thresholds Manual Reset, Watchdog, TSOT-8/MSOP-10 and 3mm x 2mm DFN Packages, H-Grade Temperature Range LTC2928 Quad Power Supply Sequencer and Supervisor Easily Configure Power Management without Software, 36-Lead LTC2932 Configurable Six Supply Monitor with Adjustable Reset Timer and Supply Tolerance Selectable Supply Tolerance, 20-Lead TSSOP Package LTC2938 Configurable 4-Supply Monitors with Watchdog Timer Adjustable Reset and Watchdog Timeout, 12-Lead MSOP and DFN Packages Rev 0 20 D17154-0-8/18(0) www.analog.com ANALOG DEVICES, INC. 2018