1. General description
The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
nWide supply voltage range from 0.8 V to 3.6 V
nHigh noise immunity
nComplies with JEDEC standards:
uJESD8-12 (0.8 V to 1.3 V)
uJESD8-11 (0.9 V to 1.65 V)
uJESD8-7 (1.2 V to 1.95 V)
uJESD8-5 (1.8 V to 2.7 V)
uJESD8-B (2.7 V to 3.6 V)
nESD protection:
uHBM JESD22-A114E Class 3A exceeds 5000 V
uMM JESD22-A115-A exceeds 200 V
uCDM JESD22-C101C exceeds 1000 V
nLow static power consumption; ICC = 0.9 µA (maximum)
nLatch-up performance exceeds 100 mA per JESD 78 Class II
nInputs accept voltages up to 3.6 V
nLow noise overshoot and undershoot < 10 % of VCC
nIOFF circuitry provides partial Power-down mode operation
nMultiple package options
nSpecified from −40 °Cto+85°C and −40 °C to +125 °C
74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
Rev. 03 — 2 July 2009 Product data sheet
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 2 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AUP1G386GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363
74AUP1G386GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 ×1.45 ×0.5 mm SOT886
74AUP1G386GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 ×1×0.5 mm SOT891
Table 2. Marking
Type number Marking code[1]
74AUP1G386GW aH
74AUP1G386GM aH
74AUP1G386GF aH
Fig 1. Logic symbol Fig 2. IEC logic symbol
mnb143
B
A
C
Y
6
3
1
41
6
= 1 4
mnb145
3
Fig 3. Logic diagram
mnb144
A
B
C
Y
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 3 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Fig 4. Pin configuration SOT363
(SC-88) Fig 5. Pin configuration SOT886
(XSON6) Fig 6. Pin configuration SOT891
(XSON6)
74AUP1G386
AC
GND
BY
001aad937
1
2
3
6
VCC
5
4
74AUP1G386
GND
001aad939
A
B
VCC
C
Y
Transparent top view
2
3
1
5
4
674AUP1G386
GND
001aad938
A
B
VCC
C
Y
Transparent top view
2
3
1
5
4
6
Table 3. Pin description
Symbol Pin Description
A 1 data input A
GND 2 ground (0 V)
B 3 data input B
Y 4 data output Y
VCC 5 supply voltage
C 6 data input C
Table 4. Function table[1]
Input Output
ABCY
LLLL
LLHH
LHLH
LHHL
HLLH
HLHL
HHLL
HHHH
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 4 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +4.6 V
IIK input clamping current VI<0V −50 - mA
VIinput voltage [1] −0.5 +4.6 V
IOK output clamping current VO<0V −50 - mA
VOoutput voltage Active mode and Power-down mode [1] −0.5 +4.6 V
IOoutput current VO=0 VtoV
CC -±20 mA
ICC supply current - 50 mA
IGND ground current −50 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb =−40 °C to +125 °C[2] - 250 mW
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.8 3.6 V
VIinput voltage 0 3.6 V
VOoutput voltage Active mode 0 VCC V
Power-down mode; VCC = 0 V 0 3.6 V
Tamb ambient temperature −40 +125 °C
∆t/∆V input transition rise and fall rate VCC = 0.8 V to 3.6 V 0 200 ns/V
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 5 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 °C
VIH HIGH-level input voltage VCC = 0.8 V 0.70 × VCC -- V
VCC = 0.9 V to 1.95 V 0.65 × VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30 × VCC V
VCC = 0.9 V to 1.95 V - - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V
IO = −1.1 mA; VCC = 1.1 V 0.75 × VCC -- V
IO = −1.7 mA; VCC = 1.4 V 1.11 - - V
IO = −1.9 mA; VCC = 1.65 V 1.32 - - V
IO = −2.3 mA; VCC = 2.3 V 2.05 - - V
IO = −3.1 mA; VCC = 2.3 V 1.9 - - V
IO = −2.7 mA; VCC = 3.0 V 2.72 - - V
IO = −4.0 mA; VCC = 3.0 V 2.6 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.31 V
IO = 1.9 mA; VCC = 1.65 V - - 0.31 V
IO = 2.3 mA; VCC = 2.3 V - - 0.31 V
IO = 3.1 mA; VCC = 2.3 V - - 0.44 V
IO = 2.7 mA; VCC = 3.0 V - - 0.31 V
IO = 4.0 mA; VCC = 3.0 V - - 0.44 V
IIinput leakage current VI= GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 µA
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.2 µA
∆IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V --±0.2 µA
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V - - 0.5 µA
∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V --40µA
CIinput capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.8 - pF
COoutput capacitance VO = GND; VCC = 0 V - 1.7 - pF
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 6 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage VCC = 0.8 V 0.70 × VCC -- V
VCC = 0.9 V to 1.95 V 0.65 × VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30 × VCC V
VCC = 0.9 V to 1.95 V - - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V
IO = −1.1 mA; VCC = 1.1 V 0.7 × VCC -- V
IO = −1.7 mA; VCC = 1.4 V 1.03 - - V
IO = −1.9 mA; VCC = 1.65 V 1.30 - - V
IO = −2.3 mA; VCC = 2.3 V 1.97 - - V
IO = −3.1 mA; VCC = 2.3 V 1.85 - - V
IO = −2.7 mA; VCC = 3.0 V 2.67 - - V
IO = −4.0 mA; VCC = 3.0 V 2.55 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.37 V
IO = 1.9 mA; VCC = 1.65 V - - 0.35 V
IO = 2.3 mA; VCC = 2.3 V - - 0.33 V
IO = 3.1 mA; VCC = 2.3 V - - 0.45 V
IO = 2.7 mA; VCC = 3.0 V - - 0.33 V
IO = 4.0 mA; VCC = 3.0 V - - 0.45 V
IIinput leakage current VI= GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.5 µA
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.5 µA
∆IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V --±0.6 µA
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V - - 0.9 µA
∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V --50µA
Table 7. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 7 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
Tamb = −40 °C to +125 °C
VIH HIGH-level input voltage VCC = 0.8 V 0.75 × VCC -- V
VCC = 0.9 V to 1.95 V 0.70 × VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.25 × VCC V
VCC = 0.9 V to 1.95 V - - 0.30 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.11 - - V
IO = −1.1 mA; VCC = 1.1 V 0.6 × VCC -- V
IO = −1.7 mA; VCC = 1.4 V 0.93 - - V
IO = −1.9 mA; VCC = 1.65 V 1.17 - - V
IO = −2.3 mA; VCC = 2.3 V 1.77 - - V
IO = −3.1 mA; VCC = 2.3 V 1.67 - - V
IO = −2.7 mA; VCC = 3.0 V 2.40 - - V
IO = −4.0 mA; VCC = 3.0 V 2.30 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.11 V
IO = 1.1 mA; VCC = 1.1 V - - 0.33 × VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.41 V
IO = 1.9 mA; VCC = 1.65 V - - 0.39 V
IO = 2.3 mA; VCC = 2.3 V - - 0.36 V
IO = 3.1 mA; VCC = 2.3 V - - 0.50 V
IO = 2.7 mA; VCC = 3.0 V - - 0.36 V
IO = 4.0 mA; VCC = 3.0 V - - 0.50 V
IIinput leakage current VI= GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.75 µA
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 µA
∆IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V --±0.75 µA
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V - - 1.4 µA
∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V --75µA
Table 7. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 8 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions 25 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
(85 °C) Max
(125 °C)
CL = 5 pF
tpd propagation delay A, B and C to Y; see Figure 7 [2]
VCC = 0.8 V - 23.4 - - - - ns
VCC = 1.1 V to 1.3 V 2.7 6.5 14.2 2.4 14.6 14.7 ns
VCC = 1.4 V to 1.6 V 2.0 4.4 8.1 2.1 8.8 9.1 ns
VCC = 1.65 V to 1.95 V 1.8 3.5 6.1 1.6 7.0 7.3 ns
VCC = 2.3 V to 2.7 V 1.5 2.7 4.3 1.2 4.6 4.8 ns
VCC = 3.0 V to 3.6 V 1.3 2.4 3.6 1.0 4.0 4.2 ns
CL = 10 pF
tpd propagation delay A, B and C to Y; see Figure 7 [2]
VCC = 0.8 V - 26.8 - - - - ns
VCC = 1.1 V to 1.3 V 3.2 7.3 15.8 2.7 16.2 16.3 ns
VCC = 1.4 V to 1.6 V 2.3 5.0 9.0 2.5 9.8 10.2 ns
VCC = 1.65 V to 1.95 V 2.2 4.1 6.9 1.9 7.8 8.2 ns
VCC = 2.3 V to 2.7 V 1.9 3.2 5.0 1.6 5.3 5.5 ns
VCC = 3.0 V to 3.6 V 1.7 2.9 4.3 1.4 4.7 4.9 ns
CL = 15 pF
tpd propagation delay A, B and C to Y; see Figure 7 [2]
VCC = 0.8 V - 30.1 - - - - ns
VCC = 1.1 V to 1.3 V 3.5 8.1 17.3 3.0 17.7 17.8 ns
VCC = 1.4 V to 1.6 V 2.6 5.6 9.8 2.8 10.7 11.1 ns
VCC = 1.65 V to 1.95 V 2.4 4.6 7.5 2.2 8.6 9.0 ns
VCC = 2.3 V to 2.7 V 2.2 3.7 5.5 1.9 5.9 6.2 ns
VCC = 3.0 V to 3.6 V 2.0 3.4 4.8 1.7 5.2 5.5 ns
CL = 30 pF
tpd propagation delay A, B and C to Y; see Figure 7 [2]
VCC = 0.8 V - 37.9 - - - - ns
VCC = 1.1 V to 1.3 V 4.5 10.3 21.6 3.9 22.0 22.1 ns
VCC = 1.4 V to 1.6 V 3.5 7.1 12.1 3.5 13.2 13.8 ns
VCC = 1.65 V to 1.95 V 3.1 5.8 9.5 2.8 10.7 11.3 ns
VCC = 2.3 V to 2.7 V 2.9 4.8 6.9 2.6 7.8 8.2 ns
VCC = 3.0 V to 3.6 V 2.7 4.5 6.1 2.3 6.6 6.9 ns
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 9 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
[1] All typical values are measured at nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] All specified values are the average typical values over all stated loads.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL×VCC2×fo) = sum of the outputs.
12. Waveforms
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation
capacitance fi = 1 MHz; VI= GND to VCC [3][4]
VCC = 0.8 V - 2.9 - - - - pF
VCC = 1.1 V to 1.3 V - 3.0 - - - - pF
VCC = 1.4 V to 1.6 V - 3.1 - - - - pF
VCC = 1.65 V to 1.95 V - 3.3 - - - - pF
VCC = 2.3 V to 2.7 V - 3.9 - - - - pF
VCC = 3.0 V to 3.6 V - 4.4 - - - - pF
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions 25 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
(85 °C) Max
(125 °C)
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Input A, B and C to output Y propagation delay times
mnb147
tPHL tPLH
tPLH
VM
VM
A, B, C
input
Y output
in phase
GND
VI
VOH
VOL
Y output
out of phase
VOH
VOL
tPHL
VM
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 10 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
[1] For measuring enable and disable times RL=5kΩ, for measuring propagation delays, setup and hold times and pulse width RL=1MΩ.
Table 9. Measurement points
Supply voltage Output Input
VCC VMVMVItr = tf
0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuitry for switching times
001aac521
DUT
RT
VIVO
VEXT
VCC
RL
5 kΩ
CL
G
Table 10. Test data
Supply voltage Load VEXT
VCC CLRL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ
0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩopen GND 2 × VCC
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 11 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
13. Package outline
Fig 9. Package outline SOT363 (SC-88)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT363 SC-88
wBM
bp
D
e1
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
456
Plastic surface-mounted package; 6 leads SOT363
UNIT A1
max bpcDEe1HELpQywv
mm 0.1 0.30
0.20 2.2
1.8
0.25
0.10 1.35
1.15 0.65
e
1.3 2.2
2.0 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.25
0.15
A
1.1
0.8
04-11-08
06-03-16
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 12 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
Fig 10. Package outline SOT886 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT886 MO-252
SOT886
04-07-15
04-07-22
DIMENSIONS (mm are the original dimensions)
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17 1.5
1.4 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
6
2
5
3
4
6×
(2)
4×
(2)
A
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 13 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
Fig 11. Package outline SOT891 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT891
SOT891
05-04-06
07-05-15
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm 0.20
0.12 1.05
0.95 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.350.55
A
max
0.5 0.04
1
6
2
5
3
4
A
6×
(1)
4×
(1)
Note
1. Can be visible in some manufacturing processes.
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 14 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
14. Abbreviations
15. Revision history
Table 11. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AUP1G386_3 20090702 Product data sheet - 74AUP1G386_2
Modifications: •Section 8 “Limiting values”:
Changed: Derating factor XSON6 packages.
•Section 11 “Dynamic characteristics”:
Changed: typical power dissipation capacitance.
74AUP1G386_2 20080110 Product data sheet - 74AUP1G386_1
74AUP1G386_1 20061129 Product data sheet - -
74AUP1G386_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 July 2009 15 of 16
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 July 2009
Document identifier: 74AUP1G386_3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
17 Contact information. . . . . . . . . . . . . . . . . . . . . 15
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
