1
Motorola Small–Signal Transistors, FETs and Diodes Device Data
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MAXIMUM RATINGS
Value
Rating Symbol BCX17LT1
BCX19LT1 BCX18LT1
BCX20LT1 Unit
Collector–Emitter Voltage VCEO 45 25 Vdc
Collector–Base Voltage VCBO 50 30 Vdc
Emitter–Base Voltage VEBO 5.0 Vdc
Collector Current — Continuous IC500 mAdc
DEVICE MARKING
BCX17LT1 = T1; BCX18LT1 = T2; BCX19LT1 = U1; BCX20LT1 = U2
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR-5 Board (1)
TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance, Junction to Ambient RθJA 556 °C/W
Total Device Dissipation
Alumina Substrate, (2) TA = 25°C
Derate above 25°C
PD300
2.4
mW
mW/°C
Thermal Resistance, Junction to Ambient RθJA 417 °C/W
Junction and Storage Temperature TJ, Tstg 55 to +150 °C
1. FR–5 = 1.0 x 0.75 x 0.062 in.
2. Alumina = 0.4 x 0.3 x 0.024 in. 99.5% alumina
Thermal Clad is a trademark of the Bergquist Company
Order this document
by BCX17LT1/D
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SEMICONDUCTOR TECHNICAL DATA
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12
3
CASE 31808, STYLE 6
SOT–23 (TO236AB)
Voltage and current are negative
for PNP transistors
Motorola, Inc. 1996
COLLECTOR 3
1
BASE
2 EMITTER
COLLECTOR 3
1
BASE
2 EMITTER
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2 Motorola Small–Signal Transistors, FETs and Diodes Device Data
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage
(IC = 10 mAdc, IB = 0) BCX17, 19
BCX18, 20
V(BR)CEO 45
25
Vdc
Collector–Emitter Breakdown Voltage
(IC = 10 µAdc, IC = 0) BCX17, 19
BCX18, 20
V(BR)CES 50
30
Vdc
Collector Cutoff Current
(VCB = 20 Vdc, IE = 0)
(VCB = 20 Vdc, IE = 0, TA = 150°C)
ICBO
100
5.0 nAdc
µAdc
Emitter Cutoff Current
(VEB = 5.0 Vdc, IC = 0) IEBO 10 µAdc
ON CHARACTERISTICS
DC Current Gain
(IC = 100 mAdc, VCE = 1.0 Vdc)
(IC = 300 mAdc, VCE = 1.0 Vdc)
(IC = 500 mAdc, VCE = 1.0 Vdc)
hFE 100
70
40
600
Collector–Emitter Saturation Voltage
(IC = 500 mAdc, IB = 50 mAdc) VCE(sat) 0.62 Vdc
Base–Emitter On Voltage
(IC = 500 mAdc, VCE = 1.0 Vdc) VBE(on) 1.2 Vdc
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3
Motorola Small–Signal Transistors, FETs and Diodes Device Data
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by TJ(max), the maximum rated junction temperature of the
die, RθJA, the thermal resistance from the device junction to
ambient, and the operating temperature, TA. Using the
values provided on the data sheet for the SOT–23 package,
PD can be calculated as follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T A of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad. Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
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4 Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE DIMENSIONS
DJ
K
L
A
C
BS
H
GV
3
12
CASE 318–08
ISSUE AE
SOT–23 (TO–236AB)
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
DIM
AMIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0180 0.0236 0.45 0.60
L0.0350 0.0401 0.89 1.02
S0.0830 0.0984 2.10 2.50
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
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