REVOLUTIONIZING NON-VOLATILE INTEGRATION
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MAX 10 FPGAs– REVOLUTIONIZING NONVOLATILE INTEGRATION
Family Overview
Device Family Details
Altera’s MAX® 10 FPGAs revolutionize non-volatile integration by delivering advanced processing capabilities in a
low-cost, single chip small form factor programmable logic device. Building upon the single chip heritage of previous
MAX device families, densities range from 2K – 50KLE, using either single or dual power supplies. The MAX 10 FPGA
family encompasses both small packaging and high I/O pin count packages.
MAX 10 FPGAs are built on TSMC’s 55 nm embedded NOR ash technology, enabling instant-on functionality. MAX 10
FPGAs include integrated analog-to-digital converters (ADCs) and dual conguration ash allowing you to store and
dynamically switch between two images on a single chip. Unlike CPLDs, MAX10 FPGAs also include full featured FPGA
capabilities such as Nios® II soft core embedded processor support, DSP blocks, and soft DDR3 memory controllers.
For Industrial and Automotive systems, the MAX 10 FPGA single-chip integration, including Nios II processor support,
provide a reduced footprint with increased design security and product reliability while lowering system cost.
For control applications in computing, consumer, communications, and other markets, MAX 10 FPGAs ADC functionality
allows integration of power-up sequencing and system control circuitry into a single device. The software-based
system management using the Nios II processor further enhances board management integration in an advanced,
reliable system controller.
The features highlighted in the gure below enable system simplication, increased capabilities, and single-chip
integration benets.
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MAX 10 FPGAs– REVOLUTIONIZING NONVOLATILE INTEGRATION
Key Features
• Up to 50,000 logic elements (LEs)
• Maximum of 500 user I/O pins
• Non-volatile instant-on architecture
• Single chip
• Embedded SRAM
• High-performance phase-locked loops (PLLs)
• External memory interface (DDR3 SDRAM/DDR3L SDRAM/DDR2 SDRAM/LPDDR2)
• Nios II embedded processor support
• DSP blocks
• 3.3 V, LVDS, PCI™, and 30+ other I/O standards supported
• Embedded ADCs – 12 bit 1 Msps
- Up to 18 analog input channels
- Temperature sensor
• Single or dual-core voltage supply oering
• Embedded ash
- Dual conguration ash
- User ash memory
• Internal oscillator
• Power Saving Features
- Sleep mode to reduce dynamic power by up to 95%
- Input buer power-down
• 128 bit Advanced Encryption Standard (AES) design security
• RoHS6 packaging
MAX 10 FPGAs– REVOLUTIONIZING NONVOLATILE INTEGRATION
Qualication and Certication
MAX 10 FPGAs are available in Commercial, Industrial, and Automotive (AEC-Q100) temperature grades. In addition, they
will be supported in a future release of the functional safety pack, TUV Certied to IEC 61508 and ISO 26262, reducing
development time and time to market.
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MAX 10 FPGAs Product Table
Notes:
1. Additional user ash may be available, depending on conguration options.
2. The number of PLLs available is dependent on the package option.
3. Availability of the ADC or TSD varies by package type. Smaller pin-count packages
do not have access to the ADC hard IP.
4. SRAM only.
5. SRAM, DDR3 SDRAM, DDR2 SDRAM, or LPDDR2.
6. “D” = Dual power supply (1.2 V/2.5 V), “S” = Single power supply (3.3 V or 3.0 V).
7. V81 package does not support analog feature set. 10M08 V81 F devices support
dual image with RSU.
8. “Easy PCB” utilizes 0.8 mm PCB design rules.
9. All data is correct at the time of printing, and may be subject to change without
prior notice. For the latest information, please visit www.altera.com.
Product Line 10M02 10M04 10M08 10M16 10M25 10M40 10M50
LEs (K) 2 4 8 16 25 40 50
Block memory (Kb) 108 189 378 549 675 1,260 1,638
User flash memory1 (KB) 12 16 – 156 32 – 172 32 – 296 32 – 400 64 – 736 64 – 736
18 x 18 multipliers 16 20 24 45 55 125 144
PLLs21, 2 1, 2 1, 2 1, 4 1, 4 1, 4 1, 4
Internal configuration Single Dual Dual Dual Dual Dual Dual
Analog-to-digital converter (ADC),
temperature sensing diode (TSD)3-1, 1 1, 1 1, 1 2, 1 2, 1 2, 1
External memory interface (EMIF) Yes4Yes4Yes4Yes5 Yes5Yes5Yes5
Package Options and I/O Pins: Feature Set Options, GPIO, True LVDS Transceiver/Receiver
V36 (D)6WLCSP
(3 mm, 0.4 mm pitch) C, 27, 3/7 – – – – – –
V81 (D)7WLCSP
(4 mm, 0.4 mm pitch) – – C/F, 56, 7/17 – – – –
F256 (D) FBGA
(17 mm, 1.0 mm pitch)
– C/A, 178, 13/54 C/A, 178, 13/54 C/A, 178, 13/54 C/A, 178, 13/54 C/A, 178, 13/54 C/A, 178, 13/54
U324 (D) UBGA
(15 mm, 0.8 mm pitch)
C, 160, 9/47 C/A, 246, 15/81 C/A, 246, 15/81 C/A, 246, 15/81 – – –
F484 (D) FBGA
(23 mm, 1.0 mm pitch)
– – C/A, 250, 15/83 C/A, 320, 22/116 C/A, 360, 24/136 C/A, 360, 24/136 C/A, 360, 24/136
F672 (D) FBGA
(27 mm, 1.0 mm pitch)
– – – – – C/A, 500, 30/192 C/A, 500, 30/192
E144 (S)6EQFP
(22 mm, 0.5 mm pitch)
C, 101, 7/27 C/A, 101, 10/27 C/A, 101, 10/27 C/A, 101, 10/27 C/A, 101, 10/27 C/A, 101, 10/28 C/A, 101, 10/28
M153 (S) MBGA
(8 mm, 0.5 mm pitch)8
C, 112, 9/29 C/A, 112, 9/29 C/A, 112, 9/29 – – – –
U169 (S) UBGA
(11 mm, 0.8 mm pitch)
C, 130, 9/38 C/A, 130, 9/38 C/A, 130, 9/38 C/A, 130, 9/38 – – –
Indicates feature set options, GPIO count, and LVDS
transmitter or receiver count. Feature set options:
C = Compact (single image), F = Flash (dual image with RSU),
A = Analog (analog features block).
Each has added premiums.
Indicates pin migration.
C, 27, 3/7
MAX 10 FPGAs– REVOLUTIONIZING NONVOLATILE INTEGRATION
Market Solutions
MAX 10 FPGAs serve many end market segments and enable a wide variety of applications.
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Automotive Infotainment
Industrial Motor Control
40MHz / 280 Mbps x4
(1.12 Gbps)
10MO2D
10M04D
1.2V / 2.5V and VDDIO
4D+C LVDS
Open LDI
OpenLDI
Video and Image
Processing Suite
CFIG GPIO Safety
TCON
Logic
miniLVDS
12D+2C
miniLVDS
LCD
960 x 540p60
Video
Source
GPU / SoC
RGB
• I/O support exibility - LVDS inputs, mini-LVDS outputs, and LVCMOS general-purpose input and output pins (GPIOs)
• Altera® intellectual property (IP) - ALTLVDS megafuction and Video and Image Processing Suite
• MAX 10 FPGA integration - Granular family oering to meet unique design needs and on-chip ash for reduced BOM
• Higher-performance - High control loop update for high-speed motors and direct non-PWM control with parallel
processing for precise timing
• Greater exibility - High I/O counts, internal ADC, custom IP, and tailored resource usage to meet performance
requirements
• Lower cost of ownership - Lower part count brings long design lifetime, matched by Altera’s long supply
lifetime
Memory
PHY
Soft
Processor DSP
FLASH ADC
Industrial
Ethernet
Encoder
Interface
I/O Safety IP
Safety
Device
Power
Stage
High Speed
Digital Encoder
Motors
MAX 10 FPGAs– REVOLUTIONIZING NONVOLATILE INTEGRATION
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System Management Applications
• System management – Power-up sequencing, temperature measurement
• Interface bridging – Translate bus protocol and voltages between incompatible devices
• I/O expansion – Increase the available I/O pins of standard devices
LED activity control
Control signal distribution
Bus protocol translation
Serial-to-Parallel data conversion
I/O Expansion Interface Bridging
Power-Up Sequencing
Multi-voltage system power-up management
Board swapping management
Device conguration
Flash controller
System Conguration
Low-Cost Development Kit Solutions
The MAX 10 FPGA evaluation and development kits feature Altera Enpirion® power products and PowerSoCs and can
be ordered on www.altera.com/max10 to get your next design up and running as quickly as possible.
With Arduino, PMOD and high-speed mezzanine card (HSMC) headers, both boards support a wealth of daughtercards
from 3rd party vendors, such as Arduino (www.arduino.cc), Terasic (www.terasic.com), and SLS (www.slscorp.com).
MAX 10 FPGAs– REVOLUTIONIZING NONVOLATILE INTEGRATION
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MAX 10 FPGA Evaluation Kits Enable Fast Evaluation and Prototyping
MAX 10 FPGA Development Kits Provide a Platform for System-Level Development
MAX 10 FPGA 10M08 Evaluation Kit
MAX 10 FPGA 10M50 Development Kit
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
USA
www.altera.com
Altera European Headquarters
Holmers Farm Way
High Wycombe
Buckinghamshire
HP12 4XF
United Kingdom
Telephone: (44) 1494 602000
Altera Japan Ltd.
Shinjuku i-Land Tower 32F
6-5-1, Nishi-Shinjuku
Shinjuku-ku, Tokyo 163-1332
Japan
Telephone: (81) 3 3340 9480
www.altera.co.jp
Altera International Ltd.
Unit 11-18, 9/F
Millennium City 1, Tower 1
388 Kwun Tong Road
Kwun Tong
Kowloon, Hong Kong
Telephone: (852) 2945 7000
©2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the
U.S. Patent and Trademark Oce and in other countries. All other words and logos identied as trademarks or service marks are the property of their respective holders as described at www.altera.com/legal.
March 2016 Broch-1013-1.4
Getting Started
Altera oers a range of design tools for MAX 10 FPGAs, including the free Quartus® Prime Design Software Web Edition,
the Nios II Embedded Design Suite, and a host of analysis tools, including the Analog Toolkit, optimized to help get your
design into production quickly.
MAX 10 FPGAs– REVOLUTIONIZING NONVOLATILE INTEGRATION
Design Tools
Powering MAX 10 FPGAs
Altera’s Enpirion portfolio of power management products oers a broad selection of solutions ideally suited for
powering the MAX 10 FPGA family. Together, Altera’s MAX 10 FPGA with Enpirion power solutions enables the
smallest, most reliable solution while minimizing cost and accelerating time to revenue. Designing a power tree for a
MAX 10 FPGA is easy with Altera’s suite of FPGA system design tools, such as Altera’s PowerPlay Early Power Estimator
tool, which seamlessly combines FPGA power consumption estimates with a recommended power tree with Enpirion
power solutions. For more details and design support for creating the optimal MAX 10 FPGA power tree, please visit
the Powering FPGAs Resource Center.
Get more details about our MAX 10 FPGA family by contacting your local Altera sales representative or FAE,
or by visiting www.altera.com/max10.
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10M25DCF256I7G 10M25DAF256I7G 10M25DCF484C7G 10M25DCF484I7G 10M25DAF256C7G
10M16DAF256I7G 10M40DCF256C7G 10M25SCE144A7G 10M25SCE144I7G 10M40DCF256C8G
10M16DAF256C8G 10M25SAE144C8G 10M25DCF484C8G 10M25SCE144C8G 10M25DCF256A7G
10M50DCF256A7G 10M16DCU324A7G 10M16SCE144A7G 10M16DCF256A7G 10M40DCF256I7G
10M16DAF256C7G 10M50SCE144A7G 10M25DAF484C7G 10M25DAF484I7G 10M25DCF256C7G
10M25DCF256C8G 10M16SCU169A7G 10M16SAU169C8G 10M08SAE144C8G 10M16SAE144C8G