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TDA7266D
May 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
WIDE SUPPL Y VOLTAG E RAN GE (3 .5 - 12V)
OUTP UT PO WER
5+5W @THD = 10%, RL = 8, VCC = 9.5V
SI NGLE SU PPL Y
MINIMUM EXTERNAL COMPONENTS
NO SVR CAPACIT O R
N O B OOTS TRAP
NO BOUCHEROT CELLS
INTERNALLY FIXED GAIN
STAND-BY & MUTE FUNCTIONS
SHORT CIRCUIT PROTECTION
THERMAL OVERLOAD PROTECTION
DESCRIPTION
The TDA7266D is a dual bridge amplifier specially
designed for LCD TV/Monitor, PC Motherboard, TV
and Portable Audio applications.
PowerSO20 Slug Down
ORDERING NUMBER: TDA7266D
PRELIMINARY DATA
5W+5W DUAL BRIDGE AMPLIFIER
TEST AND AP PLICATI ON CIRCUIT
2
5
7
Vref
ST-BY
JP1
9
IN1
C3 0.22µF
VCC
156
D02AU1407
+
-
-
+
OUT1+
OUT1-
19
16
14
MUTE 8
IN2
C5 0.22µF
+
-
-
+
OUT2+
OUT2-
20
13
S-GND
PW-GND
C1
470µFC2
100nF C7
100nF
1
10
11
C4
10µF
R1
47K
R2
47K
C6
1µF
R3 10K
R4 10K
+5V
TECHNOLOGY BI20II
TDA7266D
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ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
Notes: 1. See Application note AN668, available on WEB FR4 with 15 via holes and ground layer.
PIN CONNECTION
Symbol Parameter Value Unit
VsSupply Voltage 20 V
IOOutput Peak Current (internally limited) 1.5 A
Ptot Total Power Dissipation (Tamb = 70°C 25 W
Top Operating Temperature 0 to 70 °C
Tstg, TjStorage and Junction Temperature -40 to 150 °C
Symbol Parameter Value Unit
Rth j-case Thermal Resistance Junction-case 2.1 °C/W
Rth j-amb Thermal Resistance Junction-ambient (on recomended PCB) note1 15 °C/W
PW GND
ST BY N.C.
N.C.
N.C.
VCC
OUT1-
IN1
MUTE
OUT1+
PW GND 10
8
9
7
6
5
4
3
2
13
14
15
16
17
19
18
20
12
1
11 PW GND
D02AU1408
SGND
IN2-
OUT2-
VCC
N.C.
N.C.
OUT2+
PW GND
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TDA7266D
ELECTRICAL CHARACTERISTCS
(Refer to test circuit) V
CC
= 9.5V, R
L
= 8
, f = 1KHz, T
amb
= 25°C unless
otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
VCC Supply Range 3.5 9.5 12 V
IqTotal Quiescent Current 50 60 mA
VOS Output Offset Voltage 120 mV
POOutput Power THD 10% 4.3 5 W
THD Total Harmonic Distortion PO = 1W 0.05 0.2 %
PO = 0.1W to 2W
f = 100Hz to 15KHz 1%
SVR Supply Voltage Rejection f = 100Hz, VR =0.5V 40 56 dB
CT Crosstalk 46 60 dB
AMUTE Mute Attenuation 60 80 dB
TwThermal Threshold 150 °C
GVClosed Loop Voltage Gain 25 26 27 dB
GVVoltage Gain Matching 0.5 dB
RiInput Resis tance 25 30 K
VTMUTE Mute Threshold for VCC > 6.4V; Vo = -30dB 2.3 2.9 4.1 V
for VCC < 6.4V; Vo = -30dB VCC/2
-1 VCC/2
-0.75 VCC/2
-0.5 V
VTST-BY St-by Threshold 0.8 1.3 1.8 V
IST-BY St-by Current V6 = GND 100 µA
eNTotal Output Voltage A Curve 150 µV
TDA7266D
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APPLICATIVE SUGGESTIONS
STAND-BY AND MUTE FUNCTIONS
(A) Microprocessor Application
In order to avoid annoying "Pop-Noise" during Turn-On/Off transients, it is necessary to guarantee the right St-
by and mute signals sequence.It is quite simple to obtain this function using a microprocessor (Fig. 1 and 2).
At first St-by signal (from
µ
P) goes high and the voltage across the St-by terminal (Pin 9) starts to increase ex-
ponentially. The external RC network is intended to turn-on slowly the biasing circuits of the amplifier, this to
avoid "POP" and "CLICK" on the outputs.
When this voltage reaches the St-by threshold level, the amplifier is switched-on and the external capacitors in
series to the input terminals (C1, C3) start to charge.
It's necessary to mantain the mute signal low until the capacitors are fully charged, this to avoid that the device
goes in play mode causing a loud "Pop Noise" on the speakers.
A delay of 100-200ms between St-by and mute signals is suitable for a proper operation.
Figure 1. Micropr ocess or Applicati on
2
5
7
Vref
ST-BY 9
IN1
C1 0.22µF
VCC
156
D02AU1409
+
-
-
+
OUT1+
OUT1-
19
16
14
MUTE 8
IN2
C3 0.22µF
+
-
-
+
OUT2+
OUT2-
20
13
S-GND
PW-GND
C5
470µFC6
100nF
R1 10K
C2
10µF
µP
R2 10K
C4
1µF
1
10
11
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TDA7266D
Figure 2. Micro pr ocess or Drivin g Sig nals
B) Low Cost Application
In low cost applications where the mP is not present, the suggested circuit is shown in fig.3.
The St-by and mute ter minals are tied toget her and they are con nected to the supply line via an exter nal voltage
divider.
The device is switched-on/off from the supply line and the external capacitor C4 is intended to delay the St-by
and mute threshold exceeding, avoiding "Popping" problems.
So to avoid any popping or clicking sond, it is important to clock:
aCorrect Sequence: At turn-ON, the Stand-by m ust be removed a t first, then the Mut e must be re-
leased af ter a delay of abo ut 100-200m s. On the cont rary at t urn-OFF the M ute mu st be activated
as fir st and then the Stand-by.
With the values suggested in the Application circuit the right operation is guarant eed.
bCorrect Threshol d Vol tages: I n order t o av oid that due t o the spread in the int ernal thresholds (see
the above limits) a wrong e xternal vol tage caus es uncertain com mu tations f or the two func tions we
sugg est to use the following values:
Mute for Vcc>6.4V : VT = 2.3V
Mute for Vcc<6.4V : VT = Vcc/2 - 1
Stand-by : VT = 0.8V
+VS(V)
VIN
(mV)
VST-BY
pin 9
Iq
(mA)
ST-BY MUTE
PLAY MUTE ST-BY
+18
1.8
0.8
VMUTE
pin 8
4.1
2.3
OFF
OFF
D02AU1411
VOUT
(V)
2.9
1.3
TDA7266D
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Figure 3. Stand-alone low-cost Application
PCB Layout and External Components:
Regarding the PCB layout care must be taken for three main subjects:
c) Signal and Power Gnd separation
d) Dissipating Copper Area
e) Filter Capacitors positioning
)Signal and Power Gnd separation:
c To t he Signal GND must be referred the A udio Input Signals, the M ute and Stand-by Voltage s and
the device PIN.13. This Gnd path must be as clean as possible in order to improve the device
THD+Noi se and to avoid spurious oscillations across the speakers.
The Power GND is directly connected to the Output power Stage transistors (Emitters) and is crossed
by large amount of current, this path is also used in this device to dissipate the heating generated (no
needs of external heatsink er).
Referring to the typical application circuit, the separation between the two GND pa ths must be ob-
tained connecting them separat ely (star routing) to the bulk
Electrolithic capacitor C1 (470µF).
Regarding the Power Gnd dimens ioning we have to consider the Dissipated Power the Thermal Pro-
tection Threshold and the Package thermal Characteristics.
2
5
7
Vref
ST-BY 9
IN1
C3 0.22µF
VCC
156
D02AU1410
+
-
-
+
OUT1+
OUT1-
19
16
14
MUTE 8
IN2
C5 0.22µF
+
-
-
+
OUT2+
OUT2-
20
13
S-GND
PW-GND
C1
470µFC2
100nF C7
100nF
R1
47K
C4
10µF
R2
47K
1
10
11
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TDA7266D
d Dissipating Copper Area:
Dissipated Power:
The max dissipated power happe ns for a THD near 1% and is given by the formula:
This gives for: Vcc = 9.5V, Rl = 8
,Iq = 50mA a dissipated power of Pd = 5W.
Thermal Protection:
The thermal protection threshold is placed at a junction temperature of 150°C.
Package Thermal Characteristics:
The thermal resistance Junction to Ambient obtainable with a GND copper Area of 3x3 cm and with 16 via
holes (see picture) is about 15°C/W. This means that with the above mentioned max dissipated Power (Pd=5W)
we can expect a 75°C, this gives a safety margin before the thermal protection intervention in the consumer
environments where a 50°C ambient is specified as maximum
The Thermal constraints determine the max supply voltage that can be used for the different Load Impedances,
this in order to avoid the thermal Protection Intervention.
The max. dissipated powe r must be not i n exce ss of 5W , thi s at turns giv es the follow ing operating s upply volt-
ages:
e F ilter Capacitors Positioning:
The two Ceramic capac itors C2/C7 (100nF) must be placed as close as possible
respectively to the two Vcc pins ( 6 - 15) in order to avoid the possibiltiy of oscillations arising on the
output Au dio signals.
Package Informations:
You can find a complete description for the PowerSO package into the APPLICATION NOTE AN668 available
on web.
Here we want to focalize the attention only on the the Dissipating elements and ground layer.
Load (Ohm) Supply Voltage (V)
4 6.5
6 8.5
8 9.5
16 14
Pdmax W() 2
V
CC2
π2Rl
2
------
-------------- IqVCC
+=
TDA7266D
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Consideri ng the dis sipated power inv olved in the TDA7 266D applic ation that is in the range of 5W, as explained
in a previous section, we suggest via holes ( see fig. 4).
Using via holes a more direct thermal path is obtained from the slug to the ground layer.The number of vias is
chosen accordingly to the desired performance (in our demonstration board we use 15 vias).
In fig.4 is shown as an example the footprint to be used to create the vias.
Figure 4.
The above metioned mounting solution is enough to dissipate the power involved
In the most part of the application using the TDA7266D.
If necessary a further improvement in the Rth J-Ambient can be obtained as shown in fig.5 where the
PowerSO20 is soldered onto a via hole structure with a metal plate glued on the opposite side of the board.
Figure 5. Mounting on epoxy FR4 using via Holes for heat transfer and external metal plate
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TDA7266D
Figu re 6. Distorti on v s Frequ e ncy
Figu re 7. Gai n vs Frequ enc y
F i gure 8. M ute Att enuation vs Vp in.8
Figu re 9. S ta nd-B y atten ua ti on vs Vpi n 9
Figure 10. Quie scent Cur rent vs Supply Voltage
Figure 11. Total Power Dissipation & Efficiency
vs Pout
0.010
0.1
1
10
100 1k 10k 20k
THD(%)
Vcc = 9.5 V
Rl = 8 ohm
Pout = 100mW
Pout = 2W
frequency (Hz)
-5.000
-4.000
-3.000
-2.000
-1.000
0.0
1.0000
2.0000
3.0000
4.0000
5.0000
10 100 1k 10k 100k
Level(dBr)
Vcc = 9.5V
Rl = 8 ohm
Pout = 1W
frequency (Hz)
11.522.533.544.55
0
10
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
Attenuation (dB)
Vpin.6(V)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
0
10
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
A tten u atio n (d B )
V pin .7 ( V )
3456789101112
30
35
40
45
50
55
60
65
70 Iq (m A)
Vsupply(V)
012345
0
1
2
3
4
5
6
10
20
30
40
50
60
70
Pd(W) Eff(%)
2 X Pout (W)
Vcc= 9.5V
Rl = 8 ohm
f=1KHZ
2 C hannels
012345
0
1
2
3
4
5
6
10
20
30
40
50
60
70
Pd(W) Eff(%)
2 X Pout (W)
Vcc= 9.5V
Rl = 8 ohm
f=1KHZ
2 C hannels
TDA7266D
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Figure 12. THD+N vs Output Power Figure 13. THD+N vs Output Power
10
0.1
0.2
0.5
1
2
5
THD(%)
100m 6200m 300m 500m700m 1 2 3 4 5
Pout(W)
Vcc=9.5V
Rl=8ohm
f=1KHz
10
0.1
0.2
0.5
1
2
5
THD(%)
100m 6200m 300m 500m700m 1 2 3 4 5
Pout(W)
Vcc=9.5V
Rl=8ohm
f=1KHz
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD(%)
100m 5200m 300m 500m 700m 1 2 3 4
Pout(W)
Vcc=12V
Rl=16 ohm
f = 1KHz
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD(%)
100m 5200m 300m 500m 700m 1 2 3 4
Pout(W)
Vcc=12V
Rl=16 ohm
f = 1KHz
Figure 14. PC Board Component Layout
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TDA7266D
Figure 15. Evaluation Board Top Layer Layout
Figure 16. Evaluation Board Bottom Layer Layout
TDA7266D
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OUT LINE AND
M E CHANICA L DA TA
e
a2 A
Ea1
PSO20MEC
DETAIL A
T
D
110
1120
E1
E2
h x 45
DETAIL A
lead
slug
a3
S
Gage Plane 0.35
L
DETAIL B
R
DETAIL B
(COPLANARITY)
GC
- C -
SEATING PLANE
e3
b
c
NN
H
BO TTOM VIEW
E3
D1
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.6 0.142
a1 0.1 0.3 0.004 0.012
a2 3.3 0.130
a3 0 0.1 0.000 0.004
b 0.4 0.53 0.016 0.021
c 0.23 0.32 0.009 0.013
D (1) 15.8 16 0.622 0.630
D1 9.4 9.8 0.370 0.386
E 13.9 14.5 0.547 0.570
e 1.27 0.050
e3 11.43 0.450
E1 (1) 10.9 11.1 0.429 0.437
E2 2.9 0.114
E3 5.8 6.2 0.228 0.244
G 0 0.1 0.000 0.004
H 15.5 15.9 0.610 0.626
h 1.1 0.043
L 0.8 1.1 0.031 0.043
N 8˚ (typ.)
S 8˚ (max.)
T 10 0.394
(1) “D and E1” do not include mold flash or protusions.
- Mo l d flash or protus io ns shal l not exceed 0. 15mm (0.006”)
- Critical dimen sions: “E”, “G” and “a3 ”.
PowerSO20
0056635
JEDEC MO-166
Weight:
1.9gr
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to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authoriz ed f or use as c ri t i cal compone nt s i n l i f e suppo rt device s or systems without express wri t ten approva l of STM i croel ectronics.
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TDA7266D