1
LT1713/LT1714
Single/Dual, 7ns, Low Power,
3V/5V/±5V Rail-to-Rail Comparators
The LT
®
1713/LT1714 are UltraFast
TM
7ns, single/dual
comparators featuring rail-to-rail inputs, rail-to-rail
complementary outputs and an output latch. Optimized
for 3V and 5V power supplies, they operate over a single
supply voltage range from 2.4V to 12V or from ±2.4V to
±6V dual supplies.
The LT1713/LT1714 are designed for ease of use in a
variety of systems. In addition to wide supply voltage
flexibility, rail-to-rail input common mode range extends
100mV beyond both supply rails and the outputs are
protected against phase reversal for inputs extending
further beyond the rails. Also, the rail-to-rail inputs may be
taken to opposite rails with no significant increase in input
current. The rail-to-rail matched complementary outputs
interface directly to TTL or CMOS logic and can sink 10mA
to within 0.5V of GND or source 10mA to within 0.7V of V
+
.
The LT1713/LT1714 have internal TTL/CMOS compatible
latches for retaining data at the outputs. Each latch holds
data as long as its latch pin is held high. Latch pin
hysteresis provides protection against slow moving or
noisy latch signals. The LT1713 is available in the 8-lead
MSOP package. The LT1714 is available in the 16-lead
narrow SSOP package.
■
Ultrafast: 7ns at 20mV Overdrive
8.5ns at 5mV Overdrive
■
Rail-to-Rail Inputs
■
Rail-to-Rail Complementary Outputs
(TTL/CMOS Compatible)
■
Specified at 2.7V, 5V and ±5V Supplies
■
Low Power (Per Comparator): 5mA
■
Output Latch
■
Inputs Can Exceed Supplies Without Phase Reversal
■
LT1713: 8-Lead MSOP Package
■
LT1714: 16-Lead Narrow SSOP Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
High Speed Automatic Test Equipment
■
Current Sense for Switching Regulators
■
Crystal Oscillator Circuits
■
High Speed Sampling Circuits
■
High Speed A/D Converters
■
Pulse Width Modulators
■
Window Comparators
■
Extended Range V/F Converters
■
Fast Pulse Height/Width Discriminators
■
Line Receivers
■
High Speed Triggers UltraFast is a trademark of Linear Technology Corporation.
LT1713/LT1714 Propagation Delay
vs Input Overdrive
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
A 4× NTSC Subcarrier Voltage-Tunable Crystal Oscillator
171314 TA01
–
+
LT1713
5V
390Ω
200pF * 1% FILM RESISTOR
** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz
5V
FREQUENCY
OUTPUT
3.9k* V
IN
0V TO 5V
1M
MV-209
VARACTOR
DIODE
2k
2k
100pF
15pFY1** 100pF
0.047µF
C SELECT
(CHOOSE FOR CORRECT
PLL LOOP RESPONSE)
1M
1M 1M*
1N4148 LT1004-2.5
47k*
1k*
INPUT OVERDRIVE (mV)
0
PROPAGATION DELAY (ns)
6.5
7.0
7.5
t
PD+
t
PD–
30 50
171314 TA02
6.0
5.5
5.0 10 20 40
8.0
8.5
9.0
60
T
A
= 25°C
V
+
= 5V
V
–
= 0V
V
STEP
= 100mV
2
LT1713/LT1714
Supply Voltage
V
+
to V
–
............................................................ 12.6V
V
+
to GND ........................................................ 12.6V
V
–
to GND .............................................–10V to 0.3V
Differential Input Voltage ................................... ±12.6V
Latch Pin Voltage...................................................... 7V
Input and Latch Current..................................... ±10mA
ORDER PART
NUMBER
LT1714CGN
LT1714IGN
T
JMAX
= 150°C, θ
JA
= 120°C/W
PACKAGE/ORDER I FOR ATIO
UU
W
GN PART MARKING
1714
1714I
ABSOLUTE AXI U RATI GS
WWWU
(Note 1)
Output Current (Continuous) ..............................±20mA
Operating Temperature Range ................ –40°C to 85°C
Specified Temperature Range (Note 2)... –40°C to 85°C
Junction Temperature.......................................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
ORDER PART
NUMBER
LT1713CMS8
LT1713IMS8
MS8 PART MARKING
LTRD
LTUK
Consult factory for parts specified with wider operating temperature ranges.
T
JMAX
= 150°C, θ
JA
= 250°C/W
1
2
3
4
V
+
+IN
–IN
V
–
8
7
6
5
Q OUT
Q OUT
GND
LATCH
ENABLE
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
–IN A
+IN A
V
–
V
+
V
+
V
–
+IN B
–IN B
GND
Q A
Q A
Q B
Q B
GND
LATCH
ENABLE B
LATCH
ENABLE A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
+
Positive Supply Voltage Range ●2.4 7 V
V
OS
Input Offset Voltage (Note 4) R
S
= 50Ω, V
CM
= V
+
/2 0.5 4 mV
R
S
= 50Ω, V
CM
= V
+
/2 (Note 11) ●5mV
R
S
= 50Ω, V
CM
= 0V 0.7 mV
R
S
= 50Ω, V
CM
= V
+
1mV
∆V
OS
/∆T Input Offset Voltage Drift ●5µV/°C
I
OS
Input Offset Current 0.1 1 µA
●2µA
I
B
Input Bias Current (Note 5) –7 –1.5 2 µA
●–15 5 µA
V
CM
Input Voltage Range (Note 9) ●–0.1 V
+
+ 0.1 V
CMRR Common Mode Rejection Ratio V
+
= 5V, 0V ≤ V
CM
≤ 5V 60 70 dB
V
+
= 5V, 0V ≤ V
CM
≤ 5V ●58 dB
V
+
= 2.7V, 0V ≤ V
CM
≤ 2.7V 57 70 dB
V
+
= 2.7V, 0V ≤ V
CM
≤ 2.7V ●55 dB
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
ELECTRICAL CHARACTERISTICS
3
LT1713/LT1714
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR
+
Positive Power Supply Rejection Ratio 2.4V ≤ V
+
≤ 7V, V
CM
= 0V 65 80 dB
●60 dB
PSRR
–
Negative Power Supply Rejection Ratio –7V ≤ V
–
≤ 0V, V
+
= 5V, V
CM
= 5V 65 80 dB
●60 dB
A
V
Small-Signal Voltage Gain (Note 10) 1.5 3 V/mV
V
OH
Output Voltage Swing HIGH I
OUT
= 1mA, V
+
= 5V, V
OVERDRIVE
= 50mV ●V
+
– 0.5 V
+
– 0.2 V
I
OUT
= 10mA, V
+
= 5V, V
OVERDRIVE
= 50mV ●V
+
– 0.7 V
+
– 0.4 V
V
OL
Output Voltage Swing LOW I
OUT
= –1mA, V
OVERDRIVE
= 50mV ●0.20 0.4 V
I
OUT
= –10mA, V
OVERDRIVE
= 50mV ●0.35 0.5 V
I
+
Positive Supply Current (Per Comparator) V
+
= 5V, V
OVERDRIVE
= 1V 5 6.5 mA
●8.0 mA
I
–
Negative Supply Current (Per Comparator) V
+
= 5V, V
OVERDRIVE
= 1V 3 4.0 mA
●4.5 mA
V
IH
Latch Pin High Input Voltage ●2.4 V
V
IL
Latch Pin Low Input Voltage ●0.8 V
I
IL
Latch Pin Current V
LATCH
= V
+
●10 µA
t
PD
Propagation Delay (Note 6) ∆V
IN
= 100mV, V
OVERDRIVE
= 20mV 8.0 11.0 ns
∆V
IN
= 100mV, V
OVERDRIVE
= 20mV ●12.5 ns
∆V
IN
= 100mV, V
OVERDRIVE
= 5mV 9.0 ns
∆t
PD
Differential Propagation Delay (Note 6) ∆V
IN
= 100mV, V
OVERDRIVE
= 20mV 0.5 3 ns
t
r
Output Rise Time 10% to 90% 4 ns
t
f
Output Fall Time 90% to 10% 4 ns
t
LPD
Latch Propagation Delay (Note 7) 8ns
t
SU
Latch Setup Time (Note 7) 1.5 ns
t
H
Latch Hold Time (Note 7) 0ns
t
DPW
Minimum Latch Disable Pulse Width (Note 7) 8 ns
f
MAX
Maximum Toggle Frequency V
IN
= 100mV
P-P
Sine Wave 65 MHz
t
JITTER
Output Timing Jitter V
IN
= 630mV
P-P
(0dBm) Sine Wave, f = 30MHz 15 ps
RMS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = –5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
+
Positive Supply Voltage Range ●2.4 7 V
V
–
Negative Supply Voltage Range (Note 3) ●–7 0 V
V
OS
Input Offset Voltage (Note 4) R
S
= 50Ω, V
CM
= 0V 0.5 3 mV
R
S
= 50Ω, V
CM
= 0V ●4mV
R
S
= 50Ω, V
CM
= –5V 0.7 mV
R
S
= 50Ω, V
CM
= 5V 1 mV
∆V
OS
/∆T Input Offset Voltage Drift ●5µV/°C
I
OS
Input Offset Current 0.1 1 µA
●2µA
I
B
Input Bias Current (Note 5) –7 –1.5 2 µA
●–15 5 µA
4
LT1713/LT1714
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CM
Input Voltage Range ●–5.1 5.1 V
CMRR Common Mode Rejection Ratio –5V ≤ V
CM
≤ 5V 62 70 dB
●60 dB
PSRR
+
Positive Power Supply Rejection Ratio 2.4V ≤ V
+
≤ 7V, V
CM
= –5V 68 80 dB
●65 dB
PSRR
–
Negative Power Supply Rejection Ratio –7V ≤ V
–
≤ 0V, V
CM
= 5V 65 80 dB
●60 dB
A
V
Small-Signal Voltage Gain (Note 10) 1V ≤ V
OUT
≤ 4V, R
L
= ∞1.5 3 V/mV
V
OH
Output Voltage Swing HIGH (Note 8) I
OUT
= 1mA, V
OVERDRIVE
= 50mV ●4.5 4.8 V
I
OUT
= 10mA, V
OVERDRIVE
= 50mV ●4.3 4.6 V
V
OL
Output Voltage Swing LOW (Note 8) I
OUT
= –1mA, V
OVERDRIVE
= 50mV ●0.20 0.4 V
I
OUT
= –10mA, V
OVERDRIVE
= 50mV ●0.35 0.5 V
I
+
Positive Supply Current (Per Comparator) V
OVERDRIVE
= 1V 5.5 7.5 mA
●9.0 mA
I
–
Negative Supply Current (Per Comparator) V
OVERDRIVE
= 1V 3.5 4.5 mA
●5.0 mA
V
IH
Latch Pin High Input Voltage ●2.4 V
V
IL
Latch Pin Low Input Voltage ●0.8 V
I
IL
Latch Pin Current V
LATCH
= V
+
●10 µA
t
PD
Propagation Delay (Note 6) ∆V
IN
= 100mV, V
OVERDRIVE
= 20mV 7 10 ns
∆V
IN
= 100mV, V
OVERDRIVE
= 20mV ●12 ns
∆V
IN
= 100mV, V
OVERDRIVE
= 5mV 8.5 ns
∆t
PD
Differential Propagation Delay (Note 6) ∆V
IN
= 100mV, V
OVERDRIVE
= 20mV 0.5 3 ns
t
r
Output Rise Time 10% to 90% 4 ns
t
f
Output Fall Time 90% to 10% 4 ns
t
LPD
Latch Propagation Delay (Note 7) 8ns
t
SU
Latch Setup Time (Note 7) 1.5 ns
t
H
Latch Hold Time (Note 7) 0ns
t
DPW
Minimum Latch Disable Pulse Width (Note 7) 8 ns
f
MAX
Maximum Toggle Frequency V
IN
= 100mV
P-P
Sine Wave 65 MHz
t
JITTER
Output Timing Jitter V
IN
= 630mV
P-P
(0dBm) Sine Wave, f = 30MHz 15 ps
RMS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = –5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1713C/LT1714C are guaranteed to meet specified
performance from 0°C to 70°C. They are designed, characterized and
expected to meet specified performance from –40°C to 85°C but are not
tested or QA sampled at these temperatures. The LT1713I/LT1714I are
guaranteed to meet specified performance from –40°C to 85°C.
Note 3: The negative supply should not be greater than the ground pin
voltages and the maximum voltage across the positive and negative
supplies should not be greater than 12V.
Note 4: Input offset voltage (V
OS
) is defined as the average of the two
voltages measured by forcing first one output, then the other to V
+
/2.
Note 5: Input bias current (I
B
) is defined as the average of the two input
currents.
Note 6: Propagation delay (t
PD
) is measured with the overdrive added to
the actual V
OS
. Differential propagation delay is defined as:
∆t
PD
= t
PD+
– t
PD–
. Load capacitance is 10pF. Due to test system
requirements, the LT1713/LT1714 propagation delay is specified with a
1kΩ load to ground for ±5V supplies, or to mid-supply for 2.7V or 5V
single supplies.
Note 7: Latch propagation delay (t
LPD
) is the delay time for the output to
respond when the latch pin is deasserted. Latch setup time (t
SU
) is the
interval in which the input signal must remain stable prior to asserting the
latch signal. Latch hold time (t
H
) is the interval after the latch is asserted in
which the input signal must remain stable. Latch disable pulse width
(t
DPW
) is the width of the negative pulse on the latch enable pin that
latches in new data on the data inputs.
5
LT1713/LT1714
Note 8: Output voltage swings are characterized and tested at V
+
= 5V and
V
–
= 0V. They are designed and expected to meet these same
specifications at V
–
= –5V.
Note 9: The input voltage range is tested under the more demanding
conditions of V
+
= 5V and V
–
= –5V. The LT1713/LT1714 are designed
and expected to meet these specifications at V
–
= 0V.
ELECTRICAL CHARACTERISTICS
Note 10: The LT1713/LT1714 voltage gain is tested at V
+
= 5V and
V
–
= –5V only. Voltage gain at single supply V
+
= 5V and V
+
= 2.7V is
guaranteed by design and correlation.
Note 11: Input offset voltage over temperature at V
+
= 2.7V is guaranteed
by design and characterization.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Propagation Delay
vs Load Capacitance
Input Offset Voltage
vs Temperature
TEMPERATURE (°C)
–50
INPUT OFFSET VOLTAGE (mV)
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5 050 75
171314 G01
–25 25 100 125
V
+
= 5V
V
–
= 0V
V
CM
= 2.5V
LOAD CAPACITANCE (pF)
0 60 100
171314 G02
20
14
12
10
8
t
PD+
6
4
2
040 80 120
PROPAGATION DELAY (ns)
t
PD–
T
A
= 25°C
V
+
= 5V
V
–
= 0V
V
CM
= 2.5V
V
OD
= 20mV
V
STEP
= 100mV
TEMPERATURE (°C)
–50
PROPAGATION DELAY (ns)
100
171314 G03
050
16
14
12
10
8
6
4
2
0–25 25 75 125
t
PD+
t
PD
–
V
+
= 5V
V
–
= 0V
V
CM
= 2.5V
V
OD
= 20mV
V
STEP
= 100mV
C
LOAD
= 10pF
Propagation Delay
vs Input Common Mode Voltage Propagation Delay
vs Positive Supply Voltage Positive Supply Current
vs Positive Supply Voltage
Propagation Delay
vs Temperature
INPUT COMMON MODE (V)
–0.5
PROPAGATION DELAY (ns)
7.5
8.0 t
PD+
t
PD–
8.5
2.5 4.5
171314 G04
7.0
6.5
6.0 0.5 1.5 3.5
9.0
9.5
10.0
5.5
T
A
= 25°C
V
+
= 5V
V
–
= 0V
V
OD
= 20mV
V
STEP
= 100mV
C
LOAD
= 10pF
POSITIVE SUPPLY VOLTAGE (V)
0
PROPAGATION DELAY (ns)
9.5
6
171314 G05
8.0
7.0
24 8
6.5
6.0
10.0
9.0
8.5
7.5
10 12 14
t
PD–
T
A
= 25°C
V
–
= 0V
V
CM
= 2.5V
V
OD
= 20mV
V
STEP
= 100mV
C
LOAD
= 10pF t
PD+
POSITIVE SUPPLY VOLTAGE (V)
2
4.0
POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA)
4.5
5.0
5.5
6.0
7.0
46810
171314 G06
12
6.5
V
–
= –5V
V
–
= 0V
T
A
= 25°C
∆V
IN
= 100mV
I
OUT
= 0
6
LT1713/LT1714
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Negative Supply Current
vs Negative Supply Voltage
Positive Supply Current
vs Switching Frequency
SWITCHING FREQUENCY (MHz)
0
POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA)
20
25
30
40
171314 G07
15
10
010 20 30
5
40
35
TA = 25°C
V+ = 5V
V– = 0V
CLOAD = 10pF
NEGATIVE SUPPLY VOLTAGE (V)
0
2.0
NEGATIVE SUPPLY CURRENT (PER COMPARATOR) (mA)
2.2
2.6
2.8
3.0
4.0
3.4
–2 –4 –5
171314 G08
2.4
3.6
3.8
3.2
–1 –3 –6 –7
T
A
= 25°C
∆V
IN
= 100mV
I
OUT
= 0
V
+
= 5V
V
+
= 2.7V
Input Bias Current
vs Input Common Mode Voltage
INPUT COMMON MODE VOLTAGE (V)
–1
–6
INPUT BIAS CURRENT (µA)
–5
–3
–2
–1
345
3
171314 G09
–4
1
026
0
1
2T
A
= 25°C
V
+
= 5V
V
–
= 0V
∆V
IN
= 0mV
Output High Voltage
vs Source Current
Input Bias Current
vs Temperature Output Low Voltage
vs Sink Current
TEMPERATURE (°C)
–50
INPUT BIAS CURRENT (µA)
100
171314 G10
050
0
–1
–2
–3
–4 –25 25 75 125
V
+
= 5V
V
–
= 0V
V
CM
= 2.5V
LOADING SOURCE CURRENT (mA)
0.01
4.0
OUTPUT VOLTAGE
(V)
4.1
4.3
4.4
4.5
5.0
4.7
1
171314 G11
4.2
4.8
4.9
4.6
0.1 10
T
A
= 25°C
V
+
= 5V
V
–
= 0V
∆V
IN
= 100mV
LOADING SINK CURRENT (mA)
0.01
0
OUTPUT VOLTAGE (V)
0.1
0.3
0.4
0.5
1.0
0.7
1
171314 G12
0.2
0.8
0.9
0.6
0.1 10
T
A
= 25°C
V
+
= 5V
V
–
= 0V
∆V
IN
= 100mV
Output Timing Jitter
vs Switching Frequency Output Rising Edge, 5V Supply Output Falling Edge, 5V Supply
V
IN
V
OUT
V
IN
V
OUT
FREQUENCY (MHz)
0
0
OUTPUT TIMING JITTER (ps
RMS
)
20
60
80
100
200
140
40
171314 G13
40
160
180
120
20 60 80
T
A
= 25°C
V
+
= 5V
V
–
= 0V
V
CM
= 2.5V
V
IN
= 630mV
P-P
(0dBm) SINE WAVE
171314 G14 171314 G15
7
LT1713/LT1714
UU
U
PI FU CTIO S
LT1713
V
+
(Pin 1): Positive Supply Voltage, Usually 5V.
+IN (Pin 2): Noninverting Input.
–IN (Pin 3): Inverting Input.
V
–
(Pin 4): Negative Supply Voltage, Usually 0V or –5V.
LATCH ENABLE (Pin 5): Latch Enable Input. With a logic
high the output is latched.
GND (Pin 6): Ground Supply Voltage, Usually 0V.
Q (Pin 7): Noninverting Output.
Q (Pin 8): Inverting Output.
LT1714
–IN A (Pin 1): Inverting Input of A Channel Comparator.
+IN A (Pin 2): Noninverting Input of A Channel
Comparator.
V
–
(Pins 3, 6): Negative Supply Voltage, Usually – 5V. Pins
3 and 6 should be connected together externally.
V
+
(Pins 4, 5): Positive Supply Voltage, Usually 5V. Pins
4 and 5 should be connected together externally.
+IN B (Pin 7): Noninverting Input of B Channel
Comparator.
–IN B (Pin 8): Inverting Input of B Channel Comparator.
LATCH ENABLE B (Pin 9):
Latch Enable Input of B Channel
Comparator. With a logic high, the B output is latched.
GND (Pin 10): Ground Supply Voltage of B Channel
Comparator, Usually 0V.
Q B (Pin 11): Noninverting Output of B Channel
Comparator.
Q B (Pin 12): Inverting Output of B Channel
Comparator.
Q A (Pin 13): Inverting Output of A Channel
Comparator.
Q A (Pin 14): Noninverting Output of A Channel
Comparator.
GND (Pin 15): Ground Supply Voltage of A Channel
Comparator, Usually 0V
LATCH ENABLE A (Pin 16): Latch Enable Input of A Chan-
nel Comparator. With a logic high, the A output is latched.
8
LT1713/LT1714
APPLICATIO S I FOR ATIO
WUUU
Common Mode Considerations
The LT1713/LT1714 are specified for a common mode
range of –5.1V to 5.1V on a ±5V supply, or a common
mode range of – 0.1V to 5.1V on a single 5V supply. A more
general consideration is that the common mode range is
from 100mV below the negative supply to 100mV above
the positive supply, independent of the actual supply volt-
age. The criteria for common mode limit is that the output
still responds correctly to a small differential input signal.
When either input signal falls outside the common mode
limit, the internal PN diode formed with the substrate can
turn on resulting in significant current flow through the
die. Schottky clamp diodes between the inputs and the
supply rails speed up recovery from excessive overdrive
conditions by preventing these substrate diodes from
turning on.
Input Bias Current
Input bias current is measured with the outputs held at
2.5V with a 5V supply voltage. As with any rail-to-rail
differential input stage, the LT1713/LT1714 bias current
flows into or out of the device depending upon the com-
mon mode level. The input circuit consists of an NPN pair
and a PNP pair. For inputs near the negative rail, the NPN
pair is inactive, and the input bias current flows out of the
device; for inputs near the positive rail, the PNP pair is
inactive, and these currents flow into the device. For inputs
far enough away from the supply rails, the input bias
current will be some combination of the NPN and PNP bias
currents. As the differential input voltage increases, the
input current of each pair will increase for one of the inputs
and decrease for the other input. Large differential input
voltages result in different input currents as the input
stage enters various regions of operation. To reduce the
influence of these changing input currents on system
operation, use a low source resistance.
Latch Pin Dynamics
The internal latches of the LT1713/LT1714 comparators
retain the input data (output latched) when their respective
latch pin goes high. The latch pin will float to a low state
when disconnected, but it is better to ground the latch
when a flow-through condition is desired. The latch pin is
designed to be driven with either a TTL or CMOS output.
It has built-in hysteresis of approximately 100mV, so that
slow moving or noisy input signals do not impact latch
performance. For the LT1714, if only one of the compara-
tors is being used at a given time, it is best to latch the
second comparator to avoid any possibility of interactions
between the two comparators in the same package.
High Speed Design Techniques
A substantial amount of design effort has made the
LT1713/LT1714 relatively easy to use. As with most high
speed comparators, careful attention to PC board layout
and design is important in order to prevent oscillations.
The most common problem involves power supply by-
passing which is necessary to maintain low supply im-
pedance. Resistance and inductance in supply wires and
PC traces can quickly build up to unacceptable levels,
thereby allowing the supply voltages to move as the
supply current changes. This movement of the supply
voltages will often result in improper operation. In addi-
tion, adjacent devices connected through an unbypassed
supply can interact with each other through the finite
supply impedances.
Bypass capacitors furnish a simple solution to this prob-
lem by providing a local reservoir of energy at the device,
thus keeping supply impedance low. Bypass capacitors
should be as close as possible to the LT1713/LT1714
supply pins. A good high frequency capacitor, such as a
0.1µF ceramic, is recommended in parallel with a larger
capacitor, such as a 4.7µF tantalum.
9
LT1713/LT1714
APPLICATIO S I FOR ATIO
WUUU
Poor trace routes and high source impedances are also
common sources of problems. Keep trace lengths as
short as possible and avoid running any output trace
adjacent to an input trace to prevent unnecessary cou-
pling. If output traces are longer than a few inches,
provide proper termination impedances (typically 100Ω
to 400Ω) to eliminate any reflections that may occur. Also
keep source impedances as low as possible, preferably
much less than 1kΩ.
The input and output traces should also be isolated from
one another. Power supply traces can be used to achieve
this isolation as shown in Figure 1, a typical topside layout
of the LT1713/LT1714 on a multilayer PC board. Shown is
the topside metal etch including traces, pin escape vias and
the land pads for a GN16 LT1713/LT1714 and its adjacent
X7R 0805 bypass capacitors. The V
+
, V
–
and GND traces
all shield the inputs from the outputs. Although the two V
–
pins are connected internally, they should be shorted to-
gether externally as well in order for both to function as
shields. The same is true for the two V
+
pins. The two GND
pins are not connected internally, but in most applications
they are both connected directly to the ground plane.
1714 F01
Figure 1. Typical LT1714 Topside Metal for Multilayer PCB Layout
10
LT1713/LT1714
Figure 2. Various Configurations for Introducing Hysteresis
–
+
50k
VIN
50Ω
Q
Q
V+ = 5V
V– = –5V
VHYST = 5mV
(ALL 3 CASES)
Q
Q
–
+
50k
VIN
VREF
50Ω
Q
Q
–
+
100k
100k
VIN+
VIN–
50Ω
50Ω
171314 F02
LT1713
LT1713 LT1713
Hysteresis
Another useful technique to avoid oscillations is to provide
positive feedback, also known as hysteresis, from the
output to the input. Increased levels of hysteresis, how-
ever, reduce the sensitivity of the device to input voltage
levels, so the amount of positive feedback should be
tailored to particular system requirements. The
LT1713/LT1714 are completely flexible regarding the ap-
plication of hysteresis, due to rail-to-rail inputs and the
complementary outputs. Specifically, feedback resistors
can be connected from one or both outputs to their
corresponding inputs without regard to common mode
considerations. Figure 2 shows several configurations.
APPLICATIO S I FOR ATIO
WUUU
11
LT1713/LT1714
TYPICAL APPLICATIO S
U
Simultaneous Full Duplex 75Mbaud Interface
with Only Two Wires
The circuit of Figure 3 shows a simple, fully bidirectional,
differential 2-wire interface that gives good results to
75Mbaud, using the LT1714. Eye diagrams under condi-
tions of unidirectional and bidirectional communication
are shown in Figures 4 and 5. Although not as pristine as
the unidirectional performance of Figure␣ 4, the perfor-
mance under simultaneous bidirectional operation is still
excellent. Because the LT1714 input voltage range ex-
tends 100mV beyond both supply rails, the circuit works
with a full ±3V (one whole V
S
up or down) of ground
potential difference.
The circuit works well with the resistor values shown, but
other sets of values can be used. The starting point is the
characteristic impedance, Z
O
, of the twisted-pair cable.
The input impedance of the resistive network should
match the characteristic impedance and is given by:
RR RRR
RRRR
IN O O
=+
++
[]
2123
2123
•• ||( )
•||( )
This comes out to 120Ω for the values shown. The
Thevenin equivalent source voltage is given by:
VV
RRR
RRR
R
RRRR
TH S
O
O
=+
++
++
[]
•(–)
()
••||( )
231
231
2123
–
+
1/2
LT1714
TxD
RxD
7
8
9
LE 6
5
49.9Ω
750k
750k
100k
100k
49.9Ω
2
1
15
3
16
13
14
3V
3V
4
11
12
R2A
2.55k
R3A
124ΩR
OA
140ΩR
OB
140Ω
R1B
499Ω
6-FEET
TWISTED PAIR
Z
O
≈ 120ΩR1D
499Ω
R1C
499Ω
R3B
124Ω
R2C
2.55k 3V
100k
5
11
2
1
12 610
9
8
7
171314 F03
14
315 16 13
4
TxD
RxD
3V
R3C
124Ω
R3D
124Ω
R2D
2.55k
R2B
2.55k
R1A
499Ω
10
–
+
1/2
LT1714
LE
–
+
750k
750k
49.9Ω
49.9Ω
100k
–
+
LE
1/2
LT1714
LE
1/2
LT1714
3V 3V
DIODES: BAV99
×4
Figure 3. 75Mbaud Full Duplex Interface on Two Wires
12
LT1713/LT1714
TYPICAL APPLICATIO S
U
Figure 4. Performance of Figure 3’s Circuit When
Operated Unidirectionally. Eye is Wide Open
171112 F04
Figure 5. Performance When Operated Simultaneous
Bidirectionally (Full Duplex). Crosstalk Appears as Noise.
Eye is Slightly Shut But Performance is Still Excellent
171112 F05
This amounts to an attenuation factor of 0.0978 with the
values shown. (The actual voltage on the lines will be cut
in half again due to the 120Ω Z
O
.) The reason this
attenuation factor is important is that it is the key to
deciding the ratio between the R2-R3 resistor divider in
the receiver path. This divider allows the receiver to reject
the large signal of the local transmitter and instead sense
the attenuated signal of the remote transmitter. Note that
in the above equations, R2 and R3 are not yet fully
determined because they only appear as a sum. This
allows the designer to now place an additional constraint
on their values. The R2-R3 divide ratio should be set to
equal half the attenuation factor mentioned above or:
R3/R2 = 1/2 • 0.0976
1
.
Having already designed R2 + R3 to be 2.653k (by allocat-
ing input impedance across R
O
, R1 and R2 + R3 to get the
requisite 120Ω), R2 and R3 then become 2529Ω and
123.5Ω respectively. The nearest 1% value for R2 is 2.55k
and that for R3 is 124Ω.
Voltage-Tunable Crystal Oscillator
The front page application is a variant of a basic crystal
oscillator that permits voltage tuning of the output fre-
quency. Such voltage-controlled crystal oscillators (VCXO)
are often employed where slight variation of a stable
carrier is required. This example is specifically intended to
provide a 4× NTSC sub-carrier tunable oscillator suitable
for phase locking.
The LT1713 is set up as a crystal oscillator. The varactor
diode is biased from the tuning input. The tuning network
is arranged so a 0V to 5V drive provides a reasonably
symmetric, broad tuning range around the 14.31818MHz
center frequency. The indicated selected capacitor sets
tuning bandwidth. It should be picked to complement loop
response in phase locking applications. Figure 6 is a plot
of tuning input voltage versus frequency deviation. Tuning
deviation from the 4× NTSC 14.31818MHz center fre-
quency exceeds ±240ppm for a 0V to 5V input.
1
Using the design value of R2 + R3 = 2.653k rather than the implementation value of 2.55k +
124Ω = 2.674k.
INPUT VOLTAGE (V)
0
FREQUENCY DEVIATION (kHz)
245
9
8
7
6
5
4
3
2
1
0
171112 F06
13
14.314.0MHz
14.31818MHz
14.3217MHz
Figure 6. Control Voltage vs Output Frequency for the First Page
Application Circuit. Tuning Deviation from Center Frequency
Exceeds ±240ppm
13
LT1713/LT1714
Figure 7. LT1713 Comparator is Configured as a Series Resonant Xtal Oscillator.
LT1806 Op Amp is Configured in a Q = 5 Bandpass with fC = 1MHz
3V/DIV
1V/DIV
1V/DIV
200ns/DIV
171112 F08
Figure 8. Oscillator Waveforms with VS = 3V. Top is Comparator Output. Middle is
Xtal Feedback to Pin 2 at LT1713 (Note the Glitches). Bottom is Buffered, Inverted
and Bandpass Filtered with a Q = 5 by LT1806
–
+
LT1713
2
3
6
LE
5
1
R1
1k V
S
V
S
V
S
7
8
SQUARE
171314 F07
SINE
R3
1k
C1
0.1µF
4
R2
1k
R4
210Ω
1
6
2
3
4
7
R8
2k
V
S
1MHz
AT-CUT
R9
2k
R7
15.8k
R10
1k
R6
162Ω
R5
6.49k
C5
100pF
C2
0.1µF
C3
100pF
C4
100pF
–
+
LT1806
1MHz Series Resonant Crystal Oscillator
with Square and Sinusoid Outputs
Figure 7 shows a classic 1MHz series resonant crystal
oscillator. At series resonance, the crystal is a low imped-
ance and the positive feedback connection is what brings
about oscillation at the series resonant frequency. The RC
feedback around the other path ensures that the circuit
does not find a stable DC operating point and refuse to
oscillate. The comparator output is a 1MHz square wave
(top trace of Figure 8) with jitter measured at better than
28ps
RMS
on a 5V supply and 40ps
RMS
on a 3V supply. At
Pin 2 of the comparator, on the other side of the crystal, is
a clean sine wave except for the presence of the small high
frequency glitch (middle trace of Figure 8). This glitch is
caused by the fast edge of the comparator output feeding
back through crystal capacitance. Amplitude stability of
the sine wave is maintained by the fact that the sine wave
is basically a filtered version of the square wave. Hence,
the usual amplitude control loops associated with sinusoi-
dal oscillators are not necessary.
2
The sine wave is filtered
and buffered by the fast, low noise LT1806 op amp. To
remove the glitch, the LT1806 is configured as a bandpass
filter with a Q of 5 and unity-gain center frequency of
1MHz, with its output shown as the bottom trace of
Figure␣ 8. Distortion was measured at – 70dBc and –60dBc
on the second and third harmonics, respectively.
2
Amplitude will be a linear function of comparator output swing, which is supply dependent
and therefore adjustable. The important difference here is that any added amplitude
stabilization or control loop will not be faced with the classical task of avoiding regions of
nonoscillation versus clipping.
TYPICAL APPLICATIO S
U
14
LT1713/LT1714
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
U
PACKAGE DESCRIPTIO
MSOP (MS8) 1100
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.021 ± 0.006
(0.53 ± 0.015)
0° – 6° TYP
SEATING
PLANE
0.007
(0.18)
0.043
(1.10)
MAX
0.009 – 0.015
(0.22 – 0.38) 0.005 ± 0.002
(0.13 ± 0.05)
0.034
(0.86)
REF
0.0256
(0.65)
BSC
12
34
0.193 ± 0.006
(4.90 ± 0.15)
8765
0.118 ± 0.004*
(3.00 ± 0.102)
0.118 ± 0.004**
(3.00 ± 0.102)
15
LT1713/LT1714
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
Dimensions in inches (millimeters) unless otherwise noted.
U
PACKAGE DESCRIPTIO
GN16 (SSOP) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
12
345678
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
16 15 14 13
0.189 – 0.196*
(4.801 – 4.978)
12 11 10 9
0.016 – 0.050
(0.406 – 1.270)
0.015 ± 0.004
(0.38 ± 0.10) × 45°
0° – 8° TYP
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
0.004 – 0.0098
(0.102 – 0.249)
0.0250
(0.635)
BSC
0.009
(0.229)
REF
U
TYPICAL APPLICATIO
Rail-to-Rail Pulse Width Modulator
Using the LT1714
Binary modulation schemes are used in order to improve
efficiency and reduce physical circuit size. They do this by
reducing the power dissipation in the output driver tran-
sistors. In a normal Class A or Class AB amplifier, voltage
drop and current flow exist simultaneously in the output
transistors and power losses proportional to V • I occur.
In a binary modulation scheme, the output transistors,
whether bipolar or FET, are switched hard-on and hard-off
so that voltage drops do not occur simultaneously with
current flow. The circuit of Figure 9 shows an example of
a binary modulation scheme, in this case pulse width
modulation.
The LT1809 is configured as an integrator in order to
generate nice linear rail-to-rail voltage ramps. The polarity
of the ramp is determined by the output of the LT1714’s
comparator A into R4. The heavy hysteresis of R1 around
the LT1714’s comparator A combined with the feedback of
the LT1809 force the devices to perpetually reverse each
other, resulting in a 1MHz triangle wave. This constitutes
the usual first half of any pulse width modulator, but the
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16
LT1713/LT1714
LINEAR TECHNOLOGY CORPO RATION 2000
171314f LT/TP 0501 4K • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
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LT1720/LT1721 Dual/Quad, 4.5ns, Single Supply Comparator Dual/Quad Version of the LT1719
forte of this particular implementation is that it is rail-to-
rail allowing a full-scale analog input. Once the triangle
wave is achieved, the remainder of the pulse width modu-
lator is easy, and is constituted by doing a simple compari-
son using the second half of the LT1714. The triangle wave
and the relatively slow moving analog signal (the one to be
modulated or to do the modulation, depending on how you
look at it) are fed into the inputs of comparator B, whose
output is then the PWM representation of the analog input
voltage. The higher the analog input voltage, the wider the
output pulse. The time averaged output level is thus
proportional to the analog input voltage. This binary
output can then be fed into power transistors with direct
control over motor or speaker winding current, for
U
TYPICAL APPLICATIO
–
+
A
1/2 LT1714
2
1
–
+
2
V
+
V
+
3
315 16
C2
0.01µFR6
1k
V
+
= 2.7V TO 7V
1MHz
TRIANGLE
WAVE
R5
1k
13
6
1
4
7
14
4
V
+
V
+
R1
26.1Ω
R4
499Ω
21Ω
1k 10k
1k
C1
500pF
R2
2k
R3
2k
–
+
B
1/2 LT1714
7
8
6910
171314 F09
12
11
5
V
+
C3
100pF
LT1809
C4
0.001µF
C5
0.01µFC6
0.001µF
ANALOG
INPUT
ANTIALIASING
FILTER
16kHz ANALOG FILTER
FOR LINEARITY MEASUREMENT
COMPLEMENTARY
1MHz PWM
OUTPUTS
Figure 9. Rail-to-Rail 1MHz Pulse Width Modulator
example, with their inherent lowpass characteristic. Care
must be taken to avoid cross conduction in the output
power transistors.
The linearity of the pulse width modulated signal can easily
be ascertained by putting a simple 2-pole RC filter at the
output (as shown in Figure 9). This demodulates the signal
which can then be viewed and compared with the original
input signal on an oscilloscope. Using a spectrum analyzer
and a 1kHz reference signal, this circuit’s distortion prod-
ucts were measured as better than –50dBc (0.3%) to
about 3.5V
P-P
, degrading to –30dBc (3%) as the circuit
clips at 5V
P-P
on a single 5V supply.
