PLL BUILDING BLOCK
MDS 663 A 4Revision 080701
Integrated C ircuit Systems ● 525 R ace Street, San Jose, CA 95126 ● tel (40 8) 295-9800 ● www.icst.com
PRELIMINARY INFORMATION
ICS663
AC Electrical Characteristics
VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C, CLOAD at CLK = 15 pF, unless stated otherwise
VDD = 5.0V ±10%, Ambient Temperature 0 to +70° C, CLOAD at CLK = 15 pF, unless stated otherwise
Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit.
External Components
The ICS663 requires a minimum number of external
components for proper operation. A decoupling
capacitor of 0. 01µF should be connected between
VDD and GND as close to the ICS663 as possible. A
series termination resistor of 33 Ω may be used at the
clock output.
Special considerations must be made in choosing loop
components C1 and C2:
1) The loop capacitors should be a low-leakage type to
avoid leakage-induced phase noise. For this reason,
DO NOT use any type of polarized or electrolytic
capacitors.
2) Microphonics (mechanical board vibration) can also
induce output phase noise when the loop bandwidth is
less than 1kHz. For this reason, ceramic capacitors
should have C0G or NP0 dielectric. Avoid high-K
dielectrics like Z5U and X7R. These and some other
ceramics have piezoelectric properties that convert
Parameter Symbol Conditions Min. Typ. Max. Units
Output Clock Frequency
(from pin CLK) fCLK SEL = 1 1 100 MHz
SEL = 0 0.25 25 MHz
Input Clock Frequency
(into pins REFIN or FBIN) fREF Note 1 8 MHz
Output Rise Time tOR 0.8 to 2.0V 1.2 2 ns
Output Fall Time tOF 2.0 to 0.8V 0.75 1.5 ns
Output Clock Duty Cycle tDC At VDD/2 40 50 60 %
Jitter, Absolute peak-to-peak tJ250 ps
VCO Gain KO200 MHz/V
Charge Pump Current Icp 2.5 µA
Parameter Symbol Conditions Min. Typ. Max. Units
Output Clock Frequency
(from pin CLK) fCLK SEL = 1 1 120 MHz
SEL = 0 0.25 30 MHz
Input Clock Frequency
(into pins REFIN or FBIN) fREF Note 1 8 MHz
Output Rise Time tOR 0.8 to 2.0V 0.5 1 ns
Output Fall Time tOF 2.0 to 0.8V 0.5 1 ns
Output Clock Duty Cycle tDC At VDD/2 45 50 55 %
Jitter, Absolute peak-to-peak tJ150 ps
VCO Gain KO200 MHz/V
Charge Pump Current Icp 2.5 µA