September 2006
A
Copyright © Alliance Memory. All rights reserved.
AS7C31025C
3.3V 128K X 8 CMOS SRAM (Center power and ground)
9/20/06, v. 1.0 Alliance Memory P. 1 of 9
®
Features
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10/12 ns address access time
- 5 ns output enable access time
• Low power consumption via ship deselect
• Easy memory expansion with
CE
,
OE
inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin, TSOP 2
• ESD protection ≥ 2000 volts
Logic block diagram
131,072 x 8
Array
(1,048,576)
Sense amp
Input buffer
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O7
OE
CE
WE
Address decoder
Address decoder
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
AS7C31025C
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A9
A8
A4
A5
A6
A7
A12
A11
A10
32-pin TSOP 2
AS7C31025C
AS7C31025C
9/20/06, v. 1.0 Alliance Memory P. 2 of 9
®
Functional description
The AS7C31025C is 3V a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x
8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10 ns with output enable access times (tOE) of 5 ns are ideal for high-performance
applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When
CE
is high the device enters standby mode. A write cycle is accomplished by asserting write enable (
WE
) and chip enable (
CE
). Data
on the input pins I/O0 throug h I/O7 is written on the rising edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus co ntention,
external devices should drive I/O pins only after outputs have been disabled with output enable (
OE
) or write enable (
WE
).
A read cycle is accomplished by asserting output enable (
OE
) and chip enable (
CE
), with write enable (
WE
) high. The chip drives I/O pins
with the data word ref erenced by the input address. When either chip enable or output en able is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL- compatible, and operation is from a single 3.3 V supp ly. The AS7C31025C is packaged in common
industry standard packages.
Absolute maximum ratings
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = don’t care, L = low, H = high.
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.50 +4.6 V
Voltage on any pin relative to GND Vt2 –0.50 VCC + 0.5 V
Power dissipation PD–1.25W
Storage temperature (plastic) Tstg –55 +125 o C
Ambient temperature with VCC applied Tbias –55 +125 o C
DC current into outputs (low) IOUT –50mA
CE WE OE
Data Mode
H X X High Z Standby (ISB, ISB1)
L H H High Z Output disable (ICC)
LHL D
OUT Read (ICC)
LLX D
IN Write (ICC)
AS7C31025C
9/20/06, v. 1.0 Alliance Memory P. 3 of 9
®
Recommended operating conditions
VIL min = –2.0V for pulse width less than 5ns, once per cycle.
VIH min = –VCC + 2.0V for pulse width less than 5ns, once per cycle.
DC operating characteristics (over the operating range)1
Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2
Parameter Symbol Min Nominal Max Unit
Supply voltage VCC 3.0 3.3 3.6 V
Input voltage VIH 2.0 – VCC + 0.3 V
VIL –0.5 – 0.8 V
Ambient operating temperature (Industrial) TA–40 – 85 o C
Parameter Sym Test conditions
AS7C31025C-10
UnitMin Max
Input leakage current | ILI | VCC = Max, VIN = GND to VCC –5μA
Output leakage current | ILO | VCC = Max, CE = VIH,
Vout = GND to VCC
–5μA
Operating power supply current ICC
VCC = Max
CE ≤ VIL, f = fMax,
IOUT = 0 mA
– 150 mA
Standby power supply current1
ISB
VCC = Max
CE ≥ VIH, f = fMax
–50
mA
ISB1
VCC = Max, CE ≥ VCC–0.2 V,
VIN ≤ 0.2 V or VIN ≥ VCC –0.2 V,
f = 0
–10 mA
Output voltage VOL IOL = 8 mA, VCC = Min –0.4V
VOH IOH = –4 mA, VCC = Min 2.4 – V
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A,
CE
,
WE
,
OE
VIN = 3dV 6 pF
I/O capacitance CI/O I/O VOUT = 3dV 7 pF
Note:
1. This parameter is guaranteed by device characterization, but is not production tested.
AS7C31025C
9/20/06, v. 1.0 Alliance Memory P. 4 of 9
®
Read cycle (over the operating range)3,9
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CE and OE controlled)3,6,8,9
Parameter Symbol
AS7C31025C-10
Unit NotesMin Max
Read cycle time tRC 12 - ns
Address access time tAA –12ns3
Chip enable (
CE
) access time tACE –12ns3
Output enable (
OE
) access time tOE –6ns
Output hold from address change tOH 4–ns5
CE
low to output in low Z tCLZ 4 – ns 4, 5
CE
high to output in high Z tCHZ 0 5 ns 4, 5
OE
low to output in low Z tOLZ 0 – ns 4, 5
OE
high to output in high Z tOHZ 0 5 ns 4, 5
Power up time tPU 0 – ns 4, 5
Power down time tPD –12ns4, 5
Undefined/don’t careFalling inputRising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
Data valid
t
RC1
CE
t
OHZ
AS7C31025C
9/20/06, v. 1.0 Alliance Memory P. 5 of 9
®
Write cycle (over the operating range)11
Write waveform 1 (WE controlled)10,11
Write waveform 2 (CE controlled)10,11
Parameter Symbol
AS7C31025C-10
Unit NotesMin Max
Write cycle time tWC 12 - ns
Chip enable (
CE
) to write end tCW 8–ns
Address setup to write end tAW 8–ns
Address setup time tAS 0–ns
Write pulse width tWP 8–ns
Write recovery time tWR 0–ns
Address hold from end of write tAH 0–ns
Data valid to write end tDW 6–ns
Data hold time tDH 0 – ns 4, 5
Write enable to output in high Z tWZ 0 5 ns 4, 5
Output active from write end tOW 3 – ns 4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
t
AW
Address
CE
WE
D
OUT
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
Data valid
D
IN
t
WR
AS7C31025C
9/20/06, v. 1.0 Alliance Memory P. 6 of 9
®
AC test conditions
Notes
1 During VCC power-up, a pull-up resistor to VCC on
CE
is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4t
CLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±200 mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6
WE
is high for read cycle.
7
CE
and
OE
are low for read cycle.
8 Address is valid prior to or coincident with
CE
transition low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
255
Ω
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 3 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
C
13
320
Ω
D
OUT
GND
+3.3 V
168
Ω
Thevenin equivalent:
D
OUT
+1.728 V
Figure B: 3.3 V Output load
10%
90%
10%
90%
GND
+3.0 V
Figure A: Input pu lse
3 ns
AS7C31025C
9/20/06, v. 1.0 Alliance Memory P. 7 of 9
®
Package dimensions
32-pin TSOP 2
NN/2+1
1N/2
D
E1 E
L
ac
ZD
cbA1
A
Seating plane
eD
E1
Pin 1
b
B
A1
A2 c
E
Seating
plane
E2
A
32-pin SOJ
300 mil/400 mil
Symbol
32-pin TSOP 2 (mm)
Min Max
A–1.20
A1 0.05 0.15
b0.3 0.52
C0.12 0.21
D20.82 21.08
E1 10.03 10.29
E11.56 11.96
e1.27 BSC
L0.40 0.60
ZD 0.95 REF.
α0° 5°
Symbol
32-pin SOJ
300 mil
32-pin SOJ
400 mil
Min Max Min Max
A0.128 0.145 0.132 0.146
A1 0.025 - 0.025 -
A2 0.095 0.105 0.105 0.115
B0.026 0.032 0.026 0.032
b0.016 0.020 0.015 0.020
c0.007 0.010 0.007 0.013
D0.820 0.830 0.820 0.830
E0.255 0.275 0.354 0.378
E1 0.295 0.305 0.395 0.405
E2 0.330 0.340 0.435 0.445
e0.050 BSC 0.050 BSC
AS7C31025C
9/20/06, v. 1.0 Alliance Memory P. 8 of 9
®
Ordering Codes
Part numbering system
Package Volt/Temperature 10 ns
300-mil SOJ 3.3V Industrial AS7C31025C-12TJIN
400-mil SOJ 3.3V Industrial AS7C31025C-12JIN
TSOP 2 3.3V Industrial AS7C31025C-10TIN
AS7C X102& –XX X X X
SRAM prefix
Voltage:
3 = 3.3 V
CMOS
Device
number Access time
Package:
TJ = SOJ 300 mil
J = SOJ 400 mil
T = TSOP2
Temperature range
I = industrial, -40°
C to 85° C
N = Lead Free Part
Alliance Memory, Inc.
551 Taylor Way, Suite #1
San Carlos, CA 94070 USA
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Momory
All Rights Reserved
Part Number: AS7C31025C
Document Version: v. 1.0
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-poi nt logo, our name and Inte lliwatt are trademarks or registered trademarks of
Alliance. All other brand and produc t names may be the trademarks of th eir respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any
time, without notice. If the produc t described herein is under development, significant changes to these specifications are possible. The information in
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claims arising from such use.
AS7C31025C
®
®
