LPC4357JET256,551 - NXP Semiconductors

1. General description

The LPC435X_3X_2X_1X are ARM Cortex-M4 based microcontrollers with Floating Point

Unit (FPU) for embedded applications which include an ARM Cortex-M0 coprocessor, up

to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of EEPROM memory, two

high-speed USB controllers, Ethernet, LCD, an external memory controller, a quad SPI

Flash Interface (SPIFI) that supports execute-in-place, advanced configurable perip herals

such as the State Configurable Timer (SCTimer/PWM) and the Serial General Purpose

I/O (SGPIO) interface, and multiple digital and analog peripherals. The

LPC435X_3X_2X_1X operate at CPU frequencie s of up to 204 MHz.

The ARM Cortex-M4 is a 32- bit core that of fer s system e nhancements such as low power

consumption, enhanced deb ug features, and a high level of support block integration. The

ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals, and

includes an internal prefetch unit that supports speculative branching. The ARM

Cortex-M4 supp or ts single-cy cle dig ital signal processing and SIMD instructions. A

hardware floating-point processor is integrated into the core.

The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core,

which is upward code- and tool-co mpatible with the Cortex- M4 core. It is ideal for handling

control or peripheral handling to free up the Cortex-M4 for real-time processing. The

Cortex-M0 coprocessor offers up to 204 MHz performance with a simple instruction set

and reduced code size. In LPC43xx, the Cortex-M0 coprocessor hardware multiply is

implemented as a 32-cycle iterative multiplier.

For additional documentation related to the LPC43xx part s, see Section 17.

2. Features and benefits

Cortex-M4 Proce sso r co re

ARM Cortex-M4 processor (version r0p1), running at frequencies of up to

204 MHz.

Built-in Memory Protection Unit (MPU) supporting eight regions.

Built-in Nested Vectored Interrupt Controller (NVIC).

Hardware floating-point unit.

Non-maskable Interrupt (NM I) inpu t.

JTAG and Ser ial Wire Debug (SWD), serial trace, eight bre akpoints, and fo ur watch

points.

Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.

System tick timer.

LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB

SRAM; Ethernet, two High-speed USB, LCD, EMC

Rev. 5.2 — 26 November 2015 Product data sheet

Product data sheet Rev. 5.2 — 26 November 2015 2 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

Cortex-M0 Proce sso r co re

ARM Cortex-M0 co-processor (version r0p0) capable of off-loading the main ARM

Cortex-M4 application processo r.

Running at frequencies of up to 204 MHz.

JTAG

Built-in NVIC.

On-chip memory

Up to 1 MB on-chip dual bank flash memory with flash accelerator.

16 kB on-chip EEPROM data memory.

136 kB SRAM for code and data use.

Multiple SRAM blocks with separate bus access. Two SRAM blocks can be

powered down individually.

64 kB ROM containing boot code and on-chip software drivers.

64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose

use.

Configurable digital peripherals

Serial GPIO (SGPIO) interface.

State Configurable Timer (SCTimer/PWM) subsystem on AHB.

Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and

outputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.

Serial interfaces

Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second.

10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time

stamping (IEEE 1588-2008 v2).

One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip high-speed PHY.

One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to external high-speed PHY.

USB interface electrical test software included in ROM USB stack.

One 550 UAR T with DMA support and full modem interface.

Three 550 USARTs with DMA and synchronous mode support and a smart card

interface conforming to ISO7816 specification. One USART with IrDA interface.

Up to two C_CAN 2.0B controllers with one channel each.

Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA

support.

One SPI controller.

One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O

pins conforming to the full I2C-bus specification. Supports data rates of up to

1Mbit/s.

One standar d I2C-bus interface with monitor mode and with standard I/O pins.

Two I2S interfaces, each with DMA support and with one input and one output.

Digital peripherals

External Memory Con tro ller (E MC ) su ppor tin g ex te rn al SRAM , ROM , NO R flash ,

and SDRAM devices.

Product data sheet Rev. 5.2 — 26 November 2015 3 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

LCD controller with DMA support and a programmable display resolution of up to

1024 H  768 V. Supports monochrome and color STN panels and TFT color

panels; supports 1/2/4 /8 bpp Color Look-Up Table ( CLUT) and 16/24-bit direct pixel

mapping. Available on parts LPC4357/5 3 only.

Secure Digital Input Output (SD/MMC) card interface.

Eight-channel General-Purpose DMA controller can access all memories on the

AHB and all DMA-capable AHB slaves.

Up to 164 General-Purpose Input/Output (GPIO) pins with configurable

pull-up/pull-down resist ors.

GPIO registers are located on the AHB for fast access. GPIO ports have DMA

support.

Up to eight GPIO pins can be selected from all GPIO pins as edge and level

sensitive interrupt sources.

Two GPIO group interrupt modules enable an interrupt based on a programmable

pattern of input states of a group of GPIO pins.

Four general-purpose timer/counters with capture and match capabilities.

One motor control Pulse Width Modulator (PWM) for three-phase motor control.

One Quadrature Encoder Interface (QEI).

Repetitive Interrupt timer (RI timer).

Windowed watchdog timer (WWDT).

Ultra-low power Real-Time Clock (RTC) on separate po we r d omain with 25 6 bytes

of battery powe re d backup registers.

Alarm timer; can be battery powered.

Analog peripherals

One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.

Two 10-bit ADCs with DMA support an d a dat a conversion rate of 400 kSamples/s.

Up to eight input channels per ADC.

Unique ID for each device.

Clock generation unit

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

12 MHz internal RC oscillator trimmed to 3 % accuracy over temperature and

voltage (1.5 % accuracy for Tamb = 0 °C to 85 °C).

Ultra-low power Real-Time Clock (RTC) crystal oscillator.

Three PLLs allow CPU operation up to the maximum CPU ra te without the need for

a high-frequency crystal. The second PLL can be used with the High-speed USB,

the third PLL can be use d as au d io PLL .

Clock output.

Power

Single 3.3 V (2.4 V to 3.6 V) power supply with on-chip DC-to-DC converter for the

core supply and the RTC power domain.

RTC power domain can be powered separately by a 3 V battery supply.

Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

Processor wake-up from Sleep mode via wake-up interrupts from various

peripherals.

Product data sheet Rev. 5.2 — 26 November 2015 4 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

Wake-up from Deep-sleep, Power-down, and Deep power-down modes via

external interrupts and interrupts generated by batter y powered blocks in the RTC

power domain.

Brownout detect with four separate thresholds for interrupt and forced reset.

Power-On Reset (POR).

Availa ble as LQFP208, LQFP144, LBGA256, or TFBGA100 packages.

3. Applications

Motor control Embedded audio applications

Power management Industrial auto m ation

White goods e-metering

RFID readers

Product data sheet Rev. 5.2 — 26 November 2015 5 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

4. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

LPC4357FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2

LPC4357JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2

LPC4357JBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC4353FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2

LPC4353JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2

LPC4353JBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC4337FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2

LPC4337JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2

LPC4337JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC4337JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4333FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2

LPC4333JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2

LPC4333JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC4333JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4327JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC4327JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4325JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC4325JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4323JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC4323JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4322JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC4322JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4317JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC4317JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4315JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC4315JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4313JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC4313JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

LPC4312JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC4312JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

Product data sheet Rev. 5.2 — 26 November 2015 6 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

4.1 Ordering options

[1] J = -40 °C to +105 °C; F = -40 °C to +85 °C.

Table 2. Ordering options

Type number

Flash total

Flash bank A

Flash bank B

Total SRAM

LCD

Ethernet

USB0 (Host, Device, OTG)

USB1 (Host, Device)/

ULPI interface

Motor control PWM

QEI

ADC channels

Temperature range[1]

GPIO

LPC4357FET256 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes yes yes 8 F 164

LPC4357JET256 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes yes yes 8 J 164

LPC4357JBD208 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes yes yes 8 J 142

LPC4353FET256 512 kB 256 kB 256 kB 136 kB yes yes yes yes/ye s yes yes 8 F 164

LPC4353JET256 512 kB 256 kB 2 56 kB 136 kB yes yes ye s yes/ye s yes yes 8 J 164

LPC4353JBD208 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes yes yes 8 J 142

LPC4337FET256 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes yes yes 8 F 164

LPC4337JET256 1 MB 5 12 kB 512 kB 136 kB no yes yes yes/yes yes yes 8 J 164

LPC4337JBD144 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes yes no 8 J 83

LPC4337JET100 1 MB 5 12 kB 512 kB 136 kB no yes yes yes/no no no 4 J 49

LPC4333FET256 512 kB 256 kB 256 kB 136 kB no yes yes yes/ye s yes yes 8 F 164

LPC4333JET256 512 kB 256 kB 2 56 kB 136 kB no yes ye s yes/yes yes yes 8 J 164

LPC4333JBD144 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes yes no 8 J 83

LPC4333JET100 512 kB 256 kB 256 kB 136 kB no yes yes yes/no no no 4 J 49

LPC4327JBD144 1 MB 512 kB 512 kB 136 kB no no yes no/no yes no 8 J 83

LPC4327JET100 1 MB 5 12 kB 512 kB 136 kB no no yes no/no no no 4 J 49

LPC4325JBD144 768 kB 384 kB 384 kB 136 kB no no yes no/no yes no 8 J 83

LPC4325JET100 768 kB 384 kB 384 kB 136 kB no no yes no/no no no 4 J 49

LPC4323JBD144 512 kB 256 kB 256 kB 104 kB no no yes no/no yes no 8 J 83

LPC4323JET100 512 kB 256 kB 256 kB 104 kB no no yes no/no no no 4 J 49

LPC4322JBD144 512 kB 512 kB 0 kB 104 kB no no yes no/no yes no 8 J 83

LPC4322JET100 512 kB 512 kB 0 kB 104 kB no no yes no/no no no 4 J 49

LPC4317JBD144 1 MB 512 kB 512 kB 136 kB no no no no/no yes no 8 J 83

LPC4317JET100 1 MB 512 kB 512 kB 136 kB no no no no/no no no 4 J 49

LPC4315JBD144 768 kB 384 kB 384 kB 136 kB no no no no/no yes no 8 J 83

LPC4315JET100 768 kB 384 kB 3 84 kB 136 kB no no no no/no no no 4 J 49

LPC4313JBD144 512 kB 256 kB 256 kB 104 kB no no no no/no yes no 8 J 83

LPC4313JET100 512 kB 256 kB 2 56 kB 104 kB no no no no/no no no 4 J 49

LPC4312JBD144 512 kB 512 kB 0 kB 104 kB no no no no/no yes no 8 J 83

LPC4312JET100 512 kB 512 kB 0 kB 104 kB no no no no/no no no 4 J 49

Product data sheet Rev. 5.2 — 26 November 2015 7 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

5. Block diagram

(1) Not available on all parts. See Table 2.

Fig 1. LPC435x/3x/2x/1x Block diagram

ARM

CORTEX-M4

TEST/DEBUG

INTERFACE

I-code bus

D-code bus

system bus

DMA LCD(1) SD/

MMC

ETHERNET(1)

10/100

MAC

IEEE 1588

HIGH-SPEED

USB0(1)

HOST/

DEVICE/OTG

HIGH-SPEED

USB1(1)

HOST/DEVICE

EMC

HIGH-SPEED PHY

SPIFI

HS GPIO

SPI

SGPIO

SCT

I2C0

I2S0

I2S1

C_CAN1

MOTOR

CONTROL

PWM(1)

TIMER3

TIMER2

USART2

USART3

SSP1

RI TIMER

QEI(1)

GIMA

BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE

AHB MULTILAYER MATRIX

LPC435x/3x/2x/1x

10-bit ADC0

10-bit ADC1

C_CAN0

I2C1

10-bit DAC

BRIDGE

RGU

CCU2

CGU

CCU1

ALARM TIMER

CONFIGURATION

REGISTERS

OTP MEMORY

EVENT ROUTER

POWER MODE CONTROL

12 MHz IRC

RTC POWER DOMAIN

BACKUP REGISTERS

RTC OSC

RTC

002aah234

slaves

masters

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

= connected to DMA

GPIO

INTERRUPTS

GPIO GROUP0

INTERRUPT

GPIO GROUP1

INTERRUPT

WWDT

USART0

UART1

SSP0

TIMER0

TIMER1

SCU

32 kB AHB SRAM

16 kB +

16 kB AHB SRAM

64 kB ROM

32 kB LOCAL SRAM

40 kB LOCAL SRAM

512/256 kB FLASH A

512/256 kB FLASH B

16 kB EEPROM

Product data sheet Rev. 5.2 — 26 November 2015 8 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

6. Pinning information

6.1 Pinning

Fig 2. Pin configuration LBGA256 package Fig 3. Pin configuration TFBGA100 package

002aah177

LPC435x/3xFET256

Transparent top view

2 4 6 8 10 12

1357911

ball A1

index area

002aah179

LPC433x/2x/1xFET100

Transparent top view

24681013579

ball A1

index area

Fig 4. Pin configuration LQFP208 package Fig 5. Pin configuration LQFP144 package

LPC4357/53FBD208

104

156

105

157

208

002aah180

LPC433x/2x/1xFBD144

108

109

144

002aah181

Product data sheet Rev. 5.2 — 26 November 2015 9 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

6.2 Pin description

On the LPC435x/3x/2x/1x, digital pins are grouped into 16 ports, named P0 to P9 and PA

to PF, with up to 20 pins used per port. Each digital pin can support up to eight different

digital function s, including General Purpose I/O (GPIO), selectable through the System

Configuration Unit (SCU) registers. The pin name is not indicative of the GPIO port

assigned to it.

The parts contain two 10-bit ADCs (ADC0 and ADC1). The input channels of ADC0 and

ADC1 on dedicated pins an d multiplexed pins are combined in such a way that all channel

0 input s (nam ed ADC0_0 and ADC1_ 0) are tie d toge th er and co nne cte d to both , cha nnel

0 on ADC0 and channe l 0 on ADC1, chann el 1 inp uts (named ADC0_1 and ADC1_ 1) are

tied together and connected to channel 1 on ADC0 and ADC1, and so forth. There are

eight ADC channels total for the two ADCs.

Product data sheet Rev. 5.2 — 26 November 2015 10 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

Table 3. Pin description

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Multiplexed digital pins

P0_0 L3 G2 47 32 [2] N;

PU I/O GPIO0[0] — General purpose digital input/output pin.

I/O SSP1_MISO — Master In Slave Out for SSP1.

IENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

I/O SGPIO0 — General purpose digital input/output pin.

-R — Function reserved.

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

I/O I2S1_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

P0_1 M2 G1 50 34 [2] N;

PU I/O GPIO0[1] — General purpose digital input/output pin.

I/O SSP1_MOSI — Master Out Slave in for SSP1.

IENET_COL — Ethernet Collision detect (MII interface).

I/O SGPIO1 — General purpose digital input/output pin.

-R — Function reserved.

ENET_TX_EN — Ethernet transmit enable (RMII/MII

interface).

I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the

transmitter and read by the receiver . Corresponds to the

signal SD in the I2S-bus specification.

P1_0 P2 H1 54 38 [2] N;

PU I/O GPIO0[4] — General purpose digital input/output pin.

ICTIN_3 — SCT input 3. Capture input 1 of timer 1.

I/O EMC_A5 — External memory address line 5.

-R — Function reserved.

I/O SSP0_SSEL — Slave Select for SSP0.

I/O SGPIO7 — General purpose digital input/output pin.

I/O EMC_D12 — External memory data line 12.

Product data sheet Rev. 5.2 — 26 November 2015 11 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P1_1 R2 K2 58 42 [2] N;

PU I/O GPIO0[8] — General purpose digital input/output pi n. Boot

pin (see Table 5).

OCTOUT_7 — SCT output 7. Match output 3 of timer 1.

I/O EMC_A6 — External memory address line 6.

I/O SGPIO8 — General purpose digital input/output pin.

-R — Function reserved.

I/O SSP0_MISO — Master In Slave Out for SSP0.

-R — Function reserved.

I/O EMC_D13 — External memory data line 13.

P1_2 R3 K1 60 43 [2] N;

PU I/O GPIO0[9] — General purpose digital input/output pi n. Boot

pin (see Table 5).

OCTOUT_6 — SCT output 6. Match output 2 of timer 1.

I/O EMC_A7 — External memory address line 7.

I/O SGPIO9 — General purpose digital input/output pin.

-R — Function reserved.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

-R — Function reserved.

I/O EMC_D14 — External memory data line 14.

P1_3 P5 J1 61 44 [2] N;

PU I/O GPIO0[10] — General purpose digital input/output pin.

OCTOUT_8 — SCT output 8. Match output 0 of timer 2.

I/O SGPIO10 — General purpose digital input/output pin.

OEMC_OE — LOW active Output Enable signal.

OUSB0_IND1 — USB0 port indicator LED control

output 1.

I/O SSP1_MISO — Master In Slave Out for SSP1.

-R — Function reserved.

OSD_RST — SD/MMC reset signal for MMC4.4 card.

P1_4 T3 J2 64 47 [2] N;

PU I/O GPIO0[11] — General purpose digital input/output pin.

OCTOUT_9 — SCT output 9. Match output 3 of timer 3.

I/O SGPIO11 — General pu rpose digital input/output pin.

OEMC_BLS0 — LOW active Byte Lan e select signal 0.

OUSB0_IND0 — USB0 port indicator LED control output 0.

I/O SSP1_MOSI — Master Out Slave in for SSP1.

I/O EMC_D15 — External memory data line 15.

OSD_VOLT1 — SD/MMC bus voltage select output 1.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 12 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P1_5 R5 J4 65 48 [2] N;

PU I/O GPIO1[8] — General purpose digital input/output pin.

OCTOUT_10 — SCT output 10. Match output 3 of timer 3.

-R — Function reserved.

OEMC_CS0 — LOW active Chip Select 0 signal.

IUSB0_PWR_FAULT — Port power fault signal indicati ng

overcurrent condition; this signal monitors over-current on

the USB bus (external circ uitry required to detect

over-current condition).

I/O SSP1_SSEL — Slave Select for SSP1.

I/O SGPIO15 — General purpose digital input/output pin.

OSD_POW — SD/MMC power monitor output.

P1_6 T4 K4 67 49 [2] N;

PU I/O GPIO1[9] — General purpose digital input/output pin.

ICTIN_5 — SCT input 5. Capture input 2 of timer 2.

-R — Function reserved.

OEMC_WE — LOW active Write Enable signal.

-R — Function reserved.

OEMC_BLS0 — LOW active Byte Lane select signal 0.

I/O SGPIO14 — General purpose digital input/output pin.

I/O SD_CMD — SD/MMC command signal.

P1_7 T5 G4 69 50 [2] N;

PU I/O GPIO1[0] — General purpose digital input/output pin.

IU1_DSR — Data Set Ready input for UART1.

OCTOUT_13 — SCT output 13. Match output 3 of timer 3.

I/O EMC_D0 — External memory data line 0.

OUSB0_PPWR — VBUS drive signal (towards exte rnal

charge pump or power management unit); indicates that

VBUS must be driven (active HIGH).

Add a pull-down resistor to disable the power switch at reset.

This signal has opposite polarity compared to the

USB_PPWR used on other NXP LPC parts.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 13 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P1_8 R7 H5 71 51 [2] N;

PU I/O GPIO1[1] — General purpose digital input/output pin.

OU1_DTR — Data Terminal Ready output for UART1.

OCTOUT_12 — SCT output 12. Match output 3 of

timer 3.

I/O EMC_D1 — External memory data line 1.

-R — Function reserved.

OSD_VOLT0 — SD/MMC bus voltage select output 0.

P1_9 T7 J5 73 52 [2] N;

PU I/O GPIO1[2] — General purpose digital input/output pin.

OU1_RTS — Request to Send output for UART1.

OCTOUT_11 — SCT output 11. Match output 3 of timer 2.

I/O EMC_D2 — External memory data line 2.

-R — Function reserved.

I/O SD_DAT0 — SD/MMC data bus line 0.

P1_10 R8 H6 75 53 [2] N;

PU I/O GPIO1[3] — General purpose digital input/output pin.

IU1_RI — Ring Indicator input for UART1.

OCTOUT_14 — SCT output 14. Match output 2 of timer 3.

I/O EMC_D3 — External memory data line 3.

-R — Function reserved.

I/O SD_DAT1 — SD/MMC data bus line 1.

P1_11 T9 J7 77 55 [2] N;

PU I/O GPIO1[4] — General purpose digital input/output pin.

IU1_CTS — Clear to Send input for UART1.

OCTOUT_15 — SCT output 15. Match output 3 of timer 3.

I/O EMC_D4 — External memory data line 4.

-R — Function reserved.

I/O SD_DAT2 — SD/MMC data bus line 2.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 14 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P1_12 R9 K7 78 56 [2] N;

PU I/O GPIO1[5] — General purpose digital input/output pin.

IU1_DCD — Data Carrier Detect input for UART1.

-R — Function reserved.

I/O EMC_D5 — External memory data line 5.

IT0_CAP1 — Capture input 1 of timer 0.

-R — Function reserved.

I/O SGPIO8 — General purpose digital input/output pin.

I/O SD_DAT3 — SD/MMC data bus line 3.

P1_13 R10 H8 83 60 [2] N;

PU I/O GPIO1[6] — General purpose digital input/output pin.

OU1_TXD — Transmitter output for UART1.

-R — Function reserved.

I/O EMC_D6 — External memory data line 6.

IT0_CAP0 — Capture input 0 of timer 0.

-R — Function reserved.

I/O SGPIO9 — General purpose digital input/output pin.

ISD_CD — SD/MMC card detect input.

P1_14 R11 J8 85 61 [2] N;

PU I/O GPIO1[7] — General purpose digital input/output pin.

IU1_RXD — Receiver input for UART1.

-R — Function reserved.

I/O EMC_D7 — External memory data line 7.

OT0_MAT2 — Match output 2 of timer 0.

-R — Function reserved.

I/O SGPIO10 — General purpose digital input/output pin.

-R — Function reserved.

P1_15 T12 K8 87 62 [2] N;

PU I/O GPIO0[2] — General purpose digital input/output pin.

OU2_TXD — Transmitter output for USART2.

I/O SGPIO2 — General purpose digital input/output pin.

IENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).

OT0_MAT1 — Match output 1 of timer 0.

-R — Function reserved.

I/O EMC_D8 — External memory data line 8.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 15 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P1_16 M7 H9 90 64 [2] N;

PU I/O GPIO0[3] — General purpose digital input/output pin.

IU2_RXD — Receiver input for USART2.

I/O SGPIO3 — General purpose digital input/output pin.

IENET_CRS — Ethernet Carrier Sense (MII interface).

OT0_MAT0 — Match output 0 of timer 0.

-R — Function reserved.

I/O EMC_D9 — External memory data line 9.

IENET_RX_DV — Ethernet Recei v e Data Valid (RMII/MII

interface).

P1_17 M8 H10 93 66 [3] N;

PU I/O GPIO0[12] — General purpose digital input/output pin.

I/O U2_UCLK — Serial clock input/output for USART2 in

synchronous mode.

-R — Function reserved.

I/O ENET_MDIO — Ethernet MIIM data input and output.

IT0_CAP3 — Capture input 3 of timer 0.

OCAN1_TD — CAN1 transmitter output.

I/O SGPIO11 — General pu rpose digital input/output pin.

-R — Function reserved.

P1_18 N12 J10 95 67 [2] N;

PU I/O GPIO0[13] — General purpose digital input/output pin.

I/O U2_DIR — RS-485/EIA-485 outpu t enable/direction control

for USART2.

-R — Function reserved.

OENET_TXD0 — Ethernet transmit data 0 (RMII/MII

interface).

OT0_MAT3 — Match output 3 of timer 0.

ICAN1_RD — CAN1 receiver input.

I/O SGPIO12 — General purpose digital input/output pin.

I/O EMC_D10 — External memory data line 10.

P1_19 M11 K9 96 68 [2] N;

PU IENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit

Clock (MII interface) or Ethernet Reference Clock (RMII

interface).

I/O SSP1_SCK — Serial clock for SSP1.

-R — Function reserved.

OCLKOUT — Clock output pin.

-R — Function reserved.

OI2S0_RX_MCLK — I2S receive master clock.

I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I2S-bus specification.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 16 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P1_20 M10 K10 100 70 [2] N;

PU I/O GPIO0[15] — General purpose digital input/output pin.

I/O SSP1_SSEL — Slave Select for SSP1.

-R — Function reserved.

OENET_TXD1 — Ethernet transmit data 1 (RMII/MII

interface).

IT0_CAP2 — Capture input 2 of timer 0.

-R — Function reserved.

I/O SGPIO13 — General purpose digital input/output pin.

I/O EMC_D11 — External memory data line 11.

P2_0 T16 G10 108 75 [2] N;

PU I/O SGPIO4 — General purpose digital input/output pin.

OU0_TXD — Transmitter output for USART0. See Table 4 for

ISP mode.

I/O EMC_A13 — External memory address line 13.

OUSB0_PPWR — VBUS drive signal (towards exte rnal

charge pump or power management unit); indicates that

VBUS must be driven (active HIGH).

Add a pull-down resistor to disable the power switch at reset.

This signal has opposite polarity compared to the

USB_PPWR used on other NXP LPC parts.

I/O GPIO5[0] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP0 — Capture input 0 of timer 3.

OENET_MDC — Ethernet MIIM clock.

P2_1 N15 G7 116 81 [2] N;

PU I/O SGPIO5 — General purpose digital input/output pin.

IU0_RXD — Receiver input for USART0. See Table 4 for ISP

mode.

I/O EMC_A12 — External memory address line 12.

IUSB0_PWR_FAULT — Port power fault signal indicati ng

overcurrent condition; this signal monitors over-current on

the USB bus (external circ uitry required to detect

over-current condition).

I/O GPIO5[1] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP1 — Capture input 1 of timer 3.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 17 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P2_2 M15 F5 121 84 [2] N;

PU I/O SGPIO6 — General purpose digital input/output pin.

I/O U0_UCLK — Serial clock input/output for USART0 in

synchronous mode.

I/O EMC_A11 — External memory address line 11.

OUSB0_IND1 — USB0 port indicator LED control output 1.

I/O GPIO5[2] — General purpose digital input/output pin.

ICTIN_6 — SCT input 6. Capture input 1 of timer 3.

IT3_CAP2 — Capture input 2 of timer 3.

OEMC_CS1 — LOW active Chip Select 1 signal.

P2_3 J12 D8 127 87 [3] N;

PU I/O SGPIO12 — General purpose digital input/output pin.

I/O I2C1_SDA — I2C1 data input/output (this pin does not use a

specialized I2C pad).

OU3_TXD — Transmitter output for USART3. See Table 4 for

ISP mode.

ICTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture

input 1 of timer 2.

I/O GPIO5[3] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT0 — Match output 0 of timer 3.

OUSB0_PPWR — VBUS drive signal (towards exte rnal

charge pump or power management unit); indicates that

VBUS must be driven (active HIGH).

Add a pull-down resistor to disable the power switch at reset.

This signal has opposite polarity compared to the

USB_PPWR used on other NXP LPC parts.

P2_4 K11 D9 128 88 [3] N;

PU I/O SGPIO13 — General purpose digital input/output pin.

I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a

specialized I2C pad).

IU3_RXD — Receiver input for USART3. See Table 4 for ISP

mode.

ICTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

I/O GPIO5[4] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT1 — Match output 1 of timer 3.

IUSB0_PWR_FAULT — Port power fault signal indicati ng

overcurrent condition; this signal monitors over-current on

the USB bus (external circ uitry required to detect

over-current condition).

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 18 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P2_5 K14 D10 131 91 [3] N;

PU I/O SGPIO14 — General purpose digital input/output pin.

ICTIN_2 — SCT input 2. Capture input 2 of timer 0.

IUSB1_VBUS — Monitors the presence of USB1 bus pow er.

Note: This signal must be HIGH for USB reset to occur.

IADCTRIG1 — ADC trigger input 1.

I/O GPIO5[5] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT2 — Match output 2 of timer 3.

OUSB0_IND0 — USB0 port indicator LED control output 0.

P2_6 K16 G9 137 95 [2] N;

PU I/O SGPIO7 — General purpose digital input/output pin.

I/O U0_DIR — RS-485/EIA-485 outpu t enable/direction control

for USART0.

I/O EMC_A10 — External memory address line 10.

OUSB0_IND0 — USB0 port indicator LED control

output 0.

I/O GPIO5[6] — General purpose digital input/output pin.

ICTIN_7 — SCT input 7.

IT3_CAP3 — Capture input 3 of timer 3.

OEMC_BLS1 — LOW active Byte Lan e select signal 1.

P2_7 H14 C10 138 96 [2] N;

PU I/O GPIO0[7] — General purpose digital input/output pin. If this

pin is pulled LOW at reset, the part enters ISP mode or boots

from an external source (see Table 4 and Table 5).

OCTOUT_1 — SCT output 1. Match output 3 of timer 3.

I/O U3_UCLK — Serial clock input/output for USART3 in

synchronous mode.

I/O EMC_A9 — External memory address line 9.

-R — Function reserved.

OT3_MAT3 — Match output 3 of timer 3.

-R — Function reserved.

P2_8 J16 C6 140 98 [2] N;

PU I/O SGPIO15 — General purpose digital input/output pin. Boot

pin (see Table 5).

OCTOUT_0 — SCT output 0. Match output 0 of timer 0.

I/O U3_DIR — RS-485/EIA-485 outpu t enable/direction control

for USART3.

I/O EMC_A8 — External memory address line 8.

I/O GPIO5[7] — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 19 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P2_9 H16 B10 144 102 [2] N;

PU I/O GPIO1[10] — General purpose digital input/output pin. Boot

pin (see Table 5).

OCTOUT_3 — SCT output 3. Match output 3 of timer 0.

I/O U3_BAUD — Baud pin for USART 3.

I/O EMC_A0 — External memory address line 0.

-R — Function reserved.

P2_10 G16 E8 146 104 [2] N;

PU I/O GPIO0[14] — General purpose digital input/output pin.

OCTOUT_2 — SCT output 2. Match output 2 of timer 0.

OU2_TXD — Transmitter output for USART2.

I/O EMC_A1 — External memory address line 1.

-R — Function reserved.

P2_11 F16 A9 148 105 [2] N;

PU I/O GPIO1[11] — General purpose digital input/output pin.

OCTOUT_5 — SCT output 5. Match output 3 of timer 3.

IU2_RXD — Receiver input for USART2.

I/O EMC_A2 — External memory address line 2.

-R — Function reserved.

P2_12 E15 B9 153 106 [2] N;

PU I/O GPIO1[12] — General purpose digital input/output pin.

OCTOUT_4 — SCT output 4. Match output 3 of timer 3.

-R — Function reserved.

I/O EMC_A3 — External memory address line 3.

-R — Function reserved.

I/O U2_UCLK — Serial clock input/output for USART2 in

synchronous mode.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 20 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P2_13 C16 A10 156 108 [2] N;

PU I/O GPIO1[13] — General purpose digital input/output pin.

ICTIN_4 — SCT input 4. Capture input 2 of timer 1.

-R — Function reserved.

I/O EMC_A4 — External memory address line 4.

-R — Function reserved.

I/O U2_DIR — RS-485/EIA-485 outpu t enable/direction control

for USART2.

P3_0 F13 A8 161 112 [2] N;

PU I/O I2S0_RX_SCK — I2S receive clock. It is driven by the

master and received by the slave. Corresponds to the signal

SCK in the I2S-bus specification.

OI2S0_RX_MCLK — I2S receive master clock.

I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I2S-bus specification .

OI2S0_TX_MCLK — I2S transmit master clock.

I/O SSP0_SCK — Serial clock for SSP0.

-R — Function reserved.

P3_1 G11 F7 163 114 [2] N;

PU I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

I/O I2S0_RX_WS — Receive Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

ICAN0_RD — CAN receive r input.

OUSB1_IND1 — USB1 Port indicator LED control output 1.

I/O GPIO5[8] — General purpose digital input/output pin.

-R — Function reserved.

OLCD_VD15 — LCD data.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 21 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P3_2 F11 G6 166 116 [2] OL;

PU I/O I2S0_TX_SDA — I2S transmit data. It is driven by the

transmitter and read by the receiver . Corresponds to the

signal SD in the I2S-bus specification.

I/O I2S0_RX_SDA — I2S Receive data. It is driven by the

transmitter and read by the receiver . Corresponds to the

signal SD in the I2S-bus specification.

OCAN0_TD — CAN transmitter output.

OUSB1_IND0 — USB1 Port indicator LED control output 0.

I/O GPIO5[9] — General purpose digital input/output pin.

-R — Function reserved.

OLCD_VD14 — LCD data.

-R — Function reserved.

P3_3 B14 A7 169 118 [4] N;

PU -R — Function reserved.

I/O SPI_SCK — Serial clock for SPI.

I/O SSP0_SCK — Serial clock for SSP0.

OSPIFI_SCK — Serial clock for SPIFI.

OCGU_OUT1 — CGU spare clock output 1.

-R — Function reserved.

OI2S0_TX_MCLK — I2S transmit master clock.

I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I2S-bus specification.

P3_4 A15 B8 171 119 [2] N;

PU I/O GPIO1[14] — General purpose digital input/output pin.

-R — Function reserved.

I/O SPIFI_SIO3 — I/ O lane 3 for SPIFI.

OU1_TXD — Transmitter output for UART 1.

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

I/O I2S1_RX_SDA — I2S1 Receive data. It is driven by the

transmitter and read by the receiver . Corresponds to the

signal SD in the I2S-bus specification.

OLCD_VD13 — LCD data.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 22 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P3_5 C12 B7 173 121 [2] N;

PU I/O GPIO1[15] — General purpose digital input/output pin.

-R — Function reserved.

I/O SPIFI_SIO2 — I/ O lane 2 for SPIFI.

IU1_RXD — Receiver input for UART 1.

I/O I2S0_TX_SDA — I2S transmit data. It is driven by the

transmitter and read by the receiver . Corresponds to the

signal SD in the I2S-bus specification.

I/O I2S1_RX_WS — Receive Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

OLCD_VD12 — LCD data.

P3_6 B13 C7 174 122 [2] N;

PU I/O GPIO0[6] — General purpose digital input/output pin.

I/O SPI_MISO — Master In Slave Out for SPI.

I/O SSP0_SSEL — Slave Select for SSP0.

I/O SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output

IO1.

-R — Function reserved.

I/O SSP0_MISO — Master In Slave Out for SSP0.

-R — Function reserved.

P3_7 C11 D7 176 123 [2] N;

PU -R — Function reserved.

I/O SPI_MOSI — Master Out Slave In for SPI.

I/O SSP0_MISO — Master In Slave Out for SSP0.

I/O SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output

IO0.

I/O GPIO5[10] — General purpose digital input/output pin.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

-R — Function reserved.

P3_8 C10 E7 179 124 [2] N;

PU -R — Function reserved.

ISPI_SSEL — Slave Select for SPI. Note that this pin in an

input pin only. The SPI in master mode cannot drive the CS

input on the slave. Any GPIO pin can be used for SPI chip

select in master mode.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

I/O SPIFI_CS — SPIFI serial flash chip select.

I/O GPIO5[11] — General purpose digital input/output pin.

I/O SSP0_SSEL — Slave Select for SSP0.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 23 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P4_0 D5 - 1 1 [2] N;

PU I/O GPIO2[0] — General purpose digital input/output pin.

OMCOA0 — Motor control PWM channel 0, output A.

INMI — External interrupt input to NMI.

-R — Function reserved.

OLCD_VD13 — LCD data.

I/O U3_UCLK — Serial clock input/output for USART3 in

synchronous mode.

-R — Function reserved.

P4_1 A1 - 3 3 [5] N;

PU I/O GPIO2[1] — General purpose digital input/output pin.

OCTOUT_1 — SCT output 1. Match output 3 of timer 3.

OLCD_VD0 — LCD data.

-R — Function reserved.

OLCD_VD19 — LCD data.

OU3_TXD — Transmitter output for USART3.

IENET_COL — Ethernet Collision detect (MII interface).

AI ADC0_1 — ADC0 and ADC1, input channel 1. Configure the

pin as GPIO input and use the ADC function select register

in the SCU to select the ADC.

P4_2 D3 - 12 8 [2] N;

PU I/O GPIO2[2] — General purpose digital input/output pin.

OCTOUT_0 — SCT output 0. Match output 0 of timer 0.

OLCD_VD3 — LCD data.

-R — Function reserved.

OLCD_VD12 — LCD data.

IU3_RXD — Receiver input for USART3.

I/O SGPIO8 — General purpose digital input/output pin.

P4_3 C2 - 10 7 [5] N;

PU I/O GPIO2[3] — General purpose digital input/output pin.

OCTOUT_3 — SCT output 3. Match output 3 of timer 0.

OLCD_VD2 — LCD data.

-R — Function reserved.

OLCD_VD21 — LCD data.

I/O U3_BAUD — Baud pin for USART 3.

I/O SGPIO9 — General purpose digital input/output pin.

AI ADC0_0 — DAC, ADC0 and ADC1, input channel 0.

Configure the pin as GPIO input and use the ADC function

select register in the SCU to select the ADC.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 24 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P4_4 B1 - 14 9 [5] N;

PU I/O GPIO2[4] — General purpose digital input/output pin.

OCTOUT_2 — SCT output 2. Match output 2 of timer 0.

OLCD_VD1 — LCD data.

-R — Function reserved.

OLCD_VD20 — LCD data.

I/O U3_DIR — RS-485/EIA-485 outpu t enable/direction control

for USART3.

I/O SGPIO10 — General purpose digital input/output pin.

ODAC — DAC output. Configure the pin as GPIO input and

use the analog function select register in the SCU to select

the DAC.

P4_5 D2 - 15 10 [2] N;

PU I/O GPIO2[5] — General purpose digital input/output pin.

OCTOUT_5 — SCT output 5. Match output 3 of timer 3.

OLCD_FP — Frame pulse (STN). Vertical synchronization

pulse (TFT).

-R — Function reserved.

I/O SGPIO11 — General pu rpose digital input/output pin.

P4_6 C1 - 17 11 [2] N;

PU I/O GPIO2[6] — General purpose digital input/output pin.

OCTOUT_4 — SCT output 4. Match output 3 of timer 3.

OLCD_ENAB/LCDM — STN AC bias drive or TFT data

enable input.

-R — Function reserved.

I/O SGPIO12 — General purpose digital input/output pin.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 25 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P4_7 H4 - 21 14 [2] O;

PU OLCD_DCLK — LCD panel clock.

IGP_CLKIN — General purpose clock input to the CGU.

-R — Function reserved.

I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I2S-bus specification.

I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I2S-bus specification.

P4_8 E2 - 23 15 [2] N;

PU -R — Function reserved.

ICTIN_5 — SCT input 5. Capture input 2 of timer 2.

OLCD_VD9 — LCD data.

-R — Function reserved.

I/O GPIO5[12] — General purpose digital input/output pin.

OLCD_VD22 — LCD data.

OCAN1_TD — CAN1 transmitter output.

I/O SGPIO13 — General purpose digital input/output pin.

P4_9 L2 - 48 33 [2] N;

PU -R — Function reserved.

ICTIN_6 — SCT input 6. Capture input 1 of timer 3.

OLCD_VD11 — LCD data.

-R — Function reserved.

I/O GPIO5[13] — General purpose digital input/output pin.

OLCD_VD15 — LCD data.

ICAN1_RD — CAN1 receiver input.

I/O SGPIO14 — General purpose digital input/output pin.

P4_10 M3 - 51 35 [2] N;

PU -R — Function reserved.

ICTIN_2 — SCT input 2. Capture input 2 of timer 0.

OLCD_VD10 — LCD data.

-R — Function reserved.

I/O GPIO5[14] — General purpose digital input/output pin.

OLCD_VD14 — LCD data.

-R — Function reserved.

I/O SGPIO15 — General purpose digital input/output pin.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 26 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P5_0 N3 - 53 37 [2] N;

PU I/O GPIO2[9] — General purpose digital input/output pin.

OMCOB2 — Motor control PWM channel 2, output B.

I/O EMC_D12 — External memory data line 12.

-R — Function reserved.

IU1_DSR — Data Set Ready input for UART 1.

IT1_CAP0 — Capture input 0 of timer 1.

-R — Function reserved.

P5_1 P3 - 55 39 [2] N;

PU I/O GPIO2[10] — General purpose digital input/output pin.

IMCI2 — Mo tor control PWM channel 2, inp ut.

I/O EMC_D13 — External memory data line 13.

-R — Function reserved.

OU1_DTR — Data Terminal Ready output for UART 1. Can

also be configured to be an RS-485/EIA-485 output enable

signal for UART 1.

IT1_CAP1 — Capture input 1 of timer 1.

-R — Function reserved.

P5_2 R4 - 63 46 [2] N;

PU I/O GPIO2[11] — General purpose digital input/output pin.

IMCI1 — Mo tor control PWM channel 1, inp ut.

I/O EMC_D14 — External memory data line 14.

-R — Function reserved.

OU1_RTS — Request to Send output for UART 1. Can also

be configured to be an RS-485/EIA-485 output enable signal

for UART 1.

IT1_CAP2 — Capture input 2 of timer 1.

-R — Function reserved.

P5_3 T8 - 76 54 [2] N;

PU I/O GPIO2[12] — General purpose digital input/output pin.

IMCI0 — Mo tor control PWM channel 0, inp ut.

I/O EMC_D15 — External memory data line 15.

-R — Function reserved.

IU1_RI — Ring Indicator input for UART 1.

IT1_CAP3 — Capture input 3 of timer 1.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 27 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P5_4 P9 - 80 57 [2] N;

PU I/O GPIO2[13] — General purpose digital input/output pin.

OMCOB0 — Motor control PWM channel 0, output B.

I/O EMC_D8 — External memory data line 8.

-R — Function reserved.

IU1_CTS — Clear to Send input for UART 1.

OT1_MAT0 — Match output 0 of timer 1.

-R — Function reserved.

P5_5 P10 - 81 58 [2] N;

PU I/O GPIO2[14] — General purpose digital input/output pin.

OMCOA1 — Motor control PWM channel 1, output A.

I/O EMC_D9 — External memory data line 9.

-R — Function reserved.

IU1_DCD — Data Carrier Detect input for UART 1.

OT1_MAT1 — Match output 1 of timer 1.

-R — Function reserved.

P5_6 T13 - 89 63 [2] N;

PU I/O GPIO2[15] — General purpose digital input/output pin.

OMCOB1 — Motor control PWM channel 1, output B.

I/O EMC_D10 — External memory data line 10.

-R — Function reserved.

OU1_TXD — Transmitter output for UART 1.

OT1_MAT2 — Match output 2 of timer 1.

-R — Function reserved.

P5_7 R12 - 91 65 [2] N;

PU I/O GPIO2[7] — General purpose digital input/output pin.

OMCOA2 — Motor control PWM channel 2, output A.

I/O EMC_D11 — External memory data line 11.

-R — Function reserved.

IU1_RXD — Receiver input for UART 1.

OT1_MAT3 — Match output 3 of timer 1.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 28 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P6_0 M12 H7 105 73 [2] N;

PU -R — Function reserved.

OI2S0_RX_MCLK — I2S receive master clock.

-R — Function reserved.

I/O I2S0_RX_SCK — Receive Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I2S-bus specification.

-R — Function reserved.

P6_1 R15 G5 107 74 [2] N;

PU I/O GPIO3[0] — General purpose digital input/output pin.

OEMC_DYCS1 — SDRAM chip select 1.

I/O U0_UCLK — Serial clock input/output for USART0 in

synchronous mode.

I/O I2S0_RX_WS — Receive Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

-R — Function reserved.

IT2_CAP0 — Capture input 2 of timer 2.

-R — Function reserved.

P6_2 L13 J9 111 78 [2] N;

PU I/O GPIO3[1] — General purpose digital input/output pin.

OEMC_CKEOUT1 — SDRAM clock enable 1.

I/O U0_DIR — RS-485/EIA-485 outpu t enable/direction control

for USART0.

I/O I2S0_RX_SDA — I2S Receive data. It is driven by the

transmitter and read by the receiver . Corresponds to the

signal SD in the I2S-bus specification.

-R — Function reserved.

IT2_CAP1 — Capture input 1 of timer 2.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 29 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P6_3 P15 - 113 79 [2] N;

PU I/O GPIO3[2] — General purpose digital input/output pin.

OUSB0_PPWR — VBUS drive signal (towards exte rnal

charge pump or power management unit); indica tes that the

VBUS signal must be driven (active HIGH).

Add a pull-down resistor to disable the power switch at reset.

This signal has opposite polarity compared to the

USB_PPWR used on other NXP LPC parts.

I/O SGPIO4 — General purpose digital input/output pin.

OEMC_CS1 — LOW active Chip Select 1 signal.

-R — Function reserved.

IT2_CAP2 — Capture input 2 of timer 2.

-R — Function reserved.

P6_4 R16 F6 114 80 [2] N;

PU I/O GPIO3[3] — General purpose digital input/output pin.

ICTIN_6 — SCT input 6. Capture input 1 of timer 3.

OU0_TXD — Transmitter output for USART0.

OEMC_CAS — LOW active SDRAM Column Address St robe.

-R — Function reserved.

P6_5 P16 F9 117 82 [2] N;

PU I/O GPIO3[4] — General purpose digital input/output pin.

OCTOUT_6 — SCT output 6. Match output 2 of timer 1.

IU0_RXD — Receiver input for USART0.

OEMC_RAS — LOW active SDRAM Row Address Strob e.

-R — Function reserved.

P6_6 L14 - 119 83 [2] N;

PU I/O GPIO0[5] — General purpose digital input/output pin.

OEMC_BLS1 — LOW active Byte Lan e select signal 1.

I/O SGPIO5 — General purpose digital input/output pin.

IUSB0_PWR_FAULT — Port power fault signal indicati ng

overcurrent condition; this signal monitors over-current on

the USB bus (external circ uitry required to detect

over-current condition).

-R — Function reserved.

IT2_CAP3 — Capture input 3 of timer 2.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 30 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P6_7 J13 - 123 85 [2] N;

PU -R — Function reserved.

I/O EMC_A15 — External memory address line 15.

I/O SGPIO6 — General purpose digital input/output pin.

OUSB0_IND1 — USB0 port indicator LED control output 1.

I/O GPIO5[15] — General purpose digital input/output pin.

OT2_MAT0 — Match output 0 of timer 2.

-R — Function reserved.

P6_8 H13 - 125 86 [2] N;

PU -R — Function reserved.

I/O EMC_A14 — External memory address line 14.

I/O SGPIO7 — General purpose digital input/output pin.

OUSB0_IND0 — USB0 port indicator LED control output 0.

I/O GPIO5[16] — General purpose digital input/output pin.

OT2_MAT1 — Match output 1 of timer 2.

-R — Function reserved.

P6_9 J15 F8 139 97 [2] N;

PU I/O GPIO3[5] — General purpose digital input/output pin.

-R — Function reserved.

OEMC_DYCS0 — SDRAM chip select 0.

-R — Function reserved.

OT2_MAT2 — Match output 2 of timer 2.

-R — Function reserved.

P6_10 H15 - 142 100 [2] N;

PU I/O GPIO3[6] — General purpose digital input/output pin.

OMCABORT — Motor control PWM, LOW-active fast abort.

-R — Function reserved.

OEMC_DQMOUT1 — Data mask 1 used with SDRAM and

static devices.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 31 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P6_11 H12 C9 143 101 [2] N;

PU I/O GPIO3[7] — General purpose digital input/output pin.

-R — Function reserved.

OEMC_CKEOUT0 — SDRAM clock enable 0.

-R — Function reserved.

OT2_MAT3 — Match output 3 of timer 2.

-R — Function reserved.

P6_12 G15 - 145 103 [2] N;

PU I/O GPIO2[8] — General purpose digital input/output pin.

OCTOUT_7 — SCT output 7. Match output 3 of timer 1.

-R — Function reserved.

OEMC_DQMOUT0 — Data mask 0 used with SDRAM and

static devices.

-R — Function reserved.

P7_0 B16 - 158 110 [2] N;

PU I/O GPIO3[8] — General purpose digital input/output pin.

OCTOUT_14 — SCT output 14. Match output 2 of timer 3.

-R — Function reserved.

OLCD_LE — Line end signal.

-R — Function reserved.

I/O SGPIO4 — General purpose digital input/output pin.

P7_1 C14 - 162 113 [2] N;

PU I/O GPIO3[9] — General purpose digital input/output pin.

OCTOUT_15 — SCT output 15. Match output 3 of timer 3.

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

OLCD_VD19 — LCD data.

OLCD_VD7 — LCD data.

-R — Function reserved.

OU2_TXD — Transmitter output for USART2.

I/O SGPIO5 — General purpose digital input/output pin.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 32 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P7_2 A16 - 165 115 [2] N;

PU I/O GPIO3[10] — General purpose digital input/output pin.

ICTIN_4 — SCT input 4. Capture input 2 of timer 1.

I/O I2S0_TX_SDA — I2S transmit data. It is driven by the

transmitter and read by the receiver . Corresponds to the

signal SD in the I2S-bus specification.

OLCD_VD18 — LCD data.

OLCD_VD6 — LCD data.

-R — Function reserved.

IU2_RXD — Receiver input for USART2.

I/O SGPIO6 — General purpose digital input/output pin.

P7_3 C13 - 167 117 [2] N;

PU I/O GPIO3[11] — General purpose digital input/output pin.

ICTIN_3 — SCT input 3. Capture input 1 of timer 1.

-R — Function reserved.

OLCD_VD17 — LCD data.

OLCD_VD5 — LCD data.

-R — Function reserved.

P7_4 C8 - 189 132 [5] N;

PU I/O GPIO3[12] — General purpose digital input/output pin.

OCTOUT_13 — SCT output 13. Match output 3 of timer 3.

-R — Function reserved.

OLCD_VD16 — LCD data.

OLCD_VD4 — LCD data.

OTRACEDATA[0] — T race data, bit 0.

-R — Function reserved.

AI ADC0_4 — ADC0 and ADC1, input channel 4. Configure the

pin as GPIO input and use the ADC function select register

in the SCU to select the ADC.

P7_5 A7 - 191 133 [5] N;

PU I/O GPIO3[13] — General purpose digital input/output pin.

OCTOUT_12 — SCT output 12. Match output 3 of timer 3.

-R — Function reserved.

OLCD_VD8 — LCD data.

OLCD_VD23 — LCD data.

OTRACEDATA[1] — T race data, bit 1.

-R — Function reserved.

AI ADC0_3 — ADC0 and ADC1, input channel 3. Configure the

pin as GPIO input and use the ADC function select register

in the SCU to select the ADC.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 33 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P7_6 C7 - 194 134 [2] N;

PU I/O GPIO3[14] — General purpose digital input/output pin.

OCTOUT_11 — SCT outpu t 1. Match output 3 of timer 2.

-R — Function reserved.

OLCD_LP — Line synchronization pulse (STN). Horizontal

synchronization pul se (TFT).

-R — Function reserved.

OTRACEDATA[2] — T race data, bit 2.

-R — Function reserved.

P7_7 B6 - 201 140 [5] N;

PU I/O GPIO3[15] — General purpose digital input/output pin.

OCTOUT_8 — SCT output 8. Match output 0 of timer 2.

-R — Function reserved.

OLCD_PWR — LCD panel power enable.

-R — Function reserved.

OTRACEDATA[3] — T race data, bit 3.

OENET_MDC — Ethernet MIIM clock.

I/O SGPIO7 — General purpose digital input/output pin.

AI ADC1_6 — ADC1 and ADC0, input channel 6. Configure the

pin as GPIO input and use the ADC function select register

in the SCU to select the ADC.

P8_0 E5 - 2 - [3] N;

PU I/O GPIO4[0] — General purpose digital input/output pin.

IUSB0_PWR_FAULT — Port power fault signal indicati ng

overcurrent condition; this signal monitors over-current on

the USB bus (external circ uitry required to detect

over-current condition).

-R — Function reserved.

IMCI2 — Mo tor control PWM channel 2, inp ut.

I/O SGPIO8 — General purpose digital input/output pin.

-R — Function reserved.

OT0_MAT0 — Match output 0 of timer 0.

P8_1 H5 - 34 - [3] N;

PU I/O GPIO4[1] — General purpose digital input/output pin.

OUSB0_IND1 — USB0 port indicator LED control output 1.

-R — Function reserved.

IMCI1 — Mo tor control PWM channel 1, inp ut.

I/O SGPIO9 — General purpose digital input/output pin.

-R — Function reserved.

OT0_MAT1 — Match output 1 of timer 0.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 34 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P8_2 K4 - 36 - [3] N;

PU I/O GPIO4[2] — General purpose digital input/output pin.

OUSB0_IND0 — USB0 port indicator LED control output 0.

-R — Function reserved.

IMCI0 — Mo tor control PWM channel 0, inp ut.

I/O SGPIO10 — General purpose digital input/output pin.

-R — Function reserved.

OT0_MAT2 — Match output 2 of timer 0.

P8_3 J3 - 37 - [2] N;

PU I/O GPIO4[3] — General purpose digital input/output pin.

I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.

-R — Function reserved.

OLCD_VD12 — LCD data.

OLCD_VD19 — LCD data.

-R — Function reserved.

OT0_MAT3 — Match output 3 of timer 0.

P8_4 J2 - 39 - [2] N;

PU I/O GPIO4[4] — General purpose digital input/output pin.

I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-R — Function reserved.

OLCD_VD7 — LCD data.

OLCD_VD16 — LCD data.

-R — Function reserved.

IT0_CAP0 — Capture input 0 of timer 0.

P8_5 J1 - 40 - [2] N;

PU I/O GPIO4[5] — General purpose digital input/output pin.

I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.

-R — Function reserved.

OLCD_VD6 — LCD data.

OLCD_VD8 — LCD data.

-R — Function reserved.

IT0_CAP1 — Capture input 1 of timer 0.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 35 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P8_6 K3 - 43 - [2] N;

PU I/O GPIO4[6] — General purpose digital input/output pin.

IUSB1_ULPI_NXT — ULPI link NXT signal. Data flow control

signal from the PHY.

-R — Function reserved.

OLCD_VD5 — LCD data.

OLCD_LP — Line synchronization pulse (STN). Horizontal

synchronization pul se (TFT).

-R — Function reserved.

IT0_CAP2 — Capture input 2 of timer 0.

P8_7 K1 - 45 - [2] N;

PU I/O GPIO4[7] — General purpose digital input/output pin.

OUSB1_ULPI_STP — ULPI link STP signal. Asserte d to end

or interrupt transfers to the PHY.

-R — Function reserved.

OLCD_VD4 — LCD data.

OLCD_PWR — LCD panel power enable.

-R — Function reserved.

IT0_CAP3 — Capture input 3 of timer 0.

P8_8 L1 - 49 - [2] N;

PU -R — Function reserved.

IUSB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock

generated by the PHY.

-R — Function reserved.

OCGU_OUT0 — CGU spare clock output 0.

OI2S1_TX_MCLK — I2S1 transmit master clock.

P9_0 T1 - 59 - [2] N;

PU I/O GPIO4[12] — General purpose digital input/output pin.

OMCABORT — Motor control PWM, LOW-active fast abort.

-R — Function reserved.

IENET_CRS — Ethernet Carrier Sense (MII interface).

I/O SGPIO0 — General purpose digital input/output pin.

I/O SSP0_SSEL — Slave Select for SSP0.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 36 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P9_1 N6 - 66 - [2] N;

PU I/O GPIO4[13] — General purpose digital input/output pin.

OMCOA2 — Motor control PWM channel 2, output A.

-R — Function reserved.

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

IENET_RX_ER — Ethernet receive error (MII interface).

I/O SGPIO1 — General purpose digital input/output pin.

I/O SSP0_MISO — Master In Slave Out for SSP0.

P9_2 N8 - 70 - [2] N;

PU I/O GPIO4[14] — General purpose digital input/output pin.

OMCOB2 — Motor control PWM channel 2, output B.

-R — Function reserved.

I/O I2S0_TX_SDA — I2S transmit data. It is driven by the

transmitter and read by the receiver . Corresponds to the

signal SD in the I2S-bus specification.

IENET_RXD3 — Ethernet receive data 3 (MII interface).

I/O SGPIO2 — General purpose digital input/output pin.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

P9_3 M6 - 79 - [2] N;

PU I/O GPIO4[15] — General purpose digital input/output pin.

OMCOA0 — Motor control PWM channel 0, output A.

OUSB1_IND1 — USB1 Port indicator LED control output 1.

-R — Function reserved.

IENET_RXD2 — Ethernet receive data 2 (MII interface).

I/O SGPIO9 — General purpose digital input/output pin.

OU3_TXD — Transmitter output for USART3.

P9_4 N10 - 92 - [2] N;

PU -R — Function reserved.

OMCOB0 — Motor control PWM channel 0, output B.

OUSB1_IND0 — USB1 Port indicator LED control output 0.

-R — Function reserved.

I/O GPIO5[17] — General purpose digital input/output pin.

OENET_TXD2 — Ethernet transmit data 2 (MII interface).

I/O SGPIO4 — General purpose digital input/output pin.

IU3_RXD — Receiver input for USART3.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 37 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

P9_5 M9 - 98 69 [2] N;

PU -R — Function reserved.

OMCOA1 — Motor control PWM channel 1, output A.

OUSB1_PPWR — VBUS drive signal (towards exte rnal

charge pump or power management unit); indicates that

VBUS must be driven (active high).

Add a pull-down resistor to disable the power switch at reset.

This signal has opposite polarity compared to the

USB_PPWR used on other NXP LPC parts.

-R — Function reserved.

I/O GPIO5[18] — General purpose digital input/output pin.

OENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O SGPIO3 — General purpose digital input/output pin.

OU0_TXD — Transmitter output for USART0.

P9_6 L11 - 103 72 [2] N;

PU I/O GPIO4[11] — General purpose digital input/output pin.

OMCOB1 — Motor control PWM channel 1, output B.

IUSB1_PWR_FAULT — USB1 Port power fault signal

indicating over-current condition; this signal monitors

over-current on the USB1 bus (external circuitry required to

detect over-current condition).

-R — Function reserved.

IENET_COL — Ethernet Collision detect (MII interface).

I/O SGPIO8 — General purpose digital input/output pin.

IU0_RXD — Receiver input for USART0.

PA_0 L12 - 126 - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OI2S1_RX_MCLK — I2S1 receive master clock.

OCGU_OUT1 — CGU spare clock output 1.

-R — Function reserved.

PA_1 J14 - 134 - [3] N;

PU I/O GPIO4[8] — General purpose digital input/output pin.

IQEI_IDX — Quadrature Encoder Interface INDEX input.

-R — Function reserved.

OU2_TXD — Transmitter output for USART2.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 38 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PA_2 K15 - 136 - [3] N;

PU I/O GPIO4[9] — General purpose digital input/output pin.

IQEI_PHB — Quadrature Encoder Interface PHB input.

-R — Function reserved.

IU2_RXD — Receiver input for USART2.

-R — Function reserved.

PA_3 H11 - 147 - [3] N;

PU I/O GPIO4[10] — General purpose digital input/output pin.

IQEI_PHA — Quadrature Encoder Interface PHA input.

-R — Function reserved.

PA_4 G13 - 151 - [2] N;

PU -R — Function reserved.

OCTOUT_9 — SCT output 9. Match output 3 of timer 3.

-R — Function reserved.

I/O EMC_A23 — External memory address line 23.

I/O GPIO5[19] — General purpose digital input/output pin.

-R — Function reserved.

PB_0 B15 - 164 - [2] N;

PU -R — Function reserved.

OCTOUT_10 — SCT output 10. Match output 3 of timer 3.

OLCD_VD23 — LCD data.

-R — Function reserved.

I/O GPIO5[20] — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 39 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PB_1 A14 - 175 - [2] N;

PU -R — Function reserved.

IUSB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP

data line direction.

OLCD_VD22 — LCD data.

-R — Function reserved.

I/O GPIO5[21] — General purpose digital input/output pin.

OCTOUT_6 — SCT output 6. Match output 2 of timer 1.

-R — Function reserved.

PB_2 B12 - 177 - [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.

OLCD_VD21 — LCD data.

-R — Function reserved.

I/O GPIO5[22] — General purpose digital input/output pin.

OCTOUT_7 — SCT output 7. Match output 3 of timer 1.

-R — Function reserved.

PB_3 A13 - 178 - [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.

OLCD_VD20 — LCD data.

-R — Function reserved.

I/O GPIO5[23] — General purpose digital input/output pin.

OCTOUT_8 — SCT output 8. Match output 0 of timer 2.

-R — Function reserved.

PB_4 B11 - 180 - [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.

OLCD_VD15 — LCD data.

-R — Function reserved.

I/O GPIO5[24] — General purpose digital input/output pin.

ICTIN_5 — SCT input 5. Capture input 2 of timer 2.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 40 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PB_5 A12 - 181 - [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.

OLCD_VD14 — LCD data.

-R — Function reserved.

I/O GPIO5[25] — General purpose digital input/output pin.

ICTIN_7 — SCT input 7.

OLCD_PWR — LCD panel power enable.

-R — Function reserved.

PB_6 A6 - - - [5] N;

PU -R — Function reserved.

I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.

OLCD_VD13 — LCD data.

-R — Function reserved.

I/O GPIO5[26] — General purpose digital input/output pin.

ICTIN_6 — SCT input 6. Capture input 1 of timer 3.

OLCD_VD19 — LCD data.

-R — Function reserved.

AI ADC0_6 — ADC0 and ADC1, input channel 6. Configure the

pin as GPIO input and use the ADC function select register

in the SCU to select the ADC.

PC_0 D4 - 7 - [5] N;

PU -R — Function reserved.

IUSB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock

generated by the PHY.

-R — Function reserved.

I/O ENET_RX_CLK — Ethernet Receive Clock (MII interface).

OLCD_DCLK — LCD panel clock.

-R — Function reserved.

I/O SD_CLK — SD/MMC card clock.

AI ADC1_1 — ADC1 and ADC0, input channel 1. Configure the

pin as input (USB_ULPI_CLK) and use the ADC function

select register in the SCU to select the ADC.

PC_1 E4 - 9 - [2] N;

PU I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.

-R — Function reserved.

IU1_RI — Ring Indicator input for UART 1.

OENET_MDC — Ethernet MIIM clock.

I/O GPIO6[0] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP0 — Capture input 0 of timer 3.

OSD_VOLT0 — SD/MMC bus voltage select output 0.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 41 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PC_2 F6 - 13 - [2] N;

PU I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.

-R — Function reserved.

IU1_CTS — Clear to Send input for UART 1.

OENET_TXD2 — Ethernet transmit data 2 (MII interface).

I/O GPIO6[1] — General purpose digital input/output pin.

-R — Function reserved.

OSD_RST — SD/MMC reset signal for MMC4.4 card.

PC_3 F5 - 11 - [5] N;

PU I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.

-R — Function reserved.

OU1_RTS — Request to Send output for UART 1. Can also

be configured to be an RS-485/EIA-485 output enable signal

for UART 1.

OENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O GPIO6[2] — General purpose digital input/output pin.

-R — Function reserved.

OSD_VOLT1 — SD/MMC bus voltage select output 1.

AI ADC1_0 — DAC, ADC1 and ADC0, input channel 0.

Configure the pin as GPIO input and use the ADC function

select register in the SCU to select the ADC.

PC_4 F4 - 16 - [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.

-R — Function reserved.

ENET_TX_EN — Ethernet transmit enable (RMII/MII

interface).

I/O GPIO6[3] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP1 — Capture input 1 of timer 3.

I/O SD_DAT0 — SD/MMC data bus line 0.

PC_5 G4 - 20 - [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.

-R — Function reserved.

OENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O GPIO6[4] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP2 — Capture input 2 of timer 3.

I/O SD_DAT1 — SD/MMC data bus line 1.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 42 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PC_6 H6 - 22 - [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.

-R — Function reserved.

IENET_RXD2 — Ethernet receive data 2 (MII interface).

I/O GPIO6[5] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP3 — Capture input 3 of timer 3.

I/O SD_DAT2 — SD/MMC data bus line 2.

PC_7 G5 - - - [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-R — Function reserved.

IENET_RXD3 — Ethernet receive data 3 (MII interface).

I/O GPIO6[6] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT0 — Match output 0 of timer 3.

I/O SD_DAT3 — SD/MMC data bus line 3.

PC_8 N4 - - - [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.

-R — Function reserved.

IENET_RX_DV — Ethernet Recei v e Data Valid (RMII/MII

interface).

I/O GPIO6[7] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT1 — Match output 1 of timer 3.

ISD_CD — SD/MMC card detect input.

PC_9 K2 - - - [2] N;

PU -R — Function reserved.

IUSB1_ULPI_NXT — ULPI link NXT signal. Data flow control

signal from the PHY.

-R — Function reserved.

IENET_RX_ER — Ethernet receive error (MII interface).

I/O GPIO6[8] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT2 — Match output 2 of timer 3.

OSD_POW — SD/MMC power monitor output.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 43 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PC_10 M5 - - - [2] N;

PU -R — Function reserved.

OUSB1_ULPI_STP — ULPI link STP signal. Asserte d to end

or interrupt transfers to the PHY.

IU1_DSR — Data Set Ready input for UART 1.

-R — Function reserved.

I/O GPIO6[9] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT3 — Match output 3 of timer 3.

I/O SD_CMD — SD/MMC command signal.

PC_11 L5 - - - [2] N;

PU -R — Function reserved.

IUSB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI

data line direction.

IU1_DCD — Data Carrier Detect input for UART 1.

-R — Function reserved.

I/O GPIO6[10] — General purpose digital input/output pin.

-R — Function reserved.

I/O SD_DAT4 — SD/MMC data bus line 4.

PC_12 L6 - - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OU1_DTR — Data Terminal Ready output for UART 1. Can

also be configured to be an RS-485/EIA-485 output enable

signal for UART 1.

-R — Function reserved.

I/O GPIO6[11] — General purpose digital input/output pin.

I/O SGPIO11 — General pu rpose digital input/output pin.

I/O I2S0_TX_SDA — I2S transmit data. It is driven by the

transmitter and read by the receiver . Corresponds to the

signal SD in the I2S-bus specification.

I/O SD_DAT5 — SD/MMC data bus line 5.

PC_13 M1 - - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OU1_TXD — Transmitter output for UART 1.

-R — Function reserved.

I/O GPIO6[12] — General purpose digital input/output pin.

I/O SGPIO12 — General purpose digital input/output pin.

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

I/O SD_DAT6 — SD/MMC data bus line 6.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 44 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PC_14 N1 - - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

IU1_RXD — Receiver input for UART 1.

-R — Function reserved.

I/O GPIO6[13] — General purpose digital input/output pin.

I/O SGPIO13 — General purpose digital input/output pin.

OENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O SD_DAT7 — SD/MMC data bus line 7.

PD_0 N2 - - - [2] N;

PU -R — Function reserved.

OCTOUT_15 — SCT output 15. Match output 3 of timer 3.

OEMC_DQMOUT2 — Data mask 2 used with SDRAM and

static devices.

-R — Function reserved.

I/O GPIO6[14] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO4 — General purpose digital input/output pin.

PD_1 P1 - - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OEMC_CKEOUT2 — SDRAM clock enable 2.

-R — Function reserved.

I/O GPIO6[15] — General purpose digital input/output pin.

OSD_POW — SD/MMC power monitor output.

-R — Function reserved.

I/O SGPIO5 — General purpose digital input/output pin.

PD_2 R1 - - - [2] N;

PU -R — Function reserved.

OCTOUT_7 — SCT output 7. Match output 3 of timer 1.

I/O EMC_D16 — External memory data line 16.

-R — Function reserved.

I/O GPIO6[16] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO6 — General purpose digital input/output pin.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 45 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PD_3 P4 - - - [2] N;

PU -R — Function reserved.

OCTOUT_6 — SCT output 7. Match output 2 of timer 1.

I/O EMC_D17 — External memory data line 17.

-R — Function reserved.

I/O GPIO6[17] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO7 — General purpose digital input/output pin.

PD_4 T2 - - - [2] N;

PU -R — Function reserved.

OCTOUT_8 — SCT output 8. Match output 0 of timer 2.

I/O EMC_D18 — External memory data line 18.

-R — Function reserved.

I/O GPIO6[18] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO8 — General purpose digital input/output pin.

PD_5 P6 - - - [2] N;

PU -R — Function reserved.

OCTOUT_9 — SCT output 9. Match output 3 of timer 3.

I/O EMC_D19 — External memory data line 19.

-R — Function reserved.

I/O GPIO6[19] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO9 — General purpose digital input/output pin.

PD_6 R6 - 68 - [2] N;

PU -R — Function reserved.

OCTOUT_10 — SCT output 10. Match output 3 of timer 3.

I/O EMC_D20 — External memory data line 20.

-R — Function reserved.

I/O GPIO6[20] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO10 — General purpose digital input/output pin.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 46 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PD_7 T6 - 72 - [2] N;

PU -R — Function reserved.

ICTIN_5 — SCT input 5. Capture input 2 of timer 2.

I/O EMC_D21 — External memory data line 21.

-R — Function reserved.

I/O GPIO6[21] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO11 — General pu rpose digital input/output pin.

PD_8 P8 - 74 - [2] N;

PU -R — Function reserved.

ICTIN_6 — SCT input 6. Capture input 1 of timer 3.

I/O EMC_D22 — External memory data line 22.

-R — Function reserved.

I/O GPIO6[22] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO12 — General purpose digital input/output pin.

PD_9 T11 - 84 - [2] N;

PU -R — Function reserved.

OCTOUT_13 — SCT output 13. Match output 3 of timer 3.

I/O EMC_D23 — External memory data line 23.

-R — Function reserved.

I/O GPIO6[23] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO13 — General purpose digital input/output pin.

PD_10 P11 - 86 - [2] N;

PU -R — Function reserved.

ICTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture

input 1 of timer 2.

OEMC_BLS3 — LOW active Byte Lan e select signal 3.

-R — Function reserved.

I/O GPIO6[24] — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 47 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PD_11 N9 - 88 - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OEMC_CS3 — LOW active Chip Select 3 signal.

-R — Function reserved.

I/O GPIO6[25] — General purpose digital input/output pin.

I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.

OCTOUT_14 — SCT output 14. Match output 2 of timer 3.

-R — Function reserved.

PD_12 N11 - 94 - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OEMC_CS2 — LOW active Chip Select 2 signal.

-R — Function reserved.

I/O GPIO6[26] — General purpose digital input/output pin.

-R — Function reserved.

OCTOUT_10 — SCT output 10. Match output 3 of timer 3.

-R — Function reserved.

PD_13 T14 - 97 - [2] N;

PU -R — Function reserved.

ICTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

OEMC_BLS2 — LOW active Byte Lan e select signal 2.

-R — Function reserved.

I/O GPIO6[27] — General purpose digital input/output pin.

-R — Function reserved.

OCTOUT_13 — SCT output 13. Match output 3 of timer 3.

-R — Function reserved.

PD_14 R13 - 99 - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OEMC_DYCS2 — SDRAM chip select 2.

-R — Function reserved.

I/O GPIO6[28] — General purpose digital input/output pin.

-R — Function reserved.

OCTOUT_11 — SCT output 11. Match output 3 of timer 2.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 48 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PD_15 T15 - 101 - [2] N;

PU -R — Function reserved.

-R — Function reserved.

I/O EMC_A17 — External memory address line 17.

-R — Function reserved.

I/O GPIO6[29] — General purpose digital input/output pin.

ISD_WP — SD/MMC card write protect input.

OCTOUT_8 — SCT output 8. Match output 0 of timer 2.

-R — Function reserved.

PD_16 R14 - 104 - [2] N;

PU -R — Function reserved.

-R — Function reserved.

I/O EMC_A16 — External memory address line 16.

-R — Function reserved.

I/O GPIO6[30] — General purpose digital input/output pin.

OSD_VOLT2 — SD/MMC bus voltage select output 2.

OCTOUT_12 — SCT output 12. Match output 3 of timer 3.

-R — Function reserved.

PE_0 P14 - 106 - [2] N;

PU -R — Function reserved.

-R — Function reserved.

I/O EMC_A18 — External memory address line 18.

I/O GPIO7[0] — General purpose digital input/output pin.

OCAN1_TD — CAN1 transmitter output.

-R — Function reserved.

PE_1 N14 - 112 - [2] N;

PU -R — Function reserved.

-R — Function reserved.

I/O EMC_A19 — External memory address line 19.

I/O GPIO7[1] — General purpose digital input/output pin.

ICAN1_RD — CAN1 receiver input.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 49 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PE_2 M14 - 115 - [2] N;

PU IADCTRIG0 — ADC trigger input 0.

ICAN0_RD — CAN receive r input.

-R — Function reserved.

I/O EMC_A20 — External memory address line 20.

I/O GPIO7[2] — General purpose digital input/output pin.

-R — Function reserved.

PE_3 K12 - 118 - [2] N;

PU -R — Function reserved.

OCAN0_TD — CAN transmitter output.

IADCTRIG1 — ADC trigger input 1.

I/O EMC_A21 — External memory address line 21.

I/O GPIO7[3] — General purpose digital input/output pin.

-R — Function reserved.

PE_4 K13 - 120 - [2] N;

PU -R — Function reserved.

INMI — External interrupt input to NMI.

-R — Function reserved.

I/O EMC_A22 — External memory address line 22.

I/O GPIO7[4] — General purpose digital input/output pin.

-R — Function reserved.

PE_5 N16 - 122 - [2] N;

PU -R — Function reserved.

OCTOUT_3 — SCT output 3. Match output 3 of timer 0.

OU1_RTS — Request to Send output for UART 1. Can also

be configured to be an RS-485/EIA-485 output enable signal

for UART 1.

I/O EMC_D24 — External memory data line 24.

I/O GPIO7[5] — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 50 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PE_6 M16 - 124 - [2] N;

PU -R — Function reserved.

OCTOUT_2 — SCT output 2. Match output 2 of timer 0.

IU1_RI — Ring Indicator input for UART 1.

I/O EMC_D25 — External memory data line 25.

I/O GPIO7[6] — General purpose digital input/output pin.

-R — Function reserved.

PE_7 F15 - 149 - [2] N;

PU -R — Function reserved.

OCTOUT_5 — SCT output 5. Match output 3 of timer 3.

IU1_CTS — Clear to Send input for UART1.

I/O EMC_D26 — External memory data line 26.

I/O GPIO7[7] — General purpose digital input/output pin.

-R — Function reserved.

PE_8 F14 - 150 - [2] N;

PU -R — Function reserved.

OCTOUT_4 — SCT output 4. Match output 3 of timer 3.

IU1_DSR — Data Set Ready input for UART 1.

I/O EMC_D27 — External memory data line 27.

I/O GPIO7[8] — General purpose digital input/output pin.

-R — Function reserved.

PE_9 E16 - 152 - [2] N;

PU -R — Function reserved.

ICTIN_4 — SCT input 4. Capture input 2 of timer 1.

IU1_DCD — Data Carrier Detect input for UART 1.

I/O EMC_D28 — External memory data line 28.

I/O GPIO7[9] — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 51 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PE_10 E14 - 154 - [2] N;

PU -R — Function reserved.

ICTIN_3 — SCT input 3. Capture input 1 of timer 1.

OU1_DTR — Data Terminal Ready output for UART 1. Can

also be configured to be an RS-485/EIA-485 output enable

signal for UART 1.

I/O EMC_D29 — External memory data line 29.

I/O GPIO7[10] — General purpose digital input/output pin.

-R — Function reserved.

PE_11 D16 - - - [2] N;

PU -R — Function reserved.

OCTOUT_12 — SCT output 12. Match output 3 of timer 3.

OU1_TXD — Transmitter output for UART 1.

I/O EMC_D30 — External memory data line 30.

I/O GPIO7[11] — General purpose digital input/output pin.

-R — Function reserved.

PE_12 D15 - - - [2] N;

PU -R — Function reserved.

OCTOUT_11 — SCT output 11. Match output 3 of

timer 2.

IU1_RXD — Receiver input for UART 1.

I/O EMC_D31 — External memory data line 31.

I/O GPIO7[12] — General purpose digital input/output pin.

-R — Function reserved.

PE_13 G14 - - - [2] N;

PU -R — Function reserved.

OCTOUT_14 — SCT output 14. Match output 2 of timer 3.

I/O I2C1_SDA — I2C1 data input/output (this pin does not use a

specialized I2C pad).

OEMC_DQMOUT3 — Data mask 3 used with SDRAM and

static devices.

I/O GPIO7[13] — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 52 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PE_14 C15 - - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OEMC_DYCS3 — SDRAM chip select 3.

I/O GPIO7[14] — General purpose digital input/output pin.

-R — Function reserved.

PE_15 E13 - - - [2] N;

PU -R — Function reserved.

OCTOUT_0 — SCT output 0. Match output 0 of timer 0.

I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a

specialized I2C pad).

OEMC_CKEOUT3 — SDRAM clock enable 3.

I/O GPIO7[15] — General purpose digital input/output pin.

-R — Function reserved.

PF_0 D12 - 159 - [2] O;

PU I/O SSP0_SCK — Serial clock for SSP0.

IGP_CLKIN — General purpose clock input to the CGU.

-R — Function reserved.

OI2S1_TX_MCLK — I2S1 transmit master clock.

PF_1 E11 - - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

I/O SSP0_SSEL — Slave Select for SSP0.

-R — Function reserved.

I/O GPIO7[16] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO0 — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 53 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PF_2 D11 - 168 - [2] N;

PU -R — Function reserved.

OU3_TXD — Transmitter output for USART3.

I/O SSP0_MISO — Master In Slave Out for SSP0.

-R — Function reserved.

I/O GPIO7[17] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO1 — General purpose digital input/output pin.

-R — Function reserved.

PF_3 E10 - 170 - [2] N;

PU -R — Function reserved.

IU3_RXD — Receiver input for USART3.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

-R — Function reserved.

I/O GPIO7[18] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO2 — General purpose digital input/output pin.

-R — Function reserved.

PF_4 D10 H4 172 120 [2] O;

PU I/O SSP1_SCK — Serial clock for SSP1.

IGP_CLKIN — General purpose clock input to the CGU.

OTRACECLK — Trace clock.

-R — Function reserved.

OI2S0_TX_MCLK — I2S transmit master clock.

I/O I2S0_RX_SCK — I2S receive clock. It is driven by the

master and received by the slave. Corresponds to the signal

SCK in the I2S-bus specification.

PF_5 E9 - 190 - [5] N;

PU -R — Function reserved.

I/O U3_UCLK — Serial clock input/output for USART3 in

synchronous mode.

I/O SSP1_SSEL — Slave Select for SSP1.

OTRACEDATA[0] — T race data, bit 0.

I/O GPIO7[19] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO4 — General purpose digital input/output pin.

-R — Function reserved.

AI ADC1_4 — ADC1 and ADC0, input channel 4. Configure the

pin as GPIO input and use the ADC function select register

in the SCU to select the ADC.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 54 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PF_6 E7 - 192 - [5] N;

PU -R — Function reserved.

I/O U3_DIR — RS-485/EIA-485 outpu t enable/direction control

for USART3.

I/O SSP1_MISO — Master In Slave Out for SSP1.

OTRACEDATA[1] — T race data, bit 1.

I/O GPIO7[20] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO5 — General purpose digital input/output pin.

I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the

transmitter and read by the receiver . Corresponds to the

signal SD in the I2S-bus specification.

AI ADC1_3 — ADC1 and ADC0, input channel 3. Configure the

pin as GPIO input and use the ADC function select register

in the SCU to select the ADC.

PF_7 B7 - 193 - [5] N;

PU -R — Function reserved.

I/O U3_BAUD — Baud pin for USART 3.

I/O SSP1_MOSI — Master Out Slave in for SSP1.

OTRACEDATA[2] — T race data, bit 2.

I/O GPIO7[21] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO6 — General purpose digital input/output pin.

I/O I2S1_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

AI/

OADC1_7 — ADC1 and ADC0, input channel 7 or band gap

output. Configure the pin as GPIO input and use the ADC

function select register in the SCU to select the ADC.

PF_8 E6 - - - [5] N;

PU -R — Function reserved.

I/O U0_UCLK — Serial clock input/output for USART0 in

synchronous mode.

ICTIN_2 — SCT input 2. Capture input 2 of timer 0.

OTRACEDATA[3] — T race data, bit 3.

I/O GPIO7[22] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO7 — General purpose digital input/output pin.

-R — Function reserved.

AI ADC0_2 — ADC0 and ADC1, input channel 2. Configure the

pin as GPIO input and use the ADC function select register

in the SCU to select the ADC.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 55 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

PF_9 D6 - 203 - [5] N;

PU -R — Function reserved.

I/O U0_DIR — RS-485/EIA-485 outpu t enable/direction control

for USART0.

OCTOUT_1 — SCT output 1. Match output 3 of timer 3.

-R — Function reserved.

I/O GPIO7[23] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO3 — General purpose digital input/output pin.

-R — Function reserved.

AI ADC1_2 — ADC1 and ADC0, input channel 2. Configure the

pin as GPIO input and use the ADC function select register

in the SCU to select the ADC.

PF_10 A3 - 205 - [5] N;

PU -R — Function reserved.

OU0_TXD — Transmitter output for USART0.

-R — Function reserved.

I/O GPIO7[24] — General purpose digital input/output pin.

-R — Function reserved.

ISD_WP — SD/MMC card write protect input.

-R — Function reserved.

AI ADC0_5 — ADC0 and ADC1, input channel 5. Configure the

pin as GPIO input and use the ADC function select register

in the SCU to select the ADC.

PF_11 A2 - 207 - [5] N;

PU -R — Function reserved.

IU0_RXD — Receiver input for USART0.

-R — Function reserved.

I/O GPIO7[25] — General purpose digital input/output pin.

-R — Function reserved.

OSD_VOLT2 — SD/MMC bus voltage select output 2.

-R — Function reserved.

AI ADC1_5 — ADC1 and ADC0, input channel 5. Configure the

pin as GPIO input and use the ADC function select register

in the SCU to select the ADC.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 56 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

Clock pins

CLK0 N5 K3 62 45 [4] O;

PU OEMC_CLK0 — SDRAM clock 0.

OCLKOUT — Clock output pin.

-R — Function reserved.

I/O SD_CLK — SD/MMC card clock.

OEMC_CLK01 — SDRAM clock 0 and clock 1 combined.

I/O SSP1_SCK — Serial clock for SSP1.

IENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit

Clock (MII interface) or Ethernet Reference Clock (RMII

interface).

CLK1 T10 - - - [4] O;

PU OEMC_CLK1 — SDRAM clock 1.

OCLKOUT — Clock output pin.

-R — Function reserved.

OCGU_OUT0 — CGU spare clock output 0.

-R — Function reserved.

OI2S1_TX_MCLK — I2S1 transmit master clock.

CLK2 D14 K6 141 99 [4] O;

PU OEMC_CLK3 — SDRAM clock 3.

OCLKOUT — Clock output pin.

-R — Function reserved.

I/O SD_CLK — SD/MMC card clock.

OEMC_CLK23 — SDRAM clock 2 and clock 3 combined.

OI2S0_TX_MCLK — I2S transmit master clock.

I/O I2S1_RX_SCK — Receive Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I2S-bus specification.

CLK3 P12 - - - [4] O;

PU OEMC_CLK2 — SDRAM clock 2.

OCLKOUT — Clock output pin.

-R — Function reserved.

OCGU_OUT1 — CGU spare clock output 1.

-R — Function reserved.

I/O I2S1_RX_SCK — Receive Clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in

the I2S-bus specification.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 57 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

Debug pins

DBGEN L4 A6 41 28 [2] I I JTAG inte rface control signal. Also used for boundary scan.

To use the part in functional mode, connect this pin in one of

the following ways:

•Leave DBGEN open. The DBGEN pin is pulled up

internally by a 50 kΩ resistor .

•Tie DBGEN to VDDIO.

•Pull DBGEN up to VDDIO with an external pull-up

resistor.

TCK/SWDCLK J5 H2 38 27 [2] I; F I Test Clock for JTAG interface (default) or Serial Wire (SW)

clock.

TRST M4 B4 42 29 [2] I; PU I Test Reset for JTAG interface.

TMS/SWDIO K6 C4 44 30 [2] I; PU I Test Mode Select for JTAG interface (default) or SW debug

data input/output.

TDO/SWO K5 H3 46 31 [2] O O Test Data Out for JTAG interface (default) or SW trace

output.

TDI J4 G3 35 26 [2] I; PU I Test Data In for JTAG interface.

USB0 pins

USB0_DP F2 E1 26 18 [6] - I/O USB0 bidirectional D+ line. Do not add an external series

resistor.

USB0_DM G2 E2 28 20 [6] - I/O USB0 bidirectional D line. Do not add an external series

resistor.

USB0_VBUS F1 E3 29 21 [6][7] - I VBUS pin (power on USB cable). This pin includes an

internal pull-down resistor of 64 k (typical)  16 k.

USB0_ID H2 F1 30 22 [8] - I Indicates to the transceiver whether connected as an

A-device (USB0 _ID LOW) or B-device ( USB0_ID HIGH). For

OTG this pin has an internal pull-up resistor.

USB0_RREF H1 F3 32 24 [8] - 12.0 k (accuracy 1 %) on-board resistor to ground for

current reference.

USB1 pins

USB1_DP F12 E9 129 89 [9] - I/O USB1 bidirectional D+ line. Add an external series resistor of

33  +/- 2 %.

USB1_DM G12 E10 130 90 [9] - I/O USB1 bidirectional D line. Add an external series resistor of

33  +/- 2 %.

I2C-bus pins

I2C0_SCL L15 D6 132 92 [10] I; F I/O I2C clock input/output. Open-drain output (for I2C-bus

compliance).

I2C0_SDA L16 E6 133 93 [10] I; F I/O I2C data input/output. Open-drain output (fo r I2C-bus

compliance).

Reset and wake-up pins

RESET D9 B6 185 128 [11] I; IA I External reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default

states, and processor execution to begi n at address 0. T his

pin does not have an internal pull-up.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 58 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

WAKEUP0 A9 A4 187 130 [11] I; IA I External wake-up input; can raise an interrupt and can cause

wake-up from any of the low power modes. A pulse with a

duration of at least 45 ns wakes up the part.

Input 0 of the event monitor.No internal pull-up is enabled

when this pin is configured as input.

WAKEUP1 A10 - - - [11] I; IA I External wake-up input; can raise an interrupt and can cause

wake-up from any of the low power modes. A pulse with a

duration of at least 45 ns wakes up the part.

Input 1 of the event monitor. No internal pull-up is enabled

when this pin is configured as input.

WAKEUP2 C9 - - - [11] I; IA I External wake-up input; can raise an interrupt and can cause

wake-up from any of the low power modes. A pulse with a

duration of at least 45 ns wakes up the part.

Input 2 of the event monitor. This pin does not have an

internal pu l l-up.

WAKEUP3 D8 - - - [11] I; IA I External wake-up input; can raise an interrupt and can cause

wake-up from any of the low power modes. A pulse with a

duration of at least 45 ns wakes up the part. This pin does

not have an internal pull-up.

ADC pins

ADC0_0/

ADC1_0/DAC E3 A2 8 6 [8] I; IA I ADC input channel 0. Shared between 10-bit ADC0/1 and

DAC.

ADC0_1/

ADC1_1 C3 A1 4 2 [8] I; IA I ADC input channel 1. Shared between 10-bit ADC0/1.

ADC0_2/

ADC1_2 A4 B3 206 143 [8] I; IA I ADC input channel 2. Shared between 10-bit ADC0/1.

ADC0_3/

ADC1_3 B5 A3 200 139 [8] I; IA I ADC input channel 3. Shared between 10-bit ADC0/1.

ADC0_4/

ADC1_4 C6 - 199 138 [8] I; IA I A DC input channel 4. Shared between 10-bit ADC0/1.

ADC0_5/

ADC1_5 B3 - 208 144 [8] I; IA I A DC input channel 5. Shared between 10-bit ADC0/1.

ADC0_6/

ADC1_6 A5 - 204 142 [8] I; IA I A DC input channel 6. Shared between 10-bit ADC0/1.

ADC0_7/

ADC1_7 C5 - 197 136 [8] I; IA I A DC input channel 7. Shared between 10-bit ADC0/1.

RTC

RTC_ALARM A11 C3 186 129 [11] - O RTC controlled output.

RTCX1 A8 A5 182 125 [8] - I Input to the RTC 32 kHz ultra-low power oscillator circuit.

RTCX2 B8 B5 183 126 [8] - O Output from the RTC 32 kHz ultra-low power oscillator

circuit.

SAMPLE B9 - - - [11] O O Event monitor sample output.

Crystal oscillator pins

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 59 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

XTAL1 D1 B1 18 12 [8] - I In put to the oscillator circuit and internal clock generator

circuits.

XTAL2 E1 C1 19 13 [8] - O Output from the oscillator amplifier.

Power and ground pins

USB0_VDDA

3V3_DRIVER F3 D1 24 16 - - Separate analog 3.3 V power supply for driver.

USB0

_VDDA3V3 G3 D2 25 17 - - USB 3.3 V separate power supply voltage.

USB0_VSSA

_TERM H3 D3 27 19 - - Dedicated analog ground for clean reference for termination

resistors.

USB0_VSSA

_REF G1 F2 31 23 - - Dedi cated clean analog ground for ge neration of reference

currents and voltages.

VDDA B4 B2 198 137 - - Analog power supply and ADC reference voltage.

VBAT B10 C5 184 127 - - RTC power supply: 3.3 V on this pin supplies power to the

RTC.

VDDREG F10,

F9,

L8,

E4,

E5,

135,

188,

195,

82,

94,

131,

59,

- Main regulator power supply. Tie the VDDREG and VDDIO

pins to a common power supply to ensure the same ramp-up

time for both supply voltages.

VPP E8 - - - [12] - - OTP programming voltage.

VDDIO D7,

E12,

F7,

F8,

G10,

H10,

J6,

J7,

K7,

L9,

L10,

N7,

N13

F10,

K5 6,

52,

57,

102,

110,

155,

160,

202

36,

41,

71,

77,

107,

111,

141

[12] - - I/O power supply. Tie the VDDREG and VDDIO pins to a

common power supply to ensure the same ramp-up time for

both supply voltages.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 60 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

[1] N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in

the SFS register to enable the input buffer; I = input, OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA

= inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset

without boot code operation.

[2] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O

functions with TTL levels and hysteresis; normal drive strength.

[3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O

functions with TTL levels, and hysteresis; high drive strength.

[4] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides high-speed

digital I/O functions with TTL levels and hysteresis.

[5] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present;

if VDDIO not present, do not exceed 3.6 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital

section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP

[6] 5 V tolerant transparent analog pad.

[7] For maximum load CL = 6.5 F and maximum resistance Rpd = 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS

= 0.2 V when it is no longer driven.

[8] Transparent analog pad. Not 5 V tolerant.

[9] Pad provides USB functions; 5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V. It is designed in accordance with

the USB specification, revision 2.0 (Full-speed and Low-speed mode only).

[10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to

provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output and hysteresis.

[12] VPP is internally connected to VDDIO for all packages with the exception of the LBGA256 package.

[13] On the LQFP208 package, VSSIO and VSS are connected to a common ground plane.

VSS G9,

H7,

J10,

J11,

C8,

D4,

D5,

G8,

J3,

--[13] - - Ground.

VSSIO C4,

D13,

G6,

G7,

G8,

H8,

H9,

J8,

J9,

K9,

K10,

M13,

P7,

P13

-5,

56,

109,

157

40,

76,

109

[13] - - Ground.

VSSA B2 C2 196 135 - - Analog ground.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA100

LQFP208

LQFP144

Reset state

[1]

Type

Description

Product data sheet Rev. 5.2 — 26 November 2015 61 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7. Functional description

7.1 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-CODE bus,

and the D-code bus. The I-CODE and D-code core buses allow for concurrent code and

data accesses from different slave ports.

The LPC435x/3x/2x/1x use a multi-layer AHB matrix to connect the ARM Cortex-M4

buses and othe r bu s ma st er s to perip he ra ls in a flex ible ma nn er tha t op tim izes

performance by allowing peripherals that are on different slaves ports of the matrix to be

accessed simultaneously by different bus masters.

An ARM Cortex-M0 co-processor is included in the LPC435x/3x/2x/1x, capa ble of

off-lo ading the main ARM Cortex-M4 application pr ocessor. Most peripheral interrupt s are

connected to both processors. The processors communicate with each other via an

interprocessor communication protocol.

7.2 ARM Cortex-M4 processor

The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture

with separate local instruction and data buses as well as a third bus for peripherals, and

includes an internal prefetch unit that supports speculative branching. The ARM

Cortex-M4 supp or ts single-cy cle dig ital signal processing and SIMD instructions. A

hardware floating-point processor is integrated in the core. The processor includes an

NVIC with up to 53 interrupts.

7.3 ARM Cortex-M0 co-processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Co rtex-M0 co -proce ssor uses a

3-stage pipeline von Neumann architecture and a small but powerful instruction set

providing high-end proc essing hardware. In LPC43xx, the Cortex-M0 coprocessor

hardware multiply is implemented as a 32-cycle iterative multiplier. The co-processor

incorporates an NVIC with 32 interrupts.

7.4 Interprocessor communication

The ARM Cortex-M4 and ARM Cortex-M0 interprocessor communication is based on

using shared SRAM as mailbox and one processor raising an interrupt on the other

processor's NVIC, for example after it has delivered a new message in the mailbox. The

receiving processor can reply by raising an interrupt on the sending processor's NVIC to

acknowledge the message.

Product data sheet Rev. 5.2 — 26 November 2015 62 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.5 AHB multilayer matrix

7.6 Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral p art of the Cortex-M4. The tight co upling to the CPU allows for low

interrupt latency and efficient processing of late arriving interrupts.

The ARM Cortex-M0 co-processor has its own NVIC with 32 vectored interrupts. Most

peripheral interrupts are shared between the Cortex-M0 and Cortex-M4 NVICs.

Fig 6. AHB multilayer matrix master and slave connections

ARM

CORTEX-M4

TEST/DEBUG

INTERFACE

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

DMA ETHERNET USB1USB0 LCD SD/

MMC

EXTERNAL

MEMORY

CONTROLLER

APB, RTC

DOMAIN

PERIPHERALS

HIGH-SPEED PHY

System

bus

I-

code

bus

D-

code

bus

masters

AHB MULTILAYER MATRIX

= master-slave connection

SPIFI

AHB PERIPHERALS

INTERFACES

002aah080

32 kB AHB SRAM

16 kB AHB SRAM

slaves

64 kB ROM

32 kB LOCAL SRAM

40 kB LOCAL SRAM

256/512 kB FLASH A

256/512 kB FLASH B

16 kB EEPROM

Product data sheet Rev. 5.2 — 26 November 2015 63 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.6.1 Features

•ARM Cortex-M4 core:

–Controls system exceptions and periphe ral interrupts

–Support for up to 53 vectored interrupts

–Eight programmable interrupt priority levels with hardware priority level masking

–Relocatable vector table

–Non-Maskable Interrupt (NMI)

–Software interrupt generation

•ARM Cortex-M0 core:

–Support for up to 32 interrupts

–Four programmable interrupt priority levels with hardware priority level masking

7.6.2 Interrupt sources

Each peripheral devi ce has one interrupt line conne cted to the NVIC but may have several

interrupt flags. Individual interrup t flags may also represent more than one interrupt

source.

7.7 System Tick timer (SysTick)

The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.

Remark: The SysTick is not included in the ARM Cortex-M0 core implementation.

7.8 Event router

The event router combines various internal signals, interrupts, and the external interrupt

pins (WAKEUP[3:0]) to create an interrupt in the NVIC, if enabled. In addition, the event

router creates a wake-up signal to the ARM core and the CCU for waking up from Sleep,

Deep-sleep, Power-down, and Deep power- down modes. Individual events can be

configured as edge or level sensitive and can be enabled or disabled in the event router.

The event router can be battery powered.

The following events if enabled in the event router can create a wake-up signal from

sleep, deep-sleep, power-down, and deep power-down modes and/or create an interrupt:

•External pins WAKEUP0/1/2/3 and RESET

•Alarm timer, RTC (32 kHz oscillator running)

The following events if enab led in the event router can create a wa ke-up signal from sleep

mode only and/or create an interrupt:

•WWDT, BOD interrupts.

•C_CAN0/1 and QEI interrupts.

•Ethernet, USB0, USB1 signals.

•Selected outputs of combined timers (SCTimer/PWM and timer0/1/3).

Product data sheet Rev. 5.2 — 26 November 2015 64 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

Remark: Any interrupt can wake up the ARM Cortex-M4 from sleep mode if enabled in

the NVIC.

7.9 Global Input Multiplexer Array (GIMA)

The GIMA allows to route signals to event-driven peripheral tar gets like the

SCTimer/PWM, timers, event router, or the ADCs.

7.9.1 Features

•Single selection of a source.

•Signal inversion.

•Can capture a pulse if the input event source is faster than the target clock.

•Synchronization of input event and target clock.

•Single-cycle pulse gener ation for target.

7.10 On-chip static RAM

The LPC435x/3x/2x/1x support up to 136 kB SRAM with separate bus master access for

higher throughput and individual power control for low power operation.

7.11 On-chip flash memory

The LPC435x/3x/2x/1x contain up to 1 MB of dual-bank flash program memory. With

dual-bank flash memory, the user code can write or erase one flash bank while reading

the other flash bank without interruption. A two-port flash accelerator maximizes the flash

performance.

In-System Programming (ISP) and In-Application Programming (IAP) routines for

programming the flash memory are provided in the Boot ROM.

7.12 EEPROM

The LPC435x/3x/2x/1x contain 16 kB of on-chip byte-erasable a nd byte-programmable

EEPROM memory.

The EEPROM memory is divided into 128 pages. The user can access pages 1 through

127. Page 128 is protected.

7.13 Boot ROM

The internal ROM memor y is used to store the boot code of the LPC435x/3x/2x/1x. After a

reset, the ARM processor will start its code execution from this memory.

The boot ROM memory includes the following features:

•The ROM memory size is 64 kB.

•Supports bo oting from external st atic memory such as NOR flash, SPI flash, quad SPI

flash, USB0, and USB1.

•Includes API for OTP progra mming.

•Includes a flexible USB device stack that supports Human Interface Devic e (HI D ),

Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.

Product data sheet Rev. 5.2 — 26 November 2015 65 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

Several boot modes are available if P2_ 7 is LOW on reset depe nding on the values of the

OTP bits BOOT_SRC. If the OTP memory is not programmed or the BOOT_SRC bit s are

all zero, the boot mode is determine d by the states of the boot pins P2_9, P2_8, P1_2,

and P1_1.

[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.

Remark: Pin functions for SPIFI and SSP0 boot are different.

Table 4. Boot mode when OTP BOOT_SRC bits are programmed

Boot mode BOOT_SRC

bit 3 BOOT_SRC

bit 2 BOOT_SRC

bit 1 BOOT_SRC

bit 0 Description

Pin state 0 0 0 0 Boot source is defined by the reset state of P1_1,

P1_2, P2_8 pins , an d P2_9 . Se e Table 5.

USART0 0 0 0 1 E nter ISP mode using USART0 pins P2_0 and

P2_1.

SPIFI 0 0 1 0 Boot from Quad SPI flash connected to the SPIFI

interface using pins P3_3 to P3_8.

EMC 8-bit 0 0 1 1 Boot from external static memory (such as NOR

flash) using CS0 and an 8-bit data bus.

EMC 16-bit 0 1 0 0 Boot from external static memory (such as NOR

flash) using CS0 and a 16-bit data bus.

EMC 32-bit 0 1 0 1 Boot from external static memory (such as NOR

flash) using CS0 and a 32-bit data bus.

USB0011 0Boot from USB0.

USB1011 1Boot from USB1.

SPI (SSP) 1 0 0 0 Boot fro m SPI flash connected to the SSP0

interface on P3_3 (fu nction SSP0_SCK), P3_6

(function SSP0_SSEL), P3_7 (function

SSP0_MISO), and P3_8 (function SSP0_MOSI)[1].

USART3 1 0 0 1 E nter ISP mode using USART3 pins P2_3 and

P2_4.

Table 5. Boot mode when OPT BOOT_SRC bits are zero

Boot mode Pins Description

P2_9 P2_8 P1_2 P1_1

USART0 LOW LOW LOW LOW Enter ISP mode using USART0 pins P2_0 and

P2_1.

SPIFI LOW LOW LOW HIGH Boot from Quad SPI flash connected to the SPIFI

interface on P3_3 to P3_8[1].

EMC 8-bit LOW LOW HIGH LOW Boot from external static memory (such as NOR

flash) using CS0 and an 8-bit data bus.

EMC 16-bit LOW LOW HIGH HIGH Boot from external static memory (such as NOR

flash) using CS0 and a 16-bit data bus.

EMC 32-bit LOW HIGH LOW LOW Boot from external static memory (such as NOR

flash) using CS0 and a 32-bit data bus.

USB0 LOW HIGH LOW HIGH Boot from USB0

Product data sheet Rev. 5.2 — 26 November 2015 66 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.

Remark: Pin functions for SPIFI and SSP0 boot are different.

7.14 Memory mapping

The memory map shown in Figure 7 and Figure 8 is global to b oth th e Cor tex-M4 a nd the

Cortex-M0 processors and all SRAM, flash, and EEPROM memory is shared between

both processors. Each processor uses its own ARM private bus memory map for the

NVIC and other system functions.

USB1 LOW HIGH HIGH LOW Boot from USB1.

SPI (SSP) LOW HIGH HIGH HIGH Boot from SPI flash connected to the SSP0

interface on P3_3 (function SSP0_SCK), P3_6

(function SSP0_SSEL), P3_7 (function

SSP0_MISO), and P3_8 (function SSP0_MOSI) [1]

USART3 HIGH LOW LOW LOW Enter ISP mode using USART3 pins P2_3 and

P2_4.

Table 5. Boot mode when OPT BOOT_SRC bits are zero

Boot mode Pins Description

P2_9 P2_8 P1_2 P1_1

Product data sheet Rev. 5.2 — 26 November 2015 67 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

Fig 7. LPC435x/3x/2x/1x Memory mapping (overview)

reserved

peripheral bit band alias region

reserved

high-speed GPIO

reserved

0x0000 0000

0 GB

1 GB

4 GB

0x2200 0000

0x2400 0000

0x2800 0000

0x1000 0000

0x3000 0000

0x4000 0000

0x4001 2000

0x4004 0000

0x4005 0000

0x4010 0000

0x4400 0000

0x6000 0000

AHB peripherals

APB peripherals #0

APB peripherals #1

reserved

RTC domain peripherals

0x4006 0000

0x4008 0000

0x4009 0000

0x400A 0000

0x400B 0000

0x400C 0000

0x400D 0000

0x400E 0000

0x400F 0000

0x400F 1000

0x400F 2000

0x400F 4000

0x400F 8000

clocking/reset peripherals

APB peripherals #2

APB peripherals #3

0x2004 0000

4 x 16 kB AHB SRAM

0x2004 4000

16 kB EEPROM

SGPIO

SPI

0x4010 1000

0x4010 2000

0x4200 0000

reserved

local SRAM/flash/SPIFI data/ROM

external static memory banks

0x2000 0000

0x2001 0000

128 MB dynamic external memory DYCS0

256 MB dynamic external memory DYCS1

256 MB dynamic external memory DYCS2

256 MB dynamic external memory DYCS3 0x7000 0000

0x8000 0000

0x8800 0000

0xE000 0000

256 MB shadow area

LPC435x/3x/2x/1x

reserved

32 MB AHB SRAM bit banding

reserved

0xE010 0000

0xFFFF FFFF

reserved

128 MB SPIFI data

ARM private bus

reserved

002aah182

reserved

0x1000 0000

0x1000 8000

0x1008 0000

0x1008 A000

0x1040 0000

0x1041 0000

0x1C00 0000

0x1D00 0000

32 kB local SRAM

32 kB + 8 kB local SRAM

reserved

64 kB ROM

0x1E00 0000

0x1F00 0000

0x2000 0000

16 MB static external memory CS3

16 MB static external memory CS2

16 MB static external memory CS1

16 MB static external memory CS0

0x1400 0000

0x1800 0000

0x1A00 0000 256 kB flash A

0x1A04 0000 256 kB flash A

0x1A08 0000

0x1B00 0000 256 kB flash B

0x1B04 0000 256 kB flash B

0x1B08 0000

64 MB SPIFI data

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 5.2 — 26 November 2015 68 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

Fig 8. LPC435x/3x/2x/1x Memory mapping (peripherals)

reserved

peripheral bit band alias region

high-speed GPIO

reserved

0x4000 0000

0x0000 0000

0x1000 0000

0x4002 0000

0x4004 0000

0x4005 0000

0x4010 0000

0x4400 0000

0x6000 0000

0xFFFF FFFF

AHB peripherals

APB0 peripherals

APB1 peripherals

reserved

RTC domain peripherals

0x4006 0000

0x4008 0000

0x4009 0000

0x400A 0000

0x400B 0000

0x400C 0000

0x400D 0000

0x400E 0000

0x400F 0000

0x400F 1000

0x400F 2000

0x400F 4000

0x400F 8000

clocking/reset peripherals

APB2 peripherals

APB3 peripherals

SGPIO

SPI

0x4010 1000

0x4010 2000

0x4200 0000

reserved

external memories and

ARM private bus

APB2

peripherals

0x400C 1000

0x400C 2000

0x400C 3000

0x400C 4000

0x400C 6000

0x400C 8000

0x400C 7000

0x400C 5000

0x400C 0000 RI timer

USART2

USART3

timer2

timer3

SSP1

QEI

APB1

peripherals

0x400A 1000

0x400A 2000

0x400A 3000

0x400A 4000

0x400A 5000

0x400B 0000

0x400A 0000 motor control PWM

I2C0

I2S0

I2S1

C_CAN1

reserved

AHB

peripherals

0x4000 1000

0x4000 0000

SCT

0x4000 2000

0x4000 3000

0x4000 4000

0x4000 6000

0x4000 8000

0x4001 0000

0x4001 2000

0x4002 0000

0x4000 9000

0x4000 7000

0x4000 5000

DMA

SD/MMC

EMC

USB1

LCD

USB0

reserved

SPIFI

ethernet

reserved

0x4008 1000

0x4008 0000 WWDT

0x4008 2000

0x4008 3000

0x4008 4000

0x4008 6000

0x4008 A000

0x4008 7000

0x4008 8000

0x4008 9000

0x4008 5000

UART1 w/ modem

SSP0

timer0

timer1

SCU

GPIO interrupts

GPIO GROUP0 interrupt

GPIO GROUP1 interrupt

USART0

RTC domain

peripherals

0x4004 1000

0x4004 0000

alarm timer

0x4004 2000

0x4004 3000

0x4004 4000

0x4004 6000

0x4004 7000

0x4005 0000

0x4004 5000

power mode control

CREG

event router

OTP controller

reserved

RTC/event monitor

backup registers

clocking

reset control

peripherals

0x4005 1000

0x4005 0000

CGU

0x4005 2000

0x4005 3000

0x4005 4000

0x4006 0000

CCU2

RGU

CCU1

LPC435x/3x/2x/1x

002aah183

reserved

APB3

peripherals

0x400E 1000

0x400E 2000

0x400E 3000

0x400E 4000

0x400F 0000

0x400E 5000

0x400E 0000 I2C1

DAC

C_CAN0

ADC0

ADC1

reserved

GIMA

APB0

peripherals

256 MB memory shadow area

SRAM, flash, EEPROM memories,

SPIFI data, ROM

external memory banks

0x4000 C000

0x4000 D000

reserved

flash A controller

flash B controller

0x4000 E000

0x4000 F000

EEPROM controller

Product data sheet Rev. 5.2 — 26 November 2015 69 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.15 One-Time Programmable (OTP) memory

The OTP provides 64 bit+ 256 bit of memory for general-purpose use.

7.16 General Purpose I/O (GPIO)

The LPC435x/3x/2x/1x provide eight GPIO ports with up to 31 GPIO pins each.

Device pins that are not connected to a specific perip heral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any numbe r of outp uts simultan eou sly. The value of the

output register may be read back as well as the current state of the port pins.

All GPIO pins default to inputs with pull-up resistors enabled and input buffer disabled on

reset. The input buffer must be turned on in the system control block SFS register before

the GPIO input can be read.

7.16.1 Features

•Accelerated GPIO functions:

–GPIO registers are located on the AHB so that the fastest possible I/O timing can

be achieved.

–Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

–All GPIO registers are byte and half-word addressable.

–Entire port value can be written in one instruction.

•Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

•Direction control of individual bits.

•Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or

level-sensitive GPIO interrupt request (GPIO interrupts).

•Two GPIO group interrupts can be triggered by any pin or pins in each port (GPIO

group0 and group1 interrupts).

7.17 Configurable digital peripherals

7.17.1 State Configurable Timer (SCTim er/PWM) subsystem

The SCT imer/PWM allows a wide variety of timi ng, counting, output modulation, an d input

capture operations. The inputs and outputs of the SCTimer/PWM are shared with the

capture and mat ch inp u ts/outpu ts of the 32-b it gene r al pu rp os e co un te r/t i m ers .

The SCT imer/PWM can be co nfigured as two 16-bit counters or a unified 32 -bit counter . In

the two-counter case, in addition to the counter value the following operational elements

are independent for each half:

•State variable

•Limit, halt, stop, and start conditions

•Values of Match/Capture registers, plus reload or capture control values

Product data sheet Rev. 5.2 — 26 November 2015 70 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

In the two-counter case, the following operational elements are global to the

SCTimer/PWM, but the last three can use match conditions from either counter:

•Clock selection

•Inputs

•Events

•Outputs

•Interrupts

7.17.1.1 Features

•Tw o 16-bit counters or one 32-bit counter.

•Counters clocked by bus clock or selected input.

•Up counters or up-down counters.

•State variable allows sequencing across multiple counter cycles.

•The following conditions define an event: a counter match cond ition, an input (or

output) condition, a combination of a match and/or and input/output condition in a

specified state.

•Events control outputs, interrupts, and DMA requests.

–Match register 0 can be used as an automatic limit.

–In bi-directional mode, events can be enabled based on the count direction.

–Match events can be held until an ot he r qu a lifyin g ev en t occurs.

•Selected events can limit, halt, start, or stop a counter.

•Supports:

–8 inputs

–16 outputs

–16 match/capture registers

–16 events

–32 states

–Match register 0 to 5 support a fractional component for the dither engine

7.17.2 Serial GPIO (SGPIO)

The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate

serial stream processing.

7.17.2.1 Features

•Each SGPIO input/output slice can be used to perform a serial to parallel or p arallel to

serial data conversion.

•16 SGPIO input/output slices each with a 32-bit FIFO that can shif t the input value

from a pin or an output value to a pin with every cycle of a shift clock.

•Each slice is double-buffered.

•Interrupt is generated on a full FIFO, shift clock, or pattern match.

•Slices can be concatenated to increase buffer size.

Product data sheet Rev. 5.2 — 26 November 2015 71 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

•Each slice has a 32-bit pattern match filter.

7.18 AHB peripherals

7.18.1 General Purpose DMA

The DMA controller allows perip heral-to memory, memory-to-peripheral,

peripheral- to -p e riphe ra l, an d m em o ry- to -m e mo ry tran sa ct ion s. Eac h DM A stre am

provides unidirectional serial DMA transfers fo r a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receives. The

source and destination areas can each be either a memory region or a peripheral for

master 1, but only memory for master 0.

7.18.1.1 Features

•Eight DMA channels. Each channel can support a unidirectional transfer.

•16 DMA request lines.

•Single DMA and burst DMA request signals. Each peripheral connected to the DMA

Controller can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the DMA Controller.

•Memory-to-memory, memory-to-periphera l, peripheral-to-memory, and

periphera l-to -p e rip he ra l tra ns fe rs ar e su pp or te d.

•Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

•Hardware DMA channel priority.

•AHB slave DMA programming interface. The DMA Controller is programmed by

writing to the DMA control registers over the AHB slave interface.

•Two AHB bus masters for transferring data. These interfaces transfer dat a when a

DMA request goes active. Master 1 can access memories and peripherals, master 0

can access memories only.

•32-bit AHB master bus width.

•Incrementing or non-incrementing addressing for source and destination.

•Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data.

•Internal four-word FIFO per channel.

•Supports 8, 16, and 32-b it wid e tra n sac tio ns .

•Big-endian and little-endian support. The DMA Controller defaults to little-endian

mode on reset.

•An interrupt to the pr ocessor ca n be gene rated o n a DMA comp letion or when a DMA

error has occurred.

•Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.18.2 SPI Flash Interface (SPIFI)

The SPI Flash Interface allows low-cost seria l flash memories to be co nnected to the ARM

Cortex-M4 pr oc es sor with little per form a nc e pe na lty compared to parallel flash devices

with higher pin count.

Product data sheet Rev. 5.2 — 26 November 2015 72 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

After a few commands configure the interface at startup, the entire flash content is

accessible as normal memory using byte, halfword, and word accesses by the processor

and/or DMA channels. Simple sequences of commands handle erasing and

programming.

Many serial flash d evices use a half-duplex command-dr iven SPI protocol for device setup

and initialization and then move to a half-duplex, command-driven 4-bit protocol for

normal operation. Different serial flash vendors and devices accept or require different

commands and command formats. SPIFI provides sufficient flexibility to be compatible

with common flash devices and includes extensions to help insure compatibility with future

devices.

7.18.2.1 Features

•Interfaces to serial flash memory in the main memory map.

•Supports classic and 4-bit bidir ec tio na l seria l proto co l s.

•Half-duplex protocol compatible with various vendors and devices.

•Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per

second.

•Supports DMA access.

7.18.3 SD/MMC card interface

The SD/MMC card interface supports the following modes to control:

•Secure Digital memory (SD version 3.0)

•Secure Digital I/O (SDIO version 2.0)

•Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)

•MultiMedia Cards (MMC version 4.4)

7.18.4 External Memory Controller (EMC)

Remark: The EMC is availabl e on all LPC435x/3x/2x/1x part s. The followin g memory bus

widths are supported:

•LBGA256 packages: 32 bit

•TFBGA100 packag es: 16 bit

•LQFP208 packages: 16 bit

•LQFP144 packages: 16 bit

The LPC435x/3x/2x/1x EMC is a Memory Controller peripheral offering support for

asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it

can be used as an interface with off-chip memory-mapped devices and peripherals.

Tabl e 6. EMC pi nout for different packages

Function LBGA256 TFBGA100 LQFP208 LQFP144

A EMC_A[23:0] EMC_A[13:0] EMC_A[23:0] EMC_A[15:0]

D EMC_D[31:0] EMC_D[7:0] EMC_D[15:0] EMC_D[15:0]

BLS EMC_BLS[3:0] EMC_BLS0 EMC_BLS[1:0] EMC_BLS[1:0]

CS EMC_CS[3:0] EMC_CS0 EMC_CS[3:0] EMC_CS[1:0]

Product data sheet Rev. 5.2 — 26 November 2015 73 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.18.4.1 Features

•Dynamic memory interface supp ort including single data rate SDRAM.

•Asynchronous static memory device support including RAM, ROM, and NOR flash,

with or without asynchronous page mode.

•Low transaction latency.

•Read and write buffers to reduce latency and to improve performance.

•8/16/32 data and 24 address lines wide static memory support.

•16 bit and 32 bit wide chip select SDRAM memory support.

•Static memory features include:

–Asynchronous page mode read

–Programmable Wait States

–Bus turnaround delay

–Output enable and write enable delays

–Extended wait

•Four chip selects for synchronous memory and four chip selects for static memory

devices.

•Power-saving modes dynamically control EMC_CKEOUT and EMC_CLK signals to

SDRAMs.

•Dynamic memory self-refresh mode controlled by software.

•Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row

address synchronous memory parts. Those are typically 512 MB, 256 MB, and

128 MB parts, with 4, 8, 16, or 32 data bits per device.

•Separate reset domains allow the for auto-refresh through a chip reset if desired.

•SDRAM clock can run at full or half the Cortex-M4 core frequency.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

OE EMC_OE EMC_OE EMC_OE EMC_OE

WE EMC_WE EMC_WE EMC_WE EMC_WE

CKEOUT EMC_

CKEOUT[3:0] EMC_

CKEOUT[1:0] EMC_

CKEOUT[1:0]

CLK EMC_CLK[3:0];

EMC_CLK01,

EMC_CLK23

EMC_CLK0,

EMC_CLK3;

EMC_CLK01,

EMC_CLK23

EMC_CLK0,

EMC_CLK3;

EMC_CLK01,

EMC_CLK23

EMC_CLK0,

EMC_CLK3;

EMC_CLK01,

EMC_CLK23

DQMOUT EMC_

DQMOUT[3:0] -EMC_

DQMOUT[1:0] EMC_

DQMOUT[1:0]

DYCS EMC_

DYCS[3:0] EMC_DYCS[1:0] EMC_DYCS[2:0] EMC_DYCS[1:0]

CAS EMC_CAS EMC_CAS EMC_CAS EMC_CAS

RAS EMC_RAS EMC_RAS EMC_RAS EMC_RAS

Tabl e 6. EMC pi nout for different packages

Function LBGA256 TFBGA100 LQFP208 LQFP144

Product data sheet Rev. 5.2 — 26 November 2015 74 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.18.5 High-speed USB Host/Device/OTG interface (USB0)

Remark: USB0 is available on the following parts: LPC435x, LPC433x, LPC432x. USB0

is not available on the LPC431x parts.

The USB OTG module allows the LPC435x/3x/2x/1x to connect directly to a USB Host

such as a PC (in device mode) or to a USB Device in host mode.

7.18.5.1 Features

•Contains UTMI+ compliant high-speed transceiver (PHY).

•Complies with Universal Serial Bus specification 2.0.

•Complies with USB On-The-Go supplement.

•Complies with Enhanced Host Controller Interface Specification.

•Supports auto USB 2.0 mode disc overy.

•Supports all high-speed USB-co mplia nt per iph er a ls.

•Supports all full-speed USB-compliant peripherals.

•Supports soft ware Host Negotiation Protocol (HNP) and Session Request Protocol

(SRP) for OTG perip h er als .

•Supports interrupts.

•Supports Start Of Frame (SOF) frame length adjust.

•This module has its own, integrated DMA engine.

•USB interface electrical test software included in ROM USB stack.

7.18.6 High-speed USB Host/Device interface with ULPI (USB1)

Remark: USB1 is available on the following parts: LPC435x and LPC433x. USB1 is not

available on the LPC432x and LPC431x parts.

The USB1 interface can operate as a full-speed USB Host/Device interface or can

connect to an ext erna l ULPI PHY fo r Hi gh -s pe ed op erat ion .

7.18.6.1 Features

•Complies with Universal Serial Bus specification 2.0.

•Complies with Enhanced Host Controller Interface Specification.

•Supports auto USB 2.0 mode disc overy.

•Supports all high-speed USB-co mp lia nt per iph er a ls if conn ec te d to exte rn al UL PI

PHY.

•Supports all full-speed USB-compliant peripherals.

•Supports interrupts.

•Supports Start Of Frame (SOF) frame length adjust.

•This module has its own, integrated DMA engine.

•USB interface electrical test software included in ROM USB stack.

7.18.7 LCD controller

Remark: The LCD controller is only available on parts LPC435x. LCD is not available on

parts LPC433x, LPC432x, and LPC431x.

Product data sheet Rev. 5.2 — 26 November 2015 75 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

The LCD controller provides all of the necessary control signals to interface directly to

various color and monochrome LCD panels. Both STN (single and dual panel) and TFT

panels can be oper ated. The disp lay resolutio n is se lect able a nd can be up to 1024 768

pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.

An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of

the displayed data) while still supporting many colors.

The LCD interface includes its own DMA controller to allow it to operate independently of

the CPU and other sys te m fu nc tion s. A built-in FIF O acts as a buffer for display data,

providing flexibility for system timing. Hardware cursor support can further reduce the

amount of CPU time required to operate the display.

7.18.7.1 Features

•AHB master interface to access frame buffer.

•Setup and control via a separate AHB slave interface.

•Dual 16-deep program mable 64-bit wide FIFOs for buffering incoming display data.

•Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays

with 4-bit or 8-bit interfaces.

•Supports single and du al-panel color STN displays.

•Supports Thin Film Transistor (TFT) color displays.

•Programmable display resolution including, but not limited to: 320 200, 320 240,

640 200, 640 240, 640 480, 800 600, and 1024 768.

•Hardware cursor support for single-panel displays.

•15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.

•1, 2, or 4 bits-per-pixel (bpp) palettize d displays for monochrome STN.

•1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.

•16 bpp true-color non-palettized for color STN and TFT.

•24 bpp true-color non-palettized for color TFT.

•Programmable timing for different display panels.

•256 entry, 16-bit palette RAM, arrang ed as a 12 8 32-bit RAM.

•Frame, line, and pix el cloc k si gn als .

•AC bias signal for STN, data enable signal for TFT panels.

•Supports little and big-endian, and Windows CE data formats.

•LCD panel clock may be generated from the peripheral clock, or from a clock input

pin.

7.18.8 Ethernet

Remark: The ether net controller is available on parts LPC435x and LPC433x. Ethernet is

not available on parts LPC432x and LPC431x.

7.18.8.1 Features

•10/100 Mbit/s

•DMA support

•Power management remote wake-up frame and magic packet detection

Product data sheet Rev. 5.2 — 26 November 2015 76 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

•Supports both full-duplex an d half- du ple x op er ation

–Supports CSMA/CD Protocol for half-duplex operation.

–Supports IEEE 802.3x flow control for full-duplex operation.

–Optional forwarding of received pause control frames to the us er app lica tio n in

full-duplex operation.

–Back-press ur e supp or t for half -d up le x op er at ion .

–Automatic transmission of zero-quanta p ause frame on deassertion of flow control

input in full-duplex operation.

•Supports IEEE1588 time st amping and IEEE 1588 advanced time stamping (IEEE

1588-2008 v2).

7.19 Digital serial peripherals

7.19.1 UART1

Remark: The LPC435x/3x/2x/1x contain one UART with standard transmit and receive

data lines.

UART1 also provides a full modem control handshake interface and support for

RS-485/9-bit mode allowing both software address detection and automatic address

detection using 9-bit mode.

UART1 includes a fractional baud r ate generator. S tandard b aud rates such as 115200 Bd

can be achieved with an y crystal frequency above 2 MHz.

7.19.1.1 Features

•Maximum UART data bit rate of 8 MBit/s.

•16 B Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud ra te generator covering wide range of baud rates without a

need for external crystals of particular values.

•Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

•Equipped with standard modem interface signals. This module also provides full

support for hardware flow control.

•Support for RS-4 85 /9 -b it/EIA-485 mode (UART1).

•DMA support.

7.19.2 USART0/2/3

Remark: The LPC435x/3x/2x/1x contain three USARTs. In addition to standard transmit

and receive data lines, the USARTs support a synchronous mode.

The USARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

Product data sheet Rev. 5.2 — 26 November 2015 77 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.19.2.1 Features

•Maximum UART data bit rate of 8 MBit/s.

•16 B Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud ra te generator covering wide range of baud rates without a

need for external crystals of particular values.

•Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

•Support for RS -4 85 /9 -bit/EIA-485 mode.

•USART3 includes an IrDA mode to support infrared communication.

•All USARTs have DMA support.

•Support for synchronous mode at a data bit rate of up to 8 Mbit/s.

•Smart card mode conforming to ISO7816 specification

7.19.3 SPI serial I/O controller

Remark: The LPC435x/3x/2x/1x contain one SPI controller.

SPI is a full duplex serial interface designed to handle multiple masters and slaves

connected to a given bus. Only a single master and a single slave can communicate on

the interface during a give n data transfer. During a data transfer the master always se nds

8 bits to 16 bits of data to th e slave, and the slave always sends 8 bits to 16 bits of dat a to

the master.

7.19.3.1 Features

•Maximum SPI data bit rate 25 Mbit/s.

•Compliant with SPI specification

•Synchronous, serial, full duplex communication

•Combined SPI master and slave

•Maximum data bit rate of one eighth of the input clock rate

•8 bits to 16 bits per transfer

7.19.4 SSP serial I/O controller

Remark: The LPC435x/3x/2x/1x contain two SSP controllers.

The SSP controller ca n operate on a SPI, 4-wire SSI, or Microwire bus. It can interact with

multiple masters and slaves on the bus. Only a single master and a sin gle slave can

communicate on the bus during a given data transfer. The SSP supports full duplex

transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and

from the slave to the master. In practice, often only one of these data flows carries

meaningful data.

7.19.4.1 Features

•Maximum SSP speed in full-duplex mode of 25.5 Mbit/s; for transmit only 51 Mbit/s

(master) and 11 Mbit/s (slave)

Product data sheet Rev. 5.2 — 26 November 2015 78 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

•DMA transfers supp or ted by GPDMA

7.19.5 I2C-bus interface

Remark: The LPC435x/3x/2x/1x each contain two I2C-bus interfaces.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line

(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (for ex ample an LCD driver) or a transmitter

with the capability to both receive and send information (such as memory). Transmitters

and/or receivers can operate in either master or slave mode, depending on whethe r the

chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and

can be controlled by more than one bus master connected to it.

7.19.5.1 Features

•I2C0 is a standard I2C compliant bus interface with open-dr ain pins. I2C0 also

supports Fast mode plus with bit rates up to 1 Mbit/s.

•I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with diff erent bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake me chanism to suspend and

resume serial transfer.

•The I2C-bus can be used for test an d diagnostic purposes.

•All I2C-bus controllers support multiple address recognition and a bus monitor mode.

7.19.6 I2S interface

Remark: The LPC435x/3x/2x/1x each contain two I2S-bus interfaces.

The I2S-bus provides a standard communication interface for digital audio applications.

The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,

and one word select signal. The basic I2S-bus connection has one master, which is

always the master, and one slave. The I2S- bus interface provides a sep arate transmit and

receive channel, each of which can operate as either a master or a slave.

Product data sheet Rev. 5.2 — 26 November 2015 79 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.19.6.1 Features

•The I2S interfaces has separate input/o ut pu t ch an ne ls, each of wh ich ca n op er a te in

master or slave mode.

•Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

•Mono and stereo audio data supp orted.

•The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48,

96, 192) kHz.

•Support for an aud io ma st er clock.

•Configurable word select period in master mode (separately for I2S-bus input and

output).

•Two 8-word FIFO data buffers are provided, one for transmit and one for receive.

•Generates interrupt requests when buffer levels cross a programmable boundary.

•Two DMA requests contr olled by programmable buffer levels. The DMA requests are

connected to the GPDMA block.

•Controls include reset, stop and mute options sep arately for I2S-bus input and I2S-bus

output.

7.19.7 C_CAN

Remark: The LPC435x/3x/2x/1x each contain two C_CAN controllers.

Controller Area Network (CAN) is the definition of a high performance communication

protocol for seri al data communication. The C_ CAN controller is desig ned to provide a full

implement ation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a high level of reliability.

7.19.7.1 Features

•Conforms to protocol version 2.0 parts A and B.

•Supports bit rate of up to 1 Mbit/s.

•Supports 32 Message Objects.

•Each Message Object has its own identifier mask.

•Provides programmable FIFO mode (concatenation of Message Objects).

•Provides maskable interrupts.

•Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN

applications.

•Provides programmable loop-back mode for self-test operation.

7.20 Counter/timers and motor control

7.20.1 General purpose 32-bit timers/external event counters

Remark: The LPC435x/3x/2x/1x include four 32-bit timer/counters.

Product data sheet Rev. 5.2 — 26 November 2015 80 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

The timer/counter is designed to count cycles of the system derived clock or an

externally-supplied clock. It can optionally generate interrupts, generate timed DMA

requests, or perform other actions at specified timer values, based on four match

registers. Each timer/counter also includes two capture input s to trap the timer value when

an input signal transitio ns, optionally generating an interrupt.

7.20.1.1 Features

•A 32-bit timer/counter with a progra mmable 32-bit prescaler.

•Counter or time r op er a tion .

•Two 32-bit capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event can also generate an interrupt.

•Four 32-bit matc h re gist er s tha t allo w:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional inter rupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

•Up to two match registers can be used to generate timed DMA requests.

7.20.2 Motor control PWM

The motor control PWM is a specialized PWM supporting 3-phase motors and other

combinations. Feedback input s are provided to automatically sense rotor position and use

that information to ramp speed up or down. An abort input causes the PWM to release all

motor drive outputs immediately . At the same time, the motor control PWM is highly

configurable for other generalized timing, counting, capture, and compare applications.

7.20.3 Quadrature Encoder Interface (QEI)

A quadrature encoder, also known as a 2-channel incremental encoder, converts angular

displacement into two pulse signals. By monitoring both the number of pulses and the

relative phase of the two signals, the user code ca n track the position, direction of rotation,

and velocity. In addition, a third channel, or ind ex signal, ca n be use d to rese t the p osition

counter. The quadrature encoder interface decodes the digital pulses from a quadrature

encoder wheel to integrate position over time and determine direction of rotation. In

addition, the QEI can capture the velocity of the encoder wheel.

7.20.3.1 Features

•Tracks encoder position.

•Increments/decrements depending on direction.

•Programmable for 2 or 4 position counting.

•Velocity capture using built-in timer.

•Velocity compare function with “less than” interrupt.

Product data sheet Rev. 5.2 — 26 November 2015 81 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

•Uses 32-bit regis ter s for po sitio n an d ve loc ity.

•Three position co mpare registers with interrupts.

•Index counter for revolution counting.

•Index compare regis te r with int er ru p ts.

•Can combine index and position interrupts to produce an interrupt for whole and

partial revolution displacement.

•Digital filter with programmable delays for encoder input signals.

•Can accept decoded signal inputs (clk and direction).

7.20.4 Repetitive Interrupt (RI) timer

The repetitive interrupt timer provides a free-running 32-bit counter which is compared to

a selectable value, gen erating an interrupt when a match occurs. Any bits of the

timer/compare function can be masked such that they do not contribute to the match

detection. The repetitive interrupt timer can be used to create an interrupt that repeats at

predetermined intervals.

7.20.4.1 Features

•32-bit counter. Counter can be free-running or be reset by a ge nerated interrupt.

•32-bit compare value.

•32-bit compare mask. An inter rupt is generated when the counter value equals the

compare value, after masking. This mechanism allows for combinations not possible

with a simple compare.

7.20.5 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.20.5.1 Features

•Internally resets chip if not periodically reloaded dur ing the programmable time-out

period.

•Optional windowed operation re quires reload to occur between a minim um and

maximum time period, both programmable.

•Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

•Enabled by soft ware but requires a hardwar e reset or a watchdog reset/interrupt to be

disabled.

•Incorrect feed sequence causes reset or interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 24-bit tim er with internal prescaler.

•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in

multiples of Tcy(WDCLK) 4.

•The Watchdog Clock (WDCLK) uses the IRC as the clock source.

Product data sheet Rev. 5.2 — 26 November 2015 82 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.21 Analog peripherals

7.21.1 Analog-to-Digital Converter (ADC0/1)

Remark: The LPC435x/3x/2x/1x contain two 10-bit ADCs.

7.21.1.1 Features

•10-bit successive approximation analog to digital converter.

•Input multiplexing among 8 pins.

•Power-down mode.

•Measurem en t ra ng e 0 to VDD A.

•Sampling frequency up to 400 kSamples/s.

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer

outputs 8 or 15, or the PWM output MCOA2.

•Individual result registers for each A/D channel to reduce interrupt overhead.

•DMA support.

7.21.2 Digital-to-Analog Converter (DAC)

7.21.2.1 Features

•10-bit resolution

•Monotonic by design (resistor string architecture)

•Controllable conversion speed

•Low power consum pt ion

7.22 Peripherals in the RTC power domain

7.22.1 RTC

The Real Time Clock (R TC) is a set of counter s for measuring time when system power is

on, and optionally when it is of f. It uses little power when the CPU does not access its

registers, especially in the reduced power modes. A separate 32 kHz oscillator clocks the

RTC. The oscillator produces a 1 Hz internal time reference and is powered by its own

power supply pin, VBAT.

7.22.1.1 Features

•Measures the passage of time to maintain a calendar and clock. Provides seconds,

minutes, hours, day of month, month, year, day of week, and day of year.

•Ultra-low power design to support battery powered systems. Uses power from the

CPU power supply when it is present.

•Dedicated battery power supply pin.

•RTC power supply is isolated from the rest of the chip.

•Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution.

•Periodic interrup t s can be gene rated fro m increment s of a ny field of th e time registe rs.

Product data sheet Rev. 5.2 — 26 November 2015 83 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

•Alarm interrupt can be generated for a specific date/time.

7.22.1.2 Event monitor/recorder

The event monitor/recorder allows recording and creating a time stamp of events related

to the WAKEUP pins. Sensors report changes to the state of the WAKEUP pins, and the

event monitor/recorder stores records of such events. The event recorder can be

The event monitor/recorder can monitor the integrity of the device and record any

tampering events.

Features

•Supports three digital event inputs in the VBAT power domain .

•An event is defined as a level change at the digital event inputs.

•For each event channel, two timestamps mark the first and the last occurrence of an

event. Each channe l also has a dedicated counter tr acking the total numb er of events.

Timestamp values are taken from the RTC.

•Runs in VBAT power domain, independent of system power supply. The

event/reco rd er /m o nito r can th er ef or e op erate in Deep power -d ow n mo d e.

•Low power consum pt ion .

•Interrupt available if system is running.

•A qualified event can be used as a wake-up trigger.

•State of event interrupts accessible by software through GPIO.

7.22.2 Alarm timer

The alarm timer is a 1 6-bit timer and count s down at 1 kHz from a prese t value gener ating

alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00

and asserts an interrupt if enabled.

The alarm timer is part of the RTC power domain and can be batte ry powered.

7.23 System control

7.23.1 Configuration registers (CREG)

The following settings are contr olled in the configuration register block:

•BOD trip settings

•Oscillator output

•DMA-to-peripheral muxing

•Ethernet mode

•Memory mapping

•Timer/USART inputs

•Enabling the USB controllers

In addition, the CREG block contains the part identification and part configuration

information.

Product data sheet Rev. 5.2 — 26 November 2015 84 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.23.2 System Control Unit (SCU)

The system control unit determines the fun ction and el ectrical mode o f the digit al pin s. By

default function 0 is selected for all pins with pull-up enabled. For pins that support a

digital an d analog function, the ADC function select registers in the SCU enable the

analog function.

A separa te set of analog I/Os for the ADCs and the DAC as well as most USB pins are

located on separate pads and are not controlled through the SCU.

In addition, the clock delay register for the SDRAM EMC_CLK pins and the registers that

select the pin interrupts are located in the SCU.

7.23.3 Clock Generation Unit (CGU)

The Clock Generator Unit (CGU) generates several base clocks. The base clocks can be

unrelated in fre q ue nc y an d ph as e an d ca n ha ve different clock sources within the CGU.

One CGU base clock is routed to the CLKOUT pins. The base clock that generates the

CPU clock is referred to as CCLK.

Multiple branch cloc ks ar e de riv ed fro m each bas e cloc k. Th e branc h cloc ks offer flexible

control for power-managem ent purposes. All branch clocks are outputs of one of two

Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived

from the same base clock are synchronous in frequency and phase.

7.23.4 Internal RC oscillator (IRC)

The IRC is used as the clock source for the WWDT and/or as the clock that drives the

PLLs and the CPU. The nominal IRC freque ncy is 12 MHz. The IRC is trimmed to 1.5 %

accuracy for Tamb = 0 °C to 85 °C and 3% accuracy for Tamb = -40 °C to 0 °C and Tamb =

85 °C to 105 °C.

Upon power-up or an y chip reset, the LPC435x/ 3x/2x/1x use the IRC as the cl ock source.

The boot loader then configu res the PLL1 to provide a 96 MHz clock for the core and

PLL0USB or PLL0AUDIO as needed if an external boot source is selected.

7.23.5 PLL0USB (for USB0)

PLL0 is a dedicated PLL for the USB0 High-speed controller.

PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz

to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.

7.23.6 PLL0AUDIO (for audio)

The audio PLL PLL0AUDIO is a general purpose PLL with a very small step size. This

PLL accepts an input clock frequency derived from an external oscillator or internal IRC.

The input frequency is multiplied up to a high frequency with a Current Controlled

Oscillator (CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the

desired output frequency. The output frequency can be set as a multiple of the sampling

frequency fs to 32fs, 64fs, 128  fs, 256 fs, 384  fs, 512  fs and the sampling

frequency fs can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz.

Many other frequencies are possible as well using the integrated fractional divider.

Product data sheet Rev. 5.2 — 26 November 2015 85 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.23.7 System PLL1

The PLL1 accepts an input clock frequency from an external oscillator in the range of

1 MHz to 25 MHz. The input frequency is multiplie d up to a high frequency with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO

operates in the range of 156 MHz to 320 MHz. This range is possible through an

additional divider in the loop to keep the CCO within its frequency range while the PLL is

providing the desired output frequency. The output divider can be set to divide by 2, 4, 8,

or 16 to produce the outp ut clock. Since the minimum output divider value is 2, it is

insured that the PL L output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset. After reset, software can enable the PLL. The program must

configure and activate th e PL L, wait fo r th e PLL to lo ck, an d then con nect to the PLL as a

clock source. The PLL settling time is 100 s.

7.23.8 Reset Generation Unit (RGU)

The RGU allows generation of independent reset signals for individual blocks and

peripherals on the LPC435x/3x/2x/1x.

7.23.9 Power Management Controller (PMC)

The PMC controls the power to the cores, peripherals, and memories.

The LPC435x/3x/2x/1 x support the following p ower modes in or der from highest to lowest

power consum p tion :

1. Active mode

2. Sleep mode

3. Power-down modes:

a. Deep-sleep mode

b. Power-down mode

c. Deep power-down mode

Active mode and sleep mode apply to the state of the core. In a dual-core system, either

core can be in active or sleep mode inde pendently of the other core.

If the core is in Active mode , it is fully oper at ion al an d can ac ces s pe rip he ra ls an d

memories as configured by software. If the core is in Sleep mode, it receives no clocks,

but peripherals and memories remain running.

Either core can enter sleep mode from active mode independently of the other core and

while the other core remains in active mode or is in sleep mode.

Power-down modes app ly to the entire system. In the Power-down modes, both cores and

all peripherals except for peripherals in the always-on power domain are shut down.

Memories can rem ain powered fo r retain ing memory content s as defined by the individual

power-down mode.

Either core in active mode can put the part into one of the three power down modes if the

core is enabled to do so. If both cores are enabled for putting the system into power-down,

then the system enters powe r-down only once both cores have received a WFI or WFE

instruction.

Product data sheet Rev. 5.2 — 26 November 2015 86 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

Wake-up from sleep mode is caused by an interrupt or event in the core’s NVIC. The

interrupt is captured in the NVIC and an event is captured in the Event router. Both cores

can wake up from sleep mode independently of each other.

W ake-up from the Power-down modes, Deep-sleep, Power-down, and Deep power-down,

is caused by an event on the WAKEUP pins or an event from the RTC or alarm timer.

When waking up from Deep power-down mode, the part resets and attempts to boot.

7.23.10 Power control

The LPC435x/3x/2x/1x feature several independent power domains to control power to

the core and the peripherals (see Figure 9). The RTC and its associated peripherals (the

alarm timer, the CREG block, the OTP controller, the back-up registers, and the event

router) are located in the RTC power-domain. The main regulator or a battery supply can

power the RTC. A power selector switch ensures that the RTC block is always powered

on.

Product data sheet Rev. 5.2 — 26 November 2015 87 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.23.11 Code security (Code Read Protection - CRP)

CRP enables dif ferent levels o f security so that access to the on-chip flash and use of the

JTAG and ISP can be restricted. CRP is invoked by programming a specific pattern i nto a

dedicated flash location. IAP commands are not affected by CRP.

Fig 9. Power domains

REAL-TIME CLOCK

BACKUP REGISTERS

RESET/WAKE-UP

CONTROL

REGULATOR

32 kHz

OSCILLATOR

ALWAYS-ON/RTC POWER DOMAIN

MAIN POWER DOMAIN

RTCX1

VBAT

VDDREG

RTCX2

VDDIO

VSS

to memories,

peripherals,

oscillators,

PLLs

to cores

to I/O pads

ADC

DAC

OTP

ADC POWER DOMAIN

OTP POWER DOMAIN

USB0 POWER DOMAIN

VDDA

VSSA

VPP

USB0

USB0_VDDA3V_DRIVER

USB0_VDDA3V3

LPC43xx

ULTRA LOW-POWER

REGULATOR

ALARM

RESET

WAKEUP0/1/2/3

to RTC

domain

peripherals

002aag378

to RTC I/O

pads (Vps)

Product data sheet Rev. 5.2 — 26 November 2015 88 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

There are three levels of the Code Read Protection:

•In level CRP1, access to the chip via the JTAG is disabled. Partial flas h updates are

allowed (excluding flash sector 0 ) using a limited set of the ISP commands. This level

is useful when CRP is required and flash field updates are needed. CRP1 do es

prevent the user code from erasing all sectors.

•In level CRP2, access to the chip via the JTAG is disabled. Only a full flash erase and

update using a redu ced set of the ISP commands is allowed.

•In level CRP3, any access to the chip via the JTAG pins or the ISP is disabled. This

mode also disables the ISP override using P2_7 pin. If necessary, the application

code must provide a flash update mechanism using the IAP calls or using the

reinvoke ISP command to enable flash update via USART0. See Table 5.

7.24 Serial Wire Debug/JTAG

Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and

trace functions are su pported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four

watch points.

Remark: Serial Wire Debug is supported for the ARM Cortex-M4 only,

The ARM Cortex-M0 coprocessor supports JTAG debug. A standard ARM

Cortex-compliant debugger can debug the ARM Cortex-M4 and the ARM Cortex- M0

cores separately or both cores simultaneously.

Remark: In order to debug the ARM Cortex-M0, release the M0 reset by software in the

RGU block.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Fig 10. Dual-co re de bu g configuration

002aah448

ARM Cortex-M0 ARM Cortex-M4

TCK

DBGEN = HIGH

TMS

TRST

TDI TDO TDO

TDO

DBGEN

RESET = HIGH

RESET

TCK

TMS

TRST

TDI

TCK

TMS

TRST

TDI

JTAG ID = 0x0BA0 1477 JTAG ID = 0x4BA0 0477

LPC43xx

Product data sheet Rev. 5.2 — 26 November 2015 89 of 162

NXP Semiconductors LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

8. Limiting values

[1] The following applies to the limiting values:

a) Absolute maximum ratings state the extreme limits that the product can withstand without leading to irrecoverable failure. Failure

includes the loss of reliability and shorter lifetime of the device. Conditions for functional operation of the part are shown in Table 11

“Static characteristics”.

b) This product includes circuitry designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Dependent on package type.

[4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Table 7. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD(REG)(3V3) regulator supply voltage

(3.3 V) on pin VDDREG 0.5 3.6 V

VDD(IO) input/output supply

voltage on pin VDDIO 0.5 3.6 V

VDDA(3V3) analog supply voltage

(3.3 V) on pin VDDA 0.5 3.6 V

VBAT battery supply voltage on pin VBAT 0.5 3.6 V

Vprog(pf) polyfuse programming

voltage on pin VPP 0.5 3.6 V

VIinput voltage when VDD(IO)  2.4 V

5 V tolerant digital I/O pins

[2] 0.5 5.5 V

ADC/DAC pins and digital I/O

pins configured for an analog

function

0.5 VDDA(3V3) V

USB0 pins USB0_DP;

USB0_DM;USB0_VBUS 0.3 5.25 V

USB0 pins USB0_ID;

USB0_RREF 0.3 3.6 V

USB1 pins USB1_DP and

USB1_DM 0.3 5.25 V

IDD supply current per supply pin - 100 mA

ISS ground current per ground pin - 100 mA

Ilatch I/O latch-up current (0.5VDD(IO)) < VI < (1.5VDD(IO));

Tj < 125 C-100mA

Tstg storage temperature [3] 65 +150 C

Ptot(pack) total power dissipation

(per package) based on packa ge he at transfer,

not device power consumption -1.5W

VESD electrostatic discharge

voltage human body model; all pins [4] - 2000 V