PIN CONFIGURA TION
FEATURES
•Data Retention in the absence of power
•Automatic data protection during power
failure
•Data Retention over 10 years
•Unlimited write cycles
•Conventional SRAM write cycles
•Low power CMOS
•Equal read/write cycle times
•+5V only read/write
•Operating voltage range +10%
•Direct replacement for 512K X 8 SRAM
or EPROM
•Standard 32 pin DIP JEDEC Pinout
Functional Description
The IM 1250Y–100 is a 4,194,304 bit, fully static
NP RAM organized as 512K X 8 using CMOS and an
internal lithium energy source.
This ‘NO POWER’ RAM has all the normal char-
acteristics of a CMOS static RAM with an important
benefit of data being retained in the absence of power .
Data retention current is so small that a miniature lithium
cell contained within the package provides an energy
source to preserve data. Protection against data loss
has also been incorporated to maintain data integrity
during power on/off conditions.
The IM 1250Y–100 RAM can be directly used
in place of existing static RAMs. There is no limit to
the number of write cycles that can be executed and
no additional support circuitry is required for interface
to a microprocessor.
PIN NAMES
N C No Connection
OE Output Enable
Gnd Ground
I/O0 – I/O7 Data in/ Data Out
Vcc Power Supply +5V
WE W rite Enable
A0 – A18 Address Inputs
CE Chip Enable
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
A18 Vcc
A16 A15
A14 A17
A12 WE
A7 A13
A6 A8
A5 A9
A4 A11
A3 O E
A2 A10
A1 CE
A0 I/O7
I/O0 I/O6
I/O1 I/O5
I/O2 I/O4
Gnd I/O3
INNOVATIVE MICROTECHNOLOGY INC.Phone/Fax-440-322-8083.Website:www.innovativemicrotechnology.com
INNOVATIVE IM1250Y-100
512K X 8 NO POWER SRAM
Maximum Ratings
Operating Temperature….0oC to 70oC
Storage Temperature…….0oC to 70oC
Soldering Temperature
And Time………………….260oC for 10 sec
Supply Voltage……………. 0V to 7.0V
Input Voltage………………-0.5V to 7.0V
Input/ Output Voltage…….-0.5V to Vcc + 0.3V
Power Dissipation…………1.0W
Parameter Symbol Min. Typ Max. Unit
Supply Voltage Vcc 4.5 5.0 5.5 V
Gnd 0 - 0 V
Input Voltage V IH 2.2 3.5 Vcc
+0.3 V
VIL 0 - 0.8 V
Recommended D.C. Operating Conditions
DA T A RETENTION
The IM 1250Y-100 provides full functional ca-
pability for Vcc greater than 4.5V and write protects at
4.25V. Data is retained in the absence of Vcc without
any additional support circuitry. The SRAM constantly
monitors Vcc. The moment Vcc decays, the RAM au-
tomatically write protects itself. All inputs to the RAM
become “don’t care” and all outputs re in high imped-
ance-state. As Vcc falls below approximately 3.0V the
power switching circuit connects the lithium energy
source to RAM to retain data. During power-on, when
Vcc rises above approximately 3.0V the power switch-
ing circuit connects external Vcc to the RAM and dis-
connects the lithium energy source. Normal RAM op-
eration can resume after Vcc becomes greater than
4.5V.
FRESHNESS SEAL AND SHIPPING
The IM1250Y - 100 is shipped from INNOVATIVE
MICROTECHONOLOGY INC. with the lithium energy
source disconnected , guaranteeing full energy capac-
ity. When Vcc is first applied at a level of greater than
4.5 volts, the lithium energy source is enabled for bat-
tery back-up operation.
READ MODE
The IM 1250Y-100 performs a read cycle whenever WE
high and CE low. The unique address specified by the
19 address inputs A0-A18 defines which of the
4,194,304 bytes of data is to be accessed. Valid data
will be available to the eight data output drivers within
access time tACC after the last address input is stable,
provided that CE and OE access times are satisfied. If
OE or CE access times are not satisfied, data access
will be measured from the limiting parameter (tCO or
tOE), rather than address. The state of the eight data I/
O lines is controlled by the OE and CE control signals.
The data lines may be in an indeterminate state be-
tween tOH and tAA but the data lines will always have valid
data at tAA.
WRITE MODE
The IM 1250Y-100 is in the write mode whenever CE
and WE inputs are held low . The latter occurring falling
edge of either CE or WE determines the start of a write
cycle. A write is terminated by the earlier rising edge of
CE or WE. The address must be held valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (tWR) before another Read or
Write cycle can be initiated. CE or WE is high during
power on to perfect memory after Vcc reaches Vcc
(min) but before the processor stabilizes.
INNOVATIVE IM1250Y-100
512K X 8 NO POWER SRAM
Electrical Characeteristics
Parameter Description Test conditons Min. Typ Max Unit
ILI Input Leakage Vi = 0 to Vcc -1 - 1
IOCA Average operating Current CE = Vcc - 45 80
CE = VIH,IIO = 0mA - 1 3 mA
Ivcc Operatng Supply current CE = VIL,IIO = 0mA - - 50 mA
ILO Output Leakage CE = VIH or Vcc -1 1 µA
Vi/o = Gnd to Vcc
VOH High level output voltage IOH = - 1.0 mA 2.4 Vcc - 0.1 V
VOL Low level output voltage IOL = 2.1 mA - 0.2 0.4 V
VTP Write protection voltage - 4.25 4.37 4.49 V
Capacitance
Parameter Description Test conditons Min. Typ Max Unit
CADD Address capacitance VADD = 0V - 3 5 pF
CIInput capacitance Vi =0V - 5 6 pF
CI/O I/O capacitance VIO = 0V - 6 7 pF
µA
µA
INNOVATIVE IM1250Y-100
512K X 8 NO POWER SRAM
Switching Characteristics over the operating range
Parameter Description Min Max Unit
tRC Read cycle time 100 - ns
tACC Address access time - 100 ns
tOE Output enable access time - 50 ns
tco CE to output valid - 100 ns
tCOE OE or CE to output valid 5 - ns
tOD Output High Z from Deselection - 35 ns
tOH Output hold from adds change 5 - ns
tWC Write cycle time 100 - ns
tAW Address setup time 0 - ns
tWP Write pulse-width 75 - ns
tWR Write recovery time 5 - ns
tODW Output High Z from WE 35 ns
tOEW Output Active from WE 5 - ns
tDS Input data setup time 40 - ns
tDH1 Input data hold time 15 - ns
INNOVATIVE IM1250Y-100
512K X 8 NO POWER SRAM
VIL VIL
VIH VIH
VIH
VIL VIL
VIL VIL
tAW
tWP tWR
tODW tOEW
High
Impedance
DOUT
WRITE CYCLE 1
tDS tDH1
VIL
VIL
VIH
VIH Data In
Stable
DIN
CE
WE
VIH VIH
VIH VIL
VIH
VIH VIL
VIH
tCOE
tCOE
tOD
tOD
VOL
VOH
VOH
VOL
DOUT OUTPUT
DA T A V ALID
VIL VIL
CE
OE
READ CYCLE
Address tACC
tCO
tOH
tRC
tWC
ADDRESS
tOE
INNOVATIVE IM1250Y-100
512K X 8 NO POWER SRAM
FIG. D POWER – DOWN/ POWER –ON CONDITION
4.75V —————————————————————————————————————————————————
tF tR
3.2V ——————————————————————————————————————————————————
tPD tREC
LI Cell
Leakage Current Data Retention T ime
tDR
Notes:
1. WE is to be high during read cycle.
2. During write cycle that is controlled by CE, output buffer is in high impedance state irrespective of whether OE is
high or low level.
3. During write cycle that is controlled by WE, output buffer is in high impedance state if OE is high.
VIH VIL VIL VIH
VIL VIL
tODW
tCOE
tDS tDH
VIL
VIL
VIH
VIH Data In
Stable
DIN
VIL VIL
VIH VIH
tAW tWP
tWR
DOUT
WE
CE
ADDRESSES
WRITE CYCLE 2
INNOVATIVE IM1250Y-100
512K X 8 NO POWER SRAM
J
H
A
C
F
G E
D
DIM IN INCHES MIN. MAX.
A 1.72 1.754
B 0.72 0.74
C 0.395 0.415
D 0.09 0.12
E 0.015 0.021
F 0.12 0.16
G 0.09 0.11
H 0.59 0.63
J 0.008 0.012
INNOVATIVE
IM 1250Y - 100
NO POWER SRAM
B
mm - yy
INNOVATIVE IM1250Y-100
512K X 8 NO POWER SRAM
