5-1
FAST AND LS TTL DATA
4-BIT D-TYPE REGISTER
WITH 3-STATE OUTPUTS
The SN54/74LS173A is a high-speed 4-Bit Register featuring 3-state
outputs for use in bus-organized systems. The clock is fully edge-triggered
allowing either a load from the D inputs or a hold (retain register contents)
depending on the state of the Input Enable Lines (IE1, IE2). A HIGH on either
Output Enable line (OE1, OE2) brings the output to a high impedance state
without affecting the actual register contents. A HIGH on the Master Reset
(MR) input resets the Register regardless of the state of the Clock (CP), the
Output Enable (OE1, OE2) or the Input Enable (IE1, IE2) lines.
•Fully Edge-Triggered
•3-State Outputs
•Gated Input and Output Enables
•Input Clamp Diodes Limit High-Speed Termination Effects
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM DIP (TOP VIEW)
14 13 12 11 10 9
1234567
16 15
8
VCC
OE1
MR D0D1D2IE2
D3IE1
OE2Q0Q1Q2Q3CP GND
PIN NAMES LOADING (Note a)
HIGH LOW
D0–D3
IE1–IE2
OE1–OE2
CP
MR
Q0–Q3
Data Inputs
Input Enable (Active LOW)
Output Enable (Active LOW) Inputs
Clock Pulse (Active HIGH Going Edge)
Input
Master Reset Input (Active HIGH)
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 (25) U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 (7.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
SN54/74LS173A
4-BIT D-TYPE REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16 1
16
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
16 1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
D0D1D2D3
CP
OEMR
1 2
11
22Q1
Q0Q2Q3
910 14131211
345615
7IE
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
5-2
FAST AND LS TTL DATA
SN54/74LS173A
LOGIC DIAGRAM
CP
MR
Q0Q1Q2Q3
D0D1D2D3
CP
Q
D
Q
IE1
IE2
OE2
OE1
14
6
7
3 4 5
9
1112
10
13
15
D D D
1
2
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
TRUTH TABLE
MR CP IE1IE2DnQn
H x x x x L
L L x x x Qn
L H x x Qn
L x H x Qn
L L L L L
L L L H H
When either OE1, or OE2 are HIGH, the output is in the of f state (High Impedance);
however this does not affect the contents or sequential operation of the register.
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 –55
025
25 125
70 °C
IOH Output Current — High 54
74 –1.0
–2.6 mA
IOL Output Current — Low 54
74 12
24 mA
5-3
FAST AND LS TTL DATA
SN54/74LS173A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
V
IL
I
npu
t
LOW
V
o
lt
age 74 0.8
V
pg
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54 2.4 3.4 V VCC = MIN, IOH = MAX, VIN = VIH
V
OH
O
u
t
pu
t
HIGH
V
o
lt
age 74 2.4 3.1 V
CC ,OH ,IN IH
or VIL per T ruth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 12 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
O
u
t
pu
t
LOW
V
o
lt
age 74 0.35 0.5 V IOL = 24 mA
V
IN =
V
IL or
V
IH
per T ruth Table
IOZH Output Off Current HIGH 20 µA VCC = MAX, VO = 2.7 V
IOZL Output Off Current LOW –20 µA VCC = MAX, VO = 0.4 V
IIH
Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
I
IH
I
npu
t
HIGH
C
urren
t
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –30 –130 mA VCC = MAX
ICC Power Supply Current 30 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit T est Conditions
fMAX Maximum Input Clock Frequency 30 50 MHz
V50V
tPLH
tPHL Propagation Delay,
Clock to Output 17
22 25
30 ns VCC = 5.0 V
CL=45pF
tPHL Propagation Delay, MR to Output 26 35 ns
C
L =
45
p
F
,
RL = 667 Ω
tPZH
tPZL Output Enable T ime 15
18 23
27 ns
L
tPLZ
tPHZ Output Disable T ime 11
11 17
17 ns CL = 5.0 pF,
RL = 667 Ω
AC SETUP REQUIREMENTS (TA = 25°C)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit T est Conditions
tWClock or MR Pulse Width 20 ns
V50V
tsData Enable Setup T ime 35 ns
V50V
tsData Setup T ime 17 ns VCC = 5.0 V
thHold T ime, Any Input 0 ns
trec Recovery Time 10 ns
AC WAVEFORMS
Figure 1 Figure 2
1.3 V
1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
1.3 V
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
1.3 V
≈
1.3 V
ts(H) th(H) ts(L) th(L)
CP
D or E
Q
Q
CP
MR
tPHL
tPLH
VE
VOUT
tPLZ tPZL
0.5 V 0.5 V
VE
VOUT
VOL
≥
VOH
tPHZ
tPZH
VCC
RL
SW1
TO OUTPUT
UNDER TEST
CL*SW2
5 k
Ω
1.3 V
1 / fmax
tWtrec
tPHL
tW
Figure 3 Figure 4
Figure 5
AC LOAD CIRCUIT
SWITCH POSITIONS
*Includes Jig and Probe Capacitance.
5-4
FAST AND LS TTL DATA
SN54/74LS173A
SYMBOL SW1 SW2
tPZH Open Closed
tPZL Closed Open
tPLZ Closed Closed
tPHZ Closed Closed
