1k 10k 1M 10M
FREQUENCY (Hz)
1
10
100
100k
100 1
10
100
INPUT VOLTAGE NOISE (nV/
Hz)
INPUT CURRENT NOISE (pA/
Hz)
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LMH6654, LMH6655 Single and Dual Low Power, 250 MHz, Low Noise Amplifiers
1 Features 3 Description
The LMH6654 and LMH6655 single and dual high
1• (VS= ±5 V, TJ= 25 °C, Typical Values Unless speed voltage feedback amplifiers are designed to
Specified) have unity-gain stable operation with a bandwidth of
• Voltage Feedback Architecture 250 MHz. They operate from ±2.5 V to ±6 V and each
• Unity Gain Bandwidth 250 MHz channel consumes only 4.5 mA. The amplifiers
feature very low voltage noise and wide output swing
• Supply Voltage Range ±2.5V to ±6V to maximize signal-to-noise ratio, and possess a true
• Slew Rate 200 V/µsec single supply capability with input common mode
• Supply Current 4.5 mA/channel voltage range extending 150 mV below negative rail
and within 1.3 V of the positive rail. The high speed
• Input Common Mode Voltage −5.15V to +3.7V and low power combination of the LMH6654 and
• Output Voltage Swing (RL= 100 Ω)−3.6V to 3.4V LMH6655 make these products an ideal choice for
• Input Voltage Noise 4.5 nV/√Hz many portable, high speed applications where power
• Input Current Noise 1.7 pA/√Hz is at a premium.
• Settling Time to 0.01% 25 ns The LMH6654 and LMH6655 are built on TI’s
Advance VIP10™ (Vertically Integrated PNP)
2 Applications complementary bipolar process.
• ADC Drivers The LMH6654 is packaged in 5-Pin SOT-23 and 8-
Pin SOIC. The LMH6655 is packaged in 8-Pin
• Consumer Video VSSOP (DGK) and 8-Pin SOIC.
• Active Filters
• Pulse Delay Circuits Device Information(1)
• xDSL Receiver PART NUMBER PACKAGE BODY SIZE (NOM)
• Pre-amps LMH6654 SOIC (8) 4.90 mm x 3.91 mm
LMH6654 SOT-23 (5) 2.90 mm x 1.60 mm
LMH6655 SOIC (8) 4.90 mm x 3.91 mm
LMH6655 VSSOP (8) 3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Figure 1. Input Voltage and Curernt Noise vs.
Frequency (Vs= ±5V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6654
,
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SNOS956E –JUNE 2001–REVISED AUGUST 2014
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Table of Contents
1 Features.................................................................. 17 Application and Implementation ........................ 16
7.1 Application Information............................................ 16
2 Applications ........................................................... 17.2 Typical Application.................................................. 16
3 Description............................................................. 18 Power Supply Recommendations...................... 20
4 Revision History..................................................... 28.1 Power Dissipation ................................................... 20
5 Pin Configuration and Functions......................... 39 Layout................................................................... 20
6 Specifications......................................................... 49.1 Layout Guidelines ................................................... 20
6.1 Absolute Maximum Ratings ...................................... 410 Device and Documentation Support................. 21
6.2 Handling Ratings....................................................... 410.1 Documentation Support ........................................ 21
6.3 Recommended Operating Conditions....................... 410.2 Electrostatic Discharge Caution............................ 21
6.4 Thermal Information.................................................. 410.3 Glossary................................................................ 21
6.5 ±5V Electrical Characteristics ................................... 511 Mechanical, Packaging, and Orderable
6.6 5V Electrical Characteristics ..................................... 7Information........................................................... 21
6.7 Typical Characteristics.............................................. 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E Page
• Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device
Information Table, Application and Implementation; Power Supply Recommendations; Device and Documentation
Support; Mechanical, Packaging, and Ordering Information. Deleted Switching Characteristics due to redundancy. ......... 1
• Changed from Junction Temperature Range to "Operating Temperature Range"................................................................ 4
• Deleted TJ= 25°C................................................................................................................................................................... 5
• Deleted TJ= 25°C .................................................................................................................................................................. 7
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 19
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OUT B
1
2
3
4 5
6
7
8
OUT A
-IN A
+IN A
V-
V+
-IN B
+IN B
-+
+-
A
B
V+
1
2
3
4 5
6
7
8
N/C
-IN
+IN
V-
OUTPUT
N/C
N/C
+
-
OUTPUT
V-
+IN
V+
-IN
+-
1
2
3
5
4
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5 Pin Configuration and Functions
5-Pin (LMH6654) 8-Pin (LMH6654) 8-Pin (LMH6655)
Package DBV Package D SOIC and VSSOP (DGK)
Top View Top View Top View
Pin Functions
PIN
LMH6654 LMH6655 I/O DESCRIPTION
NAME DBV D DGK
-IN 4 2 I Inverting Input
+IN 3 3 I Non-inverting Input
-IN A 2 I ChA Inverting Input
+IN A 3 I ChA Non-inverting Input
-IN B 6 I ChB Inverting Input
+IN B 5 I ChB Non-inverting Input
N/C 1, 5, 8 –– No Connection
OUT A 1 O ChA Output
OUT B 7 O ChB Output
OUTPUT 1 6 O Output
V-2 4 4 I Negative Supply
V+5 7 8 I Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Differential ±1.2 V
Output Short Circuit Duration See (2)
Supply Voltage (V+−V−) 13.2 V
V++0.5
Voltage at Input pins V
V--0.5
Junction Temperature(3) 150 °C
Infrared or Convection (20 sec.) 235 °C
Soldering Information Wave Soldering (10 sec.) 260 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
(3) The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) −TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range −65 150 °C
Human body model (HBM), 2000
per ANSI/ESDA/JEDEC JS-001, all pins(2)
V(ESD) Electrostatic discharge(1) V
Machine model (MM)(3) 200
(1) Human body model, 1.5 kΩin series with 100 pF. Machine model: 0Ωin series with 100 pF.
(2) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions(1)
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Supply Voltage (V+- V−) ±2.5 ±6.0 V
Operating Temperature Range −40 85 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Table.
6.4 Thermal Information SOIC (D) VSSOP (DGK) SOT-23 (D)
THERMAL METRIC(1) UNIT
8 PINS 8 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 172 235 265 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 ±5V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+= +5V, V−=−5V, VCM = 0V, AV= +1, RF= 25Ωfor gain = +1, RF= 402Ω
for gain ≥+2, and RL= 100Ω.Boldface limits apply at the temperature extremes.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
DYNAMIC PERFORMANCE
AV= +1 250
AV= +2 130
fCL Close Loop Bandwidth MHz
AV= +5 52
AV= +10 26
Gain Bandwidth Product AV≥+5 260 MHz
GBWP Bandwidth for 0.1 dB Flatness AV+1 18 MHz
φm Phase Margin 50 deg
SR Slew Rate (3) AV= +1, VIN = 2 VPP 200 V/µs
Settling Time 25 ns
0.01%
tSAV= +1, 2V Step
0.1% 15 ns
trRise Time AV= +1, 0.2V Step 1.4 ns
tfFall Time AV= +1, 0.2V Step 1.2 ns
DISTORTION and NOISE RESPONSE
enInput Referred Voltage Noise f ≥0.1 MHz 4.5 nV/√Hz
inInput-Referred Current Noise f ≥0.1 MHz 1.7 pA/√Hz
Second Harmonic Distortion AV= +1, f = 5 MHz −80 dBc
Third Harmonic Distortion VO= 2 VPP, RL= 100Ω −85
Input Referred, 5 MHz, dB
XtCrosstalk (for LMH6655 only) −80
Channel-to-Channel
DG Differential Gain AV= +2, NTSC, RL= 150Ω0.01%
DP Differential Phase AV= +2, NTSC, RL= 150Ω0.025 deg
INPUT CHARACTERISTICS
−3 3
VOS Input Offset Voltage VCM = 0V ±1 mV
−4 4
TC VOS Input Offset Average Drift VCM = 0V (4) 6 µV/°C
12
IBInput Bias Current VCM = 0V 5 µA
18
−1 1
IOS Input Offset Current VCM = 0V 0.3 µA
−2 2
Common Mode 4 MΩ
RIN Input Resistance Differential Mode 20 kΩ
Common Mode 1.8
CIN Input Capacitance pF
Differential Mode 1
Input Referred, 70
CMRR Common Mode Rejection Ration 90 dB
VCM = 0V to −5V 68
−5.15 −5.0
CMVR Input Common- Mode Voltage Range CMRR ≥50 dB V
3.5 3.7
TRANSFER CHARACTERISTICS
VO= 4 VPP, RL= 100Ω60
AVOL Large Signal Voltage Gain 67 dB
58
(1) All limits are specified by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step.
(4) Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
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±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+= +5V, V−=−5V, VCM = 0V, AV= +1, RF= 25Ωfor gain = +1, RF= 402Ω
for gain ≥+2, and RL= 100Ω.Boldface limits apply at the temperature extremes.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
OUTPUT CHARACTERISTICS
3.4
Output Swing High No Load 3.6
3.2
−3.7
VOOutput Swing Low No Load −3.9 V
−3.5
3.2
Output Swing High RL= 100Ω3.4
3.0
−3.4
Output Swing Low RL= 100Ω −3.6 −3.2
Sourcing, VO= 0V 145 280
ΔVIN = 200 mV 130
ISC Short Circuit Current (5) mA
Sinking, VO= 0V 100 185
ΔVIN = 200 mV 80
Sourcing, VO= +3V 80
IOUT Output Current mA
Sinking, VO=−3V 120
ROOutput Resistance AV= +1, f <100 kHz 0.08 Ω
POWER SUPPLY
Input Referred, dB
PSRR Power Supply Rejection Ratio 60 76
VS= ±5V to ±6V 6
ISSupply Current (per channel) 4.5 mA
7
(5) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
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6.6 5V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+= +5V, V−=−0V, VCM = 2.5V, AV= +1, RF= 25 Ωfor gain = +1,
RF= 402Ωfor gain ≥+2, and RL= 100Ωto V+/2. Boldface limits apply at the temperature extremes.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
DYNAMIC PERFORMANCE
AV= +1 230
AV= +2 120
fCL Close Loop Bandwidth MHz
AV= +5 50
AV= +10 25
GBWP Gain Bandwidth Product AV≥+5 250 MHz
Bandwidth for 0.1 dB Flatness AV= +1 17 MHz
φm Phase Margin 48 deg
SR Slew Rate (3) AV= +1, VIN = 2 VPP 190 V/µs
Settling Time ns
30
0.01%
tSAV= +1, 2V Step
0.1% 20 ns
trRise Time AV= +1, 0.2V Step 1.5 ns
tfFall Time AV= +1, 0.2V Step 1.35 ns
DISTORTION and NOISE RESPONSE
enInput Referred Voltage Noise f ≥0.1 MHz 4.5 nV/√Hz
inInput Referred Current Noise f ≥0.1 MHz 1.7 pA/√Hz
Second Harmonic Distortion AV= +1, f = 5 MHz −65 dBc
Third Harmonic Distortion VO= 2 VPP, RL= 100Ω −70
XtCrosstalk (for LMH6655 only) Input Referred, 5 MHz −78 dB
INPUT CHARACTERISTICS
−5 5
VOS Input Offset Voltage VCM = 2.5V ±2 mV
−6.5 6.5
TC VOS Input Offset Average Drift VCM = 2.5V (4) 6µV/°C
12
IBInput Bias Current VCM = 2.5V 6 µA
18
−2 2
IOS Input Offset Current VCM = 2.5V 0.5 µA
−3 3
Common Mode 4 MΩ
RIN Input Resistance Differential Mode 20 kΩ
Common Mode 1.8
CIN Input Capacitance pF
Differential Mode 1
Input Referred, 70
CMRR Common Mode Rejection Ration 90 dB
VCM = 0V to −2.5V 68
CMRR ≥50 dB −0.15 0
CMVR Input Common Mode Voltage Range V
3.5 3.7
TRANSFER CHARACTERISTICS
VO= 1.6 VPP, RL= 100Ω58
AVOL Large Signal Voltage Gain 64 dB
55
(1) All limits are specified by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step.
(4) Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+= +5V, V−=−0V, VCM = 2.5V, AV= +1, RF= 25 Ωfor gain = +1,
RF= 402Ωfor gain ≥+2, and RL= 100Ωto V+/2. Boldface limits apply at the temperature extremes.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
OUTPUT CHARACTERISTICS
3.6
Output Swing High No Load 3.75
3.4
1.1
VOOutput Swing Low No Load 0.9 V
1.3
3.5
Output Swing High RL= 100Ω3.70
3.35
1.3
Output Swing Low RL= 100Ω11.45
Sourcing , VO= 2.5V 90 170
ΔVIN = 200 mV 80
ISC Short Circuit Current (5) mA
Sinking, VO= 2.5V 70 140
ΔVIN = 200 mV 60
Sourcing, VO= +3.5V 30
IOUT Output Current mA
Sinking, VO= 1.5V 60
ROOutput Resistance AV= +1, f <100 kHz .08 Ω
POWER SUPPLY
Input Referred , dB
PSRR Power Supply Rejection Ratio 60 75
VS= ± 2.5V to ± 3V 6
ISSupply Current (per channel) 4.5 mA
7
(5) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
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-60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
SUPPLY CURRENT (mA)
VS = ±5V
VS = 5V
1M 10M 100M 1G
FREQUENCY (dB)
-26
-21
-16
-11
-6
-1
4
9
14
19
24
GAIN (dB)
VS = ±2.5V
VS = ±5V
1M 10M 100M 1G
FREQUENCY (Hz)
-25
-20
-15
-10
-5
0
5
10
15
20
25
GAIN (dB)
VS = ±5V
VS = ±2.5V
1M 10M 100M 1G
FREQUENCY (Hz)
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
GAIN (dB)
VS = ±2.5V
VS = ±5V
1M 10M 100M 1G
FREQUENCY (Hz)
-21
-18
-15
-12
-9
-6
-3
0
3
6
9
GAIN (dB)
VS = ±2.5V
VS = ±5V
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6.7 Typical Characteristics
25°C, V+= ±5 V, V−=−5, RF= 25 Ωfor gain = +1, RF= 402 Ωfor gain ≥+2 and RL= 100 Ω, unless otherwise specified.
Figure 2. Closed Loop Bandwidth (G = +1) Figure 3. Closed Loop Bandwidth (G = +2)
Figure 4. Closed Loop Bandwidth (G = +5) Figure 5. Closed Loop Bandwidth (G = +10)
Figure 6. Supply Current per Channel Figure 7. Supply Current per Channel
vs. Supply Voltage vs. Temperature
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00.5 1 1.5 2 2.5 3 3.5
VCM (V)
-1
0
1
2
3
4
5
6
7
POSITIVE IBIAS (µA)
-40°C
25°C
85°C
VS = 5V
0 0.5 1 1.5 2 2.5 3 3.5
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
VOS (mV)
VCM (V)
VS = ±2.5V
-40°C
85°C
25°C
-50 0 50 100
0
1
2
3
4
5
6
7
INPUT BIAS CURRENT (µA)
TEMPERATURE (°C)
IBIAS
VOS
OFFSET VOLTAGE (mV)
45 6 7 8 9 10 11 12
VSUPPLY (V)
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
VOS (mV)
85°C
-40°C
25°C
01 2 3 4 5 6 7 8
VCM (V)
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
VOS (mV)
VS = ±5V -40°C
85°C
25°C
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Typical Characteristics (continued)
25°C, V+= ±5 V, V−=−5, RF= 25 Ωfor gain = +1, RF= 402 Ωfor gain ≥+2 and RL= 100 Ω, unless otherwise specified.
Figure 9. Offset Voltage
Figure 8. Offset Voltage vs. Common Mode
vs. Supply Voltage (VCM = 0V)
Figure 11. Bias Current and Offset Voltage
Figure 10. Offset Voltage vs. Temperature
vs. Common Mode
Figure 13. Bias Current
Figure 12. Bias Current vs. Common Mode Voltage
vs. Common Mode Voltage
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OUTPUT INPUT
(1 V/div)
TIME (12.5 ns/div)
OUTPUT INPUT
(100 mV/div)
TIME (12.5 ns/div)
OUTPUT INPUT
(1 V/div)
TIME (12.5 ns/div)
OUTPUT INPUT
TIME (12.5 ns/div)
(1 V/div)
-50 0 50 100
60
70
80
90
100
110
120
AoL, PSRR, AND CMRR (dB)
TEMPERATURE (°C)
CMRR
PSRR
AoL @ ±5V
AoL @ 5V
OUTPUT
TIME (12.5 ns/div)
INPUT
(1 V/div)
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Typical Characteristics (continued)
25°C, V+= ±5 V, V−=−5, RF= 25 Ωfor gain = +1, RF= 402 Ωfor gain ≥+2 and RL= 100 Ω, unless otherwise specified.
Figure 15. Inverting Large Signal Pulse Response
Figure 14. AOL, PSRR and CMRR (VS= 5V)
vs. Temperature
Figure 16. Inverting Large Signal Pulse Response Figure 17. Non-Inverting Large Signal Pulse Response
(VS= ±5V) (VS= 5V)
Figure 18. Non-Inverting Large Signal Pulse Response Figure 19. Non-Inverting Small Signal Pulse Response
(VS= ±5V) (VS= 5V)
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0.1 1 10 100
FREQUENCY (MHz)
-110
-100
-90
-80
-70
-60
-50
-40
-30
HARMONIC DISTORTION (dBc)
3RD
2ND
1k 10k 1M 10M
FREQUENCY (Hz)
1
10
100
100k
100 1
10
100
INPUT VOLTAGE NOISE (nV/
Hz)
INPUT CURRENT NOISE (pA/
Hz)
en
in
OUTPUT
TIME (12.5 ns/div)
INPUT
(100 mV/div)
1k 10k 1M 10M
FREQUENCY (Hz)
1
10
100
100k
100 1
10
100
INPUT VOLTAGE NOISE (nV/
Hz)
INPUT CURRENT NOISE (pA/
Hz)
en
in
OUTPUT
TIME (12.5 ns/div)
INPUT
(100 mV/div)
OUTPUT INPUT
(100 mV/div)
TIME (12.5 ns/div)
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Typical Characteristics (continued)
25°C, V+= ±5 V, V−=−5, RF= 25 Ωfor gain = +1, RF= 402 Ωfor gain ≥+2 and RL= 100 Ω, unless otherwise specified.
Figure 20. Non-Inverting Small Signal Pulse Response Figure 21. Inverting Small Signal Pulse Response
(VS= ±5V) (VS= 5V)
Figure 23. Input Voltage and Current Noise
Figure 22. Inverting Small Signal Pulse Response vs. Frequency (VS= 5V)
(VS= ±5V)
Figure 24. Input Voltage and Current Noise Figure 25. Harmonic Distortion
vs. Frequency (VS= ±5V) vs. Frequency
G = +1, VO= 2 VPP, VS= 5V
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1 2 3 4 5 6 7 8 9 10
-45
HARMONIC DISTORTION (dBc)
GAIN (V/V)
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
2ND
3RD
0.0 0.5 1.0 1.5 2.0 2.5
-100
-90
-80
-70
-60
-50
-40
-30
HARMONIC DISTORTION (dBc)
OUTPUT SWING (VPP)
2ND
3RD
-60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
-100
-95
-90
-85
-80
-75
-70
-65
-60
HARMONIC DISTORTION (dBc)
2ND
3RD
1 2 3 4 5 6 7 8 9 10
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
HARMONIC DISTORTION (dBc)
GAIN (V/V)
2ND
3RD
0.1 1 10 100
FREQUENCY (MHz)
-110
-100
-90
-80
-70
-60
-50
-40
-30
HARMONIC DISTORTION (dBc)
3RD
2ND
-60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
-100
-95
-90
-85
-80
-75
-70
-65
-60
HARMONIC DISTORTION (dBc)
2ND
3RD
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LMH6655
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SNOS956E –JUNE 2001–REVISED AUGUST 2014
Typical Characteristics (continued)
25°C, V+= ±5 V, V−=−5, RF= 25 Ωfor gain = +1, RF= 402 Ωfor gain ≥+2 and RL= 100 Ω, unless otherwise specified.
Figure 27. Harmonic Distortion
Figure 26. Harmonic Distortion vs. Temperature
vs. Frequency VS= 5V, f = 5 MHz, VO= 2 VPP
G = +1, VO= 2 VPP, VS= ±5V
Figure 29. Harmonic Distortion
Figure 28. Harmonic Distortion vs. Gain
vs. Temperature VS= 5V, f = 5 MHz, VO= 2 VPP
VS= ±5V, f = 5 MHz, VO= 2 VPP
Figure 30. Harmonic Distortion Figure 31. Harmonic Distortion
vs. Gain vs. Output Swing
VS= ±5V, f = 5 MHz, VO= 2 VPP (G = +2, VS= 5V, f = 5 MHz)
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMH6654 LMH6655
0
1
2
5
VOUT REFERENCED TO V+ (V)
.01 0.1 1 10 100
3
4
1
k
VS = ±5V
OUTPUT SOURCING CURRENT (mA)
VS = 5V
100k 1M 10M 100M
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
CROSSTALK REJECTION (dB)
FREQUENCY (Hz)
VS = 5V
0
1
2
5
VOUT REFERENCED TO V- (V)
.01 0.1 1 10 100
OUTPUT SINKING CURRENT (mA)
3
4
1
k
VS = 5V
VS = ±5V
10 1k 100k 10M
FREQUENCY
0
40
80
120
CMRR (dB)
1M
10k
100
100
60
20
VS = ±5V
0 1 2 3 4 5 6 7 8
-100
-30
HARMONIC DISTORTION (dBc)
OUTPUT SWING (VPP)
-90
-80
-70
-60
-50
-40
2ND
3RD
PSRR (dB)
90
10 1k 100k 10M
FREQUENCY (Hz)
0
20
60
1M10k
100
80
70
50
30
10
40
100 NEGATIVE
POSITIVE
LMH6654
,
LMH6655
SNOS956E –JUNE 2001–REVISED AUGUST 2014
www.ti.com
Typical Characteristics (continued)
25°C, V+= ±5 V, V−=−5, RF= 25 Ωfor gain = +1, RF= 402 Ωfor gain ≥+2 and RL= 100 Ω, unless otherwise specified.
Figure 33. PSRR vs. Frequency
Figure 32. Harmonic Distortion
vs. Output Swing
(G = +2, VS= ±5V, f = 5 MHz)
Figure 34. CMRR vs. Frequency Figure 35. Output Sinking Current
Figure 37. CrossTalk
Figure 36. Output Sourcing Current vs. Frequency (LMH6655 only)
14 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6654 LMH6655
1k 100k 10M 500M
FREQUENCY (Hz)
-20
20
60
100
GAIN (dB)
100M1M
10k
90
70
40
30
-10
80
10
0
50
PHASE
GAIN
180
144
108
72
36
0
-36
-72
-108
-144
-180
PHASE (°)
100k 1M 10M 100M
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
CROSSTALK REJECTION (dB)
FREQUENCY (Hz)
VS = ±5V
LMH6654
,
LMH6655
www.ti.com
SNOS956E –JUNE 2001–REVISED AUGUST 2014
Typical Characteristics (continued)
25°C, V+= ±5 V, V−=−5, RF= 25 Ωfor gain = +1, RF= 402 Ωfor gain ≥+2 and RL= 100 Ω, unless otherwise specified.
Figure 38. CrossTalk Figure 39. Isolation Resistance
vs. Frequency (LMH6655 only) vs. Capacitive Load
Figure 40. Open Loop Gain and Phase
vs. Frequency
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMH6654 LMH6655
-
+
25:
VIN
RISO VOUT
F = 1
2 S RISO CLOAD
LMH6654
,
LMH6655
SNOS956E –JUNE 2001–REVISED AUGUST 2014
www.ti.com
7 Application and Implementation
7.1 Application Information
The LMH6654 single and LMH6655 dual high speed, voltage feedback amplifiers are manufactured on TI’s new
VIP10™ (Vertically Integrated PNP) complementary bipolar process. These amplifiers can operate from ±2.5 V to
±6 V power supply. They offer low supply current, wide bandwidth, very low voltage noise and large output
swing. Many of the typical performance plots found in the datasheet can be reproduced if 50 Ωcoax and 50 Ω
RIN/ROUT resistors are used.
7.2 Typical Application
7.2.1 Design Requirements
7.2.1.1 Components Selection and Feedback Resistor
It is important in high-speed applications to keep all component leads short since wires are inductive at high
frequency. For discrete components, choose carbon composition axially leaded resistors and micro type
capacitors. Surface mount components are preferred over discrete components for minimum inductive effect.
Never use wire wound type resistors in high frequency applications.
Large values of feedback resistors can couple with parasitic capacitance and cause undesired effects such as
ringing or oscillation in high-speed amplifiers. Keep resistors as low as possible consistent with output loading
consideration. For a gain of 2 and higher, 402 Ωfeedback resistor used for the typical performance plots gives
optimal performance. For unity gain follower, a 25 Ωfeedback resistor is recommended rather than a direct short.
This effectively reduces the Q of what would otherwise be a parasitic inductance (the feedback wire) into the
parasitic capacitance at the inverting input.
7.2.2 Detailed Design Procedure
7.2.2.1 Driving Capacitive Loads
Capacitive loads decrease the phase margin of all op amps. The output impedance of a feedback amplifier
becomes inductive at high frequencies, creating a resonant circuit when the load is capacitive. This can lead to
overshoot, ringing and oscillation. To eliminate oscillation or reduce ringing, an isolation resistor can be placed as
shown in Figure 41 below. At frequencies above
(1)
the load impedance of the Amplifier approaches RISO. The desired performance depends on the value of the
isolation resistor. The isolation resistance vs. capacitance load graph in the typical performance characteristics
provides the means for selection of the value of RSthat provides ≤3 dB peaking in closed loop AV= 1 response.
In general, the bigger the isolation resistor, the more damped the pulse response becomes. For initial evaluation,
a 50Ωisolation resistor is recommended.
Figure 41. Isolation Resistor Placement
16 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6654 LMH6655
LMH6654
,
LMH6655
www.ti.com
SNOS956E –JUNE 2001–REVISED AUGUST 2014
Typical Application (continued)
7.2.2.2 Bias Current Cancellation
In order to cancel the bias current errors of the non-inverting configuration, the parallel combination of the gain
setting Rgand feedback Rfresistors should equal the equivalent source resistance Rseq as defined in Figure 42.
Combining this constraint with the non-inverting gain equation, allows both Rfand Rgto be determined explicitly
from the following equations:
Rf= AVRseq and Rg= Rf/(AV−1) (2)
For inverting configuration, bias current cancellation is accomplished by placing a resistor Rbon the non-inverting
input equal in value to the resistance seen by the inverting input (Rf//(Rg+Rs). The additional noise contribution of
Rbcan be minimized through the use of a shunt capacitor.
Figure 42. Non-Inverting Amplifier Configuration
Figure 43. Inverting Amplifier Configuration
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMH6654 LMH6655
eni =en
2+ 2 (in· RSeq)2+ 4kT (2RSeq)
eni =en
2+ (in+ · RSeq)2+ 4kTRSeq + (in- · (Rf|| Rg))2+ 4kT(Rf|| Rg)
et = 4kTR
LMH6654
,
LMH6655
SNOS956E –JUNE 2001–REVISED AUGUST 2014
www.ti.com
Typical Application (continued)
7.2.2.3 Total Input Noise vs. Source Resistance
The noise model for the non-inverting amplifier configuration showing all noise sources is described in Figure 44.
In addition to the intrinsic input voltage noise (en) and current noise (in= in+ = in−) sources, there also exits
thermal voltage noise associated with each of the external resistors. Equation 3 provides the general
form for total equivalent input voltage noise density (eni). Equation 4 is a simplification of Equation 3 that
assumes Rf|| Rg= Rseq for bias current cancellation. Figure 45 illustrates the equivalent noise model using this
assumption. The total equivalent output voltage noise (eno) is eni * AV.
Figure 44. Non-Inverting Amplifier Noise Model
(3)
Figure 45. Noise Model with Rf|| Rg= Rseq
(4)
If bias current cancellation is not a requirement, then Rf|| Rgdoes not need to equal Rseq. In this case, according
to Equation 3, Rfand Rgshould be as low as possible in order to minimize noise. Results similar to Equation 3
are obtained for the inverting configuration on if Rseq is replaced by Rb|| Rgis replaced by Rg+ Rs. With these
substitutions, Equation 3 will yield an eni referred to the non-inverting input. Referring eni to the inverting input is
easily accomplished by multiplying eni by the ratio of non-inverting to inverting gains.
18 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6654 LMH6655
4kTRSeq
en
2+ in
2(RSeq + (Rf|| Rg))2+ 4KTRSeq + 4kt (Rf|| Rg)
NF = 10LOG Si/Ni
So/No= 10LOG eni2
et2
LMH6654
,
LMH6655
www.ti.com
SNOS956E –JUNE 2001–REVISED AUGUST 2014
Typical Application (continued)
7.2.2.3.1 Noise Figure
Noise Figure (NF) is a measure of the noise degradation caused by an amplifier.
(5)
The noise figure formula is shown in Equation 5. The addition of a terminating resistor RT, reduces the external
thermal noise but increases the resulting NF.
The NF is increased because the RTreduces the input signal amplitude thus reducing the input SNR.
(6)
The noise figure is related to the equivalent source resistance (Rseq) and the parallel combination of Rfand Rg.
To minimize noise figure, the following steps are recommended:
1. Minimize Rf||Rg
2. Choose the Optimum Rs(ROPT)
ROPT is the point at which the NF curve reaches a minimum and is approximated by:
ROPT ≈(en/in)
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMH6654 LMH6655
V+10 µF
0.1 µF
0.1 µF
10 µF
V-
+
+
LMH6654
,
LMH6655
SNOS956E –JUNE 2001–REVISED AUGUST 2014
www.ti.com
8 Power Supply Recommendations
8.1 Power Dissipation
The package power dissipation should be taken into account when operating at high ambient temperature and/or
high power dissipative conditions. In determining maximum operable temperature of the device, make sure the
total power dissipation of the device is considered; this power dissipated in the device with a load connected to
the output as well as the nominal dissipation of the op amp.
9 Layout
9.1 Layout Guidelines
With all high frequency devices, board layouts with stray capacitance have a strong influence on the AC
performance. The LMH6654/LMH6655 are not exception and the inverting input and output pins are particularly
sensitive to the coupling of parasitic capacitance to AC ground. Parasitic capacitances on the inverting input and
output nodes to ground could cause frequency response peaking and possible circuit oscillation. Therefore, the
power supply, ground traces and ground plan should be placed away from the inverting input and output pins.
Also, it is very important to keep the parasitic capacitance across the feedback to an absolute minimum.
The PCB should have a ground plane covering all unused portion of the component side of the board to provide
a low impedance path. All trace lengths should be minimized to reduce series inductance.
Supply bypassing is required for the amplifiers performance. The bypass capacitors provide a low impedance
return current path at the supply pins. They also provide high frequency filtering on the power supply traces. It is
recommended that a ceramic decoupling capacitor 0.1 µF chip should be placed with one end connected to the
ground plane and the other side as close as possible to the power pins. An additional 10 µF tantalum electrolytic
capacitor should be connected in parallel, to supply current for fast large signal changes at the output.
Figure 46. Supply Bypass Capacitors
9.1.1 Evaluation Boards
TI provides the following evaluation boards as a guide for high frequency layout and as an aid in device testing
and characterization.
DEVICE PACKAGE EVALULATION BOARD PN
LMH6654MF 5-Pin SOT-23 LMH730216
LMH6654MA 8-Pin SOIC LMH730227
LMH6655MA 8-Pin SOIC LMH730036
LMH6655MM 8-Pin VSSOP (DGK) LMH730123
20 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6654 LMH6655
LMH6654
,
LMH6655
www.ti.com
SNOS956E –JUNE 2001–REVISED AUGUST 2014
Components Needed to Evaluate the LMH6654 on the LMH730227 Evaluation Board:
• Rf, Rguse the datasheet to select values.
• RIN, ROUT typically 50 Ω(Refer to the Basic Operation section of the evaluation board datasheet for details)
• Rfis an optional resistor for inverting again configurations (select Rfto yield desired input impedance = Rg||Rf)
• C1, C2use 0.1 µF ceramic capacitors
• C3, C4use 10 µF tantalum capacitors
Components not used:
1. C5, C6, C7, C8
2. R1 thru R8
The evaluation boards are designed to accommodate dual supplies. The board can be modified to provide single
operation. For best performance;
1) Do not connect the unused supply.
2) Ground the unused supply pin.
10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
10.1.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LMH6654 Click here Click here Click here Click here Click here
LMH6655 Click here Click here Click here Click here Click here
10.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LMH6654 LMH6655
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6654MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH66
54MA
LMH6654MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH66
54MA
LMH6654MF NRND SOT-23 DBV 5 1000 Non-RoHS
& Green Call TI Call TI -40 to 85 A66A
LMH6654MF/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A66A
LMH6654MFX/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A66A
LMH6655MA NRND SOIC D 8 95 Non-RoHS
& Green Call TI Call TI -40 to 85 LMH66
55MA
LMH6655MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH66
55MA
LMH6655MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH66
55MA
LMH6655MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A67A
LMH6655MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A67A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6654MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6654MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6654MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6654MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6655MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6655MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMH6655MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6654MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6654MF SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6654MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6654MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMH6655MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6655MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMH6655MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/E 09/2019
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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