Wide Supply Range, Rail-to-Rail
Output Instrumentation Amplifier
AD8426
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
FEATURES
2 channels in a small, 4 mm × 4 mm LFCSP
LFCSP package has no metal pad
More routing room
No current leakage to pad
Gain set with 1 external resistor
Gain range: 1 to 1000
Input voltage goes below ground
Inputs protected beyond supplies
Very wide power supply range
Single supply: 2.2 V to 36 V
Dual supply: ±1.35 V to ±18 V
Bandwidth (G = 1): 1 MHz
CMRR (G = 1): 80 dB minimum
Input noise: 24 nV/√Hz
Typical supply current (per amplifier): 350 μA
Specified temperature range: −40°C to +125°C
APPLICATIONS
Industrial process controls
Bridge amplifiers
Medical instrumentation
Portable data acquisition
Multichannel systems
CONNECTION DIAGRAM
1
2
3
4
12
11
10
9
5678
13141516
–IN1
+IN1
RG1
RG1
AD8426
+V
S
OUT1
OUT2
–V
S
–IN2
+IN2
RG2
RG2
09490-001
+V
S
–V
S
REF1
REF2
Figure 1.
Table 1. Instrumentation Amplifiers by Category1
General-
Purpose
Zero
Drift
Military
Grade
Low
Power
High Speed
PGA
AD8220 AD8231 AD620 AD627 AD8250
AD8221 AD8290 AD621 AD623 AD8251
AD8222 AD8293 AD524 AD8235 AD8253
AD8224 AD8553 AD526 AD8236
AD8228 AD8556 AD624 AD8426
AD8295 AD8557 AD8226
AD8227
1 See www.analog.com for the latest instrumentation amplifiers.
GENERAL DESCRIPTION
The AD8426 is a dual-channel, low cost, wide supply range
instrumentation amplifier that requires only one external
resistor to set any gain from 1 to 1000.
The AD8426 is designed to work with a variety of signal
voltages. A wide input range and rail-to-rail output allow the
signal to make full use of the supply rails. Because the input
range can also go below the negative supply, small signals near
ground can be amplified without requiring dual supplies. The
AD8426 operates on supplies ranging from ±1.35 V to ±18 V
for dual supplies and 2.2 V to 36 V for a single supply.
The robust AD8426 inputs are designed to connect to real-
world sensors. In addition to its wide operating range, the
AD8426 can handle voltages beyond the rails. For example,
with a ±5 V supply, the part is guaranteed to withstand ±35 V
at the input with no damage. Minimum and maximum input
bias currents are specified to facilitate open-wire detection.
The AD8426 is designed to make PCB routing easy and efficient.
The two amplifiers are arranged in a logical way so that typical
application circuits have short routes and few vias. Unlike most
chip scale packages, the AD8426 does not have an exposed metal
pad on the bottom of the part, which frees additional space for
routing and vias. The AD8426 offers two in-amps in the equivalent
board space of a typical MSOP package.
The AD8426 is ideal for multichannel, space-constrained industrial
applications. Unlike other low cost, low power instrumentation
amplifiers, the AD8426 is designed with a minimum gain of 1 and
can easily handle ±10 V signals. With its space-saving LFCSP
package and 125°C temperature rating, the AD8426 thrives in
tightly packed, zero airflow designs.
The AD8226 is the single-channel version of the AD8426.
AD8426
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual-Supply Operation ............................................................... 3
Single-Supply Operation ............................................................. 6
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 21
Architecture ................................................................................. 21
Gain Selection ............................................................................. 21
Reference Terminal .................................................................... 22
Input Voltage Range ................................................................... 22
Layout .......................................................................................... 23
Input Bias Current Return Path ............................................... 24
Input Protection ......................................................................... 24
Radio Frequency Interference (RFI) ........................................ 24
Applications Information .............................................................. 25
Precision Strain Gage ................................................................. 25
Differential Drive ....................................................................... 25
Driving a Cable ........................................................................... 26
Driving an ADC ......................................................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
7/11—Revision 0: Initial Version
AD8426
Rev. 0 | Page 3 of 28
SPECIFICATIONS
DUAL-SUPPLY OPERATION
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.
Table 2.
Test Conditions/
Comments
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION
RATIO (CMRR)
VCM = −10 V to +10 V
CMRR, DC to 60 Hz
G = 1 80 90 dB
G = 10 100 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
CMRR at 5 kHz
G = 1 80 80 dB
G = 10 90 90 dB
G = 100 90 90 dB
G = 1000 100 100 dB
NOISE Total noise:
eN = √(eNI2 + (eNO/G)2)
Voltage Noise f = 1 kHz
Input Voltage Noise, eNI 24 27 24 27 nV/√Hz
Output Voltage Noise, eNO 120 125 120 125 nV/√Hz
RTI Noise f = 0.1 Hz to 10 Hz
G = 1 2 2 μV p-p
G = 10 0.5 0.5 μV p-p
G = 100 to 1000 0.4 0.4 μV p-p
Current Noise f = 1 kHz 100 100 fA/√Hz
f = 0.1 Hz to 10 Hz 3 3 pA p-p
VOLTAGE OFFSET Total offset voltage:
VOS = VOSI + (VOSO/G)
Input Offset, VOSI V
S = ±5 V to ±15 V 200 100 μV
Average Temperature
Coefficient
TA = −40°C to +125°C 0.5 2 0.5 1 μV/°C
Output Offset, VOSO V
S = ±5 V to ±15 V 1000 500 μV
Average Temperature
Coefficient
TA = −40°C to +125°C 2 10 1 5 μV/°C
Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V
G = 1 80 90 dB
G = 10 100 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
INPUT CURRENT
Input Bias Current1
TA = +25°C 5 20 27 5 20 27 nA
T
A = +125°C 5 15 25 5 15 25 nA
T
A = −40°C 5 30 35 5 30 35 nA
Average Temperature
Coefficient
TA = −40°C to +125°C 70 70 pA/°C
Input Offset Current TA = +25°C 1.5 0.5 nA
T
A = +125°C 1.5 0.5 nA
T
A = −40°C 2 0.5 nA
Average Temperature
Coefficient
TA = −40°C to +125°C 5 5 pA/°C
AD8426
Rev. 0 | Page 4 of 28
Test Conditions/
Comments
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit
REFERENCE INPUT
RIN 100 100
IIN 7 7 μA
Voltage Range −VS +VS −VS +VS V
Reference Gain to Output 1 1 V/V
Reference Gain Error 0.01 0.01 %
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 1 1000 V/V
Gain Error VOUT ± 10 V
G = 1 0.04 0.01 %
G = 5 to 1000 0.3 0.1 %
Gain Nonlinearity VOUT = −10 V to +10 V
G = 1 to 10 RL ≥ 2 kΩ 20 20 ppm
G = 100 RL ≥ 2 kΩ 75 75 ppm
G = 1000 RL ≥ 2 kΩ 750 750 ppm
Gain vs. Temperature2
G = 1 TA = −40°C to +85°C 5 1 ppm/°C
T
A = +85°C to +125°C 5 2 ppm/°C
G > 1 TA = −40°C to +125°C −100 −100 ppm/°C
INPUT VS = ±1.35 V to +36 V
Input Impedance
Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF
Input Operating Voltage
Range3
TA = +25°C −VS − 0.1 +VS − 0.8 −VS − 0.1 +VS − 0.8 V
T
A = +125°C −VS 0.05 +VS − 0.6 −VS − 0.05 +VS − 0.6 V
T
A = −40°C −VS 0.15 +VS − 0.9 −VS − 0.15 +VS − 0.9 V
Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V
OUTPUT
Output Swing
RL = 2 kΩ to Ground TA = +25°C −VS + 0.4 +VS − 0.7 −VS + 0.4 +VS − 0.7 V
T
A = +125°C −VS + 0.4 +VS − 1.0 −VS + 0.4 +VS − 1.0 V
T
A = −40°C −VS + 1.2 +VS − 1.1 −VS + 1.2 +VS − 1.1 V
RL = 10 kΩ to Ground TA = +25°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V
T
A = +125°C −VS + 0.3 +VS − 0.3 −VS + 0.3 +VS − 0.3 V
T
A = −40°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V
RL = 100 kΩ to Ground TA = −40°C to +125°C −VS + 0.1 +VS − 0.1 −VS + 0.1 +VS − 0.1 V
Short-Circuit Current 13 13 mA
POWER SUPPLY
Operating Range Dual-supply operation ±1.35 ±18 ±1.35 ±18 V
Quiescent Current
(Per Amplifier)
TA = +25°C 350 425 350 425 μA
T
A = −40°C 250 325 250 325 μA
T
A = +85°C 450 525 450 525 μA
T
A = +125°C 525 600 525 600 μA
TEMPERATURE RANGE −40 +125 −40 +125 °C
1 The input stage uses PNP transistors; therefore, input bias current always flows into the part.
2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3 Input voltage range of the AD8426 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the section for more information. Input Voltage Range
AD8426
Rev. 0 | Page 5 of 28
Dynamic Performance Specifications
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.
Table 3. Single-Ended Output Configuration (Both Amplifiers)
Test Conditions/
Comments
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1 1000 1000 kHz
G = 10 160 160 kHz
G = 100 20 20 kHz
G = 1000 2 2 kHz
Settling Time 0.01% 10 V step
G = 1 25 25 μs
G = 10 15 15 μs
G = 100 40 40 μs
G = 1000 750 750 μs
Slew Rate
G = 1 0.4 0.4 V/μs
G = 5 to 100 0.6 0.6 V/μs
Table 4. Differential Output Configuration
Test Conditions/
Comments
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1 850 850 kHz
G = 10 300 300 kHz
G = 100 30 30 kHz
G = 1000 2 2 kHz
Settling Time 0.01% 10 V step
G = 1 25 25 μs
G = 10 15 15 μs
G = 100 80 80 μs
G = 1000 300 300 μs
Slew Rate
G = 1 0.4 0.4 V/μs
G = 5 to 100 0.6 0.6 V/μs
AD8426
Rev. 0 | Page 6 of 28
SINGLE-SUPPLY OPERATION
+VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.
Table 5.
Test Conditions/
Comments
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION
RATIO (CMRR)
VCM = 0 V to 1.7 V
CMRR, DC to 60 Hz
G = 1 80 90 dB
G = 10 100 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
CMRR at 5 kHz
G = 1 80 80 dB
G = 10 90 90 dB
G = 100 90 90 dB
G = 1000 100 100 dB
NOISE Total noise:
eN = √(eNI2 + (eNO/G)2)
Voltage Noise f = 1 kHz
Input Voltage Noise, eNI 24 27 24 27 nV/√Hz
Output Voltage Noise, eNO 120 125 120 125 nV/√Hz
RTI Noise f = 0.1 Hz to 10 Hz
G = 1 2 2 μV p-p
G = 10 0.5 0.5 μV p-p
G = 100 to 1000 0.4 0.4 μV p-p
Current Noise f = 1 kHz 100 100 fA/√Hz
f = 0.1 Hz to 10 Hz 3 3 pA p-p
VOLTAGE OFFSET Total offset voltage:
VOS = VOSI + (VOSO/G)
Input Offset, VOSI 300 150 μV
Average Temperature
Coefficient
TA = −40°C to +125°C 0.5 3 0.5 1.5 μV/°C
Output Offset, VOSO 1000 500 μV
Average Temperature
Coefficient
TA = −40°C to +125°C 2 12 1 8 μV/°C
Offset RTI vs. Supply (PSR) VS = 2.7 V to 36 V
G = 1 80 90 dB
G = 10 100 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
INPUT CURRENT
Input Bias Current1
TA = +25°C 5 20 30 5 20 30 nA
T
A = +125°C 5 15 28 5 15 28 nA
T
A = −40°C 5 30 38 5 30 38 nA
Average Temperature
Coefficient
TA = −40°C to +125°C 70 70 pA/°C
Input Offset Current TA = +25°C 2 1 nA
T
A = +125°C 2 1 nA
T
A = −40°C 3 1 nA
Average Temperature
Coefficient
TA = −40°C to +125°C 5 5 pA/°C
AD8426
Rev. 0 | Page 7 of 28
Test Conditions/
Comments
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit
REFERENCE INPUT
RIN 100 100
IIN 7 7 μA
Voltage Range −VS +VS −VS +VS V
Reference Gain to Output 1 1 V/V
Reference Gain Error 0.01 0.01 %
GAIN G = 1 + (49.4 kΩ/RG)
Gain Range 1 1000 1 1000 V/V
Gain Error
G = 1 VOUT = 0.8 V to 1.8 V 0.05 0.05 %
G = 5 to 1000 VOUT = 0.2 V to 2.5 V 0.3 0.1 %
Gain vs. Temperature2
G = 1 TA = −40°C to +85°C 5 1 ppm/°C
T
A = +85°C to +125°C 5 2 ppm/°C
G > 1 TA = −40°C to +125°C −100 −100 ppm/°C
INPUT −VS = 0 V, +VS = 2.7 V
to 36 V
Input Impedance
Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF
Input Operating Voltage
Range3
TA = +25°C −0.1 +VS − 0.7 −0.1 +VS − 0.7 V
T
A = +125°C −0.05 +VS − 0.6 −0.05 +VS − 0.6 V
T
A = −40°C −0.15 +VS − 0.9 −0.15 +VS − 0.9 V
Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V
OUTPUT
Output Swing
RL = 10 kΩ to 1.35 V TA = −40°C to +125°C 0.1 +VS − 0.1 0.1 +VS − 0.1 V
Short-Circuit Current 13 13 mA
POWER SUPPLY
Operating Range Single-supply operation 2.2 36 2.2 36 V
Quiescent Current
(Per Amplifier)
−VS = 0 V, +VS = 2.7 V
T
A = +25°C 325 400 325 400 μA
T
A = −40°C 250 325 250 325 μA
T
A = +85°C 425 500 425 500 μA
T
A = +125°C 475 550 475 550 μA
TEMPERATURE RANGE −40 +125 −40 +125 °C
1 The input stage uses PNP transistors; therefore, input bias current always flows into the part.
2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3 Input voltage range of the AD8426 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the section for more information. Input Voltage Range
AD8426
Rev. 0 | Page 8 of 28
Dynamic Performance Specifications
+VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 k, specifications referred to input, unless otherwise noted.
Table 6. Single-Ended Output Configuration (Both Amplifiers)
Test Conditions/
Comments
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1 1000 1000 kHz
G = 10 160 160 kHz
G = 100 20 20 kHz
G = 1000 2 2 kHz
Settling Time 0.01% 2 V step
G = 1 6 6 μs
G = 10 6 6 μs
G = 100 35 35 μs
G = 1000 750 750 μs
Slew Rate
G = 1 0.4 0.4 V/μs
G = 5 to 100 0.6 0.6 V/μs
Table 7. Differential Output Configuration
Test Conditions/
Comments
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1 850 850 kHz
G = 10 300 300 kHz
G = 100 30 30 kHz
G = 1000 2 2 kHz
Settling Time 0.01% 2 V step
G = 1 25 25 μs
G = 10 15 15 μs
G = 100 80 80 μs
G = 1000 300 300 μs
Slew Rate
G = 1 0.4 0.4 V/μs
G = 5 to 100 0.6 0.6 V/μs
AD8426
Rev. 0 | Page 9 of 28
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
Parameter Rating
Supply Voltage ±18 V
Output Short-Circuit Current Indefinite
Maximum Voltage at −INx or +INx −VS + 40 V
Minimum Voltage at −INx or +INx +VS − 40 V
REFx Voltage ±VS
Storage Temperature Range −65°C to +150°C
Specified Temperature Range −40°C to +125°C
Maximum Junction Temperature 130°C
ESD
Human Body Model 1.5 kV
Charged Device Model 1.5 kV
Machine Model 100 V
The θJA value in Table 9 assumes a 4-layer JEDEC standard
board with zero airflow.
Table 9.
Package θJA Unit
16-Lead LFCSP (CP-16-19) 86 °C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD8426
Rev. 0 | Page 10 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
12
11
10
9
5678
13141516
–IN1
+IN1
RG1
RG1
AD8426
+V
S
OUT1
OUT2
–V
S
–IN2
+IN2
RG2
RG2
09490-002
+V
S
–V
S
REF1
REF2
Figure 2. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN1 Negative Input, In-Amp 1
2 RG1 Gain-Setting Resistor Terminal, In-Amp 1
3 RG1 Gain-Setting Resistor Terminal, In-Amp 1
4 +IN1 Positive Input, In-Amp 1
5 +VS Positive Supply
6 REF1 Reference Adjust, In-Amp 1
7 REF2 Reference Adjust, In-Amp 2
8 −VS Negative Supply
9 +IN2 Positive Input, In-Amp 2
10 RG2 Gain-Setting Resistor Terminal, In-Amp 2
11 RG2 Gain-Setting Resistor Terminal, In-Amp 2
12 −IN2 Negative Input, In-Amp 2
13 −VS Negative Supply
14 OUT2 Output, In-Amp 2
15 OUT1 Output, In-Amp 1
16 +VS Positive Supply
AD8426
Rev. 0 | Page 11 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.
60
0
10
20
30
40
50
–100 100500–50
HITS
CMRR (µV/V)
IN-AMP 1
IN-AMP 2
09490-303
Figure 3. Typical Distribution for CMRR (G = 1)
0
10
20
30
40
50
–100 100500–50
HITS
V
OSI
(µV)
IN-AMP 1
IN-AMP 2
09490-304
Figure 4. Typical Distribution of Input Offset Voltage
0
10
20
30
40
60
50
–600 600200 4000–200–400
HITS
IN-AMP 1
IN-AMP 2
09490-305
V
OSO
(µV)
Figure 5. Typical Distribution of Output Offset Voltage
0
10
20
30
40
–21 –20 –19 –18 –17
HITS
I
BIAS
(nA)
IN-AMP 1
IN-AMP 2
09490-306
Figure 6. Typical Distribution of Input Bias Current, Inverting Input
0
10
20
30
40
50
–21 –20 –19 –18 –17
HITS
I
BIAS
(nA)
IN-AMP 1
IN-AMP 2
09490-307
Figure 7. Typical Distribution of Input Bias Current, Noninverting Input
0
10
20
30
50
70
40
60
–0.010 –0.005 0 0.005 0.010
HITS
GAIN ERROR (%)
IN-AMP 1
IN-AMP 2
09490-308
Figure 8. Typical Distribution of Gain Error (G = 1)
AD8426
Rev. 0 | Page 12 of 28
+0.01V, +1.90V
0.00V, –0. 45V
+2.17V, +0.90V
+1.35V, +1.95V
+0.01V, +1.28V
+0.01V, +0.31V
+1.35V, –0.41V
+2.61V, +0.37V
+2.61V, +1.13V
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0
INPUT COMMON-MODE VOLTAGE (V)
OUT P UT VOLTAGE ( V )
V
REF
= 0V
V
REF
= +1.35V
09490-103
Figure 9. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = 2.7 V, G = 1
+0.02V, +4.25V
+0.01V, –0. 30V
+4.64V, +2.03V
+2.50V, +4.25V
+0.02V, +2.95V
+0.01V, +0.87V
+2.50V, –0. 40V
+4.90V, +0.82V
+4.90V, +3.03V
–1
0
1
2
3
4
5
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 6.05.55.0
INPUT COM M O N-MO DE VOLTAGE (V)
OUTPUT VOLTAGE (V)
V
REF
= 0V
V
REF
= +2.5V
09490-104
Figure 10. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = 5 V, G = 1
0V, +4.25V
–4.93V, + 1. 77V
–4.93V, –2. 83V
0V, –5.30V
+4.90V, –2.84V
+4.87V, +1.79V
–6
–4
–2
0
2
4
6
–6 –4 –2 0 2 46
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
09490-105
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±5 V, G = 1
+0.01V, +1.90V
+0.01V, –0. 40V
+2.46V, +0.72V
+1.35V, +1.94V
+0.01V, +1.19V
+0.01V, +0.05V
+1.35V, –0. 55V
+2.61V, +0.08V
+2.60V, + 1. 11V
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0
INPUT COMMON-MODE VOLT AGE (V)
OUTPUT VOLTAGE (V)
V
REF
= 0V
V
REF
= +1.35V
09490-106
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = 2.7 V, G = 100
+0.02V, + 4. 20V
+0.01V, –0. 40V
+4.77V, +1.71V
+2.49V, +4.25V
+0.02V, +2.89V
+0.01V, +0.69V
+2.49V, –0. 30V
+4.90V, +0.54V
+4.90V, +3.02V
–1
0
1
2
3
4
5
–0.5 0 0.5 1.0 2.0 3.0 4.0 5.55.01.52.53.54.5
INPUT COMMON-MODE VOLT AGE (V)
OUTPUT VOLTAGE (V)
V
REF
= 0V
V
REF
= +2.50V
09490-107
Figure 13. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = 5 V, G = 100
0V, +4. 24V
–4.93V, + 1. 74V
–4.93V, –3. 15V
–0.01V, –5. 30V
+4.90V, –3. 18V
+4.90V, +1.76V
–6
–4
–2
0
2
4
6
–6 –4 –2 0 2 4 6
OUT P UT VO LTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
09490-108
Figure 14. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±5 V, G = 100
AD8426
Rev. 0 | Page 13 of 28
20
–20
–15
–10
–5
0
5
10
15
–20 –15 –10 –5 0 5 10 15 20
INPUT COMMON-MODE VOLTAGE (V)
OUTPUT VOLTAGE (V)
0V, –15.3V
0V, –12.3V
+11.8V, –6.5V
+14.8V, –7.9V
+14.8V, +6.8V
+11.9V, +5.3V
0V, +14.2V
0V, +11.2V
–11.9V, +5.2V
–14.9V, +6.7V
–14.9V, –7.6V
–11.9V, –6.0V
V
S
= ±15V
V
S
= ±12V
09490-109
Figure 15. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±15 V and VS = ±12 V, G = 1
2.75
–0.25
0.6
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
OUTPUT VOLTAGE (V)
INPUT CURRENT (mA)
INPUT VOLTAGE (V)
V
S
= 2.7V
G = 1
–V
IN
= 0V
V
OUT
I
IN
09490-110
Figure 16. Input Overvoltage Performance,
Single Supply, VS = 2.7 V, G = 1
16
–16
–14
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
12
14
0.6
0.7
0.8
–0.6
–0.7
–0.8
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
OUTPUT VOLTAGE (V)
INPUT CURRENT (mA)
INPUT VOLTAGE (V)
V
S
= ±15V
G = 1
–V
IN
= 0V V
OUT
I
IN
09490-111
Figure 17. Input Overvoltage Performance,
Dual Supply, VS = ±15 V, G = 1
20
–20
–15
–10
–5
0
5
10
15
–20 –15 –10 –5 0 5 10 15 20
INPUT COMMON-MODE VOLTAGE (V)
OUTPUT VOLTAGE (V)
–0.01V, –15.3V
–0.01V, –12.3V
+11.8V, –6.63V
+14.8V, –8.18V
+14.8V, +6.64V
+11.8V, +5.25V
0V, +14.1V
0V, +11.2V
–11.9V, +5.22V
–14.9V, +6.61V
–14.9V, –8.09V
–11.9V, –6.71V
V
S
= ±15V
V
S
= ±12V
09490-112
Figure 18. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±15 V and VS = ±12 V, G = 100
2.75
–0.25
0.6
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
OUTPUT VOLTAGE (V)
INPUT CURRENT (mA)
INPUT VOLTAGE (V)
V
S
= 2.7V
G = 100
–V
IN
= 0V
V
OUT
I
IN
09490-113
Figure 19. Input Overvoltage Performance,
Single Supply, VS = 2.7 V, G = 100
16
–16
–14
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
12
14
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
OUTPUT VOLTAGE (V)
INPUT CURRENT (mA)
INPUT VOLTAGE (V)
V
S
= ±15V
G = 100
–V
IN
= 0V
09490-114
0.6
0.7
0.8
–0.6
–0.7
–0.8
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
V
OUT
I
IN
Figure 20. Input Overvoltage Performance,
Dual Supply, VS = ±15 V, G = 100
AD8426
Rev. 0 | Page 14 of 28
30
16
18
20
22
24
26
28
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
INPUT BIAS CURRENT (nA)
COMMON-MODE VOLTAGE (V)
–0.12V
+4.22V
09490-115
Figure 21. Input Bias Current vs. Common-Mode Voltage,
Single Supply, VS = 5 V
160
140
120
100
80
60
40
20
0
0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
POSITIVE PSRR (dB)
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
09490-322
Figure 22. Positive PSRR vs. Frequency, RTI
70
60
50
–30
–20
–10
0
10
20
30
40
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
GAIN (dB)
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
V
S
= ±15V
09490-323
Figure 23. Gain vs. Frequency, Dual Supply, VS = ±15 V
50
–5
0
5
10
15
20
25
30
35
40
45
–16 –12 –8 –4 0 4 8 12 16
INPUT BIAS CURRENT (nA)
COMMON-MODE VOLTAGE (V)
–15.1V
+14.1V
09490-118
Figure 24. Input Bias Current vs. Common-Mode Voltage,
Dual Supply, VS = ±15 V
160
140
120
100
80
60
40
20
0
0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
NE
G
A
TIVE PSRR (dB)
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
09490-325
Figure 25. Negative PSRR vs. Frequency
70
60
50
–20
–10
0
10
20
30
40
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
GAIN (dB)
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
09490-326
Figure 26. Gain vs. Frequency, Single Supply, VS = 2.7 V
AD8426
Rev. 0 | Page 15 of 28
160
140
120
100
80
60
40
20
0
0.1 1 10 100 1k 10k 100k
FREQUENCY (Hz)
CMRR (dB)
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
BANDWIDTH
LIMITED
09490-327
Figure 27. CMRR vs. Frequency, RTI
120
100
80
60
40
20
0
0.1 1 10 100 1k 10k 100k
FREQUENCY (Hz)
CMRR (dB)
GAIN = 1000
GAIN = 1
GAIN = 100
GAIN = 10
BANDWIDTH
LIMITED
09490-328
Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
6
4
2
0
–2
–4
5
3
1
–1
–3
–5
–6
020 40 60 80 10010 30 50 70 90 110 120
WARM-UP TIME (Seconds)
CHANGE IN INPUT OFFSET VOLTAGE (µV)
09490-329
Figure 29. Change in Input Offset Voltage vs. Warm-Up Time
0
30
25
20
15
10
5
–50
250
200
150
100
50
0
–45 –25 –5 15 35 55 75 95 115 135
INPUT BIAS CURRENT (nA)
INPUT OFFSET CURRENT (pA)
TEMPERATURE (°C)
I
OS
±I
B
09490-330
Figure 30. Input Bias Current and Input Offset Current vs. Temperature
40
–80
–60
–40
–20
0
20
–60 –40 –20 0 20 40 60 100 14080 120
GAIN ERROR (µV/V)
TEMPERATURE (°C)
NORMALIZED AT 25°C
09490-125
Figure 31. Gain Error vs. Temperature, G = 1
10
–20
–15
–10
–5
0
5
–60 –40 –20 0 20 40 60 100 14080 120
CMRR (µV/V)
TEMPERATURE (°C)
REPRESENTATIVE DATA
NORMALIZED AT 25°C
09490-126
Figure 32. CMRR vs. Temperature, G = 1
AD8426
Rev. 0 | Page 16 of 28
+
V
S
–0.2
–0.4
–0.6
–0.8
–V
S
–0.2
–0.4
–0.6
–0.8
2 4 6 8 10 12 14 16 18
SUPPLY VOLTAGE (±V
S
)
INPUT VOLTAGE (V)
REFERRED TO SUPPLY VOLTAGES
–40°C +25°C +85°C +105°C +125°C
09490-333
Figure 33. Input Voltage Limit vs. Supply Voltage
+
V
S
–0.1
–0.2
–0.3
–0.4
–V
S
+0.3
+0.2
+0.1
+0.4
2 4 6 8 10 12 14 16 18
SUPPLY VOLTAGE (±V
S
)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–40°C
+25°C
+85°C
+105°C
+125°C
09490-334
Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
+
V
S
–0.8
–1.0
–1.2
–0.2
–0.4
–0.6
–V
S
+0.4
+0.2
+1.0
+0.8
+0.6
+1.2
2 4 6 8 10 12 14 16 18
SUPPLY VOLTAGE (±V
S
)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–40°C
+25°C
+85°C
+105°C
+125°C
09490-335
Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ
15
–15
–10
–5
0
5
10
100 1k 100k10k
OUTPUT VOLTAGE SWING (V)
LOAD RESISTANCE ()
–40°C
+25°C
+85°C
+105°C
+125°C
09490-130
Figure 36. Output Voltage Swing vs. Load Resistance
+
V
S
–0.2
–0.4
–0.6
–0.8
+0.8
+0.6
+0.4
+0.2
–V
S
0.01 0.1 101
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
OUTPUT CURRENT (µA)
–40°C
+25°C
+85°C
+105°C
+125°C
09490-131
Figure 37. Output Voltage Swing vs. Output Current, G = 1
OUTPUT VOLTAGE (V)
LINEARITY (10ppm/DIV)
09490-338
Figure 38. Gain Nonlinearity, RL ≥ 10 kΩ, G = 1
AD8426
Rev. 0 | Page 17 of 28
OUTPUT VOLTAGE (V)
LINEARITY (10ppm/DIV)
09490-339
Figure 39. Gain Nonlinearity, RL ≥ 10 kΩ, G = 10
OUTPUT VOLTAGE (V)
LINEARITY (10ppm/DIV)
09490-340
Figure 40. Gain Nonlinearity, RL ≥ 10 kΩ, G = 100
09490-341
OUTPUT VOLTAGE (V)
LINEARITY (100ppm/DIV)
Figure 41. Gain Nonlinearity, RL ≥ 10 kΩ, G = 1000
10
100
1k
1 100k1k 10k10010
NOISE (nV/ Hz)
FREQUENCY (Hz)
GAIN = 1000
GAIN = 100 GAIN = 10
GAIN = 1
09490-342
Figure 42. Voltage Noise Spectral Density vs. Frequency
1s/DIV
GAIN = 1000, 200nV/DIV
GAIN = 1, 1µV/DIV
09490-343
Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000
1k
100
10
1 10 100 1k 10k
FREQUENCY (Hz)
NOISE (fA/ Hz)
09490-344
Figure 44. Current Noise Spectral Density vs. Frequency
AD8426
Rev. 0 | Page 18 of 28
1.5pA/DIV 1s/DIV
09490-345
Figure 45. 0.1 Hz to 10 Hz Current Noise
0
3
6
9
12
15
18
21
24
27
30
100 1k 10k 100k 1M
OUTPUT VOLTAGE (V p-p)
FREQUENCY (Hz)
V
S
= ±15V
V
S
= +5V
09490-346
Figure 46. Large Signal Frequency Response
5V/DIV
26µs TO 0.01%
27µs TO 0.001%
0.002%/DIV
50µs/DIV
09490-347
Figure 47. Large Signal Pulse Response and Settling Time,
10 V Step, Dual Supply, VS = ±15 V, G = 1
5V/DIV
17µs TO 0.01%
23µs TO 0.001%
0.002%/DIV
50µs/DIV
09490-348
Figure 48. Large Signal Pulse Response and Settling Time,
10 V Step, Dual Supply, VS = ±15 V, G = 10
5V/DIV
42µs TO 0.01%
60µs TO 0.001%
0.002%/DIV
100µs/DIV
09490-349
Figure 49. Large Signal Pulse Response and Settling Time,
10 V Step, Dual Supply, VS = ±15 V, G = 100
5V/DIV
580µs TO 0.01%
780µs TO 0.001%
0.002%/DIV
500µs/DIV
09490-350
Figure 50. Large Signal Pulse Response and Settling Time,
10 V Step, Dual Supply, VS = ±15 V, G = 1000
AD8426
Rev. 0 | Page 19 of 28
20mV/DIV 4µs/DIV
09490-145
Figure 51. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 1
20mV/DIV 4µs/DIV
09490-146
Figure 52. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 10
20mV/DIV 20µs/DIV
09490-147
Figure 53. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 100
20mV/DIV 100µs/DIV
09490-148
Figure 54. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 1000
20mV/DIV 4µs/DIV
NO LOAD
47pF
100pF
147pF
09490-149
Figure 55. Small Signal Pulse Response with Various Capacitive Loads,
G = 1, RL = Infinity
60
50
40
30
20
10
0
2468101214161820
STEP SIZE (V)
SETTLING TIME (µs)
SETTLED TO 0.01%
SETTLED TO 0.001%
09490-356
Figure 56. Settling Time vs. Step Size, Dual Supply, VS = ±15 V
AD8426
Rev. 0 | Page 20 of 28
1864
760
740
720
700
680
660
640
620
06124110218
SUPPLY CURRENT (µA)
SUPPLY VOLTAGE (±V
S
)
09490-151
Figure 57. Supply Current vs. Supply Voltage (Both Amplifiers)
0
20
40
60
80
100
120
140
160
180
200
100 1M10k 100k1k
CHANNEL SEPA
R
A
TION (dB)
FREQUENCY (Hz)
GAIN = 1
GAIN = 1000
09490-358
Figure 58. Channel Separation vs. Frequency, RL = 2 kΩ,
Source Channel at G = 1 and G = 1000
–20
–10
0
10
20
30
40
50
60
70
100 1M10k 100k1k
GAIN (dB)
FREQUENCY (Hz)
GAIN = 1
GAIN = 10
GAIN = 100
GAIN = 1000
09490-359
Figure 59. Gain vs. Frequency, Differential Output Configuration
100
90
80
70
60
50
40
30
20
10
0
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
OUTPUT BALANCE (dB)
LIMITED BY
MEASUREMENT
SYSTEM
09490-360
Figure 60. Output Balance vs. Frequency, Differential Output Configuration
AD8426
Rev. 0 | Page 21 of 28
THEORY OF OPERATION
A3
R2
24.7k
R1
24.7k
A1 A2 Q2Q1 –IN
+IN
+V
S
–V
S
R3
50k
R4
50k
R5
50k
R
B
R
B
+V
S
–V
S
V
OUT
REF
NODE 1
NODE 2
R
G
V
BIAS
+
V
S
–V
S
+V
S
–V
S
NODE 4NODE 3
R6
50k
DIFFERENCE
AMPLIFIER STAGEGAIN STAGE
ESD AND
OVERVOLTAGE
PROTECTION
ESD AND
OVERVOLTAGE
PROTECTION
–V
S
0
9490-003
Figure 61. Simplified Schematic
ARCHITECTURE
The AD8426 is based on the classic 3-op-amp topology. This
topology has two stages: a gain stage (preamplifier) to provide
differential amplification, followed by a difference amplifier stage
to remove the common-mode voltage. Figure 61 shows a simplified
schematic of one of the instrumentation amplifiers in the AD8426.
The first stage works as follows. To maintain a constant voltage
across the bias resistor, RB, A1 must keep Node 3 at a constant
diode drop above the positive input voltage. Similarly, A2 keeps
Node 4 at a constant diode drop above the negative input voltage.
Therefore, a replica of the differential input voltage is placed
across the gain setting resistor, RG. The current that flows across
this resistance must also flow through the R1 and R2 resistors,
creating a gained differential signal between the A2 and A1 out-
puts. Note that, in addition to a gained differential signal, the
original common-mode signal, shifted up by a diode drop, is
also still present.
The second stage is a difference amplifier, composed of A3 and
four 50 kΩ resistors. The purpose of this stage is to remove the
common-mode signal from the amplified differential signal.
The transfer function of the AD8426 is
VOUT = G × (VIN+VIN−) + VREF
where:
GR
Gk49.4
1+=
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the
AD8426. The gain can be calculated by referring to Table 11
or by using the following gain equation:
1
k49.4
=G
RG
Table 11. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG Calculated Gain
49.9 kΩ 1.990
12.4 kΩ 4.984
5.49 kΩ 9.998
2.61 kΩ 19.93
1.00 kΩ 50.40
499 Ω 100.0
249 Ω 199.4
100 Ω 495.0
49.9 Ω 991.0
The AD8426 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8426 specifications to determine the total gain accu-
racy of the system. When the gain resistor is not used, gain
error and gain drift are minimal.
AD8426
Rev. 0 | Page 22 of 28
REFERENCE TERMINAL
The output voltage of the AD8426 is developed with respect
to the potential on the reference terminal. This is useful when
the output signal needs to be offset to a precise midsupply level.
For example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8426 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
For the best performance, source impedance to the REF
terminal should be kept below 2 Ω. As shown in Figure 62,
the reference terminal, REF, is at one end of a 50 k resistor.
Additional impedance at the REF terminal adds to this 50 k
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional RREF
can be computed by 2 × (50 k + RREF)/100 k + RREF.
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades the CMRR of
the amplifier.
CORRECT
AD8426
OP1177
+
CORRECT
AD8426
AD8426
+
REF REF
INCORRECT
V
REF
V
REF
V
REF
AD8426
REF
09490-156
Figure 62. Driving the Reference Pin
INPUT VOLTAGE RANGE
The 3-op-amp architecture of the AD8426 applies gain in
the first stage before removing common-mode voltage in the
difference amplifier stage. In addition, the input transistors in
the first stage shift the common-mode voltage up one diode
drop. Therefore, internal nodes between the first and second
stages (Node 1 and Node 2 in Figure 61) experience a combina-
tion of gained signal, common-mode signal, and a diode drop.
This combined signal can be limited by the voltage supplies even
when the individual input and output signals are not limited.
Figure 9 to Figure 15 and Figure 18 show the allowable common-
mode input voltage ranges for various output voltages and
supply voltages.
Equation 1 to Equation 3 can be used to understand the inter-
action of the gain (G), common-mode input voltage (VCM),
differential input voltage (VDIFF), and reference voltage (VREF).
The values for the constants (V−LIMIT, V+LIMIT, and VREF_LIMIT)
at different temperatures are shown in Table 12. These three
equations, along with the input and output voltage range speci-
fications in Table 2 and Table 5 , set the operating boundaries
of the part.
LIMIT
S
DIFF
CM VV
GV
V
+>
×
2 (1)
LIMIT
S
DIFF
CM VV
GV
V+
+<
×
+2 (2)
REF_LIMIT
S
REF
CM
DIFF
VV
VV
GV
+<
++
×
2
2 (3)
Table 12. Input Voltage Range Constants for Various
Temperatures
Temperature V−LIMIT (V) V+LIMIT (V) VREF_LIMIT (V)
−40°C −0.55 +0.8 +1.3
+25°C −0.35 +0.7 +1.15
+85°C −0.15 +0.65 +1.05
+125°C −0.05 +0.6 +0.9
The common-mode input voltage range shifts upward with temp-
erature. At cold temperatures, the part requires extra headroom
from the positive supply, whereas operation near the negative
supply has more margin. Conversely, at hot temperatures, the part
requires less headroom from the positive supply but is subject
to the worst-case conditions for input voltages near the negative
supply.
A typical part functions up to the boundaries described in this
section. However, for best performance, designing with a few
hundred millivolts of extra margin is recommended. As signals
approach the boundary, internal transistors begin to saturate,
which can affect frequency and linearity performance.
AD8426
Rev. 0 | Page 23 of 28
LAYOUT
To ensure optimum performance of the AD8426 at the PCB
level, care must be taken in the design of the board layout.
The AD8426 pins are arranged in a logical manner to aid in
this task.
1
2
3
4
12
11
10
9
5678
13141516
–IN1
+IN1
RG1
RG1
AD8426
+V
S
OUT1
OUT2
–V
S
–IN2
+IN2
RG2
RG2
+V
S
–V
S
REF1
REF2
09490-002
Figure 63. Pinout Diagram
Package Considerations
The AD8426 is available in a 16-lead, 4 mm × 4 mm LFCSP with
no exposed paddle. The footprint from another 4 mm × 4 mm
LFCSP part should not be copied because it may not have the
correct lead pitch and lead width dimensions. Refer to the
Outline Dimensions section to verify that the corresponding
dimensional symbol has the correct dimensions.
Hidden Paddle Package
The AD8426 is available in an LFCSP package with a hidden
paddle. Unlike chip scale packages where the pad limits routing
capability, this package allows routes and vias directly beneath
the chip. In this way, the full space savings of the small LFCSP
can be realized. Although the package has no metal in the center
of the part, the manufacturing process leaves a very small section
of exposed metal at each of the package corners, as shown in
Figure 64 and in Figure 73 in the Outline Dimensions section.
This metal is connected to −VS through the part. Because of the
possibility of a short, vias should not be placed beneath these
exposed metal tabs.
09490-158
HIDDEN
PADDLE
EXPOSED METAL
TABS
BOTTOM VIEW
NOTES
1. EXPOSED METAL TABS AT THE FOUR
CORNERS OF THE PACKAGE ARE
INTERNALLY CONNECTED TO –V
S
.
Figure 64. Hidden Paddle Package, Bottom View
Common-Mode Rejection Ratio over Frequency
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp. Such
conversions occur when one input path has a frequency response
that is different from the other. To keep CMRR over frequency
high, the input source impedance and capacitance of each path
should be closely matched. Additional source resistance in the
input paths (for example, for input protection) should be placed
close to the in-amp inputs to minimize the interaction of the
inputs with parasitic capacitance from the PCB traces.
Parasitic capacitance at the gain setting pins can also affect CMRR
over frequency. If the board design has a component at the gain
setting pins (for example, a switch or jumper), the component
should be chosen so that the parasitic capacitance is as small as
possible.
Power Supplies
A stable dc voltage should be used to power the instrumenta-
tion amplifier. Noise on the supply pins can adversely affect
performance. See the PSRR performance curves in Figure 22
and Figure 25 for more information.
A 0.1 µF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 65, a 10 µF capacitor can be used
farther away from the part. In most cases, it can be shared by
other precision integrated circuits.
AD8426
+
V
S
+IN
–IN
LOAD
REF
0.1µF 10µF
0.1µF 10µF
–V
S
OUT
09490-006
R
G
Figure 65. Supply Decoupling, REF, and Output Referred to Local Ground
References
The output voltage of the AD8426 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie the REFx pins to the appropriate local ground. This should
also help minimize crosstalk between the two channels.
AD8426
Rev. 0 | Page 24 of 28
INPUT BIAS CURRENT RETURN PATH The other AD8426 terminals should be kept within the supplies.
All terminals of the AD8426 are protected against ESD.
The input bias current of the AD8426 must have a return path
to ground. When the source, such as a thermocouple, cannot
provide a current return path, one should be created, as shown
in Figure 66.
For applications where the AD8426 encounters voltages beyond
the allowed limits, external current limiting resistors and low
leakage diode clamps such as the BAV199L, the FJH1100, or the
SP720 should be used.
THERMOCOUPLE
+V
S
REF
–V
S
AD8426
CAPACITIVELY COUPLED
+V
S
REF
C
C
–V
S
AD8426
TRANSFORMER
+V
S
REF
–V
S
AD8426
INCORREC
T
CAPACITIVELY COUPLED
+V
S
REF
C
R
R
C
–V
S
AD8426
1
f
HIGH-PASS
= 2RC
THERMOCOUPLE
+V
S
REF
–V
S
10M
AD8426
TRANSFORMER
+V
S
REF
–V
S
AD8426
CORRECT
09490-007
RADIO FREQUENCY INTERFERENCE (RFI)
RF interference is often a problem when amplifiers are used in
applications where there are strong RF signals. The precision
circuits in the AD8426 can rectify the RF signals so that they
appear as a dc offset voltage error. To avoid this rectification,
place a low-pass RC filter at the input of the instrumentation
amplifier (see Figure 67). The filter limits both the differential
and common-mode bandwidth, as shown in the following
equations:
)2(π2
1
C
D
DIFF CCR
uencyFilterFreq +
=
C
CM RC
uencyFilterFreq π2
1
=
where CD 10 CC.
R
R
AD8426
+
V
S
+IN
–IN
0.1µF 10µF
10µF
0.1µF
REF
OUT
–VS
RG
CD
10nF
CC
1nF
CC
1nF
4.02k
4.02k
09490-008
Figure 67. RFI Suppression
Figure 66. Creating an Input Bias Current Return Path
CD affects the differential signal, and CC affects the common-
mode signal. Values of R and CC should be chosen to minimize
RFI. Any mismatch between the R × CC at the positive input
and the R × CC at the negative input degrades the CMRR of the
AD8426. By using a value of CD one order of magnitude larger
than CC, the effect of the mismatch is reduced, and performance
is improved.
INPUT PROTECTION
The AD8426 has very robust inputs and typically does not
need additional input protection. Input voltages can be up to
40 V from the opposite supply rail. For example, with a +5 V
positive supply and a −8 V negative supply, the part can safely
withstand voltages from −35 V to +32 V. Unlike some other
instrumentation amplifiers, the part can handle large differen-
tial input voltages even when the part is in high gain. Figure 16,
Figure 17, Figure 19, and Figure 20 show the behavior of the
part under overvoltage conditions.
AD8426
Rev. 0 | Page 25 of 28
APPLICATIONS INFORMATION
PRECISION STRAIN GAGE
The low offset and high CMRR over frequency of the AD8426
make it an excellent candidate for bridge measurements. The
bridge can be connected directly to the inputs of the amplifier
(see Figure 68).
5
V
2.5V
10µF 0.1µF
AD8426
+IN
–IN
R
G
350
350350
350
+
09490-010
Figure 68. Precision Strain Gage
DIFFERENTIAL DRIVE
The differential output configuration of the AD8426 has the
same excellent dc precision specifications as the single-ended
output configuration.
Differential Output Using Both AD8426 Amplifiers
The circuit configuration is shown in Figure 69. The differential
output specifications in Table 2, Table 4, Table 5, and Table 7
refer to this configuration only. The circuit includes an RC filter
that maintains the stability of the loop.
+IN1
–IN1
AD8426
+
AD8426
+
100pF
+INx
V
OUT
V
OUT+
10k
REF2
09490-163
R
G
Figure 69. Differential Circuit Schematic
The differential output voltage is set by the following equation:
VDIFF_OUT = VOUT+VOUT− = G × (VIN+VIN−)
where:
G
R
G Ω
+= k4.49
1
The common-mode output voltage is set by the average of +IN2
and REF2. The transfer function is
VCM_OUT = (VOUT+ + VOUT−)/2 = (V+IN2 + VREF2)/2
A common application sets the common-mode output voltage
to the midscale of a differential ADC. In this case, the ADC
reference voltage is sent to the +IN2 terminal, and ground is
connected to the REF2 terminal. This produces a common-
mode output voltage of half the ADC reference voltage.
2-Channel Differential Output Using a Dual Op Amp
Another differential output topology is shown in Figure 70.
Instead of a second in-amp, one-half of a dual op amp creates
the inverted output. The recommended dual op amps (the
AD8642 and the AD822) are packaged in an MSOP. This
configuration allows the creation of a dual-channel, precision
differential output in-amp with little board area.
Figure 70 shows how to configure the AD8426 for differential
output.
+IN
–IN
REF
AD8426
V
BIAS
R
+
OP AMP
V
OUT+
V
OUT
R
RECOMMENDED OP AMPS: AD8642, AD822.
RECOMMENDED R VALUES: 5kTO 20k.
09490-009
Figure 70. Differential Output Using an Op Amp
The differential output voltage is set by the following equation:
VDIFF_OUT = VOUT+VOUT− = G × (VIN+VIN−)
where:
G
R
G Ω
+= k4.49
1
The common-mode output voltage is set by the following
equation:
VCM_OUT = (VOUT+VOUT−)/2 = VBIAS
The advantage of this circuit is that the dc differential accuracy
depends on the AD8426 and not on the op amp or the resistors.
This circuit takes advantage of the precise control of the AD8426
over its output voltage relative to the reference voltage. Op amp
dc performance and resistor matching do affect the dc common-
mode output accuracy. However, because common-mode errors
are likely to be rejected by the next device in the signal chain, these
errors typically have little effect on overall system accuracy.
For best ac performance, an op amp with gain bandwidth of at
least 2 MHz and a slew rate of at least 1 V/µs is recommended.
Good choices for op amps are the AD8642 and the AD822.
AD8426
Rev. 0 | Page 26 of 28
Tips for Best Differential Output Performance
Keep trace lengths from resistors to the inverting terminal of
the op amp as short as possible. Excessive capacitance at this
node can cause the circuit to be unstable. If capacitance cannot
be avoided, use lower value resistors.
For best linearity and ac performance, a minimum positive supply
voltage (+VS) is required. Table 13 shows the minimum supply
voltage required for optimum performance, where VCM_MAX
indicates the maximum common-mode voltage expected at the
input of the AD8426.
Table 13. Minimum Positive Supply Voltage
Temperature Equation
Less than −10°C +VS > (VCM_MAX + VBIAS)/2 + 1.4 V
−10°C to +25°C +VS > (VCM_MAX + VBIAS)/2 + 1.25 V
More than +25°C +VS > (VCM_MAX + VBIAS)/2 + 1.1 V
DRIVING A CABLE
All cables have a certain capacitance per unit length, which varies
widely with cable type. The capacitive load from the cable may
cause peaking in the output response of the AD8426. To reduce
the peaking, use a resistor between the AD8426 outputs and the
cable (see Figure 71). Because cable capacitance and desired output
response vary widely, this resistor is best determined empirically.
A good starting point is 50 .
AD8426
AD8426
09490-165
DIFFERENTIAL OUTPUT
SINGLE OUTPUT
Figure 71. Driving a Cable
The AD8426 operates at such a relatively low frequency that
transmission line effects are rarely an issue; therefore, the resistor
need not match the characteristic impedance of the cable.
AD8426
Rev. 0 | Page 27 of 28
DRIVING AN ADC Option 2 shows a circuit for driving higher frequency signals.
It uses a precision op amp (AD8616) with relatively high band-
width and output drive. This amplifier can drive a resistor and
capacitor with a much higher time constant and is, therefore,
suited for higher frequency applications.
Figure 72 shows several different methods of driving an ADC.
The ADC in the ADuC7026 microcontroller was chosen for
this example because it has an unbuffered, charge sampling
architecture that is typical of most modern ADCs. This type of
architecture typically requires an RC buffer stage between the
ADC and the amplifier to work correctly.
Option 3 is useful for applications where the AD8426 must
operate from a large voltage supply but drives a single-supply
ADC. In normal operation, the AD8426 output signal stays
within the ADC range, and the AD8616 simply buffers the signal.
However, in a fault condition, the output of the AD8426 may
go outside the supply range of both the AD8616 and the ADC.
This is not a problem in this circuit, because the 10 k resistor
between the two amplifiers limits the current into the AD8616
to a safe level.
Option 1 shows the minimum configuration required to drive
a charge sampling ADC. The capacitor provides charge to the
ADC sampling capacitor, and the resistor shields the AD8426
from the capacitance. To keep the AD8426 stable, the RC time
constant of the resistor and capacitor needs to stay above 5 µs.
This circuit is mainly useful for lower frequency signals.
AD8426
REF 100nF
100
10k
10
10nF
ADC0
ADC1
ADC2
AGND
3.3V 3.3V
3.3V
OPTION 1: DRIVING LOW FREQUENCY SIGNALS
OPTION 2: DRIVING HIGH FREQUENCY SIGNALS
OPTION 3: PROTECTING ADC FROM LARGE VOLTAGES
3.3V
AD8426
AD8616
ADuC7026
REF
3.3V
10
10nF
AD8426
AD8616
REF
+15V
–15V
AVDD
09490-065
Figure 72. Driving an ADC
AD8426
Rev. 0 | Page 28 of 28
OUTLINE DIMENSIONS
COMPLIANT
TO
JEDEC STANDARDS MO-263-VBBC
062309-B
3.75
BCS SQ
4.00
BSC SQ
0.65
BSC
0.75
0.60
0.50
TOP VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
COPLANARITY
0.08
1.00
0.85
0.80
0.35
0.30
0.25
0.05 MAX
0.02 NOM
0.20 REF
BOTTOM VIEW
0.60 M
A
X
0.60 MAX
1.95 REF
SQ
1
16
5
8
9
12
13
4
Figure 73. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad, with Hidden Paddle
(CP-16-19)
Dimensions shown in millimeters
ORDERING GUIDE
Model1Temperature Range Package Description Package Option
AD8426ACPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19
AD8426ACPZ-WP −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19
AD8426BCPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19
AD8426BCPZ-WP −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19
1 Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09490-0-7/11(0)