© Semiconductor Components Industries, LLC, 2008
December, 2019 − Rev. 2
1Publication Order Number:
FQB12P20/D
MOSFET – P-Channel, QFET)
-200 V, -11.5 A, 470 mW
FQB12P20
General Description
These P−Channel enhancement mode power field effect transistors
are produced using ON Semiconductor’s proprietary, planar stripe,
DMOS technology.
This advanced technology has been especially tailored to minimize
on−state resistance, provide superior switching performance, and
withstand high energy pulse in the avalanche and commutation mode.
These devices are well suited for high efficiency switching DC/DC
converters.
Features
•−11.5 A, −200 V, RDS(on) = 0.47 @ VGS = −10 V
•Low Gate Charge (Typical 31 nC)
•Low Crss (typical 30 pF)
•Fast Switching
•100% Avalanche Tested
•Improved dv/dt Capability
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol Parameter FQB12P20 Unit
VDSS Drain−Source Voltage −200 V
ID Drain Current − Continuous (TC = 25°C)
− Continuous (TC = 100°C)
−11.5 A
−7.27 A
IDM Drain Current − Pulsed (Note 1) −46 A
VGSS Gate−Source Voltage +30 V
EAS Single Pulsed Avalanche Energy (Note 2) 810 mJ
IAR Avalanche Current (Note 1) −11.5 A
EAR Repetitive Avalanche Energy (Note 1) 12 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) −5.5 V/ns
PD Power Dissipation (TA = 25°C) * 3.13 W
Power Dissipation (TC = 25°C)
− Derate above 25°C
120 W
0.96 W/°C
TJ, TSTG Operating and Storage Temperature
Range
−55 to +150 °C
TL Maximum lead temperature for soldering
purposes, 1/8” from case for 5 seconds
300 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
*When mounted on the minimum pad size recommended (PCB Mount)
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 9.2 mH, IAS = −11.5 A, VDD = −50 V, RG = 25 , Starting TJ = 25°C
3. ISD ≤ −11.5 A, di/dt ≤ 300 A/s, VDD ≤ BVDSS, Starting TJ = 25°C
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D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
MARKING DIAGRAM
See detailed ordering and shipping information on page 6 of
this data sheet.
ORDERING INFORMATION
FQB12P20 = Specific Device Code
$Y = ON Semiconductor Logo
&Z = Assembly Plant Code
&3 = Digit Date Code
&K = Lot Run Traceability Code
$Y&Z&3&K
FQB
12P20
VDSS RDS(ON) MAX ID MAX
−200 V 0.47 @ −10 V −11.5 A
P−CHANNEL MOSFET
D
S
G
FQB12P20
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2
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol Parameter Typ Max Unit
RJC Thermal Resistance, Junction−to−Case −1.04 °C/W
RJA Thermal Resistance, Junction−to−Ambient * −40 °C/W
RJA Thermal Resistance, Junction−to−Ambient −62.5 °C/W
*When mounted on the minimum pad size recommended (PCB Mount)
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise specified)
Symbol Parameter Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
BVDSS Drain−Source Breakdown Voltage VGS = 0 V, ID = −250 A−200 − − V
BVDSS / TJ Breakdown Voltage Temperature Coefficient ID = −250 A, Referenced to 25°C− − − V/°C
IDSS Zero Gate Voltage Drain Current VDS = −200 V, VGS = 0 V − − −1A
VDS = −160 V, TC = 125°C− − −10 A
IGSSF Gate−Body Leakage Current, Forward VGS = −30 V, VDS = 0 V − − −100 nA
IGSSR Gate−Body Leakage Current, Reverse VGS = 30 V, VDS = 0 V − − 100 nA
ON CHARACTERISTICS
VGS(th) Gate Threshold Voltage VDS = VGS, ID = −250 A−3.0 − −5.0 V
RDS(on) Static Drain−Source On−Resistance VGS = −10 V, ID = −5.75 A −0.36 0.47
gFS Forward Transconductance VDS = −40 V, ID = −5.75 A (Note 4) −6.4 −S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VDS = −25 V, VGS = 0 V, f = 1.0 MHz −920 1200 pF
Coss Output Capacitance −190 250 pF
Crss Reverse Transfer Capacitance −30 40 pF
SWITCHING CHARACTERISTICS
td(on) Turn−On Delay Time VDD = −100 V, ID = −11.5 A,
RG = 25
(Note 4, 5)
−20 50 ns
tr Turn−On Rise Time −195 400 ns
td(off) Turn−Off Delay Time −40 90 ns
tf Turn−Off Fall Time −60 130 ns
Qg Total Gate Charge VDS = −160 V, ID = −11.5 A,
VGS = −10 V
(Note 4, 5)
−31 40 nC
Qgs Gate−Source Charge −8.1 −nC
Qgd Gate−Drain Charge −16 −nC
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUMUM RATINGS
IS Maximum Continuous Drain−Source Diode Forward Current − − −11.5 A
ISM Maximum Pulsed Drain−Source Diode Forward Current − − −46 A
VSD Drain−Source Diode Forward Voltage VGS = 0 V, IS = −11.5 A − − −5.0 V
trr Reverse Recovery Time VGS = 0 V, IS = −11.5 A,
dIF / dt = 100 A/s (Note 4)
−180 −ns
Qrr Reverse Recovery Charge −1.44 −C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: Pulse width ≤ 300 s, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
FQB12P20
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TYPICAL CHARACTERISTICS
Figure 1. On Characteristics Figure 2. Transfer Characteristics
−VDS, Drain−Source Voltage (V)
Figure 3. On−Resistance Variation vs. Drain Current
and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and Temperature
−ID, Drain Current (A) −VSD, Source−Drain Voltage (V)
Figure 5. Capacitance Characteristics
−VDS, Drain−Source Voltage (V) QG, Total Gate Charge (nC)
−ID, Drain Current (A)
−IDR, Reverse Drain Current (A)
Capacitance (pF)
−VGS, Gate−Source Voltage (V)
RDS(on), Drain−Source On−Resistance ()
−VGS, Gate−Source Voltage (V)
−ID, Drain Current (A)
Figure 6. Gate Charge Characteristics
0
2
4
6
8
10
12
0
400
800
1200
1600
2000
2400
0 10203040
0.0
0.5
1.0
1.5
2.0
2
VGS
Top: −15.0 V
−10.0 V
−8.0 V
−7.0 V
−6.5 V
−6.0 V
Bottom: −5.5 V
10−1100101
10−1
100
101
Notes:
1. 250 s Pulse Test
2. TC = 25°C
46810
10−1
100
101
150°C
Note: TJ = 25°C
VGS = − 10 V
VGS = − 20 V
10−1
100
101
10−1
100
101
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Notes:
1. VDS = −40 V
2. 250 s Pulse Test
Notes:
1. VGS = 0 V
2. 250 s Pulse Test
150°C 25°C
10−1100101
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
−55°C
Ciss
Coss
Crss
0 5 10 15 20 25 30 35
25°C
VDS = −40 V
VDS = −100 V
VDS = −160 V
Note: ID = 11.5 A
FQB12P20
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4
TYPICAL CHARACTERISTICS (continued)
Operation in This Area
is Limited by RDS(on)
Figure 7. Breakdown Voltage Variation vs.
Temperature
Figure 8. On−Resistance Variation vs.
Temperature
TJ, Junction Temperature (°C)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs.
Case Temperature
−VDS, Drain−Source Voltage (V) TC, Case Temperature (°C)
Figure 11. Capacitance Characteristics
t1, Square Wave Pulse Duration (s)
−BVDSS, (Normalized)
Drain−Source Breakdown Voltage
−ID, Drain Current (A)
ZJC (t), Thermal Response
ID, Drain Current (A)
TJ, Junction Temperature (°C)
RDS(on), (Normalized) Drain−Source
On−Resistance ()
single pulse
D = 0.5
0.02
0.2
0.05
0.1
0.01
25 50 75 100 125 150
0
2
4
6
8
10
12
0.0
0.5
1.0
1.5
2.0
2.5
0.8
0.9
1.0
1.1
1.2
−100 −50 0 50 100 150 200
Notes:
1. VGS = 0 V
2. ID = 250 A
−100 −50 0 50 100 150 200
Notes:
1. VGS = −10 V
2. ID = −5.75 A
Notes:
1. TC = 25°C
2. TJ = 150°C
3. Single Pulse
100 s
1 ms
10 ms
DC
100101102
10−1
100
101
102
t1
PDM
t2
Notes:
1. ZJC (t) = 1.04°C/W Max.
2. Duty Factor, D = t1 / t2
3. TJM − TC = PDM * ZJC (t)
10−510−410−3
10−2
10−1
100
100101
10−1
10−2
FQB12P20
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5
Charge
VGS
−10 V
Qg
Qgs Qgd
−3 mA
VGS
DUT
VDS
12 V
Same Type
as DUT
300 nF
200 nF
VDS
VGS 10%
90%
d(on) tr
ton toff
td(off) tf
VDD
−10 V
VDS
RL
DUT
R
G
V
GS
t
VDD
VDS
BVDSS
tp
VDD
IAS
VDS (t)
ID(t)
Time
−10 V DUT
RG
L
ID
tp
L
I
50 k
EAS +
1
2LI2
AS
BVDSS
BVDSS *VDD
Figure 12. Gate Charge Test Circuit & Waveform
Figure 13. Resistive Switching Test Circuit & Waveforms
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
FQB12P20
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6
DUT
VDS
+
_
Driver
R
GCompliment of DUT
(N−Channel)
VGS Sdv/dt controlled by RG
SISD controlled by pulse period
VDD
L
ISD
10 V
VGS
(Driver)
ISD
(DUT)
VDS
(DUT)
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pulse Period
Driver
RCompliment of DUT
(N−Channel)
L
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
PACKAGE MARKING AND ORDERING INFORMATION
Device Marking Package Reel Size Tape Width Shipping
†
FQB12P20TM FQB12P20 D
2
PAK
(Pb−Free)
330 mm 24 mm 800 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
QFET is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
D
2
PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
ISSUE F
DATE 11 MAR 2021
SCALE 1:1
XX
XXXXXXXXX
AWLYWWG
GENERIC MARKING DIAGRAMS*
XXXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
W = Week Code (SSG)
M = Month Code (SSG)
G = Pb−Free Package
AKA = Polarity Indicator
IC Standard
XXXXXXXXG
AYWW
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Rectifier
AYWW
XXXXXXXXG
AKA
SSG
XXXXXX
XXYMW
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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