LMP7715MFE/NOPB - Texas Instruments

LMP7715, LMP7716, LMP7716Q

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SNOSAV0E –MARCH 2006–REVISED MARCH 2013

Single and Dual Precision, 17 MHz, Low Noise, CMOS Input Amplifiers

Check for Samples: LMP7715,LMP7716,LMP7716Q

1FEATURES DESCRIPTION

The LMP7715/LMP7716/LMP7716Q are single and

23• Unless Otherwise Noted, dual low noise, low offset, CMOS input, rail-to-rail

Typical Values at VS= 5V. output precision amplifiers with high gain bandwidth

– Input Offset Voltage ±150 μV (Max) products. The LMP7715/LMP7716/LMP7716Q are

– Input Bias Current 100 fA part of the LMP™ precision amplifier family and are

ideal for a variety of instrumentation applications.

– Input Voltage Noise 5.8 nV/√Hz Utilizing a CMOS input stage, the

– Gain Bandwidth Product 17 MHz LMP7715/LMP7716/LMP7716Q achieve an input bias

– Supply Current (LMP7715) 1.15 mA current of 100 fA, an input referred voltage noise of

– Supply Current (LMP7716/LMP7716Q) 1.30 5.8 nV/√Hz, and an input offset voltage of less than

mA ±150 μV. These features make the

LMP7715/LMP7716/LMP7716Q superior choices for

– Supply Voltage Range 1.8V to 5.5V precision applications.

– THD+N @ f = 1 kHz 0.001% Consuming only 1.15 mA of supply current, the

– Operating Temperature Range −40°C to LMP7715 offers a high gain bandwidth product of 17

125°C MHz, enabling accurate amplification at high closed

– Rail-to-rail Output Swing loop gains.

– Space Saving SOT-23 Package (LMP7715) The LMP7715/LMP7716/LMP7716Q have a supply

– 8-Pin VSSOP Package voltage range of 1.8V to 5.5V, which makes these

(LMP7716/LMP7716Q) ideal choices for portable low power applications with

– LMP7716Q is AEC-Q100 Grade 1 Qualified low supply voltage requirements.

and is Manufactured on an Automotive The LMP7715/LMP7716/LMP7716Q are built with

Grade Flow TI’s advanced VIP50 process technology. The

LMP7715 is offered in a 5-pin SOT-23 package and

APPLICATIONS the LMP7716/LMP7716Q is offered in an 8-pin

VSSOP.

• Active Filters and Buffers The LMP7716Q incorporates enhanced

• Sensor Interface Applications manufacturing and support processes for the

• Transimpedance Amplifiers automotive market, including defect detection

• Automotive methodologies. Reliability qualification is compliant

with the requirements and temperature grades

defined in the AEC-Q100 standard.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2LMP is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

-200 -100 0 100 200

PERCENTAGE (%)

OFFSET VOLTAGE (PV)

VS = 5V

VCM = VS/2

UNITS TESTED: 10,000

110 100 10k 100k

FREQUENCY (Hz)

100

VOLTAGE NOISE (nV/

Hz)

VS = 2.5V

VS = 5.5V

LMP7715, LMP7716, LMP7716Q

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

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Typical Performance

Figure 1. Offset Voltage Distribution Figure 2. Input Referred Voltage Noise

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)(2)

Human Body Model 2000V

ESD Tolerance(3) Machine Model 200V

Charge-Device Model 1000V

VIN Differential ±0.3V

Supply Voltage (VS= V+– V−) 6.0V

Voltage on Input/Output Pins V++0.3V, V−−0.3V

Storage Temperature Range −65°C to 150°C

Junction Temperature(4) +150°C

Infrared or Convection (20 sec) 235°C

Soldering Information Wave Soldering Lead Temp. (10 sec) 260°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test

conditions, see the Electrical Characteristics Tables.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of

JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

(4) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is

PD= (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.

Operating Ratings(1)

Temperature Range(2) −40°C to 125°C

0°C ≤TA≤125°C 1.8V to 5.5V

Supply Voltage (VS= V+– V−)−40°C ≤TA≤125°C 2.0V to 5.5V

5-Pin SOT-23 180°C/W

Package Thermal Resistance (θJA(2))8-Pin VSSOP 236°C/W

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test

conditions, see the Electrical Characteristics Tables.

(2) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is

PD= (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

LMP7715, LMP7716, LMP7716Q

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SNOSAV0E –MARCH 2006–REVISED MARCH 2013

2.5V Electrical Characteristics

Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 2.5V, V−= 0V ,VO= VCM = V+/2. Boldface limits apply at

the temperature extremes.

Symbol Parameter Conditions Min(1) Typ(2) Max(1) Units

VOS ±20 ±180

−20°C ≤TA≤85°C ±330

Input Offset Voltage μV

±20 ±180

−40°C ≤TA≤125°C ±430

TC VOS Input Offset Voltage Temperature LMP7715 -1 ±4 μV/°C

Drift(3)(4) LMP7716/LMP7716Q -1.75

IB−40°C ≤TA≤85°C 0.05 1

Input Bias Current VCM = 1.0V(4)(5) pA

−40°C ≤TA≤125°C 0.05 1

100

IOS 0.006 0.5

Input Offset Current VCM = 1V(4) pA

83 100

CMRR Common Mode Rejection Ratio 0V ≤VCM ≤1.4V dB

PSRR 2.0V ≤V+≤5.5V 85 100

V−= 0V, VCM = 0 80

Power Supply Rejection Ratio dB

1.8V ≤V+≤5.5V 85 98

V−= 0V, VCM = 0

CMVR CMRR ≥80 dB −0.3 1.5

Common Mode Voltage Range V

CMRR ≥78 dB –0.3 1.5

AVOL LMP7715, VO= 0.15 to 2.2V 88 98

RL= 2 kΩto V+/2 82

LMP7716/LMP7716Q, VO= 0.15 to 2.2V 84 92

RL= 2 kΩto V+/2 80

Open Loop Voltage Gain dB

LMP7715, VO= 0.15 to 2.2V 92 110

RL= 10 kΩto V+/2 88

LMP7716/ LMP7716Q, VO= 0.15 to 2.2V 90 95

RL= 10 kΩto V+/2 86

VOUT 25 70

RL= 2 kΩto V+/2 77

Output Voltage Swing

High 20 60 mV from

RL= 10 kΩto V+/2 66 either rail

30 70

RL= 2 kΩto V+/2 73

Output Voltage Swing

Low 15 60

RL= 10 kΩto V+/2 62

IOUT Sourcing to V−36 52

VIN = 200 mV (6) 30

Output Current mA

Sinking to V+7.5 15

VIN =−200 mV(6) 5.0

IS0.95 1.30

LMP7715 1.65

Supply Current mA

1.10 1.50

LMP7716/LMP7716Q (per channel) 1.85

SR AV= +1, Rising (10% to 90%) 8.3

Slew Rate V/μs

AV= +1, Falling (90% to 10%) 10.3

(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the

Statistical Quality Control (SQC) method.

(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped

production material.

(3) Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.

(4) This parameter is specified by design and/or characterization and is not tested in production.

(5) Positive current corresponds to current flowing into the device.

(6) The short circuit test is a momentary open loop test.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

LMP7715, LMP7716, LMP7716Q

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

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2.5V Electrical Characteristics (continued)

Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 2.5V, V−= 0V ,VO= VCM = V+/2. Boldface limits apply at

the temperature extremes.

Symbol Parameter Conditions Min(1) Typ(2) Max(1) Units

GBW Gain Bandwidth 14 MHz

enf = 400 Hz 6.8

Input Referred Voltage Noise Density nV/

f = 1 kHz 5.8

inInput Referred Current Noise Density f = 1 kHz 0.01 pA/√Hz

THD+N f = 1 kHz, AV= 1, RL= 100 kΩ0.003

VO= 0.9 VPP

Total Harmonic Distortion + Noise %

f = 1 kHz, AV= 1, RL= 600Ω0.004

VO= 0.9 VPP

5V Electrical Characteristics

Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5V, V−= 0V, VCM = V+/2. Boldface limits apply at the

temperature extremes.

Symbol Parameter Conditions Min(1) Typ(2) Max(1) Units

VOS Input Offset Voltage −20°C ≤TA≤85°C ±10 ±150

±300 μV

−40°C ≤TA≤125°C ±10 ±150

±400

TC VOS Input Offset Voltage Temperature LMP7715 -1 ±4 μV/°C

Drift(3)(4) LMP7716/LMP7716Q -1.75

IB0.1 1

−40°C ≤TA≤85°C 25

Input Bias Current VCM = 2.0V(4)(5) pA

0.1 1

−40°C ≤TA≤125°C 100

IOS 0.01 0.5

Input Offset Current VCM = 2.0V(4) pA

CMRR 85 100

Common Mode Rejection Ratio 0V ≤VCM ≤3.7V dB

PSRR 2.0V ≤V+≤5.5V 85 100

V−= 0V, VCM = 0 80

Power Supply Rejection Ratio dB

1.8V ≤V+≤5.5V 85 98

V−= 0V, VCM = 0

CMVR CMRR ≥80 dB −0.3 4

Common Mode Voltage Range V

CMRR ≥78 dB –0.3 4

AVOL LMP7715, VO= 0.3 to 4.7V 88 107

RL= 2 kΩto V+/2 82

LMP7716/LMP7716Q, VO= 0.3 to 4.7V 84 90

RL= 2 kΩto V+/2 80

Open Loop Voltage Gain dB

LMP7715, VO= 0.3 to 4.7V 92 110

RL= 10 kΩto V+/2 88

LMP7716/LMP7716Q, VO= 0.3 to 4.7V 90 95

RL= 10 kΩto V+/2 86

(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the

Statistical Quality Control (SQC) method.

(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped

production material.

(3) Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.

(4) This parameter is specified by design and/or characterization and is not tested in production.

(5) Positive current corresponds to current flowing into the device.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

+IN B

OUT B

OUT A

-IN A

+IN A

V-

-IN B

V+

OUTPUT

V-

+IN

V+

-IN

LMP7715, LMP7716, LMP7716Q

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SNOSAV0E –MARCH 2006–REVISED MARCH 2013

5V Electrical Characteristics (continued)

Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5V, V−= 0V, VCM = V+/2. Boldface limits apply at the

temperature extremes.

Symbol Parameter Conditions Min(1) Typ(2) Max(1) Units

VOUT 32 70

RL= 2 kΩto V+/2 77

Output Voltage Swing

High 22 60

RL= 10 kΩto V+/2 66 mV from

either rail

RL= 2 kΩto V+/2 42 70

(LMP7715) 73

Output Voltage Swing RL= 2 kΩto V+/2 45 75

Low (LMP7716/LMP7716Q) 78

20 60

RL= 10 kΩto V+/2 62

IOUT Sourcing to V−46 66

VIN = 200 mV(6) 38

Output Current mA

Sinking to V+10.5 23

VIN =−200 mV(6) 6.5

IS1.15 1.40

LMP7715 1.75

Supply Current mA

1.30 1.70

LMP7716/LMP7716Q (per channel) 2.05

SR AV= +1, Rising (10% to 90%) 6.0 9.5

Slew Rate V/μs

AV= +1, Falling (90% to 10%) 7.5 11.5

GBW Gain Bandwidth 17 MHz

enf = 400 Hz 7.0

Input Referred Voltage Noise Density nV/√Hz

f = 1 kHz 5.8

inInput Referred Current Noise Density f = 1 kHz 0.01 pA/√Hz

THD+N f = 1 kHz, AV= 1, RL= 100 kΩ0.001

VO= 4 VPP

Total Harmonic Distortion + Noise %

f = 1 kHz, AV= 1, RL= 600Ω0.004

VO= 4 VPP

(6) The short circuit test is a momentary open loop test.

Connection Diagram

5-Pin SOT-23 8-Pin VSSOP

Figure 3. Top View Figure 4. Top View

Product Folder Links: LMP7715 LMP7716 LMP7716Q

OFFSET VOLTAGE (PV)

-0.3 0 0.3 0.6 0.9 1.2 1.5

VCM (V)

-200

-150

-100

-50

100

150

200

125°C

25°C

-40°C

VS = 1.8V

-0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1

VCM (V)

-200

-150

-100

-50

100

150

200

OFFSET VOLTAGE (PV)

-40°C

25°C

125°C

VS = 2.5V

-200 -100 0 100 200

PERCENTAGE (%)

OFFSET VOLTAGE (PV)

VS = 5V

VCM = VS/2

UNITS TESTED: 10,000

PERCENTAGE (%)

TCVOS (PV/°C)

-3 -2 -1 0

-4

-40°C dTAd125°C

VS = 2.5V, 5V

VCM = VS/2

UNITS TESTED:

10,000

PERCENTAGE (%)

OFFSET VOLTAGE (PV)

-100 0 100 200

-200

VS = 2.5V

VCM = VS/2

UNITS TESTED:10,000

PERCENTAGE (%)

0-4 -3 -2 -1 0 1 2

TCVOS (PV/°C)

25 -40°C dTAd125qC

VS = 2.5V, 5V

VCM = VS/2

UNITS TESTED:

10,000

LMP7715, LMP7716, LMP7716Q

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

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Typical Performance Characteristics

Unless otherwise noted: TA= 25°C, VS= 5V, VCM = VS/2.

Offset Voltage Distribution TCVOS Distribution (LMP7715)

Figure 5. Figure 6.

Offset Voltage Distribution TCVOS Distribution (LMP7716/LMP7716Q)

Figure 7. Figure 8.

Offset Voltage vs. VCM Offset Voltage vs. VCM

Figure 9. Figure 10.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

01 2 3 4

VCM (V)

-3000

-2500

-2000

-1500

-1000

-500

500

1000

INPUT BIAS CURRENT (fA)

VS = 5V

25°C

-40°C

0 1 2 3 4

-50

INPUT BIAS CURRENT (pA)

VCM (V)

-40

-30

-20

-10

125°C

VS = 5V

85°C

-40 -20 0 20 40 60 80 100 120 125

-200

-150

-100

-50

150

OFFSET VOLTAGE (PV)

TEMPERATURE (°C)

100

VS = 2.5V

VS = 5V

LMP7711

LMP7712

10 1k 1M

FREQUENCY (Hz)

120

CMRR (dB)

100k

10k

100

VS = 2.5V

VS = 5V

1.5 2.5 3.5 4.5 5.5 6

-200

-150

-100

-50

200

OFFSET VOLTAGE (PV)

VS (V)

100

150

-40°C

25°C

125°C

25°C

-0.3 0.7 1.7 2.7 3.7 4.7

-200

-150

-100

-50

100

150

200

OFFSET VOLTAGE (PV)

VCM (V)

-40°C

125°C

VS = 5V

LMP7715, LMP7716, LMP7716Q

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SNOSAV0E –MARCH 2006–REVISED MARCH 2013

Typical Performance Characteristics (continued)

Unless otherwise noted: TA= 25°C, VS= 5V, VCM = VS/2.

Offset Voltage vs. VCM Offset Voltage vs. Supply Voltage

Figure 11. Figure 12.

Offset Voltage vs. Temperature CMRR vs. Frequency

Figure 13. Figure 14.

Input Bias Current vs. VCM Input Bias Current vs. VCM

Figure 15. Figure 16.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

1.5 2.5 3.5 4.5 5.5

ISINK (mA)

VS (V)

125°C

25°C

-40°C

0 1 2 3 4 5

ISOURCE (mA)

VOUT (V)

125°C

25°C

1.5 2.5 3.5 4.5 5.5

ISOURCE (mA)

VS (V)

125°C

25°C -40°C

160

1k 100k 100M

FREQUENCY (Hz)

CROSSTALK REJECTION RATIO (dB)

10M

10k

120

100

140

1.5 2.5 3.5 4.5 5.5

0.4

0.8

1.2

1.6

SUPPLY CURRENT (mA)

VS (V)

125°C 25°C

-40°C

1.5 2.5 3.5 4.5 5.5

0.4

0.8

1.2

1.6

SUPPLY CURRENT (mA)

VS (V)

25°C

-40°C

125°C

LMP7715, LMP7716, LMP7716Q

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

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Typical Performance Characteristics (continued)

Unless otherwise noted: TA= 25°C, VS= 5V, VCM = VS/2.

Supply Current vs. Supply Voltage (LMP7715) Supply Current vs. Supply Voltage (LMP7716/LMP7716Q)

Figure 17. Figure 18.

Crosstalk Rejection Ratio (LMP7716/LMP7716Q) Sourcing Current vs. Supply Voltage

Figure 19. Figure 20.

Sinking Current vs. Supply Voltage Sourcing Current vs. Output Voltage

Figure 21. Figure 22.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

1.5 2.5 3.5 4.5 5.5

VOUT FROM RAIL (mV)

VS (V)

-40°C

25°C

125°C

RL = 2 k:

1.5 2.5 3.5 4.5 5.5

120

150

VOUT FROM RAIL (mV)

VS (V)

125°C

25°C

-40°C

RL = 600:

1.5 2.5 3.5 4.5 5.5

VOUT FROM RAIL (mV)

VS (V)

125°C

25°C

-40°C

RL =10 k:

1.5 2.5 3.5 4.5 5.5

VOUT FROM RAIL (mV)

VS (V)

125°C 25°C

-40°C

RL = 2 k:

0 1 2 3 4 5

ISINK (mA)

VOUT (V)

125°C

25°C

-40°C

1.5 2.5 3.5 4.5 5.5

VOUT FROM RAIL (mV)

VS (V)

125°C 25°C

-40°C

RL = 10 k:

LMP7715, LMP7716, LMP7716Q

www.ti.com

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

Typical Performance Characteristics (continued)

Unless otherwise noted: TA= 25°C, VS= 5V, VCM = VS/2.

Sinking Current vs. Output Voltage Output Swing High vs. Supply Voltage

Figure 23. Figure 24.

Output Swing Low vs. Supply Voltage Output Swing High vs. Supply Voltage

Figure 25. Figure 26.

Output Swing Low vs. Supply Voltage Output Swing High vs. Supply Voltage

Figure 27. Figure 28.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

020 40 60 80 100 120

CAPACITIVE LOAD (pF)

OVERSHOOT AND UNDERSHOOT (%)

UNDERSHOOT%

OVERSHOOT %

PHASE MARGIN (°)

10 100 1000

CAPACITIVE LOAD (pF)

VS = 5V

RL = 10 k:

RL = 600:

RL = 10 M:

-40

-20

100

120

GAIN (dB)

-60

PHASE (°)

-40

-20

100

120

-60

FREQUENCY (Hz)

10k 100k 1M 10M 100M

PHASE

GAIN

RL = 600:10k: 10 M:

PHASE MARGIN (°)

10 100 1000

CAPACITIVE LOAD (pF)

RL = 10 M:

VS = 2.5V

RL = 10 k:

RL = 600:

1.5 2.5 3.5 4.5 5.5

120

150

VOUT FROM RAIL (mV)

VS (V)

125°C 25°C

-40°C

RL = 600:

1k 10k 100k 1M 10M 100M

-40

-20

100

120

GAIN (dB)

FREQUENCY (Hz)

-60

PHASE (°)

-40

-20

100

120

-60

CL = 20 pF

CL = 50 pF

CL = 100 pF

GAIN

CL = 100 pF

CL = 50 pF

CL = 20 pF

PHASE

LMP7715, LMP7716, LMP7716Q

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

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Typical Performance Characteristics (continued)

Unless otherwise noted: TA= 25°C, VS= 5V, VCM = VS/2.

Output Swing Low vs. Supply Voltage Open Loop Frequency Response

Figure 29. Figure 30.

Open Loop Frequency Response Phase Margin vs. Capacitive Load

Figure 31. Figure 32.

Phase Margin vs. Capacitive Load Overshoot and Undershoot vs. Capacitive Load

Figure 33. Figure 34.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

0.01 0.1 1 10

OUTPUT AMPLITUDE (VPP)

-120

-100

-80

-60

-40

-20

THD+N (dB)

VS = 1.8V

f = 1 kHz

AV = +2

RL = 600:

RL = 100 k:

200 mV/DIV

800 ns/DIV

VIN = 1 VPP

f = 200 kHz, AV = +1

VS = 5V, CL = 10 pF

800 ns/DIV

200 mV/DIV

VIN = 1 VPP

f = 200 kHz, AV = +1

VS = 2.5V, CL = 10 pF

10 mV/DIV

200 ns/DIV

VIN = 20 mVPP

f = 1 MHz, AV = +1

VS = 5V, CL = 10 pF

1.5 2.5 3.5 4.5 5.5 6

SLEW RATE (V/Ps)

VS (V)

FALLING EDGE

RISING EDGE

10 mV/DIV

200 ns/DIV

VIN = 20 mVPP

f = 1 MHz, AV = +1

VS = 2.5V, CL = 10 pF

LMP7715, LMP7716, LMP7716Q

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SNOSAV0E –MARCH 2006–REVISED MARCH 2013

Typical Performance Characteristics (continued)

Unless otherwise noted: TA= 25°C, VS= 5V, VCM = VS/2.

Slew Rate vs. Supply Voltage Small Signal Step Response

Figure 35. Figure 36.

Large Signal Step Response Small Signal Step Response

Figure 37. Figure 38.

Large Signal Step Response THD+N vs. Output Voltage

Figure 39. Figure 40.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

110 100 10k 100k

FREQUENCY (Hz)

100

VOLTAGE NOISE (nV/

Hz)

VS = 2.5V

VS = 5.5V

400 nV/DIV

1 s/DIV

VS = ±2.5V

VCM = 0.0V

120

10 1k 100k 10M

FREQUENCY (Hz)

PSRR (dB)

1M10k

100

VS = 5.5V, -PSRR VS = 1.8V, -PSRR

VS = 5.5V, +PSRR

VS = 1.8V, +PSRR

10 100 1k 10k 100k

FREQUENCY (Hz)

0.001

0.002

0.003

0.004

0.005

0.006

THD+N (%)

RL = 600:

RL = 100 k:

VS = 5V

VO = 4 VPP

AV = +2

0.01 0.1 1 10

OUTPUT AMPLITUDE (VPP)

-140

-120

-100

-80

-60

-40

-20

THD+N (dB)

VS = 5.5V

f = 1 kHz

AV = +2

RL = 600:

RL = 100 k:

10 100 1k 10k 100k

FREQUENCY (Hz)

0.001

0.002

0.003

0.004

0.005

0.006

THD+N (%)

RL = 600:

RL = 100 k:

VS = 1.8V

VO = 0.9 VPP

AV = +2

LMP7715, LMP7716, LMP7716Q

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

www.ti.com

Typical Performance Characteristics (continued)

Unless otherwise noted: TA= 25°C, VS= 5V, VCM = VS/2.

THD+N vs. Output Voltage THD+N vs. Frequency

Figure 41. Figure 42.

THD+N vs. Frequency PSRR vs. Frequency

Figure 43. Figure 44.

Input Referred Voltage Noise vs. Frequency Time Domain Voltage Noise

Figure 45. Figure 46.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

10 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

0.01

0.1

100

OUTPUT IMPEDANCE (:)

100

100 10k 10M

FREQUENCY (Hz)

-5

-1

GAIN (dB)

100 k

-3

-2

-4

PHASE

GAIN

VS = 5V

RL = 2 k:

CL = 20 pF

VO = 2 VPP

AV = +1

-45

225

135

-135

180

-90

-180

-225

PHASE (°)

LMP7715, LMP7716, LMP7716Q

www.ti.com

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

Typical Performance Characteristics (continued)

Unless otherwise noted: TA= 25°C, VS= 5V, VCM = VS/2.

Closed Loop Frequency Response Closed Loop Output Impedance vs. Frequency

Figure 47. Figure 48.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

LMP7715, LMP7716, LMP7716Q

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

www.ti.com

APPLICATION INFORMATION

LMP7715/LMP7716/LMP7716Q

The LMP7715/LMP7716/LMP7716Q are single and dual, low noise, low offset, rail-to-rail output precision

amplifiers with a wide gain bandwidth product of 17 MHz and low supply current. The wide bandwidth makes the

LMP7715/LMP7716/LMP7716Q ideal choices for wide-band amplification in portable applications.

The LMP7715/LMP7716/LMP7716Q are superior for sensor applications. The very low input referred voltage

noise of only 5.8 nV/√Hz at 1 kHz and very low input referred current noise of only 10 fA/√Hz mean more signal

fidelity and higher signal-to-noise ratio.

The LMP7715/LMP7716/LMP7716Q have a supply voltage range of 1.8V to 5.5V over a wide temperature range

of 0°C to 125°C. This is optimal for low voltage commercial applications. For applications where the ambient

temperature might be less than 0°C, the LMP7715/LMP7716/LMP7716Q are fully operational at supply voltages

of 2.0V to 5.5V over the temperature range of −40°C to 125°C.

The outputs of the LMP7715/LMP7716/LMP7716Q swing within 25 mV of either rail providing maximum dynamic

range in applications requiring low supply voltage. The input common mode range of the

LMP7715/LMP7716/LMP7716Q extends to 300 mV below ground. This feature enables users to utilize this

device in single supply applications.

The use of a very innovative feedback topology has enhanced the current drive capability of the

LMP7715/LMP7716/LMP7716Q, resulting in sourcing currents of as much as 47 mA with a supply voltage of only

1.8V.

The LMP7715 is offered in the space saving SOT-23 package and the LMP7716/LMP7716Q is offered in an 8-

pin VSSOP. These small packages are ideal solutions for applications requiring minimum PC board footprint.

CAPACITIVE LOAD

The unity gain follower is the most sensitive configuration to capacitive loading. The combination of a capacitive

load placed directly on the output of an amplifier along with the output impedance of the amplifier creates a

phase lag which in turn reduces the phase margin of the amplifier. If phase margin is significantly reduced, the

response will be either underdamped or the amplifier will oscillate.

The LMP7715/LMP7716/LMP7716Q can directly drive capacitive loads of up to 120 pF without oscillating. To

drive heavier capacitive loads, an isolation resistor, RISO as shown in Figure 49, should be used. This resistor

and CLform a pole and hence delay the phase lag or increase the phase margin of the overall system. The

larger the value of RISO, the more stable the output voltage will be. However, larger values of RISO result in

reduced output swing and reduced output current drive.

Figure 49. Isolating Capacitive Load

INPUT CAPACITANCE

CMOS input stages inherently have low input bias current and higher input referred voltage noise. The

LMP7715/LMP7716/LMP7716Q enhance this performance by having the low input bias current of only 50 fA, as

well as, a very low input referred voltage noise of 5.8 nV/√Hz. In order to achieve this a larger input stage has

been used. This larger input stage increases the input capacitance of the LMP7715/LMP7716/LMP7716Q.

Figure 50 shows typical input common mode capacitance of the LMP7715/LMP7716/LMP7716Q.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

+¨

-1

2CIN

P1,2 = 1

R2r1

-4 A0CIN

-R2/R1

1 + s

+s2

CIN R2

VOUT

VIN (s) =

A0 R1

R1 + R2

CIN

VOUT

VIN

VOUT

VIN

AV = - = -

0 1 2 3 4

CCM (pF)

VCM (V)

VS = 5V

LMP7715, LMP7716, LMP7716Q

www.ti.com

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

Figure 50. Input Common Mode Capacitance

This input capacitance will interact with other impedances, such as gain and feedback resistors which are seen

on the inputs of the amplifier, to form a pole. This pole will have little or no effect on the output of the amplifier at

low frequencies and under DC conditions, but will play a bigger role as the frequency increases. At higher

frequencies, the presence of this pole will decrease phase margin and also cause gain peaking. In order to

compensate for the input capacitance, care must be taken in choosing feedback resistors. In addition to being

selective in picking values for the feedback resistor, a capacitor can be added to the feedback path to increase

stability.

The DC gain of the circuit shown in Figure 51 is simply −R2/R1.

Figure 51. Compensating for Input Capacitance

For the time being, ignore CF. The AC gain of the circuit in Figure 51 can be calculated as follows:

(1)

This equation is rearranged to find the location of the two poles:

(2)

As shown in Equation 2, as the values of R1and R2are increased, the magnitude of the poles are reduced,

which in turn decreases the bandwidth of the amplifier. Figure 52 shows the frequency response with different

value resistors for R1and R2. Whenever possible, it is best to chose smaller feedback resistors.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

10k 100k 1M 10M

FREQUENCY (Hz)

-40

-30

-20

-10

GAIN (dB)

CF = 0 pF

CF = 5 pF

CF = 2 pF

R1, R2 = 30 k:

AV = -1

10k 100k 1M 10M 100M

FREQUENCY (Hz)

-25

-20

-15

-10

-5

GAIN (dB)

R1, R2 = 30 k:

AV = -1

R1, R2 = 10 k:

R1, R2 = 1 k:

LMP7715, LMP7716, LMP7716Q

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

www.ti.com

Figure 52. Closed Loop Frequency Response

As mentioned before, adding a capacitor to the feedback path will decrease the peaking. This is because CFwill

form yet another pole in the system and will prevent pairs of poles, or complex conjugates from forming. It is the

presence of pairs of poles that cause the peaking of gain. Figure 53 shows the frequency response of the

schematic presented in Figure 51 with different values of CF. As can be seen, using a small value capacitor

significantly reduces or eliminates the peaking.

Figure 53. Closed Loop Frequency Response

TRANSIMPEDANCE AMPLIFIER

In many applications the signal of interest is a very small amount of current that needs to be detected. Current

that is transmitted through a photodiode is a good example. Barcode scanners, light meters, fiber optic receivers,

and industrial sensors are some typical applications utilizing photodiodes for current detection. This current

needs to be amplified before it can be further processed. This amplification is performed using a current-to-

voltage converter configuration or transimpedance amplifier. The signal of interest is fed to the inverting input of

an op amp with a feedback resistor in the current path. The voltage at the output of this amplifier will be equal to

the negative of the input current times the value of the feedback resistor. Figure 54 shows a transimpedance

amplifier configuration. CDrepresents the photodiode parasitic capacitance and CCM denotes the common-mode

capacitance of the amplifier. The presence of all of these capacitances at higher frequencies might lead to less

stable topologies at higher frequencies. Care must be taken when designing a transimpedance amplifier to

prevent the circuit from oscillating.

With a wide gain bandwidth product, low input bias current and low input voltage and current noise, the

LMP7715/LMP7716/LMP7716Q are ideal for wideband transimpedance applications.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

IF RA < < RF

CFc = ¨

§1 + RB

CF = CIN

GBWP  2 SRF

CCM

IIN

VOUT

IIN - RF

CIN = CD + CCM

LMP7715, LMP7716, LMP7716Q

www.ti.com

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

Figure 54. Transimpedance Amplifier

A feedback capacitance CFis usually added in parallel with RFto maintain circuit stability and to control the

frequency response. To achieve a maximally flat, 2nd order response, RFand CFshould be chosen by using

Equation 3

(3)

Calculating CFfrom Equation 3 can sometimes result in capacitor values which are less than 2 pF. This is

especially the case for high speed applications. In these instances, it is often more practical to use the circuit

shown in Figure 55 in order to allow more sensible choices for CF. The new feedback capacitor, CF′, is (1+

RB/RA) CF. This relationship holds as long as RA<< RF.

Figure 55. Modified Transimpedance Amplifier

SENSOR INTERFACE

The LMP7715/LMP7716/LMP7716Q have low input bias current and low input referred noise, which make them

ideal choices for sensor interfaces such as thermopiles, Infra Red (IR) thermometry, thermocouple amplifiers,

and pH electrode buffers.

Thermopiles generate voltage in response to receiving radiation. These voltages are often only a few microvolts.

As a result, the operational amplifier used for this application needs to have low offset voltage, low input voltage

noise, and low input bias current. Figure 56 shows a thermopile application where the sensor detects radiation

from a distance and generates a voltage that is proportional to the intensity of the radiation. The two resistors, RA

and RB, are selected to provide high gain to amplify this signal, while CFremoves the high frequency noise.

Product Folder Links: LMP7715 LMP7716 LMP7716Q

R1R2

R3R4

10 k:

VIN

VOUT

V+

V-

V+

V-

= 1 +

VOUT

RACF

VIN = KI

IR RADIATION

INTENSITY, I

THERMOPILE

VOUT RA

K(RA + RB)

I =

LMP7715, LMP7716, LMP7716Q

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

www.ti.com

Figure 56. Thermopile Sensor Interface

PRECISION RECTIFIER

Rectifiers are electrical circuits used for converting AC signals to DC signals. Figure 57 shows a full-wave

precision rectifier. Each operational amplifier used in this circuit has a diode on its output. This means for the

diodes to conduct, the output of the amplifier needs to be positive with respect to ground. If VIN is in its positive

half cycle then only the output of the bottom amplifier will be positive. As a result, the diode on the output of the

bottom amplifier will conduct and the signal will show at the output of the circuit. If VIN is in its negative half cycle

then the output of the top amplifier will be positive, resulting in the diode on the output of the top amplifier

conducting and delivering the signal from the amplifier's output to the circuit's output.

For R2/ R1≥2, the resistor values can be found by using the equation shown in Figure 57. If R2/ R1= 1, then R3

should be left open, no resistor needed, and R4should simply be shorted.

Figure 57. Precision Rectifier

Product Folder Links: LMP7715 LMP7716 LMP7716Q

LMP7715, LMP7716, LMP7716Q

www.ti.com

SNOSAV0E –MARCH 2006–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision D (March 2013) to Revision E Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 18

Product Folder Links: LMP7715 LMP7716 LMP7716Q

PACKAGE OPTION ADDENDUM

www.ti.com 25-Feb-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMP7715MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AV3A

LMP7715MFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AV3A

LMP7715MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AV3A

LMP7716MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AX3A

LMP7716MME/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AX3A

LMP7716MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AX3A

LMP7716QMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AR5A

LMP7716QMME/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AR5A

LMP7716QMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AR5A

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

PACKAGE OPTION ADDENDUM

www.ti.com 25-Feb-2015

Addendum-Page 2

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LMP7716, LMP7716-Q1 :

•Catalog: LMP7716

•Automotive: LMP7716-Q1

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMP7715MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMP7715MFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMP7715MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMP7716MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMP7716MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMP7716MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMP7716QMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMP7716QMME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMP7716QMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMP7715MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LMP7715MFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0

LMP7715MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LMP7716MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

LMP7716MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0

LMP7716MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0

LMP7716QMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

LMP7716QMME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0

LMP7716QMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2016

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

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