1/11Septe mber 2001
■MEDIUM SPEED OPERATION :
10 MHz (Typ.) at VDD = 10 V
■FULLY STATIC OPERATION
■STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
■ QUIESCENT CURRENT SPECIFIED UP TO
20V
■5V, 10V AND 15V PARAMETRIC RATINGS
■INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
■100% TE STE D FOR QUIES CE NT CURRENT
■MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRI PTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4017B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4017B is 5-stage Johnson counter
having 10 decoded outputs. Inputs include a
CLOCK, a RESET, and a CLOCK INHIBIT signal.
Schmitt trigger action in the clock input circuit
prov ides pulse shaping that allows unlimited clock
input pulse rise and fall times. This counter is
advanced one count at the positive clock signal
transition if the CLOCK INHIBIT signal is low.
Counter advanced via the clock line is inhibited
when the CLOCK INHIBIT signal is high. A high
RESET si gnal clears the counter to its zero count.
Use of the Johnson de ca de-counter configuration
permits high speed operation, 2-input decimal
decode gating and spike-free decoded outputs.
Anti-lock gating is provided, thus assuring proper
counting sequence. The decoded outputs are
normally low and go high only at their respective
dec oded time slot. Eac h decoded ou tput rema ins
high for one full clock cycle. A CARRY - OUT
signal completes one cycle every 10 clock input
cycles and is used to ripple-clock the succeeding
dev ice in a multi-device counting chain.
HCF4017B
DECADE COUNTER WITH 10 DECODED OUTP UTS
PIN CONNECTIO N
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4017BEY
SOP HCF4017BM1 HCF4017M013TR
DIP SOP
HCF4017B
2/11
INPUT EQUIVALENT CIRCUIT
FUNCTIONAL DI AGRAM
PIN DESCRIPTION
TRUTH TABLE
X : Don’t Care
Q n : No Change
LOGIC DIAGRAM
Th i s l ogic diagram h as not be us ed to est i m ate propaga tion delays
PIN No SYMBOL NAME AND FUNCTION
3, 2, 4, 7, 10,
1, 5, 6, 9, 11 0 to 9 Decoded Decimal Output
14 CLOCK Clock Input
13 CLOCK
INHIBIT Clock Inhibit Input
15 RESET Reset Input
12 CARRY OUT Carry Output
8VSS Negative Supply Voltage
16 VDD Positive Supply Voltage
CLOCK CLOCK
INHIBIT RESET DECODED
OUTPUT
XXHQ
0
LXL Q
n
XHL Q
n
LL
Q
n+1
LLQ
n
HL
Q
n
HL
Q
n+1
HCF4017B
3/11
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied .
All voltage val ues ar e referred to VSS pin vol tage.
RECOMMENDE D OPERATING CONDITIONS
Symbol Parameter Value Unit
VDD Supply Voltage -0.5 to +22 V
VIDC Input Voltage -0.5 to VDD + 0.5 V
IIDC Input Current ± 10 mA
PDPower Dissipation per Package 200 mW
Power Dissipation per Output Transistor 100 mW
Top Operating Temperature -55 to +125 °C
Tstg Storage Temperature -65 to +150 °C
Symbol Parameter Value Unit
VDD Supply Voltage 3 to 20 V
VIInput Voltage 0 to VDD V
Top Operating Temperature -55 to 125 °C
HCF4017B
4/11
DC SPE CIFICATI ONS
Th e Noise Margin fo r bot h " 1" and "0" le vel is: 1V mi n. wit h VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
Symbol Parameter
Test Condition Value
Unit
VI
(V) VO
(V) |IO|
(µA) VDD
(V)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
ILQuiescent Current 0/5 5 0.04 5 150 150
µA
0/10 10 0.04 10 300 300
0/15 15 0.04 20 600 600
0/20 20 0.08 100 3000 3000
VOH High Level Output
Voltage 0/5 <1 5 4.95 4.95 4.95 V0/10 <1 10 9.95 9.95 9.95
0/15 <1 15 14.95 14.95 14.95
VOL Low Level Output
Voltage 5/0 <1 5 0.05 0.05 0.05 V10/0 <1 10 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
VIH High Level Input
Voltage 0.5/4.5 <1 5 3.5 3.5 3.5 V1/9 <1 10 7 7 7
1.5/13.5 <1 15 11 11 11
VIL Low Level Input
Voltage 4.5/0.5 <1 5 1.5 1.5 1.5 V9/1 <1 10 3 3 3
13.5/1.5 <1 15 4 4 4
IOH Output Drive
Current 0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1
mA
0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36
0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9
0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
IOL Output Sink
Current 0/5 0.4 <1 5 0.44 1 0.36 0.36 mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9
0/15 1.5 <1 15 3.0 6.8 2.4 2.4
IIInput Leakage
Current 0/18 Any Input 18 ±10-5 ±0.1 ±1±1µA
CIInput Capacitance Any Input 5 7.5 pF
HCF4017B
5/11
DYNAMIC ELE CTRI CAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
(* ) T ypical temper ature coeffic i ent for all VDD value is 0.3 %/°C.
(1) Measured wi t h resp ect to ca rry out l i ne.
Symbol Parameter Test Cond ition Valu e (*) Unit
VDD (V) Min. Typ. Max.
CLOCKED OPERATION
tPLH tPHL Propagation Delay Time
(decode out) 5 325 650 ns10 135 270
15 85 170
Propagation Delay Time
(carry out) 5 300 600 ns10 125 250
15 80 160
tTHL tTLH Transition Time (carry out
or decoded out lines) 5 100 200 ns10 50 100
15 40 80
fCL (1) Maximum Clock Input
Frequency 5 2.5 5 5 MHz10 5 10
15 5.5 11
tWMinimum Clock Pulse
Width 5 100 200 ns10 45 90
15 30 60
tr , tf Clock Input Rise or Fall
Time 5unlimited µs10
15
tsetup Data Setup Time Minimum
Clock Inhibit 5 115 230 ns10 50 100
15 35 75
RESET OPERATION
tPLH, tPHL Propagation Delay Time
(carry out or decoded out
lines)
5 265 530 ns10 115 230
15 85 170
tWMinimum Reset Pulse
Width 5 130 260 ns10 55 110
15 30 60
tREM Minimum Reset Removal
Time 5 200 400 ns10 140 280
15 75 150
HCF4017B
6/11
TYPICAL APPLICATIONS
DIVIDE BY N COUNTER(N < 10) WITH
DECODED OUTPUTS
When the Nth decoded output is reached (Nth
clock pulse) the S-R fli p-flop (constructed from two
NOR gates of the HCF4001B) generates a reset
pulse which clears the HCF4017B to its zero
count. At this time, if the Nth decoded output is
greater t han or equal to 6, the COUT l ine goes high
to clock the next HCF401 7B counter section. The
"0" decoded output also goes high at this time.
Coincidence of the clock low and decoded "0"
output high resets the S-R flip-flop to enable the
HC F4017B. If the Nth decoded output i s le ss than
6, the COUT line will not go high and, therefore,
cannot be used. In this case "0" decoded output
may be used to perform the clocking function for
the next counter.
TEST CIRCUIT
CL = 50p F or equivalent (i nclud es jig and prob e capaci t ance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
HCF4017B
7/11
WAVE FORM 1 : PROPAGATI ON DELAY TIMES (f=1MHz; 50% duty cycl e )
WAV EFORM 2 : MINIMUM SETUP TIME (CLOCK INHIBIT TO CLOCK) (f =1M Hz; 50% duty cycle)
HCF4017B
8/11
WAVEFORM 3 : PROPAGATION DELAY TIMES, MINIMUM RESET PULSE WIDTH (f=1MHz; 50% duty
cycle)
WAVEFORM 4 : MINIMUM SETUP TIME (CLOCK TO CLOCK INHIBIT) (f=1MHz; 50% duty cycle)
HCF4017B
9/11
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
Plastic DIP-16 (0.25) MECHANICAL DATA
P001C
HCF4017B
10/11
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024
S8° (max.)
SO-16 MECHANICAL DATA
PO13H
HCF4017B
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